<s>
static
void
bounds_check
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
,
const_tree
exp
,
const
char
*
desc
)
{
HOST_WIDE_INT
lane
;
gcc_assert
(
CONST_INT_P
(
operand
)
)
;
lane
=
INTVAL
(
operand
)
;
if
(
lane
<
low
||
lane
>=
high
)
{
if
(
exp
)
error_at
(
EXPR_LOCATION
(
exp
)
,
"%s %wd out of range %wd - %wd"
,
desc
,
lane
,
low
,
high
1
)
;
else
error
(
"%s %wd out of range %wd - %wd"
,
desc
,
lane
,
low
,
high
1
)
;
}
}
</s>

Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) . Raise ERR if it does n't . FIXME : NEON bounds checks occur late in compilation , so reported source locations are bogus .


<s> void expand_fusion_p9_load ( rtx * operands ) { rtx tmp_reg = operands [ 0 ] ; rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == FLOAT_EXTEND || GET_CODE ( orig_mem ) == ZERO_EXTEND ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( extend , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_P9 ) ; set = gen_rtx_SET ( target , new_mem ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , tmp_reg ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ; emit_insn ( insn ) ; return ; } </s>

During the peephole2 pass , adjust and expand the insns for an extended fusion load sequence . The operands are : operands [ 0 ] register set with addis operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] . This is similar to the fusion introduced with power8 , except it scales to both loads/stores and does not require the result register to be the same as the base register . At the moment , we only do this if register set with addis is dead .


<s>
SUnit
*
SystemZPostRASchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
IsTopNode
=
true
;
if
(
Available
.
empty
(
)
)
return
nullptr
;
if
(
Available
.
size
(
)
==
1
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Only one: "
;
HazardRec
->
dumpSU
(
*
Available
.
begin
(
)
,
dbgs
(
)
)
;
dbgs
(
)
<<
"\n"
;
)
;
return
*
Available
.
begin
(
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"** Available: "
;
Available
.
dump
(
*
HazardRec
)
;
)
;
Candidate
Best
;
for
(
auto
*
SU
:
Available
)
{
Candidate
c
(
SU
,
*
HazardRec
)
;
if
(
Best
.
SU
==
nullptr
||
c
<
Best
)
{
Best
=
c
;
LLVM_DEBUG
(
dbgs
(
)
<<
"** Best so far: "
;
)
;
}
else
LLVM_DEBUG
(
dbgs
(
)
<<
"** Tried      : "
;
)
;
LLVM_DEBUG
(
HazardRec
->
dumpSU
(
c
.
SU
,
dbgs
(
)
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
" Height:"
<<
c
.
SU
->
getHeight
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
if
(
!
SU
->
isScheduleHigh
&&
Best
.
noCost
(
)
)
break
;
}
assert
(
Best
.
SU
!=
nullptr
)
;
return
Best
.
SU
;
}
</s>

Pick the next node to schedule , or return NULL .

SystemZ
SystemZ
1
"** Only one: "
"\n"
"** Available: "
"** Best so far: "
"** Tried      : "
" Height:"
"\n"


<s> static bool rs6000_legitimate_combined_insn ( rtx_insn * insn ) { int icode = INSN_CODE ( insn ) ; if ( icode != CODE_FOR_nothing && ( icode == CODE_FOR_bdz_si || icode == CODE_FOR_bdz_di || icode == CODE_FOR_bdnz_si || icode == CODE_FOR_bdnz_di || icode == CODE_FOR_bdztf_si || icode == CODE_FOR_bdztf_di || icode == CODE_FOR_bdnztf_si || icode == CODE_FOR_bdnztf_di ) ) return false ; return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( 2 , Size - 1 ) . getAsInteger ( 10 , RegNo ) ; if ( ! Failed && RegNo >= 0 && RegNo <= 31 ) { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . useCRBits ( ) ) return false ; initialize ( MF ) ; collectCRLogicals ( ) ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; const MachineOperand & DefMO = DefMI -> getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; bool IsRegCR ; if ( TRI -> isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI -> isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; switch ( Directive ) { default : break ; case PPC :: DIR_7400 : case PPC :: DIR_750 : case PPC :: DIR_970 : case PPC :: DIR_E5500 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> static void mips_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( ISA_HAS_MSA ) sizes -> safe_push ( 16 ) ; } </s>


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ"


"LEG DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s>
bool
X86CallLowering
::
splitToValueTypes
(
const
ArgInfo
&
OrigArg
,
SmallVectorImpl
<
ArgInfo
>
&
SplitArgs
,
const
DataLayout
&
DL
,
MachineRegisterInfo
&
MRI
,
SplitArgTy
PerformArgSplit
)
const
{
const
X86TargetLowering
&
TLI
=
*
getTLI
<
X86TargetLowering
>
(
)
;
LLVMContext
&
Context
=
OrigArg
.
Ty
->
getContext
(
)
;
SmallVector
<
EVT
,
4
>
SplitVTs
;
SmallVector
<
uint64_t
,
4
>
Offsets
;
ComputeValueVTs
(
TLI
,
DL
,
OrigArg
.
Ty
,
SplitVTs
,
&
Offsets
,
0
)
;
assert
(
OrigArg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
if
(
OrigArg
.
Ty
->
isVoidTy
(
)
)
return
true
;
EVT
VT
=
SplitVTs
[
0
]
;
unsigned
NumParts
=
TLI
.
getNumRegisters
(
Context
,
VT
)
;
if
(
NumParts
==
1
)
{
SplitArgs
.
emplace_back
(
OrigArg
.
Regs
[
0
]
,
VT
.
getTypeForEVT
(
Context
)
,
OrigArg
.
Flags
,
OrigArg
.
IsFixed
)
;
return
true
;
}
SmallVector
<
Register
,
8
>
SplitRegs
;
EVT
PartVT
=
TLI
.
getRegisterType
(
Context
,
VT
)
;
Type
*
PartTy
=
PartVT
.
getTypeForEVT
(
Context
)
;
for
(
unsigned
i
=
0
;
i
<
NumParts
;
++
i
)
{
ArgInfo
Info
=
ArgInfo
{
MRI
.
createGenericVirtualRegister
(
getLLTForType
(
*
PartTy
,
DL
)
)
,
PartTy
,
OrigArg
.
Flags
}
;
SplitArgs
.
push_back
(
Info
)
;
SplitRegs
.
push_back
(
Info
.
Regs
[
0
]
)
;
}
PerformArgSplit
(
SplitRegs
)
;
return
true
;
}
</s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> static bool moxie_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x , bool strict_p , addr_space_t as ) { gcc_assert ( ADDR_SPACE_GENERIC_P ( as ) ) ; if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && moxie_reg_ok_for_base_p ( XEXP ( x , 0 ) , strict_p ) && CONST_INT_P ( XEXP ( x , 1 ) ) && IN_RANGE ( INTVAL ( XEXP ( x , 1 ) ) , - 32768 , 32767 ) ) return true ; if ( REG_P ( x ) && moxie_reg_ok_for_base_p ( x , strict_p ) ) return true ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == CONST ) return true ; return false ; } </s>

Worker function for TARGET_LEGITIMATE_ADDRESS_P .


<s> static bool aarch64_evpc_ext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; i ++ ) { unsigned int required = location + i ; if ( d -> one_vector_p ) { required &= ( nelt - 1 ) ; } if ( d -> perm [ i ] != required ) return false ; } switch ( d -> vmode ) { case V16QImode : gen = gen_aarch64_extv16qi ; break ; case V8QImode : gen = gen_aarch64_extv8qi ; break ; case V4HImode : gen = gen_aarch64_extv4hi ; break ; case V8HImode : gen = gen_aarch64_extv8hi ; break ; case V2SImode : gen = gen_aarch64_extv2si ; break ; case V4SImode : gen = gen_aarch64_extv4si ; break ; case V2SFmode : gen = gen_aarch64_extv2sf ; break ; case V4SFmode : gen = gen_aarch64_extv4sf ; break ; case V2DImode : gen = gen_aarch64_extv2di ; break ; case V2DFmode : gen = gen_aarch64_extv2df ; break ; default : return false ; } if ( d -> testing_p ) return true ; if ( BYTES_BIG_ENDIAN && ( location != 0 ) ) { std :: swap ( d -> op0 , d -> op1 ) ; location = nelt - location ; } offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> unsigned int rs6000_special_round_type_align ( tree type , int computed , int specified ) { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && TREE_CODE ( field ) != FIELD_DECL ) field = TREE_CHAIN ( field ) ; if ( field == NULL || field == type || DECL_MODE ( field ) != DFmode ) return MAX ( computed , specified ) ; return MAX ( MAX ( computed , specified ) , 64 ) ; } </s>

Darwin , AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"OpenRISC Assembly Printer"
;
}
</s>


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsSubtarget & STI = static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) ; const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( STI . getInstrInfo ( ) ) ; LongBranchSeqSize = ! IsPIC ? 2 : ( ABI . IsN64 ( ) ? 10 : ( ! STI . isTargetNaCl ( ) ? 9 : 10 ) ) ; if ( STI . inMips16Mode ( ) || ! STI . enableLongBranchPass ( ) ) return false ; if ( IsPIC && static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) . IsO32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; int ShVal = STI . inMicroMipsMode ( ) ? 2 : 4 ; int64_t Offset = computeOffset ( I -> Br ) / ShVal ; if ( STI . isTargetNaCl ( ) ) { Offset *= 2 ; } if ( ! ForceLongBranch && isInt < 16 > ( Offset ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( IsPIC ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>


<s> inline tree function_instance :: vector_type ( unsigned int i ) const { return acle_vector_types [ 0 ] [ type_suffix ( i ) . vector_type ] ; } </s>

Return the vector type associated with type suffix I .


<s> static int sparc_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( get_cumulative_args ( cum ) , mode , type , named , false , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { const int size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { const int size = int_size_in_bytes ( type ) ; if ( size > UNITS_PER_WORD && ( slotno == SPARC_INT_ARG_MAX - 1 || slotno == SPARC_FP_ARG_MAX - 1 ) ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT || ( ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || ( type && VECTOR_TYPE_P ( type ) ) ) && ! ( TARGET_FPU && named ) ) ) { const int size = ( type && VECTOR_FLOAT_TYPE_P ( type ) ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_INT_ARG_MAX - 1 ) return UNITS_PER_WORD ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT || ( type && VECTOR_TYPE_P ( type ) ) ) { const int size = ( type && VECTOR_FLOAT_TYPE_P ( type ) ) ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD && slotno == SPARC_FP_ARG_MAX - 1 ) return UNITS_PER_WORD ; } } return 0 ; } </s>

For an arg passed partly in registers and partly in memory , this is the number of bytes of registers used . For args passed entirely in registers or entirely in memory , zero . Any arg that starts in the first 6 regs but wo n't entirely fit in them needs partial registers on v8 . On v9 , structures with integer values in arg slots 5,6 will be passed in % o5 and SP+176 , and complex fp values that begin in the last fp reg [ where `` last fp reg '' varies with the mode ] will be split between that reg and memory .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Delay Slot Fille"
;
}
</s>


"********** ARM MVE VPT Optimisations **********\n"


<s> Value * ARMTargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) return M . getGlobalVariable ( "__security_cookie" ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


<s>
static
void
rs6000_xcoff_file_start
(
void
)
{
rs6000_gen_section_name
(
&
xcoff_bss_section_name
,
main_input_filename
,
".bss_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_data_section_name
,
main_input_filename
,
".rw_"
)
;
rs6000_gen_section_name
(
&
xcoff_read_only_section_name
,
main_input_filename
,
".ro_"
)
;
rs6000_gen_section_name
(
&
xcoff_tls_data_section_name
,
main_input_filename
,
".tls_"
)
;
rs6000_gen_section_name
(
&
xcoff_tbss_section_name
,
main_input_filename
,
".tbss_[UL]"
)
;
fputs
(
"\t.file\t"
,
asm_out_file
)
;
output_quoted_string
(
asm_out_file
,
main_input_filename
)
;
fputc
(
'\n'
,
asm_out_file
)
;
if
(
write_symbols
!=
NO_DEBUG
)
switch_to_section
(
private_data_section
)
;
switch_to_section
(
text_section
)
;
if
(
profile_flag
)
fprintf
(
asm_out_file
,
"\t.extern %s\n"
,
RS6000_MCOUNT
)
;
rs6000_file_start
(
)
;
}
</s>

Output at beginning of assembler file . Initialize the section names for the RS/6000 at this point . Specify filename , including full path , to assembler . We want to go into the TOC section so at least one .toc will be emitted . Also , in order to output proper .bs/.es pairs , we need at least one static [ RW ] section emitted . Finally , declare mcount when profiling to make the assembler happy .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Align , RTLIB :: MEMMOVE ) ; } </s>

Emit target-specific code that performs a memmove .


<s> std :: unique_ptr < TargetInstrInfo :: PipelinerLoopInfo > ARMBaseInstrInfo :: analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const { MachineBasicBlock :: iterator I = LoopBB -> getFirstTerminator ( ) ; MachineBasicBlock * Preheader = * LoopBB -> pred_begin ( ) ; if ( Preheader == LoopBB ) Preheader = * std :: next ( LoopBB -> pred_begin ( ) ) ; if ( I != LoopBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2Bcc ) { MachineInstr * CCSetter = nullptr ; for ( auto & L : LoopBB -> instrs ( ) ) { if ( L . isCall ( ) ) return nullptr ; if ( isCPSRDefined ( L ) ) CCSetter = & L ; } if ( CCSetter ) return std :: make_unique < ARMPipelinerLoopInfo > ( & * I , CCSetter ) ; else return nullptr ; } if ( I != LoopBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2LoopEnd ) { for ( auto & L : LoopBB -> instrs ( ) ) if ( L . isCall ( ) ) return nullptr ; else if ( isVCTP ( & L ) ) return nullptr ; Register LoopDecResult = I -> getOperand ( 0 ) . getReg ( ) ; MachineRegisterInfo & MRI = LoopBB -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * LoopDec = MRI . getUniqueVRegDef ( LoopDecResult ) ; if ( ! LoopDec || LoopDec -> getOpcode ( ) != ARM :: t2LoopDec ) return nullptr ; MachineInstr * LoopStart = nullptr ; for ( auto & J : Preheader -> instrs ( ) ) if ( J . getOpcode ( ) == ARM :: t2DoLoopStart ) LoopStart = & J ; if ( ! LoopStart ) return nullptr ; return std :: make_unique < ARMPipelinerLoopInfo > ( & * I , LoopDec ) ; } return nullptr ; } </s>

Analyze loop L , which must be a single-basic-block loop , and if the conditions can be understood enough produce a PipelinerLoopInfo object .


<s> static rtx ix86_expand_sse_cmp ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx op_true , rtx op_false ) { machine_mode mode = GET_MODE ( dest ) ; machine_mode cmp_ops_mode = GET_MODE ( cmp_op0 ) ; machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == 64 ) { cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , 0 ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || reg_overlap_mentioned_p ( dest , op_true ) || reg_overlap_mentioned_p ( dest , op_false ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode && ! maskcmp ) { x = force_reg ( cmp_ops_mode , x ) ; convert_move ( dest , x , false ) ; } else emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; return dest ; } </s>

Expand an sse vector comparison . Return the register with the result .


<s> rtx extract_nth_access_reg ( rtx_insn * insn , int index ) { switch ( GET_CODE ( PATTERN ( insn ) ) ) { case PARALLEL : return extract_nth_lmsw_access_reg ( insn , index ) ; case SET : return extract_nth_ls2_access_reg ( insn , index ) ; default : gcc_unreachable ( ) ; } } </s>

Returns the register operated by the nth load/store operation in the real micro-operation accessing order .


<s> bool ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return false ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } return false ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s>
virtual
const
char
*
getPassName
(
)
const
LLVM_OVERRIDE
{
return
"X86 AT&T-Style Assembly Printer"
;
}
</s>


<s> void print ( raw_ostream * O ) const { if ( O ) print ( * O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> const PPCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> Reloc :: Model getRelocationModel ( ) const { return RM ; } </s>

Returns the code generation relocation model .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

SystemZ
SystemZ
SystemZAddressingMode::AddrForm
SystemZAddressingMode::DispRange
"Unexpected asm memory constraint"
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp12Only
SystemZAddressingMode::FormBDXNormal
SystemZAddressingMode::Disp12Only
SystemZAddressingMode::FormBD
SystemZAddressingMode::Disp20Only
SystemZAddressingMode::FormBDXNormal
SystemZAddressingMode::Disp20Only


<s> rtx function_expander :: use_pred_x_insn ( insn_code icode ) { gcc_assert ( pred == PRED_x ) ; unsigned int nops = args . length ( ) - 1 ; bool has_float_operand_p = FLOAT_MODE_P ( insn_data [ icode ] . operand [ 0 ] . mode ) ; add_output_operand ( icode ) ; add_input_operand ( icode , args [ 0 ] ) ; for ( unsigned int i = 0 ; i < nops ; ++ i ) { add_input_operand ( icode , args [ i + 1 ] ) ; if ( FLOAT_MODE_P ( GET_MODE ( args [ i + 1 ] ) ) ) has_float_operand_p = true ; } if ( has_float_operand_p ) { rtx pred = m_ops [ 1 ] . value ; if ( flag_trapping_math && pred != CONST1_RTX ( GET_MODE ( pred ) ) ) add_integer_operand ( SVE_STRICT_GP ) ; else add_integer_operand ( SVE_RELAXED_GP ) ; } return generate_insn ( icode ) ; } </s>

Implement the call using instruction ICODE , which is a predicated operation that returns arbitrary values for inactive lanes .


<s> StringRef getType ( ) const { return CurType . Name ; } </s>

Overload to return most specific vector type .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
TargetIRAnalysis
MipsTargetMachine
::
getTargetIRAnalysis
(
)
{
return
TargetIRAnalysis
(
[
this
]
(
Function
&
F
)
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
getDataLayout
(
)
)
;
}
DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
)
;
}
</s>

Get a TargetIRAnalysis appropriate for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s> bool X86TargetLowering :: isTruncateFree ( MVT VT1 , MVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return Subtarget -> is64Bit ( ) || NumBits1 < 64 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
TargetInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
break
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> int pa_shadd_constant_p ( int val ) { if ( val == 2 || val == 4 || val == 8 ) return 1 ; else return 0 ; } </s>

Return 1 if the given constant is 2 , 4 , or 8 . These are the valid constants for shadd instructions .


Expand setmem , as if from a __builtin_memset . Return true if we succeed , otherwise return false .


<s> static bool mips_cfun_call_saved_reg_p ( unsigned int regno ) { if ( global_regs [ regno ] ) return false ; if ( cfun -> machine -> interrupt_handler_p && mips_interrupt_extra_call_saved_reg_p ( regno ) ) return true ; return ( regno == GLOBAL_POINTER_REGNUM ? TARGET_CALL_SAVED_GP : ! call_used_regs [ regno ] ) ; } </s>

Return true if the current function should treat register REGNO as call-saved .


Output the assembly for a call instruction .


<s>
void
LoongArchDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
SDLoc
DL
(
Node
)
;
switch
(
Opcode
)
{
default
:
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static void rs6000_elf_select_rtx_section ( enum machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) toc_section ( ) ; else default_elf_select_rtx_section ( mode , x , align ) ; } </s>

A C statement or statements to switch to the appropriate section for output of RTX in mode MODE . You can assume that RTX is some kind of constant in RTL . The argument MODE is redundant except in the case of a ` const_int ' rtx . Select the section by calling ` text_section ' or one of the alternatives for other sections . Do not define this macro if you put all constants in the read-only data section .


<s> static void rs6000_emit_stack_tie ( rtx fp , bool hard_frame_needed ) { rtvec p ; int i ; rtx regs [ 3 ] ; i = 0 ; regs [ i ++ ] = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ; p = rtvec_alloc ( i ) ; while ( -- i >= 0 ) { rtx mem = gen_frame_mem ( BLKmode , regs [ i ] ) ; RTVEC_ELT ( p , i ) = gen_rtx_SET ( mem , const0_rtx ) ; } emit_insn ( gen_stack_tie ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ) ; } </s>

This ties together stack memory ( MEM with an alias set of rs6000_sr_alias_set ) and the change to the stack pointer .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { bool is64 = getPointerSize ( ) == 8 ; return createPPCELFObjectWriter ( OS , is64 , isLittleEndian ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86TTIImpl :: isLegalMaskedScatter ( Type * DataType ) { return isLegalMaskedGather ( DataType ) ; } </s>

Return true if the target supports masked scatter .


<s> void CSKYAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> bool rs6000_fndecl_pcrel_p ( const_tree fndecl ) { if ( DEFAULT_ABI != ABI_ELFv2 ) return false ; struct cl_target_option * opts = target_opts_for_fn ( fndecl ) ; return ( ( opts -> x_rs6000_isa_flags & OPTION_MASK_PCREL ) != 0 && TARGET_CMODEL == CMODEL_MEDIUM ) ; } </s>

Return whether we should generate PC-relative code for FNDECL .


<s> static bool rs6000_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if TYPE must be passed on the stack and not in registers .


<s> bool PPCCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & DL = F . getParent ( ) -> getDataLayout ( ) ; auto & TLI = * getTLI < PPCTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned I = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ I ] , Arg , I } ; setArgFlags ( OrigArg , I + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ I ; } CCAssignFn * AssignFn = TLI . ccAssignFnForCall ( F . getCallingConv ( ) , false , F . isVarArg ( ) ) ; IncomingValueAssigner ArgAssigner ( AssignFn ) ; FormalArgHandler ArgHandler ( MIRBuilder , MRI ) ; return determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align , const GlobalObject * GO ) const { if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align , GO ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisableInstrFormPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCLoopInstrFormPrepPass ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass ( ) ) ; return false ; } </s>


<s>
bool
mep_mov_ok
(
rtx
*
operands
,
machine_mode
mode
ATTRIBUTE_UNUSED
)
{
int
i
;
fprintf
(
stderr
,
"mep_mov_ok %s %c=%c\n"
,
mode_name
[
mode
]
,
mep_section_tag
(
operands
[
0
]
)
,
mep_section_tag
(
operands
[
1
]
)
)
;
debug_rtx
(
operands
[
0
]
)
;
debug_rtx
(
operands
[
1
]
)
;
if
(
GET_CODE
(
operands
[
1
]
)
==
HIGH
)
return
false
;
if
(
mep_section_tag
(
operands
[
0
]
)
==
'f'
||
mep_section_tag
(
operands
[
1
]
)
==
'f'
)
{
fprintf
(
stderr
,
" - no, f\n"
)
;
return
false
;
}
i
=
mep_section_tag
(
operands
[
1
]
)
;
if
(
(
i
==
'b'
||
i
==
't'
)
&&
!
reload_completed
&&
!
reload_in_progress
)
{
fprintf
(
stderr
,
" - no, bt\n"
)
;
return
false
;
}
for
(
i
=
0
;
i
<
2
;
i
++
)
{
rtx
x
=
operands
[
i
]
;
if
(
GET_CODE
(
x
)
==
SUBREG
)
x
=
XEXP
(
x
,
0
)
;
if
(
GET_CODE
(
x
)
==
REG
&&
!
MEP_CONTROL_REG
(
x
)
)
{
fprintf
(
stderr
,
" - ok\n"
)
;
return
true
;
}
}
fprintf
(
stderr
,
" - no, no gen reg\n"
)
;
return
false
;
}
</s>

Cases where the pattern ca n't be made to use at all .


<s> static inline bool inline_secondary_memory_needed ( enum reg_class class1 , enum reg_class class2 , machine_mode mode , int strict ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class1 ) || MAYBE_FLOAT_CLASS_P ( class2 ) != FLOAT_CLASS_P ( class2 ) || MAYBE_SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class1 ) || MAYBE_SSE_CLASS_P ( class2 ) != SSE_CLASS_P ( class2 ) || MAYBE_MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class1 ) || MAYBE_MMX_CLASS_P ( class2 ) != MMX_CLASS_P ( class2 ) || MAYBE_MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class1 ) || MAYBE_MASK_CLASS_P ( class2 ) != MASK_CLASS_P ( class2 ) ) { gcc_assert ( ! strict || lra_in_progress ) ; return true ; } if ( FLOAT_CLASS_P ( class1 ) != FLOAT_CLASS_P ( class2 ) ) return true ; if ( ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) && ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) ) return true ; if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) return true ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) { if ( ! TARGET_SSE2 ) return true ; if ( ( SSE_CLASS_P ( class1 ) && ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) || ( SSE_CLASS_P ( class2 ) && ! TARGET_INTER_UNIT_MOVES_TO_VEC ) ) return true ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return true ; } return false ; } </s>

If we are copying between general and FP registers , we need a memory location . The same is true for SSE and MMX registers . To optimize register_move_cost performance , allow inline variant . The macro ca n't work reliably when one of the CLASSES is class containing registers from multiple units ( SSE , MMX , integer ) . We avoid this by never combining those units in single alternative in the machine description . Ensure that this constraint holds to avoid unexpected surprises . When STRICT is false , we are being called from REGISTER_MOVE_COST , so do not enforce these sanity checks .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) , nullptr ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv :: X86_FastCall ) ; SecurityCheckCookie -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; return ; } if ( Subtarget . isTargetGlibc ( ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
static
char
*
describe_cache
(
struct
cache_desc
level1
,
struct
cache_desc
level2
)
{
char
size
[
100
]
,
line
[
100
]
,
size2
[
100
]
;
snprintf
(
size
,
sizeof
(
size
)
,
"--param l1-cache-size=%u "
,
level1
.
sizekb
)
;
snprintf
(
line
,
sizeof
(
line
)
,
"--param l1-cache-line-size=%u "
,
level1
.
line
)
;
snprintf
(
size2
,
sizeof
(
size2
)
,
"--param l2-cache-size=%u "
,
level2
.
sizekb
)
;
return
concat
(
size
,
line
,
size2
,
)
;
}
</s>

Returns parameters that describe L1_ASSOC associative cache of size L1_SIZEKB with lines of size L1_LINE , and L2_SIZEKB .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TM = static_cast < const PPCTargetMachine * > ( & MF . getTarget ( ) ) ; TII = TM -> getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void SparcFrameLowering :: emitPrologue ( MachineFunction & MF ) const { SparcMachineFunctionInfo * FuncInfo = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; unsigned SAVEri = SP :: SAVEri ; unsigned SAVErr = SP :: SAVErr ; if ( FuncInfo -> isLeafProc ( ) ) { if ( NumBytes == 0 ) return ; SAVEri = SP :: ADDri ; SAVErr = SP :: ADDrr ; } NumBytes = - MF . getTarget ( ) . getSubtarget < SparcSubtarget > ( ) . getAdjustedFrameSize ( NumBytes ) ; emitSPAdjustment ( MF , MBB , MBBI , NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; unsigned regFP = MRI -> getDwarfRegNum ( SP :: I6 , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = MRI -> getDwarfRegNum ( SP :: I7 , true ) ; unsigned regOutRA = MRI -> getDwarfRegNum ( SP :: O7 , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc Sparc Sparc Sparc Sparc Sparc SP::SAVEri SP::SAVErr 0 SP::ADDri SP::ADDrr Sparc SP SP::I6 SP::I7 SP::O7


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
LivePhysRegs
LiveRegs
(
&
getRegisterInfo
(
)
)
;
LiveRegs
.
addLiveOuts
(
MBB
)
;
SmallVector
<
std
::
pair
<
unsigned
,
const
MachineOperand
*
>
,
8
>
Clobbers
;
LiveRegs
.
stepForward
(
*
MIB
,
Clobbers
)
;
for
(
const
auto
&
C
:
Clobbers
)
{
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
)
;
MIB
.
addReg
(
C
.
first
,
RegState
::
Implicit
|
RegState
::
Define
)
;
}
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


Return an array that contains the direct target flag values and their names .


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p ) { aarch64_add_offset ( Pmode , stack_pointer_rtx , stack_pointer_rtx , - delta , temp1 , temp2 , frame_related_p ) ; } </s>

Subtract DELTA from the stack pointer , marking the instructions frame-related if FRAME_RELATED_P . TEMP1 is available as a temporary if nonnull .


<s> void sh_expand_prologue ( void ) { int save_flags = target_flags ; tree sp_switch_attr = lookup_attribute ( "sp_switch" , DECL_ATTRIBUTES ( current_function_decl ) ) ; current_function_interrupt = sh_cfun_interrupt_handler_p ( ) ; int pretend_args = crtl -> args . pretend_args_size ; if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) && ( NPARM_REGS ( SImode ) > crtl -> args . info . arg_count [ ( int ) SH_ARG_INT ] ) ) pretend_args = 0 ; output_stack_adjust ( - pretend_args , stack_pointer_rtx , 0 , NULL , true ) ; int stack_usage = pretend_args ; if ( cfun -> stdarg ) { if ( TARGET_VARARGS_PRETEND_ARGS ( current_function_decl ) ) { for ( int i = 0 ; i < NPARM_REGS ( SImode ) ; i ++ ) { int rn = NPARM_REGS ( SImode ) + FIRST_PARM_REG - i - 1 ; if ( i >= ( NPARM_REGS ( SImode ) - crtl -> args . info . arg_count [ ( int ) SH_ARG_INT ] ) ) break ; push ( rn ) ; stack_usage += GET_MODE_SIZE ( SImode ) ; } } } if ( sp_switch_attr ) { rtx lab , newsrc ; tree arg = TREE_VALUE ( TREE_VALUE ( sp_switch_attr ) ) ; const char * s = ggc_strdup ( TREE_STRING_POINTER ( arg ) ) ; rtx sp_switch = gen_rtx_SYMBOL_REF ( Pmode , s ) ; lab = add_constant ( sp_switch , SImode , 0 ) ; newsrc = gen_rtx_LABEL_REF ( VOIDmode , lab ) ; emit_insn ( gen_sp_switch_1 ( newsrc ) ) ; } HARD_REG_SET live_regs_mask ; int d = calc_live_regs ( & live_regs_mask ) ; if ( target_flags != save_flags && ! current_function_interrupt ) emit_insn ( gen_toggle_sz ( ) ) ; push_regs ( & live_regs_mask , current_function_interrupt ) ; stack_usage += d ; if ( flag_pic && ! TARGET_FDPIC && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) emit_insn ( gen_GOTaddr2picreg ( const0_rtx ) ) ; if ( target_flags != save_flags && ! current_function_interrupt ) emit_insn ( gen_toggle_sz ( ) ) ; target_flags = save_flags ; output_stack_adjust ( - rounded_frame_size ( d ) , stack_pointer_rtx , 0 , NULL , true ) ; stack_usage += rounded_frame_size ( d ) ; if ( frame_pointer_needed ) emit_frame_insn ( GEN_MOV ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( crtl -> profile || flag_exceptions || flag_unwind_tables ) emit_insn ( gen_blockage ( ) ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = stack_usage ; } </s>


<s>
SDValue
MipsSETargetLowering
::
PerformDAGCombine
(
SDNode
*
N
,
DAGCombinerInfo
&
DCI
)
const
{
SelectionDAG
&
DAG
=
DCI
.
DAG
;
SDValue
Val
;
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ADDE
:
return
performADDECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
AND
:
Val
=
performANDCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
OR
:
Val
=
performORCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SUBE
:
return
performSUBECombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
MUL
:
return
performMULCombine
(
N
,
DAG
,
DCI
,
this
)
;
case
ISD
::
SHL
:
Val
=
performSHLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
break
;
case
ISD
::
SRA
:
return
performSRACombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
SRL
:
return
performSRLCombine
(
N
,
DAG
,
DCI
,
Subtarget
)
;
case
ISD
::
VSELECT
:
return
performVSELECTCombine
(
N
,
DAG
)
;
case
ISD
::
XOR
:
Val
=
performXORCombine
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SETCC
:
Val
=
performSETCCCombine
(
N
,
DAG
)
;
break
;
}
if
(
Val
.
getNode
(
)
)
{
DEBUG
(
dbgs
(
)
<<
"\nMipsSE DAG Combine:\n"
;
N
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n=> \n"
;
Val
.
getNode
(
)
->
printrWithDepth
(
dbgs
(
)
,
&
DAG
)
;
dbgs
(
)
<<
"\n"
)
;
return
Val
;
}
return
MipsTargetLowering
::
PerformDAGCombine
(
N
,
DCI
)
;
}
</s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips
Mips
ISD::ADDE
ISD::AND
ISD::OR
ISD::SUBE
ISD::MUL
ISD::SHL
ISD::SRA
ISD::SRL
ISD::VSELECT
ISD::XOR
ISD::SETCC
"\nMipsSE DAG Combine:\n"
"\n=> \n"
"\n"
Mips


<s> void SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; if ( this -> getSparcTargetMachine ( ) . getSubtargetImpl ( ) -> insertNOPLoad ( ) ) { addPass ( new InsertNOPLoad ( getSparcTargetMachine ( ) ) ) ; } } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> tree function_resolver :: resolve_uniform_opt_n ( unsigned int nops ) { unsigned int i , nargs ; type_suffix_index type ; if ( ! check_gp_argument ( nops , i , nargs ) || ( type = infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; unsigned int first_arg = i ++ ; for ( ; i < nargs - 1 ; ++ i ) if ( ! require_matching_vector_type ( i , type ) ) return error_mark_node ; return finish_opt_n_resolution ( i , first_arg , type ) ; } </s>

Resolve a ( possibly predicated ) function that offers a choice between taking : - NOPS like-typed vector arguments or - NOPS - 1 like-typed vector arguments followed by a scalar argument Return the function decl of the resolved function on success , otherwise report a suitable error and return error_mark_node .


<s> const char * arm_gen_far_branch ( rtx * operands , int pos_label , const char * dest , const char * branch_format ) { rtx_code_label * tmp_label = gen_label_rtx ( ) ; char label_buf [ 256 ] ; char buffer [ 128 ] ; ASM_GENERATE_INTERNAL_LABEL ( label_buf , dest , \ CODE_LABEL_NUMBER ( tmp_label ) ) ; const char * label_ptr = arm_strip_name_encoding ( label_buf ) ; rtx dest_label = operands [ pos_label ] ; operands [ pos_label ] = tmp_label ; snprintf ( buffer , sizeof ( buffer ) , "%s%s" , branch_format , label_ptr ) ; output_asm_insn ( buffer , operands ) ; snprintf ( buffer , sizeof ( buffer ) , "b\t%%l0%d\n%s:" , pos_label , label_ptr ) ; operands [ pos_label ] = dest_label ; output_asm_insn ( buffer , operands ) ; return "" ; } </s>

Generate code to enable conditional branches in functions over 1 MiB . Parameters are : operands : is the operands list of the asm insn ( see arm_cond_branch or arm_cond_branch_reversed ) . pos_label : is an index into the operands array where operands [ pos_label ] is the asm label of the final jump destination . dest : is a string which is used to generate the asm label of the intermediate destination branch_format : is a string denoting the intermediate branch format , e.g . `` beq '' , `` bne '' , etc .


<s> const char * CAHPTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( CAHPISD :: NodeType ) Opcode ) { case CAHPISD :: FIRST_NUMBER : break ; case CAHPISD :: BR_CC : return "CAHPISD::BR_CC" ; case CAHPISD :: CALL : return "CAHPISD::CALL" ; case CAHPISD :: SELECT_CC : return "CAHPISD::SELECT_CC" ; case CAHPISD :: RET_FLAG : return "CAHPISD::RET_FLAG" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


"operation not permitted on type %<bfloat16_t%>"

"cannot combine GNU and SVE vectors in a binary operation"

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Immediate ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


Create the va_list data type . We keep 3 pointers , and two offsets . Two pointers are to the overflow area , which starts at the CFA . One of these is constant , for addressing into the GPR save area below it . The other is advanced up the stack through the overflow region . The third pointer is to the GPR save area . Since the FPR save area is just below it , we can address FPR slots off this pointer . We also keep two one-byte offsets , which are to be subtracted from the constant pointers to yield addresses in the GPR and FPR save areas . These are downcounted as float or non-float arguments are used , and when they get to zero , the argument must be obtained from the overflow region . If ! EABI_FLOAT_VARARGS_P , then no FPR save area exists , and a single pointer is enough . It 's started at the GPR save area , and is advanced , period . Note that the GPR save area is not constant size , due to optimization in the prologue . Hence , we ca n't use a design with two pointers and two offsets , although we could have designed this with two pointers and three offsets .


"We have a different number of location and args?!"

Use Handler to insert code to handle the argument/return values represented by Args .


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const PPCFrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: SPERCRegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : case PPC :: VSSRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void aarch64_emit_call_insn ( rtx pat ) { rtx insn = emit_call_insn ( pat ) ; rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP0_REGNUM ) ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP1_REGNUM ) ) ; } </s>

Emit call insn with PAT and do aarch64-specific handling .


<s> static machine_mode rx_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree funtype ATTRIBUTE_UNUSED , int for_return ) { if ( for_return != 1 || GET_MODE_SIZE ( mode ) >= 4 || COMPLEX_MODE_P ( mode ) || GET_MODE_SIZE ( mode ) < 1 ) return mode ; return SImode ; } </s>

TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with regard to function returns as does TARGET_FUNCTION_VALUE .


"emitting conditional microcode insn %s\t[%s] #%d"

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : CSR_SVR432_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) { gcc_assert ( sparc_leaf_function_p == current_function_uses_only_leaf_regs ) ; sparc_output_scratch_registers ( file ) ; } </s>

This function generates the assembly code for function entry , which boils down to emitting the necessary .register directives .


<s>
bool
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
override
{
switch
(
ConstraintID
)
{
default
:
errs
(
)
<<
"ConstraintID: "
<<
ConstraintID
<<
"\n"
;
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_es
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Z
:
case
InlineAsm
::
Constraint_Zy
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
,
1
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i32
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> int check_pic ( int i ) { rtx op ; switch ( flag_pic ) { case 1 : op = recog_data . operand [ i ] ; gcc_assert ( GET_CODE ( op ) != SYMBOL_REF && ( GET_CODE ( op ) != CONST || ( GET_CODE ( XEXP ( op , 0 ) ) == MINUS && XEXP ( XEXP ( op , 0 ) , 0 ) == sparc_got ( ) && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST ) ) ) ; case 2 : default : return 1 ; } } </s>

Ensure that we are not using patterns that are not OK with PIC .


<s> static void tryAddingPcLoadReferenceComment ( uint64_t Address , int Value , const MCDisassembler * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; Dis -> tryAddingPcLoadReferenceComment ( Value , Address ) ; } </s>

Try to add a comment on the PC-relative load .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
,
STI
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
MCInst
Res
;
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
createImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
createReg
(
0
)
)
;
Inst
=
std
::
move
(
Res
)
;
return
;
}
Inst
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( SDValue Mask , MVT VT ) const { if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( Mask . getNode ( ) -> getNumOperands ( ) <= 4 || isIdentityMask ( Mask . getNode ( ) ) || isIdentityMask ( Mask . getNode ( ) , true ) || isSplatMask ( Mask . getNode ( ) ) || X86 :: isPSHUFHWMask ( Mask . getNode ( ) ) || X86 :: isPSHUFLWMask ( Mask . getNode ( ) ) || X86 :: isUNPCKLMask ( Mask . getNode ( ) ) || X86 :: isUNPCKHMask ( Mask . getNode ( ) ) || X86 :: isUNPCKL_v_undef_Mask ( Mask . getNode ( ) ) || X86 :: isUNPCKH_v_undef_Mask ( Mask . getNode ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool AArch64InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) return true ; switch ( MI . getOpcode ( ) ) { case AArch64 :: HINT : if ( MI . getOperand ( 0 ) . getImm ( ) == 0x14 ) return true ; break ; case AArch64 :: DSB : case AArch64 :: ISB : return true ; default : ; } return isSEHInstruction ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> bool csky_emit_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { bool invert ; rtx cc_reg = gen_rtx_REG ( CCmode , CSKY_CC_REGNUM ) ; if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_FLOAT ) return csky_emit_compare_float ( code , op0 , op1 ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( op1 ) ; switch ( code ) { case GTU : if ( val == 0 ) code = NE ; else if ( TARGET_MINI_REGISTERS ? CSKY_CONST_OK_FOR_J ( val + 1 ) : CSKY_CONST_OK_FOR_Uk ( val + 1 ) ) { op1 = GEN_INT ( val + 1 ) ; code = GEU ; } break ; case GT : case LE : if ( TARGET_MINI_REGISTERS ? CSKY_CONST_OK_FOR_J ( val + 1 ) : CSKY_CONST_OK_FOR_Uk ( val + 1 ) ) { op1 = GEN_INT ( val + 1 ) ; code = code == LE ? LT : GE ; } break ; default : break ; } } if ( CONSTANT_P ( op1 ) && GET_CODE ( op1 ) != CONST_INT ) op1 = force_reg ( GET_MODE ( op1 ) , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; case NE : if ( GET_CODE ( op1 ) == CONST_INT && ( TARGET_MINI_REGISTERS ? ! csky_literal_K_operand ( op1 , SImode ) : ! csky_literal_I_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : code = GT ; invert = true ; case GT : if ( GET_CODE ( op1 ) == CONST_INT ) op1 = force_reg ( SImode , op1 ) ; break ; case GE : code = LT ; invert = true ; case LT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 && ( TARGET_MINI_REGISTERS ? ! csky_literal_J_operand ( op1 , SImode ) : ! csky_literal_Uk_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case GTU : gcc_assert ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) != 0 ) ; code = LEU ; invert = true ; case LEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; case LTU : code = GEU ; invert = true ; case GEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 && ( TARGET_MINI_REGISTERS ? ! csky_literal_J_operand ( op1 , SImode ) : ! csky_literal_Uk_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; default : break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return invert ; } </s>

Emit a comparison instruction . Return true if an inverted comparison is generated .


<s> void LanaiTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == 0 ) { Result = DAG . getTargetConstant ( 0 , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < 16 > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= 31 ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < 32 > ( Val ) ) && ( ( Val & 0xffff ) == 0 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - 33554432 ) && ( Val <= 33554431 ) ) { Result = DAG . getTargetConstant ( Val , SDLoc ( C ) , Op . getValueType ( ) ) ; break ; } } return ; default : break ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> static SparcOperand * CreateReg ( unsigned RegNum , unsigned Kind , SMLoc S , SMLoc E ) { SparcOperand * Op = new SparcOperand ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = ( SparcOperand :: RegisterKind ) Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .

Sparc Sparc Sparc Sparc SparcOperand::RegisterKind


<s> void CSKYTargetStreamer :: emitCurrentConstantPool ( ) { ConstantPool -> emitAll ( Streamer ) ; ConstantPool -> clearCache ( ) ; } </s>

Callback used to implement the .ltorg directive .


<s> bool Thumb2InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { while ( MBBI -> isDebugInstr ( ) ) { ++ MBBI ; if ( MBBI == MBB . end ( ) ) return false ; } Register PredReg ; return getITInstrPredicate ( * MBBI , PredReg ) == ARMCC :: AL ; } </s>

Return true if it 's legal to split the given basic block at the specified instruction ( i.e .


<s> void SystemZPassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createSystemZPostRewritePass ( getSystemZTargetMachine ( ) ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static void mt_machine_reorg ( void ) { if ( mt_flag_delayed_branch ) dbr_schedule ( get_insns ( ) , dump_file ) ; if ( TARGET_MS2 ) { split_all_insns_noflow ( ) ; mt_reorg_hazard ( ) ; } } </s>

Fixup the looping instructions , do delayed branch scheduling , fixup scheduling hazards .


<s> bool X86TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86ISelDag ( * this , OptLevel ) ) ; if ( ! Subtarget . is64Bit ( ) ) PM . add ( createGlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


runOnMachineFunction - Emit the function body .


<s> bool xstormy16_splittable_below100_operand ( rtx x , machine_mode mode ) { if ( MEM_P ( x ) && MEM_VOLATILE_P ( x ) ) return 0 ; return xstormy16_below100_operand ( x , mode ) ; } </s>

Likewise , but only for non-volatile MEMs , for patterns where the MEM will get split into smaller sized accesses .


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && align >= 128 ) clear_step = 16 ; else if ( TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) clear_step = 8 ; else if ( TARGET_SPE && align >= 64 ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= 16 && TARGET_ALTIVEC && align >= 128 ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_SPE && align >= 64 ) { clear_bytes = 8 ; mode = V2SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 8 ; mode = DImode ; if ( offset == 0 && align < 64 ) { rtx addr ; addr = XEXP ( orig_dest , 0 ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , 1 ) ) & 3 ) != 0 ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> bool AArch64TargetLowering :: isLegalICmpImmediate ( int64_t Immed ) const { return isLegalAddImmediate ( Immed ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y , rtx scratch ) { machine_mode mode ; rtx cc_reg ; int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , 0 , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s>
int
ix86_attr_length_immediate_default
(
rtx
insn
,
int
shortform
)
{
int
len
=
0
;
int
i
;
extract_insn_cached
(
insn
)
;
for
(
i
=
recog_data
.
n_operands
1
;
i
>=
0
;
i
)
if
(
CONSTANT_P
(
recog_data
.
operand
[
i
]
)
)
{
gcc_assert
(
!
len
)
;
if
(
shortform
&&
GET_CODE
(
recog_data
.
operand
[
i
]
)
==
CONST_INT
&&
CONST_OK_FOR_LETTER_P
(
INTVAL
(
recog_data
.
operand
[
i
]
)
,
'K'
)
)
len
=
1
;
else
{
switch
(
get_attr_mode
(
insn
)
)
{
case
MODE_QI
:
len
+=
1
;
break
;
case
MODE_HI
:
len
+=
2
;
break
;
case
MODE_SI
:
len
+=
4
;
break
;
case
MODE_DI
:
len
+=
4
;
break
;
default
:
fatal_insn
(
"unknown insn mode"
,
insn
)
;
}
}
}
return
len
;
}
</s>

Compute default value for `` length_immediate '' attribute . When SHORTFORM is set expect that insn have 8bit immediate alternative .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; unsigned AS = DstPtrInfo . getAddrSpace ( ) ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) , AS ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> unsigned X86FrameLowering :: getWinEHParentFrameOffset ( const MachineFunction & MF ) const { unsigned Offset = 16 ; Offset += SlotSize ; Offset += MF . getInfo < X86MachineFunctionInfo > ( ) -> getCalleeSavedFrameSize ( ) ; Offset += getWinEHFuncletFrameSize ( MF ) ; return Offset ; } </s>

The parent frame offset ( aka dispFrame ) is only used on X86_64 to retrieve the parent 's frame pointer .


<s> unsigned PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> GetInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return 5 ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> bool PPCInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { if ( ! LdSt . mayLoadOrStore ( ) || LdSt . getNumExplicitOperands ( ) != 3 ) return false ; if ( ! LdSt . getOperand ( 1 ) . isImm ( ) || ( ! LdSt . getOperand ( 2 ) . isReg ( ) && ! LdSt . getOperand ( 2 ) . isFI ( ) ) ) return false ; if ( ! LdSt . getOperand ( 1 ) . isImm ( ) || ( ! LdSt . getOperand ( 2 ) . isReg ( ) && ! LdSt . getOperand ( 2 ) . isFI ( ) ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; Offset = LdSt . getOperand ( 1 ) . getImm ( ) ; BaseReg = & LdSt . getOperand ( 2 ) ; return true ; } </s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool PPCTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_PPC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
void
rs6000_xcoff_declare_function_name
(
FILE
*
file
,
const
char
*
name
,
tree
decl
)
{
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
1
)
;
char
*
p
;
int
dollar_inside
=
0
;
struct
declare_alias_data
data
=
{
file
,
false
}
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
decl
)
)
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.globl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
}
else
{
if
(
dollar_inside
)
{
fprintf
(
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
fprintf
(
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
fputs
(
"\t.lglobl ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
putc
(
'\n'
,
file
)
;
}
fputs
(
"\t.csect "
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
TARGET_32BIT
"[DS]\n"
:
"[DS],3\n"
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
fputs
(
TARGET_32BIT
"\t.long ."
:
"\t.llong ."
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
", TOC[tc0], 0\n"
,
file
)
;
in_section
=
;
switch_to_section
(
function_section
(
decl
)
)
;
putc
(
'.'
,
file
)
;
RS6000_OUTPUT_BASENAME
(
file
,
buffer
)
;
fputs
(
":\n"
,
file
)
;
data
.
function_descriptor
=
true
;
symtab_node
::
get
(
decl
)
->
call_for_symbol_and_aliases
(
rs6000_declare_alias
,
&
data
,
true
)
;
if
(
write_symbols
!=
NO_DEBUG
&&
!
DECL_IGNORED_P
(
decl
)
)
xcoffout_declare_function
(
file
,
decl
,
buffer
)
;
return
;
}
</s>

This macro produces the initial definition of a function name . On the RS/6000 , we need to place an extra ' . ' in the function name and output the function descriptor . Dollar signs are converted to underscores . The csect for the function will have already been created when text_section was selected . We do have to go back to that csect , however . The third and fourth parameters to the .function pseudo-op ( 16 and 044 ) are placeholders which no longer have any use . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> rtx aarch64_ptrue_reg ( machine_mode mode ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) ; rtx reg = force_reg ( VNx16BImode , CONSTM1_RTX ( VNx16BImode ) ) ; return gen_lowpart ( mode , reg ) ; } </s>

Return an all-true predicate register of mode MODE .


This function will set the fpscr from memory . MODE is the mode we are setting it to .


<s> static HOST_WIDE_INT rs6000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ( STRICT_ALIGNMENT || ! optimize_size ) ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> bool PPCTTIImpl :: isHardwareLoopProfitable ( Loop * L , ScalarEvolution & SE , AssumptionCache & AC , TargetLibraryInfo * LibInfo , HardwareLoopInfo & HWLoopInfo ) { const PPCTargetMachine & TM = ST -> getTargetMachine ( ) ; TargetSchedModel SchedModel ; SchedModel . init ( ST ) ; unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , 32 > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( 6 * SchedModel . getIssueWidth ( ) ) ) return false ; } SmallPtrSet < const Value * , 4 > Visited ; for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo , Visited ) ) return false ; SmallVector < BasicBlock * , 4 > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ; if ( ! TI ) continue ; if ( BranchInst * BI = dyn_cast < BranchInst > ( TI ) ) { uint64_t TrueWeight = 0 , FalseWeight = 0 ; if ( ! BI -> isConditional ( ) || ! BI -> extractProfMetadata ( TrueWeight , FalseWeight ) ) continue ; bool TrueIsExit = ! L -> contains ( BI -> getSuccessor ( 0 ) ) ; if ( ( TrueIsExit && FalseWeight < TrueWeight ) || ( ! TrueIsExit && FalseWeight > TrueWeight ) ) return false ; } } SmallVector < BasicBlock * , 4 > ExitBlocks ; L -> getExitBlocks ( ExitBlocks ) ; for ( auto & BB : ExitBlocks ) { for ( auto & PHI : BB -> phis ( ) ) { for ( int Idx = 0 , EndIdx = PHI . getNumIncomingValues ( ) ; Idx < EndIdx ; Idx ++ ) { const BasicBlock * IncomingBB = PHI . getIncomingBlock ( Idx ) ; const Value * IncomingValue = PHI . getIncomingValue ( Idx ) ; if ( L -> contains ( IncomingBB ) && memAddrUsesCTR ( IncomingValue , TM , Visited ) ) return false ; } } } LLVMContext & C = L -> getHeader ( ) -> getContext ( ) ; HWLoopInfo . CountType = TM . isPPC64 ( ) ? Type :: getInt64Ty ( C ) : Type :: getInt32Ty ( C ) ; HWLoopInfo . LoopDecrement = ConstantInt :: get ( HWLoopInfo . CountType , 1 ) ; return true ; } </s>

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s>
void
arm_emit_eabi_attribute
(
const
char
*
name
,
int
num
,
int
val
)
{
asm_fprintf
(
asm_out_file
,
"\t.eabi_attribute %d, %d"
,
num
,
val
)
;
if
(
flag_verbose_asm
||
flag_debug_asm
)
asm_fprintf
(
asm_out_file
,
"\t%s %s"
,
ASM_COMMENT_START
,
name
)
;
asm_fprintf
(
asm_out_file
,
"\n"
)
;
}
</s>

This function is used to emit an EABI tag and its associated value . We emit the numerical value of the tag in case the assembler does not support textual tags . ( Eg gas prior to 2.20 ) . If requested we include the tag name in a comment so that anyone reading the assembler output will know which tag is being set . This function is not static because arm-c.cc needs it too .

arm
"\t.eabi_attribute %d, %d"
"\t%s %s"
"\n"


<s> static void pa_init_libfuncs ( void ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { set_optab_libfunc ( add_optab , TFmode , "_U_Qfadd" ) ; set_optab_libfunc ( sub_optab , TFmode , "_U_Qfsub" ) ; set_optab_libfunc ( smul_optab , TFmode , "_U_Qfmpy" ) ; set_optab_libfunc ( sdiv_optab , TFmode , "_U_Qfdiv" ) ; set_optab_libfunc ( smin_optab , TFmode , "_U_Qmin" ) ; set_optab_libfunc ( smax_optab , TFmode , "_U_Qfmax" ) ; set_optab_libfunc ( sqrt_optab , TFmode , "_U_Qfsqrt" ) ; set_optab_libfunc ( abs_optab , TFmode , "_U_Qfabs" ) ; set_optab_libfunc ( neg_optab , TFmode , "_U_Qfneg" ) ; set_optab_libfunc ( eq_optab , TFmode , "_U_Qfeq" ) ; set_optab_libfunc ( ne_optab , TFmode , "_U_Qfne" ) ; set_optab_libfunc ( gt_optab , TFmode , "_U_Qfgt" ) ; set_optab_libfunc ( ge_optab , TFmode , "_U_Qfge" ) ; set_optab_libfunc ( lt_optab , TFmode , "_U_Qflt" ) ; set_optab_libfunc ( le_optab , TFmode , "_U_Qfle" ) ; set_optab_libfunc ( unord_optab , TFmode , "_U_Qfunord" ) ; set_conv_libfunc ( sext_optab , TFmode , SFmode , "_U_Qfcnvff_sgl_to_quad" ) ; set_conv_libfunc ( sext_optab , TFmode , DFmode , "_U_Qfcnvff_dbl_to_quad" ) ; set_conv_libfunc ( trunc_optab , SFmode , TFmode , "_U_Qfcnvff_quad_to_sgl" ) ; set_conv_libfunc ( trunc_optab , DFmode , TFmode , "_U_Qfcnvff_quad_to_dbl" ) ; set_conv_libfunc ( sfix_optab , SImode , TFmode , TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" : "_U_Qfcnvfxt_quad_to_sgl" ) ; set_conv_libfunc ( sfix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_dbl" ) ; set_conv_libfunc ( ufix_optab , SImode , TFmode , "_U_Qfcnvfxt_quad_to_usgl" ) ; set_conv_libfunc ( ufix_optab , DImode , TFmode , "_U_Qfcnvfxt_quad_to_udbl" ) ; set_conv_libfunc ( sfloat_optab , TFmode , SImode , "_U_Qfcnvxf_sgl_to_quad" ) ; set_conv_libfunc ( sfloat_optab , TFmode , DImode , "_U_Qfcnvxf_dbl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , SImode , "_U_Qfcnvxf_usgl_to_quad" ) ; set_conv_libfunc ( ufloat_optab , TFmode , DImode , "_U_Qfcnvxf_udbl_to_quad" ) ; } if ( TARGET_SYNC_LIBCALL ) init_sync_libfuncs ( UNITS_PER_WORD ) ; } </s>

Initialize optabs to point to emulation routines .


<s> SDValue PPCTargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . isPPC64 ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Default : case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; default : return DAG . getNode ( PPCISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } } </s>

Returns relocation base for the given PIC jumptable .


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> static HOST_WIDE_INT iq2000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> bool AArch64RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const PPCSubtarget & Subtarget = FuncInfo . MF -> getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . isPPC64 ( ) && Subtarget . isSVR4ABI ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

PowerPC PPC::createFastISel PPC PPC PPC PPC


<s> bool AArch64InstrInfo :: isPreSt ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRWpre : case AArch64 :: STRXpre : case AArch64 :: STRSpre : case AArch64 :: STRDpre : case AArch64 :: STRQpre : return true ; } } </s>

Returns whether the instruction is a pre-indexed store .


<s>
bool
X86AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
if
(
Subtarget
->
isTargetCOFF
(
)
)
{
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
EmitRawText
(
"\t.def\t "
+
Twine
(
CurrentFnSym
->
getName
(
)
)
+
";\t.scl\t"
+
Twine
(
F
->
hasInternalLinkage
(
)
COFF
::
C_STAT
:
COFF
::
C_EXT
)
+
";\t.type\t"
+
Twine
(
COFF
::
DT_FCN
<<
COFF
::
N_BTSHFT
)
+
";\t.endef"
)
;
}
EmitFunctionHeader
(
)
;
EmitFunctionBody
(
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> inline hashval_t libcall_hasher :: hash ( const rtx_def * p1 ) { return hash_rtx ( p1 , VOIDmode , NULL , NULL , FALSE ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
It
;
return
CallPt
;
}
saveLROnStack
(
MBB
,
It
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
0
"No callee-saved register available?"
ARM::LR
ARM::LR


<s>
const
MCPhysReg
*
ARM64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_ARM64_AllRegs_SaveList
;
else
return
CSR_ARM64_AAPCS_SaveList
;
}
</s>


<s> static bool ix86_use_mask_cmp_p ( machine_mode mode , machine_mode cmp_mode , rtx op_true , rtx op_false ) { int vector_size = GET_MODE_SIZE ( mode ) ; if ( cmp_mode == HFmode ) return true ; else if ( vector_size < 16 ) return false ; else if ( vector_size == 64 ) return true ; else if ( GET_MODE_INNER ( cmp_mode ) == HFmode ) return true ; gcc_assert ( ! op_true == ! op_false ) ; if ( ! op_true || ! ix86_valid_mask_cmp_mode ( cmp_mode ) ) return false ; if ( op_false == CONST0_RTX ( mode ) || op_true == CONST0_RTX ( mode ) || ( INTEGRAL_MODE_P ( mode ) && ( op_true == CONSTM1_RTX ( mode ) || op_false == CONSTM1_RTX ( mode ) ) ) ) return false ; return true ; } </s>

Return true if integer mask comparison should be used .