<s> static bool mep_use_post_modify_p_1 ( rtx_insn * set_insn , rtx reg , rtx offset ) { rtx_insn * insn ; insn = set_insn ; do { insn = PREV_INSN ( insn ) ; if ( INSN_P ( insn ) ) { if ( mep_use_post_modify_for_set_p ( PATTERN ( insn ) , reg , offset ) ) { mep_make_parallel ( insn , set_insn ) ; return true ; } if ( reg_set_p ( reg , insn ) || reg_referenced_p ( reg , PATTERN ( insn ) ) || volatile_insn_p ( PATTERN ( insn ) ) ) return false ; } } while ( ! NOTE_INSN_BASIC_BLOCK_P ( insn ) ) ; return false ; } </s>

SET_INSN is an instruction that adds OFFSET to REG . Go back through the basic block to see if any previous load or store instruction can be persuaded to do SET_INSN as a side-effect . Return true if so .


<s> static void nds32_relax_group ( void ) { rtx_insn * insn ; compute_bb_for_insn ( ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_insn_rescan_all ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_active_insn ( insn ) ; insn ; insn = next_active_insn ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_sethi && nds32_symbolic_operand ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) , SImode ) ) nds32_group_insns ( insn ) ; } } df_insn_rescan_all ( ) ; df_finish_pass ( false ) ; free_dominance_info ( CDI_DOMINATORS ) ; } </s>

Group the relax candidate instructions for linker .


"passing %qT to argument %d of %qE, but its"

Finish resolving a function whose final argument can be a vector or a scalar , with the function having an implicit `` _n '' suffix in the latter case . This `` _n '' form might only exist for certain type suffixes . ARGNO is the index of the final argument . The inferred type suffix was obtained from argument FIRST_ARGNO , which has type FIRST_TYPE . EXPECTED_TCLASS and EXPECTED_BITS describe the expected properties of the final vector or scalar argument , in the same way as for require_derived_vector_type . INFERRED_TYPE is the inferred type suffix itself , or NUM_TYPE_SUFFIXES if it 's the same as FIRST_TYPE . Return the function decl of the resolved function on success , otherwise report a suitable error and return error_mark_node .


<s>
static
void
mips16_build_function_stub
(
void
)
{
const
char
*
fnname
,
*
alias_name
,
*
separator
;
char
*
secname
,
*
stubname
;
tree
stubdecl
;
unsigned
int
f
;
rtx
symbol
,
alias
;
symbol
=
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
;
alias
=
mips16_local_alias
(
symbol
)
;
fnname
=
targetm
.
strip_name_encoding
(
XSTR
(
symbol
,
0
)
)
;
alias_name
=
targetm
.
strip_name_encoding
(
XSTR
(
alias
,
0
)
)
;
secname
=
ACONCAT
(
(
".mips16.fn."
,
fnname
,
)
)
;
stubname
=
ACONCAT
(
(
"__fn_stub_"
,
fnname
,
)
)
;
stubdecl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
stubname
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
set_decl_section_name
(
stubdecl
,
secname
)
;
DECL_RESULT
(
stubdecl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
fprintf
(
asm_out_file
,
"\t# Stub function for %s ("
,
current_function_name
(
)
)
;
separator
=
""
;
for
(
f
=
(
unsigned
int
)
crtl
->
args
.
info
.
fp_code
;
f
!=
0
;
f
>>=
2
)
{
fprintf
(
asm_out_file
,
"%s%s"
,
separator
,
(
f
&
3
)
==
1
"float"
:
"double"
)
;
separator
=
", "
;
}
fprintf
(
asm_out_file
,
")\n"
)
;
assemble_start_function
(
stubdecl
,
stubname
)
;
mips_start_function_definition
(
stubname
,
false
)
;
if
(
TARGET_ABICALLS_PIC2
)
{
if
(
TARGET_ABSOLUTE_ABICALLS
)
fprintf
(
asm_out_file
,
"\t.option\tpic0\n"
)
;
else
{
output_asm_insn
(
"%(.cpload\t%^%)"
,
)
;
output_asm_insn
(
".reloc\t0,R_MIPS_NONE,%0"
,
&
symbol
)
;
symbol
=
alias
;
}
}
output_asm_insn
(
"la\t%^,%0"
,
&
symbol
)
;
mips_output_args_xfer
(
crtl
->
args
.
info
.
fp_code
,
'f'
)
;
output_asm_insn
(
"jr\t%^"
,
)
;
if
(
TARGET_ABICALLS_PIC2
&&
TARGET_ABSOLUTE_ABICALLS
)
fprintf
(
asm_out_file
,
"\t.option\tpic2\n"
)
;
mips_end_function_definition
(
stubname
)
;
ASM_OUTPUT_DEF
(
asm_out_file
,
alias_name
,
fnname
)
;
switch_to_section
(
function_section
(
current_function_decl
)
)
;
}
</s>

Write a MIPS16 stub for the current function . This stub is used for functions which take arguments in the floating-point registers . It is normal-mode code that moves the floating-point arguments into the general registers and then jumps to the MIPS16 code .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: PPC32_GOT : return "PPCISD::PPC32_GOT" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> std :: unique_ptr < CSEConfigBase > MipsPassConfig :: getCSEConfig ( ) const { return getStandardCSEConfigForOpt ( TM -> getOptLevel ( ) ) ; } </s>

Returns the CSEConfig object to use for the current optimization level .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle , bool MinSize ) : ARMGenSubtargetInfo ( TT , CPU , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new ARMCallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new ARMLegalizerInfo ( * this ) ) ; auto * RBI = new ARMRegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createARMInstructionSelector ( * static_cast < const ARMBaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 vzeroupper inserter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static pad_direction pa_function_arg_padding ( machine_mode mode , const_tree type ) { if ( mode == BLKmode || ( TARGET_64BIT && type && ( AGGREGATE_TYPE_P ( type ) || TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) ) ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( int_size_in_bytes ( type ) * BITS_PER_UNIT ) % PARM_BOUNDARY == 0 ) return PAD_NONE ; if ( TARGET_64BIT ) return PAD_UPWARD ; else return PAD_DOWNWARD ; } if ( GET_MODE_BITSIZE ( mode ) < PARM_BOUNDARY ) return PAD_DOWNWARD ; else return PAD_NONE ; } </s>


<s> void ia64_expand_unpack ( rtx operands [ 3 ] , bool unsignedp , bool highp ) { rtx sign = ia64_unpack_sign ( operands [ 1 ] , unsignedp ) ; ia64_unpack_assemble ( operands [ 0 ] , operands [ 1 ] , sign , highp ) ; } </s>

Emit an integral vector unpack operation .


<s> int eq_neq_comparison_operator ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ; } </s>

Return 1 if OP is an equality comparison , else return 0 .


<s>
static
int
ia64_dfa_new_cycle
(
FILE
*
dump
,
int
verbose
,
rtx_insn
*
insn
,
int
last_clock
,
int
clock
,
int
*
sort_p
)
{
gcc_assert
(
insn
&&
INSN_P
(
insn
)
)
;
if
(
DEBUG_INSN_P
(
insn
)
)
return
0
;
gcc_assert
(
!
(
reload_completed
&&
safe_group_barrier_needed
(
insn
)
)
||
last_scheduled_insn
)
;
if
(
(
reload_completed
&&
(
safe_group_barrier_needed
(
insn
)
||
(
mflag_sched_stop_bits_after_every_cycle
&&
last_clock
!=
clock
&&
last_scheduled_insn
&&
scheduled_good_insn
(
last_scheduled_insn
)
)
)
)
||
(
last_scheduled_insn
&&
(
CALL_P
(
last_scheduled_insn
)
||
unknown_for_bundling_p
(
last_scheduled_insn
)
)
)
)
{
init_insn_group_barriers
(
)
;
if
(
verbose
&&
dump
)
fprintf
(
dump
,
"//    Stop should be before %d%s\n"
,
INSN_UID
(
insn
)
,
last_clock
==
clock
" + cycle advance"
:
""
)
;
stop_before_p
=
1
;
current_cycle
=
clock
;
mem_ops_in_group
[
current_cycle
%
4
]
=
0
;
if
(
last_clock
==
clock
)
{
state_transition
(
curr_state
,
dfa_stop_insn
)
;
if
(
TARGET_EARLY_STOP_BITS
)
*
sort_p
=
(
last_scheduled_insn
==
NULL_RTX
||
!
CALL_P
(
last_scheduled_insn
)
)
;
else
*
sort_p
=
0
;
return
1
;
}
if
(
last_scheduled_insn
)
{
if
(
unknown_for_bundling_p
(
last_scheduled_insn
)
)
state_reset
(
curr_state
)
;
else
{
memcpy
(
curr_state
,
prev_cycle_state
,
dfa_state_size
)
;
state_transition
(
curr_state
,
dfa_stop_insn
)
;
state_transition
(
curr_state
,
dfa_pre_cycle_insn
)
;
state_transition
(
curr_state
,
)
;
}
}
}
return
0
;
}
</s>

We are about to being issuing INSN . Return nonzero if we can not issue it on given cycle CLOCK and return zero if we should not sort the ready queue on the next clock start .


<s> unsigned PPCTargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getCPUDirective ( ) ) { default : return 3 ; case PPC :: DIR_440 : case PPC :: DIR_A2 : case PPC :: DIR_E500 : case PPC :: DIR_E500mc : case PPC :: DIR_E5500 : return 2 ; } } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> bool function_resolver :: check_gp_argument ( unsigned int nops , unsigned int & i , unsigned int & nargs ) { i = 0 ; if ( pred != PRED_none ) { gcc_assert ( nops != 1 || pred != PRED_m ) ; nargs = nops + 1 ; if ( ! check_num_arguments ( nargs ) || ! require_vector_type ( i , VECTOR_TYPE_svbool_t ) ) return false ; i += 1 ; } else { nargs = nops ; if ( ! check_num_arguments ( nargs ) ) return false ; } return true ; } </s>

If the function is predicated , check that the first argument is a suitable governing predicate . Also check that there are NOPS further arguments after any governing predicate , but do n't check what they are . Return true on success , otherwise report a suitable error . When returning true : - set I to the number of the first unchecked argument . - set NARGS to the total number of arguments .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Promote Constant"
;
}
</s>


<s> enum reg_class mips_secondary_reload_class ( enum reg_class rclass , machine_mode mode , rtx x , bool ) { int regno ; if ( mips_dangerous_for_la25_p ( x ) ) return reg_class_subset_p ( rclass , LEA_REGS ) ? NO_REGS : LEA_REGS ; regno = true_regnum ( x ) ; if ( TARGET_MIPS16 ) { if ( ! reg_class_subset_p ( rclass , M16_REGS ) && ! M16_REG_P ( regno ) ) return M16_REGS ; return NO_REGS ; } if ( reg_class_subset_p ( rclass , ACC_REGS ) ) return GP_REG_P ( regno ) ? NO_REGS : GR_REGS ; if ( ACC_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; if ( reg_class_subset_p ( rclass , FP_REGS ) ) { if ( regno < 0 || ( MEM_P ( x ) && ( GET_MODE_SIZE ( mode ) == 4 || GET_MODE_SIZE ( mode ) == 8 ) ) ) return NO_REGS ; if ( GP_REG_P ( regno ) || x == CONST0_RTX ( mode ) ) return NO_REGS ; if ( CONSTANT_P ( x ) && ! targetm . cannot_force_const_mem ( mode , x ) ) return NO_REGS ; if ( FP_REG_P ( regno ) && mips_mode_ok_for_mov_fmt_p ( mode ) ) return NO_REGS ; return GR_REGS ; } if ( FP_REG_P ( regno ) ) return reg_class_subset_p ( rclass , GR_REGS ) ? NO_REGS : GR_REGS ; return NO_REGS ; } </s>

This function returns the register class required for a secondary register when copying between one of the registers in CLASS , and X , using MODE . If IN_P is nonzero , the copy is going from X to the register , otherwise the register is the source . A return value of NO_REGS means that no secondary register is required .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { AArch64FI = F . getInfo < AArch64FunctionInfo > ( ) ; STI = static_cast < const AArch64Subtarget * > ( & F . getSubtarget ( ) ) ; return AsmPrinter :: runOnMachineFunction ( F ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: LXVX : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : case PPC :: SPILLTOVSR_LD : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool CSKYConstantPool :: empty ( ) { return Entries . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> std :: vector < std :: pair < uint64_t , uint64_t >> findPltEntries ( uint64_t PltSectionVA , ArrayRef < uint8_t > PltContents , uint64_t GotPltSectionVA , const Triple & TargetTriple ) const override { std :: vector < std :: pair < uint64_t , uint64_t >> Result ; for ( uint64_t Byte = 0 , End = PltContents . size ( ) ; Byte + 7 < End ; Byte += 4 ) { uint32_t Insn = support :: endian :: read32le ( PltContents . data ( ) + Byte ) ; if ( ( Insn & 0x9f000000 ) != 0x90000000 ) continue ; uint64_t Imm = ( ( ( PltSectionVA + Byte ) >> 12 ) << 12 ) + ( ( ( Insn >> 29 ) & 3 ) << 12 ) + ( ( ( Insn >> 5 ) & 0x3ffff ) << 14 ) ; uint32_t Insn2 = support :: endian :: read32le ( PltContents . data ( ) + Byte + 4 ) ; if ( Insn2 >> 22 == 0x3e5 ) { Imm += ( ( Insn2 >> 10 ) & 0xfff ) << 3 ; Result . push_back ( std :: make_pair ( PltSectionVA + Byte , Imm ) ) ; Byte += 4 ; } } return Result ; } </s>

Returns ( PLT virtual address , GOT virtual address ) pairs for PLT entries .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { const DataLayout & DL = MF -> getDataLayout ( ) ; SectionKind Kind = CPE . getSectionKind ( & DL ) ; const Constant * C = CPE . Val . ConstVal ; unsigned Align = CPE . Alignment ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( DL , Kind , C , Align ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s>
Register
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
return
MIRBuilder
.
buildFrameIndex
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
,
FI
)
.
getReg
(
0
)
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


Function to tell the preprocessor about the defines for the current target .


"multiversioning needs %<ifunc%> which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI -> getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
void
Finish
(
)
{
const
size_t
VendorHeaderSize
=
4
+
CurrentVendor
.
size
(
)
+
1
;
const
size_t
TagHeaderSize
=
1
+
4
;
Streamer
.
EmitIntValue
(
VendorHeaderSize
+
TagHeaderSize
+
ContentsSize
,
4
)
;
Streamer
.
EmitBytes
(
CurrentVendor
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
Streamer
.
EmitIntValue
(
ARMBuildAttrs
::
File
,
1
)
;
Streamer
.
EmitIntValue
(
TagHeaderSize
+
ContentsSize
,
4
)
;
for
(
unsigned
int
i
=
0
;
i
<
Contents
.
size
(
)
;
++
i
)
{
AttributeItemType
item
=
Contents
[
i
]
;
Streamer
.
EmitULEB128IntValue
(
item
.
Tag
,
0
)
;
switch
(
item
.
Type
)
{
case
AttributeItemType
::
NumericAttribute
:
Streamer
.
EmitULEB128IntValue
(
item
.
IntValue
,
0
)
;
break
;
case
AttributeItemType
::
TextAttribute
:
Streamer
.
EmitBytes
(
item
.
StringValue
.
upper
(
)
,
0
)
;
Streamer
.
EmitIntValue
(
0
,
1
)
;
break
;
default
:
assert
(
0
&&
"Invalid attribute type"
)
;
}
}
Contents
.
clear
(
)
;
}
</s>

Finish - Do final processing and write the object to the output stream .


<s> bool SystemZExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const SystemZInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>


<s> void FPGATTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { UP . Threshold = 0 ; UP . PartialThreshold = 0 ; UP . Count = 1 ; UP . MaxCount = 1 ; UP . FullUnrollMaxCount = 1 ; UP . Partial = false ; UP . Runtime = false ; UP . AllowRemainder = false ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


"Can only insert epilog into returning blocks"


<s> bool ARMInstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; MachineInstr * PopMI = MF . CreateMachineInstr ( get ( ARM :: tPOP ) , MI -> getDebugLoc ( ) ) ; MBB . insert ( MI , PopMI ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; PopMI -> setDesc ( get ( ARM :: tPOP_RET ) ) ; MBB . erase ( MI ) ; } PopMI -> addOperand ( MachineOperand :: CreateReg ( Reg , true ) ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool Cpu0PassConfig :: addInstSelector ( ) { addPass ( createCpu0SEISelDag ( getCpu0TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> const ARM64RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , 0 ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ; } </s>

Locate some local-dynamic symbol still in use by this function so that we can print its name in local-dynamic base patterns .


<s>
const
char
*
output_movedouble
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
machine_mode
mode
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
MEM_P
(
dst
)
&&
GET_CODE
(
XEXP
(
dst
,
0
)
)
==
PRE_DEC
)
return
"mov.l	%T1,%0"
"\n"
"	mov.l	%1,%0"
;
if
(
register_operand
(
dst
,
mode
)
&&
register_operand
(
src
,
mode
)
)
{
if
(
REGNO
(
src
)
==
MACH_REG
)
return
"sts	mach,%S0"
"\n"
"	sts	macl,%R0"
;
if
(
REGNO
(
src
)
+
1
==
REGNO
(
dst
)
)
return
"mov	%T1,%T0"
"\n"
"	mov	%1,%0"
;
else
return
"mov	%1,%0"
"\n"
"	mov	%T1,%T0"
;
}
else
if
(
CONST_INT_P
(
src
)
)
{
if
(
INTVAL
(
src
)
<
0
)
output_asm_insn
(
"mov	#-1,%S0"
,
operands
)
;
else
output_asm_insn
(
"mov	#0,%S0"
,
operands
)
;
return
"mov	%1,%R0"
;
}
else
if
(
MEM_P
(
src
)
)
{
int
ptrreg
=
1
;
int
dreg
=
REGNO
(
dst
)
;
rtx
inside
=
XEXP
(
src
,
0
)
;
switch
(
GET_CODE
(
inside
)
)
{
case
REG
:
ptrreg
=
REGNO
(
inside
)
;
break
;
case
SUBREG
:
ptrreg
=
subreg_regno
(
inside
)
;
break
;
case
PLUS
:
ptrreg
=
REGNO
(
XEXP
(
inside
,
0
)
)
;
gcc_assert
(
!
REG_P
(
XEXP
(
inside
,
1
)
)
)
;
break
;
case
LABEL_REF
:
return
"mov.l	%1,%0"
"\n"
"	mov.l	%1+4,%T0"
;
case
POST_INC
:
return
"mov.l	%1,%0"
"\n"
"	mov.l	%1,%T0"
;
default
:
gcc_unreachable
(
)
;
}
if
(
dreg
==
ptrreg
)
return
"mov.l	%T1,%T0"
"\n"
"	mov.l	%1,%0"
;
}
return
"mov.l	%1,%0"
"\n"
"	mov.l	%T1,%T0"
;
}
</s>

Return a sequence of instructions to perform DI or DF move . Since the SH can not move a DI or DF in one instruction , we have to take care when we see overlapping source and dest registers .


<s> int rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > 4 && ninsns <= 8 && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 || rs6000_cpu == PROCESSOR_POWER7 || rs6000_cpu == PROCESSOR_POWER8 || rs6000_cpu == PROCESSOR_POWER9 ) ) return 5 ; else return align_loops_log ; } </s>


<s> bool AArch64InstrInfo :: hasUnscaledLdStOffset ( unsigned Opc ) { switch ( Opc ) { default : return false ; case AArch64 :: STURSi : case AArch64 :: STRSpre : case AArch64 :: STURDi : case AArch64 :: STRDpre : case AArch64 :: STURQi : case AArch64 :: STRQpre : case AArch64 :: STURBBi : case AArch64 :: STURHHi : case AArch64 :: STURWi : case AArch64 :: STRWpre : case AArch64 :: STURXi : case AArch64 :: STRXpre : case AArch64 :: LDURSi : case AArch64 :: LDRSpre : case AArch64 :: LDURDi : case AArch64 :: LDRDpre : case AArch64 :: LDURQi : case AArch64 :: LDRQpre : case AArch64 :: LDURWi : case AArch64 :: LDRWpre : case AArch64 :: LDURXi : case AArch64 :: LDRXpre : case AArch64 :: LDURSWi : case AArch64 :: LDURHHi : case AArch64 :: LDURBBi : case AArch64 :: LDURSBWi : case AArch64 :: LDURSHWi : return true ; } } </s>

Return true if it has an unscaled load/store offset .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool arm_frame_pointer_required ( void ) { return ( cfun -> has_nonlocal_label || SUBTARGET_FRAME_POINTER_REQUIRED || ( TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ( ) ) ) ; } </s>


<s> void arm_reset_previous_fndecl ( void ) { arm_previous_fndecl = NULL_TREE ; } </s>


<s> void reset ( ) override { MappingSymbolCounter = 0 ; State = EMS_None ; MCELFStreamer :: reset ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool MipsTargetLowering :: IsGlobalInSmallSection ( GlobalValue * GV ) { const TargetData * TD = getTargetData ( ) ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypePaddedSize ( Ty ) ; if ( GVA -> hasInitializer ( ) && GV -> hasLocalLinkage ( ) ) { Constant * C = GVA -> getInitializer ( ) ; const ConstantArray * CVA = dyn_cast < ConstantArray > ( C ) ; if ( CVA && CVA -> isCString ( ) ) return false ; } return IsInSmallSection ( Size ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> virtual void EmitInstruction ( const MCInst & Inst ) { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static std :: unique_ptr < Cpu0Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = make_unique < Cpu0Operand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static tree arm_extract_valist_ptr ( tree valist ) { if ( TREE_TYPE ( valist ) == error_mark_node ) return error_mark_node ; if ( TARGET_AAPCS_BASED ) { tree ap_field = TYPE_FIELDS ( TREE_TYPE ( valist ) ) ; valist = build3 ( COMPONENT_REF , TREE_TYPE ( ap_field ) , valist , ap_field , NULL_TREE ) ; } return valist ; } </s>

Return an expression of type `` void * '' pointing to the next available argument in a variable-argument list . VALIST is the user-level va_list object , of type __builtin_va_list .


<s> static bool expand_vec_perm_identity ( struct expand_vec_perm_d * d ) { unsigned i , nelt = d -> nelt ; for ( i = 0 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != i ) return false ; if ( ! d -> testing_p ) emit_move_insn ( d -> target , d -> op0 ) ; return true ; } </s>


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP && CS != X86 :: RSP && CS != X86 :: ESP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TII = static_cast < const AArch64InstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86TargetLowering :: isFsqrtCheap ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getScalarType ( ) == MVT :: f16 ) return true ; if ( DAG . getNodeIfExists ( X86ISD :: FRSQRT , DAG . getVTList ( VT ) , Op ) ) return false ; if ( VT . isVector ( ) ) return Subtarget . hasFastVectorFSQRT ( ) ; return Subtarget . hasFastScalarFSQRT ( ) ; } </s>

Return true if SQRT ( X ) should n't be replaced with X * RSQRT ( X ) .


<s>
SDValue
ARMTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
Subtarget
->
isTargetDarwin
(
)
LowerGlobalAddressDarwin
(
Op
,
DAG
)
:
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
,
Subtarget
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
LowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
,
VarArgsFrameIndex
)
;
case
ISD
::
SINT_TO_FP
:
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
)
;
case
ISD
::
FP_TO_SINT
:
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
)
;
case
ISD
::
FCOPYSIGN
:
return
LowerFCOPYSIGN
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
break
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
return
LowerGLOBAL_OFFSET_TABLE
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_VOID
:
case
ISD
::
INTRINSIC_W_CHAIN
:
return
LowerINTRINSIC_W_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
LowerINTRINSIC_WO_CHAIN
(
Op
,
DAG
)
;
case
ISD
::
BIT_CONVERT
:
return
ExpandBIT_CONVERT
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShift
(
Op
.
getNode
(
)
,
DAG
,
Subtarget
)
;
case
ISD
::
VSETCC
:
return
LowerVSETCC
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
case
ISD
::
SCALAR_TO_VECTOR
:
return
LowerSCALAR_TO_VECTOR
(
Op
,
DAG
)
;
case
ISD
::
EXTRACT_VECTOR_ELT
:
return
LowerEXTRACT_VECTOR_ELT
(
Op
,
DAG
)
;
case
ISD
::
CONCAT_VECTORS
:
return
LowerCONCAT_VECTORS
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> TargetTransformInfo X86TargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( X86TTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> bool ConstantPool :: empty ( ) { return Entries . empty ( ) ; } </s>

Determine whether this version information is empty ( e.g. , all version components are zero ) .


<s> bool GeneralShuffle :: add ( SDValue Op , unsigned Elem ) { unsigned BytesPerElement = VT . getVectorElementType ( ) . getStoreSize ( ) ; EVT FromVT = Op . getNode ( ) ? Op . getValueType ( ) : VT ; unsigned FromBytesPerElement = FromVT . getVectorElementType ( ) . getStoreSize ( ) ; if ( FromBytesPerElement < BytesPerElement ) return false ; unsigned Byte = ( ( Elem * FromBytesPerElement ) % SystemZ :: VectorBytes + ( FromBytesPerElement - BytesPerElement ) ) ; while ( Op . getNode ( ) ) { if ( Op . getOpcode ( ) == ISD :: BITCAST ) Op = Op . getOperand ( 0 ) ; else if ( Op . getOpcode ( ) == ISD :: VECTOR_SHUFFLE && Op . hasOneUse ( ) ) { SmallVector < int , SystemZ :: VectorBytes > OpBytes ; getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , OpBytes ) ; int NewByte ; if ( ! getShuffleInput ( OpBytes , Byte , BytesPerElement , NewByte ) ) break ; if ( NewByte < 0 ) { addUndef ( ) ; return true ; } Op = Op . getOperand ( unsigned ( NewByte ) / SystemZ :: VectorBytes ) ; Byte = unsigned ( NewByte ) % SystemZ :: VectorBytes ; } else if ( Op . isUndef ( ) ) { addUndef ( ) ; return true ; } else break ; } unsigned OpNo = 0 ; for ( ; OpNo < Ops . size ( ) ; ++ OpNo ) if ( Ops [ OpNo ] == Op ) break ; if ( OpNo == Ops . size ( ) ) Ops . push_back ( Op ) ; unsigned Base = OpNo * SystemZ :: VectorBytes + Byte ; for ( unsigned I = 0 ; I < BytesPerElement ; ++ I ) Bytes . push_back ( Base + I ) ; return true ; } </s>


<s> static void aarch64_emit_store_exclusive ( machine_mode mode , rtx bval , rtx rval , rtx mem , rtx model_rtx ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; switch ( mode ) { case QImode : gen = gen_aarch64_store_exclusiveqi ; break ; case HImode : gen = gen_aarch64_store_exclusivehi ; break ; case SImode : gen = gen_aarch64_store_exclusivesi ; break ; case DImode : gen = gen_aarch64_store_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( bval , rval , mem , model_rtx ) ) ; } </s>


<s> bool X86PassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>


<s> bool MipsTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT != MVT :: f32 && VT != MVT :: f64 ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

"immediate operand must be in the range [0,15]"


<s> static void update_set_flags ( rtx x , struct reg_flags * pflags ) { rtx src = SET_SRC ( x ) ; switch ( GET_CODE ( src ) ) { case CALL : return ; case IF_THEN_ELSE : return ; default : if ( COMPARISON_P ( src ) && SCALAR_FLOAT_MODE_P ( GET_MODE ( XEXP ( src , 0 ) ) ) ) pflags -> is_fp = 1 ; else if ( GET_CODE ( src ) == AND ) pflags -> is_and = 1 ; else if ( GET_CODE ( src ) == IOR ) pflags -> is_or = 1 ; break ; } } </s>

Examine X , which is a SET rtx , and update the flags , the predicate , and the condition , stored in * PFLAGS , * PPRED and * PCOND .


<s>
static
tree
ix86_build_builtin_va_list
(
void
)
{
if
(
TARGET_64BIT
)
{
sysv_va_list_type_node
=
ix86_build_builtin_va_list_64
(
)
;
tree
char_ptr_type
=
build_pointer_type
(
char_type_node
)
;
tree
attr
=
tree_cons
(
get_identifier
(
"ms_abi va_list"
)
,
NULL_TREE
,
TYPE_ATTRIBUTES
(
char_ptr_type
)
)
;
ms_va_list_type_node
=
build_type_attribute_variant
(
char_ptr_type
,
attr
)
;
return
(
(
ix86_abi
==
MS_ABI
)
ms_va_list_type_node
:
sysv_va_list_type_node
)
;
}
else
{
return
build_pointer_type
(
char_type_node
)
;
}
}
</s>


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> bool aarch_mm_needs_acquire ( rtx const_int ) { enum memmodel model = memmodel_from_int ( INTVAL ( const_int ) ) ; return ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_release ( model ) ) ; } </s>

Return non-zero if the RTX representing a memory model is a memory model that needs acquire semantics .


<s> bool AArch64PagerandoOptimizer :: runOnMachineFunction ( MachineFunction & MF ) { auto & F = MF . getFunction ( ) ; if ( ! F . isPagerando ( ) || skipFunction ( F ) ) { return false ; } auto BinPrefix = F . getSectionPrefix ( ) . getValue ( ) ; std :: vector < MachineInstr * > Worklist ; for ( auto & BB : MF ) { for ( auto & MI : BB ) { if ( isIntraBin ( MI , BinPrefix ) ) Worklist . push_back ( & MI ) ; } } for ( auto * MI : Worklist ) optimizeCalls ( MI ) ; return ! Worklist . empty ( ) ; } </s>


<s>
void
SICDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

SIC
SIC
"Selecting: "
"\n"
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
ExpandVectorExtension
(
N
,
DAG
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
ATOMIC_LOAD_ADD
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMADD64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_AND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_NAND
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMNAND64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_OR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_SUB
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSUB64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_XOR
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMXOR64_DAG
)
;
return
;
case
ISD
::
ATOMIC_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMSWAP64_DAG
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMCMPXCHG64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMIN
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMIN64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_MAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMMAX64_DAG
)
;
return
;
case
ISD
::
ATOMIC_LOAD_UMAX
:
ReplaceATOMIC_OP_64
(
N
,
Results
,
DAG
,
ARMISD
::
ATOMUMAX64_DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool ARMBaseInstrInfo :: areLoadsFromSameBasePtr ( SDNode * Load1 , SDNode * Load2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; if ( ! Load1 -> isMachineOpcode ( ) || ! Load2 -> isMachineOpcode ( ) ) return false ; switch ( Load1 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } switch ( Load2 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } if ( Load1 -> getOperand ( 0 ) != Load2 -> getOperand ( 0 ) || Load1 -> getOperand ( 4 ) != Load2 -> getOperand ( 4 ) ) return false ; if ( Load1 -> getOperand ( 3 ) != Load2 -> getOperand ( 3 ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; return true ; } return false ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s> const X86InstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) -> getInstrInfo ( ) ; } </s>


<s> char * csky_output_call ( rtx * operands , int index ) { static char buffer [ 20 ] ; rtx addr = operands [ index ] ; if ( REG_P ( addr ) ) sprintf ( buffer , "jsr\t%%%d" , index ) ; else if ( flag_pic && ( GET_CODE ( addr ) == UNSPEC ) ) sprintf ( buffer , "bsr\t%%%d" , index ) ; else sprintf ( buffer , "jbsr\t%%%d" , index ) ; return buffer ; } </s>

Functions to output assembly code for a function call .

csky 20 "jsr\t%%%d" "bsr\t%%%d" "jbsr\t%%%d"


<s> int fmpyaddoperands ( rtx * operands ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( ! ( mode == GET_MODE ( operands [ 1 ] ) && mode == GET_MODE ( operands [ 2 ] ) && mode == GET_MODE ( operands [ 3 ] ) && mode == GET_MODE ( operands [ 4 ] ) && mode == GET_MODE ( operands [ 5 ] ) ) ) return 0 ; if ( ! ( GET_CODE ( operands [ 1 ] ) == REG && GET_CODE ( operands [ 2 ] ) == REG && GET_CODE ( operands [ 3 ] ) == REG && GET_CODE ( operands [ 4 ] ) == REG && GET_CODE ( operands [ 5 ] ) == REG ) ) return 0 ; if ( ! rtx_equal_p ( operands [ 3 ] , operands [ 4 ] ) && ! rtx_equal_p ( operands [ 3 ] , operands [ 5 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 3 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 1 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 2 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 4 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 5 ] , operands [ 0 ] ) ) return 0 ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ 0 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 1 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 2 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 3 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 4 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 5 ] ) ) != FPUPPER_REGS ) ) return 0 ; return 1 ; } </s>

Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpyadd instructions .


<s> bool X86AsmParser :: processInstruction ( MCInst & Inst , const OperandVector & Ops ) { return false ; } </s>

Process a single instruction and collect debug info anchors .


<s> void CSKYFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { CSKYMachineFunctionInfo * CFI = MF . getInfo < CSKYMachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = CSKY :: R14 ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; } const auto & CSI = MFI . getCalleeSavedInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; if ( hasFP ( MF ) ) { const CSKYInstrInfo * TII = STI . getInstrInfo ( ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ; } else { adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ; } adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ; } </s>


<s> bool mep_emit_intrinsic ( int intrinsic , const rtx * operands ) { const struct cgen_insn * cgen_insn ; const struct insn_data_d * idata ; rtx newop [ 10 ] ; int i ; if ( ! mep_get_intrinsic_insn ( intrinsic , & cgen_insn ) ) return false ; idata = & insn_data [ cgen_insn -> icode ] ; for ( i = 0 ; i < idata -> n_operands ; i ++ ) { newop [ i ] = mep_convert_arg ( idata -> operand [ i ] . mode , operands [ i ] ) ; if ( ! idata -> operand [ i ] . predicate ( newop [ i ] , idata -> operand [ i ] . mode ) ) return false ; } emit_insn ( idata -> genfun ( newop [ 0 ] , newop [ 1 ] , newop [ 2 ] , newop [ 3 ] , newop [ 4 ] , newop [ 5 ] , newop [ 6 ] , newop [ 7 ] , newop [ 8 ] ) ) ; return true ; } </s>

Try to instantiate INTRINSIC with the operands given in OPERANDS . Return true on success . This function can fail if the intrinsic is unavailable or if the operands do n't satisfy their predicates .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static short find_set_regmode_weight ( rtx x , enum machine_mode mode ) { if ( GET_CODE ( x ) == CLOBBER && register_operand ( SET_DEST ( x ) , mode ) ) return 1 ; if ( GET_CODE ( x ) == SET && register_operand ( SET_DEST ( x ) , mode ) ) { if ( GET_CODE ( SET_DEST ( x ) ) == REG ) { if ( ! reg_mentioned_p ( SET_DEST ( x ) , SET_SRC ( x ) ) ) return 1 ; else return 0 ; } return 1 ; } return 0 ; } </s>


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static int distance_agu_use_in_bb ( unsigned int regno , rtx_insn * insn , int distance , rtx_insn * start , bool * found , bool * redefined ) { basic_block bb = NULL ; rtx_insn * next = start ; rtx_insn * prev = NULL ; * found = false ; * redefined = false ; if ( start != NULL_RTX ) { bb = BLOCK_FOR_INSN ( start ) ; if ( start != BB_HEAD ( bb ) ) prev = insn ; } while ( next && next != insn && distance < LEA_SEARCH_THRESHOLD ) { if ( NONDEBUG_INSN_P ( next ) && NONJUMP_INSN_P ( next ) ) { distance = increase_distance ( prev , next , distance ) ; if ( insn_uses_reg_mem ( regno , next ) ) { * found = true ; return distance ; } if ( insn_defines_reg ( regno , INVALID_REGNUM , next ) ) { * redefined = true ; return - 1 ; } prev = next ; } if ( next == BB_END ( bb ) ) break ; next = NEXT_INSN ( next ) ; } return distance ; } </s>

Return the distance in half-cycles between INSN and the next insn that uses register number REGNO in memory address added to DISTANCE . Return -1 if REGNO0 is set . Put true value into * FOUND if register usage was found and false otherwise . Put true value into * REDEFINED if register redefinition was found and false otherwise .


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; else if ( RC == & PPC :: F4RCRegClass && Subtarget . hasP8Vector ( ) ) return & PPC :: VSSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC , MF ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass PPC::F4RCRegClass PPC::VSSRCRegClass


<s> outliner :: InstrType X86InstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MIT , unsigned Flags ) const { MachineInstr & MI = * MIT ; if ( MI . isDebugInstr ( ) || MI . isIndirectDebugValue ( ) ) return outliner :: InstrType :: Invisible ; if ( MI . isKill ( ) ) return outliner :: InstrType :: Invisible ; if ( isTailCall ( MI ) ) return outliner :: InstrType :: Legal ; if ( MI . isTerminator ( ) || MI . isReturn ( ) ) { if ( MI . getParent ( ) -> succ_empty ( ) ) return outliner :: InstrType :: Legal ; return outliner :: InstrType :: Illegal ; } if ( MI . modifiesRegister ( X86 :: RSP , & RI ) || MI . readsRegister ( X86 :: RSP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RSP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RSP ) ) return outliner :: InstrType :: Illegal ; if ( MI . readsRegister ( X86 :: RIP , & RI ) || MI . getDesc ( ) . hasImplicitUseOfPhysReg ( X86 :: RIP ) || MI . getDesc ( ) . hasImplicitDefOfPhysReg ( X86 :: RIP ) ) return outliner :: InstrType :: Illegal ; if ( MI . isPosition ( ) ) return outliner :: InstrType :: Illegal ; for ( const MachineOperand & MOP : MI . operands ( ) ) if ( MOP . isCPI ( ) || MOP . isJTI ( ) || MOP . isCFIIndex ( ) || MOP . isFI ( ) || MOP . isTargetIndex ( ) ) return outliner :: InstrType :: Illegal ; return outliner :: InstrType :: Legal ; } </s>

Returns how or if MIT should be outlined .


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { return & SystemZ :: ADDR64BitRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
static
void
replace_swap_with_copy
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
copy
=
gen_rtx_SET
(
SET_DEST
(
body
)
,
src_reg
)
;
rtx_insn
*
new_insn
=
emit_insn_before
(
copy
,
insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
insn
)
)
;
df_insn_rescan
(
new_insn
)
;
if
(
dump_file
)
{
unsigned
int
new_uid
=
INSN_UID
(
new_insn
)
;
fprintf
(
dump_file
,
"Replacing swap %d with copy %d\n"
,
i
,
new_uid
)
;
}
df_insn_delete
(
insn
)
;
remove_insn
(
insn
)
;
insn
->
set_deleted
(
)
;
}
</s>

Find the insn from the Ith table entry , which is known to be a register swap Y = SWAP ( X ) . Replace it with a copy Y = X .

powerpcspe
0
"Replacing swap %d with copy %d\n"


<s> static bool reg_offset_addressing_ok_p ( machine_mode mode ) { switch ( mode ) { case E_V16QImode : case E_V8HImode : case E_V4SFmode : case E_V4SImode : case E_V2DFmode : case E_V2DImode : case E_V1TImode : case E_TImode : case E_TFmode : case E_KFmode : if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) ) return mode_supports_dq_form ( mode ) ; break ; case E_OOmode : case E_XOmode : return TARGET_MMA ; case E_SDmode : if ( TARGET_NO_SDMODE_STACK ) return false ; break ; default : break ; } return true ; } </s>

Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p .


<s> static rtx sh_function_arg ( cumulative_args_t ca_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( mode == VOIDmode ) return ca -> renesas_abi ? const1_rtx : const0_rtx ; if ( sh_pass_in_reg_p ( * ca , mode , type ) && ( named || ! ( TARGET_HITACHI || ca -> renesas_abi ) ) ) { int regno ; if ( mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ( ! FUNCTION_ARG_SCmode_WART || ( sh_round_reg ( * ca , mode ) & 1 ) ) ) { rtx r1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( sh_round_reg ( * ca , mode ) ^ 1 ) ) , const0_rtx ) ; rtx r2 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SFmode , BASE_ARG_REG ( mode ) + ( ( sh_round_reg ( * ca , mode ) + 1 ) ^ 1 ) ) , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( SCmode , gen_rtvec ( 2 , r1 , r2 ) ) ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && ca -> free_single_fp_reg && mode == SFmode ) return gen_rtx_REG ( mode , ca -> free_single_fp_reg ) ; regno = ( BASE_ARG_REG ( mode ) + sh_round_reg ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } return NULL_RTX ; } </s>

Define where to put the arguments to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On SH the first args are normally in registers and the rest are pushed . Any arg that starts within the first NPARM_REGS words is at least partially passed in a register unless its data type forbids .


<s> bool AArch64LowerHomogeneousPE :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= runOnMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameDestroy ) ; ++ MI ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void print ( raw_ostream & OS ) const override { } </s>

print - Print a debug representation of the operand to the given stream .


<s> void MipsAsmPrinter :: emitStartOfAsmFile ( Module & M ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; TS . setPic ( OutContext . getObjectFileInfo ( ) -> isPositionIndependent ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = MIPS_MC :: selectMipsCPU ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const MipsTargetMachine & MTM = static_cast < const MipsTargetMachine & > ( TM ) ; const MipsSubtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM , None ) ; bool IsABICalls = STI . isABICalls ( ) ; const MipsABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; if ( ! isPositionIndependent ( ) && STI . hasSym32 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( ".mdebug." ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , 0 ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; TS . updateABIInfo ( STI ) ; if ( ( ABI . IsO32 ( ) && ( STI . isABI_FPXX ( ) || STI . isFP64bit ( ) ) ) || STI . useSoftFloat ( ) ) TS . emitDirectiveModuleFP ( ) ; if ( ABI . IsO32 ( ) && ( ! STI . useOddSPReg ( ) || STI . isABI_FPXX ( ) ) ) TS . emitDirectiveModuleOddSPReg ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .

Mips Mips Mips MIPS_MC::selectMipsCPU Mips Mips Mips Mips ".mdebug." 0


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const outliner :: TargetCostInfo & TCI ) const { if ( TCI . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s>
char
*
crx_prepare_push_pop_string
(
int
push_or_pop
)
{
static
char
mask_str
[
50
]
;
int
i
=
0
;
int
ra_in_bitmask
=
0
;
char
*
return_str
;
char
*
temp_str
;
return_str
=
(
char
*
)
xmalloc
(
120
)
;
temp_str
=
(
char
*
)
xmalloc
(
120
)
;
memset
(
return_str
,
0
,
3
)
;
while
(
i
<=
last_reg_to_save
)
{
mask_str
[
0
]
=
0
;
if
(
i
<=
SP_REGNUM
)
{
int
j
=
0
;
while
(
j
<
MAX_COUNT
&&
i
<=
SP_REGNUM
)
{
if
(
save_regs
[
i
]
)
{
if
(
i
==
RETURN_ADDRESS_REGNUM
)
ra_in_bitmask
=
1
;
if
(
j
>
0
)
strcat
(
mask_str
,
", "
)
;
strcat
(
mask_str
,
reg_names
[
i
]
)
;
++
j
;
}
++
i
;
}
}
else
{
while
(
i
<=
last_reg_to_save
)
{
if
(
save_regs
[
i
]
)
{
strcat
(
mask_str
,
"lo, hi"
)
;
i
=
last_reg_to_save
+
1
;
break
;
}
++
i
;
}
}
if
(
strlen
(
mask_str
)
==
0
)
continue
;
if
(
push_or_pop
==
1
)
{
if
(
crx_interrupt_function_p
(
)
)
mpushpop_str
(
temp_str
,
"popx"
,
mask_str
)
;
else
{
if
(
ra_in_bitmask
)
{
mpushpop_str
(
temp_str
,
"popret"
,
mask_str
)
;
ra_in_bitmask
=
0
;
}
else
mpushpop_str
(
temp_str
,
"pop"
,
mask_str
)
;
}
strcat
(
return_str
,
temp_str
)
;
}
else
{
if
(
crx_interrupt_function_p
(
)
)
mpushpop_str
(
temp_str
,
"pushx"
,
mask_str
)
;
else
mpushpop_str
(
temp_str
,
"push"
,
mask_str
)
;
strcat
(
temp_str
,
return_str
)
;
strcpy
(
strcat
(
return_str
,
"\t"
)
,
temp_str
)
;
}
}
if
(
push_or_pop
==
1
)
{
if
(
crx_interrupt_function_p
(
)
)
strcat
(
return_str
,
"\n\tretx\n"
)
;
else
if
(
!
FUNC_IS_NORETURN_P
(
current_function_decl
)
&&
!
save_regs
[
RETURN_ADDRESS_REGNUM
]
)
strcat
(
return_str
,
"\n\tjump\tra\n"
)
;
}
return_str
+=
2
;
return
return_str
;
}
</s>

Called from crx.md . The return value depends on the parameter push_or_pop : * When push_or_pop is zero - > string for push instructions of prologue . * When push_or_pop is nonzero - > string for pop/popret/retx in epilogue . * Relies on the assumptions : * 1 . RA is the last register to be saved . * 2 . The maximal value of the counter is MAX_COUNT .


"Unable to create a unique discriminator "

"for instruction with memory operand in: "

". This is likely due to a large macro expansion. \n"

"New discriminator shouldn't be present in set"


"passing %qT to argument %d of %qE, which"

" expects a vector of unsigned integers"

Like infer_vector_type , but also require the type to be an unsigned integer .


<s> int arm_const_double_rtx ( rtx x ) { REAL_VALUE_TYPE r ; int i ; if ( ! fp_consts_inited ) init_fp_table ( ) ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return 0 ; for ( i = 0 ; i < fp_consts_inited ; i ++ ) if ( REAL_VALUES_EQUAL ( r , values_fp [ i ] ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FP constant .


<s> static bool multiple_operation_profitable_p ( bool is_store ATTRIBUTE_UNUSED , int nops , HOST_WIDE_INT add_offset ) { if ( nops == 2 && arm_ld_sched && add_offset != 0 ) return false ; if ( nops <= 2 && arm_tune_xscale && ! optimize_size ) return false ; return true ; } </s>

Return true iff it would be profitable to turn a sequence of NOPS loads or stores ( depending on IS_STORE ) into a load-multiple or store-multiple instruction . ADD_OFFSET is nonzero if the base address register needs to be modified with an add instruction before we can use it .


"Can't break virtual register dependencies."

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> void fma_node :: add_child ( fma_node * child ) { this -> m_children -> push_back ( child ) ; } </s>

Add a child to this node in the list of children .


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool LEGFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> const TargetRegisterClass * X86RegisterInfo :: getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned SubIdx ) const { if ( ! Is64Bit && SubIdx == X86 :: sub_8bit ) { A = X86GenRegisterInfo :: getSubClassWithSubReg ( A , X86 :: sub_8bit_hi ) ; if ( ! A ) return 0 ; } return X86GenRegisterInfo :: getMatchingSuperRegClass ( A , B , SubIdx ) ; } </s>

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B .


<s>
void
emitValueImpl
(
const
MCExpr
*
Value
,
unsigned
Size
,
SMLoc
Loc
)
override
{
if
(
const
MCSymbolRefExpr
*
SRE
=
dyn_cast_or_null
<
MCSymbolRefExpr
>
(
Value
)
)
{
if
(
SRE
->
getKind
(
)
==
MCSymbolRefExpr
::
VK_ARM_SBREL
&&
!
(
Size
==
4
)
)
{
getContext
(
)
.
reportError
(
Loc
,
"relocated expression must be 32-bit"
)
;
return
;
}
getOrCreateDataFragment
(
)
;
}
emitDataMappingSymbol
(
)
;
MCELFStreamer
::
emitValueImpl
(
Value
,
Size
,
Loc
)
;
}
</s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .

ARM
ARM
4
"relocated expression must be 32-bit"


<s> unsigned getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , AArch64 :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) . getReg ( 0 ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 1 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> void MipsTargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( 16u , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( 16u , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( 16u , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . emitCodeAlignment ( Alignment , Alignment ) ; else OS . emitValueToAlignment ( Alignment , 0 , 1 , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ; if ( Features [ Mips :: FeatureGP64Bit ] ) { if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_32BITMODE ; } else if ( Features [ Mips :: FeatureMips64r2 ] || Features [ Mips :: FeatureMips64 ] ) EFlags |= ELF :: EF_MIPS_32BITMODE ; if ( ! Features [ Mips :: FeatureNoABICalls ] ) EFlags |= ELF :: EF_MIPS_CPIC ; if ( Pic ) EFlags |= ELF :: EF_MIPS_PIC | ELF :: EF_MIPS_CPIC ; if ( getABI ( ) . IsCheriPureCap ( ) ) EFlags |= ELF :: EF_MIPS_ABI_CHERIABI ; MCA . setELFHeaderEFlags ( EFlags ) ; MipsELFStreamer & MEF = static_cast < MipsELFStreamer & > ( Streamer ) ; MEF . EmitMipsOptionRecords ( ) ; emitMipsAbiFlags ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> static unsigned int rs6000_parm_offset ( void ) { return ( DEFAULT_ABI == ABI_V4 ? 2 : DEFAULT_ABI == ABI_ELFv2 ? 4 : 6 ) ; } </s>

The offset in words to the start of the parameter save area .


<s> bool X86TargetLowering :: isCheapToSpeculateCttz ( ) const { return Subtarget . hasBMI ( ) ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> bool SSACCmpConv :: isDeadDef ( unsigned DstReg ) { if ( DstReg == ARM64 :: WZR || DstReg == ARM64 :: XZR ) return true ; if ( ! TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) return false ; return MRI -> use_nodbg_empty ( DstReg ) ; } </s>

Return true if this instruction has a dead def .


<s> bool X86TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { return true ; } </s>

Return if the target supports combining a chain like :


<s>
void
ARMTargetLowering
::
HandleByVal
(
CCState
*
State
,
unsigned
&
size
,
unsigned
Align
)
const
{
unsigned
reg
=
State
->
AllocateReg
(
GPRArgRegs
,
4
)
;
assert
(
(
State
->
getCallOrPrologue
(
)
==
Prologue
||
State
->
getCallOrPrologue
(
)
==
Call
)
&&
"unhandled ParmContext"
)
;
if
(
(
ARM
::
R0
<=
reg
)
&&
(
reg
<=
ARM
::
R3
)
)
{
if
(
Subtarget
->
isAAPCS_ABI
(
)
&&
Align
>
4
)
{
unsigned
AlignInRegs
=
Align
/
4
;
unsigned
Waste
=
(
ARM
::
R4
reg
)
%
AlignInRegs
;
for
(
unsigned
i
=
0
;
i
<
Waste
;
++
i
)
reg
=
State
->
AllocateReg
(
GPRArgRegs
,
4
)
;
}
if
(
reg
!=
0
)
{
unsigned
excess
=
4
*
(
ARM
::
R4
reg
)
;
const
unsigned
NSAAOffset
=
State
->
getNextStackOffset
(
)
;
if
(
Subtarget
->
isAAPCS_ABI
(
)
&&
NSAAOffset
!=
0
&&
size
>
excess
)
{
while
(
State
->
AllocateReg
(
GPRArgRegs
,
4
)
)
;
return
;
}
unsigned
ByValRegBegin
=
reg
;
unsigned
ByValRegEnd
=
(
size
<
excess
)
reg
+
size
/
4
:
(
unsigned
)
ARM
::
R4
;
State
->
addInRegsParamInfo
(
ByValRegBegin
,
ByValRegEnd
)
;
for
(
unsigned
i
=
reg
+
1
;
i
!=
ByValRegEnd
;
++
i
)
State
->
AllocateReg
(
GPRArgRegs
,
4
)
;
if
(
size
<
excess
)
size
=
0
;
else
size
-=
excess
;
}
}
}
</s>

Target-specific cleanup for formal ByVal parameters .


<s> void CSKYELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; LSDAEncoding = dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; PersonalityEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; TTypeEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; } </s>

This method must be called before any actual lowering is done .


<s> rtx mips_gen_const_int_vector ( machine_mode mode , HOST_WIDE_INT val ) { rtx c = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; return gen_const_vec_duplicate ( mode , c ) ; } </s>

Return a const_int vector of VAL with mode MODE .


<s>
void
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> void MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; addPass ( createMipsHazardSchedule ( ) ) ; addPass ( createMipsLongBranchPass ( TM ) ) ; addPass ( createMipsConstantIslandPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


"// ia64_dfa_sched_reorder (type %d):\n"

We are about to being issuing insns for this clock cycle . Override the default sort algorithm to better slot instructions .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { unsigned Align = Subtarget . isPPC64 ( ) ? 8 : 4 ; if ( Subtarget . hasAltivec ( ) || Subtarget . hasQPX ( ) ) getMaxByValAlign ( Ty , Align , Subtarget . hasQPX ( ) ? 32 : 16 ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


"Odd number of callee-saved regs to spill!"

"Expected GPR64 callee-saved register pair!"

"Expected FPR64 callee-saved register pair!"

"Offset out of bounds for LDP immediate"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
unsigned
MipsOutgoingValueHandler
::
assignCustomValue
(
CallLowering
::
ArgInfo
&
Arg
,
ArrayRef
<
CCValAssign
>
VAs
)
{
const
CCValAssign
&
VALo
=
VAs
[
0
]
;
const
CCValAssign
&
VAHi
=
VAs
[
1
]
;
assert
(
VALo
.
getLocVT
(
)
==
MVT
::
i32
&&
VAHi
.
getLocVT
(
)
==
MVT
::
i32
&&
VALo
.
getValVT
(
)
==
MVT
::
f64
&&
VAHi
.
getValVT
(
)
==
MVT
::
f64
&&
"unexpected custom value"
)
;
auto
Unmerge
=
MIRBuilder
.
buildUnmerge
(
{
LLT
::
scalar
(
32
)
,
LLT
::
scalar
(
32
)
}
,
Arg
.
Regs
[
0
]
)
;
Register
Lo
=
Unmerge
.
getReg
(
0
)
;
Register
Hi
=
Unmerge
.
getReg
(
1
)
;
Arg
.
OrigRegs
.
assign
(
Arg
.
Regs
.
begin
(
)
,
Arg
.
Regs
.
end
(
)
)
;
Arg
.
Regs
=
{
Lo
,
Hi
}
;
if
(
!
STI
.
isLittle
(
)
)
std
::
swap
(
Lo
,
Hi
)
;
MIRBuilder
.
buildCopy
(
VALo
.
getLocReg
(
)
,
Lo
)
;
MIRBuilder
.
buildCopy
(
VAHi
.
getLocReg
(
)
,
Hi
)
;
return
2
;
}
</s>

Handle custom values , which may be passed into one or more of VAs .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
void
pa_asm_output_aligned_bss
(
FILE
*
stream
,
const
char
*
name
,
unsigned
HOST_WIDE_INT
size
,
unsigned
int
align
)
{
switch_to_section
(
bss_section
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_TYPE_DIRECTIVE
(
stream
,
name
,
"object"
)
;
ASM_OUTPUT_SIZE_DIRECTIVE
(
stream
,
name
,
size
)
;
fprintf
(
stream
,
"\t.align %u\n"
,
align
/
BITS_PER_UNIT
)
;
ASM_OUTPUT_LABEL
(
stream
,
name
)
;
fprintf
(
stream
,
"\t.block "
HOST_WIDE_INT_PRINT_UNSIGNED
"\n"
,
size
)
;
}
</s>

This function places uninitialized global data in the bss section . The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this function on the SOM port to prevent uninitialized global data from being placed in the data section .

pa
"\t.align %u\n"
"object"
"\t.align %u\n"
"\t.block "
"\n"


<s> int d30v_trampoline_size ( ) { return 16 ; } </s>

A C expression for the size in bytes of the trampoline , as an integer .


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CalleeSavedRegs [ ] = { SystemZ :: R6D , SystemZ :: R7D , SystemZ :: R8D , SystemZ :: R9D , SystemZ :: R10D , SystemZ :: R11D , SystemZ :: R12D , SystemZ :: R13D , SystemZ :: R14D , SystemZ :: R15D , SystemZ :: F8D , SystemZ :: F9D , SystemZ :: F10D , SystemZ :: F11D , SystemZ :: F12D , SystemZ :: F13D , SystemZ :: F14D , SystemZ :: F15D , 0 } ; return CalleeSavedRegs ; } </s>


<s> static bool pa_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( from == to ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return false ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return false ; return true ; } </s>


<s> static bool aarch64_evpc_rev_global ( struct expand_vec_perm_d * d ) { poly_uint64 nelt = d -> perm . length ( ) ; if ( ! d -> one_vector_p || d -> vec_flags != VEC_SVE_DATA ) return false ; if ( ! d -> perm . series_p ( 0 , 1 , nelt - 1 , - 1 ) ) return false ; if ( d -> testing_p ) return true ; rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , UNSPEC_REV ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV insn , which reverses elements within a full vector .


<s> static void mips_multi_add_label ( const char * label ) { struct mips_multi_member * member ; member = mips_multi_add ( ) ; member -> is_label_p = true ; member -> format = label ; } </s>

Add the given label definition to the current multi-insn sequence . The definition should include the colon .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

"incompatible options %<-mstack-protector-guard=global%> and "

Reset options between modes that the user has specified .


<s> unsigned getReturnSaveOffset ( ) const { return ReturnSaveOffset ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> static void ix86_recompute_optlev_based_flags ( struct gcc_options * opts , struct gcc_options * opts_set ) { if ( TARGET_64BIT_P ( opts -> x_ix86_isa_flags ) ) { if ( opts -> x_optimize >= 1 ) SET_OPTION_IF_UNSET ( opts , opts_set , flag_omit_frame_pointer , ! USE_IX86_FRAME_POINTER ) ; if ( opts -> x_flag_asynchronous_unwind_tables && TARGET_64BIT_MS_ABI ) SET_OPTION_IF_UNSET ( opts , opts_set , flag_unwind_tables , 1 ) ; if ( opts -> x_flag_asynchronous_unwind_tables == 2 ) opts -> x_flag_unwind_tables = opts -> x_flag_asynchronous_unwind_tables = 1 ; if ( opts -> x_flag_pcc_struct_return == 2 ) opts -> x_flag_pcc_struct_return = 0 ; } else { if ( opts -> x_optimize >= 1 ) SET_OPTION_IF_UNSET ( opts , opts_set , flag_omit_frame_pointer , ! ( USE_IX86_FRAME_POINTER || opts -> x_optimize_size ) ) ; if ( opts -> x_flag_asynchronous_unwind_tables == 2 ) opts -> x_flag_asynchronous_unwind_tables = ! USE_IX86_FRAME_POINTER ; if ( opts -> x_flag_pcc_struct_return == 2 ) { if ( TARGET_IAMCU_P ( opts -> x_target_flags ) ) opts -> x_flag_pcc_struct_return = 0 ; else opts -> x_flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN ; } } } </s>

( Re ) compute option overrides affected by optimization levels in target-specific ways .


<s> MCSection * getNonexecutableStackSection ( MCContext & Ctx ) const override { return nullptr ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tRestore
0


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"-mslow-flash-data only supports non-pic code on armv7-m targets"

Check any incompatible options that the user has specified .


<s> bool aarch64_sve_float_arith_immediate_p ( rtx x , bool negate_p ) { rtx elt ; REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || GET_CODE ( elt ) != CONST_DOUBLE ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ; if ( real_equal ( & r , & dconsthalf ) ) return true ; return false ; } </s>

Return true if X is a valid immediate operand for an SVE FADD or FSUB instruction . Negate X first if NEGATE_P is true .


<s> void function_arg_advance ( struct sparc_args * cum , enum machine_mode mode , tree type , int named ) { int slotno , regno , padding ; slotno = function_arg_slotno ( cum , mode , type , named , 0 , & regno , & padding ) ; if ( slotno != - 1 ) cum -> words += padding ; if ( TARGET_ARCH32 ) { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) ; } else { if ( type && AGGREGATE_TYPE_P ( type ) ) { int size = int_size_in_bytes ( type ) ; if ( size <= 8 ) ++ cum -> words ; else if ( size <= 16 ) cum -> words += 2 ; else ++ cum -> words ; } else { cum -> words += ( mode != BLKmode ? ROUND_ADVANCE ( GET_MODE_SIZE ( mode ) ) : ROUND_ADVANCE ( int_size_in_bytes ( type ) ) ) ; } } } </s>

Handle the FUNCTION_ARG_ADVANCE macro . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s> unsigned SparcInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: LDri || MI -> getOpcode ( ) == SP :: LDXri || MI -> getOpcode ( ) == SP :: LDFri || MI -> getOpcode ( ) == SP :: LDDFri ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static int thumb_far_jump_used_p ( void ) { rtx_insn * insn ; bool far_jump = false ; unsigned int func_size = 0 ; if ( cfun -> machine -> far_jump_used ) return 1 ; if ( ! ( ARM_DOUBLEWORD_ALIGN || reload_completed ) ) { if ( df_regs_ever_live_p ( ARG_POINTER_REGNUM ) ) cfun -> machine -> arg_pointer_live = 1 ; else if ( ! cfun -> machine -> arg_pointer_live ) return 0 ; } if ( reload_in_progress || reload_completed ) return 0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) { far_jump = true ; } func_size += get_attr_length ( insn ) ; } if ( far_jump ) { if ( ( func_size * 3 ) >= 2048 ) { cfun -> machine -> far_jump_used = 1 ; return 1 ; } } return 0 ; } </s>

Returns non-zero if the current function contains , or might contain a far jump .


<s> static bool call_ABI_of_interest ( tree fndecl ) { if ( symtab -> state == EXPANSION ) { struct cgraph_node * c_node ; if ( fndecl == NULL_TREE ) return true ; if ( DECL_EXTERNAL ( fndecl ) ) return true ; c_node = cgraph_node :: get ( fndecl ) ; c_node = c_node -> ultimate_alias_target ( ) ; return ! c_node -> only_called_directly_p ( ) ; } return false ; } </s>

Return TRUE if a call to function FNDECL may be one that potentially affects the function calling ABI of the object file .


<s> virtual bool isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


"invalid feature modifier %qs in %<-mcpu=%s%>"

Validate a command-line -mcpu option . Parse the cpu and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results if they are valid in RES and ISA_FLAGS . Return whether the option is valid .


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
(
Subtarget
.
isSVR4ABI
(
)
&&
CallConv
==
CallingConv
::
Cold
)
RetCC_PPC_Cold
:
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> bool FISCFrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
int
AArch64AsmParser
::
tryParseRegister
(
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
const
AsmToken
&
Tok
=
Parser
.
getTok
(
)
;
assert
(
Tok
.
is
(
AsmToken
::
Identifier
)
&&
"Token is not an Identifier"
)
;
std
::
string
lowerCase
=
Tok
.
getString
(
)
.
lower
(
)
;
if
(
isSVEVectorOrPredicateRegister
(
lowerCase
)
)
return
1
;
unsigned
RegNum
=
matchRegisterNameAlias
(
lowerCase
,
false
)
;
if
(
RegNum
==
0
)
RegNum
=
StringSwitch
<
unsigned
>
(
lowerCase
)
.
Case
(
"fp"
,
AArch64
::
FP
)
.
Case
(
"lr"
,
AArch64
::
LR
)
.
Case
(
"x31"
,
AArch64
::
XZR
)
.
Case
(
"w31"
,
AArch64
::
WZR
)
.
Default
(
0
)
;
if
(
RegNum
==
0
)
return
1
;
Parser
.
Lex
(
)
;
return
RegNum
;
}
</s>

tryParseRegister - parse one register if possible


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


"RESTORE_QUADWORD does not define its destination"

lowerQuadwordRestore - Generate code to restore paired general register .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { validDomains = getExecutionDomainCustom ( MI ) ; if ( validDomains ) return std :: make_pair ( domain , validDomains ) ; if ( lookup ( opcode , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( 0 , 0 ) ; validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) ) { if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = 0xa ; else validDomains = 0xc ; } } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


Return a register priority for hard reg REGNO .


<s> const_iterator begin ( ) const { return m_SectToExData . begin ( ) ; } </s>


<s> void PPCTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
Subtarget
.
hasVector
(
)
)
VerifyVectorTypes
(
Outs
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
Register
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static rtx_insn * mips_epilogue_emit_cfa_restores ( void ) { rtx_insn * insn ; insn = get_last_insn ( ) ; if ( mips_epilogue . cfa_restores ) { gcc_assert ( insn && ! REG_NOTES ( insn ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = mips_epilogue . cfa_restores ; mips_epilogue . cfa_restores = 0 ; } return insn ; } </s>

Attach all pending register saves to the previous instruction . Return that instruction .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Darwin PPC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .