<s>
bool
AArch64CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
AArch64
::
RET_ReallyLR
)
;
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
bool
Success
=
true
;
if
(
VReg
)
{
const
AArch64TargetLowering
&
TLI
=
*
getTLI
<
AArch64TargetLowering
>
(
)
;
CCAssignFn
*
AssignFn
=
TLI
.
CCAssignFnForReturn
(
F
.
getCallingConv
(
)
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
F
.
getParent
(
)
->
getDataLayout
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
F
.
getCallingConv
(
)
,
[
&
]
(
unsigned
Reg
,
uint64_t
Offset
)
{
MIRBuilder
.
buildExtract
(
Reg
,
VReg
,
Offset
)
;
}
)
;
OutgoingArgHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
AssignFn
,
AssignFn
)
;
Success
=
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
Success
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & Args = F . getArgumentList ( ) ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : Args ) { ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + 1 , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ i ] , Regs , Offsets ) ; } ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! handleAssignments ( MIRBuilder , AssignFn , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
k_Token
:
OS
<<
"Token: "
<<
getToken
(
)
<<
"\n"
;
break
;
case
k_Register
:
OS
<<
"Reg: #"
<<
getReg
(
)
<<
"\n"
;
break
;
case
k_Immediate
:
OS
<<
"Imm: "
<<
getImm
(
)
<<
"\n"
;
break
;
case
k_MemoryReg
:
OS
<<
"Mem: "
<<
getMemBase
(
)
<<
"+"
<<
getMemOffsetReg
(
)
<<
"\n"
;
break
;
case
k_MemoryImm
:
assert
(
getMemOff
(
)
!=
nullptr
)
;
OS
<<
"Mem: "
<<
getMemBase
(
)
<<
"+"
<<
*
getMemOff
(
)
<<
"\n"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> const MachineDomTreeNode * MBBInfo :: getNode ( ) const { return Node ; } </s>


<s> void MINA32RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


Decide whether to use the unrolling heuristic described above aarch64_vector_costs : :unrolled_advsimd_niters , updating that field if so . LOOP_VINFO describes the loop that we 're vectorizing and COSTS are the costs that we 're calculating for it .


<s> static bool mep_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF && ( reload_in_progress || reload_completed ) ) { char e = mep_section_tag ( x ) ; return ( e != 't' && e != 'b' ) ; } return 1 ; } </s>


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> int ia64_direct_return ( void ) { if ( reload_completed && ! frame_pointer_needed ) { ia64_compute_frame_size ( get_frame_size ( ) ) ; return ( current_frame_info . total_size == 0 && current_frame_info . n_spilled == 0 && current_frame_info . r [ reg_save_b0 ] == 0 && current_frame_info . r [ reg_save_pr ] == 0 && current_frame_info . r [ reg_save_ar_pfs ] == 0 && current_frame_info . r [ reg_save_ar_unat ] == 0 && current_frame_info . r [ reg_save_ar_lc ] == 0 ) ; } return 0 ; } </s>

Return 1 if br.ret can do all the work required to return from a function .


<s> bool ARM64TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isREVMask ( M , VT , 64 ) || isREVMask ( M , VT , 32 ) || isREVMask ( M , VT , 16 ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == 128 ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static rtx gen_stack_pointer_inc ( rtx increment ) { return gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , increment ) ) ; } </s>

Generate an increment for the stack pointer .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static rtx nds32_expand_builtin_load ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx addr_helper = gen_reg_rtx ( insn_data [ icode ] . operand [ 1 ] . mode ) ; target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , 1 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 , addr_helper ) ; if ( ! pat ) return NULL_RTX ; emit_move_insn ( addr_helper , GEN_INT ( 0 ) ) ; emit_insn ( pat ) ; return target ; } </s>


<s> static bool mips_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { return TARGET_SIBCALLS ; } </s>

We can handle any sibcall when TARGET_SIBCALLS is true .


<s> virtual const XNCMInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> EVT SystemZTargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { return Subtarget . hasVector ( ) ? MVT :: v2i64 : MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>


Change register usage conditional on target flags .


<s> static void ix86_default_align ( struct gcc_options * opts ) { if ( opts -> x_align_loops == 0 ) { opts -> x_align_loops = processor_target_table [ ix86_tune ] . align_loop ; align_loops_max_skip = processor_target_table [ ix86_tune ] . align_loop_max_skip ; } if ( opts -> x_align_jumps == 0 ) { opts -> x_align_jumps = processor_target_table [ ix86_tune ] . align_jump ; align_jumps_max_skip = processor_target_table [ ix86_tune ] . align_jump_max_skip ; } if ( opts -> x_align_functions == 0 ) { opts -> x_align_functions = processor_target_table [ ix86_tune ] . align_func ; } } </s>

Default align_ * from the processor table .


"insertBranch must not be told to insert a fallthrough"

"VE branch conditions should have three component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> static tree ix86_canonical_va_list_type ( tree type ) { tree wtype , htype ; if ( TREE_CODE ( type ) == MEM_REF ) type = TREE_TYPE ( type ) ; else if ( POINTER_TYPE_P ( type ) && POINTER_TYPE_P ( TREE_TYPE ( type ) ) ) type = TREE_TYPE ( type ) ; else if ( POINTER_TYPE_P ( type ) && TREE_CODE ( TREE_TYPE ( type ) ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( TARGET_64BIT && va_list_type_node != NULL_TREE ) { wtype = va_list_type_node ; gcc_assert ( wtype != NULL_TREE ) ; htype = type ; if ( TREE_CODE ( wtype ) == ARRAY_TYPE ) { if ( TREE_CODE ( htype ) == ARRAY_TYPE || POINTER_TYPE_P ( htype ) ) { wtype = TREE_TYPE ( wtype ) ; htype = TREE_TYPE ( htype ) ; } } if ( TYPE_MAIN_VARIANT ( wtype ) == TYPE_MAIN_VARIANT ( htype ) ) return va_list_type_node ; wtype = sysv_va_list_type_node ; gcc_assert ( wtype != NULL_TREE ) ; htype = type ; if ( TREE_CODE ( wtype ) == ARRAY_TYPE ) { if ( TREE_CODE ( htype ) == ARRAY_TYPE || POINTER_TYPE_P ( htype ) ) { wtype = TREE_TYPE ( wtype ) ; htype = TREE_TYPE ( htype ) ; } } if ( TYPE_MAIN_VARIANT ( wtype ) == TYPE_MAIN_VARIANT ( htype ) ) return sysv_va_list_type_node ; wtype = ms_va_list_type_node ; gcc_assert ( wtype != NULL_TREE ) ; htype = type ; if ( TREE_CODE ( wtype ) == ARRAY_TYPE ) { if ( TREE_CODE ( htype ) == ARRAY_TYPE || POINTER_TYPE_P ( htype ) ) { wtype = TREE_TYPE ( wtype ) ; htype = TREE_TYPE ( htype ) ; } } if ( TYPE_MAIN_VARIANT ( wtype ) == TYPE_MAIN_VARIANT ( htype ) ) return ms_va_list_type_node ; return NULL_TREE ; } return std_canonical_va_list_type ( type ) ; } </s>

Returns the canonical va_list type specified by TYPE . If there is no valid TYPE provided , it return NULL_TREE .


<s> static ds_t ia64_get_insn_spec_ds ( rtx_insn * insn ) { int code = get_insn_spec_code ( insn ) ; switch ( code ) { case UNSPEC_LDA : return BEGIN_DATA ; case UNSPEC_LDS : case UNSPEC_LDS_A : return BEGIN_CONTROL ; case UNSPEC_LDSA : return BEGIN_DATA | BEGIN_CONTROL ; default : return 0 ; } } </s>

If INSN is a speculative load , return a ds with the speculation types . Otherwise [ if INSN is a normal instruction ] return 0 .


<s> void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


"AltiVec argument passed to unprototyped function"

Target hook for invalid_arg_for_unprototyped_fn .


<s> static unsigned HOST_WIDE_INT arm_shift_truncation_mask ( machine_mode mode ) { return mode == SImode ? 255 : 0 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . SImode shifts use normal ARM insns and therefore guarantee that the shift count is modulo 256 . DImode shifts ( those implemented by lib1funcs.asm or by optabs.c ) guarantee no particular behavior for out-of-range counts .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static tree aarch64_comparison_type ( stmt_vec_info stmt_info ) { if ( auto * assign = dyn_cast < gassign * > ( stmt_info -> stmt ) ) if ( TREE_CODE_CLASS ( gimple_assign_rhs_code ( assign ) ) == tcc_comparison ) return TREE_TYPE ( gimple_assign_rhs1 ( assign ) ) ; return aarch64_embedded_comparison_type ( stmt_info ) ; } </s>

If STMT_INFO is a comparison or contains an embedded comparison , return the scalar type of the values being compared . Return null otherwise .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) return AArch64II :: MO_GOT ; if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? AArch64II :: MO_GOT : AArch64II :: MO_NO_FLAG ; else return GV -> hasLocalLinkage ( ) ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; } return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s>
const
char
*
host_detect_local_cpu
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
cpu
=
;
char
buf
[
128
]
;
FILE
*
f
;
bool
arch
;
if
(
argc
<
1
)
return
;
arch
=
strcmp
(
argv
[
0
]
,
"arch"
)
==
0
;
if
(
!
arch
&&
strcmp
(
argv
[
0
]
,
"tune"
)
)
return
;
f
=
fopen
(
"/proc/cpuinfo"
,
"r"
)
;
if
(
f
==
)
return
;
while
(
fgets
(
buf
,
sizeof
(
buf
)
,
f
)
!=
)
if
(
startswith
(
buf
,
"cpu model"
)
)
{
if
(
strstr
(
buf
,
"Godson2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.2"
)
!=
||
strstr
(
buf
,
"Loongson-2E"
)
!=
)
cpu
=
"loongson2e"
;
else
if
(
strstr
(
buf
,
"Godson2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2 V0.3"
)
!=
||
strstr
(
buf
,
"Loongson-2F"
)
!=
)
cpu
=
"loongson2f"
;
else
if
(
strstr
(
buf
,
"Godson3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3 V0.5"
)
!=
||
strstr
(
buf
,
"Loongson-3A"
)
!=
)
cpu
=
"loongson3a"
;
else
if
(
strstr
(
buf
,
"SiByte SB1"
)
!=
)
cpu
=
"sb1"
;
else
if
(
strstr
(
buf
,
"R5000"
)
!=
)
cpu
=
"r5000"
;
else
if
(
strstr
(
buf
,
"Octeon II"
)
!=
)
cpu
=
"octeon2"
;
else
if
(
strstr
(
buf
,
"Octeon"
)
!=
)
cpu
=
"octeon"
;
break
;
}
fclose
(
f
)
;
if
(
cpu
==
)
return
;
return
concat
(
"-m"
,
argv
[
0
]
,
"="
,
cpu
,
)
;
}
</s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const PPCTargetMachine & TM ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , DL ( getDataLayoutString ( TargetTriple ) ) , IsPPC64 ( TargetTriple . getArch ( ) == Triple :: ppc64 || TargetTriple . getArch ( ) == Triple :: ppc64le ) , TargetABI ( PPC_ABI_UNKNOWN ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( * this ) , TLInfo ( TM ) , TSInfo ( & DL ) { } </s>

This constructor initializes the data members to match that of the specified triple .


runOnMachineFunction - Emit the function body .


<s> virtual const MipsRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
isDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> void rs6000_expand_vector_init ( rtx target , rtx vals ) { enum machine_mode mode = GET_MODE ( target ) ; enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; rtx x , mem ; int i ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONSTANT_P ( x ) ) ++ n_var , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { if ( mode != V4SFmode && all_const_zero ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_XOR ( mode , target , target ) ) ) ; return ; } else if ( mode != V4SFmode && easy_vector_constant ( vals , mode ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , vals ) ) ; return ; } else if ( all_same ) ; else { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } } if ( all_same ) { mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) , 0 ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , 0 ) , XVECEXP ( vals , 0 , 0 ) ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , target , mem ) , x ) ) ) ; x = gen_rtx_VEC_SELECT ( inner_mode , target , gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_VEC_DUPLICATE ( mode , x ) ) ) ; return ; } if ( n_var == 1 ) { rtx copy = copy_rtx ( vals ) ; XVECEXP ( copy , 0 , one_var ) = XVECEXP ( vals , 0 , ( one_var + 1 ) % n_elts ) ; rs6000_expand_vector_init ( target , copy ) ; rs6000_expand_vector_set ( target , XVECEXP ( vals , 0 , one_var ) , one_var ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) , 0 ) ; for ( i = 0 ; i < n_elts ; i ++ ) emit_move_insn ( adjust_address_nv ( mem , inner_mode , i * GET_MODE_SIZE ( inner_mode ) ) , XVECEXP ( vals , 0 , i ) ) ; emit_move_insn ( target , mem ) ; } </s>


<s>
const
char
*
ix86_output_call_insn
(
rtx_insn
*
insn
,
rtx
call_op
)
{
bool
direct_p
=
constant_call_address_operand
(
call_op
,
VOIDmode
)
;
bool
seh_nop_p
=
false
;
const
char
*
xasm
;
if
(
SIBLING_CALL_P
(
insn
)
)
{
if
(
direct_p
)
xasm
=
"%!jmp\t%P0"
;
else
if
(
TARGET_SEH
)
xasm
=
"%!rex.W jmp %A0"
;
else
xasm
=
"%!jmp\t%A0"
;
output_asm_insn
(
xasm
,
&
call_op
)
;
return
""
;
}
if
(
TARGET_SEH
)
{
rtx_insn
*
i
;
for
(
i
=
NEXT_INSN
(
insn
)
;
i
;
i
=
NEXT_INSN
(
i
)
)
{
if
(
INSN_P
(
i
)
)
break
;
if
(
NOTE_P
(
i
)
&&
NOTE_KIND
(
i
)
==
NOTE_INSN_EPILOGUE_BEG
&&
!
flag_non_call_exceptions
&&
!
can_throw_internal
(
insn
)
)
{
seh_nop_p
=
true
;
break
;
}
}
if
(
i
==
)
seh_nop_p
=
true
;
}
if
(
direct_p
)
xasm
=
"%!call\t%P0"
;
else
xasm
=
"%!call\t%A0"
;
output_asm_insn
(
xasm
,
&
call_op
)
;
if
(
seh_nop_p
)
return
"nop"
;
return
""
;
}
</s>

Output the assembly for a call instruction .


<s> bool AArch64TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return false ; int64_t Val = Imm . getSExtValue ( ) ; if ( Val == 0 || AArch64_AM :: isLogicalImmediate ( Val , BitSize ) ) return true ; if ( ( int64_t ) Val < 0 ) Val = ~ Val ; if ( BitSize == 32 ) Val &= ( 1LL << 32 ) - 1 ; unsigned LZ = countLeadingZeros ( ( uint64_t ) Val ) ; unsigned Shift = ( 63 - LZ ) / 16 ; return ( Shift < 3 ) ? true : false ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> int crx_memory_move_cost ( enum machine_mode mode , enum reg_class class ATTRIBUTE_UNUSED , int in ATTRIBUTE_UNUSED ) { if ( reg_classes_intersect_p ( class , GENERAL_REGS ) ) { return 4 * HARD_REGNO_NREGS ( 0 , mode ) ; } else if ( reg_classes_intersect_p ( class , HILO_REGS ) ) { return ( REGISTER_MOVE_COST ( mode , in ? GENERAL_REGS : HILO_REGS , in ? HILO_REGS : GENERAL_REGS ) + 4 ) * HARD_REGNO_NREGS ( 0 , mode ) ; } else { return 100 ; } } </s>

Return the cost of moving data of mode MODE between a register of class * CLASS and memory ; IN is zero if the value is to be written to memory , * nonzero if it is to be read in . This cost is relative to those in * REGISTER_MOVE_COST .


<s> ix86_dependencies_evaluation_hook static int ix86_reassociation_width ( unsigned int op , machine_mode mode ) { int width = 1 ; if ( VECTOR_MODE_P ( mode ) ) { int div = 1 ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == 1 ) return 1 ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return 1 ; if ( TARGET_AVX512_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 256 ) div = GET_MODE_BITSIZE ( mode ) / 256 ; else if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 128 ) div = GET_MODE_BITSIZE ( mode ) / 128 ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 64 ) div = GET_MODE_BITSIZE ( mode ) / 64 ; width = ( width + div - 1 ) / div ; } else if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_fp ; if ( ! TARGET_64BIT && width > 2 ) width = 2 ; return width ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> void PPCPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } if ( getPPCTargetMachine ( ) . isPositionIndependent ( ) ) { addPass ( & LiveVariablesID , false ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & MachinePipelinerID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void ix86_emit_save_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { ix86_emit_save_reg_using_mov ( V4SFmode , regno , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to save SSE registers using MOV insns . First register is stored at CFA - CFA_OFFSET .


"built-in function %qE not supported for MIPS16"

Expand builtin functions . This is called from TARGET_EXPAND_BUILTIN .


Enable AARCH64_FL_ * flags EXTRA_FLAGS on top of the base Advanced SIMD set .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> int MipsAsmParser :: tryParseRegister ( bool is64BitReg ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase , is64BitReg ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , is64BitReg ? Mips :: GPR64RegClassID : Mips :: GPR32RegClassID ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> void PPCPassConfig :: addPreRegAlloc ( ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; if ( getPPCTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( createPPCTLSDynamicCallPass ( ) ) ; } </s>


Returns the calling convention specific va_list date type . The argument ABI can be DEFAULT_ABI , MS_ABI , or SYSV_ABI .


<s> bool loongarch_symbol_binds_local_p ( const_rtx x ) { if ( TARGET_DIRECT_EXTERN_ACCESS ) return true ; if ( SYMBOL_REF_P ( x ) ) return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; else return false ; } </s>

Return true if SYMBOL_REF X binds locally .


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = REG_NREGS ( operands [ 1 ] ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { emitRegPlusImmediate ( isARM , MBB , MBBI , dl , TII , ARM :: SP , ARM :: SP , NumBytes , MIFlags , Pred , PredReg ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM::SP ARM::SP


<s>
const
char
*
SICAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
SICTargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
SICABIInfo
::
ABI
::
O32
:
return
"abiO32"
;
case
SICABIInfo
::
ABI
::
S32
:
return
"abiS32"
;
default
:
llvm_unreachable
(
"Unknown SIC ABI"
)
;
}
}
</s>


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> static bool ix86_pic_register_p ( rtx x ) { if ( GET_CODE ( x ) == VALUE && CSELIB_VAL_PTR ( x ) ) return ( pic_offset_table_rtx && rtx_equal_for_cselib_p ( x , pic_offset_table_rtx ) ) ; else if ( ! REG_P ( x ) ) return false ; else if ( pic_offset_table_rtx ) { if ( REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; if ( HARD_REGISTER_P ( x ) && ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false ; } else return REGNO ( x ) == PIC_OFFSET_TABLE_REGNUM ; } </s>

Return true if X is a representation of the PIC register . This copes with calls from ix86_find_base_term , where the register might have been replaced by a cselib value .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & AArch64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
void
SystemZPostRASchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"** Scheduling SU("
<<
SU
->
NodeNum
<<
") "
;
if
(
Available
.
size
(
)
==
1
)
dbgs
(
)
<<
"(only one) "
;
Candidate
c
(
SU
,
*
HazardRec
)
;
c
.
dumpCosts
(
)
;
dbgs
(
)
<<
"\n"
;
)
;
Available
.
erase
(
SU
)
;
HazardRec
->
EmitInstruction
(
SU
)
;
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

SystemZ
SystemZ
"** Scheduling SU("
") "
1
"(only one) "
"\n"


"invalid instruction size for rip-relative lea"

Given an instruction with a memory operand that could require relocation , returns the offset within the instruction of that relocation .


<s> static bool aarch64_valid_floating_const ( machine_mode mode , rtx x ) { if ( ! CONST_DOUBLE_P ( x ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; if ( ! ( mode == SFmode || mode == DFmode ) ) return false ; return aarch64_float_const_representable_p ( x ) ; } </s>

Return true if X holds either a quarter-precision or floating-point +0.0 constant .


<s> static std :: unique_ptr < MINA32Operand > CreateMem ( unsigned Base , const MCExpr * Off , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < MINA32Operand > ( k_Memory ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; const AArch64Subtarget & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; const unsigned RedZoneSize = Subtarget . getTargetLowering ( ) -> getRedZoneSize ( MF . getFunction ( ) ) ; if ( ! RedZoneSize ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > RedZoneSize || getSVEStackSize ( MF ) ) ; } </s>

Can this function use the red zone for local allocations .


<s> rtx mips_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { enum insn_code icode ; enum mips_builtin_type type ; tree fndecl , arglist ; unsigned int fcode ; const struct builtin_description * bdesc ; const struct bdesc_map * m ; fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , 0 ) , 0 ) ; arglist = TREE_OPERAND ( exp , 1 ) ; fcode = DECL_FUNCTION_CODE ( fndecl ) ; bdesc = NULL ; for ( m = bdesc_arrays ; m < & bdesc_arrays [ ARRAY_SIZE ( bdesc_arrays ) ] ; m ++ ) { if ( fcode < m -> size ) { bdesc = m -> bdesc ; icode = bdesc [ fcode ] . icode ; type = bdesc [ fcode ] . builtin_type ; break ; } fcode -= m -> size ; } if ( bdesc == NULL ) return 0 ; switch ( type ) { case MIPS_BUILTIN_DIRECT : return mips_expand_builtin_direct ( icode , target , arglist , true ) ; case MIPS_BUILTIN_DIRECT_NO_TARGET : return mips_expand_builtin_direct ( icode , target , arglist , false ) ; case MIPS_BUILTIN_MOVT : case MIPS_BUILTIN_MOVF : return mips_expand_builtin_movtf ( type , icode , bdesc [ fcode ] . cond , target , arglist ) ; case MIPS_BUILTIN_CMP_ANY : case MIPS_BUILTIN_CMP_ALL : case MIPS_BUILTIN_CMP_UPPER : case MIPS_BUILTIN_CMP_LOWER : case MIPS_BUILTIN_CMP_SINGLE : return mips_expand_builtin_compare ( type , icode , bdesc [ fcode ] . cond , target , arglist ) ; case MIPS_BUILTIN_BPOSGE32 : return mips_expand_builtin_bposge ( type , target ) ; default : return 0 ; } } </s>


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; if ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( mask == 0 || ( mask & ix86_isa_flags ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s>
void
AArch64FrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
AArch64InstrInfo
*
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
DebugLoc
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
if
(
!
IsDestroy
)
Amount
=
Amount
;
if
(
CalleePopAmount
==
0
)
{
assert
(
Amount
>
0xffffff
&&
Amount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
Amount
,
TII
)
;
}
}
else
if
(
CalleePopAmount
!=
0
)
{
assert
(
CalleePopAmount
<
0xffffff
&&
"call frame too large"
)
;
emitFrameOffset
(
MBB
,
I
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
CalleePopAmount
,
TII
)
;
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> bool X86TargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) != ISD :: FP_EXTEND ) return false ; bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != X86ISD :: RET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'L'
:
O
<<
getDataLayout
(
)
.
getPointerSize
(
)
<<
"("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
case
'y'
:
O
<<
"0, "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'U'
:
case
'X'
:
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


Hook to validate the current # pragma GCC target and set the arch custom mode state . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> void X86LoadValueInjectionLoadHardeningPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineDominanceFrontier > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void LC3InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LC3 :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static void mips_sim_wait_regs ( struct mips_sim * state , rtx insn ) { mips_sim_insn = insn ; note_uses ( & PATTERN ( insn ) , mips_sim_wait_regs_1 , state ) ; } </s>

Advance simulation state STATE until all of INSN 's register dependencies are satisfied .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 1 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; if ( MI . getOperand ( 2 ) . isImm ( ) ) { CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; } else { CmpMask = CmpValue = 0 ; } return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget . isTargetGlibc ( ) ) TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static bool sh_cannot_copy_insn_p ( rtx_insn * insn ) { rtx pat ; if ( ! reload_completed || ! flag_pic ) return false ; if ( ! NONJUMP_INSN_P ( insn ) ) return false ; if ( asm_noperands ( insn ) >= 0 ) return false ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == USE ) return false ; if ( TARGET_FDPIC && GET_CODE ( pat ) == PARALLEL ) { rtx t = XVECEXP ( pat , 0 , XVECLEN ( pat , 0 ) - 1 ) ; if ( GET_CODE ( t ) == USE && unspec_caller_rtx_p ( XEXP ( t , 0 ) ) ) return true ; } if ( GET_CODE ( pat ) != SET ) return false ; pat = SET_SRC ( pat ) ; if ( unspec_caller_rtx_p ( pat ) ) return true ; return false ; } </s>

Indicate that INSN can not be duplicated . This is true for insn that generates a unique label .


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { CommentStream = & CStream ; InternalInstruction InternalInstr ; dlog_t LoggerFn = logger ; if ( & VStream == & nulls ( ) ) LoggerFn = nullptr ; Region R ( Bytes , Address ) ; int Ret = decodeInstruction ( & InternalInstr , regionReader , ( const void * ) & R , LoggerFn , ( void * ) & VStream , ( const void * ) MII . get ( ) , Address , fMode ) ; if ( Ret ) { Size = InternalInstr . readerCursor - Address ; return Fail ; } else { Size = InternalInstr . length ; bool Ret = translateInstruction ( Instr , InternalInstr , this ) ; if ( ! Ret ) { unsigned Flags = X86 :: IP_NO_PREFIX ; if ( InternalInstr . hasAdSize ) Flags |= X86 :: IP_HAS_AD_SIZE ; if ( ! InternalInstr . mandatoryPrefix ) { if ( InternalInstr . hasOpSize ) Flags |= X86 :: IP_HAS_OP_SIZE ; if ( InternalInstr . repeatPrefix == 0xf2 ) Flags |= X86 :: IP_HAS_REPEAT_NE ; else if ( InternalInstr . repeatPrefix == 0xf3 && InternalInstr . opcode != 0x90 ) Flags |= X86 :: IP_HAS_REPEAT ; } Instr . setFlags ( Flags ) ; } return ( ! Ret ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s>
void
F2003fMCAsmStreamer
::
emitValueToOffset
(
const
MCExpr
*
Offset
,
unsigned
char
Value
,
SMLoc
Loc
)
{
llvm_unreachable
(
"2003lk doesn't support this directive"
)
;
}
</s>

Emit some number of copies of Value until the byte offset Offset is reached .


<s> void reset ( unsigned RequiredSize ) { RequiredShadowSize = RequiredSize ; CurrentShadowSize = 0 ; InShadow = true ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget -> isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget -> isUnalignedMem32Slow ( ) ; break ; } } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool movd44_even_dep_p ( rtx_insn * insn , rtx def_reg ) { if ( ! movd44_insn_p ( insn ) ) return false ; rtx use_rtx = SET_SRC ( PATTERN ( insn ) ) ; if ( REG_P ( def_reg ) ) { return rtx_equal_p ( def_reg , use_rtx ) ; } else if ( GET_CODE ( def_reg ) == SUBREG && GET_MODE ( def_reg ) == SImode && rtx_equal_p ( SUBREG_REG ( def_reg ) , use_rtx ) ) { if ( TARGET_BIG_ENDIAN && SUBREG_BYTE ( def_reg ) == 4 ) return true ; if ( ! TARGET_BIG_ENDIAN && SUBREG_BYTE ( def_reg ) == 0 ) return true ; return false ; } return false ; } </s>

Check if INSN is a movd44 insn consuming DEF_REG .


<s>
bool
Mips16HardFloat
::
runOnModule
(
Module
&
M
)
{
DEBUG
(
errs
(
)
<<
"Run on Module Mips16HardFloat\n"
)
;
bool
Modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
isDeclaration
(
)
||
F
->
hasFnAttribute
(
"mips16_fp_stub"
)
||
F
->
hasFnAttribute
(
"nomips16"
)
)
continue
;
Modified
|=
fixupFPReturnAndCall
(
*
F
,
&
M
,
Subtarget
)
;
FPParamVariant
V
=
whichFPParamVariantNeeded
(
*
F
)
;
if
(
V
!=
NoSig
)
{
Modified
=
true
;
createFPFnStub
(
F
,
&
M
,
V
,
Subtarget
)
;
}
}
return
Modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> StringRef getPassName ( ) const override { return "AArch64O0PreLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> bool X86TargetLowering :: hasBitTest ( SDValue X , SDValue Y ) const { return X . getValueType ( ) . isScalarInteger ( ) ; } </s>

Return true if the target has a bit-test instruction : ( X & ( 1 < < Y ) ) ==/ ! = 0 This knowledge can be used to prevent breaking the pattern , or creating it if it could be recognized .


"emitting conditional microcode insn %s\t[%s] #%d"

Define FINAL_PRESCAN_INSN if some processing needs to be done before outputting the assembler code . On the PowerPC , we remember if the current insn is a prefixed insn where we need to emit a ' p ' before the insn . In addition , if the insn is part of a PC-relative reference to an external label optimization , this is recorded also .


<s>
unsigned
ARMBaseInstrInfo
::
getNumMicroOps
(
const
InstrItineraryData
*
ItinData
,
const
MachineInstr
*
MI
)
const
{
if
(
!
ItinData
||
ItinData
->
isEmpty
(
)
)
return
1
;
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
Class
=
Desc
.
getSchedClass
(
)
;
unsigned
UOps
=
ItinData
->
Itineraries
[
Class
]
.
NumMicroOps
;
if
(
UOps
)
return
UOps
;
unsigned
Opc
=
MI
->
getOpcode
(
)
;
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Unexpected multi-uops instruction!"
)
;
case
ARM
::
VLDMQIA
:
case
ARM
::
VSTMQIA
:
return
2
;
case
ARM
::
VLDMDIA
:
case
ARM
::
VLDMDIA_UPD
:
case
ARM
::
VLDMDDB_UPD
:
case
ARM
::
VLDMSIA
:
case
ARM
::
VLDMSIA_UPD
:
case
ARM
::
VLDMSDB_UPD
:
case
ARM
::
VSTMDIA
:
case
ARM
::
VSTMDIA_UPD
:
case
ARM
::
VSTMDDB_UPD
:
case
ARM
::
VSTMSIA
:
case
ARM
::
VSTMSIA_UPD
:
case
ARM
::
VSTMSDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
;
return
(
NumRegs
/
2
)
+
(
NumRegs
%
2
)
+
1
;
}
case
ARM
::
LDMIA_RET
:
case
ARM
::
LDMIA
:
case
ARM
::
LDMDA
:
case
ARM
::
LDMDB
:
case
ARM
::
LDMIB
:
case
ARM
::
LDMIA_UPD
:
case
ARM
::
LDMDA_UPD
:
case
ARM
::
LDMDB_UPD
:
case
ARM
::
LDMIB_UPD
:
case
ARM
::
STMIA
:
case
ARM
::
STMDA
:
case
ARM
::
STMDB
:
case
ARM
::
STMIB
:
case
ARM
::
STMIA_UPD
:
case
ARM
::
STMDA_UPD
:
case
ARM
::
STMDB_UPD
:
case
ARM
::
STMIB_UPD
:
case
ARM
::
tLDMIA
:
case
ARM
::
tLDMIA_UPD
:
case
ARM
::
tSTMIA_UPD
:
case
ARM
::
tPOP_RET
:
case
ARM
::
tPOP
:
case
ARM
::
tPUSH
:
case
ARM
::
t2LDMIA_RET
:
case
ARM
::
t2LDMIA
:
case
ARM
::
t2LDMDB
:
case
ARM
::
t2LDMIA_UPD
:
case
ARM
::
t2LDMDB_UPD
:
case
ARM
::
t2STMIA
:
case
ARM
::
t2STMDB
:
case
ARM
::
t2STMIA_UPD
:
case
ARM
::
t2STMDB_UPD
:
{
unsigned
NumRegs
=
MI
->
getNumOperands
(
)
Desc
.
getNumOperands
(
)
+
1
;
if
(
Subtarget
.
isCortexA8
(
)
)
{
if
(
NumRegs
<
4
)
return
2
;
UOps
=
(
NumRegs
/
2
)
;
if
(
NumRegs
%
2
)
++
UOps
;
return
UOps
;
}
else
if
(
Subtarget
.
isCortexA9
(
)
)
{
UOps
=
(
NumRegs
/
2
)
;
if
(
(
NumRegs
%
2
)
||
!
MI
->
hasOneMemOperand
(
)
||
(
*
MI
->
memoperands_begin
(
)
)
->
getAlignment
(
)
<
8
)
++
UOps
;
return
UOps
;
}
else
{
return
NumRegs
;
}
}
}
}
</s>

Return the number of issue slots required for this MI .


<s> void SHUXIAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> SDValue MipsTargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlign ( ) , N -> getOffset ( ) , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s>
void
MipsInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SW
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
{
if
(
!
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
.
isMips1
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SDC1
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
MBB
.
getParent
(
)
->
getTarget
(
)
.
getRegisterInfo
(
)
;
const
unsigned
*
SubSet
=
TRI
->
getSubRegisters
(
SrcReg
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SubSet
[
0
]
,
getKillRegState
(
isKill
)
)
.
addImm
(
0
)
.
addFrameIndex
(
FI
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Mips
::
SWC1
)
)
.
addReg
(
SubSet
[
1
]
,
getKillRegState
(
isKill
)
)
.
addImm
(
4
)
.
addFrameIndex
(
FI
)
;
}
}
else
llvm_unreachable
(
"Register class not handled!"
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool mips_global_symbol_p ( const_rtx x ) { const_tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl ) return ! SYMBOL_REF_LOCAL_P ( x ) || SYMBOL_REF_EXTERNAL_P ( x ) ; return DECL_P ( decl ) && ( TREE_PUBLIC ( decl ) || DECL_WEAK ( decl ) ) ; } </s>

Return true if SYMBOL_REF X is associated with a global symbol ( in the STB_GLOBAL sense ) .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; bool Changed = AsmPrinter :: runOnMachineFunction ( MF ) ; emitXRayTable ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void PPCInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { const char * RegName = getRegisterName ( RegNo ) ; if ( RegName [ 0 ] == 'q' ) { std :: string RN ( RegName ) ; RN [ 0 ] = 'f' ; OS << RN ; return ; } OS << RegName ; } </s>


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
,
Mnemonic
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> bool isProfitableToUnpredicate ( ) const { return IsProfitableToUnpredicate ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


"Do not know how to custom type legalize this operation!"

"Unexpected result type for CTR decrement intrinsic"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> const TargetRegisterClass * CJGRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & CJG :: GPRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> bool ARMTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( llvm :: abs64 ( Imm ) ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( llvm :: abs64 ( Imm ) ) != - 1 ; return Imm >= 0 && Imm <= 255 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getFnAttributes ( ) . hasOptimizeForSizeAttr ( ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == X86ISD :: CALL || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; bool SrcIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> static rtx_insn * rs6000_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( SImode , CA_REGNO ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CA_REGNO ) ; return NULL ; } </s>

Implement TARGET_MD_ASM_ADJUST . All asm statements are considered to clobber the XER [ CA ] bit because clobbering that bit without telling the compiler worked just fine with versions of GCC before GCC 5 , and breaking a lot of older code in ways that are hard to track down is not such a great idea .


"You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use these intrinsics."

"%Klane index must be a constant immediate"

Expand a Neon builtin , i.e . those registered only if TARGET_NEON holds . Most of these are `` special '' because they do n't have symbolic constants defined per-instruction or per instruction-variant . Instead , the required info is looked up in the table neon_builtin_data .


<s> Value * ARM64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm64_stlxp : Intrinsic :: arm64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall3 ( Stxr , Lo , Hi , Addr ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm64_stlxr : Intrinsic :: arm64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall2 ( Stxr , Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr ) ; } </s>

Perform a store-conditional operation to Addr .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


"After expanding ARM pseudo instructions."


<s>
void
LC3AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
isPCRel
)
const
{
unsigned
NumBytes
=
4
;
Value
=
adjustFixupValue
(
Fixup
,
Value
)
;
if
(
!
Value
)
{
return
;
}
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool Thumb1InstrInfo :: canCopyGluedNodeDuringSchedule ( SDNode * N ) const { unsigned Opcode = N -> getMachineOpcode ( ) ; if ( Opcode == ARM :: tADCS || Opcode == ARM :: tSBCS ) return true ; return false ; } </s>

Return true if the given SDNode can be copied during scheduling even if it has glue .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
PM
.
add
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
getARMSubtarget
(
)
.
hasNEON
(
)
)
PM
.
add
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
PM
.
add
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
addPass
(
IfConverterID
)
;
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
PM
.
add
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM::DPRRegClass
ARM
ARM
ARM


<s> bool X86PassConfig :: addPostRegAlloc ( ) { PM . add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , const AttributeList & FuncAttributes ) const { bool CanImplicitFloat = ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; bool CanUseNEON = Subtarget -> hasNEON ( ) && CanImplicitFloat ; bool CanUseFP = Subtarget -> hasFPARMv8 ( ) && CanImplicitFloat ; bool IsSmallMemset = IsMemset && Size < 32 ; auto AlignmentIsAcceptable = [ & ] ( EVT VT , unsigned AlignCheck ) { if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , 0 , 1 , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: v2i64 , 16 ) ) return MVT :: v2i64 ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( MVT :: f128 , 16 ) ) return MVT :: f128 ; if ( Size >= 8 && AlignmentIsAcceptable ( MVT :: i64 , 8 ) ) return MVT :: i64 ; if ( Size >= 4 && AlignmentIsAcceptable ( MVT :: i32 , 4 ) ) return MVT :: i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> const PPCTargetMachine & getTargetMachine ( ) const { return TM ; } </s>

Return the target machine ( if available ) .


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE2 ( ) || Subtarget . hasX87 ( ) ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( ( VECTOR_MEM_VSX_P ( mode ) && mode != TDmode && mode != TFmode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) reg_size = UNITS_PER_SPE_WORD ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else if ( TARGET_E500_DOUBLE && FLOAT_MODE_P ( mode ) && mode != SCmode && ! DECIMAL_FLOAT_MODE_P ( mode ) && SPE_SIMD_REGNO_P ( regno ) ) reg_size = UNITS_PER_FP_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - 1 ) / reg_size ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s>
bool
CSKYAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
OS
)
{
if
(
!
ExtraCode
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
if
(
!
MO
.
isReg
(
)
)
return
true
;
OS
<<
"("
<<
CSKYInstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
", 0)"
;
return
false
;
}
return
AsmPrinter
::
PrintAsmMemoryOperand
(
MI
,
OpNo
,
ExtraCode
,
OS
)
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool pbsada_insn_rt_dep_reg_p ( rtx pbsada_insn , rtx def_reg ) { rtx pbsada_rt = SET_DEST ( PATTERN ( pbsada_insn ) ) ; if ( rtx_equal_p ( def_reg , pbsada_rt ) ) return true ; return false ; } </s>

Determine if the latency is occured when the consumer PBSADA_INSN uses the value of DEF_REG in its Rt field .


<s>
bool
SystemZDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SystemZAddressingMode
::
AddrForm
Form
;
SystemZAddressingMode
::
DispRange
DispRange
;
SDValue
Base
,
Disp
,
Index
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_i
:
case
InlineAsm
::
Constraint_Q
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_R
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp12Only
;
break
;
case
InlineAsm
::
Constraint_S
:
Form
=
SystemZAddressingMode
::
FormBD
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
case
InlineAsm
::
Constraint_T
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_p
:
Form
=
SystemZAddressingMode
::
FormBDXNormal
;
DispRange
=
SystemZAddressingMode
::
Disp20Only
;
break
;
}
if
(
selectBDXAddr
(
Form
,
DispRange
,
Op
,
Base
,
Disp
,
Index
)
)
{
const
TargetRegisterClass
*
TRC
=
Subtarget
->
getRegisterInfo
(
)
->
getPointerRegClass
(
*
MF
)
;
SDLoc
DL
(
Base
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
DL
,
MVT
::
i32
)
;
if
(
Base
.
getOpcode
(
)
!=
ISD
::
TargetFrameIndex
&&
Base
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Base
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Base
.
getValueType
(
)
,
Base
,
RC
)
,
0
)
;
}
if
(
Index
.
getOpcode
(
)
!=
ISD
::
Register
)
{
Index
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
DL
,
Index
.
getValueType
(
)
,
Index
,
RC
)
,
0
)
;
}
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Disp
)
;
OutOps
.
push_back
(
Index
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> int ix86_attr_length_address_default ( rtx_insn * insn ) { int i ; if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) , addr ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; addr = SET_SRC ( set ) ; return memory_address_length ( addr , true ) ; } extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( MEM_P ( recog_data . operand [ i ] ) ) { constrain_operands_cached ( insn , reload_completed ) ; if ( which_alternative != - 1 ) { const char * constraints = recog_data . constraints [ i ] ; int alt = which_alternative ; while ( * constraints == '=' || * constraints == '+' ) constraints ++ ; while ( alt -- > 0 ) while ( * constraints ++ != ',' ) ; if ( * constraints == 'X' ) continue ; } return memory_address_length ( XEXP ( recog_data . operand [ i ] , 0 ) , false ) ; } return 0 ; } </s>

Compute default value for `` length_address '' attribute .


<s> static rtx rs6000_emit_savres_rtx ( rs6000_stack_t * info , rtx frame_reg_rtx , int save_area_offset , int lr_offset , machine_mode reg_mode , int sel ) { int i ; int offset , start_reg , end_reg , n_regs , use_reg ; int reg_size = GET_MODE_SIZE ( reg_mode ) ; rtx sym ; rtvec p ; rtx par , insn ; offset = 0 ; start_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save : - 1 ) ; end_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? 32 : ( sel & SAVRES_REG ) == SAVRES_FPR ? 64 : ( sel & SAVRES_REG ) == SAVRES_VR ? LAST_ALTIVEC_REGNO + 1 : - 1 ) ; n_regs = end_reg - start_reg ; p = rtvec_alloc ( 3 + ( ( sel & SAVRES_LR ) ? 1 : 0 ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? 1 : 0 ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , 0 ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = 0 ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != 0 ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , 0 ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) { insn = emit_jump_insn ( par ) ; JUMP_LABEL ( insn ) = ret_rtx ; } else insn = emit_insn ( par ) ; return insn ; } </s>

Construct a parallel rtx describing the effect of a call to an out-of-line register save/restore routine , and emit the insn or jump_insn as appropriate .


<s> static unsigned int ix86_autovectorize_vector_sizes ( void ) { return TARGET_AVX512F ? 64 | 32 | 16 : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? 32 | 16 : 0 ; } </s>

If AVX is enabled then try vectorizing with both 256bit and 128bit vectors . If AVX512F is enabled then try vectorizing with 512bit , 256bit and 128bit vectors .


<s> static save_entry * sh5_schedule_saves ( HARD_REG_SET * live_regs_mask , save_schedule * schedule , int offset_base ) { int align , i ; save_entry * entry = schedule -> entries ; int tmpx = 0 ; int offset ; if ( ! current_function_interrupt ) for ( i = FIRST_GENERAL_REG ; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG ; i ++ ) if ( call_really_used_regs [ i ] && ! fixed_regs [ i ] && i != PR_MEDIA_REG && ! FUNCTION_ARG_REGNO_P ( i ) && i != FIRST_RET_REG && ! ( cfun -> static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM ) && ! ( current_function_calls_eh_return && ( i == EH_RETURN_STACKADJ_REGNO || ( ( unsigned ) i >= EH_RETURN_DATA_REGNO ( 0 ) && ( unsigned ) i <= EH_RETURN_DATA_REGNO ( 3 ) ) ) ) ) schedule -> temps [ tmpx ++ ] = i ; entry -> reg = - 1 ; entry -> mode = VOIDmode ; entry -> offset = offset_base ; entry ++ ; offset = offset_base ; for ( align = 1 ; align >= 0 ; align -- ) { for ( i = FIRST_PSEUDO_REGISTER - 1 ; i >= 0 ; i -- ) if ( TEST_HARD_REG_BIT ( * live_regs_mask , i ) ) { enum machine_mode mode = REGISTER_NATURAL_MODE ( i ) ; int reg = i ; if ( current_function_interrupt ) { if ( TARGET_REGISTER_P ( i ) ) continue ; if ( GENERAL_REGISTER_P ( i ) ) mode = DImode ; } if ( mode == SFmode && ( i % 2 ) == 1 && ! TARGET_FPU_SINGLE && FP_REGISTER_P ( i ) && ( TEST_HARD_REG_BIT ( * live_regs_mask , ( i ^ 1 ) ) ) ) { mode = DFmode ; i -- ; reg -- ; } if ( ( GET_MODE_SIZE ( mode ) % ( STACK_BOUNDARY / BITS_PER_UNIT ) == 0 ) != align ) continue ; if ( current_function_interrupt && GENERAL_REGISTER_P ( i ) && tmpx < MAX_TEMPS ) schedule -> temps [ tmpx ++ ] = i ; offset -= GET_MODE_SIZE ( mode ) ; entry -> reg = i ; entry -> mode = mode ; entry -> offset = offset ; entry ++ ; } if ( align && current_function_interrupt ) for ( i = LAST_TARGET_REG ; i >= FIRST_TARGET_REG ; i -- ) if ( TEST_HARD_REG_BIT ( * live_regs_mask , i ) ) { offset -= GET_MODE_SIZE ( DImode ) ; entry -> reg = i ; entry -> mode = DImode ; entry -> offset = offset ; entry ++ ; } } entry -> reg = - 1 ; entry -> mode = VOIDmode ; entry -> offset = offset ; schedule -> temps [ tmpx ] = - 1 ; return entry - 1 ; } </s>

Fill in SCHEDULE according to LIVE_REGS_MASK . If RESTORE is nonzero , use reverse order . Returns the last entry written to ( not counting the delimiter ) . OFFSET_BASE is a number to be added to all offset entries .


<s> const char * output_branch ( int logic , rtx_insn * insn , rtx * operands ) { switch ( get_attr_length ( insn ) ) { case 6 : if ( ! TARGET_RELAX ) { int label = lf ++ ; rtx op0 = operands [ 0 ] ; if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( final_sequence -> insn ( 0 ) ) && get_attr_length ( final_sequence -> insn ( 1 ) ) ) { asm_fprintf ( asm_out_file , "\tb%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; print_slot ( final_sequence ) ; } else asm_fprintf ( asm_out_file , "\tb%s\t%LLF%d\n" , logic ? "f" : "t" , label ) ; output_asm_insn ( "bra\t%l0" , & op0 ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 2 : return logic ? "bt%.\t%l0" : "bf%.\t%l0" ; case 8 : if ( ! TARGET_RELAX ) { int label = lf ++ ; gcc_assert ( ! final_sequence || ! ( INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , 0 , 0 ) ) ) ) ; asm_fprintf ( asm_out_file , "b%s%ss\t%LLF%d\n" , logic ? "f" : "t" , ASSEMBLER_DIALECT ? "/" : "." , label ) ; fprintf ( asm_out_file , "\tnop\n" ) ; output_asm_insn ( "bra\t%l0" , operands ) ; fprintf ( asm_out_file , "\tnop\n" ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , "LF" , label ) ; return "" ; } case 4 : { char buffer [ 10 ] ; sprintf ( buffer , "b%s%ss\t%%l0" , logic ? "t" : "f" , ASSEMBLER_DIALECT ? "/" : "." ) ; output_asm_insn ( buffer , & operands [ 0 ] ) ; return "nop" ; } default : gcc_unreachable ( ) ; } } </s>

Output a conditional/unconditional branch to LABEL . COND is the string condition . INSN is the instruction .


<s> int csky_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { ( ( CLASS ) == GENERAL_REGS || ( CLASS ) == MINI_REGS || ( CLASS ) == SP_REGS \ || ( CLASS ) == LOW_REGS ) ( ( CLASS ) == HILO_REGS ) ( ( CLASS ) == V_REGS ) if ( V_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) return 2 ; if ( ( V_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) ) return 6 ; if ( ( HILO_REG_CLASS_P ( from ) && GR_REG_CLASS_P ( to ) ) || ( GR_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return 16 ; if ( HILO_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) return 32 ; if ( ( HILO_REG_CLASS_P ( from ) && V_REG_CLASS_P ( to ) ) || ( V_REG_CLASS_P ( from ) && HILO_REG_CLASS_P ( to ) ) ) return 64 ; return 2 ; } </s>

Implement TARGET_REGISTER_MOVE_COST : compute extra cost of moving data between one register class and another .


<s> bool AArch64InstrInfo :: isPreLdSt ( const MachineInstr & MI ) { return isPreLd ( MI ) || isPreSt ( MI ) ; } </s>

Returns whether the instruction is a pre-indexed load/store .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return Subtarget . is64Bit ( ) ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool mayNeedRelaxation ( const MCInst & , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . isPPC64 ( ) ; const TargetRegisterClass * G8RC = & PPC :: G8RCRegClass ; const TargetRegisterClass * GPRC = & PPC :: GPRCRegClass ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFCR8pseud : PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) { unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; } addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( const MCSubtargetInfo & STI ) const { if ( STI . hasFeature ( X86 :: Is16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Is64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s>
const
char
*
output_fp_compare
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
eflags_p
,
bool
unordered_p
)
{
int
stack_top_dies
;
rtx
cmp_op0
,
cmp_op1
;
int
is_sse
=
SSE_REG_P
(
operands
[
0
]
)
||
SSE_REG_P
(
operands
[
1
]
)
;
if
(
eflags_p
)
{
cmp_op0
=
operands
[
0
]
;
cmp_op1
=
operands
[
1
]
;
}
else
{
cmp_op0
=
operands
[
1
]
;
cmp_op1
=
operands
[
2
]
;
}
if
(
is_sse
)
{
if
(
GET_MODE
(
operands
[
0
]
)
==
SFmode
)
if
(
unordered_p
)
return
"%vucomiss\t{%1, %0|%0, %1}"
;
else
return
"%vcomiss\t{%1, %0|%0, %1}"
;
else
if
(
unordered_p
)
return
"%vucomisd\t{%1, %0|%0, %1}"
;
else
return
"%vcomisd\t{%1, %0|%0, %1}"
;
}
gcc_assert
(
STACK_TOP_P
(
cmp_op0
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
!=
0
;
if
(
cmp_op1
==
CONST0_RTX
(
GET_MODE
(
cmp_op1
)
)
)
{
if
(
stack_top_dies
)
{
output_asm_insn
(
"ftst\n\tfnstsw\t%0"
,
operands
)
;
return
output_387_ffreep
(
operands
,
1
)
;
}
else
return
"ftst\n\tfnstsw\t%0"
;
}
if
(
STACK_REG_P
(
cmp_op1
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
REGNO
(
cmp_op1
)
)
&&
REGNO
(
cmp_op1
)
!=
FIRST_STACK_REG
)
{
if
(
eflags_p
)
{
if
(
unordered_p
)
output_asm_insn
(
"fucomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
else
output_asm_insn
(
"fcomip\t{%y1, %0|%0, %y1}"
,
operands
)
;
return
output_387_ffreep
(
operands
,
0
)
;
}
else
{
if
(
unordered_p
)
return
"fucompp\n\tfnstsw\t%0"
;
else
return
"fcompp\n\tfnstsw\t%0"
;
}
}
else
{
static
const
char
*
const
alt
[
16
]
=
{
"fcom%Z2\t%y2\n\tfnstsw\t%0"
,
"fcomp%Z2\t%y2\n\tfnstsw\t%0"
,
"fucom%Z2\t%y2\n\tfnstsw\t%0"
,
"fucomp%Z2\t%y2\n\tfnstsw\t%0"
,
"ficom%Z2\t%y2\n\tfnstsw\t%0"
,
"ficomp%Z2\t%y2\n\tfnstsw\t%0"
,
,
,
"fcomi\t{%y1, %0|%0, %y1}"
,
"fcomip\t{%y1, %0|%0, %y1}"
,
"fucomi\t{%y1, %0|%0, %y1}"
,
"fucomip\t{%y1, %0|%0, %y1}"
,
,
,
,
}
;
int
mask
;
const
char
*
ret
;
mask
=
eflags_p
<<
3
;
mask
|=
(
GET_MODE_CLASS
(
GET_MODE
(
cmp_op1
)
)
==
MODE_INT
)
<<
2
;
mask
|=
unordered_p
<<
1
;
mask
|=
stack_top_dies
;
gcc_assert
(
mask
<
16
)
;
ret
=
alt
[
mask
]
;
gcc_assert
(
ret
)
;
return
ret
;
}
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s> void SystemZRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
void
Cpu0SEFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
Cpu0MachineFunctionInfo
*
Cpu0FI
=
MF
.
getInfo
<
Cpu0MachineFunctionInfo
>
(
)
;
const
Cpu0SEInstrInfo
&
TII
=
*
static_cast
<
const
Cpu0SEInstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
const
Cpu0RegisterInfo
&
RegInfo
=
*
static_cast
<
const
Cpu0RegisterInfo
*
>
(
STI
.
getRegisterInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
Cpu0ABIInfo
ABI
=
STI
.
getABI
(
)
;
unsigned
SP
=
Cpu0
::
SP
;
const
TargetRegisterClass
*
RC
=
&
Cpu0
::
GPROutRegClass
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
TII
.
adjustStackPtr
(
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
for
(
unsigned
i
=
0
;
i
<
CSI
.
size
(
)
;
++
i
)
++
MBBI
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
{
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
MRI
->
getDwarfRegNum
(
Reg
,
1
)
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void AArch64BranchRelaxation :: verify ( ) { unsigned PrevNum = MF -> begin ( ) -> getNumber ( ) ; for ( MachineBasicBlock & MBB : * MF ) { unsigned Align = MBB . getAlignment ( ) ; unsigned Num = MBB . getNumber ( ) ; assert ( BlockInfo [ Num ] . Offset % ( 1u << Align ) == 0 ) ; assert ( ! Num || BlockInfo [ PrevNum ] . postOffset ( ) <= BlockInfo [ Num ] . Offset ) ; PrevNum = Num ; } } </s>


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
tree
target_parts
=
DECL_FUNCTION_SPECIFIC_TARGET
(
decl
)
;
struct
cl_target_option
*
targ_options
;
if
(
target_parts
)
targ_options
=
TREE_TARGET_OPTION
(
target_parts
)
;
else
targ_options
=
TREE_TARGET_OPTION
(
target_option_current_node
)
;
gcc_assert
(
targ_options
)
;
arm_print_asm_arch_directives
(
stream
,
targ_options
)
;
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } else if ( Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSFRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s>
const
char
*
nds32_output_16bit_load
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
nds32_mem_format
(
operands
[
1
]
)
)
{
case
ADDRESS_REG
:
operands
[
1
]
=
code
;
output_asm_insn
(
"lwi450\t%0, [%1]"
,
operands
)
;
break
;
case
ADDRESS_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci333\t%%0, %%1"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_INC_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci333.bi\t%%0, %%1"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_FP_IMM7U
:
output_asm_insn
(
"lwi37\t%0, %1"
,
operands
)
;
break
;
case
ADDRESS_SP_IMM7U
:
operands
[
1
]
=
XEXP
(
code
,
1
)
;
output_asm_insn
(
"lwi37.sp\t%0, [ + (%1)]"
,
operands
)
;
break
;
default
:
break
;
}
return
""
;
}
</s>


<s> rtx sh_movrt_set_dest ( const rtx_insn * i ) { if ( i == NULL ) return NULL ; const_rtx p = PATTERN ( i ) ; if ( GET_CODE ( p ) == PARALLEL ) p = XVECEXP ( p , 0 , 0 ) ; return GET_CODE ( p ) == SET && arith_reg_dest ( XEXP ( p , 0 ) , SImode ) && negt_reg_operand ( XEXP ( p , 1 ) , VOIDmode ) ? XEXP ( p , 0 ) : NULL ; } </s>

Given an insn , check whether it 's a 'movrt ' kind of insn , i.e . an insn that stores the negated T bit in a register , and return the destination register rtx , or null .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AArch64SIMDInstrOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( & ST ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; bool Changed = false ; for ( auto OptimizationKind : { VectorElem , Interleave } ) { if ( ! shouldExitEarly ( & MF , OptimizationKind ) ) { SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ; bool InstRewrite ; if ( OptimizationKind == VectorElem ) InstRewrite = optimizeVectElement ( MI ) ; else InstRewrite = optimizeLdStInterleave ( MI ) ; if ( InstRewrite ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } ++ MII ; } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> Candidate ( ) : SU ( nullptr ) , GroupingCost ( 0 ) , ResourcesCost ( 0 ) { } </s>


<s> const unsigned * ARMRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { ARM :: LR , ARM :: R11 , ARM :: R10 , ARM :: R9 , ARM :: R8 , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; static const unsigned DarwinCalleeSavedRegs [ ] = { ARM :: LR , ARM :: R7 , ARM :: R6 , ARM :: R5 , ARM :: R4 , ARM :: R11 , ARM :: R10 , ARM :: R9 , ARM :: R8 , ARM :: D15 , ARM :: D14 , ARM :: D13 , ARM :: D12 , ARM :: D11 , ARM :: D10 , ARM :: D9 , ARM :: D8 , 0 } ; return STI . isTargetDarwin ( ) ? DarwinCalleeSavedRegs : CalleeSavedRegs ; } </s>


"ACLE function %qD is incompatible with the use of %qs"

Check whether the registers required by SVE function fndecl are available . Report an error against LOCATION and return false if not .


<s> static void add_constant ( int dest , int src , int value , int mark_frame ) { rtx_insn * insn ; int hi , lo ; if ( src == dest && value == 0 ) return ; if ( value == 0 ) { insn = emit_move_insn ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) ) ; if ( mark_frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; return ; } if ( value >= - 32768 && value <= 32767 ) { insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , GEN_INT ( value ) ) ) ; if ( mark_frame ) RTX_FRAME_RELATED_P ( insn ) = 1 ; return ; } hi = trunc_int_for_mode ( value & 0xffff0000 , SImode ) ; lo = value & 0xffff ; insn = emit_move_insn ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( hi ) ) ; if ( lo ) { insn = emit_insn ( gen_iorsi3 ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( lo ) ) ) ; } insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) ) ) ; if ( mark_frame ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , dest ) , gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , dest ) , GEN_INT ( value ) ) ) ) ; } } </s>

Add a constant to the pool and return its label .


<s> virtual const ARMRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .