<s>
void
PPCHazardRecognizer970
::
EmitInstruction
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
Opcode
==
PPC
::
MTCTR
)
HasCTRSet
=
true
;
if
(
isStore
)
{
unsigned
ThisStoreSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown store instruction!"
)
;
case
PPC
::
STB
:
case
PPC
::
STB8
:
case
PPC
::
STBU
:
case
PPC
::
STBU8
:
case
PPC
::
STBX
:
case
PPC
::
STBX8
:
case
PPC
::
STVEBX
:
ThisStoreSize
=
1
;
break
;
case
PPC
::
STH
:
case
PPC
::
STH8
:
case
PPC
::
STHU
:
case
PPC
::
STHU8
:
case
PPC
::
STHX
:
case
PPC
::
STHX8
:
case
PPC
::
STVEHX
:
case
PPC
::
STHBRX
:
ThisStoreSize
=
2
;
break
;
case
PPC
::
STFS
:
case
PPC
::
STFSU
:
case
PPC
::
STFSX
:
case
PPC
::
STWX
:
case
PPC
::
STWX8
:
case
PPC
::
STWUX
:
case
PPC
::
STW
:
case
PPC
::
STW8
:
case
PPC
::
STWU
:
case
PPC
::
STVEWX
:
case
PPC
::
STFIWX
:
case
PPC
::
STWBRX
:
ThisStoreSize
=
4
;
break
;
case
PPC
::
STD_32
:
case
PPC
::
STDX_32
:
case
PPC
::
STD
:
case
PPC
::
STDU
:
case
PPC
::
STFD
:
case
PPC
::
STFDX
:
case
PPC
::
STDX
:
case
PPC
::
STDUX
:
ThisStoreSize
=
8
;
break
;
case
PPC
::
STVX
:
case
PPC
::
STVXL
:
ThisStoreSize
=
16
;
break
;
}
StoreSize
[
NumStores
]
=
ThisStoreSize
;
StorePtr1
[
NumStores
]
=
Node
->
getOperand
(
1
)
;
StorePtr2
[
NumStores
]
=
Node
->
getOperand
(
2
)
;
++
NumStores
;
}
if
(
InstrType
==
PPCII
::
PPC970_BRU
||
isSingle
)
NumIssued
=
4
;
++
NumIssued
;
if
(
isCracked
)
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
void
thumb1_final_prescan_insn
(
rtx_insn
*
insn
)
{
if
(
flag_print_asm_name
)
asm_fprintf
(
asm_out_file
,
"%@ 0x%04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
INSN_CODE
(
insn
)
!=
CODE_FOR_cbranchsi4_insn
)
{
enum
attr_conds
conds
;
if
(
cfun
->
machine
->
thumb1_cc_insn
)
{
if
(
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op0
,
insn
)
||
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op1
,
insn
)
)
CC_STATUS_INIT
;
}
conds
=
get_attr_conds
(
insn
)
;
if
(
conds
==
CONDS_SET
)
{
rtx
set
=
single_set
(
insn
)
;
cfun
->
machine
->
thumb1_cc_insn
=
insn
;
cfun
->
machine
->
thumb1_cc_op0
=
SET_DEST
(
set
)
;
cfun
->
machine
->
thumb1_cc_op1
=
const0_rtx
;
cfun
->
machine
->
thumb1_cc_mode
=
CC_NOOVmode
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_thumb1_subsi3_insn
)
{
rtx
src1
=
XEXP
(
SET_SRC
(
set
)
,
1
)
;
if
(
src1
==
const0_rtx
)
cfun
->
machine
->
thumb1_cc_mode
=
CCmode
;
}
else
if
(
REG_P
(
SET_DEST
(
set
)
)
&&
REG_P
(
SET_SRC
(
set
)
)
)
{
cfun
->
machine
->
thumb1_cc_op0
=
SET_SRC
(
set
)
;
}
}
else
if
(
conds
!=
CONDS_NOCOND
)
cfun
->
machine
->
thumb1_cc_insn
=
NULL_RTX
;
}
if
(
cfun
->
machine
->
lr_save_eliminated
&&
get_attr_far_jump
(
insn
)
==
FAR_JUMP_YES
)
internal_error
(
"Unexpected thumb1 far jump"
)
;
}
</s>

Scan INSN just before assembler is output for it . For Thumb-1 , we track the status of the condition codes ; this information is used in the cbranchsi4_insn pattern .

arm
"%@ 0x%04x\n"
1
"Unexpected thumb1 far jump"


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Subtarget . isSVR4ABI ( ) && PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { if ( Subtarget . isPPC64 ( ) ) { FrameIdx = 0 ; } else if ( CRSpillFrameIdx ) { FrameIdx = CRSpillFrameIdx ; } else { MachineFrameInfo * MFI = ( ( MachineFunction & ) MF ) . getFrameInfo ( ) ; FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; CRSpillFrameIdx = FrameIdx ; } return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createX86IndirectBranchTrackingPass ( ) ) ; addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } addPass ( createX86EvexToVexInsts ( ) ) ; addPass ( createX86DiscriminateMemOpsPass ( ) ) ; addPass ( createX86InsertPrefetchPass ( ) ) ; addPass ( createX86InsertX87waitPass ( ) ) ; addPass ( createX86EncodeLiterals ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool sh_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( to == SFmode && VECTOR_MODE_P ( from ) && GET_MODE_INNER ( from ) == SFmode ) return optimize ? ! reg_classes_intersect_p ( GENERAL_REGS , rclass ) : true ; if ( GET_MODE_SIZE ( from ) != GET_MODE_SIZE ( to ) ) { if ( TARGET_LITTLE_ENDIAN ) { if ( GET_MODE_SIZE ( to ) < 8 || GET_MODE_SIZE ( from ) < 8 ) return ! reg_classes_intersect_p ( DF_REGS , rclass ) ; } else { if ( GET_MODE_SIZE ( from ) < 8 ) return ! reg_classes_intersect_p ( DF_REGS , rclass ) ; } } return true ; } </s>


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_Ghc_SaveList ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> static void get_scratch_register_on_entry ( struct scratch_reg * sr ) { int regno ; sr -> saved = false ; if ( TARGET_64BIT ) { regno = R11_REG ; } else { tree decl = current_function_decl , fntype = TREE_TYPE ( decl ) ; bool fastcall_p = lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool thiscall_p = lookup_attribute ( "thiscall" , TYPE_ATTRIBUTES ( fntype ) ) != NULL_TREE ; bool static_chain_p = DECL_STATIC_CHAIN ( decl ) ; int regparm = ix86_function_regparm ( fntype , decl ) ; int drap_regno = crtl -> drap_reg ? REGNO ( crtl -> drap_reg ) : INVALID_REGNUM ; if ( ( regparm < 1 || ( fastcall_p && ! static_chain_p ) ) && drap_regno != AX_REG ) regno = AX_REG ; else if ( thiscall_p && ! static_chain_p && drap_regno != AX_REG ) regno = AX_REG ; else if ( regparm < 2 && ! thiscall_p && drap_regno != DX_REG ) regno = DX_REG ; else if ( regparm < 3 && ! fastcall_p && ! thiscall_p && ! static_chain_p && drap_regno != CX_REG ) regno = CX_REG ; else if ( ix86_save_reg ( BX_REG , true , false ) ) regno = BX_REG ; else if ( ! ( regparm == 3 && static_chain_p ) && ix86_save_reg ( SI_REG , true , false ) ) regno = SI_REG ; else if ( ix86_save_reg ( DI_REG , true , false ) ) regno = DI_REG ; else { regno = ( drap_regno == AX_REG ? DX_REG : AX_REG ) ; sr -> saved = true ; } } sr -> reg = gen_rtx_REG ( Pmode , regno ) ; if ( sr -> saved ) { rtx_insn * insn = emit_insn ( gen_push ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Return a short-lived scratch register for use on function entry . In 32-bit mode , it is valid only after the registers are saved in the prologue . This register must be released by means of release_scratch_register_on_entry once it is dead .


<s> void ARMConstantPoolMBB :: print ( raw_ostream & O ) const { O << "BB#" << MBB -> getNumber ( ) ; ARMConstantPoolValue :: print ( O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> bool ARM64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( ! DoLoadStoreOpt ) return false ; const TargetMachine & TM = Fn . getTarget ( ) ; TII = static_cast < const ARM64InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> static sbitmap aarch64_get_separate_components ( void ) { sbitmap components = sbitmap_alloc ( LAST_SAVED_REGNUM + 1 ) ; bitmap_clear ( components ) ; for ( unsigned regno = 0 ; regno <= LAST_SAVED_REGNUM ; regno ++ ) if ( aarch64_register_saved_on_entry ( regno ) ) { poly_int64 offset = cfun -> machine -> frame . reg_offset [ regno ] ; if ( ! frame_pointer_needed ) offset += cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( offset_12bit_unsigned_scaled_p ( DImode , offset ) ) bitmap_set_bit ( components , regno ) ; } if ( frame_pointer_needed ) bitmap_clear_bit ( components , HARD_FRAME_POINTER_REGNUM ) ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; if ( reg2 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg2 ) ; if ( reg1 != INVALID_REGNUM ) bitmap_clear_bit ( components , reg1 ) ; bitmap_clear_bit ( components , LR_REGNUM ) ; bitmap_clear_bit ( components , SP_REGNUM ) ; return components ; } </s>


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> bool X86TargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void rs6000_emit_le_vsx_permute ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! altivec_indexed_or_indirect_operand ( dest , mode ) ) ; gcc_assert ( ! altivec_indexed_or_indirect_operand ( source , mode ) ) ; if ( FLOAT128_VECTOR_P ( mode ) ) { dest = gen_lowpart ( V1TImode , dest ) ; source = gen_lowpart ( V1TImode , source ) ; mode = V1TImode ; } if ( mode == TImode || mode == V1TImode ) emit_insn ( gen_rtx_SET ( dest , gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_VEC_SELECT ( mode , source , par ) ) ) ; } } </s>

Emit an lxvd2x , stxvd2x , or xxpermdi instruction for a VSX load or store operation .


<s> bool X86TargetLowering :: shouldScalarizeBinop ( SDValue VecOp ) const { unsigned Opc = VecOp . getOpcode ( ) ; if ( Opc >= ISD :: BUILTIN_OP_END ) return false ; EVT VecVT = VecOp . getValueType ( ) ; if ( ! isOperationLegalOrCustomOrPromote ( Opc , VecVT ) ) return true ; EVT ScalarVT = VecVT . getScalarType ( ) ; return isOperationLegalOrCustomOrPromote ( Opc , ScalarVT ) ; } </s>

Scalar ops always have equal or better analysis/performance/power than the vector equivalent , so this always makes sense if the scalar op is supported .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; if ( Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_64_SwiftError_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: ANY_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


"The function works only with LEA instructions"


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> static bool aarch64_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( TARGET_SIMD && aarch64_vect_struct_mode_p ( mode ) ) return false ; if ( ( GET_CODE ( x ) == CONST_VECTOR && aarch64_simd_valid_immediate ( x , mode , false , NULL ) ) || CONST_INT_P ( x ) || aarch64_valid_floating_const ( mode , x ) ) return ! targetm . cannot_force_const_mem ( mode , x ) ; if ( GET_CODE ( x ) == HIGH && aarch64_valid_symref ( XEXP ( x , 0 ) , GET_MODE ( XEXP ( x , 0 ) ) ) ) return true ; return aarch64_constant_address_p ( x ) ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P hook . Return true for constants that should be rematerialized rather than spilled .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , 0 ) ; if ( mode == BLKmode ) { intoffset = intoffset & - BITS_PER_WORD ; mode = word_mode ; } } else mode = word_mode ; startbit = intoffset & - BITS_PER_WORD ; endbit = ( bitpos + BITS_PER_WORD - 1 ) & - BITS_PER_WORD ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


"operation not permitted on type %<bfloat16_t%>"

Return the diagnostic message string if the unary operation OP is not permitted on TYPE , NULL otherwise .


<s> static bool originalEVTTypeIsVectorFloat ( EVT Ty ) { if ( Ty . isVector ( ) && Ty . getVectorElementType ( ) . isFloatingPoint ( ) ) return true ; return false ; } </s>

Return true if the original type was vXfXX .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: MEMBARRIER : return PerformMEMBARRIERCombine ( N , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
HOST_WIDE_INT
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
OPTION_MASK_PPC_GPOPT
|
OPTION_MASK_MFCRF
\
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
OPTION_MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
darwin_file_start
(
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_default_cpu
;
if
(
OPTION_SET_P
(
rs6000_cpu_index
)
)
cpu_id
=
processor_target_table
[
rs6000_cpu_index
]
.
name
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
rs6000_isa_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .


<s> bool isMem ( ) const { return isMEMrr ( ) || isMEMri ( ) ; } </s>


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: TlsGd : return "MipsISD::TlsGd" ; case MipsISD :: TprelHi : return "MipsISD::TprelHi" ; case MipsISD :: TprelLo : return "MipsISD::TprelLo" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: WrapperPIC : return "MipsISD::WrapperPIC" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::TlsGd "MipsISD::TlsGd" MipsISD::TprelHi "MipsISD::TprelHi" MipsISD::TprelLo "MipsISD::TprelLo" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::WrapperPIC "MipsISD::WrapperPIC" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins"


<s> static void emit_final_str_compare_gpr ( rtx str1 , rtx str2 , rtx result ) { machine_mode m = GET_MODE ( str1 ) ; rtx rot_amt = gen_reg_rtx ( m ) ; rtx rot1_1 = gen_reg_rtx ( m ) ; rtx rot1_2 = gen_reg_rtx ( m ) ; rtx rot2_1 = gen_reg_rtx ( m ) ; rtx rot2_2 = gen_reg_rtx ( m ) ; if ( m == SImode ) { emit_insn ( gen_clzsi2 ( rot_amt , result ) ) ; emit_insn ( gen_addsi3 ( rot_amt , rot_amt , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_rotlsi3 ( rot1_1 , str1 , gen_lowpart ( SImode , rot_amt ) ) ) ; emit_insn ( gen_andsi3_mask ( rot1_2 , rot1_1 , GEN_INT ( 0xff ) ) ) ; emit_insn ( gen_rotlsi3 ( rot2_1 , str2 , gen_lowpart ( SImode , rot_amt ) ) ) ; emit_insn ( gen_andsi3_mask ( rot2_2 , rot2_1 , GEN_INT ( 0xff ) ) ) ; emit_insn ( gen_subsi3 ( result , rot1_2 , rot2_2 ) ) ; } else if ( m == DImode ) { emit_insn ( gen_clzdi2 ( rot_amt , result ) ) ; emit_insn ( gen_adddi3 ( rot_amt , rot_amt , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_rotldi3 ( rot1_1 , str1 , gen_lowpart ( SImode , rot_amt ) ) ) ; emit_insn ( gen_anddi3_mask ( rot1_2 , rot1_1 , GEN_INT ( 0xff ) ) ) ; emit_insn ( gen_rotldi3 ( rot2_1 , str2 , gen_lowpart ( SImode , rot_amt ) ) ) ; emit_insn ( gen_anddi3_mask ( rot2_2 , rot2_1 , GEN_INT ( 0xff ) ) ) ; emit_insn ( gen_subdi3 ( result , rot1_2 , rot2_2 ) ) ; } else gcc_unreachable ( ) ; return ; } </s>

Generate the final sequence that identifies the differing byte and generates the final result , taking into account zero bytes : cntlzd get bit of first zero/diff byte addi convert for rldcl use rldcl rldcl extract diff/zero byte subf subtract for final result STR1 is the reg rtx for data from string 1 . STR2 is the reg rtx for data from string 2 . RESULT is the reg rtx for the comparison result .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableSVEPostVec ) { addPass ( createSVEAddressingModesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } return false ; } </s>


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Searching for mode conversion candidates...\n"

"There are no candidates for optimization.\n"

"Chain #%d conversion is not profitable\n"

Main STV pass function . Find and convert scalar instructions into vector mode when profitable .


<s> static bool aarch64_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { pure_scalable_type_info pst_info ; switch ( pst_info . analyze ( type ) ) { case pure_scalable_type_info :: IS_PST : return ( pst_info . num_zr ( ) > NUM_FP_ARG_REGS || pst_info . num_pr ( ) > NUM_PR_ARG_REGS ) ; case pure_scalable_type_info :: DOESNT_MATTER : gcc_assert ( aarch64_return_in_memory_1 ( type ) ) ; return true ; case pure_scalable_type_info :: NO_ABI_IDENTITY : case pure_scalable_type_info :: ISNT_PST : return aarch64_return_in_memory_1 ( type ) ; } gcc_unreachable ( ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY . If the type T of the result of a function is such that void func ( T arg ) would require that arg be passed as a value in a register ( or set of registers ) according to the parameter passing rules , then the result is returned in the same registers as would be used for such an argument .


<s> static rtx aarch64_struct_value_rtx ( tree fndecl ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , AARCH64_STRUCT_VALUE_REGNUM ) ; } </s>


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . isOSWindows ( ) || TargetABI == ARMBaseTargetMachine :: ARM_ABI_AAPCS16 ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } initAsmInfo ( ) ; } </s>


<s> static rtx mips_find_pic_call_symbol ( rtx_insn * insn , rtx reg , bool recurse_p ) { df_ref use ; struct df_link * defs ; rtx symbol ; use = df_find_use ( insn , regno_reg_rtx [ REGNO ( reg ) ] ) ; if ( ! use ) return NULL_RTX ; defs = DF_REF_CHAIN ( use ) ; if ( ! defs ) return NULL_RTX ; symbol = mips_pic_call_symbol_from_set ( defs -> ref , reg , recurse_p ) ; if ( ! symbol ) return NULL_RTX ; for ( defs = defs -> next ; defs ; defs = defs -> next ) { rtx other ; other = mips_pic_call_symbol_from_set ( defs -> ref , reg , recurse_p ) ; if ( ! rtx_equal_p ( symbol , other ) ) return NULL_RTX ; } return symbol ; } </s>

Find the definition of the use of REG in INSN . See if the definition is one of the ways we load a register with a symbol address for a mips_use_pic_fn_addr_reg_p call . If it is return the symbol reference of the function , otherwise return NULL_RTX . RECURSE_P is as for mips_pic_call_symbol_from_set .


<s> static int dispatch_function_versions ( tree dispatch_decl , void * fndecls_p , basic_block * empty_bb ) { tree default_decl ; gimple * ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = 0 ; unsigned int actual_versions = 0 ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= 2 ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - 1 ) ) ; default_decl = ( * fndecls ) [ 0 ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( get_ix86_builtin ( IX86_BUILTIN_CPU_INIT ) , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = 1 ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority = priority ; actual_versions ++ ; } qsort ( function_version_info , actual_versions , sizeof ( struct _function_version_info ) , feature_compare ) ; for ( i = 0 ; i < actual_versions ; ++ i ) * empty_bb = add_condition_to_bb ( dispatch_decl , function_version_info [ i ] . version_decl , function_version_info [ i ] . predicate_chain , * empty_bb ) ; * empty_bb = add_condition_to_bb ( dispatch_decl , default_decl , NULL , * empty_bb ) ; free ( function_version_info ) ; return 0 ; } </s>

This function generates the dispatch function for multi-versioned functions . DISPATCH_DECL is the function which will contain the dispatch logic . FNDECLS are the function choices for dispatch , and is a tree chain . EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch code is generated .


<s> unsigned getTOCSaveOffset ( ) const { return TOCSaveOffset ; } </s>

getTOCSaveOffset - Return the previous frame offset to save the TOC register � ? 64-bit SVR4 ABI only .


"We have a different number of location and args?!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void MipsSETargetLowering :: addMSAIntType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: EXTRACT_VECTOR_ELT , Ty , Custom ) ; setOperationAction ( ISD :: INSERT_VECTOR_ELT , Ty , Legal ) ; setOperationAction ( ISD :: BUILD_VECTOR , Ty , Custom ) ; setOperationAction ( ISD :: ADD , Ty , Legal ) ; setOperationAction ( ISD :: AND , Ty , Legal ) ; setOperationAction ( ISD :: CTLZ , Ty , Legal ) ; setOperationAction ( ISD :: CTPOP , Ty , Legal ) ; setOperationAction ( ISD :: MUL , Ty , Legal ) ; setOperationAction ( ISD :: OR , Ty , Legal ) ; setOperationAction ( ISD :: SDIV , Ty , Legal ) ; setOperationAction ( ISD :: SREM , Ty , Legal ) ; setOperationAction ( ISD :: SHL , Ty , Legal ) ; setOperationAction ( ISD :: SRA , Ty , Legal ) ; setOperationAction ( ISD :: SRL , Ty , Legal ) ; setOperationAction ( ISD :: SUB , Ty , Legal ) ; setOperationAction ( ISD :: UDIV , Ty , Legal ) ; setOperationAction ( ISD :: UREM , Ty , Legal ) ; setOperationAction ( ISD :: VECTOR_SHUFFLE , Ty , Custom ) ; setOperationAction ( ISD :: VSELECT , Ty , Legal ) ; setOperationAction ( ISD :: XOR , Ty , Legal ) ; if ( Ty == MVT :: v4i32 || Ty == MVT :: v2i64 ) { setOperationAction ( ISD :: FP_TO_SINT , Ty , Legal ) ; setOperationAction ( ISD :: FP_TO_UINT , Ty , Legal ) ; setOperationAction ( ISD :: SINT_TO_FP , Ty , Legal ) ; setOperationAction ( ISD :: UINT_TO_FP , Ty , Legal ) ; } setOperationAction ( ISD :: SETCC , Ty , Legal ) ; setCondCodeAction ( ISD :: SETNE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGT , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGT , Ty , Expand ) ; } </s>

Enable MSA support for the given integer type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::BITCAST ISD::LOAD ISD::STORE ISD::EXTRACT_VECTOR_ELT ISD::INSERT_VECTOR_ELT ISD::BUILD_VECTOR ISD::ADD ISD::AND ISD::CTLZ ISD::CTPOP ISD::MUL ISD::OR ISD::SDIV ISD::SREM ISD::SHL ISD::SRA ISD::SRL ISD::SUB ISD::UDIV ISD::UREM ISD::VECTOR_SHUFFLE ISD::VSELECT ISD::XOR MVT::v4i32 MVT::v2i64 ISD::FP_TO_SINT ISD::FP_TO_UINT ISD::SINT_TO_FP ISD::UINT_TO_FP ISD::SETCC ISD::SETNE ISD::SETGE ISD::SETGT ISD::SETUGE ISD::SETUGT


<s> bool sh_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( SPECIAL_REGISTER_P ( regno ) ) return mode == SImode ; if ( regno == FPUL_REG ) return ( mode == SImode || mode == SFmode ) ; if ( FP_REGISTER_P ( regno ) && mode == SFmode ) return true ; if ( mode == V2SFmode ) { if ( ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 2 == 0 ) || GENERAL_REGISTER_P ( regno ) ) ) return true ; else return false ; } if ( mode == V4SFmode ) { if ( ( FP_REGISTER_P ( regno ) && ( regno - FIRST_FP_REG ) % 4 == 0 ) || GENERAL_REGISTER_P ( regno ) ) return true ; else return false ; } if ( mode == V16SFmode ) return regno == FIRST_XD_REG ; if ( FP_REGISTER_P ( regno ) ) { if ( mode == SFmode || mode == SImode || ( ( TARGET_SH2E ) && mode == SCmode ) || ( ( ( TARGET_FPU_DOUBLE && mode == DFmode ) || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & 1 ) == 0 ) || ( TARGET_SH4 && mode == TImode && ( ( regno - FIRST_FP_REG ) & 3 ) == 0 ) ) return true ; else return false ; } if ( XD_REGISTER_P ( regno ) ) return mode == DFmode ; if ( regno == PR_REG ) return mode == SImode ; if ( regno == FPSCR_REG ) return mode == SImode ; return true ; } </s>

Return true if hard register REGNO can hold a value of machine-mode MODE . We can allow any mode in any general register . The special registers only allow SImode . Do n't allow any mode in the PR . We can not hold DCmode values in the XD registers because alter_reg handles subregs of them incorrectly . We could work around this by spacing the XD registers like the DR registers , but this would require additional memory in every compilation to hold larger register vectors . We could hold SFmode / SCmode values in XD registers , but that would require a tertiary reload when reloading from / to memory , and a secondary reload to reload from / to general regs ; that seems to be a losing proposition . We want to allow TImode FP regs so that when V4SFmode is loaded as TImode , it wo n't be ferried through GP registers first .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>


<s> static unsigned int rest_of_insert_bti ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx bti_insn ; rtx_insn * insn ; basic_block bb ; if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch64_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = gen_bti_c ( ) ; emit_insn_before ( bti_insn , insn ) ; } } bb = 0 ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) || ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_DELETED_LABEL ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - 1 ; j >= 0 ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , 0 ) ) ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>

This is implemented as a late RTL pass that runs before branch shortening and does the following .


"virtual function multiversioning not supported"

Generate the dispatching code body to dispatch multi-versioned function DECL . The target hook is called to process the `` target '' attributes and provide the code to dispatch the right function at run-time . NODE points to the dispatcher decl whose body will be created .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" PPC


<s> static rtx ix86_get_drap_rtx ( void ) { if ( ix86_force_drap || ( ( cfun -> machine -> outgoing_args_on_stack || crtl -> sp_is_clobbered_by_asm ) && ! ACCUMULATE_OUTGOING_ARGS ) ) crtl -> need_drap = true ; if ( stack_realign_drap ) { unsigned int regno = find_drap_reg ( ) ; rtx drap_vreg ; rtx arg_ptr ; rtx_insn * seq , * insn ; arg_ptr = gen_rtx_REG ( Pmode , regno ) ; crtl -> drap_reg = arg_ptr ; start_sequence ( ) ; drap_vreg = copy_to_reg ( arg_ptr ) ; seq = get_insns ( ) ; end_sequence ( ) ; insn = emit_insn_before ( seq , NEXT_INSN ( entry_of_function ( ) ) ) ; if ( ! optimize ) { add_reg_note ( insn , REG_CFA_SET_VDRAP , drap_vreg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return drap_vreg ; } else return NULL ; } </s>

Handle the TARGET_GET_DRAP_RTX hook . Return NULL if no DRAP is needed or an rtx for DRAP otherwise .


<s>
static
void
*
cygwin_gt_pch_get_address
(
size_t
sz
,
int
fd
)
{
void
*
base
;
off_t
p
=
lseek
(
fd
,
0
,
SEEK_CUR
)
;
if
(
p
==
(
off_t
)
1
)
fatal_error
(
input_location
,
"cannot get position in PCH file: %m"
)
;
if
(
(
size_t
)
p
<
sz
)
{
if
(
ftruncate
(
fd
,
sz
)
==
1
)
fatal_error
(
input_location
,
"cannot extend PCH file: %m"
)
;
}
base
=
mmap
(
,
sz
,
PROT_READ
|
PROT_WRITE
,
MAP_PRIVATE
,
fd
,
0
)
;
if
(
base
==
MAP_FAILED
)
base
=
;
else
munmap
(
base
,
sz
)
;
if
(
lseek
(
fd
,
p
,
SEEK_SET
)
==
(
off_t
)
1
)
fatal_error
(
input_location
,
"cannot set position in PCH file: %m"
)
;
return
base
;
}
</s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( SIBCALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( PCREL_OFFSET ) ; OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( PREFETCH ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function entry .


<s> bool PPCRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return ( ( EnablePPC32RS && ! Subtarget . isPPC64 ( ) ) || ( EnablePPC64RS && Subtarget . isPPC64 ( ) ) ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static bool timode_mem_p ( rtx x ) { return MEM_P ( x ) && ( TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || ! misaligned_operand ( x , TImode ) ) ; } </s>

Check for a suitable TImode memory operand .


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DstReg
,
const
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
getCMovFromCond
(
(
X86
::
CondCode
)
Cond
[
0
]
.
getImm
(
)
,
MRI
.
getRegClass
(
DstReg
)
->
getSize
(
)
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; a = arm_function_value ( TREE_TYPE ( exp ) , decl , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s> void MipsTargetELFStreamer :: emitLabel ( MCSymbol * S ) { auto * Symbol = cast < MCSymbolELF > ( S ) ; getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ; uint8_t Type = Symbol -> getType ( ) ; if ( Type != ELF :: STT_FUNC ) return ; if ( isMicroMipsEnabled ( ) ) Symbol -> setOther ( ELF :: STO_MIPS_MICROMIPS ) ; } </s>

Emit a label for Symbol into the current section .


<s> static bool ix86_expand_vec_one_operand_perm_avx512 ( struct expand_vec_perm_d * d ) { machine_mode mode = GET_MODE ( d -> op0 ) ; machine_mode maskmode = mode ; unsigned inner_size = GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; rtx ( * gen ) ( rtx , rtx , rtx ) = NULL ; rtx target , op0 , mask ; rtx vec [ 64 ] ; if ( ! rtx_equal_p ( d -> op0 , d -> op1 ) ) return false ; if ( ! TARGET_AVX512F ) return false ; if ( ! TARGET_AVX512VL && GET_MODE_SIZE ( mode ) < 64 ) return false ; if ( ! TARGET_AVX512BW && inner_size == 2 ) return false ; if ( ! TARGET_AVX512VBMI && inner_size == 1 ) return false ; switch ( mode ) { case E_V16SImode : gen = gen_avx512f_permvarv16si ; break ; case E_V16SFmode : gen = gen_avx512f_permvarv16sf ; maskmode = V16SImode ; break ; case E_V8DImode : gen = gen_avx512f_permvarv8di ; break ; case E_V8DFmode : gen = gen_avx512f_permvarv8df ; maskmode = V8DImode ; break ; case E_V32HImode : gen = gen_avx512bw_permvarv32hi ; break ; case E_V16HImode : gen = gen_avx512vl_permvarv16hi ; break ; case E_V8HImode : gen = gen_avx512vl_permvarv8hi ; break ; case E_V64QImode : gen = gen_avx512bw_permvarv64qi ; break ; case E_V32QImode : gen = gen_avx512vl_permvarv32qi ; break ; case E_V16QImode : gen = gen_avx512vl_permvarv16qi ; break ; default : return false ; } if ( d -> testing_p ) return true ; target = d -> target ; op0 = d -> op0 ; for ( int i = 0 ; i < d -> nelt ; ++ i ) vec [ i ] = GEN_INT ( d -> perm [ i ] ) ; mask = gen_rtx_CONST_VECTOR ( maskmode , gen_rtvec_v ( d -> nelt , vec ) ) ; emit_insn ( gen ( target , op0 , force_reg ( maskmode , mask ) ) ) ; return true ; } </s>

Try to expand one-operand permutation with constant mask .


<s> static rtl_opt_pass * make_pass_fma_steering ( gcc :: context * ctxt ) { return new pass_fma_steering ( ctxt ) ; } </s>

Create a new fma steering pass instance .


<s>
static
void
pru_print_operand_address
(
FILE
*
file
,
machine_mode
mode
,
rtx
op
)
{
if
(
CONSTANT_ADDRESS_P
(
op
)
&&
text_segment_operand
(
op
,
VOIDmode
)
)
{
output_operand_lossage
(
"unexpected text address:"
)
;
return
;
}
switch
(
GET_CODE
(
op
)
)
{
case
CONST
:
case
LABEL_REF
:
case
CONST_WIDE_INT
:
case
SYMBOL_REF
:
break
;
case
CONST_INT
:
{
unsigned
HOST_WIDE_INT
caddr
=
INTVAL
(
op
)
;
int
base
=
pru_get_ctable_base_index
(
caddr
)
;
int
offs
=
pru_get_ctable_base_offset
(
caddr
)
;
if
(
base
<
0
)
{
output_operand_lossage
(
"unsupported constant address:"
)
;
return
;
}
fprintf
(
file
,
"%d, %d"
,
base
,
offs
)
;
return
;
}
break
;
case
PLUS
:
{
int
base
;
rtx
op0
=
XEXP
(
op
,
0
)
;
rtx
op1
=
XEXP
(
op
,
1
)
;
if
(
REG_P
(
op0
)
&&
CONST_INT_P
(
op1
)
&&
pru_get_ctable_exact_base_index
(
INTVAL
(
op1
)
)
>=
0
)
{
base
=
pru_get_ctable_exact_base_index
(
INTVAL
(
op1
)
)
;
fprintf
(
file
,
"%d, %s"
,
base
,
pru_asm_regname
(
op0
)
)
;
return
;
}
else
if
(
REG_P
(
op1
)
&&
CONST_INT_P
(
op0
)
&&
pru_get_ctable_exact_base_index
(
INTVAL
(
op0
)
)
>=
0
)
{
gcc_unreachable
(
)
;
}
else
if
(
REG_P
(
op0
)
&&
CONSTANT_P
(
op1
)
)
{
fprintf
(
file
,
"%s, "
,
pru_asm_regname
(
op0
)
)
;
output_addr_const
(
file
,
op1
)
;
return
;
}
else
if
(
REG_P
(
op1
)
&&
CONSTANT_P
(
op0
)
)
{
gcc_unreachable
(
)
;
}
else
if
(
REG_P
(
op1
)
&&
REG_P
(
op0
)
)
{
fprintf
(
file
,
"%s, %s"
,
pru_asm_regname
(
op0
)
,
pru_asm_regname
(
op1
)
)
;
return
;
}
}
break
;
case
REG
:
fprintf
(
file
,
"%s, 0"
,
pru_asm_regname
(
op
)
)
;
return
;
case
MEM
:
{
rtx
base
=
XEXP
(
op
,
0
)
;
pru_print_operand_address
(
file
,
mode
,
base
)
;
return
;
}
default
:
break
;
}
output_operand_lossage
(
"unsupported memory expression:"
)
;
}
</s>


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
neon_lane_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
)
{
bounds_check
(
operand
,
low
,
high
,
"lane out of range"
)
;
}
</s>


<s> static bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { struct gcc_options func_options ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; tree old_optimize = build_optimization_node ( & global_options ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; new_optimize = build_optimization_node ( & func_options ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } finalize_options_struct ( & func_options ) ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ; MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool SparcTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createSparcISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool PPCTargetLowering :: SelectAddressRegReg ( SDValue N , SDValue & Base , SDValue & Index , SelectionDAG & DAG , MaybeAlign EncodingAlignment ) const { if ( SelectAddressPCRel ( N , Base ) ) return false ; int16_t Imm = 0 ; if ( N . getOpcode ( ) == ISD :: ADD ) { if ( hasSPE ( ) && SelectAddressEVXRegReg ( N , Base , Index , DAG ) ) return true ; if ( isIntS16Immediate ( N . getOperand ( 1 ) , Imm ) && ( ! EncodingAlignment || isAligned ( * EncodingAlignment , Imm ) ) ) return false ; if ( N . getOperand ( 1 ) . getOpcode ( ) == PPCISD :: Lo ) return false ; Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } else if ( N . getOpcode ( ) == ISD :: OR ) { if ( isIntS16Immediate ( N . getOperand ( 1 ) , Imm ) && ( ! EncodingAlignment || isAligned ( * EncodingAlignment , Imm ) ) ) return false ; KnownBits LHSKnown = DAG . computeKnownBits ( N . getOperand ( 0 ) ) ; if ( LHSKnown . Zero . getBoolValue ( ) ) { KnownBits RHSKnown = DAG . computeKnownBits ( N . getOperand ( 1 ) ) ; if ( ~ ( LHSKnown . Zero | RHSKnown . Zero ) == 0 ) { Base = N . getOperand ( 0 ) ; Index = N . getOperand ( 1 ) ; return true ; } } } return false ; } </s>

SelectAddressRegReg - Given the specified addressed , check to see if it can be more efficiently represented as [ r+imm ] .


<s> static int mips_binary_cost ( rtx x , int single_cost , int double_cost , bool speed ) { int cost ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * 2 ) cost = double_cost ; else cost = single_cost ; return ( cost + set_src_cost ( XEXP ( x , 0 ) , GET_MODE ( x ) , speed ) + rtx_cost ( XEXP ( x , 1 ) , GET_MODE ( x ) , GET_CODE ( x ) , 1 , speed ) ) ; } </s>

Return the cost of binary operation X , given that the instruction sequence for a word-sized or smaller operation has cost SINGLE_COST and that the sequence of a double-word operation has cost DOUBLE_COST . If SPEED is true , optimize for speed otherwise optimize for size .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * PPCSubTarget -> getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; DebugLoc dl ; if ( PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) == MVT :: i32 ) { if ( PPCSubTarget -> isTargetELF ( ) ) { GlobalBaseReg = PPC :: R30 ; if ( M -> getPICLevel ( ) == PICLevel :: SmallPIC ) { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MoveGOTtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } else { BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & PPC :: GPRCRegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: UpdateGBR ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < PPCFunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } } else { MF -> getInfo < PPCFunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

PowerPC PPC PPC PPC MVT::i32 PPC PPC::R30 PPC::MoveGOTtoLR PPC::MFLR PPC PPC::MovePCtoLR PPC::MFLR PPC::GPRCRegClass PPC::UpdateGBR PPC PPC::GPRC_and_GPRC_NOR0RegClass PPC::MovePCtoLR PPC::MFLR PPC PPC::G8RC_and_G8RC_NOX0RegClass PPC::MovePCtoLR8 PPC::MFLR8 PPC


<s> TargetPassConfig * PPCTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new PPCPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void thumb1_reorg ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx dest , src ; rtx pat , op0 , set = NULL ; rtx_insn * prev , * insn = BB_END ( bb ) ; bool insn_clobbered = false ; while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; pat = PATTERN ( insn ) ; op0 = XEXP ( XEXP ( SET_SRC ( pat ) , 0 ) , 0 ) ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; } if ( insn_clobbered ) continue ; if ( ! set ) continue ; dest = SET_DEST ( set ) ; src = SET_SRC ( set ) ; if ( ! low_register_operand ( dest , SImode ) || ! low_register_operand ( src , SImode ) ) continue ; if ( REGNO ( op0 ) == REGNO ( src ) || REGNO ( op0 ) == REGNO ( dest ) ) { dest = copy_rtx ( dest ) ; src = copy_rtx ( src ) ; src = gen_rtx_MINUS ( SImode , src , const0_rtx ) ; PATTERN ( prev ) = gen_rtx_SET ( VOIDmode , dest , src ) ; INSN_CODE ( prev ) = - 1 ; XEXP ( XEXP ( SET_SRC ( pat ) , 0 ) , 0 ) = copy_rtx ( dest ) ; INSN_CODE ( insn ) = - 1 ; } } } </s>

Rewrite move insn into subtract of 0 if the condition codes will be useful in next conditional jump insn .


<s> static int ix86_compare_version_priority ( tree decl1 , tree decl2 ) { unsigned int priority1 = get_builtin_code_for_version ( decl1 , NULL ) ; unsigned int priority2 = get_builtin_code_for_version ( decl2 , NULL ) ; return ( int ) priority1 - ( int ) priority2 ; } </s>

This compares the priority of target features in function DECL1 and DECL2 . It returns positive value if DECL1 is higher priority , negative value if DECL2 is higher priority and 0 if they are the same .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void nds32_emit_stack_v3push ( rtx Rb , rtx Re , rtx En4 ATTRIBUTE_UNUSED , rtx imm8u ) { int regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx push_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; num_use_regs = REGNO ( Re ) - REGNO ( Rb ) + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = - ( num_use_regs * 4 ) ; for ( regno = REGNO ( Rb ) ; regno <= ( int ) REGNO ( Re ) ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; push_rtx = gen_rtx_SET ( VOIDmode , mem , reg ) ; XVECEXP ( parallel_insn , 0 , par_index ) = push_rtx ; RTX_FRAME_RELATED_P ( push_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; offset = - ( num_use_regs * 4 ) ; adjust_sp_rtx = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset - INTVAL ( imm8u ) ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; RTX_FRAME_RELATED_P ( adjust_sp_rtx ) = 1 ; parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; } </s>

Function to create a parallel rtx pattern which presents stack v3push behavior . The overall concept are : `` push registers to memory '' , `` adjust stack pointer '' .


<s> ATTRIBUTE_UNUSED static section * x86_64_elf_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) { if ( ix86_in_large_data_p ( decl ) ) { const char * sname = NULL ; unsigned int flags = SECTION_WRITE | SECTION_LARGE ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_DATA : sname = ".ldata" ; break ; case SECCAT_DATA_REL : sname = ".ldata.rel" ; break ; case SECCAT_DATA_REL_LOCAL : sname = ".ldata.rel.local" ; break ; case SECCAT_DATA_REL_RO : sname = ".ldata.rel.ro" ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = ".ldata.rel.ro.local" ; break ; case SECCAT_BSS : sname = ".lbss" ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : sname = ".lrodata" ; flags &= ~ SECTION_WRITE ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS : gcc_unreachable ( ) ; case SECCAT_TEXT : case SECCAT_TDATA : case SECCAT_TBSS : break ; } if ( sname ) { if ( ! DECL_P ( decl ) ) return get_section ( sname , flags , NULL ) ; return get_named_section ( decl , sname , reloc ) ; } } return default_elf_select_section ( decl , reloc , align ) ; } </s>

switch to the appropriate section for output of DECL . DECL is either a ` VAR_DECL ' node or a constant of some sort . RELOC indicates whether forming the initial value of DECL requires link-time relocations .


<s> int ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( MI -> isCopyLike ( ) || MI -> isInsertSubreg ( ) || MI -> isRegSequence ( ) || MI -> isImplicitDef ( ) ) return 1 ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return 1 ; if ( MI -> isBundle ( ) ) { int Latency = 0 ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != ARM :: t2IT ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ; if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( ARM :: CPSR ) ) ) * PredCost = 1 ; if ( UOps ) return ItinData -> getStageLatency ( Class ) ; return getNumMicroOps ( ItinData , MI ) ; } </s>

Compute the instruction latency of a given instruction .


<s> int PPCInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , const MachineInstr & DefMI , unsigned DefIdx , const MachineInstr & UseMI , unsigned UseIdx ) const { int Latency = PPCGenInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( ! DefMI . getParent ( ) ) return Latency ; const MachineOperand & DefMO = DefMI . getOperand ( DefIdx ) ; unsigned Reg = DefMO . getReg ( ) ; bool IsRegCR ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { const MachineRegisterInfo * MRI = & DefMI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; IsRegCR = MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRRCRegClass ) || MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( & PPC :: CRBITRCRegClass ) ; } else { IsRegCR = PPC :: CRRCRegClass . contains ( Reg ) || PPC :: CRBITRCRegClass . contains ( Reg ) ; } if ( UseMI . isBranch ( ) && IsRegCR ) { if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; unsigned Directive = Subtarget . getMcpu ( ) ; switch ( Directive ) { default : break ; case PPC :: MCPU_7400 : case PPC :: MCPU_750 : case PPC :: MCPU_970 : case PPC :: MCPU_E5500 : case PPC :: MCPU_PWR4 : case PPC :: MCPU_PWR5 : case PPC :: MCPU_PWR5X : case PPC :: MCPU_PWR6 : case PPC :: MCPU_PWR6X : case PPC :: MCPU_PWR7 : case PPC :: MCPU_PWR8 : Latency += 2 ; break ; } } return Latency ; } </s>

Compute and return the use operand latency of a given pair of def and use .


<s> static inline int and_xor_ior_costs ( rtx x , int code ) { const int cost_scale = ! TARGET_SHMEDIA && GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 * cost_scale ; int i = INTVAL ( XEXP ( x , 1 ) ) ; if ( TARGET_SHMEDIA ) { if ( satisfies_constraint_I10 ( XEXP ( x , 1 ) ) || satisfies_constraint_J16 ( XEXP ( x , 1 ) ) ) return 1 ; else return 1 + rtx_cost ( XEXP ( x , 1 ) , AND , 1 , ! optimize_size ) ; } if ( ( i == 0xff || i == 0xffff ) && code == AND ) return 1 * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return 2 * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return 2 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an AND/XOR/IOR operation .


<s>
static
void
rs6000_elf_output_toc_section_asm_op
(
const
void
*
data
ATTRIBUTE_UNUSED
)
{
if
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_MINIMAL_TOC
)
{
if
(
!
toc_initialized
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"LCTOC"
,
0
)
;
fprintf
(
asm_out_file
,
"\t.tc "
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1[TC],"
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
else
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
}
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
toc_initialized
=
1
;
}
}
else
{
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
}
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s> void mips_expand_vec_reduc ( rtx target , rtx in , rtx ( * gen ) ( rtx , rtx , rtx ) ) { machine_mode vmode = GET_MODE ( in ) ; unsigned char perm2 [ 2 ] ; rtx last , next , fold , x ; bool ok ; last = in ; fold = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case E_V2SFmode : perm2 [ 0 ] = 1 ; perm2 [ 1 ] = 2 ; ok = mips_expand_vselect_vconcat ( fold , last , last , perm2 , 2 ) ; gcc_assert ( ok ) ; break ; case E_V2SImode : emit_insn ( gen_loongson_punpckhwd ( fold , last , last ) ) ; break ; case E_V4HImode : emit_insn ( gen_loongson_punpckhwd_hi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v4hi ( fold , last , x ) ) ; break ; case E_V8QImode : emit_insn ( gen_loongson_punpckhwd_qi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 16 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( 8 ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( target , last , fold ) ) ; } </s>


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC , Subtarget . isTargetWin64 ( ) ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
RC
->
getSize
(
)
,
16
)
;
bool
isAligned
=
(
TM
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
TM
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void nds32_emit_stack_v3pop ( unsigned Rb , unsigned Re , unsigned imm8u ) { unsigned regno ; int num_use_regs ; int par_index ; int offset ; rtx reg ; rtx mem ; rtx pop_rtx ; rtx adjust_sp_rtx ; rtx parallel_insn ; rtx dwarf = NULL_RTX ; num_use_regs = Re - Rb + 1 + 3 ; parallel_insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_use_regs + 1 ) ) ; par_index = 0 ; offset = 0 ; for ( regno = Rb ; regno <= Re ; regno ++ ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , 0 , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = 1 ; offset = offset + 4 ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset + imm8u ) ) ; XVECEXP ( parallel_insn , 0 , par_index ) = adjust_sp_rtx ; if ( frame_pointer_needed ) { rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; } else { dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , copy_rtx ( adjust_sp_rtx ) , dwarf ) ; } parallel_insn = emit_insn ( parallel_insn ) ; RTX_FRAME_RELATED_P ( parallel_insn ) = 1 ; REG_NOTES ( parallel_insn ) = dwarf ; } </s>

Function to create a parallel rtx pattern which presents stack v3pop behavior . The overall concept are : `` pop registers from memory '' , `` adjust stack pointer '' .


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
LaneLen
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
LaneLen
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
LaneLen
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
{
if
(
Mask
[
i
]
>=
0
)
{
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
Mask
[
i
]
,
LaneLen
)
)
)
;
}
else
{
unsigned
StartMask
=
0
;
for
(
unsigned
j
=
1
;
j
<
LaneLen
;
j
++
)
{
if
(
Mask
[
j
*
Factor
+
i
]
>=
0
)
{
StartMask
=
Mask
[
j
*
Factor
+
i
]
j
;
break
;
}
}
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
StartMask
,
LaneLen
)
)
)
;
}
}
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s> SDValue AArch64TargetLowering :: getTargetNode ( GlobalAddressSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetGlobalAddress ( N -> getGlobal ( ) , SDLoc ( N ) , Ty , 0 , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) != AtomicRMWInst :: Nand && Size < 128 ) { if ( Subtarget -> hasLSE ( ) ) return AtomicExpansionKind :: None ; if ( Subtarget -> outlineAtomics ( ) ) { if ( AI -> getOperation ( ) != AtomicRMWInst :: Min && AI -> getOperation ( ) != AtomicRMWInst :: Max && AI -> getOperation ( ) != AtomicRMWInst :: UMin && AI -> getOperation ( ) != AtomicRMWInst :: UMax ) { return AtomicExpansionKind :: None ; } } } if ( getTargetMachine ( ) . getOptLevel ( ) == CodeGenOpt :: None ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> unsigned int LC2200AsmBackend :: getNumFixupKinds ( ) const { return LC2200 :: Fixups :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool Cpu0AsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { MCOp = MCInstLowering . LowerOperand ( MO ) ; return MCOp . isValid ( ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { const TargetRegisterInfo * TRI = PPCSubTarget -> getRegisterInfo ( ) ; const TargetRegisterClass * TRC = TRI -> getPointerRegClass ( * MF , 1 ) ; SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , MVT :: i32 ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , 0 ) ; OutOps . push_back ( NewOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> static bool is_store_insn1 ( rtx pat , rtx * str_mem ) { if ( ! pat || pat == NULL_RTX ) return false ; if ( GET_CODE ( pat ) == SET ) { if ( REG_P ( SET_SRC ( pat ) ) || SUBREG_P ( SET_SRC ( pat ) ) ) return find_mem_ref ( SET_DEST ( pat ) , str_mem ) ; else return false ; } if ( GET_CODE ( pat ) == PARALLEL ) { int i ; for ( i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( is_store_insn1 ( XVECEXP ( pat , 0 , i ) , str_mem ) ) return true ; } return false ; } </s>

Determine if PAT is a PATTERN of a store insn .


<s> unsigned X86RegisterInfo :: getRARegister ( ) const { return Is64Bit ? X86 :: RIP : X86 :: EIP ; } </s>

This method should return the register where the return address can be found .


<s>
static
void
rs6000_elf_asm_out_constructor
(
rtx
symbol
,
int
priority
)
{
const
char
*
section
=
".ctors"
;
char
buf
[
16
]
;
if
(
priority
!=
DEFAULT_INIT_PRIORITY
)
{
sprintf
(
buf
,
".ctors.%.5u"
,
MAX_INIT_PRIORITY
priority
)
;
section
=
buf
;
}
switch_to_section
(
get_section
(
section
,
SECTION_WRITE
,
)
)
;
assemble_align
(
POINTER_SIZE
)
;
if
(
TARGET_RELOCATABLE
)
{
fputs
(
"\t.long ("
,
asm_out_file
)
;
output_addr_const
(
asm_out_file
,
symbol
)
;
fputs
(
")@fixup\n"
,
asm_out_file
)
;
}
else
assemble_integer
(
symbol
,
POINTER_SIZE
/
BITS_PER_UNIT
,
POINTER_SIZE
,
1
)
;
}
</s>


<s> static int find_gr_spill ( int try_locals ) { int regno ; if ( current_function_is_leaf ) { for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; regno ++ ) if ( ! regs_ever_live [ regno ] && call_used_regs [ regno ] && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) & 1 ) == 0 ) { current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } } if ( try_locals ) { regno = current_frame_info . n_local_regs ; if ( regno < ( 80 - frame_pointer_needed ) ) { current_frame_info . n_local_regs = regno + 1 ; return LOC_REG ( 0 ) + regno ; } } return 0 ; } </s>

Helper function for ia64_compute_frame_size : find an appropriate general register to spill some special register to . SPECIAL_SPILL_MASK contains bits in GR0 to GR31 that have already been allocated by this routine . TRY_LOCALS is true if we should attempt to locate a local regnum .


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return X86II :: MO_NO_FLAG ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: X86_RegCall == F -> getCallingConv ( ) ) ) return X86II :: MO_GOTPCREL ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( ! is64Bit ( ) && ! GV && TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_PLT ; } if ( is64Bit ( ) ) { if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s> static void fusion_split_address ( rtx addr , rtx * p_hi , rtx * p_lo ) { rtx hi , lo ; if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) { hi = XEXP ( addr , 0 ) ; lo = XEXP ( addr , 1 ) ; } else gcc_unreachable ( ) ; * p_hi = hi ; * p_lo = lo ; } </s>

Given an address , convert it into the addis and load offset parts . Addresses created during the peephole2 process look like : ( lo_sum ( high ( unspec [ ( sym ) ] UNSPEC_TOCREL ) ) ( unspec [ ( ... ) ] UNSPEC_TOCREL ) )


<s> X86DCBasicBlock & getParent ( ) { return static_cast < X86DCBasicBlock & > ( DCInstruction :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s> bool VEInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = & * I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = & * I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } SecondLastInst = & * I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { parseCondBranch ( SecondLastInst , TBB , Cond ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int
OffsetA
=
0
,
OffsetB
=
0
;
int
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr & MI ) { unsigned Idx = isPairedLdSt ( MI ) ? 3 : 2 ; return MI . getOperand ( Idx ) ; } </s>

Returns the immediate offset operator of a load/store .


<s> virtual const PPCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool SystemZXPLINKFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; auto & Regs = Subtarget . getSpecialRegisters < SystemZXPLINK64Registers > ( ) ; unsigned LowGPR = 0 ; int LowOffset = INT32_MAX ; unsigned HighGPR = LowGPR ; int HighOffset = - 1 ; unsigned RegSP = Regs . getStackPointerRegister ( ) ; auto & GRRegClass = SystemZ :: GR64BitRegClass ; const unsigned RegSize = 8 ; auto ProcessCSI = [ & ] ( std :: vector < CalleeSavedInfo > & CSIList ) { for ( auto & CS : CSIList ) { unsigned Reg = CS . getReg ( ) ; int Offset = RegSpillOffsets [ Reg ] ; if ( Offset >= 0 ) { if ( GRRegClass . contains ( Reg ) ) { if ( LowOffset > Offset ) { LowOffset = Offset ; LowGPR = Reg ; } if ( Offset > HighOffset ) { HighOffset = Offset ; HighGPR = Reg ; } } int FrameIdx = MFFrame . CreateFixedSpillStackObject ( RegSize , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI ) ; MFI -> setRestoreGPRRegs ( LowGPR , HighGPR , LowOffset ) ; ProcessCSI ( Spills ) ; MFI -> setSpillGPRRegs ( LowGPR , HighGPR , LowOffset ) ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ; int FrameIdx = MFFrame . CreateStackObject ( Size , Alignment , true ) ; CS . setFrameIdx ( FrameIdx ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> uint64_t MipsGOTPLT :: emit ( MemoryRegion & pRegion ) { uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; uint64_t result = 0 ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { GOTPLTEntry * got = & ( llvm :: cast < GOTPLTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; result += got -> size ( ) ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .


<s> static machine_mode rs6000_secondary_memory_needed_mode ( machine_mode mode ) { if ( lra_in_progress && mode == SDmode ) return DDmode ; return mode ; } </s>

Return the mode to be used for memory when a secondary memory location is needed . For SDmode values we need to use DDmode , in all other cases we can use the same mode .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer -> EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM ARM 1 0 ARM::tBX ARMCC::AL 0


<s>
void
output_ascii
(
FILE
*
file
,
const
char
*
p
,
int
n
)
{
char
c
;
int
i
,
count_string
;
const
char
*
for_string
=
"\t.byte \""
;
const
char
*
for_decimal
=
"\t.byte "
;
const
char
*
to_close
=
;
count_string
=
0
;
for
(
i
=
0
;
i
<
n
;
i
++
)
{
c
=
*
p
++
;
if
(
c
>=
' '
&&
c
<
0177
)
{
if
(
for_string
)
fputs
(
for_string
,
file
)
;
putc
(
c
,
file
)
;
if
(
c
==
'"'
)
{
putc
(
c
,
file
)
;
++
count_string
;
}
for_string
=
;
for_decimal
=
"\"\n\t.byte "
;
to_close
=
"\"\n"
;
++
count_string
;
if
(
count_string
>=
512
)
{
fputs
(
to_close
,
file
)
;
for_string
=
"\t.byte \""
;
for_decimal
=
"\t.byte "
;
to_close
=
;
count_string
=
0
;
}
}
else
{
if
(
for_decimal
)
fputs
(
for_decimal
,
file
)
;
fprintf
(
file
,
"%d"
,
c
)
;
for_string
=
"\n\t.byte \""
;
for_decimal
=
", "
;
to_close
=
"\n"
;
count_string
=
0
;
}
}
if
(
to_close
)
fputs
(
to_close
,
file
)
;
}
</s>

Output an assembler pseudo-op to write an ASCII string of N characters starting at P to FILE . On the RS/6000 , we have to do this using the .byte operation and write out special characters outside the quoted string . Also , the assembler is broken ; very long strings are truncated , so we must artificially break them up early .


<s> static rtx ix86_expand_vec_init_builtin ( tree type , tree exp , rtx target ) { machine_mode tmode = TYPE_MODE ( type ) ; machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; rtvec v = rtvec_alloc ( n_elt ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; gcc_assert ( call_expr_nargs ( exp ) == n_elt ) ; for ( i = 0 ; i < n_elt ; ++ i ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , i ) ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_init ( true , target , gen_rtx_PARALLEL ( tmode , v ) ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_init . We DO have language-level syntax for this , in the form of ( type ) { init-list } . Except that since we ca n't place emms instructions from inside the compiler , we ca n't allow the use of MMX registers unless the user explicitly asks for it . So we do * not * define vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md . Instead we have builtins invoked by mmintrin.h that gives us license to emit these sorts of instructions .


<s> void PPCPostRASchedStrategy :: enterMBB ( MachineBasicBlock * MBB ) { PostGenericScheduler :: enterMBB ( MBB ) ; } </s>

Tell the strategy that MBB is about to be processed .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( shouldAssumeGlobalReferenceLocal ( this , TM , M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>