<s> static bool rs6000_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict ) { bool reg_offset_p = reg_offset_addressing_ok_p ( mode ) ; bool quad_offset_p = mode_supports_dq_form ( mode ) ; if ( VECTOR_MEM_ALTIVEC_P ( mode ) && GET_CODE ( x ) == AND && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == - 16 ) x = XEXP ( x , 0 ) ; if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return 0 ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) ) return 1 ; if ( quad_offset_p ) { if ( quad_address_p ( x , mode , reg_ok_strict ) ) return 1 ; } else if ( virtual_stack_registers_memory_p ( x ) ) return 1 ; else if ( reg_offset_p ) { if ( legitimate_small_data_p ( mode , x ) ) return 1 ; if ( legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return 1 ; } if ( mode == TImode && TARGET_VSX ) return 0 ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && ( XEXP ( x , 0 ) == virtual_stack_vars_rtx || XEXP ( x , 0 ) == arg_pointer_rtx ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return 1 ; if ( ! FLOAT128_2REG_P ( mode ) && ( TARGET_HARD_FLOAT || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , 1 ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , 1 ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) return 1 ; if ( reg_offset_p && ! quad_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return 1 ; return 0 ; } </s>

TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . On the RS/6000 , there are four valid address : a SYMBOL_REF that refers to a constant pool entry of an address ( or the sum of it plus a constant ) , a short ( 16-bit signed ) constant plus a register , the sum of two registers , or a register indirect , possibly with an auto-increment . For DFmode , DDmode and DImode with a constant plus register , we must ensure that both words are addressable or PowerPC64 with offset word aligned . For modes spanning multiple registers ( DFmode and DDmode in 32-bit GPRs , 32-bit DImode , TImode , TFmode , TDmode ) , indexed addressing can not be used because adjacent memory cells are accessed by adding word-sized offsets during assembly output .


<s> bool PPCTargetLowering :: isFPExtFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return true ; } </s>

Return true if an fpext operation is free ( for instance , because single-precision floating-point numbers are implicitly extended to double-precision ) .


<s>
DecodeStatus
CSKYDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
uint32_t
Insn
;
DecodeStatus
Result
=
MCDisassembler
::
Fail
;
Insn
=
support
::
endian
::
read16le
(
Bytes
.
data
(
)
)
;
if
(
(
Insn
>>
14
)
==
0x3
)
{
if
(
Bytes
.
size
(
)
<
4
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
Insn
=
(
Insn
<<
16
)
|
support
::
endian
::
read16le
(
&
Bytes
[
2
]
)
;
if
(
decodeFPUV3Instruction
(
MI
,
Insn
,
Address
,
this
,
STI
)
)
Result
=
MCDisassembler
::
Success
;
else
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CSKY 32-bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable32
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
}
Size
=
4
;
}
else
{
if
(
Bytes
.
size
(
)
<
2
)
{
Size
=
0
;
return
MCDisassembler
::
Fail
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Trying CSKY 16-bit table :\n"
)
;
Result
=
decodeInstruction
(
DecoderTable16
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
Size
=
2
;
}
handleCROperand
(
MI
)
;
return
Result
;
}
</s>

Returns the disassembly of a single instruction .


<s> bool WinEHStatePass :: doFinalization ( Module & M ) { assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
static
void
csky_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
const
char
*
fnname
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
thunk
)
)
;
const
char
*
thiz
=
"a0"
;
const
char
*
reg0
=
"t0"
;
const
char
*
reg1
=
"t1"
;
int
maxoff
=
4096
;
assemble_start_function
(
thunk
,
fnname
)
;
final_start_function
(
emit_barrier
(
)
,
file
,
1
)
;
rtx
fnaddr
=
XEXP
(
DECL_RTL
(
function
)
,
0
)
;
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
reg0
=
"l0"
;
reg1
=
"l1"
;
maxoff
=
256
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0, l1\n"
)
;
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0\n"
)
;
}
if
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
)
thiz
=
"a1"
;
if
(
delta
!=
0
)
{
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg0
,
(
long
)
delta
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
delta
>
0
"addi"
:
"subi"
)
,
thiz
,
thiz
,
(
long
)
(
delta
>
0
delta
:
delta
)
)
;
}
if
(
vcall_offset
!=
0
)
{
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
thiz
)
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg1
,
(
long
)
vcall_offset
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
reg0
,
reg0
,
reg1
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
vcall_offset
>
0
"addi"
:
"subi"
)
,
reg0
,
reg0
,
(
long
)
(
vcall_offset
>
0
vcall_offset
:
vcall_offset
)
)
;
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
reg0
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\tld.w\tl1, (sp, 4)\n"
)
;
fprintf
(
file
,
"\taddi\t sp, sp, 8\n"
)
;
}
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\taddi\tsp, sp, 4\n"
)
;
}
}
fprintf
(
file
,
"\tjbr\t"
)
;
output_addr_const
(
file
,
fnaddr
)
;
fprintf
(
file
,
"\n"
)
;
final_end_function
(
)
;
assemble_end_function
(
thunk
,
fnname
)
;
}
</s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> bool MipsLongBranch :: runOnMachineFunction ( MachineFunction & F ) { const MipsInstrInfo * TII = static_cast < const MipsInstrInfo * > ( TM . getInstrInfo ( ) ) ; if ( TM . getSubtarget < MipsSubtarget > ( ) . inMips16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < MipsSubtarget > ( ) . isABI_O32 ( ) && F . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVector < MBBInfo , 16 > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < 16 > ( computeOffset ( I -> Br ) / 4 ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * 4 ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = 0 ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ; } for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) if ( I -> HasLongBranch ) expandToLongBranch ( * I ) ; MF -> RenumberBlocks ( ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue VETargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: TRUNCATE : return combineTRUNCATE ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool pa_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return ( int_size_in_bytes ( type ) > ( TARGET_64BIT ? 16 : 8 ) || int_size_in_bytes ( type ) <= 0 ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> const Cpu0Subtarget * getSubtargetImpl ( ) const { return & DefaultSubtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> unsigned long arm_current_func_type ( ) { if ( ARM_FUNC_TYPE ( cfun -> machine -> func_type ) == ARM_FT_UNKNOWN ) cfun -> machine -> func_type = arm_compute_func_type ( ) ; return cfun -> machine -> func_type ; } </s>

Returns the type of the current function .


<s> SDNode * PPCDAGToDAGISel :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) { const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; if ( PPCLowering . getPointerTy ( ) == MVT :: i32 ) { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: GPRCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR ) , PPC :: LR ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR ) , GlobalBaseReg ) ; } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( PPC :: G8RCRegisterClass ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MovePCtoLR8 ) , PPC :: LR8 ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( PPC :: MFLR8 ) , GlobalBaseReg ) ; } } return CurDAG -> getRegister ( GlobalBaseReg , PPCLowering . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void aarch64_emit_unop ( rtx dest , optab unoptab , rtx op ) { rtx tmp = expand_unop ( GET_MODE ( dest ) , unoptab , op , dest , 0 ) ; if ( dest != tmp ) emit_move_insn ( dest , tmp ) ; } </s>

Apply UNOPTAB to OP and store the result in DEST .


<s> enum reg_class arm_mode_base_reg_class ( machine_mode mode ) { if ( TARGET_HAVE_MVE && ( mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode ) ) return LO_REGS ; return MODE_BASE_REG_REG_CLASS ( mode ) ; } </s>

If given mode matches , load from memory to LO_REGS . ( i.e [ Rn ] , Rn < = LO_REGS ) .


<s> bool nds32_long_call_p ( rtx symbol ) { return TARGET_CMODEL_LARGE ; } </s>


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
GPR32RegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( ! shouldAssumeDSOLocal ( RM , TargetTriple , * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> BitVector LC3RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( LC3 :: SP ) ; Reserved . set ( LC3 :: LR ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
;
dumpBBs
(
)
;
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n\n"
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>


<s>
SDValue
LC2200TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
report_fatal_error
(
"unimplemented operand"
)
;
case
ISD
::
SHL
:
return
lowerShiftLeft
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
lowerBrCc
(
Op
,
DAG
)
;
case
ISD
::
BR
:
return
lowerBr
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
lowerSelectCc
(
Op
,
DAG
)
;
case
ISD
::
AND
:
return
lowerAnd
(
Op
,
DAG
)
;
case
ISD
::
OR
:
return
lowerOr
(
Op
,
DAG
)
;
case
ISD
::
XOR
:
return
lowerXor
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
SRL
:
return
ExpandLibCall
(
"__srlu"
,
Op
,
false
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { if ( Subtarget . hasNEON ( ) ) { if ( MI . getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; if ( Subtarget . useNEONForFPMovs ( ) && ! isPredicated ( MI ) && ( MI . getOpcode ( ) == ARM :: VMOVRS || MI . getOpcode ( ) == ARM :: VMOVSR || MI . getOpcode ( ) == ARM :: VMOVS ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; } unsigned Domain = MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


"unknown flag passed in -moverride=%s (%s)"

Parse TOKEN , which has length LENGTH to see if it is an option described in FLAG . If it is , return the index bit for that fusion type . If not , error ( printing OPTION_NAME ) and return zero .


<s> bool X86RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( DisableFramePointerElim ( MF ) || needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static int rs6000_darwin64_struct_check_p ( machine_mode mode , const_tree type ) { return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > 0 ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == 8 ) ) ? 1 : 0 ; } </s>

Check for an item that needs to be considered specially under the darwin 64 bit ABI . These are record types where the mode is BLK or the structure is 8 bytes in size .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI -> CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI -> CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI -> CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , * Subtarget -> getRegisterInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ix86_expand_fp_absneg_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx mask , set , dst , src ; bool use_sse = false ; bool vector_mode = VECTOR_MODE_P ( mode ) ; machine_mode vmode = mode ; if ( vector_mode ) use_sse = true ; else if ( mode == TFmode ) use_sse = true ; else if ( TARGET_SSE_MATH ) { use_sse = SSE_FLOAT_MODE_P ( mode ) ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; } if ( use_sse ) mask = ix86_build_signbit_mask ( vmode , vector_mode , code == ABS ) ; else mask = NULL_RTX ; dst = operands [ 0 ] ; src = operands [ 1 ] ; set = gen_rtx_fmt_e ( code , mode , src ) ; set = gen_rtx_SET ( VOIDmode , dst , set ) ; if ( mask ) { rtx use , clob ; rtvec par ; use = gen_rtx_USE ( VOIDmode , mask ) ; if ( vector_mode ) par = gen_rtvec ( 2 , set , use ) ; else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; par = gen_rtvec ( 3 , set , use , clob ) ; } emit_insn ( gen_rtx_PARALLEL ( VOIDmode , par ) ) ; } else emit_insn ( set ) ; } </s>

Generate code for floating point ABS or NEG .


<s> TargetPassConfig * OR1KTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new OR1KPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
return
;
case
ISD
::
BIT_CONVERT
:
Results
.
push_back
(
ExpandBIT_CONVERT
(
N
,
DAG
)
)
;
return
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
{
SDValue
Res
=
LowerShift
(
N
,
DAG
,
Subtarget
)
;
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
return
;
}
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::BIT_CONVERT
ISD::SRL
ISD::SRA


<s> bool aarch64_expand_sve_vec_cmp_float ( rtx target , rtx_code code , rtx op0 , rtx op1 , bool can_invert_p ) { machine_mode pred_mode = GET_MODE ( target ) ; machine_mode data_mode = GET_MODE ( op0 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; switch ( code ) { case UNORDERED : op1 = force_reg ( data_mode , op1 ) ; case LT : case LE : case GT : case GE : case EQ : case NE : { rtx cond = gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ; aarch64_emit_sve_ptrue_op ( target , ptrue , cond ) ; return false ; } case LTGT : aarch64_emit_sve_or_conds ( target , LT , GT , ptrue , op0 , op1 ) ; return false ; case UNEQ : if ( ! flag_trapping_math ) { op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_sve_or_conds ( target , UNORDERED , EQ , ptrue , op0 , op1 ) ; return false ; } case UNLT : case UNLE : case UNGT : case UNGE : if ( flag_trapping_math ) { rtx ordered = gen_reg_rtx ( pred_mode ) ; op1 = force_reg ( data_mode , op1 ) ; aarch64_emit_sve_inverted_cond ( ordered , ptrue , UNORDERED , op0 , op1 ) ; if ( code == UNEQ ) code = NE ; else code = reverse_condition_maybe_unordered ( code ) ; if ( can_invert_p ) { aarch64_emit_sve_predicated_cond ( target , code , ordered , op0 , op1 ) ; return true ; } rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_sve_predicated_cond ( tmp , code , ordered , op0 , op1 ) ; aarch64_emit_unop ( target , one_cmpl_optab , tmp ) ; return false ; } break ; case ORDERED : op1 = force_reg ( data_mode , op1 ) ; break ; default : gcc_unreachable ( ) ; } code = reverse_condition_maybe_unordered ( code ) ; if ( can_invert_p ) { rtx cond = gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ; aarch64_emit_sve_ptrue_op ( target , ptrue , cond ) ; return true ; } aarch64_emit_sve_inverted_cond ( target , ptrue , code , op0 , op1 ) ; return false ; } </s>

Expand an SVE floating-point comparison : TARGET = CODE ( OP0 , OP1 ) If CAN_INVERT_P is true , the caller can also handle inverted results ; return true if the result is in fact inverted .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( shouldAssumeDSOLocal ( RM , TargetTriple , M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i8 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> static rtx mips_expand_builtin_bposge ( enum mips_builtin_type builtin_type , rtx target ) { rtx label1 , label2 , if_then_else ; rtx cmp_result ; int cmp_value ; if ( target == 0 || GET_MODE ( target ) != SImode ) target = gen_reg_rtx ( SImode ) ; cmp_result = gen_rtx_REG ( CCDSPmode , CCDSP_PO_REGNUM ) ; if ( builtin_type == MIPS_BUILTIN_BPOSGE32 ) cmp_value = 32 ; else gcc_assert ( 0 ) ; emit_move_insn ( target , const0_rtx ) ; label1 = gen_label_rtx ( ) ; label2 = gen_label_rtx ( ) ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( GE , CCDSPmode , cmp_result , GEN_INT ( cmp_value ) ) , gen_rtx_LABEL_REF ( VOIDmode , label1 ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_then_else ) ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_LABEL_REF ( VOIDmode , label2 ) ) ) ; emit_barrier ( ) ; emit_label ( label1 ) ; emit_move_insn ( target , const1_rtx ) ; emit_label ( label2 ) ; return target ; } </s>

Expand a bposge builtin of type BUILTIN_TYPE . TARGET , if nonnull , suggests a good place to put the boolean result . The sequence we want is li target , 0 bposge * label1 j label2 label1 : li target , 1 label2 :


<s> const CSKYInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
bool
X86CondBrFolding
::
analyzeCompare
(
const
MachineInstr
&
MI
,
unsigned
&
SrcReg
,
int
&
CmpValue
)
{
unsigned
SrcRegIndex
=
0
;
unsigned
ValueIndex
=
0
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
X86
::
CMP64ri32
:
case
X86
::
CMP64ri8
:
case
X86
::
CMP32ri
:
case
X86
::
CMP32ri8
:
case
X86
::
CMP16ri
:
case
X86
::
CMP16ri8
:
case
X86
::
CMP8ri
:
SrcRegIndex
=
0
;
ValueIndex
=
1
;
break
;
case
X86
::
SUB64ri32
:
case
X86
::
SUB64ri8
:
case
X86
::
SUB32ri
:
case
X86
::
SUB32ri8
:
case
X86
::
SUB16ri
:
case
X86
::
SUB16ri8
:
case
X86
::
SUB8ri
:
SrcRegIndex
=
1
;
ValueIndex
=
2
;
break
;
}
SrcReg
=
MI
.
getOperand
(
SrcRegIndex
)
.
getReg
(
)
;
assert
(
MI
.
getOperand
(
ValueIndex
)
.
isImm
(
)
&&
"Expecting Imm operand"
)
;
CmpValue
=
MI
.
getOperand
(
ValueIndex
)
.
getImm
(
)
;
return
true
;
}
</s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void mips_expand_vector_init ( rtx target , rtx vals ) { machine_mode vmode = GET_MODE ( target ) ; machine_mode imode = GET_MODE_INNER ( vmode ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; unsigned nvar = 0 , one_var = - 1u ; bool all_same = true ; rtx x ; for ( i = 0 ; i < nelt ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! mips_constant_elt_p ( x ) ) nvar ++ , one_var = i ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( nvar == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , XVEC ( vals , 0 ) ) ) ; return ; } if ( nelt == 2 ) { rtx op0 = force_reg ( imode , XVECEXP ( vals , 0 , 0 ) ) ; rtx op1 = force_reg ( imode , XVECEXP ( vals , 0 , 1 ) ) ; x = gen_rtx_VEC_CONCAT ( vmode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( target , x ) ) ; return ; } gcc_assert ( TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS ) ; if ( all_same ) { mips_expand_vi_broadcast ( vmode , target , XVECEXP ( vals , 0 , 0 ) ) ; return ; } if ( nvar == 1 && vmode == V4HImode ) { mips_expand_vi_loongson_one_pinsrh ( target , vals , one_var ) ; return ; } mips_expand_vi_general ( vmode , imode , nelt , nvar , target , vals ) ; } </s>


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; unsigned FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; unsigned SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; unsigned SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; unsigned DestReg = MI . getOperand ( 0 ) . getReg ( ) ; unsigned DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; unsigned DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , * LdMI , * LdMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static bool const_load_sequence_p ( swap_web_entry * insn_entry , rtx insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , 0 ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false ) ) return false ; split_const ( XVECEXP ( tocrel_base , 0 , 0 ) , & base , & offset ) ; if ( GET_CODE ( base ) != SYMBOL_REF || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; } } return true ; } </s>

Return TRUE if insn is a swap fed by a load from the constant pool .


"Unexpected fixup kind in fixupNeedsRelaxation()!"

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> static __inline unsigned long long sh_media_LDHI_L ( void * p , int s ) { return __builtin_sh_media_LDHI_L ( ( char * ) p + s ) ; } </s>


<s> DecodeStatus SparcDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableSparc32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul\n"
;
if
(
BaseType
==
FrameIndexBase
)
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
;
dbgs
(
)
<<
" Scale "
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul\n"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" MCSym "
;
if
(
MCSym
)
dbgs
(
)
<<
MCSym
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul\n"
" Base.FrameIndex "
" Scale "
"IndexReg "
"nul\n"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" MCSym "
"nul"
" JT"
" Align"


<s>
const
char
*
arm_output_iwmmxt_shift_immediate
(
const
char
*
insn_name
,
rtx
*
operands
,
bool
wror_or_wsra
)
{
int
shift
=
INTVAL
(
operands
[
2
]
)
;
char
templ
[
50
]
;
machine_mode
opmode
=
GET_MODE
(
operands
[
0
]
)
;
gcc_assert
(
shift
>=
0
)
;
if
(
(
(
opmode
==
V4HImode
)
&&
(
shift
>
15
)
)
||
(
(
opmode
==
V2SImode
)
&&
(
shift
>
31
)
)
||
(
(
opmode
==
DImode
)
&&
(
shift
>
63
)
)
)
{
if
(
wror_or_wsra
)
{
sprintf
(
templ
,
"%s\t%%0, %%1, #%d"
,
insn_name
,
32
)
;
output_asm_insn
(
templ
,
operands
)
;
if
(
opmode
==
DImode
)
{
sprintf
(
templ
,
"%s\t%%0, %%0, #%d"
,
insn_name
,
32
)
;
output_asm_insn
(
templ
,
operands
)
;
}
}
else
{
sprintf
(
templ
,
"wzero\t%%0"
)
;
output_asm_insn
(
templ
,
operands
)
;
}
return
""
;
}
if
(
(
opmode
==
DImode
)
&&
(
shift
>
32
)
)
{
sprintf
(
templ
,
"%s\t%%0, %%1, #%d"
,
insn_name
,
32
)
;
output_asm_insn
(
templ
,
operands
)
;
sprintf
(
templ
,
"%s\t%%0, %%0, #%d"
,
insn_name
,
shift
32
)
;
output_asm_insn
(
templ
,
operands
)
;
}
else
{
sprintf
(
templ
,
"%s\t%%0, %%1, #%d"
,
insn_name
,
shift
)
;
output_asm_insn
(
templ
,
operands
)
;
}
return
""
;
}
</s>

Output assembly for a WMMX immediate shift instruction .


<s> void MipsInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool mips_expand_vpc_loongson_bcast ( struct expand_vec_perm_d * d ) { unsigned i , elt ; rtx t0 , t1 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( d -> vmode != V8QImode ) return false ; if ( ! d -> one_vector_p ) return false ; elt = d -> perm [ 0 ] ; for ( i = 1 ; i < 8 ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( V8QImode ) ; if ( elt < 4 ) emit_insn ( gen_loongson_punpcklbh ( t0 , d -> op0 , d -> op0 ) ) ; else emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op0 ) ) ; elt &= 3 ; elt *= 0x55 ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , gen_lowpart ( V4HImode , t0 ) , force_reg ( SImode , GEN_INT ( elt ) ) ) ) ; emit_move_insn ( d -> target , gen_lowpart ( V8QImode , t1 ) ) ; return true ; } </s>

Recognize broadcast patterns for the Loongson .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void mips_declare_object_name ( FILE * stream , const char * name , tree decl ATTRIBUTE_UNUSED ) { ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "object" ) ; size_directive_output = 0 ; if ( ! flag_inhibit_size_directive && DECL_SIZE ( decl ) ) { HOST_WIDE_INT size ; size_directive_output = 1 ; size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; } mips_declare_object ( stream , name , "" , ":\n" ) ; } </s>

Implement ASM_DECLARE_OBJECT_NAME . This is like most of the standard ELF definitions except that it uses mips_declare_object ( ) to emit the label .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Case
(
"x18"
,
AArch64
::
X18
)
.
Case
(
"w18"
,
AArch64
::
W18
)
.
Case
(
"x20"
,
AArch64
::
X20
)
.
Case
(
"w20"
,
AArch64
::
W20
)
.
Default
(
0
)
;
if
(
(
(
Reg
==
AArch64
::
X18
||
Reg
==
AArch64
::
W18
)
&&
!
Subtarget
->
isX18Reserved
(
)
)
||
(
(
Reg
==
AArch64
::
X20
||
Reg
==
AArch64
::
W20
)
&&
!
Subtarget
->
isX20Reserved
(
)
)
)
Reg
=
0
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> enum mips_loadgp_style mips_current_loadgp_style ( void ) { if ( ! TARGET_USE_GOT || cfun -> machine -> global_pointer == INVALID_REGNUM ) return LOADGP_NONE ; if ( TARGET_RTP_PIC ) return LOADGP_RTP ; if ( TARGET_ABSOLUTE_ABICALLS ) return LOADGP_ABSOLUTE ; return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI ; } </s>

Return the style of GP load sequence that is being used for the current function .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget -> is64Bit ( ) ) { unsigned TyAlign = DL . getABITypeAlignment ( Ty ) ; if ( TyAlign > 8 ) return TyAlign ; return 8 ; } unsigned Align = 4 ; if ( Subtarget -> hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ; return Align ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s>
static
void
aarch64_parse_sve_width_string
(
const
char
*
tune_string
,
struct
tune_params
*
tune
)
{
int
width
=
1
;
int
n
=
sscanf
(
tune_string
,
"%d"
,
&
width
)
;
if
(
n
==
EOF
)
{
error
(
"invalid format for sve_width"
)
;
return
;
}
switch
(
width
)
{
case
SVE_128
:
case
SVE_256
:
case
SVE_512
:
case
SVE_1024
:
case
SVE_2048
:
break
;
default
:
error
(
"invalid sve_width value: %d"
,
width
)
;
}
tune
->
sve_width
=
(
enum
aarch64_sve_vector_bits_enum
)
width
;
}
</s>

Parse the sve_width tuning moverride string in TUNE_STRING . Accept the valid SVE vector widths allowed by aarch64_sve_vector_bits_enum and use it to override sve_width in TUNE .


<s> bool mips_expand_ins_as_unaligned_store ( rtx dest , rtx src , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { rtx left , right ; machine_mode mode ; if ( ! mips_get_unaligned_mem ( dest , width , bitpos , & left , & right ) ) return false ; mode = mode_for_size ( width , MODE_INT , 0 ) ; src = gen_lowpart ( mode , src ) ; if ( mode == DImode ) { emit_insn ( gen_mov_sdl ( dest , src , left ) ) ; emit_insn ( gen_mov_sdr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } else { emit_insn ( gen_mov_swl ( dest , src , left ) ) ; emit_insn ( gen_mov_swr ( copy_rtx ( dest ) , copy_rtx ( src ) , right ) ) ; } return true ; } </s>

Try to use left/right stores to expand an `` ins '' pattern . DEST , WIDTH , BITPOS and SRC are the operands passed to the expander ; the operation is the equivalent of : ( set ( zero_extract DEST WIDTH BITPOS ) SRC ) Return true on success .


<s> unsigned ARMTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return Subtarget -> useSjLjEH ( ) ? ARM :: NoRegister : ARM :: R0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> char * aarch64_output_sve_scalar_inc_dec ( rtx offset ) { poly_int64 offset_value = rtx_to_poly_int64 ( offset ) ; gcc_assert ( offset_value . coeffs [ 0 ] == offset_value . coeffs [ 1 ] ) ; if ( offset_value . coeffs [ 1 ] > 0 ) return aarch64_output_sve_cnt_immediate ( "inc" , "%x0" , AARCH64_SV_ALL , offset_value . coeffs [ 1 ] , 0 ) ; else return aarch64_output_sve_cnt_immediate ( "dec" , "%x0" , AARCH64_SV_ALL , - offset_value . coeffs [ 1 ] , 0 ) ; } </s>

Return the asm string for adding SVE INC/DEC immediate OFFSET to operand 0 .


<s> bool AArch64TargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N ) const { EVT VT = N -> getValueType ( 0 ) ; if ( N -> getOpcode ( ) == ISD :: AND && ( VT == MVT :: i32 || VT == MVT :: i64 ) && isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) { uint64_t TruncMask = N -> getConstantOperandVal ( 1 ) ; if ( isMask_64 ( TruncMask ) && N -> getOperand ( 0 ) . getOpcode ( ) == ISD :: SRL && isa < ConstantSDNode > ( N -> getOperand ( 0 ) -> getOperand ( 1 ) ) ) return false ; } return true ; } </s>

Return true if it is profitable to move this shift by a constant amount through its operand , adjusting any immediate operands as necessary to preserve semantics .


<s> static void emit_save_or_restore_regs ( int action ) { HOST_WIDE_INT offset ; rtx base ; offset = frame_base_offset - apparent_fsize ; if ( offset < - 4096 || offset + num_gfregs * 4 > 4095 ) { base = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( base , GEN_INT ( offset ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , base , gen_rtx_PLUS ( Pmode , frame_base_reg , base ) ) ) ; offset = 0 ; } else base = frame_base_reg ; offset = save_or_restore_regs ( 0 , 8 , base , offset , action ) ; save_or_restore_regs ( 32 , TARGET_V9 ? 96 : 64 , base , offset , action ) ; } </s>

Emit code to save call-saved registers .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
&
MI
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
MI
.
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


<s>
const
char
*
pa_output_64bit_ior
(
rtx
*
operands
)
{
unsigned
HOST_WIDE_INT
mask
=
INTVAL
(
operands
[
2
]
)
;
int
bs0
,
bs1
,
p
,
len
;
if
(
INTVAL
(
operands
[
2
]
)
==
0
)
return
"copy %1,%0"
;
for
(
bs0
=
0
;
bs0
<
HOST_BITS_PER_WIDE_INT
;
bs0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs0
)
)
!=
0
)
break
;
for
(
bs1
=
bs0
;
bs1
<
HOST_BITS_PER_WIDE_INT
;
bs1
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs1
)
)
==
0
)
break
;
gcc_assert
(
bs1
==
HOST_BITS_PER_WIDE_INT
||
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs1
)
>
mask
)
;
p
=
63
bs0
;
len
=
bs1
bs0
;
operands
[
2
]
=
GEN_INT
(
p
)
;
operands
[
3
]
=
GEN_INT
(
len
)
;
return
"depdi -1,%2,%3,%0"
;
}
</s>

Return a string to perform a bitwise-and of operands [ 1 ] with operands [ 2 ] storing the result in operands [ 0 ] .


<s> static struct machine_function * mips_init_machine_status ( void ) { return ( ( struct machine_function * ) ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> unsigned MipsFastISel :: fastEmitInst_rr ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , unsigned Op1 ) { if ( MachineInstOpcode == Mips :: MUL ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , II . getNumDefs ( ) ) ; Op1 = constrainOperandRegClass ( II , Op1 , II . getNumDefs ( ) + 1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 ) . addReg ( Op1 ) . addReg ( Mips :: HI0 , RegState :: ImplicitDefine | RegState :: Dead ) . addReg ( Mips :: LO0 , RegState :: ImplicitDefine | RegState :: Dead ) ; return ResultReg ; } return FastISel :: fastEmitInst_rr ( MachineInstOpcode , RC , Op0 , Op1 ) ; } </s>

Emit a MachineInstr with two register operands and a result register in the given register class .


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , neg_bval , mod_s_rtx ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( operands [ 5 ] != const0_rtx ) ; mod_s_rtx = operands [ 6 ] ; mod_s = memmodel_from_int ( INTVAL ( mod_s_rtx ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 7 ] ) ) ; neg_bval = TARGET_THUMB1 ? operands [ 0 ] : operands [ 8 ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && aarch_mm_needs_acquire ( mod_s_rtx ) ; bool use_release = TARGET_HAVE_LDACQ && aarch_mm_needs_release ( mod_s_rtx ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; if ( TARGET_32BIT ) { cond = arm_gen_compare_reg ( NE , rval , oldval , neg_bval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { cond = gen_rtx_NE ( VOIDmode , rval , oldval ) ; if ( thumb1_cmpneg_operand ( oldval , SImode ) ) { rtx src = rval ; if ( ! satisfies_constraint_L ( oldval ) ) { gcc_assert ( satisfies_constraint_J ( oldval ) ) ; emit_move_insn ( neg_bval , rval ) ; src = neg_bval ; } emit_unlikely_jump ( gen_cbranchsi4_neg_late ( neg_bval , src , oldval , label2 , cond ) ) ; } else { emit_move_insn ( neg_bval , const1_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4_insn ( cond , rval , oldval , label2 ) ) ; } } arm_emit_store_exclusive ( mode , neg_bval , mem , newval , use_release ) ; if ( TARGET_32BIT ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , neg_bval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , neg_bval , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , neg_bval , const0_rtx , label1 ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> static int iq2000_address_cost ( rtx addr , machine_mode mode , addr_space_t as , bool speed ) { switch ( GET_CODE ( addr ) ) { case LO_SUM : return 1 ; case LABEL_REF : return 2 ; case CONST : { rtx offset = const0_rtx ; addr = eliminate_constant_term ( XEXP ( addr , 0 ) , & offset ) ; if ( GET_CODE ( addr ) == LABEL_REF ) return 2 ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return 4 ; if ( ! SMALL_INT ( offset ) ) return 2 ; } case SYMBOL_REF : return SYMBOL_REF_FLAG ( addr ) ? 1 : 2 ; case PLUS : { rtx plus0 = XEXP ( addr , 0 ) ; rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && GET_CODE ( plus1 ) == REG ) plus0 = XEXP ( addr , 1 ) , plus1 = XEXP ( addr , 0 ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return SMALL_INT ( plus1 ) ? 1 : 2 ; case CONST : case SYMBOL_REF : case LABEL_REF : case HIGH : case LO_SUM : return iq2000_address_cost ( plus1 , mode , as , speed ) + 1 ; default : break ; } } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR .


<s> bool MLxExpansion :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const ARMBaseInstrInfo * > ( Fn . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & Fn . getRegInfo ( ) ; const ARMSubtarget * STI = & Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI -> expandMLx ( ) ) return false ; isLikeA9 = STI -> isLikeA9 ( ) || STI -> isSwift ( ) ; isSwift = STI -> isSwift ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= ExpandFPMLxInstructions ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"FPDelta isn't aligned per the Win64 ABI!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool ARMBaseInstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: CMPri : case ARM :: t2CMPri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case ARM :: CMPrr : case ARM :: t2CMPrr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case ARM :: TSTri : case ARM :: t2TSTri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = MI . getOperand ( 1 ) . getImm ( ) ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAcquireOrStronger ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> bool ARMGlobalMerge :: runOnFunction ( Function & F ) { return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void rs6000_split_logical_inner ( rtx dest , rtx op1 , rtx op2 , enum rtx_code code , machine_mode mode , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { rtx bool_rtx ; if ( op2 && CONST_INT_P ( op2 ) && ( mode == SImode || ( mode == DImode && TARGET_POWERPC64 ) ) && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { HOST_WIDE_INT mask = GET_MODE_MASK ( mode ) ; HOST_WIDE_INT value = INTVAL ( op2 ) & mask ; if ( code == AND ) { if ( value == 0 ) { emit_insn ( gen_rtx_SET ( dest , const0_rtx ) ) ; return ; } else if ( value == mask ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } else if ( code == IOR || code == XOR ) { if ( value == 0 ) { if ( ! rtx_equal_p ( dest , op1 ) ) emit_insn ( gen_rtx_SET ( dest , op1 ) ) ; return ; } } } if ( code == AND && mode == SImode && ! complement_final_p && ! complement_op1_p && ! complement_op2_p ) { emit_insn ( gen_andsi3 ( dest , op1 , op2 ) ) ; return ; } if ( complement_op1_p ) op1 = gen_rtx_NOT ( mode , op1 ) ; if ( complement_op2_p ) op2 = gen_rtx_NOT ( mode , op2 ) ; if ( ! complement_op1_p && complement_op2_p ) std :: swap ( op1 , op2 ) ; bool_rtx = ( ( code == NOT ) ? gen_rtx_NOT ( mode , op1 ) : gen_rtx_fmt_ee ( code , mode , op1 , op2 ) ) ; if ( complement_final_p ) bool_rtx = gen_rtx_NOT ( mode , bool_rtx ) ; emit_insn ( gen_rtx_SET ( dest , bool_rtx ) ) ; } </s>

Helper function for rs6000_split_logical to emit a logical instruction after spliting the operation to single GPR registers . DEST is the destination register . OP1 and OP2 are the input source registers . CODE is the base operation ( AND , IOR , XOR , NOT ) . MODE is the machine mode . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


<s> unsigned getBranchTargetOpValue ( const MachineInstr & MI , unsigned Op ) const { return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool constant_address_p ( rtx x ) { return CONSTANT_P ( x ) && ix86_legitimate_address_p ( Pmode , x , 1 ) ; } </s>

Determine if a given RTX is a valid constant address .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'h' : return std :: make_pair ( 0U , & SystemZ :: GRH32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } if ( Constraint [ 0 ] == '{' ) { if ( Constraint [ 1 ] == 'r' ) { if ( VT == MVT :: i32 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR32BitRegClass , SystemZMC :: GR32Regs ) ; if ( VT == MVT :: i128 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR128BitRegClass , SystemZMC :: GR128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: GR64BitRegClass , SystemZMC :: GR64Regs ) ; } if ( Constraint [ 1 ] == 'f' ) { if ( VT == MVT :: f32 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP32BitRegClass , SystemZMC :: FP32Regs ) ; if ( VT == MVT :: f128 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP128BitRegClass , SystemZMC :: FP128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: FP64BitRegClass , SystemZMC :: FP64Regs ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool MMIXInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case MMIX :: LDI : expandLDImm ( MI ) ; return true ; case MMIX :: LDA : expandLDAddr ( MI ) ; return true ; } } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> TargetLowering :: ConstraintType XNCMTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
void
ARMAsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
.
getOpcode
(
)
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
if
(
(
Inst
.
getOpcode
(
)
==
ARM
::
tCBZ
||
Inst
.
getOpcode
(
)
==
ARM
::
tCBNZ
)
&&
RelaxedOp
==
ARM
::
tHINT
)
{
Res
.
setOpcode
(
RelaxedOp
)
;
Res
.
addOperand
(
MCOperand
::
CreateImm
(
0
)
)
;
Res
.
addOperand
(
MCOperand
::
CreateImm
(
14
)
)
;
Res
.
addOperand
(
MCOperand
::
CreateReg
(
0
)
)
;
return
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool SHUXIFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void X86FlagsCopyLoweringPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AArch64FrameLowering :: canUseRedZone ( const MachineFunction & MF ) const { if ( ! EnableRedZone ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const AArch64FunctionInfo * AFI = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t NumBytes = AFI -> getLocalStackSize ( ) ; return ! ( MFI . hasCalls ( ) || hasFP ( MF ) || NumBytes > 128 || getSVEStackSize ( MF ) ) ; } </s>

Can this function use the red zone for local allocations .


<s> int arm_attr_length_move_neon ( rtx_insn * insn ) { rtx reg , mem , addr ; int load ; machine_mode mode ; extract_insn_cached ( insn ) ; if ( REG_P ( recog_data . operand [ 0 ] ) && REG_P ( recog_data . operand [ 1 ] ) ) { mode = GET_MODE ( recog_data . operand [ 0 ] ) ; switch ( mode ) { case EImode : case OImode : return 8 ; case CImode : return 12 ; case XImode : return 16 ; default : gcc_unreachable ( ) ; } } load = REG_P ( recog_data . operand [ 0 ] ) ; reg = recog_data . operand [ ! load ] ; mem = recog_data . operand [ load ] ; gcc_assert ( MEM_P ( mem ) ) ; mode = GET_MODE ( reg ) ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS ) addr = XEXP ( addr , 0 ) ; if ( GET_CODE ( addr ) == LABEL_REF || GET_CODE ( addr ) == PLUS ) { int insns = HARD_REGNO_NREGS ( REGNO ( reg ) , mode ) / 2 ; return insns * 4 ; } else return 4 ; } </s>

Compute and return the length of neon_mov < mode > , where < mode > is one of VSTRUCT modes : EI , OI , CI or XI .


<s> static int add_sp_insn_p ( rtx_insn * insn ) { rtx pat ; if ( ! single_set ( insn ) ) return 0 ; pat = PATTERN ( insn ) ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG ) return 0 ; if ( REGNO ( SET_DEST ( pat ) ) != SP_REGNO ) return 0 ; if ( GET_CODE ( SET_SRC ( pat ) ) != PLUS ) return 0 ; if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 0 ) ) != REG ) return 0 ; if ( REGNO ( XEXP ( SET_SRC ( pat ) , 0 ) ) != SP_REGNO ) return 0 ; if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , 1 ) ) != CONST_INT ) return 0 ; return INTVAL ( XEXP ( SET_SRC ( pat ) , 1 ) ) ; } </s>

If this insn adjusts the stack , return the adjustment , else return zero .


<s> void ARMELFMCAsmInfo :: setUseIntegratedAssembler ( bool Value ) { UseIntegratedAssembler = Value ; if ( ! UseIntegratedAssembler ) { DwarfRegNumForCFI = true ; } } </s>

Set whether assembly ( inline or otherwise ) should be parsed .


<s> static void ix86_emit_restore_regs_using_mov ( rtx pointer , HOST_WIDE_INT offset , int maybe_eh_return ) { int regno ; rtx base_address = gen_rtx_MEM ( Pmode , pointer ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ix86_save_reg ( regno , maybe_eh_return ) ) { if ( TARGET_64BIT && offset != trunc_int_for_mode ( offset , SImode ) ) { rtx r11 ; r11 = gen_rtx_REG ( DImode , FIRST_REX_INT_REG + 3 ) ; emit_move_insn ( r11 , GEN_INT ( offset ) ) ; emit_insn ( gen_adddi3 ( r11 , r11 , pointer ) ) ; base_address = gen_rtx_MEM ( Pmode , r11 ) ; offset = 0 ; } emit_move_insn ( gen_rtx_REG ( Pmode , regno ) , adjust_address ( base_address , Pmode , offset ) ) ; offset += UNITS_PER_WORD ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from POINTER + OFFSET .


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case DImode : case SCmode : case DCmode : case TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && TARGET_FPRS && ! FLOAT128_VECTOR_P ( mode ) && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || FLOAT128_VECTOR_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> void arm_emit_call_insn ( rtx pat , rtx addr , bool sibcall ) { rtx insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && ! sibcall && GET_CODE ( addr ) == SYMBOL_REF && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr ) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) { require_pic_register ( ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , cfun -> machine -> pic_reg ) ; } if ( TARGET_AAPCS_BASED ) { rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP_REGNUM ) ) ; } } </s>

Emit a call instruction with pattern PAT . ADDR is the address of the call target .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
AArch64_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> void SystemZHazardRecognizer :: Reset ( ) { CurrGroupSize = 0 ; clearProcResCounters ( ) ; GrpCount = 0 ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ; DEBUG ( CurGroupDbg = "" ; ) ; } </s>


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
if
(
!
ST
->
isThumb2
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
unsigned
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
ImmutableCallSite
CS
(
&
I
)
;
if
(
const
Function
*
F
=
CS
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
value_op_begin
(
)
,
I
.
value_op_end
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UpperBound
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; if ( ( SVT . is128BitVector ( ) && Subtarget -> hasSSSE3 ( ) ) || ( SVT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ) { bool isLegal = true ; for ( unsigned I = 0 , E = M . size ( ) ; I != E ; ++ I ) { if ( M [ I ] >= ( int ) SVT . getVectorNumElements ( ) || ShuffleCrosses128bitLane ( SVT , I , M [ I ] ) ) { isLegal = false ; break ; } } if ( isLegal ) return true ; } return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isMOVHLPSMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isPSHUFDMask ( M , SVT ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isBlendMask ( M , SVT , Subtarget -> hasSSE41 ( ) , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORWrr
)
)
;
case
X86
::
KSET0D
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORDrr
)
)
;
case
X86
::
KSET0Q
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXORQrr
)
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORWrr
)
)
;
case
X86
::
KSET1D
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORDrr
)
)
;
case
X86
::
KSET1Q
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
KXNORQrr
)
)
;
case
TargetOpcode
::
LOAD_STACK_GUARD
:
expandLoadStackGuard
(
MIB
,
*
this
)
;
return
true
;
}
return
false
;
}
</s>


<s> static bool expand_vec_perm_even_odd ( struct expand_vec_perm_d * d ) { unsigned i , odd , nelt = d -> nelt ; odd = d -> perm [ 0 ] ; if ( odd != 0 && odd != 1 ) return false ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != 2 * i + odd ) return false ; if ( d -> vmode == E_V32HImode && d -> testing_p && ! TARGET_AVX512BW ) return false ; return expand_vec_perm_even_odd_1 ( d , odd ) ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Pattern match extract-even and extract-odd permutations .


<s> bool shouldTrackPressure ( ) const override { return false ; } </s>

PostRA scheduling does not track pressure .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


Control the placement of special register scavenging spill slots when allocating a stack frame .


<s> void order_regs_for_local_alloc ( void ) { static int last_order_nonleaf = 1 ; if ( df_regs_ever_live_p ( 15 ) != last_order_nonleaf ) { last_order_nonleaf = ! last_order_nonleaf ; memcpy ( ( char * ) reg_alloc_order , ( const char * ) reg_alloc_orders [ last_order_nonleaf ] , FIRST_PSEUDO_REGISTER * sizeof ( int ) ) ; } } </s>

Choose the order in which to allocate hard registers for pseudo-registers local to a basic block . Store the desired register order in the array ` reg_alloc_order ' . Element 0 should be the register to allocate first ; element 1 , the next register ; and so on .


"module has aliases, which LLVM does not yet support for AIX"

Set up the AsmPrinter when we are working on a new module .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_tune ) { case PROCESSOR_RS64A : case PROCESSOR_PPC601 : case PROCESSOR_PPC7450 : return 3 ; case PROCESSOR_PPC440 : case PROCESSOR_PPC603 : case PROCESSOR_PPC750 : case PROCESSOR_PPC7400 : case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : case PROCESSOR_CELL : case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case PROCESSOR_PPCE6500 : case PROCESSOR_TITAN : return 2 ; case PROCESSOR_PPC476 : case PROCESSOR_PPC604 : case PROCESSOR_PPC604e : case PROCESSOR_PPC620 : case PROCESSOR_PPC630 : return 4 ; case PROCESSOR_POWER4 : case PROCESSOR_POWER5 : case PROCESSOR_POWER6 : case PROCESSOR_POWER7 : return 5 ; case PROCESSOR_POWER8 : return 7 ; case PROCESSOR_POWER9 : return 6 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> static rtx arm_function_arg ( cumulative_args_t pcum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int nregs ; if ( mode == VOIDmode ) return const0_rtx ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { aapcs_layout_arg ( pcum , mode , type , named ) ; return pcum -> aapcs_reg ; } if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( mode ) && pcum -> named_count > pcum -> nargs + 1 ) { if ( pcum -> iwmmxt_nregs <= 9 ) return gen_rtx_REG ( mode , pcum -> iwmmxt_nregs + FIRST_IWMMXT_REGNUM ) ; else { pcum -> can_split = false ; return NULL_RTX ; } } if ( pcum -> nregs & 1 && ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align ( mode , type ) ) pcum -> nregs ++ ; if ( pcum -> can_split ) nregs = 1 ; else nregs = ARM_NUM_REGS2 ( mode , type ) ; if ( ! named || pcum -> nregs + nregs > NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( mode , pcum -> nregs ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : return C_RegisterClass ; break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const MCPhysReg * X86TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const { static const MCPhysReg ScratchRegs [ ] = { X86 :: R11 , 0 } ; return ScratchRegs ; } </s>

Returns a 0 terminated array of registers that can be safely used as scratch registers .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> registered_function & function_builder :: add_function ( const function_instance & instance , const char * name , tree fntype , tree attrs , uint64_t required_extensions , bool overloaded_p ) { unsigned int code = vec_safe_length ( registered_functions ) ; code = ( code << AARCH64_BUILTIN_SHIFT ) | AARCH64_BUILTIN_SVE ; tree decl = simulate_builtin_function_decl ( input_location , name , fntype , code , NULL , attrs ) ; registered_function & rfn = * ggc_alloc < registered_function > ( ) ; rfn . instance = instance ; rfn . decl = decl ; rfn . required_extensions = required_extensions ; rfn . overloaded_p = overloaded_p ; vec_safe_push ( registered_functions , & rfn ) ; return rfn ; } </s>

Add a function called NAME with type FNTYPE and attributes ATTRS . INSTANCE describes what the function does .


<s>
void
X86IntelInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> unsigned int ix86_minimum_alignment ( tree exp , machine_mode mode , unsigned int align ) { tree type , decl ; if ( exp && DECL_P ( exp ) ) { type = TREE_TYPE ( exp ) ; decl = exp ; } else { type = exp ; decl = NULL ; } if ( TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64 ) return align ; if ( ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ( ! TYPE_USER_ALIGN ( type ) && ! TYPE_ATOMIC ( strip_array_types ( type ) ) ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) { gcc_checking_assert ( ! TARGET_STV ) ; return 32 ; } return align ; } </s>

Compute the minimum required alignment for dynamic stack realignment purposes for a local variable , parameter or a stack slot . EXP is the data type or decl itself , MODE is its mode and ALIGN is the alignment that the object would ordinarily have .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlign ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } llvm :: stable_sort ( SortingObjects , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> void ix86_emit_fp_unordered_jump ( rtx label ) { rtx reg = gen_reg_rtx ( HImode ) ; rtx temp ; emit_insn ( gen_x86_fnstsw_1 ( reg ) ) ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) { emit_insn ( gen_x86_sahf_1 ( reg ) ) ; temp = gen_rtx_REG ( CCmode , FLAGS_REG ) ; temp = gen_rtx_UNORDERED ( VOIDmode , temp , const0_rtx ) ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( reg , GEN_INT ( 0x04 ) ) ) ; temp = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; temp = gen_rtx_NE ( VOIDmode , temp , const0_rtx ) ; } temp = gen_rtx_IF_THEN_ELSE ( VOIDmode , temp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; temp = gen_rtx_SET ( pc_rtx , temp ) ; emit_jump_insn ( temp ) ; predict_jump ( REG_BR_PROB_BASE * 10 / 100 ) ; } </s>

Output code to perform a conditional jump to LABEL , if C2 flag in FP status register is set .


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
return
Res
;
}
</s>


"All AArch64 cmps should have 2 operands"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> int ix86_data_alignment ( tree type , int align , bool opt ) { int max_align_compat = MIN ( 256 , MAX_OFILE_ALIGNMENT ) ; int max_align = MIN ( ( unsigned ) ix86_tune_cost -> prefetch_block * 8 , MAX_OFILE_ALIGNMENT ) ; if ( max_align < BITS_PER_WORD ) max_align = BITS_PER_WORD ; switch ( ix86_align_data_type ) { case ix86_align_data_type_abi : opt = false ; break ; case ix86_align_data_type_compat : max_align = BITS_PER_WORD ; break ; case ix86_align_data_type_cacheline : break ; } if ( TARGET_IAMCU ) align = iamcu_alignment ( type , align ) ; if ( opt && AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) { if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align_compat ) && align < max_align_compat ) align = max_align_compat ; if ( wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , max_align ) && align < max_align ) align = max_align ; } if ( TARGET_64BIT ) { if ( ( opt ? AGGREGATE_TYPE_P ( type ) : TREE_CODE ( type ) == ARRAY_TYPE ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( wi :: to_wide ( TYPE_SIZE ( type ) ) , 128 ) && align < 128 ) return 128 ; } if ( ! opt ) return align ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s>
bool
ARMTargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
bool
EltIs64Bits
=
DL
.
getTypeAllocSizeInBits
(
EltTy
)
==
64
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
||
EltIs64Bits
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
Op0
->
getType
(
)
->
getVectorNumElements
(
)
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
arm_neon_vst2
,
Intrinsic
::
arm_neon_vst3
,
Intrinsic
::
arm_neon_vst4
}
;
SmallVector
<
Value
*
,
6
>
Ops
;
Type
*
Int8Ptr
=
Builder
.
getInt8PtrTy
(
SI
->
getPointerAddressSpace
(
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
Int8Ptr
)
)
;
Type
*
Tys
[
]
=
{
Int8Ptr
,
SubVecTy
}
;
Function
*
VstNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
getInt32
(
SI
->
getAlignment
(
)
)
)
;
Builder
.
CreateCall
(
VstNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> TargetIRAnalysis SystemZTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( SystemZTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( GET_CODE ( op ) != SYMBOL_REF ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; return dalign >= dsize ; } } else gcc_unreachable ( ) ; dalign /= BITS_PER_UNIT ; if ( dalign > POWERPC64_TOC_POINTER_ALIGNMENT ) dalign = POWERPC64_TOC_POINTER_ALIGNMENT ; mask = dalign - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { MachineFunction * MF = CurBB -> getParent ( ) ; unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s>
unsigned
LanaiTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"pc"
,
Lanai
::
PC
)
.
Case
(
"sp"
,
Lanai
::
SP
)
.
Case
(
"fp"
,
Lanai
::
FP
)
.
Case
(
"rr1"
,
Lanai
::
RR1
)
.
Case
(
"r10"
,
Lanai
::
R10
)
.
Case
(
"rr2"
,
Lanai
::
RR2
)
.
Case
(
"r11"
,
Lanai
::
R11
)
.
Case
(
"rca"
,
Lanai
::
RCA
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> static tree rs6000_builtin_reciprocal ( tree fndecl ) { switch ( DECL_MD_FUNCTION_CODE ( fndecl ) ) { case VSX_BUILTIN_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_4SF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> static bool loongarch_mode_ok_for_mov_fmt_p ( machine_mode mode ) { switch ( mode ) { case E_FCCmode : case E_SFmode : return TARGET_HARD_FLOAT ; case E_DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; default : return 0 ; } } </s>

Return true if moves in mode MODE can use the FPU 's fmov.fmt instruction ,


<s> bool ARMBaseInstrInfo :: isPredicable ( MachineInstr & MI ) const { if ( ! MI . isPredicable ( ) ) return false ; if ( MI . isBundle ( ) ) return false ; if ( ! isEligibleForITBlock ( & MI ) ) return false ; ARMFunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } else { if ( ( MI . getDesc ( ) . TSFlags & ARMII :: DomainMask ) == ARMII :: DomainNEON ) return false ; } return true ; } </s>

Return true if the specified instruction can be predicated .

ARM ARM ARM ARM ARMII::DomainMask ARMII::DomainNEON


<s> static bool mips_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { if ( mips_abi == ABI_EABI ) { int size ; if ( mode == DImode || mode == DFmode || mode == DQmode || mode == UDQmode || mode == DAmode || mode == UDAmode ) return 0 ; size = type ? int_size_in_bytes ( type ) : GET_MODE_SIZE ( mode ) ; return size == - 1 || size > UNITS_PER_WORD ; } else { return targetm . calls . must_pass_in_stack ( mode , type ) ; } } </s>

Return nonzero when an argument must be passed by reference .


<s> unsigned getMaxNumElements ( ElementCount VF , const Function * F = nullptr ) const { if ( ! VF . isScalable ( ) ) return VF . getFixedValue ( ) ; unsigned MaxNumVScale = 16 ; if ( F && F -> hasFnAttribute ( Attribute :: VScaleRange ) ) { unsigned VScaleMax = F -> getFnAttribute ( Attribute :: VScaleRange ) . getVScaleRangeArgs ( ) . second ; if ( VScaleMax > 0 ) MaxNumVScale = VScaleMax ; } return MaxNumVScale * VF . getKnownMinValue ( ) ; } </s>

Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF .


<s> static rtx aarch64_gen_storewb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case E_DImode : return gen_storewb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; case E_DFmode : return gen_storewb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ; default : gcc_unreachable ( ) ; } } </s>

Generate and return an instruction to store the pair of registers REG and REG2 of mode MODE to location BASE with write-back adjusting the stack location BASE by ADJUSTMENT .


<s> static const struct mips_cpu_info * mips_cpu_info_from_isa ( int isa ) { const struct mips_cpu_info * p ; for ( p = mips_cpu_info_table ; p -> name != 0 ; p ++ ) if ( p -> isa == isa ) return p ; return 0 ; } </s>

Return the processor associated with the given ISA level , or null if the ISA is n't valid .


<s> const LanaiSubtarget * getSubtargetImpl ( const llvm :: Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> int sparc_splitdi_legitimate ( rtx reg , rtx mem ) { gcc_assert ( reload_completed ) ; if ( ! offsettable_memref_p ( mem ) ) return 0 ; if ( ( REGNO ( reg ) % 2 ) == 0 && mem_min_alignment ( mem , 8 ) ) return 0 ; return 1 ; } </s>

Return 1 if REG and MEM are legitimate enough to allow the various mem < -- > reg splits to be run .


<s> static int shmedia_target_regs_stack_space ( HARD_REG_SET * live_regs_mask ) { int reg ; int stack_space = 0 ; int interrupt_handler = sh_cfun_interrupt_handler_p ( ) ; for ( reg = LAST_TARGET_REG ; reg >= FIRST_TARGET_REG ; reg -- ) if ( ( ! call_really_used_regs [ reg ] || interrupt_handler ) && ! TEST_HARD_REG_BIT ( * live_regs_mask , reg ) ) stack_space += GET_MODE_SIZE ( REGISTER_NATURAL_MODE ( reg ) ) ; return stack_space ; } </s>

Calculate how much extra space is needed to save all callee-saved target registers . LIVE_REGS_MASK is the register mask calculated by calc_live_regs .


<s> static void aarch64_init_bf16_types ( void ) { lang_hooks . types . register_builtin_type ( bfloat16_type_node , "__bf16" ) ; aarch64_bf16_ptr_type_node = build_pointer_type ( bfloat16_type_node ) ; } </s>

Initialize the backend REAL_TYPE type supporting bfloat types .