<s> void aarch64_expand_epilogue ( bool for_sibcall ) { aarch64_layout_frame ( ) ; HOST_WIDE_INT initial_adjust = cfun -> machine -> frame . initial_adjust ; HOST_WIDE_INT callee_adjust = cfun -> machine -> frame . callee_adjust ; HOST_WIDE_INT final_adjust = cfun -> machine -> frame . final_adjust ; HOST_WIDE_INT callee_offset = cfun -> machine -> frame . callee_offset ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; rtx cfi_ops = NULL ; rtx_insn * insn ; bool need_barrier_p = ( get_frame_size ( ) + cfun -> machine -> frame . saved_varargs_size ) != 0 ; if ( final_adjust > crtl -> outgoing_args_size || cfun -> calls_alloca || crtl -> calls_eh_return ) { emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; need_barrier_p = false ; } if ( frame_pointer_needed && ( final_adjust || cfun -> calls_alloca ) ) { insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - callee_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = callee_adjust == 0 ; } else aarch64_add_sp ( IP1_REGNUM , final_adjust , df_regs_ever_live_p ( IP1_REGNUM ) ) ; aarch64_restore_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != 0 , & cfi_ops ) ; aarch64_restore_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != 0 , & cfi_ops ) ; if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != 0 ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != 0 || initial_adjust > 65536 ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; cfi_ops = NULL ; } aarch64_add_sp ( IP0_REGNUM , initial_adjust , df_regs_ever_live_p ( IP0_REGNUM ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) = cfi_ops ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( aarch64_return_address_signing_enabled ( ) && ( for_sibcall || ! TARGET_ARMV8_3 || crtl -> calls_eh_return ) ) { insn = emit_insn ( gen_autisp ( ) ) ; add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( crtl -> calls_eh_return ) { emit_insn ( gen_add2_insn ( stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } emit_use ( gen_rtx_REG ( DImode , LR_REGNUM ) ) ; if ( ! for_sibcall ) emit_jump_insn ( ret_rtx ) ; } </s>

Generate the epilogue instructions for returning from a function .


<s>
void
i386_pe_seh_cold_init
(
FILE
*
f
,
const
char
*
name
)
{
struct
seh_frame_state
*
seh
;
HOST_WIDE_INT
alloc_offset
,
offset
;
if
(
!
TARGET_SEH
)
return
;
if
(
cfun
->
is_thunk
)
return
;
seh
=
cfun
->
machine
->
seh
;
fputs
(
"\t.seh_proc\t"
,
f
)
;
assemble_name
(
f
,
name
)
;
fputc
(
'\n'
,
f
)
;
offset
=
seh
->
sp_offset
INCOMING_FRAME_SP_OFFSET
;
if
(
offset
<
SEH_MAX_FRAME_SIZE
&&
!
crtl
->
accesses_prior_frames
)
alloc_offset
=
seh
->
sp_offset
;
else
alloc_offset
=
MIN
(
seh
->
cfa_offset
+
240
,
seh
->
sp_offset
)
;
offset
=
alloc_offset
INCOMING_FRAME_SP_OFFSET
;
if
(
offset
>
0
)
fprintf
(
f
,
"\t.seh_stackalloc\t"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
for
(
int
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
seh
->
reg_offset
[
regno
]
>
0
&&
seh
->
reg_offset
[
regno
]
<=
alloc_offset
)
{
if
(
SSE_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savexmm\t"
,
f
)
;
else
if
(
GENERAL_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savereg\t"
,
f
)
;
else
gcc_unreachable
(
)
;
print_reg
(
gen_rtx_REG
(
DImode
,
regno
)
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
alloc_offset
seh
->
reg_offset
[
regno
]
)
;
}
if
(
seh
->
cfa_reg
!=
stack_pointer_rtx
)
{
offset
=
alloc_offset
seh
->
cfa_offset
;
gcc_assert
(
(
offset
&
15
)
==
0
)
;
gcc_assert
(
IN_RANGE
(
offset
,
0
,
240
)
)
;
fputs
(
"\t.seh_setframe\t"
,
f
)
;
print_reg
(
seh
->
cfa_reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
if
(
alloc_offset
!=
seh
->
sp_offset
)
{
offset
=
seh
->
sp_offset
alloc_offset
;
if
(
offset
>
0
&&
offset
<
SEH_MAX_FRAME_SIZE
)
fprintf
(
f
,
"\t.seh_stackalloc\t"
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
for
(
int
regno
=
0
;
regno
<
FIRST_PSEUDO_REGISTER
;
regno
++
)
if
(
seh
->
reg_offset
[
regno
]
>
alloc_offset
)
{
if
(
SSE_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savexmm\t"
,
f
)
;
else
if
(
GENERAL_REGNO_P
(
regno
)
)
fputs
(
"\t.seh_savereg\t"
,
f
)
;
else
gcc_unreachable
(
)
;
print_reg
(
gen_rtx_REG
(
DImode
,
regno
)
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
seh
->
sp_offset
seh
->
reg_offset
[
regno
]
)
;
}
}
fputs
(
"\t.seh_endprologue\n"
,
f
)
;
}
</s>

Emit assembler directives to reconstruct the SEH state .


<s> static inline int shiftcosts ( rtx x ) { int value ; if ( TARGET_SHMEDIA ) return 1 ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == 1 ) return 2 ; return 10000 ; } if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return SH_DYNAMIC_SHIFT_COST ; value = INTVAL ( XEXP ( x , 1 ) ) ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > 1 + SH_DYNAMIC_SHIFT_COST ) cost = 1 + SH_DYNAMIC_SHIFT_COST ; return cost ; } else return shift_insns [ value ] ; } </s>


<s>
const
char
*
nds32_output_16bit_store
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
char
size
;
rtx
code
=
XEXP
(
operands
[
0
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
nds32_mem_format
(
operands
[
0
]
)
)
{
case
ADDRESS_REG
:
operands
[
0
]
=
code
;
output_asm_insn
(
"swi450\t%1, [%0]"
,
operands
)
;
break
;
case
ADDRESS_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci333\t%%1, %%0"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_INC_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci333.bi\t%%1, %%0"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_FP_IMM7U
:
output_asm_insn
(
"swi37\t%1, %0"
,
operands
)
;
break
;
case
ADDRESS_SP_IMM7U
:
operands
[
0
]
=
XEXP
(
code
,
1
)
;
output_asm_insn
(
"swi37.sp\t%1, [ + (%0)]"
,
operands
)
;
break
;
default
:
break
;
}
return
""
;
}
</s>


<s> bool PPCRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; return true ; } </s>

True if the stack can be realigned for the target .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static bool arm_vectorize_vec_perm_const_ok ( machine_mode vmode , const unsigned char * sel ) { struct expand_vec_perm_d d ; unsigned int i , nelt , which ; bool ret ; d . vmode = vmode ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = true ; memcpy ( d . perm , sel , nelt ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < 2 * nelt ) ; which |= ( e < nelt ? 1 : 2 ) ; } if ( which == 2 ) for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_vector_p = ( which != 3 ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ret = arm_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , DebugLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s>
bool
ARMBlockPlacement
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
DEBUG_PREFIX
<<
"Running on "
<<
MF
.
getName
(
)
<<
"\n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
MF
.
RenumberBlocks
(
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
RevertedWhileLoops
.
clear
(
)
;
for
(
auto
*
ML
:
*
MLI
)
Changed
|=
processPostOrderLoops
(
ML
)
;
for
(
auto
*
WlsInstr
:
RevertedWhileLoops
)
Changed
|=
revertWhileToDoLoop
(
WlsInstr
)
;
return
Changed
;
}
</s>

ARM
ARM
ARM
ARM
"Running on "
"\n"
ARM
ARM
ARM


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESSRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
LOW32_ADDR_ACCESS_RBPRegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
if
(
X86
::
FR32XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
FR64XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR128XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR256XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR512RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
VECRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s> static unsigned int mips_global_pointer ( void ) { unsigned int regno ; if ( ! TARGET_USE_GOT ) return GLOBAL_POINTER_REGNUM ; if ( mips_cfun_has_inflexible_gp_ref_p ( ) ) return GLOBAL_POINTER_REGNUM ; if ( TARGET_ABSOLUTE_JUMPS && ! mips_cfun_has_flexible_gp_ref_p ( ) ) return INVALID_REGNUM ; if ( TARGET_CALL_SAVED_GP && crtl -> is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM ; } </s>

Return the register that should be used as the global pointer within this function . Return 0 if the function does n't need a global pointer .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask ) ; return Subtarget . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : CSR_SVR432_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
X86TargetLowering
::
allowTruncateForTailCall
(
Type
*
Ty1
,
Type
*
Ty2
)
const
{
if
(
!
Ty1
->
isIntegerTy
(
)
||
!
Ty2
->
isIntegerTy
(
)
)
return
false
;
if
(
!
isTypeLegal
(
EVT
::
getEVT
(
Ty1
)
)
)
return
false
;
assert
(
Ty1
->
getPrimitiveSizeInBits
(
)
<=
64
&&
"i128 is probably not a noop"
)
;
return
true
;
}
</s>

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position .


<s> const char * sh_symbian_strip_name_encoding ( const char * name ) { int skip ; while ( ( skip = sh_symbian_get_strip_length ( * name ) ) ) name += skip ; return name ; } </s>

Return a pointer to a function 's name with any and all prefix encodings stripped from it .


<s> bool SystemZInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb , AliasAnalysis * AA ) const { if ( ! MIa . hasOneMemOperand ( ) || ! MIb . hasOneMemOperand ( ) ) return false ; MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ; int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ; int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> void Comet2ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> void LC2200InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
const
RegisterBankInfo
*
X86Subtarget
::
getRegBankInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getRegBankInfo
(
)
;
}
</s>

If the information for the register banks is available , return it .


<s> bool DLXTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return isGlobalInSmallSectionImpl ( GO , TM ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> const SparcSubtarget * SparcTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < SparcSubtarget > ( TargetTriple , CPU , FS , * this , this -> is64Bit ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Sparc Sparc Sparc "target-cpu" "target-features" "use-soft-float" "use-soft-float" "true" "+soft-float" ",+soft-float" Sparc


<s> static bool xstormy16_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


"%qs attribute only applies to functions"


"\t! The vector %02d is a critical isr !\n"

Function to emit isr jump table section .


<s> MCSymbol * AArch64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s>
MachineBasicBlock
*
OR1KTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
OR1K
::
Select
:
case
OR1K
::
Selectf32
:
return
emitSelect
(
MI
,
BB
)
;
case
OR1K
::
ATOMIC_LOAD_ADD_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
ADD
)
;
case
OR1K
::
ATOMIC_LOAD_AND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
AND
)
;
case
OR1K
::
ATOMIC_LOAD_OR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
OR
)
;
case
OR1K
::
ATOMIC_LOAD_XOR_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
XOR
)
;
case
OR1K
::
ATOMIC_LOAD_NAND_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
0
,
true
)
;
case
OR1K
::
ATOMIC_LOAD_SUB_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
OR1K
::
SUB
)
;
case
OR1K
::
ATOMIC_SWAP_I32
:
return
emitAtomicBinary
(
MI
,
BB
,
0
)
;
case
OR1K
::
ATOMIC_CMP_SWAP_I32
:
return
emitAtomicCmpSwap
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ; } </s>


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'f' : case 'r' : return C_RegisterClass ; case 'I' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetSubtargetInfo * STI , const ScheduleDAG * DAG ) const { unsigned Directive = static_cast < const PPCSubtarget * > ( STI ) -> getMcpu ( ) ; if ( Directive == PPC :: MCPU_440 || Directive == PPC :: MCPU_A2 || Directive == PPC :: MCPU_E500mc || Directive == PPC :: MCPU_E5500 ) { const InstrItineraryData * II = static_cast < const PPCSubtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == MVT :: f64 && X86ScalarSSEf64 ) || ( VT == MVT :: f32 && X86ScalarSSEf32 ) || ( VT == MVT :: f16 && X86ScalarSSEf16 ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


"rs6000_secondary_reload_inner:%d, type = %s\n"

Better tracing for rs6000_secondary_reload_inner .


<s> static int ix86_flags_dependant ( rtx insn , rtx dep_insn , enum attr_type insn_type ) { rtx set , set2 ; if ( insn_type != TYPE_SETCC && insn_type != TYPE_ICMOV && insn_type != TYPE_FCMOV && insn_type != TYPE_IBR ) return 0 ; if ( ( set = single_set ( dep_insn ) ) != 0 ) { set = SET_DEST ( set ) ; set2 = NULL_RTX ; } else if ( GET_CODE ( PATTERN ( dep_insn ) ) == PARALLEL && XVECLEN ( PATTERN ( dep_insn ) , 0 ) == 2 && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) == SET && GET_CODE ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 1 ) ) == SET ) { set = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; set2 = SET_DEST ( XVECEXP ( PATTERN ( dep_insn ) , 0 , 0 ) ) ; } else return 0 ; if ( GET_CODE ( set ) != REG || REGNO ( set ) != FLAGS_REG ) return 0 ; if ( ! reg_overlap_mentioned_p ( set , PATTERN ( insn ) ) ) return 0 ; if ( set2 && reg_overlap_mentioned_p ( set2 , PATTERN ( insn ) ) ) return 0 ; return 1 ; } </s>

A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set by DEP_INSN and nothing set by DEP_INSN .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , Address , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>


<s> int num_insns_constant_wide ( HOST_WIDE_INT value ) { if ( CONST_OK_FOR_LETTER_P ( value , 'I' ) ) return 1 ; else if ( CONST_OK_FOR_LETTER_P ( value , 'L' ) ) return 1 ; else if ( TARGET_POWERPC64 ) { HOST_WIDE_INT low = ( ( value & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; HOST_WIDE_INT high = value >> 31 ; if ( high == 0 || high == - 1 ) return 2 ; high >>= 1 ; if ( low == 0 ) return num_insns_constant_wide ( high ) + 1 ; else return ( num_insns_constant_wide ( high ) + num_insns_constant_wide ( low ) + 1 ) ; } else return 2 ; } </s>

Return the number of instructions it takes to form a constant in an integer register .


<s> unsigned int mips_sync_loop_insns ( rtx_insn * insn , rtx * operands ) { mips_branch_likely = TARGET_FIX_R10000 ; mips_process_sync_loop ( insn , operands ) ; return mips_multi_num_insns ; } </s>

Return the number of individual instructions in sync loop INSN , which has the operands given by OPERANDS .


<s> void MandarinFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MandarinInstrInfo & TII = * static_cast < const MandarinInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( Size ) { if ( MI . getOpcode ( ) == MD :: ADJCALLSTACKDOWN ) { BuildMI ( MF , MI . getDebugLoc ( ) , TII . get ( MD :: SUBri ) , MD :: R30 ) . addReg ( MD :: R30 ) . addImm ( Size ) ; } else { BuildMI ( MF , MI . getDebugLoc ( ) , TII . get ( MD :: ADDri ) , MD :: R30 ) . addReg ( MD :: R30 ) . addImm ( Size ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool LanaiInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TrueBlock , MachineBasicBlock * & FalseBlock , SmallVectorImpl < MachineOperand > & Condition , bool AllowModify ) const { MachineBasicBlock :: iterator Instruction = MBB . end ( ) ; while ( Instruction != MBB . begin ( ) ) { -- Instruction ; if ( Instruction -> isDebugInstr ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * Instruction ) ) break ; if ( ! Instruction -> isBranch ( ) ) return true ; if ( Instruction -> getOpcode ( ) == Lanai :: BT ) { if ( ! AllowModify ) { TrueBlock = Instruction -> getOperand ( 0 ) . getMBB ( ) ; continue ; } while ( std :: next ( Instruction ) != MBB . end ( ) ) { std :: next ( Instruction ) -> eraseFromParent ( ) ; } Condition . clear ( ) ; FalseBlock = nullptr ; if ( MBB . isLayoutSuccessor ( Instruction -> getOperand ( 0 ) . getMBB ( ) ) ) { TrueBlock = nullptr ; Instruction -> eraseFromParent ( ) ; Instruction = MBB . end ( ) ; continue ; } TrueBlock = Instruction -> getOperand ( 0 ) . getMBB ( ) ; continue ; } unsigned Opcode = Instruction -> getOpcode ( ) ; if ( Opcode != Lanai :: BRCC ) return true ; if ( Condition . empty ( ) ) { LPCC :: CondCode BranchCond = static_cast < LPCC :: CondCode > ( Instruction -> getOperand ( 1 ) . getImm ( ) ) ; FalseBlock = TrueBlock ; TrueBlock = Instruction -> getOperand ( 0 ) . getMBB ( ) ; Condition . push_back ( MachineOperand :: CreateImm ( BranchCond ) ) ; continue ; } return true ; } return false ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> SDValue SystemZTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ZERO_EXTEND : return combineZERO_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND : return combineSIGN_EXTEND ( N , DCI ) ; case ISD :: SIGN_EXTEND_INREG : return combineSIGN_EXTEND_INREG ( N , DCI ) ; case SystemZISD :: MERGE_HIGH : case SystemZISD :: MERGE_LOW : return combineMERGE ( N , DCI ) ; case ISD :: STORE : return combineSTORE ( N , DCI ) ; case ISD :: EXTRACT_VECTOR_ELT : return combineEXTRACT_VECTOR_ELT ( N , DCI ) ; case SystemZISD :: JOIN_DWORDS : return combineJOIN_DWORDS ( N , DCI ) ; case ISD :: FP_ROUND : return combineFP_ROUND ( N , DCI ) ; case ISD :: BSWAP : return combineBSWAP ( N , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : case ISD :: ROTL : return combineSHIFTROT ( N , DCI ) ; case SystemZISD :: BR_CCMASK : return combineBR_CCMASK ( N , DCI ) ; case SystemZISD :: SELECT_CCMASK : return combineSELECT_CCMASK ( N , DCI ) ; case SystemZISD :: GET_CCMASK : return combineGET_CCMASK ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
MIB
.
addUse
(
PhysReg
,
RegState
::
Implicit
)
;
Register
ExtReg
;
unsigned
PhysRegSize
=
MRI
.
getTargetRegisterInfo
(
)
->
getRegSizeInBits
(
PhysReg
,
MRI
)
;
unsigned
ValSize
=
VA
.
getValVT
(
)
.
getSizeInBits
(
)
;
unsigned
LocSize
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
if
(
PhysRegSize
>
ValSize
&&
LocSize
==
ValSize
)
{
assert
(
(
PhysRegSize
==
128
||
PhysRegSize
==
80
)
&&
"We expect that to be 128 bit"
)
;
ExtReg
=
MIRBuilder
.
buildAnyExt
(
LLT
::
scalar
(
PhysRegSize
)
,
ValVReg
)
.
getReg
(
0
)
;
}
else
ExtReg
=
extendRegister
(
ValVReg
,
VA
)
;
MIRBuilder
.
buildCopy
(
PhysReg
,
ExtReg
)
;
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static bool is_microcoded_insn ( rtx insn ) { if ( ! insn || ! INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_LOAD_EXT_U || type == TYPE_LOAD_EXT_UX || type == TYPE_LOAD_UX || type == TYPE_STORE_UX || type == TYPE_MFCR ) return true ; } return false ; } </s>

The function returns a true if INSN is microcoded . Return false otherwise .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool PPCLoopDataPrefetch :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static void loongarch_extend_comparands ( rtx_code code , rtx * op0 , rtx * op1 ) { if ( GET_MODE_SIZE ( word_mode ) > GET_MODE_SIZE ( GET_MODE ( * op0 ) ) ) { if ( unsigned_condition ( code ) == code && GET_MODE ( * op0 ) == QImode ) { * op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ; if ( CONST_INT_P ( * op1 ) ) * op1 = GEN_INT ( ( uint8_t ) INTVAL ( * op1 ) ) ; else * op1 = gen_rtx_ZERO_EXTEND ( word_mode , * op1 ) ; } else { * op0 = gen_rtx_SIGN_EXTEND ( word_mode , * op0 ) ; if ( * op1 != const0_rtx ) * op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ; } } } </s>

Sign- or zero-extend OP0 and OP1 for integer comparisons .


<s> static rtx altivec_expand_lxvr_builtin ( enum insn_code icode , tree exp , rtx target , bool blk , bool sign_extend ) { rtx pat , addr ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode smode = insn_data [ icode ] . operand [ 1 ] . mode ; machine_mode mode0 = Pmode ; machine_mode mode1 = Pmode ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; if ( icode == CODE_FOR_nothing ) return 0 ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( op0 == const0_rtx ) addr = gen_rtx_MEM ( blk ? BLKmode : tmode , op1 ) ; else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( blk ? BLKmode : smode , gen_rtx_PLUS ( Pmode , op1 , op0 ) ) ; } if ( sign_extend ) { rtx discratch = gen_reg_rtx ( DImode ) ; rtx tiscratch = gen_reg_rtx ( TImode ) ; pat = GEN_FCN ( icode ) ( tiscratch , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; rtx scratch = gen_lowpart ( smode , tiscratch ) ; if ( icode == CODE_FOR_vsx_lxvrbx ) emit_insn ( gen_extendqidi2 ( discratch , scratch ) ) ; else if ( icode == CODE_FOR_vsx_lxvrhx ) emit_insn ( gen_extendhidi2 ( discratch , scratch ) ) ; else if ( icode == CODE_FOR_vsx_lxvrwx ) emit_insn ( gen_extendsidi2 ( discratch , scratch ) ) ; if ( icode == CODE_FOR_vsx_lxvrdx ) discratch = scratch ; emit_insn ( gen_extendditi2 ( target , discratch ) ) ; return target ; } else { pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } return 0 ; } </s>

For the load and sign extend rightmost elements ; load and zero extend rightmost element builtins .


<s> static bool ix86_tieable_integer_mode_p ( machine_mode mode ) { switch ( mode ) { case E_HImode : case E_SImode : return true ; case E_QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case E_DImode : return TARGET_64BIT ; default : return false ; } } </s>

A subroutine of ix86_modes_tieable_p . Return true if MODE is a tieable integer mode .


<s> unsigned VEAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { VEOperand & Op = ( VEOperand & ) GOp ; switch ( Kind ) { default : break ; case MCK_F32 : if ( Op . isReg ( ) && VEOperand :: MorphToF32Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_I32 : if ( Op . isReg ( ) && VEOperand :: MorphToI32Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_F128 : if ( Op . isReg ( ) && VEOperand :: MorphToF128Reg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_MISC : if ( Op . isImm ( ) && VEOperand :: MorphToMISCReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ! getARMSubtarget ( ) . isTargetNaCl ( ) && TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> static void mips_expand_vi_broadcast ( machine_mode vmode , rtx target , rtx elt ) { struct expand_vec_perm_d d ; rtx t1 ; bool ok ; if ( elt != const0_rtx ) elt = force_reg ( GET_MODE_INNER ( vmode ) , elt ) ; if ( REG_P ( elt ) ) elt = gen_lowpart ( DImode , elt ) ; t1 = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case E_V8QImode : emit_insn ( gen_loongson_vec_init1_v8qi ( t1 , elt ) ) ; break ; case E_V4HImode : emit_insn ( gen_loongson_vec_init1_v4hi ( t1 , elt ) ) ; break ; default : gcc_unreachable ( ) ; } memset ( & d , 0 , sizeof ( d ) ) ; d . target = target ; d . op0 = t1 ; d . op1 = t1 ; d . vmode = vmode ; d . nelt = GET_MODE_NUNITS ( vmode ) ; d . one_vector_p = true ; ok = mips_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( ok ) ; } </s>

A subroutine of mips_expand_vec_init , expand via broadcast .


<s> void MipsAsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; O << "\t.frame\t" << '$' << LowercaseString ( getRegisterName ( stackReg ) ) << ',' << stackSize << ',' << '$' << LowercaseString ( getRegisterName ( returnReg ) ) << '\n' ; } </s>


<s> static unsigned getIntrinsicID ( const SDNode * N ) { unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { default : return Intrinsic :: not_intrinsic ; case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; if ( IID < Intrinsic :: num_intrinsics ) return IID ; return Intrinsic :: not_intrinsic ; } } } </s>

Return the target intrinsic ID of a function , or 0 .


runOnMachineFunction - Emit the function body .


<s> void ARMHazardRecognizer :: AdvanceCycle ( ) { if ( FpMLxStalls && -- FpMLxStalls == 0 ) LastMI = nullptr ; ScoreboardHazardRecognizer :: AdvanceCycle ( ) ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { const Value * Ptr = LI -> getPointerOperand ( ) ; X86AddressMode AM ; if ( ! X86SelectAddress ( Ptr , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , LI -> getAlign ( ) , true ) ; if ( ! Result ) return false ; unsigned OperandNo = 0 ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ; unsigned IndexReg = constrainOperandRegClass ( Result -> getDesc ( ) , MO . getReg ( ) , OperandNo ) ; if ( IndexReg == MO . getReg ( ) ) continue ; MO . setReg ( IndexReg ) ; } Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; Result -> cloneInstrSymbols ( * FuncInfo . MF , * MI ) ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> MVT X86TargetLowering :: getPreferredSwitchConditionType ( LLVMContext & Context , EVT ConditionVT ) const { if ( ConditionVT . getSizeInBits ( ) < 32 ) return MVT :: i32 ; return TargetLoweringBase :: getPreferredSwitchConditionType ( Context , ConditionVT ) ; } </s>

Returns preferred type for switch condition .


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( Type * Ty ) const { const TargetMachine & TM = getTargetMachine ( ) ; if ( TM . getSubtarget < PPCSubtarget > ( ) . isDarwin ( ) ) return 4 ; return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget . isAIXABI ( ) ) return LowerFormalArguments_AIX ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; if ( Subtarget . is64BitELFABI ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; assert ( Subtarget . is32BitELFABI ( ) ) ; return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Stack Tagging"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx mips_function_value_1 ( const_tree valtype , const_tree fn_decl_or_type , machine_mode mode ) { if ( valtype ) { tree fields [ 2 ] ; int unsigned_p ; const_tree func ; if ( fn_decl_or_type && DECL_P ( fn_decl_or_type ) ) func = fn_decl_or_type ; else func = NULL ; mode = TYPE_MODE ( valtype ) ; unsigned_p = TYPE_UNSIGNED ( valtype ) ; mode = promote_function_mode ( valtype , mode , & unsigned_p , func , 1 ) ; switch ( mips_fpr_return_fields ( valtype , fields ) ) { case 1 : return mips_return_fpr_single ( mode , TYPE_MODE ( TREE_TYPE ( fields [ 0 ] ) ) ) ; case 2 : return mips_return_fpr_pair ( mode , TYPE_MODE ( TREE_TYPE ( fields [ 0 ] ) ) , int_byte_position ( fields [ 0 ] ) , TYPE_MODE ( TREE_TYPE ( fields [ 1 ] ) ) , int_byte_position ( fields [ 1 ] ) ) ; } if ( mips_return_in_msb ( valtype ) ) { HOST_WIDE_INT size = int_size_in_bytes ( valtype ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } if ( mips_abi != ABI_EABI && ! FLOAT_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , GP_RETURN ) ; } if ( ! TARGET_MIPS16 ) { if ( mode == TFmode ) return mips_return_fpr_pair ( mode , DImode , 0 , DImode , GET_MODE_SIZE ( mode ) / 2 ) ; if ( mips_return_mode_in_fpr_p ( mode ) ) { if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) return mips_return_fpr_pair ( mode , GET_MODE_INNER ( mode ) , 0 , GET_MODE_INNER ( mode ) , GET_MODE_SIZE ( mode ) / 2 ) ; else return gen_rtx_REG ( mode , FP_RETURN ) ; } } return gen_rtx_REG ( mode , GP_RETURN ) ; } </s>

Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .


"Basic block should contain at least a RET but is empty"


<s> void DLXFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const DLXRegisterInfo * LRI = STI . getRegisterInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; unsigned StackAlign = LRI -> needsStackRealignment ( MF ) ? MFI . getMaxAlignment ( ) : getStackAlignment ( ) ; unsigned MaxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; if ( MFI . hasVarSizedObjects ( ) ) MaxCallFrameSize = alignTo ( MaxCallFrameSize , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI . adjustsStack ( ) ) ) FrameSize += MaxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> int sparc_split_reg_reg_legitimate ( rtx reg1 , rtx reg2 ) { gcc_assert ( reload_completed ) ; if ( GET_CODE ( reg1 ) == SUBREG ) reg1 = SUBREG_REG ( reg1 ) ; if ( GET_CODE ( reg1 ) != REG ) return 0 ; const int regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return 0 ; const int regno2 = REGNO ( reg2 ) ; if ( SPARC_INT_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) return 1 ; if ( TARGET_VIS3 ) { if ( ( SPARC_INT_REG_P ( regno1 ) && SPARC_FP_REG_P ( regno2 ) ) || ( SPARC_FP_REG_P ( regno1 ) && SPARC_INT_REG_P ( regno2 ) ) ) return 1 ; } return 0 ; } </s>

Like sparc_split_reg_mem_legitimate but for REG < -- > REG moves .


<s> Function * X86TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { return M . getFunction ( "__security_check_cookie" ) ; } return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


<s> const X86InstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> unsigned ARMFastISel :: fastEmitInst_rri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , unsigned Op1 , bool Op1IsKill , uint64_t Imm ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; Op1 = constrainOperandRegClass ( II , Op1 , 2 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addReg ( Op1 , Op1IsKill * RegState :: Kill ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with two register operands , an immediate , and a result register in the given register class .


<s> rtx ix86_zero_extend_to_Pmode ( rtx exp ) { return force_reg ( Pmode , convert_to_mode ( Pmode , exp , 1 ) ) ; } </s>

Zero extend possibly SImode EXP to Pmode register .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> void ARMBaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr * Orig , const TargetRegisterInfo & TRI ) const { unsigned Opcode = Orig -> getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> substituteRegister ( Orig -> getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig -> getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , Orig -> getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) ; MIB -> setMemRefs ( Orig -> memoperands_begin ( ) , Orig -> memoperands_end ( ) ) ; break ; } } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility "

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> static tree pa_d_handle_target_float_abi ( void ) { const char * abi ; if ( TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT ) abi = "soft" ; else abi = "hard" ; return build_string_literal ( strlen ( abi ) + 1 , abi ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` floatAbi '' ) ' .


<s> static bool sparc_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { if ( ! TARGET_VIS2 ) return false ; if ( ! target ) return true ; if ( vmode != V8QImode ) return false ; rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; op1 = force_reg ( vmode , op1 ) ; unsigned int i , mask ; for ( i = mask = 0 ; i < 8 ; ++ i ) mask |= ( sel [ i ] & 0xf ) << ( 28 - i * 4 ) ; rtx mask_rtx = force_reg ( SImode , gen_int_mode ( mask , SImode ) ) ; emit_insn ( gen_bmasksi_vis ( gen_reg_rtx ( SImode ) , mask_rtx , const0_rtx ) ) ; emit_insn ( gen_bshufflev8qi_vis ( target , op0 , op1 ) ) ; return true ; } </s>


<s> MCSection * X86WindowsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( Kind . isMergeableConst ( ) && C ) { const unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; std :: string COMDATSymName ; if ( Kind . isMergeableConst4 ( ) || Kind . isMergeableConst8 ( ) ) COMDATSymName = "__real@" + scalarConstantToHexString ( C ) ; else if ( Kind . isMergeableConst16 ( ) ) COMDATSymName = "__xmm@" + scalarConstantToHexString ( C ) ; if ( ! COMDATSymName . empty ( ) ) return getContext ( ) . getCOFFSection ( ".rdata" , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } return TargetLoweringObjectFile :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static rtx push ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode , rn ) ) ; x = frame_insn ( x ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; return x ; } </s>

Output RTL to push register RN onto the stack .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( EH_SJLJ_LONGJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETJMP ) TARGET_NODE_CASE ( EH_SJLJ_SETUP_DISPATCH ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( TS1AM ) TARGET_NODE_CASE ( VEC_UNPACK_LO ) TARGET_NODE_CASE ( VEC_UNPACK_HI ) TARGET_NODE_CASE ( VEC_PACK ) TARGET_NODE_CASE ( VEC_BROADCAST ) TARGET_NODE_CASE ( REPL_I32 ) TARGET_NODE_CASE ( REPL_F32 ) TARGET_NODE_CASE ( LEGALAVL ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER VE VE VE VE


<s> unsigned X86RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ; } </s>


<s>
static
void
symbian_add_attribute
(
tree
node
,
const
char
*
attr_name
)
{
tree
attrs
;
tree
attr
;
attrs
=
DECL_P
(
node
)
DECL_ATTRIBUTES
(
node
)
:
TYPE_ATTRIBUTES
(
node
)
;
if
(
lookup_attribute
(
attr_name
,
attrs
)
!=
NULL_TREE
)
return
;
attr
=
get_identifier
(
attr_name
)
;
if
(
DECL_P
(
node
)
)
DECL_ATTRIBUTES
(
node
)
=
tree_cons
(
attr
,
NULL_TREE
,
attrs
)
;
else
TYPE_ATTRIBUTES
(
node
)
=
tree_cons
(
attr
,
NULL_TREE
,
attrs
)
;
fprintf
(
stderr
,
"propogate %s attribute"
,
attr_name
)
;
print_node_brief
(
stderr
,
" to"
,
node
,
0
)
;
fprintf
(
stderr
,
"\n"
)
;
}
</s>

Add the named attribute to the given node . Copes with both DECLs and TYPEs . Will only add the attribute if it is not already present .

sh
"propogate %s attribute"
" to"
0
"\n"


<s> bool SystemZTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( Imm . isZero ( ) || Imm . isNegZero ( ) ) return true ; return SystemZVectorConstantInfo ( Imm ) . isVectorConstantLegal ( Subtarget ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
static
bool
arm_rtx_costs
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
outer_code
,
int
opno
ATTRIBUTE_UNUSED
,
int
*
total
,
bool
speed
)
{
bool
result
;
int
code
=
GET_CODE
(
x
)
;
gcc_assert
(
current_tune
->
insn_extra_cost
)
;
result
=
arm_rtx_costs_internal
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
current_tune
->
insn_extra_cost
,
total
,
speed
)
;
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
total
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

arm
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; TM = & TPC -> getTM < PPCTargetMachine > ( ) ; STI = TM -> getSubtargetImpl ( F ) ; TLI = STI -> getTargetLowering ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; SchedModel . init ( STI ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> rtx sfunc_uses_reg ( rtx_insn * insn ) { int i ; rtx pattern , part , reg_part , reg ; if ( ! NONJUMP_INSN_P ( insn ) ) return NULL_RTX ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) return NULL_RTX ; for ( reg_part = NULL_RTX , i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , 0 ) ) == SImode ) reg_part = part ; } if ( ! reg_part ) return NULL_RTX ; reg = XEXP ( reg_part , 0 ) ; for ( int i = XVECLEN ( pattern , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( pattern , 0 , i ) ; if ( part == reg_part || GET_CODE ( part ) == CLOBBER ) continue ; if ( reg_mentioned_p ( reg , ( ( GET_CODE ( part ) == SET && REG_P ( SET_DEST ( part ) ) ) ? SET_SRC ( part ) : part ) ) ) return NULL_RTX ; } return reg ; } </s>

If the instruction INSN is implemented by a special function , and we can positively find the register that is used to call the sfunc , and this register is not used anywhere else in this instruction - except as the destination of a set , return this register ; else , return 0 .


"insertBranch must not be told to insert a fallthrough"

"ARM branch conditions have two or three components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMVEVPTOptimisationsPass ( ) ) ; addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Mips
::
NumTargetFixupKinds
]
=
{
{
"fixup_Mips_16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_REL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_26"
,
0
,
26
,
0
}
,
{
"fixup_Mips_HI16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LO16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_LITERAL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Global"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOT_Local"
,
0
,
16
,
0
}
,
{
"fixup_Mips_PC16"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_Mips_CALL16"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GPREL32"
,
0
,
32
,
0
}
,
{
"fixup_Mips_SHIFT5"
,
6
,
5
,
0
}
,
{
"fixup_Mips_SHIFT6"
,
6
,
5
,
0
}
,
{
"fixup_Mips_64"
,
0
,
64
,
0
}
,
{
"fixup_Mips_TLSGD"
,
0
,
16
,
0
}
,
{
"fixup_Mips_GOTTPREL"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_TLSLDM"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_HI"
,
0
,
16
,
0
}
,
{
"fixup_Mips_DTPREL_LO"
,
0
,
16
,
0
}
,
{
"fixup_Mips_Branch_PCRel"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( AArch64 :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"too large function value type, needs %d registers,\ have only %d registers for this"


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static bool nonindexed_address_p ( rtx x , bool strict ) { rtx xfoo0 ; if ( REG_P ( x ) ) { if ( ! reload_in_progress || reg_equiv_mem ( REGNO ( x ) ) == 0 || indirectable_address_p ( reg_equiv_mem ( REGNO ( x ) ) , strict , false ) ) return true ; } if ( indirectable_constant_address_p ( x , false ) ) return true ; if ( indirectable_address_p ( x , strict , false ) ) return true ; xfoo0 = XEXP ( x , 0 ) ; if ( MEM_P ( x ) && indirectable_address_p ( xfoo0 , strict , true ) ) return true ; if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC ) && BASE_REGISTER_P ( xfoo0 , strict ) ) return true ; return false ; } </s>

Return 1 if x is a valid address not using indexing . ( This much is the easy part . )


<s>
void
ARMCallLowering
::
splitToValueTypes
(
const
ArgInfo
&
OrigArg
,
SmallVectorImpl
<
ArgInfo
>
&
SplitArgs
,
const
DataLayout
&
DL
,
MachineRegisterInfo
&
MRI
)
const
{
const
ARMTargetLowering
&
TLI
=
*
getTLI
<
ARMTargetLowering
>
(
)
;
LLVMContext
&
Ctx
=
OrigArg
.
Ty
->
getContext
(
)
;
SmallVector
<
EVT
,
4
>
SplitVTs
;
SmallVector
<
uint64_t
,
4
>
Offsets
;
ComputeValueVTs
(
TLI
,
DL
,
OrigArg
.
Ty
,
SplitVTs
,
&
Offsets
,
0
)
;
assert
(
SplitVTs
.
size
(
)
==
1
&&
"Unsupported type"
)
;
SplitArgs
.
emplace_back
(
OrigArg
.
Reg
,
SplitVTs
[
0
]
.
getTypeForEVT
(
Ctx
)
,
OrigArg
.
Flags
,
OrigArg
.
IsFixed
)
;
}
</s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> void rs6000_xcoff_asm_globalize_decl_name ( FILE * stream , tree decl ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , 0 ) , 0 ) ; fputs ( GLOBAL_ASM_OP , stream ) ; assemble_name ( stream , name ) ; fputs ( rs6000_xcoff_visibility ( decl ) , stream ) ; putc ( '\n' , stream ) ; } </s>

Output assembly language to globalize a symbol from a DECL , possibly with visibility .


<s> static void add_pop_cfi_notes ( rtx_insn * insn , unsigned int high , unsigned int low ) { rtx t = plus_constant ( Pmode , stack_pointer_rtx , ( high - low + 1 ) * UNITS_PER_WORD ) ; t = gen_rtx_SET ( stack_pointer_rtx , t ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , t ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( unsigned int i = low ; i <= high ; i ++ ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( word_mode , i ) ) ; } </s>


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11L ) ; Reserved . set ( SystemZ :: R11H ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15L ) ; Reserved . set ( SystemZ :: R15H ) ; Reserved . set ( SystemZ :: R14Q ) ; Reserved . set ( SystemZ :: A0 ) ; Reserved . set ( SystemZ :: A1 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void loongarch_rewrite_small_data_1 ( rtx * loc ) { subrtx_ptr_iterator :: array_type array ; FOR_EACH_SUBRTX_PTR ( iter , array , loc , ALL ) { rtx * loc = * iter ; if ( MEM_P ( * loc ) ) { loongarch_rewrite_small_data_1 ( & XEXP ( * loc , 0 ) ) ; iter . skip_subrtxes ( ) ; } } } </s>

Rewrite * LOC so that it refers to small data using explicit relocations .


<s> static int ix86_mode_after ( int entity , int mode , rtx_insn * insn ) { switch ( entity ) { case AVX_U128 : return ix86_avx_u128_mode_after ( mode , insn ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return mode ; default : gcc_unreachable ( ) ; } } </s>

Return the mode that an insn results in .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
StackOffset
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
hasStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
if
(
!
IgnoreSPUpdates
&&
!
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> BitVector LC3bRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedLC3bRegs [ ] = { LC3b :: R6 , LC3b :: R7 , LC3b :: PC , LC3b :: PSR , LC3b :: IR } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedLC3bRegs ) ; ++ I ) { Reserved . set ( ReservedLC3bRegs [ I ] ) ; } return Reserved ; } </s>


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
Orig
.
modifiesRegister
(
X86
::
EFLAGS
,
&
TRI
)
;
if
(
ClobbersEFLAGS
&&
MBB
.
computeRegisterLiveness
(
&
TRI
,
X86
::
EFLAGS
,
I
)
!=
MachineBasicBlock
::
LQR_Dead
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
add
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> static bool rs6000_optab_supported_p ( int op , machine_mode mode1 , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return ( opt_type == OPTIMIZE_FOR_SPEED && RS6000_RECIP_AUTO_RSQRTE_P ( mode1 ) ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> bool X86TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s>
MCSymbol
*
KudeyarMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

Kudeyar
Kudeyar
"Unknown target flag on GV operand"
0


Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST . Like the default implementation , but returns a lower bound .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; if ( EnableDelJmp ) { MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ; if ( FJ == F . end ( ) ) return Changed ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FJ != FE ; ++ FI , ++ FJ ) Changed |= runOnMachineBasicBlock ( * FI , * FJ ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCLoopPreIncPrepPass ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createHardwareLoopsPass ( ) ) ; return false ; } </s>


<s> static bool mips_cfg_in_reorg ( void ) { return ( mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE || TARGET_RELAX_PIC_CALLS ) ; } </s>

Return whether CFG is used in mips_reorg .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt ) ) return false ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


"ARM64 pseudo instruction expansion pass"

getPassName - Return a nice clean name for a pass .


<s> void F2003fInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( F2003f :: KRZrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx set_dest ; rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fuseable_ops & ARM_FUSE_MOVW_MOVT ) { set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , 0 ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , 0 ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


"stack frame not a multiple of octabyte: %wd"

Expands the function epilogue into RTX .


<s> static void mips_sim_finish_insn ( struct mips_sim * state , rtx insn ) { if ( JUMP_P ( insn ) ) mips_sim_issue_nop ( state ) ; switch ( GET_CODE ( SEQ_BEGIN ( insn ) ) ) { case CODE_LABEL : case CALL_INSN : mips_sim_reset ( state ) ; break ; case JUMP_INSN : if ( INSN_ANNULLED_BRANCH_P ( SEQ_BEGIN ( insn ) ) ) mips_sim_reset ( state ) ; break ; default : break ; } } </s>

Update simulation state STATE so that it 's ready to accept the instruction after INSN . INSN should be part of the main rtl chain , not a member of a SEQUENCE .


<s> const std :: string & MipsLA25Stub :: name ( ) const { return m_Name ; } </s>

Gets the name of the pass we are mixed into .


<s> bool AArch64RegisterInfo :: requiresVirtualBaseRegisters ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access .


<s> static bool or1k_pass_by_reference ( cumulative_args_t , machine_mode mode , const_tree type , bool ) { HOST_WIDE_INT size ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return true ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; return size < 0 || size > 8 ; } </s>

Worker for TARGET_PASS_BY_REFERENCE . Returns true if an argument of TYPE in MODE should be passed by reference as required by the OpenRISC ABI . On OpenRISC structures , unions and arguments larger than 64-bits are passed by reference .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static bool alg_usable_p ( enum stringop_alg alg , bool memset , bool have_as ) { if ( alg == no_stringop ) return false ; if ( alg == vector_loop ) return TARGET_SSE || TARGET_AVX ; if ( alg == rep_prefix_1_byte || alg == rep_prefix_4_byte || alg == rep_prefix_8_byte ) { if ( have_as ) return false ; if ( fixed_regs [ CX_REG ] || fixed_regs [ DI_REG ] || ( memset ? fixed_regs [ AX_REG ] : fixed_regs [ SI_REG ] ) ) return false ; } return true ; } </s>

Return true if ALG can be used in current context . Assume we expand memset if MEMSET is true .


<s> bool mips_unsigned_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = 0 ) { return ( x & ( ( 1 << shift ) - 1 ) ) == 0 && x < ( ( unsigned ) 1 << ( shift + bits ) ) ; } </s>

Return true if X fits within an unsigned field of BITS bits that is shifted left SHIFT bits before being used .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s>
Register
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
IsDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
LLT
::
scalar
(
64
)
;
if
(
!
is64Bit
&&
VT
!=
LLT
::
scalar
(
32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
(
IsDarwinABI
||
isPPC64
)
Register
(
)
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
IsDarwinABI
)
Register
(
)
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
void
setReg
(
unsigned
Reg
)
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
Base
.
Reg
=
Reg
;
}
</s>

Assigns the associated register for this edge .


<s> int leaf_return_peephole_ok ( ) { return ( actual_fsize == 0 ) ; } </s>

Return nonzero if a return peephole merging return with setting of output register is ok .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> SDValue X86TargetLowering :: expandIndirectJTBranch ( const SDLoc & dl , SDValue Value , SDValue Addr , SelectionDAG & DAG ) const { const Module * M = DAG . getMachineFunction ( ) . getMMI ( ) . getModule ( ) ; Metadata * IsCFProtectionSupported = M -> getModuleFlag ( "cf-protection-branch" ) ; if ( IsCFProtectionSupported ) { return DAG . getNode ( X86ISD :: NT_BRIND , dl , MVT :: Other , Value , Addr ) ; } return TargetLowering :: expandIndirectJTBranch ( dl , Value , Addr , DAG ) ; } </s>

Expands target specific indirect branch for the case of JumpTable expansion .


<s> void ix86_fixup_binary_operands_no_copy ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { rtx dst = ix86_fixup_binary_operands ( code , mode , operands ) ; gcc_assert ( dst == operands [ 0 ] ) ; } </s>

Similarly , but assume that the destination has already been set up properly .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 4095 , OnlyOptimizeForSize ) ) ; } return false ; } </s>


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( 1u << Bits ) - 1 ) ) Bits = CountTrailingZeros_32 ( Size ) ; return Bits ; } </s>

Compute the number of known offset bits internally to this block .


<s>
MCFragment
*
AArch64AuthMCExpr
::
findAssociatedFragment
(
)
const
{
llvm_unreachable
(
"FIXME: what goes here?"
)
;
}
</s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool XNCMPassConfig :: addInstSelector ( ) { PM . add ( createXNCMISelDag ( getXNCMTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool SystemZInstrInfo :: isPredicable ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: Return_XPLINK || Opcode == SystemZ :: Trap || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::Return_XPLINK SystemZ::Trap SystemZ::CallJG SystemZ::CallBR


<s> static void aarch64_expand_builtin_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { const CUMULATIVE_ARGS * cum ; tree f_stack , f_grtop , f_vrtop , f_groff , f_vroff ; tree stack , grtop , vrtop , groff , vroff ; tree t ; int gr_save_area_size ; int vr_save_area_size ; int vr_offset ; cum = & crtl -> args . info ; gr_save_area_size = ( NUM_ARG_REGS - cum -> aapcs_ncrn ) * UNITS_PER_WORD ; vr_save_area_size = ( NUM_FP_ARG_REGS - cum -> aapcs_nvrn ) * UNITS_PER_VREG ; if ( ! TARGET_FLOAT ) { gcc_assert ( cum -> aapcs_nvrn == 0 ) ; vr_save_area_size = 0 ; } f_stack = TYPE_FIELDS ( va_list_type_node ) ; f_grtop = DECL_CHAIN ( f_stack ) ; f_vrtop = DECL_CHAIN ( f_grtop ) ; f_groff = DECL_CHAIN ( f_vrtop ) ; f_vroff = DECL_CHAIN ( f_groff ) ; stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_stack ) , valist , f_stack , NULL_TREE ) ; grtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_grtop ) , valist , f_grtop , NULL_TREE ) ; vrtop = build3 ( COMPONENT_REF , TREE_TYPE ( f_vrtop ) , valist , f_vrtop , NULL_TREE ) ; groff = build3 ( COMPONENT_REF , TREE_TYPE ( f_groff ) , valist , f_groff , NULL_TREE ) ; vroff = build3 ( COMPONENT_REF , TREE_TYPE ( f_vroff ) , valist , f_vroff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( stack ) , virtual_incoming_args_rtx ) ; if ( cum -> aapcs_stack_size > 0 ) t = fold_build_pointer_plus_hwi ( t , cum -> aapcs_stack_size * UNITS_PER_WORD ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( stack ) , stack , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( grtop ) , virtual_incoming_args_rtx ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( grtop ) , grtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( vrtop ) , virtual_incoming_args_rtx ) ; vr_offset = ROUND_UP ( gr_save_area_size , STACK_BOUNDARY / BITS_PER_UNIT ) ; if ( vr_offset ) t = fold_build_pointer_plus_hwi ( t , - vr_offset ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vrtop ) , vrtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( groff ) , groff , build_int_cst ( TREE_TYPE ( groff ) , - gr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( vroff ) , vroff , build_int_cst ( TREE_TYPE ( vroff ) , - vr_save_area_size ) ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>


"%qE attribute not available to functions with arguments "

"%qE attribute not available to functions with variable number "

"%qE attribute not available to functions that return value on "

This function returns true if a function with declaration FNDECL and type FNTYPE uses the stack to pass arguments or return variables and false otherwise . This is used for functions with the attributes 'cmse_nonsecure_call ' or 'cmse_nonsecure_entry ' and this function will issue diagnostic messages if the stack is used . NAME is the name of the attribute used .


<s> void PPCVSXSwapRemoval :: initialize ( MachineFunction & MFParm ) { MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; TII = static_cast < const PPCInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; const int InitialVectorSize ( 256 ) ; SwapVector . clear ( ) ; SwapVector . reserve ( InitialVectorSize ) ; EC = new EquivalenceClasses < int > ; } </s>

Initialize the strategy after building the DAG for a new region .


<s>
void
mmix_trampoline_template
(
FILE
*
stream
)
{
fprintf
(
stream
,
"\tGETA $255,1F\n\t"
)
;
fprintf
(
stream
,
"LDOU %s,$255,0\n\t"
,
reg_names
[
MMIX_STATIC_CHAIN_REGNUM
]
)
;
fprintf
(
stream
,
"LDOU $255,$255,8\n\t"
)
;
fprintf
(
stream
,
"GO $255,$255,0\n"
)
;
fprintf
(
stream
,
"1H\tOCTA 0\n\t"
)
;
fprintf
(
stream
,
"OCTA 0\n"
)
;
}
</s>


<s> static rtx_insn * nds32_md_asm_adjust ( vec < rtx > & outputs ATTRIBUTE_UNUSED , vec < rtx > & inputs ATTRIBUTE_UNUSED , vec < machine_mode > & input_modes ATTRIBUTE_UNUSED , vec < const char * > & constraints ATTRIBUTE_UNUSED , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { if ( ! flag_inline_asm_r15 ) { clobbers . safe_push ( gen_rtx_REG ( SImode , TA_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , TA_REGNUM ) ; } return NULL ; } </s>


<s>
const
char
*
output_probe_stack_range
(
rtx
reg1
,
rtx
reg2
)
{
static
int
labelno
=
0
;
char
loop_lab
[
32
]
;
rtx
xops
[
2
]
;
ASM_GENERATE_INTERNAL_LABEL
(
loop_lab
,
"LPSRL"
,
labelno
++
)
;
ASM_OUTPUT_INTERNAL_LABEL
(
asm_out_file
,
loop_lab
)
;
xops
[
0
]
=
reg1
;
xops
[
1
]
=
GEN_INT
(
PROBE_INTERVAL
)
;
output_asm_insn
(
"add\t%0, %1, %0"
,
xops
)
;
xops
[
1
]
=
reg2
;
output_asm_insn
(
"cmp\t%0, %1"
,
xops
)
;
if
(
TARGET_ARCH64
)
fputs
(
"\tbne,pt\t%xcc,"
,
asm_out_file
)
;
else
fputs
(
"\tbne\t"
,
asm_out_file
)
;
assemble_name_raw
(
asm_out_file
,
loop_lab
)
;
fputc
(
'\n'
,
asm_out_file
)
;
xops
[
1
]
=
GEN_INT
(
SPARC_STACK_BIAS
)
;
output_asm_insn
(
" st\t%%g0, [%0+%1]"
,
xops
)
;
return
""
;
}
</s>

Wrapper around the output_probe_stack_range routines .


<s> static const char * aarch64_get_multilib_abi_name ( void ) { if ( TARGET_BIG_END ) return TARGET_ILP32 ? "aarch64_be_ilp32" : "aarch64_be" ; return TARGET_ILP32 ? "aarch64_ilp32" : "aarch64" ; } </s>


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool MipsOptimizePICCall :: runOnMachineFunction ( MachineFunction & F ) { if ( static_cast < const MipsSubtarget & > ( F . getSubtarget ( ) ) . inMips16Mode ( ) ) return false ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; bool Changed = false ; SmallVector < MBBInfo , 8 > WorkList ( 1 , MBBInfo ( MDT -> getRootNode ( ) ) ) ; while ( ! WorkList . empty ( ) ) { MBBInfo & MBBI = WorkList . back ( ) ; if ( MBBI . isVisited ( ) ) { MBBI . postVisit ( ) ; WorkList . pop_back ( ) ; continue ; } MBBI . preVisit ( ScopedHT ) ; Changed |= visitNode ( MBBI ) ; const MachineDomTreeNode * Node = MBBI . getNode ( ) ; WorkList . append ( Node -> begin ( ) , Node -> end ( ) ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool pru_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { switch ( GET_MODE_SIZE ( mode ) ) { case 1 : return true ; case 2 : return ( regno % 4 ) <= 2 ; case 4 : return ( regno % 4 ) == 0 ; case 8 : return ( regno % 4 ) == 0 ; case 16 : return ( regno % 4 ) == 0 ; case 32 : return ( regno % 4 ) == 0 ; default : gcc_assert ( mode == BLKmode || mode == VOIDmode ) ; return ( regno % 4 ) == 0 ; } } </s>


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "ve" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { unsigned Idx = Endian == support :: little ? i : 3 - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned PPCTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return Subtarget . isPPC64 ( ) ? PPC :: X4 : PPC :: R4 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: X86_64_Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; else return CSR_64_AllRegs_RegMask ; } else { if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; else return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>


<s> static void rs6000_set_default_type_attributes ( tree type ) { if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( "longcall" ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; darwin_set_default_type_attributes ( type ) ; } </s>

Set longcall attributes on all functions declared when rs6000_default_long_calls is true .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . getNumXRegisterReserved ( ) - hasBasePointer ( MF ) - MF . getFunction ( ) . isPagerando ( ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static void predict_jump ( int prob ) { rtx_insn * insn = get_last_insn ( ) ; gcc_assert ( JUMP_P ( insn ) ) ; add_reg_br_prob_note ( insn , profile_probability :: from_reg_br_prob_base ( prob ) ) ; } </s>

Predict just emitted jump instruction to be taken with probability PROB .


<s> bool X86AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < X86Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) . hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; EmitFPOData = false ; return false ; } </s>


<s> tree gimple_folder :: force_vector ( gimple_seq & stmts , tree vectype , tree value ) { if ( ! VECTOR_TYPE_P ( TREE_TYPE ( value ) ) ) value = gimple_build_vector_from_val ( & stmts , vectype , value ) ; return value ; } </s>

VALUE might be a vector of type VECTYPE or a single scalar element . Duplicate it into a vector of type VECTYPE in the latter case , adding any new statements to STMTS .


<s> bool aarch64_offset_7bit_signed_scaled_p ( machine_mode mode , poly_int64 offset ) { HOST_WIDE_INT multiple ; return ( constant_multiple_p ( offset , GET_MODE_SIZE ( mode ) , & multiple ) && IN_RANGE ( multiple , - 64 , 63 ) ) ; } </s>

Return true if OFFSET is a signed 7-bit value multiplied by the size of MODE .


<s> static bool ix86_function_ok_for_sibcall ( tree decl , tree exp ) { tree type , decl_or_type ; rtx a , b ; if ( ! TARGET_MACHO && ! TARGET_64BIT && flag_pic && ( ! decl || ! targetm . binds_local_p ( decl ) ) ) return false ; if ( ix86_minimum_incoming_stack_boundary ( true ) < PREFERRED_STACK_BOUNDARY ) return false ; if ( decl ) { decl_or_type = decl ; type = TREE_TYPE ( decl ) ; } else { type = CALL_EXPR_FN ( exp ) ; type = TREE_TYPE ( type ) ; type = TREE_TYPE ( type ) ; decl_or_type = type ; } a = ix86_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else { if ( ! decl || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P ( decl ) ) ) { if ( ix86_function_regparm ( type , NULL ) >= 3 ) { return false ; } } } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> bool SparcSubtarget :: enableMachineScheduler ( ) const { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> void AArch64TargetStreamer :: finish ( ) { ConstantPools -> emitAll ( Streamer ) ; if ( MarkBTIProperty ) emitNoteSection ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getTargetData ( ) -> getPointerSizeInBits ( ) == 64 ; TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , unsigned StackAlignOverride , bool is64Bit ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( is64Bit ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> llvm :: FastISel * X86 :: createFastISel ( FunctionLoweringInfo & funcInfo ) { return new X86FastISel ( funcInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void ix86_split_copysign_const ( rtx operands [ ] ) { enum machine_mode mode , vmode ; rtx dest , op0 , op1 , mask , x ; dest = operands [ 0 ] ; op0 = operands [ 1 ] ; op1 = operands [ 2 ] ; mask = operands [ 3 ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , 0 ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) { x = gen_rtx_IOR ( vmode , dest , op0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; } } </s>

Deconstruct a copysign operation into bit masks . Operand 0 is known to be a constant , and so has already been expanded into a vector constant .


<s> bool MipsSERegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool mips_eh_uses ( unsigned int regno ) { if ( reload_completed && ! TARGET_ABSOLUTE_JUMPS ) { if ( mips_cfun_has_cprestore_slot_p ( ) ) { if ( regno == CPRESTORE_SLOT_REGNUM ) return true ; } else { if ( cfun -> machine -> global_pointer == regno ) return true ; } } return false ; } </s>


<s> unsigned VEInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: LDSri || MI . getOpcode ( ) == VE :: LDLri || MI . getOpcode ( ) == VE :: LDUri ) { if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { unsigned Reg = MI . getOperand ( OpNum ) . getReg ( ) ; if ( MI . killsRegister ( Reg , TRI ) ) return ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: GR64RegClass . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , X86 :: sub_32bit ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: XOR32rr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: GR32RegClass . contains ( Reg ) ) { BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: XOR32rr ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .