<s> static inline tree def_builtin ( HOST_WIDE_INT mask , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( mask == 0 || ( mask & ix86_isa_flags ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ; ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
case
TYPE_MM32
:
\
case
TYPE_MM
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_MM0
+
index
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
if
(
index
>
8
)
\
*
valid
=
0
;
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; const bool isPPC64 = Subtarget . isPPC64 ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( Subtarget . is32BitELFABI ( ) && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static bool rs6000_maybe_emit_fp_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return 0 ; switch ( code ) { case EQ : case GE : case GT : break ; case NE : case LT : case LE : code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; break ; default : return false ; } compare_rtx = gen_rtx_fmt_ee ( code , CCFPmode , op0 , op1 ) ; cmove_rtx = gen_rtx_SET ( dest , gen_rtx_IF_THEN_ELSE ( result_mode , compare_rtx , true_cond , false_cond ) ) ; clobber_rtx = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( V2DImode ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , cmove_rtx , clobber_rtx ) ) ) ; return true ; } </s>

Possibly emit a floating point conditional move by generating a compare that sets a mask instruction and a XXSEL select instruction . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return false if the operation can not be generated , and true if we could generate the instruction .


<s> static void rs6000_split_v4si_init_di_reg ( rtx dest , rtx si1 , rtx si2 , rtx tmp ) { const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C ( 0xffffffff ) ; if ( CONST_INT_P ( si1 ) && CONST_INT_P ( si2 ) ) { unsigned HOST_WIDE_INT const1 = ( UINTVAL ( si1 ) & mask_32bit ) << 32 ; unsigned HOST_WIDE_INT const2 = UINTVAL ( si2 ) & mask_32bit ; emit_move_insn ( dest , GEN_INT ( const1 | const2 ) ) ; return ; } if ( CONST_INT_P ( si1 ) ) emit_move_insn ( dest , GEN_INT ( ( UINTVAL ( si1 ) & mask_32bit ) << 32 ) ) ; else { rtx si1_di = gen_rtx_REG ( DImode , regno_or_subregno ( si1 ) ) ; rtx shift_rtx = gen_rtx_ASHIFT ( DImode , si1_di , GEN_INT ( 32 ) ) ; rtx mask_rtx = GEN_INT ( mask_32bit << 32 ) ; rtx and_rtx = gen_rtx_AND ( DImode , shift_rtx , mask_rtx ) ; gcc_assert ( ! reg_overlap_mentioned_p ( dest , si1 ) ) ; emit_insn ( gen_rtx_SET ( dest , and_rtx ) ) ; } gcc_assert ( ! reg_overlap_mentioned_p ( dest , tmp ) ) ; if ( CONST_INT_P ( si2 ) ) emit_move_insn ( tmp , GEN_INT ( UINTVAL ( si2 ) & mask_32bit ) ) ; else emit_insn ( gen_zero_extendsidi2 ( tmp , si2 ) ) ; emit_insn ( gen_iordi3 ( dest , dest , tmp ) ) ; return ; } </s>

Helper function for rs6000_split_v4si_init to build up a DImode value from two SImode values .


<s> Align getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> bool PPCInstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool addInstSelector ( ) { addPass ( createLC3bISelDag ( getLC3bTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static inline HOST_WIDE_INT htm_spr_regno ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_REGNO ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_REGNO ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR || code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASR_REGNO ; } </s>

Return the appropriate SPR regno associated with the given builtin .


<s>
bool
SystemZRegisterInfo
::
shouldCoalesce
(
MachineInstr
*
MI
,
const
TargetRegisterClass
*
SrcRC
,
unsigned
SubReg
,
const
TargetRegisterClass
*
DstRC
,
unsigned
DstSubReg
,
const
TargetRegisterClass
*
NewRC
,
LiveIntervals
&
LIS
)
const
{
assert
(
MI
->
isCopy
(
)
&&
"Only expecting COPY instructions"
)
;
if
(
!
(
NewRC
->
hasSuperClassEq
(
&
SystemZ
::
GR128BitRegClass
)
&&
(
getRegSizeInBits
(
*
SrcRC
)
<=
64
||
getRegSizeInBits
(
*
DstRC
)
<=
64
)
)
)
return
true
;
unsigned
WideOpNo
=
(
getRegSizeInBits
(
*
SrcRC
)
==
128
1
:
0
)
;
Register
GR128Reg
=
MI
->
getOperand
(
WideOpNo
)
.
getReg
(
)
;
Register
GRNarReg
=
MI
->
getOperand
(
(
WideOpNo
==
1
)
0
:
1
)
.
getReg
(
)
;
LiveInterval
&
IntGR128
=
LIS
.
getInterval
(
GR128Reg
)
;
LiveInterval
&
IntGRNar
=
LIS
.
getInterval
(
GRNarReg
)
;
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineInstr
*
FirstMI_GR128
=
LIS
.
getInstructionFromIndex
(
IntGR128
.
beginIndex
(
)
)
;
MachineInstr
*
FirstMI_GRNar
=
LIS
.
getInstructionFromIndex
(
IntGRNar
.
beginIndex
(
)
)
;
MachineInstr
*
LastMI_GR128
=
LIS
.
getInstructionFromIndex
(
IntGR128
.
endIndex
(
)
)
;
MachineInstr
*
LastMI_GRNar
=
LIS
.
getInstructionFromIndex
(
IntGRNar
.
endIndex
(
)
)
;
if
(
(
!
FirstMI_GR128
||
FirstMI_GR128
->
getParent
(
)
!=
MBB
)
||
(
!
FirstMI_GRNar
||
FirstMI_GRNar
->
getParent
(
)
!=
MBB
)
||
(
!
LastMI_GR128
||
LastMI_GR128
->
getParent
(
)
!=
MBB
)
||
(
!
LastMI_GRNar
||
LastMI_GRNar
->
getParent
(
)
!=
MBB
)
)
return
false
;
MachineBasicBlock
::
iterator
MII
=
nullptr
,
MEE
=
nullptr
;
if
(
WideOpNo
==
1
)
{
MII
=
FirstMI_GR128
;
MEE
=
LastMI_GRNar
;
}
else
{
MII
=
FirstMI_GRNar
;
MEE
=
LastMI_GR128
;
}
BitVector
PhysClobbered
(
getNumRegs
(
)
)
;
MEE
++
;
for
(
;
MII
!=
MEE
;
++
MII
)
{
for
(
const
MachineOperand
&
MO
:
MII
->
operands
(
)
)
if
(
MO
.
isReg
(
)
&&
Register
::
isPhysicalRegister
(
MO
.
getReg
(
)
)
)
{
for
(
MCSuperRegIterator
SI
(
MO
.
getReg
(
)
,
this
,
true
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
NewRC
->
contains
(
*
SI
)
)
{
PhysClobbered
.
set
(
*
SI
)
;
break
;
}
}
}
unsigned
const
DemandedFreeGR128
=
3
;
if
(
PhysClobbered
.
count
(
)
>
(
NewRC
->
getNumRegs
(
)
DemandedFreeGR128
)
)
return
false
;
return
true
;
}
</s>


<s> static bool rs6000_use_blocks_for_constant_p ( machine_mode mode , const_rtx x ) { return ! ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ; } </s>


<s> rtx or1k_initial_frame_addr ( ) { crtl -> accesses_prior_frames = 1 ; return arg_pointer_rtx ; } </s>

Worker for INITIAL_FRAME_ADDRESS_RTX . Returns the RTX representing the address of the initial stack frame .


<s> static tree ATTRIBUTE_UNUSED rs6000_stack_protect_fail ( void ) { return ( DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic ) ? default_hidden_stack_protect_fail ( ) : default_external_stack_protect_fail ( ) ; } </s>

For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . Otherwise it is better to call __stack_chk_fail directly .


<s> static void ia64_set_sched_context ( void * _sc ) { ia64_sched_context_t sc = ( ia64_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; memcpy ( prev_cycle_state , sc -> prev_cycle_state , dfa_state_size ) ; last_scheduled_insn = sc -> last_scheduled_insn ; memcpy ( rws_sum , sc -> rws_sum , sizeof ( rws_sum ) ) ; memcpy ( rws_insn , sc -> rws_insn , sizeof ( rws_insn ) ) ; first_instruction = sc -> first_instruction ; pending_data_specs = sc -> pending_data_specs ; current_cycle = sc -> current_cycle ; memcpy ( mem_ops_in_group , sc -> mem_ops_in_group , sizeof ( mem_ops_in_group ) ) ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; if ( STI . is64Bit ( ) ) return false ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = X86FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const X86InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned PC ; if ( STI . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & X86 :: GR32RegClass ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: MOVPC32r ) , PC ) . addImm ( 0 ) ; if ( STI . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: ADD32ri ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , X86II :: MO_GOT_ABSOLUTE_ADDRESS ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx rs6000_gen_le_vsx_permute ( rtx source , machine_mode mode ) { if ( FLOAT128_VECTOR_P ( mode ) || mode == TImode ) return gen_rtx_ROTATE ( mode , source , GEN_INT ( 64 ) ) ; else { rtx par = gen_rtx_PARALLEL ( VOIDmode , rs6000_const_vec ( mode ) ) ; return gen_rtx_VEC_SELECT ( mode , source , par ) ; } } </s>

Generate a permute rtx that represents an lxvd2x , stxvd2x , or xxpermdi for a VSX load or store operation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps ( ) ; } delete EC ; return Changed ; } </s>


<s>
static
void
process_cfa_adjust_cfa
(
FILE
*
asm_out_file
,
rtx
pat
,
rtx
insn
,
bool
unwind
,
bool
frame
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
if
(
dest
==
stack_pointer_rtx
)
{
if
(
GET_CODE
(
src
)
==
PLUS
)
{
rtx
op0
=
XEXP
(
src
,
0
)
;
rtx
op1
=
XEXP
(
src
,
1
)
;
gcc_assert
(
op0
==
dest
&&
GET_CODE
(
op1
)
==
CONST_INT
)
;
if
(
INTVAL
(
op1
)
<
0
)
{
gcc_assert
(
!
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
asm_out_file
,
"\t.fframe "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
INTVAL
(
op1
)
)
;
}
else
process_epilogue
(
asm_out_file
,
insn
,
unwind
,
frame
)
;
}
else
{
gcc_assert
(
src
==
hard_frame_pointer_rtx
)
;
process_epilogue
(
asm_out_file
,
insn
,
unwind
,
frame
)
;
}
}
else
if
(
dest
==
hard_frame_pointer_rtx
)
{
gcc_assert
(
src
==
stack_pointer_rtx
)
;
gcc_assert
(
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
asm_out_file
,
"\t.vframe r%d\n"
,
ia64_dbx_register_number
(
REGNO
(
dest
)
)
)
;
}
else
gcc_unreachable
(
)
;
}
</s>

This function processes a SET pattern for REG_CFA_ADJUST_CFA .


<s> static bool mips_return_in_memory ( const_tree type , const_tree fndecl ATTRIBUTE_UNUSED ) { return ( TARGET_OLDABI ? TYPE_MODE ( type ) == BLKmode : ! IN_RANGE ( int_size_in_bytes ( type ) , 0 , 2 * UNITS_PER_WORD ) ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY . Under the old ( i.e. , 32 and O64 ABIs ) all BLKmode objects are returned in memory . Under the new ( N32 and 64-bit MIPS ABIs ) small structures are returned in a register . Objects with varying size must still be returned in memory , of course .


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; case Mips :: SNZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_B ) ; case Mips :: SNZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_H ) ; case Mips :: SNZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_W ) ; case Mips :: SNZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_D ) ; case Mips :: SNZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_V ) ; case Mips :: SZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_B ) ; case Mips :: SZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_H ) ; case Mips :: SZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_W ) ; case Mips :: SZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_D ) ; case Mips :: SZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_V ) ; case Mips :: COPY_FW_PSEUDO : return emitCOPY_FW ( MI , BB ) ; case Mips :: COPY_FD_PSEUDO : return emitCOPY_FD ( MI , BB ) ; case Mips :: INSERT_FW_PSEUDO : return emitINSERT_FW ( MI , BB ) ; case Mips :: INSERT_FD_PSEUDO : return emitINSERT_FD ( MI , BB ) ; case Mips :: INSERT_B_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 1 , false ) ; case Mips :: INSERT_H_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 2 , false ) ; case Mips :: INSERT_W_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , false ) ; case Mips :: INSERT_D_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , false ) ; case Mips :: INSERT_FW_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , true ) ; case Mips :: INSERT_FD_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , true ) ; case Mips :: FILL_FW_PSEUDO : return emitFILL_FW ( MI , BB ) ; case Mips :: FILL_FD_PSEUDO : return emitFILL_FD ( MI , BB ) ; case Mips :: FEXP2_W_1_PSEUDO : return emitFEXP2_W_1 ( MI , BB ) ; case Mips :: FEXP2_D_1_PSEUDO : return emitFEXP2_D_1 ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> int i386_pe_dllimport_name_p ( const char * symbol ) { return ( strncmp ( DLL_IMPORT_PREFIX , symbol , strlen ( DLL_IMPORT_PREFIX ) ) == 0 ) ; } </s>

Return nonzero if SYMBOL is marked as being dllimport 'd .


<s> unsigned getMaxPrefetchIterationsAhead ( ) const override { return MaxPrefetchIterationsAhead ; } </s>

Return the maximum prefetch distance in terms of loop iterations .


<s> static void swap_const_vector_halves ( rtx * op_ptr ) { int i ; rtx op = * op_ptr ; enum rtx_code code = GET_CODE ( op ) ; if ( GET_CODE ( op ) == CONST_VECTOR ) { int units = GET_MODE_NUNITS ( GET_MODE ( op ) ) ; rtx_vector_builder builder ( GET_MODE ( op ) , units , 1 ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i + units / 2 ) ) ; for ( i = 0 ; i < units / 2 ; ++ i ) builder . quick_push ( CONST_VECTOR_ELT ( op , i ) ) ; * op_ptr = builder . build ( ) ; } else { int j ; const char * fmt = GET_RTX_FORMAT ( code ) ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) swap_const_vector_halves ( & XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) swap_const_vector_halves ( & XVECEXP ( op , i , j ) ) ; } } </s>

OP is either a CONST_VECTOR or an expression containing one . Swap the first half of the vector with the second in the first case . Recurse to find it in the second .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , MCSectionELF :: SHT_FINI_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } } </s>

This method must be called before any actual lowering is done .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"MachineFunction required"
)
;
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
callsEHReturn
(
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
MF
->
getInfo
<
X86MachineFunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_64_CXX_TLS_Darwin_PE_SaveList
:
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
X86_RegCall
:
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
return
(
HasSSE
CSR_Win64_RegCall_SaveList
:
CSR_Win64_RegCall_NoSSE_SaveList
)
;
}
else
{
return
(
HasSSE
CSR_SysV64_RegCall_SaveList
:
CSR_SysV64_RegCall_NoSSE_SaveList
)
;
}
}
else
{
return
(
HasSSE
CSR_32_RegCall_SaveList
:
CSR_32_RegCall_NoSSE_SaveList
)
;
}
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX512
)
return
CSR_64_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_64_AllRegs_SaveList
;
return
CSR_64_AllRegs_NoSSE_SaveList
;
}
else
{
if
(
HasAVX512
)
return
CSR_32_AllRegs_AVX512_SaveList
;
if
(
HasAVX
)
return
CSR_32_AllRegs_AVX_SaveList
;
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
{
if
(
!
HasSSE
)
return
CSR_Win64_NoSSE_SaveList
;
return
CSR_Win64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
if
(
Subtarget
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
->
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_64_SwiftError_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? nullptr : std :: next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 || Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; const bool LittleEndian = getContext ( ) . getAsmInfo ( ) -> isLittleEndian ( ) ; EmitA64MappingSymbol ( ) ; for ( unsigned II = 0 ; II != 4 ; ++ II ) { const unsigned I = LittleEndian ? ( 4 - II - 1 ) : II ; Buffer [ 4 - II - 1 ] = uint8_t ( Inst >> I * CHAR_BIT ) ; } MCELFStreamer :: EmitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> static inline unsigned long * ia64_rse_skip_regs ( unsigned long * addr , long num_regs ) { long delta = ia64_rse_slot_num ( addr ) + num_regs ; if ( num_regs < 0 ) delta -= 0x3e ; return addr + num_regs + delta / 0x3f ; } </s>

The inverse of the above : given bspstore and the number of registers , calculate ar.bsp .


<s> static void rs6000_alloc_sdmode_stack_slot ( void ) { tree t ; basic_block bb ; gimple_stmt_iterator gsi ; gcc_assert ( cfun -> machine -> sdmode_stack_slot == NULL_RTX ) ; if ( ira_use_lra_p ) return ; if ( TARGET_NO_SDMODE_STACK ) return ; FOR_EACH_BB_FN ( bb , cfun ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { tree ret = walk_gimple_op ( gsi_stmt ( gsi ) , rs6000_check_sdmode , NULL ) ; if ( ret ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } for ( t = DECL_ARGUMENTS ( cfun -> decl ) ; t ; t = DECL_CHAIN ( t ) ) { if ( TREE_TYPE ( t ) == error_mark_node ) continue ; if ( TYPE_MODE ( TREE_TYPE ( t ) ) == SDmode || TYPE_MODE ( DECL_ARG_TYPE ( t ) ) == SDmode ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , 0 ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , 0 ) ; return ; } } } </s>

Allocate a 64-bit stack slot to be used for copying SDmode values through if this function has any SDmode references . If we are on a power7 or later , we do n't need the 64-bit stack slot since the LFIWZX and STIFWX instructions can load/store the value .


<s> bool ARMInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! AFI -> isThumbFunction ( ) || CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ARM :: tPUSH ) ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static int unspec_sqrdcmlah ( int rot ) { switch ( rot ) { case 0 : return UNSPEC_SQRDCMLAH ; case 90 : return UNSPEC_SQRDCMLAH90 ; case 180 : return UNSPEC_SQRDCMLAH180 ; case 270 : return UNSPEC_SQRDCMLAH270 ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_SQRDCMLAH * unspec for rotation amount ROT .


<s> static bool is_called_in_ARM_mode ( tree func ) { gcc_assert ( TREE_CODE ( func ) == FUNCTION_DECL ) ; if ( TARGET_CALLEE_INTERWORKING && TREE_PUBLIC ( func ) ) return true ; return lookup_attribute ( "interfacearm" , DECL_ATTRIBUTES ( func ) ) != NULL_TREE ; return false ; } </s>

Return non-zero if FUNC must be entered in ARM mode .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
&
MI
,
ArrayRef
<
MachineOperand
>
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
if
(
Opcode
==
SystemZ
::
Trap
)
{
MI
.
setDesc
(
get
(
SystemZ
::
CondTrap
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
Return
||
Opcode
==
SystemZ
::
Return_XPLINK
)
{
MI
.
setDesc
(
get
(
Opcode
==
SystemZ
::
Return
SystemZ
::
CondReturn
:
SystemZ
::
CondReturn_XPLINK
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallJG
)
{
MachineOperand
FirstOp
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
removeOperand
(
1
)
;
MI
.
removeOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBRCL
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
FirstOp
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
if
(
Opcode
==
SystemZ
::
CallBR
)
{
MachineOperand
Target
=
MI
.
getOperand
(
0
)
;
const
uint32_t
*
RegMask
=
MI
.
getOperand
(
1
)
.
getRegMask
(
)
;
MI
.
removeOperand
(
1
)
;
MI
.
removeOperand
(
0
)
;
MI
.
setDesc
(
get
(
SystemZ
::
CallBCR
)
)
;
MachineInstrBuilder
(
*
MI
.
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
add
(
Target
)
.
addRegMask
(
RegMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> static rtx alignment_with_canonical_addr ( rtx align ) { rtx canon ; rtx addr = XEXP ( align , 0 ) ; if ( REG_P ( addr ) ) canon = addr ; else if ( GET_CODE ( addr ) == PLUS ) { rtx addrop0 = XEXP ( addr , 0 ) ; rtx addrop1 = XEXP ( addr , 1 ) ; if ( ! REG_P ( addrop0 ) ) addrop0 = force_reg ( GET_MODE ( addrop0 ) , addrop0 ) ; if ( ! REG_P ( addrop1 ) ) addrop1 = force_reg ( GET_MODE ( addrop1 ) , addrop1 ) ; canon = gen_rtx_PLUS ( GET_MODE ( addr ) , addrop0 , addrop1 ) ; } else canon = force_reg ( GET_MODE ( addr ) , addr ) ; return gen_rtx_AND ( GET_MODE ( align ) , canon , GEN_INT ( - 16 ) ) ; } </s>

Return RTX with its address canonicalized to ( reg ) or ( + reg reg ) . Here RTX is an ( & addr ( const_int -16 ) ) . Always return a new copy to avoid problems with combine .


isArgumentReg - Returns true if Reg can be used as an argument to a function .


<s> bool X86LowerTileCopy :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & ST = MF . getSubtarget < X86Subtarget > ( ) ; const X86InstrInfo * TII = ST . getInstrInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ++ ; if ( ! MI . isCopy ( ) ) continue ; MachineOperand & DstMO = MI . getOperand ( 0 ) ; MachineOperand & SrcMO = MI . getOperand ( 1 ) ; Register SrcReg = SrcMO . getReg ( ) ; Register DstReg = DstMO . getReg ( ) ; if ( ! X86 :: TILERegClass . contains ( DstReg , SrcReg ) ) continue ; const TargetRegisterInfo * TRI = ST . getRegisterInfo ( ) ; unsigned Size = TRI -> getSpillSize ( X86 :: TILERegClass ) ; Align Alignment = TRI -> getSpillAlign ( X86 :: TILERegClass ) ; int TileSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Size = TRI -> getSpillSize ( X86 :: GR64RegClass ) ; Alignment = TRI -> getSpillAlign ( X86 :: GR64RegClass ) ; int StrideSS = MF . getFrameInfo ( ) . CreateSpillStackObject ( Size , Alignment ) ; Register GR64Cand = X86 :: RAX ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , TII -> get ( X86 :: IMPLICIT_DEF ) , GR64Cand ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64mr ) ) , StrideSS ) . addReg ( GR64Cand ) ; BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64ri ) , GR64Cand ) . addImm ( 64 ) ; unsigned Opc = X86 :: TILESTORED ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) ) , TileSS ) . addReg ( SrcReg , getKillRegState ( SrcMO . isKill ( ) ) ) ; MachineOperand & MO = NewMI -> getOperand ( 2 ) ; MO . setReg ( GR64Cand ) ; MO . setIsKill ( true ) ; Opc = X86 :: TILELOADD ; NewMI = addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( Opc ) , DstReg ) , TileSS ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( X86 :: MOV64rm ) , GR64Cand ) , StrideSS ) ; MI . eraseFromParent ( ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned getMaxNumElements ( ElementCount VF ) const { if ( ! VF . isScalable ( ) ) return VF . getFixedValue ( ) ; return VF . getKnownMinValue ( ) * ST -> getVScaleForTuning ( ) ; } </s>

Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF .


" EXPORTed [base class of exported class]\n"

Decide if a base class of a class should also have its vtable and rtti exported .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> MVT AArch64TargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const { return MVT :: i64 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> static rtx loongarch_force_address ( rtx x , machine_mode mode ) { if ( ! loongarch_legitimate_address_p ( mode , x , false ) ) x = force_reg ( Pmode , x ) ; return x ; } </s>

If X is not a valid address for mode MODE , force it into a register .


<s> static tree rs6000_init_stack_protect_guard ( void ) { if ( rs6000_stack_protector_guard == SSP_GLOBAL ) return default_stack_protect_guard ( ) ; return NULL_TREE ; } </s>

Only create the global variable for the stack protect guard if we are using the global flavor of that guard .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) || ( VT == MVT :: v16f32 && Subtarget . useAVX512Regs ( ) ) ) { if ( VT == MVT :: f32 && Enabled == ReciprocalEstimate :: Unspecified ) return SDValue ( ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; unsigned Opcode = VT == MVT :: v16f32 ? X86ISD :: RCP14 : X86ISD :: FRCP ; return DAG . getNode ( Opcode , SDLoc ( Op ) , VT , Op ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> bool X86TargetLowering :: IsDesirableToPromoteOp ( SDValue Op , EVT & PVT ) const { EVT VT = Op . getValueType ( ) ; if ( VT != MVT :: i16 ) return false ; auto IsFoldableRMW = [ ] ( SDValue Load , SDValue Op ) { if ( ! Op . hasOneUse ( ) ) return false ; SDNode * User = * Op -> use_begin ( ) ; if ( ! ISD :: isNormalStore ( User ) ) return false ; auto * Ld = cast < LoadSDNode > ( Load ) ; auto * St = cast < StoreSDNode > ( User ) ; return Ld -> getBasePtr ( ) == St -> getBasePtr ( ) ; } ; bool Commute = false ; switch ( Op . getOpcode ( ) ) { default : return false ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : break ; case ISD :: SHL : case ISD :: SRL : { SDValue N0 = Op . getOperand ( 0 ) ; if ( MayFoldLoad ( N0 ) && IsFoldableRMW ( N0 , Op ) ) return false ; break ; } case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : Commute = true ; LLVM_FALLTHROUGH ; case ISD :: SUB : { SDValue N0 = Op . getOperand ( 0 ) ; SDValue N1 = Op . getOperand ( 1 ) ; if ( MayFoldLoad ( N1 ) && ( ! Commute || ! isa < ConstantSDNode > ( N0 ) || ( Op . getOpcode ( ) != ISD :: MUL && IsFoldableRMW ( N1 , Op ) ) ) ) return false ; if ( MayFoldLoad ( N0 ) && ( ( Commute && ! isa < ConstantSDNode > ( N1 ) ) || ( Op . getOpcode ( ) != ISD :: MUL && IsFoldableRMW ( N0 , Op ) ) ) ) return false ; } } PVT = MVT :: i32 ; return true ; } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type .


<s> static pad_direction rs6000_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! AGGREGATE_PADDING_FIXED ) { if ( BYTES_BIG_ENDIAN ) { HOST_WIDE_INT size = 0 ; if ( mode == BLKmode ) { if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == 1 || size == 2 || size == 4 ) return PAD_DOWNWARD ; } return PAD_UPWARD ; } if ( AGGREGATES_PAD_UPWARD_ALWAYS ) { if ( type != 0 && AGGREGATE_TYPE_P ( type ) ) return PAD_UPWARD ; } return default_function_arg_padding ( mode , type ) ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . For the AIX ABI structs are always stored left shifted in their argument slot .


<s> machine_mode memory_vector_mode ( const function_instance & fi ) const OVERRIDE { poly_uint64 nunits = GET_MODE_NUNITS ( fi . vector_mode ( 0 ) ) ; return aarch64_sve_data_mode ( m_to_mode , nunits ) . require ( ) ; } </s>

If the function addresses memory , return a vector mode whose GET_MODE_NUNITS is the number of elements addressed and whose GET_MODE_INNER is the mode of a single scalar memory element .


<s> static rtx loongarch_expand_builtin_direct ( enum insn_code icode , rtx target , tree exp , bool has_target_p ) { struct expand_operand ops [ MAX_RECOG_OPERANDS ] ; int opno , argno ; opno = 0 ; if ( has_target_p ) create_output_operand ( & ops [ opno ++ ] , target , TYPE_MODE ( TREE_TYPE ( exp ) ) ) ; gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ; for ( argno = 0 ; argno < call_expr_nargs ( exp ) ; argno ++ ) loongarch_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno ) ; return loongarch_expand_builtin_insn ( icode , opno , ops , has_target_p ) ; } </s>

Expand a LARCH_BUILTIN_DIRECT or LARCH_BUILTIN_DIRECT_NO_TARGET function ; HAS_TARGET_P says which . EXP is the CALL_EXPR that calls the function and ICODE is the code of the associated .md pattern . TARGET , if nonnull , suggests a good place to put the result .


<s> const LoongArchInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> InstructionCost ARMTTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , Optional < FastMathFlags > FMF , TTI :: TargetCostKind CostKind ) { if ( TTI :: requiresOrderedReduction ( FMF ) ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , FMF , CostKind ) ; EVT ValVT = TLI -> getValueType ( DL , ValTy ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ValVT . isSimple ( ) || ISD != ISD :: ADD ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , FMF , CostKind ) ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; static const CostTblEntry CostTblAdd [ ] { { ISD :: ADD , MVT :: v16i8 , 1 } , { ISD :: ADD , MVT :: v8i16 , 1 } , { ISD :: ADD , MVT :: v4i32 , 1 } , } ; if ( const auto * Entry = CostTableLookup ( CostTblAdd , ISD , LT . second ) ) return Entry -> Cost * ST -> getMVEVectorCostFactor ( CostKind ) * LT . first ; return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , FMF , CostKind ) ; } </s>

Calculate the cost of vector reduction intrinsics .


<s>
StringRef
CSKYMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_CSKY_ADDR
:
return
""
;
case
VK_CSKY_PCREL
:
return
""
;
case
VK_CSKY_GOT
:
return
"@GOT"
;
case
VK_CSKY_GOTPC
:
return
"@GOTPC"
;
case
VK_CSKY_GOTOFF
:
return
"@GOTOFF"
;
case
VK_CSKY_PLT
:
return
"@PLT"
;
case
VK_CSKY_TPOFF
:
return
"@TPOFF"
;
case
VK_CSKY_TLSGD
:
return
"@TLSGD"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .

CSKY
CSKY
"Invalid ELF symbol kind"
CSKY
""
CSKY
""
CSKY
"@GOT"
CSKY
"@GOTPC"
CSKY
"@GOTOFF"
CSKY
"@PLT"
CSKY
"@TPOFF"
CSKY
"@TLSGD"


<s> const AArch64Subtarget * AArch64TargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < AArch64Subtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return MVT :: v32i8 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return MVT :: i8 ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return MVT :: v16i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


runOnMachineFunction - Emit the function body .


<s> const TargetRegisterClass * X86RegisterInfo :: getGPRsForTailCall ( const MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( F && F -> getCallingConv ( ) == CallingConv :: GHC ) { if ( Is64Bit ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } if ( IsWin64 || ( F && F -> getCallingConv ( ) == CallingConv :: X86_64_Win64 ) ) return & X86 :: GR64_TCW64RegClass ; else if ( Is64Bit ) return & X86 :: GR64_TCRegClass ; bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & X86 :: GR32RegClass ; return & X86 :: GR32_TCRegClass ; } </s>

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls .


<s> bool SHUXIFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( SHUXI :: POP ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> virtual unsigned getNumFixupKinds ( ) const LLVM_OVERRIDE { return SystemZ :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
void
SystemZInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
&
SystemZ
::
GR32RegClass
||
RC
==
&
SystemZ
::
ADDR32RegClass
)
Opc
=
SystemZ
::
MOV32mr
;
else
if
(
RC
==
&
SystemZ
::
GR64RegClass
||
RC
==
&
SystemZ
::
ADDR64RegClass
)
{
Opc
=
SystemZ
::
MOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP32RegClass
)
{
Opc
=
SystemZ
::
FMOV32mr
;
}
else
if
(
RC
==
&
SystemZ
::
FP64RegClass
)
{
Opc
=
SystemZ
::
FMOV64mr
;
}
else
if
(
RC
==
&
SystemZ
::
GR64PRegClass
)
{
Opc
=
SystemZ
::
MOV64Pmr
;
}
else
if
(
RC
==
&
SystemZ
::
GR128RegClass
)
{
Opc
=
SystemZ
::
MOV128mr
;
}
else
llvm_unreachable
(
"Unsupported regclass to store"
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool ix86_force_load_from_GOT_p ( rtx x ) { return ( ( TARGET_64BIT || HAVE_AS_IX86_GOT32X ) && ! TARGET_PECOFF && ! TARGET_MACHO && ! flag_plt && ! flag_pic && ix86_cmodel != CM_LARGE && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) && ! SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

True if the function symbol operand X should be loaded from GOT . NB : In 32-bit mode , only non-PIC is allowed in inline assembly statements , since a PIC register could not be available at the call site .


"Asked to disassemble an ARM instruction but Subtarget is in Thumb "

Returns the disassembly of a single instruction .


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
(
const
AArch64InstrInfo
*
)
MF
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>


<s> static rtx_insn * emit_window_save ( rtx increment ) { rtx_insn * insn = emit_insn ( gen_window_save ( increment ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ) ) ; add_reg_note ( insn , REG_CFA_WINDOW_SAVE , const0_rtx ) ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , hard_frame_pointer_rtx , INCOMING_FRAME_SP_OFFSET ) ) ; return insn ; } </s>


<s> void MipsPassConfig :: addPreSched2 ( ) { addPass ( createMipsExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM64
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm64_pcrel_adr_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_adrp_imm21"
,
0
,
32
,
PCRelFlagVal
}
,
{
"fixup_arm64_add_imm12"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale1"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale2"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale4"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale8"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldst_imm12_scale16"
,
10
,
12
,
0
}
,
{
"fixup_arm64_ldr_pcrel_imm19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_arm64_movw"
,
5
,
16
,
0
}
,
{
"fixup_arm64_pcrel_branch14"
,
5
,
14
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_branch19"
,
5
,
19
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_branch26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_arm64_pcrel_call26"
,
0
,
26
,
PCRelFlagVal
}
,
{
"fixup_arm64_tlsdesc_call"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"accessing thread-local storage is not currently supported "

"with %<-mpure-code%> or %<-mslow-flash-data%>"

Return TRUE if X contains any TLS symbol references .


<s>
int
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
MFI
.
getObjectOffset
(
FI
)
;
}
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( F . hasAvailableExternallyLinkage ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool isReg ( ) const { return Kind == Register ; } </s>


"X86-64 PIC uses RIP relative addressing"


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static bool valid_src_p ( rtx src , rtx_insn * insn , struct loop * loop , bool * pre_post , rtx * base , rtx * offset , bool load_pair ) { subrtx_var_iterator :: array_type array ; rtx x = NULL_RTX ; FOR_EACH_SUBRTX_VAR ( iter , array , src , NONCONST ) if ( MEM_P ( * iter ) ) { x = * iter ; break ; } if ( ! x ) return false ; struct aarch64_address_info addr ; machine_mode mode = GET_MODE ( x ) ; if ( ! aarch64_classify_address ( & addr , XEXP ( x , 0 ) , mode , true ) ) return false ; unsigned regno = REGNO ( addr . base ) ; if ( global_regs [ regno ] || fixed_regs [ regno ] ) return false ; if ( addr . type == ADDRESS_REG_WB ) { unsigned code = GET_CODE ( XEXP ( x , 0 ) ) ; * pre_post = true ; * base = addr . base ; if ( code == PRE_MODIFY || code == POST_MODIFY ) * offset = addr . offset ; else { unsigned int_offset = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( load_pair && ( code == POST_INC || code == POST_DEC ) ) int_offset *= 2 ; * offset = GEN_INT ( int_offset ) ; } return true ; } else if ( addr . type == ADDRESS_REG_IMM || addr . type == ADDRESS_REG_REG ) { if ( ! iv_p ( insn , addr . base , loop ) ) return false ; * base = addr . base ; * offset = addr . offset ; return true ; } return false ; } </s>

Return true if SRC is a strided load in the LOOP , false otherwise . If it is a strided load , set the BASE and OFFSET . Also , if this is a pre/post increment load , set PRE_POST to true .


"Tail call for extern symbol not yet supported."

Targets should implement this to emit instructions .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , ARM :: QPRRegisterClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , ARM :: CCRRegisterClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> std :: unique_ptr < ARMInputExMap > ARMInputExMap :: create ( Input & pInput ) { std :: unique_ptr < ARMInputExMap > exMap ( new ARMInputExMap ( ) ) ; LDContext * ctx = pInput . context ( ) ; for ( LDContext :: sect_iterator it = ctx -> sectBegin ( ) , end = ctx -> sectEnd ( ) ; it != end ; ++ it ) { LDSection * sect = * it ; if ( sect -> type ( ) == llvm :: ELF :: SHT_ARM_EXIDX ) { ARMExSectionTuple * exTuple = exMap -> getOrCreateByExSection ( * sect ) ; exTuple -> setExIdxSection ( sect ) ; exTuple -> setTextSection ( sect -> getLink ( ) ) ; if ( sect -> getLink ( ) == NULL ) { fatal ( diag :: eh_missing_text_section ) << sect -> name ( ) << pInput . name ( ) ; } } } ARMInputExMap :: iterator it = exMap -> begin ( ) ; ARMInputExMap :: iterator end = exMap -> end ( ) ; while ( it != end ) { ARMExSectionTuple * exTuple = it -> second . get ( ) ; LDSection * const text = exTuple -> getTextSection ( ) ; LDSection * const exIdx = exTuple -> getExIdxSection ( ) ; if ( ( text -> kind ( ) == LDFileFormat :: Ignore ) || ( text -> kind ( ) == LDFileFormat :: Folded ) ) { exIdx -> setKind ( LDFileFormat :: Ignore ) ; ARMInputExMap :: iterator deadIt = it ++ ; exMap -> erase ( deadIt ) ; continue ; } RegionFragment * textFrag = findRegionFragment ( * text ) ; RegionFragment * exIdxFrag = findRegionFragment ( * exIdx ) ; exTuple -> setTextFragment ( textFrag ) ; exTuple -> setExIdxFragment ( exIdxFrag ) ; if ( exIdxFrag == NULL ) { ARMInputExMap :: iterator deadIt = it ++ ; exMap -> erase ( deadIt ) ; continue ; } ++ it ; } return exMap ; } </s>

ARM ARM ARMInputExMap::create ARM ARM ARM ARM ARMInputExMap::iterator ARMInputExMap::iterator ARM ARMInputExMap::iterator ARMInputExMap::iterator


<s> bool easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , 0 ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , 1 ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , 0 ) ) == - 1 && INTVAL ( CONST_VECTOR_ELT ( op , 1 ) ) == - 1 ) return true ; return false ; } else if ( mode == V1TImode ) return false ; step = GET_MODE_NUNITS ( mode ) / 4 ; copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return true ; return false ; } </s>

Return true if OP is of the given MODE and can be synthesized with a vspltisb , vspltish or vspltisw .


<s> enum tls_model tls_symbolic_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) != SYMBOL_REF ) return TLS_MODEL_NONE ; return SYMBOL_REF_TLS_MODEL ( op ) ; } </s>

Return the TLS type for TLS symbols , 0 for otherwise .


<s> int X86TTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID IID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF ) { static const CostTblEntry XOPCostTbl [ ] = { { ISD :: BITREVERSE , MVT :: v4i64 , 4 } , { ISD :: BITREVERSE , MVT :: v8i32 , 4 } , { ISD :: BITREVERSE , MVT :: v16i16 , 4 } , { ISD :: BITREVERSE , MVT :: v32i8 , 4 } , { ISD :: BITREVERSE , MVT :: v2i64 , 1 } , { ISD :: BITREVERSE , MVT :: v4i32 , 1 } , { ISD :: BITREVERSE , MVT :: v8i16 , 1 } , { ISD :: BITREVERSE , MVT :: v16i8 , 1 } , { ISD :: BITREVERSE , MVT :: i64 , 3 } , { ISD :: BITREVERSE , MVT :: i32 , 3 } , { ISD :: BITREVERSE , MVT :: i16 , 3 } , { ISD :: BITREVERSE , MVT :: i8 , 3 } } ; unsigned ISD = ISD :: DELETED_NODE ; switch ( IID ) { default : break ; case Intrinsic :: bitreverse : ISD = ISD :: BITREVERSE ; break ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; MVT MTy = LT . second ; if ( ST -> hasXOP ( ) ) if ( const auto * Entry = CostTableLookup ( XOPCostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; return BaseT :: getIntrinsicInstrCost ( IID , RetTy , Tys , FMF ) ; } </s>


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI . getOpcode ( ) == ARM :: INLINEASM ) return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: MOVi16_ga_pcrel : case ARM :: MOVTi16_ga_pcrel : case ARM :: t2MOVi16_ga_pcrel : case ARM :: t2MOVTi16_ga_pcrel : return 4 ; case ARM :: MOVi32imm : case ARM :: t2MOVi32imm : return 8 ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: Int_eh_sjlj_longjmp : return 16 ; case ARM :: tInt_eh_sjlj_longjmp : return 10 ; case ARM :: tInt_WIN_eh_sjlj_longjmp : return 12 ; case ARM :: Int_eh_sjlj_setjmp : case ARM :: Int_eh_sjlj_setjmp_nofp : return 20 ; case ARM :: tInt_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp_nofp : return 12 ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; } } </s>


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static void register_builtin_types ( ) { scalar_types [ VECTOR_TYPE_ ## ACLE_NAME ] = SCALAR_TYPE ; for ( unsigned int i = 0 ; i < NUM_VECTOR_TYPES ; ++ i ) { tree eltype = scalar_types [ i ] ; tree vectype ; unsigned int num_zr = 0 , num_pr = 0 ; if ( eltype == boolean_type_node ) { vectype = build_truth_vector_type_for_mode ( BYTES_PER_SVE_VECTOR , VNx16BImode ) ; gcc_assert ( TYPE_MODE ( vectype ) == VNx16BImode && TYPE_MODE ( vectype ) == TYPE_MODE_RAW ( vectype ) && TYPE_ALIGN ( vectype ) == 16 && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BYTES_PER_SVE_VECTOR ) ) ; num_pr = 1 ; } else { scalar_mode elmode = SCALAR_TYPE_MODE ( eltype ) ; unsigned int elbytes = GET_MODE_SIZE ( elmode ) ; poly_uint64 nunits = exact_div ( BYTES_PER_SVE_VECTOR , elbytes ) ; machine_mode mode = aarch64_sve_data_mode ( elmode , nunits ) . require ( ) ; vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) == 128 && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BITS_PER_SVE_VECTOR ) ) ; num_zr = 1 ; } vectype = build_distinct_type_copy ( vectype ) ; gcc_assert ( vectype == TYPE_MAIN_VARIANT ( vectype ) ) ; SET_TYPE_STRUCTURAL_EQUALITY ( vectype ) ; TYPE_ARTIFICIAL ( vectype ) = 1 ; TYPE_INDIVISIBLE_P ( vectype ) = 1 ; add_sve_type_attribute ( vectype , num_zr , num_pr , vector_types [ i ] . mangled_name ) ; make_type_sizeless ( vectype ) ; abi_vector_types [ i ] = vectype ; lang_hooks . types . register_builtin_type ( vectype , vector_types [ i ] . abi_name ) ; } } </s>

Register the built-in RVV ABI types , such as __rvv_int32m1_t .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s>
const
char
*
thumb2_output_casesi
(
rtx
*
operands
)
{
rtx
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
2
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"cmp\t%0, %1"
,
operands
)
;
output_asm_insn
(
"bhi\t%l3"
,
operands
)
;
switch
(
GET_MODE
(
diff_vec
)
)
{
case
E_QImode
:
return
"tbb\t[%|pc, %0]"
;
case
E_HImode
:
return
"tbh\t[%|pc, %0, lsl #1]"
;
case
E_SImode
:
if
(
flag_pic
)
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
output_asm_insn
(
"ldr\t%5, [%4, %0, lsl #2]"
,
operands
)
;
output_asm_insn
(
"add\t%4, %4, %5"
,
operands
)
;
return
"bx\t%4"
;
}
else
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
return
"ldr\t%|pc, [%4, %0, lsl #2]"
;
}
default
:
gcc_unreachable
(
)
;
}
}
</s>


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"-mslow-flash-data only supports non-pic code on armv7-m targets"

"-mpure-code only supports non-pic code on armv7-m targets"

Check any incompatible options that the user has specified .


<s> void pa_d_target_versions ( void ) { if ( TARGET_64BIT ) d_add_builtin_version ( "HPPA64" ) ; else d_add_builtin_version ( "HPPA" ) ; if ( TARGET_SOFT_FLOAT ) d_add_builtin_version ( "D_SoftFloat" ) ; else d_add_builtin_version ( "D_HardFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for HPPA targets .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> const uint32_t * SystemZXPLINK64Registers :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_SystemZ_XPLINK64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void ix86_sse_copysign_to_positive ( rtx result , rtx abs_value , rtx sign , rtx mask ) { machine_mode mode = GET_MODE ( sign ) ; rtx sgn = gen_reg_rtx ( mode ) ; if ( mask == NULL_RTX ) { machine_mode vmode ; if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else vmode = mode ; mask = ix86_build_signbit_mask ( vmode , VECTOR_MODE_P ( mode ) , false ) ; if ( ! VECTOR_MODE_P ( mode ) ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) ) ; tmp = gen_rtx_VEC_SELECT ( mode , mask , tmp ) ; mask = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , tmp ) ) ; } } else mask = gen_rtx_NOT ( mode , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , sgn , gen_rtx_AND ( mode , mask , sign ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , result , gen_rtx_IOR ( mode , abs_value , sgn ) ) ) ; } </s>

Expand copysign from SIGN to the positive value ABS_VALUE storing in RESULT . If MASK is non-null , it shall be a mask to mask out the sign-bit .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


<s> bool aarch64_sve_cnt_immediate_p ( rtx x ) { poly_int64 value ; return poly_int_rtx_p ( x , & value ) && aarch64_sve_cnt_immediate_p ( value ) ; } </s>


<s> bool nds32_rtx_costs_impl ( rtx x , int code , int outer_code , int opno ATTRIBUTE_UNUSED , int * total , bool speed ) { if ( speed ) goto performance_cost ; else goto size_cost ; performance_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case MULT : * total = COSTS_N_INSNS ( 1 ) ; break ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( 7 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; size_cost : switch ( code ) { case SET : return false ; case USE : * total = 0 ; break ; case CONST_INT : if ( outer_code == SET ) { if ( satisfies_constraint_Is05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else if ( satisfies_constraint_Is20 ( x ) ) * total = COSTS_N_INSNS ( 1 ) ; else * total = COSTS_N_INSNS ( 2 ) ; } else if ( outer_code == PLUS || outer_code == MINUS ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFT ) { if ( satisfies_constraint_Iu03 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else if ( outer_code == ASHIFTRT || outer_code == LSHIFTRT ) { if ( satisfies_constraint_Iu05 ( x ) ) * total = COSTS_N_INSNS ( 1 ) - 2 ; else * total = COSTS_N_INSNS ( 1 ) ; } else { * total = COSTS_N_INSNS ( 1 ) ; } break ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( 2 ) ; break ; default : * total = COSTS_N_INSNS ( 1 ) ; break ; } return true ; } </s>

This target hook describes the relative costs of RTL expressions . Return 'true ' when all subexpressions of x have been processed . Return 'false ' to sum the costs of sub-rtx , plus cost of this operation . Refer to gcc/rtlanal.cc for more information .


<s> const TargetRegisterClass * ARM64RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & ARM64 :: CCRRegClass ) return nullptr ; return RC ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> static unsigned HOST_WIDE_INT compute_not_to_clear_mask ( tree arg_type , rtx arg_rtx , int regno , uint32_t * padding_bits_to_clear ) { int last_used_bit = 0 ; unsigned HOST_WIDE_INT not_to_clear_mask ; if ( RECORD_OR_UNION_TYPE_P ( arg_type ) ) { not_to_clear_mask = comp_not_to_clear_mask_str_un ( arg_type , & regno , padding_bits_to_clear , 0 , & last_used_bit ) ; if ( last_used_bit != 0 ) padding_bits_to_clear [ regno ] |= ( ( uint32_t ) - 1 ) - ( ( uint32_t ) 1 << last_used_bit ) + 1 ; else not_to_clear_mask &= ~ ( HOST_WIDE_INT_1U << regno ) ; } else { not_to_clear_mask = 0 ; if ( GET_MODE ( arg_rtx ) == BLKmode ) { int i , arg_regs ; rtx reg ; gcc_assert ( TARGET_HARD_FLOAT_ABI ) ; for ( i = 0 ; i < XVECLEN ( arg_rtx , 0 ) ; i ++ ) { reg = XEXP ( XVECEXP ( arg_rtx , 0 , i ) , 0 ) ; gcc_assert ( REG_P ( reg ) ) ; not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO ( reg ) ; arg_regs = ARM_NUM_REGS ( GET_MODE ( reg ) ) ; if ( arg_regs > 1 ) { unsigned HOST_WIDE_INT mask ; mask = HOST_WIDE_INT_1U << ( REGNO ( reg ) + arg_regs ) ; mask -= HOST_WIDE_INT_1U << REGNO ( reg ) ; not_to_clear_mask |= mask ; } } } else { int arg_regs = ARM_NUM_REGS ( GET_MODE ( arg_rtx ) ) ; not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO ( arg_rtx ) ; if ( arg_regs > 1 ) { unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U << ( REGNO ( arg_rtx ) + arg_regs ) ; mask -= HOST_WIDE_INT_1U << REGNO ( arg_rtx ) ; not_to_clear_mask |= mask ; } } } return not_to_clear_mask ; } </s>

In the context of ARMv8-M Security Extensions , this function is used for both 'cmse_nonsecure_call ' and 'cmse_nonsecure_entry ' functions to compute what registers are used when returning or passing arguments , which is then returned as a mask . It will also compute a mask to indicate padding/unused bits for each of these registers , and passes this through the PADDING_BITS_TO_CLEAR pointer . The tree of the argument type is passed in ARG_TYPE , the rtl representation of the argument is passed in ARG_RTX and the starting register used to pass this argument or return value is passed in REGNO . It makes use of 'comp_not_to_clear_mask_str_un ' to compute these for struct and union types .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func -> hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool CJGInstrInfo :: isUnpredicatedTerminator ( const MachineInstr & MI ) const { if ( ! MI . isTerminator ( ) ) return false ; if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ; if ( ! MI . isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> bool PPCRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const PPCInstrInfo * InstrInfo = Subtarget . getInstrInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & Info = MFI . getCalleeSavedInfo ( ) ; if ( ! MFI . isCalleeSavedInfoValid ( ) ) return true ; unsigned FrameSize = MFI . getStackSize ( ) ; if ( FrameSize & ~ 0x7FFF ) return true ; for ( unsigned i = 0 ; i < Info . size ( ) ; i ++ ) { int FrIdx = Info [ i ] . getFrameIdx ( ) ; unsigned Reg = Info [ i ] . getReg ( ) ; const TargetRegisterClass * RC = getMinimalPhysRegClass ( Reg ) ; unsigned Opcode = InstrInfo -> getStoreOpcodeForSpill ( RC ) ; if ( ! MFI . isFixedObjectIndex ( FrIdx ) ) { if ( offsetMinAlignForOpcode ( Opcode ) > 1 ) return true ; } if ( InstrInfo -> isXFormMemOp ( Opcode ) ) return true ; } return false ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> FastISel * PPC :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { const PPCSubtarget & Subtarget = FuncInfo . MF -> getSubtarget < PPCSubtarget > ( ) ; if ( Subtarget . isPPC64 ( ) ) return new PPCFastISel ( FuncInfo , LibInfo ) ; return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

PowerPC PPC::createFastISel PPC PPC PPC PPC


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? getSUBriOpcode ( Is64Bit , Offset ) : getADDriOpcode ( Is64Bit , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s>
bool
ARMBaseInstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
if
(
!
WidenVMOVS
||
!
MI
->
isCopy
(
)
)
return
false
;
unsigned
DstRegS
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
SrcRegS
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
if
(
!
ARM
::
SPRRegClass
.
contains
(
DstRegS
,
SrcRegS
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
DstRegD
=
TRI
->
getMatchingSuperReg
(
DstRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
unsigned
SrcRegD
=
TRI
->
getMatchingSuperReg
(
SrcRegS
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DstRegD
||
!
SrcRegD
)
return
false
;
if
(
!
MI
->
definesRegister
(
DstRegD
,
TRI
)
||
MI
->
readsRegister
(
DstRegD
,
TRI
)
)
return
false
;
if
(
MI
->
getOperand
(
0
)
.
isDead
(
)
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"widening:    "
<<
*
MI
)
;
int
ImpDefIdx
=
MI
->
findRegisterDefOperandIdx
(
DstRegD
)
;
if
(
ImpDefIdx
!=
1
)
MI
->
RemoveOperand
(
ImpDefIdx
)
;
MI
->
setDesc
(
get
(
ARM
::
VMOVD
)
)
;
MI
->
getOperand
(
0
)
.
setReg
(
DstRegD
)
;
MI
->
getOperand
(
1
)
.
setReg
(
SrcRegD
)
;
AddDefaultPred
(
MachineInstrBuilder
(
MI
)
)
;
MI
->
getOperand
(
1
)
.
setIsUndef
(
)
;
MachineInstrBuilder
(
MI
)
.
addReg
(
SrcRegS
,
RegState
::
Implicit
)
;
if
(
MI
->
getOperand
(
1
)
.
isKill
(
)
)
{
MI
->
getOperand
(
1
)
.
setIsKill
(
false
)
;
MI
->
addRegisterKilled
(
SrcRegS
,
TRI
,
true
)
;
}
DEBUG
(
dbgs
(
)
<<
"replaced by: "
<<
*
MI
)
;
return
true
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool MipsTargetELFStreamer :: emitDirectiveCpRestore ( int Offset , function_ref < unsigned ( ) > GetATReg , SMLoc IDLoc , const MCSubtargetInfo * STI ) { MipsTargetStreamer :: emitDirectiveCpRestore ( Offset , GetATReg , IDLoc , STI ) ; if ( ! Pic || ( getABI ( ) . IsN32 ( ) || getABI ( ) . IsN64 ( ) ) ) return true ; emitStoreWithImmOffset ( Mips :: SW , GPReg , Mips :: SP , Offset , GetATReg , IDLoc , STI ) ; return true ; } </s>


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . canUseCMOV ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> bool MipsCallEntry :: isAliased ( const MachineFrameInfo * ) const { return false ; } </s>

Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Value .


<s> void PPCAIXAsmPrinter :: emitGlobalVariable ( const GlobalVariable * GV ) { if ( isSpecialLLVMGlobalArrayToSkip ( GV ) || isSpecialLLVMGlobalArrayForStaticInit ( GV ) ) return ; if ( GV -> hasAttribute ( "toc-data" ) ) { TOCDataGlobalVars . push_back ( GV ) ; return ; } emitGlobalVariableHelper ( GV ) ; } </s>

Emit the specified global variable to the .s file .


<s> static void mips_restore_reg ( rtx reg , rtx mem ) { if ( TARGET_MIPS16 && REGNO ( reg ) == RETURN_ADDR_REGNUM ) reg = gen_rtx_REG ( GET_MODE ( reg ) , GP_REG_FIRST + 7 ) ; else if ( GET_MODE ( reg ) == DFmode && ( ! TARGET_FLOAT64 || mips_abi == ABI_32 ) ) { mips_add_cfa_restore ( mips_subword ( reg , true ) ) ; mips_add_cfa_restore ( mips_subword ( reg , false ) ) ; } else mips_add_cfa_restore ( reg ) ; mips_emit_save_slot_move ( reg , mem , MIPS_EPILOGUE_TEMP ( GET_MODE ( reg ) ) ) ; if ( REGNO ( reg ) == REGNO ( mips_epilogue . cfa_reg ) ) mips_epilogue_set_cfa ( stack_pointer_rtx , mips_epilogue . cfa_restore_sp_offset ) ; } </s>

Emit instructions to restore register REG from slot MEM .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
bool
LEAUsesAG
=
ST
.
leaUsesAG
(
)
;
bool
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
MF
.
getFunction
(
)
.
hasOptSize
(
)
;
bool
UseLEAForSP
=
ST
.
useLeaForSP
(
)
;
TSM
.
init
(
&
ST
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
auto
*
PSI
=
&
getAnalysis
<
ProfileSummaryInfoWrapperPass
>
(
)
.
getPSI
(
)
;
auto
*
MBFI
=
(
PSI
&&
PSI
->
hasProfileSummary
(
)
)
&
getAnalysis
<
LazyMachineBlockFrequencyInfoPass
>
(
)
.
getBFI
(
)
:
nullptr
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
bool
OptIncDecPerBB
=
OptIncDec
||
llvm
::
shouldOptimizeForSize
(
&
MBB
,
PSI
,
MBFI
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
{
if
(
!
isLEA
(
I
->
getOpcode
(
)
)
)
continue
;
if
(
optTwoAddrLEA
(
I
,
MBB
,
OptIncDecPerBB
,
UseLEAForSP
)
)
continue
;
if
(
IsSlowLEA
)
processInstructionForSlowLEA
(
I
,
MBB
)
;
else
if
(
IsSlow3OpsLEA
)
processInstrForSlow3OpLEA
(
I
,
MBB
,
OptIncDecPerBB
)
;
}
if
(
LEAUsesAG
)
{
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
++
I
)
processInstruction
(
I
,
MBB
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void ARMELFStreamer :: reset ( ) { MCTargetStreamer & TS = * getTargetStreamer ( ) ; ARMTargetStreamer & ATS = static_cast < ARMTargetStreamer & > ( TS ) ; ATS . reset ( ) ; MappingSymbolCounter = 0 ; MCELFStreamer :: reset ( ) ; LastMappingSymbols . clear ( ) ; LastEMSInfo . reset ( ) ; getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_ARM_EABI_VER5 ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static bool arm_evpc_neon_vtbl ( struct expand_vec_perm_d * d ) { rtx rperm [ MAX_VECT_LEN ] , sel ; machine_mode vmode = d -> vmode ; unsigned int i , nelt = d -> nelt ; if ( BYTES_BIG_ENDIAN ) return false ; if ( d -> testing_p ) return true ; if ( vmode != V8QImode && vmode != V16QImode ) return false ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( d -> perm [ i ] ) ; sel = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; sel = force_reg ( vmode , sel ) ; arm_expand_vec_perm_1 ( d -> target , d -> op0 , d -> op1 , sel ) ; return true ; } </s>

The NEON VTBL instruction is a fully variable permuation that 's even stronger than what we expose via VEC_PERM_EXPR . What it does n't do is mask the index operand as VEC_PERM_EXPR requires . Therefore we can do slightly better by expanding this as a constant where we do n't have to apply a mask .


<s> int arm_is_longcall_p ( rtx sym_ref , int call_cookie , int call_symbol ) { if ( ! call_symbol ) { if ( GET_CODE ( sym_ref ) != MEM ) return 0 ; sym_ref = XEXP ( sym_ref , 0 ) ; } if ( GET_CODE ( sym_ref ) != SYMBOL_REF ) return 0 ; if ( call_cookie & CALL_SHORT ) return 0 ; if ( TARGET_LONG_CALLS ) { if ( flag_function_sections || DECL_SECTION_NAME ( current_function_decl ) ) return 1 ; } if ( current_file_function_operand ( sym_ref ) ) return 0 ; return ( call_cookie & CALL_LONG ) || ENCODED_LONG_CALL_ATTR_P ( XSTR ( sym_ref , 0 ) ) || TARGET_LONG_CALLS ; } </s>

Return nonzero if a 32 bit `` long_call '' should be generated for this call . We generate a long_call if the function : a. has an __attribute__ ( ( long call ) ) or b. is within the scope of a # pragma long_calls or c. the -mlong-calls command line switch has been specified . and either : 1 . -ffunction-sections is in effect or 2. the current function has __attribute__ ( ( section ) ) or 3. the target function has __attribute__ ( ( section ) ) However we do not generate a long call if the function : d. has an __attribute__ ( ( short_call ) ) or e. is inside the scope of a # pragma no_long_calls or f. is defined within the current compilation unit . This function will be called by C fragments contained in the machine description file . SYM_REF and CALL_COOKIE correspond to the matched rtl operands . CALL_SYMBOL is used to distinguish between two different callers of the function . It is set to 1 in the `` call_symbol '' and `` call_symbol_value '' patterns and to 0 in the `` call '' and `` call_value '' patterns . This is because of the difference in the SYM_REFs passed by these patterns .


<s> bool OR1KFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( * Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Modified = false ; bool enableNarrowLdOpt = Subtarget -> mergeNarrowLoads ( ) && ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowLdOpt ) ; return Modified ; } </s>


"InsertNOPsLoadStore: Erratum Fix LBR37: insert NOPs between "

"single-precision loads and the store, so the number of "

getPassName - Return a nice clean name for a pass .


<s> StringRef getPassName ( ) const override { return ARM_BRANCH_TARGETS_NAME ; } </s>


"expand_builtin_saveregs: offset from ap = %d\n"

If defined , is a C expression that produces the machine-specific code for a call to ` __builtin_saveregs ' . This code will be moved to the very beginning of the function , before any parameter access are made . The return value of this function should be an RTX that contains the value to use as the return of ` __builtin_saveregs ' . If this macro is not defined , the compiler will output an ordinary call to the library function ` __builtin_saveregs ' .


<s> static void ix86_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { if ( ! op0_preserve_value && GET_CODE ( * op0 ) == FLOAT && MEM_P ( XEXP ( * op0 , 0 ) ) && REG_P ( * op1 ) ) { enum rtx_code scode = swap_condition ( ( enum rtx_code ) * code ) ; if ( ix86_fp_compare_code_to_integer ( scode ) != UNKNOWN ) { std :: swap ( * op0 , * op1 ) ; * code = ( int ) scode ; } } } </s>

Canonicalize a comparison from one we do n't have to one we do have .


<s> static void insn_dependent_p_1 ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_mentioned_p ( x , * pinsn ) ) * pinsn = NULL_RTX ; } </s>

A helper routine for insn_dependent_p called through note_stores .


<s> static rtx push ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( TARGET_FPU_DOUBLE && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_frame_insn ( x ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; return x ; } </s>

Output RTL to push register RN onto the stack .


<s> bool loongarch_use_ins_ext_p ( rtx op , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { if ( ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; if ( ! IN_RANGE ( width , 1 , GET_MODE_BITSIZE ( GET_MODE ( op ) ) - 1 ) ) return false ; if ( bitpos < 0 || bitpos + width > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ; return true ; } </s>

Return true if ( zero_extract OP WIDTH BITPOS ) can be used as the source of an `` ext '' instruction or the destination of an `` ins '' instruction . OP must be a register operand and the following conditions must hold : 0 < = BITPOS < GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < WIDTH < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) 0 < BITPOS + WIDTH < = GET_MODE_BITSIZE ( GET_MODE ( op ) ) Also reject lengths equal to a word as they are better handled by the move patterns .


<s> bool PPCTTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) { if ( ST -> getDarwinDirective ( ) == PPC :: DIR_A2 ) return true ; return LoopHasReductions ; } </s>

Do n't restrict interleaved unrolling to small loops .


<s> bool MipsPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> void i386_pe_unique_section ( tree decl , int reloc ) { int len ; const char * name , * prefix ; char * string ; name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; name = i386_pe_strip_name_encoding_full ( name ) ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) prefix = ".text$" ; else if ( decl_readonly_section ( decl , reloc ) ) prefix = ".rdata$" ; else prefix = ".data$" ; len = strlen ( name ) + strlen ( prefix ) ; string = alloca ( len + 1 ) ; sprintf ( string , "%s%s" , prefix , name ) ; DECL_SECTION_NAME ( decl ) = build_string ( len , string ) ; } </s>


"built-in function %qE not supported for MIPS16"

Expand builtin functions . This is called from TARGET_EXPAND_BUILTIN .


<s> void PPCRegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex , int SPAdj , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; ( void ) SPAdj ; ( void ) RS ; bool LP64 = Subtarget . isPPC64 ( ) ; unsigned Reg = LP64 ? PPC :: X0 : PPC :: R0 ; unsigned SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: MFCR8pseud : PPC :: MFCRpseud ) , Reg ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( 0 ) . isKill ( ) ) ) ; if ( SrcReg != PPC :: CR0 ) BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: RLWINM8 : PPC :: RLWINM ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( getPPCRegisterNumbering ( SrcReg ) * 4 ) . addImm ( 0 ) . addImm ( 31 ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? PPC :: STW8 : PPC :: STW ) ) . addReg ( Reg , getKillRegState ( MI . getOperand ( 1 ) . getImm ( ) ) ) , FrameIndex ) ; MBB . erase ( II ) ; } </s>

lowerCRSpilling - Generate the code for spilling a CR register .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_type_node ) return "U6__booll" ; if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 && ! TARGET_IEEEQUAD ) return "g" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> static bool aapcs_vfp_allocate ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { int rmode_size = MAX ( GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) , GET_MODE_SIZE ( SFmode ) ) ; int shift = rmode_size / GET_MODE_SIZE ( SFmode ) ; unsigned mask = ( 1 << ( shift * pcum -> aapcs_vfp_rcount ) ) - 1 ; int regno ; for ( regno = 0 ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! TARGET_NEON ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= 2 ; rshift /= 2 ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = 0 ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return false ; } </s>

Implement the allocate field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


"ByVal args of size 0 should have been ignored by front-end."

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const MCExpr * PPCAIXAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const Function * F = dyn_cast < Function > ( CV ) ) { MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( F -> isDeclaration ( ) ? getObjFileLowering ( ) . getSectionForExternalReference ( F , TM ) : getObjFileLowering ( ) . getSectionForFunctionDescriptor ( F , TM ) ) ; return MCSymbolRefExpr :: create ( Csect -> getQualNameSymbol ( ) , OutContext ) ; } return PPCAsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> int sh_loop_align ( rtx label ) { rtx next = label ; do next = next_nonnote_insn ( next ) ; while ( next && GET_CODE ( next ) == CODE_LABEL ) ; if ( ! next || ! INSN_P ( next ) || GET_CODE ( PATTERN ( next ) ) == ADDR_DIFF_VEC || recog_memoized ( next ) == CODE_FOR_consttable_2 ) return 0 ; return align_loops_log ; } </s>

If we are inside a phony loop , almost any kind of label can turn up as the first one in the loop . Aligning a braf label causes incorrect switch destination addresses ; we can detect braf labels because they are followed by a BARRIER . Applying loop alignment to small constant or switch tables is a waste of space , so we suppress this too .


<s> bool isFPImm ( ) const { return Kind == k_FPImmediate ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> void mips_expand_scc ( rtx operands [ ] ) { rtx target = operands [ 0 ] ; enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 2 ] ; rtx op1 = operands [ 3 ] ; gcc_assert ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_INT ) ; if ( code == EQ || code == NE ) { if ( ISA_HAS_SEQ_SNE && reg_imm10_operand ( op1 , GET_MODE ( op1 ) ) ) mips_emit_binary ( code , target , op0 , op1 ) ; else { rtx zie = mips_zero_if_equal ( op0 , op1 ) ; mips_emit_binary ( code , target , zie , const0_rtx ) ; } } else mips_emit_int_order_test ( code , 0 , target , op0 , op1 ) ; } </s>

Try performing the comparison in OPERANDS [ 1 ] , whose arms are OPERANDS [ 2 ] and OPERAND [ 3 ] . Store the result in OPERANDS [ 0 ] . On 64-bit targets , the mode of the comparison and target will always be SImode , thus possibly narrower than that of the comparison 's operands .


<s> static inline struct loongarch_abi isa_default_abi ( const struct loongarch_isa * isa ) { struct loongarch_abi abi ; switch ( isa -> fpu ) { case ISA_EXT_FPU64 : if ( isa -> base == ISA_BASE_LA64V100 ) abi . base = ABI_BASE_LP64D ; break ; case ISA_EXT_FPU32 : if ( isa -> base == ISA_BASE_LA64V100 ) abi . base = ABI_BASE_LP64F ; break ; case ISA_EXT_NOFPU : if ( isa -> base == ISA_BASE_LA64V100 ) abi . base = ABI_BASE_LP64S ; break ; default : gcc_unreachable ( ) ; } abi . ext = ABI_EXT_BASE ; return abi ; } </s>

Returns the default ABI for the given instruction set .