<s> bool SystemZInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , unsigned Reg , MachineRegisterInfo * MRI ) const { unsigned DefOpc = DefMI . getOpcode ( ) ; if ( DefOpc != SystemZ :: LHIMux && DefOpc != SystemZ :: LHI && DefOpc != SystemZ :: LGHI ) return false ; if ( DefMI . getOperand ( 0 ) . getReg ( ) != Reg ) return false ; int32_t ImmVal = ( int32_t ) DefMI . getOperand ( 1 ) . getImm ( ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc ; unsigned UseIdx ; int CommuteIdx = - 1 ; bool TieOps = false ; switch ( UseOpc ) { case SystemZ :: SELRMux : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCRMux : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCHIMux ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; case SystemZ :: SELGR : TieOps = true ; LLVM_FALLTHROUGH ; case SystemZ :: LOCGR : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = SystemZ :: LOCGHI ; if ( UseMI . getOperand ( 2 ) . getReg ( ) == Reg ) UseIdx = 2 ; else if ( UseMI . getOperand ( 1 ) . getReg ( ) == Reg ) UseIdx = 2 , CommuteIdx = 1 ; else return false ; break ; default : return false ; } if ( CommuteIdx != - 1 ) if ( ! commuteInstruction ( UseMI , false , CommuteIdx , UseIdx ) ) return false ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; UseMI . setDesc ( get ( NewUseOpc ) ) ; if ( TieOps ) UseMI . tieOperands ( 0 , 1 ) ; UseMI . getOperand ( UseIdx ) . ChangeToImmediate ( ImmVal ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } </s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s>
void
ARMAsmPrinter
::
emitMachineConstantPoolValue
(
MachineConstantPoolValue
*
MCPV
)
{
const
DataLayout
&
DL
=
getDataLayout
(
)
;
int
Size
=
DL
.
getTypeAllocSize
(
MCPV
->
getType
(
)
)
;
ARMConstantPoolValue
*
ACPV
=
static_cast
<
ARMConstantPoolValue
*
>
(
MCPV
)
;
if
(
ACPV
->
isPromotedGlobal
(
)
)
{
auto
*
ACPC
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
;
for
(
const
auto
*
GV
:
ACPC
->
promotedGlobals
(
)
)
{
if
(
!
EmittedPromotedGlobalLabels
.
count
(
GV
)
)
{
MCSymbol
*
GVSym
=
getSymbol
(
GV
)
;
OutStreamer
->
emitLabel
(
GVSym
)
;
EmittedPromotedGlobalLabels
.
insert
(
GV
)
;
}
}
return
emitGlobalConstant
(
DL
,
ACPC
->
getPromotedGlobalInit
(
)
)
;
}
MCSymbol
*
MCSym
;
if
(
ACPV
->
isLSDA
(
)
)
{
MCSym
=
getCurExceptionSym
(
)
;
}
else
if
(
ACPV
->
isBlockAddress
(
)
)
{
const
BlockAddress
*
BA
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getBlockAddress
(
)
;
MCSym
=
GetBlockAddressSymbol
(
BA
)
;
}
else
if
(
ACPV
->
isGlobalValue
(
)
)
{
const
GlobalValue
*
GV
=
cast
<
ARMConstantPoolConstant
>
(
ACPV
)
->
getGV
(
)
;
unsigned
char
TF
=
Subtarget
->
isTargetMachO
(
)
ARMII
::
MO_NONLAZY
:
0
;
MCSym
=
GetARMGVSymbol
(
GV
,
TF
)
;
}
else
if
(
ACPV
->
isMachineBasicBlock
(
)
)
{
const
MachineBasicBlock
*
MBB
=
cast
<
ARMConstantPoolMBB
>
(
ACPV
)
->
getMBB
(
)
;
MCSym
=
MBB
->
getSymbol
(
)
;
}
else
{
assert
(
ACPV
->
isExtSymbol
(
)
&&
"unrecognized constant pool value"
)
;
auto
Sym
=
cast
<
ARMConstantPoolSymbol
>
(
ACPV
)
->
getSymbol
(
)
;
MCSym
=
GetExternalSymbolSymbol
(
Sym
)
;
}
const
MCExpr
*
Expr
=
MCSymbolRefExpr
::
create
(
MCSym
,
getModifierVariantKind
(
ACPV
->
getModifier
(
)
)
,
OutContext
)
;
if
(
ACPV
->
getPCAdjustment
(
)
)
{
MCSymbol
*
PCLabel
=
getPICLabel
(
DL
.
getPrivateGlobalPrefix
(
)
,
getFunctionNumber
(
)
,
ACPV
->
getLabelId
(
)
,
OutContext
)
;
const
MCExpr
*
PCRelExpr
=
MCSymbolRefExpr
::
create
(
PCLabel
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createAdd
(
PCRelExpr
,
MCConstantExpr
::
create
(
ACPV
->
getPCAdjustment
(
)
,
OutContext
)
,
OutContext
)
;
if
(
ACPV
->
mustAddCurrentAddress
(
)
)
{
MCSymbol
*
DotSym
=
OutContext
.
createTempSymbol
(
)
;
OutStreamer
->
emitLabel
(
DotSym
)
;
const
MCExpr
*
DotExpr
=
MCSymbolRefExpr
::
create
(
DotSym
,
OutContext
)
;
PCRelExpr
=
MCBinaryExpr
::
createSub
(
PCRelExpr
,
DotExpr
,
OutContext
)
;
}
Expr
=
MCBinaryExpr
::
createSub
(
Expr
,
PCRelExpr
,
OutContext
)
;
}
OutStreamer
->
emitValue
(
Expr
,
Size
)
;
}
</s>

EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file .

ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARMII::MO_NONLAZY
0
ARM
ARM
"unrecognized constant pool value"
ARM


"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


<s> static rtx_insn * rs6000_emit_savres_rtx ( rs6000_stack_t * info , rtx frame_reg_rtx , int save_area_offset , int lr_offset , machine_mode reg_mode , int sel ) { int i ; int offset , start_reg , end_reg , n_regs , use_reg ; int reg_size = GET_MODE_SIZE ( reg_mode ) ; rtx sym ; rtvec p ; rtx par ; rtx_insn * insn ; offset = 0 ; start_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? info -> first_gp_reg_save : ( sel & SAVRES_REG ) == SAVRES_FPR ? info -> first_fp_reg_save : ( sel & SAVRES_REG ) == SAVRES_VR ? info -> first_altivec_reg_save : - 1 ) ; end_reg = ( ( sel & SAVRES_REG ) == SAVRES_GPR ? 32 : ( sel & SAVRES_REG ) == SAVRES_FPR ? 64 : ( sel & SAVRES_REG ) == SAVRES_VR ? LAST_ALTIVEC_REGNO + 1 : - 1 ) ; n_regs = end_reg - start_reg ; p = rtvec_alloc ( 3 + ( ( sel & SAVRES_LR ) ? 1 : 0 ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? 1 : 0 ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , 0 ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = 0 ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != 0 ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , 0 ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) { insn = emit_jump_insn ( par ) ; JUMP_LABEL ( insn ) = ret_rtx ; } else insn = emit_insn ( par ) ; return insn ; } </s>

Construct a parallel rtx describing the effect of a call to an out-of-line register save/restore routine , and emit the insn or jump_insn as appropriate .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SUB : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: PTRADD : return performCIncOffsetToCandAddrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performINTRINSIC_WO_CHAINCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::SHL ISD::SUB ISD::PTRADD ISD::INTRINSIC_WO_CHAIN


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
getDarwinCalleeSavedRegs
(
MF
)
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CFGuard_Check
)
return
CSR_Win_AArch64_CFGuard_Check_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_SVE_VectorCall
)
return
CSR_AArch64_SVE_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return AArch64 :: X0 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> void aarch64_addti_scratch_regs ( rtx op1 , rtx op2 , rtx * low_dest , rtx * low_in1 , rtx * low_in2 , rtx * high_dest , rtx * high_in1 , rtx * high_in2 ) { * low_dest = gen_reg_rtx ( DImode ) ; * low_in1 = gen_lowpart ( DImode , op1 ) ; * low_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_lowpart_offset ( DImode , TImode ) ) ; * high_dest = gen_reg_rtx ( DImode ) ; * high_in1 = gen_highpart ( DImode , op1 ) ; * high_in2 = simplify_gen_subreg ( DImode , op2 , TImode , subreg_highpart_offset ( DImode , TImode ) ) ; } </s>

Generate DImode scratch registers for 128-bit ( TImode ) addition . OP1 represents the TImode destination operand 1 OP2 represents the TImode destination operand 2 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 .


<s> unsigned SystemZInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SystemZII :: SimpleBDXStore ) ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> int arm_const_double_rtx ( rtx x ) { const REAL_VALUE_TYPE * r ; if ( ! fp_consts_inited ) init_fp_table ( ) ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_MINUS_ZERO ( * r ) ) return 0 ; if ( real_equal ( r , & value_fp0 ) ) return 1 ; return 0 ; } </s>

Return TRUE if rtx X is a valid immediate FP constant .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"FISC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case Cpu0 :: fixup_Cpu0_16 : FullSize = 2 ; break ; default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void mips_multi_add_insn ( const char * format , ... ) { struct mips_multi_member * member ; va_list ap ; unsigned int i ; rtx op ; member = mips_multi_add ( ) ; member -> is_label_p = false ; member -> format = format ; va_start ( ap , format ) ; i = 0 ; while ( ( op = va_arg ( ap , rtx ) ) ) member -> operands [ i ++ ] = op ; va_end ( ap ) ; mips_multi_num_insns ++ ; } </s>

Add a normal insn with the given asm format to the current multi-insn sequence . The other arguments are a null-terminated list of operands .


<s> int iq2000_reg_mode_ok_for_base_p ( rtx reg , enum machine_mode mode ATTRIBUTE_UNUSED , int strict ) { return ( strict ? REGNO_MODE_OK_FOR_BASE_P ( REGNO ( reg ) , mode ) : GP_REG_OR_PSEUDO_NONSTRICT_P ( REGNO ( reg ) , mode ) ) ; } </s>

Return nonzero if REG is valid for MODE .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = MF -> begin ( ) ; const TargetInstrInfo & TII = * MF -> getTarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
SmallVector
<
MachineInstr
*
,
4
>
ToDelete
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineInstr
*
MI
=
I
;
if
(
MI
->
getOpcode
(
)
==
PPC
::
XXLOR
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
MI
->
getOperand
(
1
)
.
getReg
(
)
&&
MI
->
getOperand
(
0
)
.
getReg
(
)
==
MI
->
getOperand
(
2
)
.
getReg
(
)
)
ToDelete
.
push_back
(
MI
)
;
}
if
(
!
ToDelete
.
empty
(
)
)
Changed
=
true
;
for
(
unsigned
i
=
0
,
ie
=
ToDelete
.
size
(
)
;
i
!=
ie
;
++
i
)
{
DEBUG
(
dbgs
(
)
<<
"Removing VSX self-copy: "
<<
*
ToDelete
[
i
]
)
;
ToDelete
[
i
]
->
eraseFromParent
(
)
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> void AArch64CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , 4 > SplitVTs ; SmallVector < uint64_t , 4 > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , 0 ) ; if ( SplitVTs . size ( ) == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ 0 ] . getTypeForEVT ( Ctx ) , OrigArg . Flags ) ; return ; } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags } ) ; } SmallVector < uint64_t , 4 > BitOffsets ; for ( auto Offset : Offsets ) BitOffsets . push_back ( Offset * 8 ) ; SmallVector < unsigned , 8 > SplitRegs ; for ( auto I = & SplitArgs [ FirstRegIdx ] ; I != SplitArgs . end ( ) ; ++ I ) SplitRegs . push_back ( I -> Reg ) ; PerformArgSplit ( SplitRegs , BitOffsets ) ; } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> int non_hard_reg_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ! ( GET_CODE ( op ) == REG && REGNO ( op ) < FIRST_PSEUDO_REGISTER ) ; } </s>

Return 1 if this operand is anything other than a hard register .


<s>
void
relaxInstruction
(
const
MCInst
&
,
llvm
::
MCInst
&
)
const
{
llvm_unreachable
(
"Cannot relax instructions"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool isBarrier ( ) const { return Kind == k_Barrier ; } </s>

Tests if this is an Order dependence that is marked as a barrier .


<s> static rtx ix86_static_chain ( const_tree fndecl_or_type , bool incoming_p ) { unsigned regno ; if ( TARGET_64BIT ) { regno = R10_REG ; } else { const_tree fntype , fndecl ; unsigned int ccvt ; regno = CX_REG ; if ( TREE_CODE ( fndecl_or_type ) == FUNCTION_DECL ) { fntype = TREE_TYPE ( fndecl_or_type ) ; fndecl = fndecl_or_type ; } else { fntype = fndecl_or_type ; fndecl = NULL ; } ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { regno = AX_REG ; } else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { regno = AX_REG ; } else if ( ix86_function_regparm ( fntype , fndecl ) == 3 ) { if ( incoming_p ) { if ( fndecl == current_function_decl && ! ix86_static_chain_on_stack ) { gcc_assert ( ! reload_completed ) ; ix86_static_chain_on_stack = true ; } return gen_frame_mem ( SImode , plus_constant ( Pmode , arg_pointer_rtx , - 8 ) ) ; } regno = SI_REG ; } } return gen_rtx_REG ( Pmode , regno ) ; } </s>

Find a location for the static chain incoming to a nested function . This is a register , unless all free registers are used by arguments .


"Should only have an r11 thunk on 64-bit targets"

runOnMachineFunction - Emit the function body .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( ! Subtarget . isTargetAndroid ( ) ) return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; unsigned AddressSpace , Offset ; Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; AddressSpace = getAddressSpace ( ) ; return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> static rtx sh_delegitimize_address ( rtx orig_x ) { rtx x , y ; orig_x = delegitimize_mem_from_attrs ( orig_x ) ; x = orig_x ; if ( MEM_P ( x ) ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == CONST ) { y = XEXP ( x , 0 ) ; if ( GET_CODE ( y ) == UNSPEC ) { if ( XINT ( y , 1 ) == UNSPEC_GOT || XINT ( y , 1 ) == UNSPEC_GOTOFF || XINT ( y , 1 ) == UNSPEC_SYMOFF ) return XVECEXP ( y , 0 , 0 ) ; else if ( XINT ( y , 1 ) == UNSPEC_PCREL_SYMOFF ) { if ( GET_CODE ( XVECEXP ( y , 0 , 0 ) ) == CONST ) { rtx symplt = XEXP ( XVECEXP ( y , 0 , 0 ) , 0 ) ; if ( GET_CODE ( symplt ) == UNSPEC && XINT ( symplt , 1 ) == UNSPEC_PLT ) return XVECEXP ( symplt , 0 , 0 ) ; } } else if ( TARGET_SHMEDIA && ( XINT ( y , 1 ) == UNSPEC_EXTRACT_S16 || XINT ( y , 1 ) == UNSPEC_EXTRACT_U16 ) ) { rtx offset = XVECEXP ( y , 0 , 1 ) ; x = gen_rtx_PLUS ( Pmode , XVECEXP ( y , 0 , 0 ) , offset ) ; if ( MEM_P ( orig_x ) ) x = replace_equiv_address_nv ( orig_x , x ) ; return x ; } } } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize various UNSPEC sequences and turn them back into a direct symbol reference .


<s> bool iq2000_function_value_regno_p ( const unsigned int regno ) { return ( regno == GP_RETURN ) ; } </s>

Worker function for FUNCTION_VALUE_REGNO_P . On the IQ2000 , R2 and R3 are the only register thus used .


<s>
void
AArch64TargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
(
0
,
0
)
;
if
(
Constraint
.
size
(
)
!=
1
)
return
;
switch
(
Constraint
[
0
]
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'Z'
:
{
ConstantSDNode
*
C
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
C
)
return
;
uint64_t
CVal
=
C
->
getZExtValue
(
)
;
uint32_t
Bits
;
switch
(
Constraint
[
0
]
)
{
default
:
llvm_unreachable
(
"Unimplemented C_Other constraint"
)
;
case
'I'
:
if
(
CVal
<=
0xfff
)
break
;
return
;
case
'K'
:
if
(
A64Imms
::
isLogicalImm
(
32
,
CVal
,
Bits
)
)
break
;
return
;
case
'L'
:
if
(
A64Imms
::
isLogicalImm
(
64
,
CVal
,
Bits
)
)
break
;
return
;
case
'Z'
:
if
(
CVal
==
0
)
break
;
return
;
}
Result
=
DAG
.
getTargetConstant
(
CVal
,
Op
.
getValueType
(
)
)
;
break
;
}
case
'S'
:
{
if
(
const
GlobalAddressSDNode
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetGlobalAddress
(
GA
->
getGlobal
(
)
,
SDLoc
(
Op
)
,
GA
->
getValueType
(
0
)
)
;
}
else
if
(
const
BlockAddressSDNode
*
BA
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetBlockAddress
(
BA
->
getBlockAddress
(
)
,
BA
->
getValueType
(
0
)
)
;
}
else
if
(
const
ExternalSymbolSDNode
*
ES
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
{
Result
=
DAG
.
getTargetExternalSymbol
(
ES
->
getSymbol
(
)
,
ES
->
getValueType
(
0
)
)
;
}
else
return
;
break
;
}
case
'Y'
:
if
(
const
ConstantFPSDNode
*
CFP
=
dyn_cast
<
ConstantFPSDNode
>
(
Op
)
)
{
if
(
CFP
->
isExactlyValue
(
0.0
)
)
{
Result
=
DAG
.
getTargetConstantFP
(
0.0
,
CFP
->
getValueType
(
0
)
)
;
break
;
}
}
return
;
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool has_memory_op ( rtx_insn * mem_insn ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( mem_insn ) , ALL ) if ( MEM_P ( * iter ) ) return true ; return false ; } </s>

Return true if the rtx_insn contains a MEM RTX somewhere in it .


<s> InstructionCost AArch64TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: Add : case Instruction :: Sub : case Instruction :: Mul : case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = ( BitSize + 63 ) / 64 ; InstructionCost Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s>
StringRef
getPassName
(
)
const
override
{
return
"CSKY Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int ia64_arg_partial_bytes ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , bool named ATTRIBUTE_UNUSED ) { int words = ia64_function_arg_words ( type , mode ) ; int offset = ia64_function_arg_offset ( cum , type , words ) ; if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return 0 ; if ( words + cum -> words + offset <= MAX_ARGUMENT_SLOTS ) return 0 ; return ( MAX_ARGUMENT_SLOTS - cum -> words - offset ) * UNITS_PER_WORD ; } </s>

Return number of bytes , at the beginning of the argument , that must be put in registers . 0 is the argument is entirely in registers or entirely in memory .


<s> static bool rs6000_is_costly_dependence ( rtx insn , rtx next , rtx link , int cost , int distance ) { if ( rs6000_sched_costly_dep == no_dep_costly ) return false ; if ( rs6000_sched_costly_dep == all_deps_costly ) return true ; if ( rs6000_sched_costly_dep == store_to_load_dep_costly && is_load_insn ( next ) && is_store_insn ( insn ) ) return true ; if ( rs6000_sched_costly_dep == true_store_to_load_dep_costly && is_load_insn ( next ) && is_store_insn ( insn ) && ( ! link || ( int ) REG_NOTE_KIND ( link ) == 0 ) ) return true ; if ( rs6000_sched_costly_dep <= max_dep_latency && ( ( cost - distance ) >= ( int ) rs6000_sched_costly_dep ) ) return true ; return false ; } </s>

Returns whether the dependence between INSN and NEXT is considered costly by the given target .


<s> static bool mips_ok_for_lazy_binding_p ( rtx x ) { return ( TARGET_USE_GOT && GET_CODE ( x ) == SYMBOL_REF && ! SYMBOL_REF_BIND_NOW_P ( x ) && ! mips_symbol_binds_local_p ( x ) ) ; } </s>

Return true if calls to X can use R_MIPS_CALL * relocations .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ 0 ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool X86PassConfig :: addInstSelector ( ) { addPass ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getTargetTriple ( ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; addPass ( createX86GlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> SDValue LanaiTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Lanai32 ) ; for ( unsigned I = 0 ; I != RVLocs . size ( ) ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool mips_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( ! mips_mode_ok_for_mov_fmt_p ( mode1 ) && ! mips_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ; } </s>


<s> bool CJGFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == 8 ) return false ; if ( Subtarget . hasInt256 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getArgOperand ( 3 ) -> getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align :: None ( ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
const
char
*
nds32_output_16bit_load
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
=
XEXP
(
operands
[
1
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
nds32_mem_format
(
operands
[
1
]
)
)
{
case
ADDRESS_REG
:
operands
[
1
]
=
code
;
output_asm_insn
(
"lwi450\t%0, [%1]"
,
operands
)
;
break
;
case
ADDRESS_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"l%ci333\t%%0, %%1"
,
size
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_INC_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"lwi333.bi\t%%0, %%1, 4"
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_POST_MODIFY_LO_REG_IMM3U
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"lwi333.bi\t%%0, %%1"
)
;
output_asm_insn
(
pattern
,
operands
)
;
break
;
case
ADDRESS_R8_IMM7U
:
output_asm_insn
(
"lwi45.fe\t%0, %e1"
,
operands
)
;
break
;
case
ADDRESS_FP_IMM7U
:
output_asm_insn
(
"lwi37\t%0, %1"
,
operands
)
;
break
;
case
ADDRESS_SP_IMM7U
:
operands
[
1
]
=
XEXP
(
code
,
1
)
;
output_asm_insn
(
"lwi37.sp\t%0, [ + (%1)]"
,
operands
)
;
break
;
default
:
break
;
}
return
""
;
}
</s>


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { if ( ! Subtarget -> hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some equality condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; OPERANDS [ 3 ] is the second operand and may be zero or a register .


<s> static void mmix_file_end ( void ) { switch_to_section ( data_section ) ; } </s>


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForMemchr ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src , SDValue Char , SDValue Length , MachinePointerInfo SrcPtrInfo ) const { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: i32 , MVT :: Other ) ; Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , MVT :: i32 ) ; Char = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Char , DAG . getConstant ( 255 , DL , MVT :: i32 ) ) ; SDValue Limit = DAG . getNode ( ISD :: ADD , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( SystemZISD :: SEARCH_STRING , DL , VTs , Chain , Limit , Src , Char ) ; SDValue CCReg = End . getValue ( 1 ) ; Chain = End . getValue ( 2 ) ; SDValue Ops [ ] = { End , DAG . getConstant ( 0 , DL , PtrVT ) , DAG . getTargetConstant ( SystemZ :: CCMASK_SRST , DL , MVT :: i32 ) , DAG . getTargetConstant ( SystemZ :: CCMASK_SRST_FOUND , DL , MVT :: i32 ) , CCReg } ; End = DAG . getNode ( SystemZISD :: SELECT_CCMASK , DL , PtrVT , Ops ) ; return std :: make_pair ( End , Chain ) ; } </s>

Emit target-specific code that performs a memchr , in cases where that is faster than a libcall .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && Subtarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } else if ( Constraint == "wa" || Constraint == "wd" || Constraint == "wf" ) { return std :: make_pair ( 0U , & PPC :: VSRCRegClass ) ; } else if ( Constraint == "ws" ) { return std :: make_pair ( 0U , & PPC :: VSFRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && Subtarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> virtual const OpenRISCSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Retpoline Thunks"
;
}
</s>


<s> bool mips_legitimize_address ( rtx * xloc , enum machine_mode mode ) { enum mips_symbol_type symbol_type ; if ( mips_tls_operand_p ( * xloc ) ) { * xloc = mips_legitimize_tls_address ( * xloc ) ; return true ; } if ( mips_symbolic_constant_p ( * xloc , & symbol_type ) && mips_symbolic_address_p ( symbol_type , mode ) && mips_split_p [ symbol_type ] ) { * xloc = mips_split_symbol ( 0 , * xloc ) ; return true ; } if ( GET_CODE ( * xloc ) == PLUS && GET_CODE ( XEXP ( * xloc , 1 ) ) == CONST_INT ) { rtx reg ; reg = XEXP ( * xloc , 0 ) ; if ( ! mips_valid_base_register_p ( reg , mode , 0 ) ) reg = copy_to_mode_reg ( Pmode , reg ) ; * xloc = mips_add_offset ( 0 , reg , INTVAL ( XEXP ( * xloc , 1 ) ) ) ; return true ; } return false ; } </s>

This function is used to implement LEGITIMIZE_ADDRESS . If * XLOC can be legitimized in a way that the generic machinery might not expect , put the new address in * XLOC and return true . MODE is the mode of the memory being accessed .


<s> bool ARMBaseRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { return ! getReservedRegs ( MF ) . test ( PhysReg ) ; } </s>

Returns false if we ca n't guarantee that Physreg , specified as an IR asm clobber constraint , will be preserved across the statement .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getX86TargetMachine ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSNaCl ( ) && Triple ( TM -> getTargetTriple ( ) ) . isArch64Bit ( ) && NaClDontBreakABI ) { addPass ( createClearPtrToIntTop32Pass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'L'
:
O
<<
getDataLayout
(
)
.
getPointerSize
(
)
<<
"("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
case
'y'
:
O
<<
"0, "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'I'
:
if
(
MI
->
getOperand
(
OpNo
)
.
isImm
(
)
)
O
<<
"i"
;
return
false
;
case
'U'
:
case
'X'
:
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> InstructionCost getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst = nullptr ) { return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return ( STI . isTargetIOS ( ) ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
const
MCPhysReg
*
X86RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
const
X86Subtarget
&
Subtarget
=
MF
->
getSubtarget
<
X86Subtarget
>
(
)
;
bool
HasSSE
=
Subtarget
.
hasSSE1
(
)
;
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
bool
HasAVX512
=
Subtarget
.
hasAVX512
(
)
;
bool
CallsEHReturn
=
MF
->
getMMI
(
)
.
callsEHReturn
(
)
;
assert
(
MF
&&
"MachineFunction required"
)
;
switch
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
)
{
case
CallingConv
::
GHC
:
case
CallingConv
::
HiPE
:
return
CSR_NoRegs_SaveList
;
case
CallingConv
::
AnyReg
:
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
return
CSR_64_AllRegs_SaveList
;
case
CallingConv
::
PreserveMost
:
return
CSR_64_RT_MostRegs_SaveList
;
case
CallingConv
::
PreserveAll
:
if
(
HasAVX
)
return
CSR_64_RT_AllRegs_AVX_SaveList
;
return
CSR_64_RT_AllRegs_SaveList
;
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Is64Bit
)
return
CSR_64_TLS_Darwin_SaveList
;
break
;
case
CallingConv
::
Intel_OCL_BI
:
{
if
(
HasAVX512
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX512
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX512_SaveList
;
if
(
HasAVX
&&
IsWin64
)
return
CSR_Win64_Intel_OCL_BI_AVX_SaveList
;
if
(
HasAVX
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_AVX_SaveList
;
if
(
!
HasAVX
&&
!
IsWin64
&&
Is64Bit
)
return
CSR_64_Intel_OCL_BI_SaveList
;
break
;
}
case
CallingConv
::
HHVM
:
return
CSR_64_HHVM_SaveList
;
case
CallingConv
::
Cold
:
if
(
Is64Bit
)
return
CSR_64_MostRegs_SaveList
;
break
;
case
CallingConv
::
X86_64_Win64
:
return
CSR_Win64_SaveList
;
case
CallingConv
::
X86_64_SysV
:
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
case
CallingConv
::
X86_INTR
:
if
(
Is64Bit
)
{
if
(
HasAVX
)
return
CSR_64_AllRegs_AVX_SaveList
;
else
return
CSR_64_AllRegs_SaveList
;
}
else
{
if
(
HasSSE
)
return
CSR_32_AllRegs_SSE_SaveList
;
else
return
CSR_32_AllRegs_SaveList
;
}
default
:
break
;
}
if
(
Is64Bit
)
{
if
(
IsWin64
)
return
CSR_Win64_SaveList
;
if
(
CallsEHReturn
)
return
CSR_64EHRet_SaveList
;
return
CSR_64_SaveList
;
}
if
(
CallsEHReturn
)
return
CSR_32EHRet_SaveList
;
return
CSR_32_SaveList
;
}
</s>


<s> static void rs6000_destroy_cost_data ( void * data ) { free ( data ) ; } </s>


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { SmallVector < const MachineMemOperand * , 1 > Accesses ; if ( MI . mayLoad ( ) && hasLoadFromStackSlot ( MI , Accesses ) && Accesses . size ( ) == 1 ) { FrameIndex = cast < FixedStackPseudoSourceValue > ( Accesses . front ( ) -> getPseudoValue ( ) ) -> getFrameIndex ( ) ; return true ; } return false ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> MVT PPCTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( Subtarget . hasSPE ( ) && VT == MVT :: f64 ) return MVT :: i32 ; return PPCTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool ARMBaseRegisterInfo :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo & TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; static const uint16_t CallerSavedRegs32Bit [ ] = { X86 :: EAX , X86 :: EDX , X86 :: ECX , 0 } ; static const uint16_t CallerSavedRegs64Bit [ ] = { X86 :: RAX , X86 :: RDX , X86 :: RCX , X86 :: RSI , X86 :: RDI , X86 :: R8 , X86 :: R9 , X86 :: R10 , X86 :: R11 , 0 } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETI : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( const uint16_t * AsI = TRI . getOverlaps ( Reg ) ; * AsI ; ++ AsI ) Uses . insert ( * AsI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> bool X86TargetMachine :: addPostRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
bool
Is64Bit
=
MBB
.
getParent
(
)
->
getSubtarget
<
PPCSubtarget
>
(
)
.
isPPC64
(
)
;
for
(
MachineBasicBlock
::
iterator
I
=
MBB
.
begin
(
)
,
IE
=
MBB
.
end
(
)
;
I
!=
IE
;
)
{
MachineInstr
&
MI
=
*
I
;
if
(
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsgdLADDR32
&&
MI
.
getOpcode
(
)
!=
PPC
::
ADDItlsldLADDR32
)
{
++
I
;
continue
;
}
DEBUG
(
dbgs
(
)
<<
"TLS Dynamic Call Fixup:\n    "
<<
MI
)
;
unsigned
OutReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
unsigned
InReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
GPR3
=
Is64Bit
PPC
::
X3
:
PPC
::
R3
;
unsigned
Opc1
,
Opc2
;
const
unsigned
OrigRegs
[
]
=
{
OutReg
,
InReg
,
GPR3
}
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode inconsistency error"
)
;
case
PPC
::
ADDItlsgdLADDR
:
Opc1
=
PPC
::
ADDItlsgdL
;
Opc2
=
PPC
::
GETtlsADDR
;
break
;
case
PPC
::
ADDItlsldLADDR
:
Opc1
=
PPC
::
ADDItlsldL
;
Opc2
=
PPC
::
GETtlsldADDR
;
break
;
case
PPC
::
ADDItlsgdLADDR32
:
Opc1
=
PPC
::
ADDItlsgdL32
;
Opc2
=
PPC
::
GETtlsADDR32
;
break
;
case
PPC
::
ADDItlsldLADDR32
:
Opc1
=
PPC
::
ADDItlsldL32
;
Opc2
=
PPC
::
GETtlsldADDR32
;
break
;
}
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKDOWN
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
MachineInstr
*
Addi
=
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc1
)
,
GPR3
)
.
addReg
(
InReg
)
;
Addi
->
addOperand
(
MI
.
getOperand
(
2
)
)
;
MachineBasicBlock
::
iterator
First
=
I
;
First
;
MachineInstr
*
Call
=
(
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Opc2
)
,
GPR3
)
.
addReg
(
GPR3
)
)
;
Call
->
addOperand
(
MI
.
getOperand
(
3
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
PPC
::
ADJCALLSTACKUP
)
)
.
addImm
(
0
)
.
addImm
(
0
)
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
OutReg
)
.
addReg
(
GPR3
)
;
MachineBasicBlock
::
iterator
Last
=
I
;
Last
;
++
I
;
MI
.
removeFromParent
(
)
;
LIS
->
repairIntervalsInRange
(
&
MBB
,
First
,
Last
,
OrigRegs
)
;
Changed
=
true
;
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> bool ARMBaseRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , unsigned PhysReg ) const { return ! getReservedRegs ( MF ) . test ( PhysReg ) ; } </s>


<s> Optional < uint64_t > X86MCInstrAnalysis :: evaluateMemoryOperandAddress ( const MCInst & Inst , const MCSubtargetInfo * STI , uint64_t Addr , uint64_t Size ) const { const MCInstrDesc & MCID = Info -> get ( Inst . getOpcode ( ) ) ; int MemOpStart = X86II :: getMemoryOperandNo ( MCID . TSFlags ) ; if ( MemOpStart == - 1 ) return None ; MemOpStart += X86II :: getOperandBias ( MCID ) ; const MCOperand & SegReg = Inst . getOperand ( MemOpStart + X86 :: AddrSegmentReg ) ; const MCOperand & BaseReg = Inst . getOperand ( MemOpStart + X86 :: AddrBaseReg ) ; const MCOperand & IndexReg = Inst . getOperand ( MemOpStart + X86 :: AddrIndexReg ) ; const MCOperand & ScaleAmt = Inst . getOperand ( MemOpStart + X86 :: AddrScaleAmt ) ; const MCOperand & Disp = Inst . getOperand ( MemOpStart + X86 :: AddrDisp ) ; if ( SegReg . getReg ( ) != 0 || IndexReg . getReg ( ) != 0 || ScaleAmt . getImm ( ) != 1 || ! Disp . isImm ( ) ) return None ; if ( BaseReg . getReg ( ) == X86 :: RIP ) return Addr + Size + Disp . getImm ( ) ; return None ; } </s>

Given an instruction tries to get the address of a memory operand .


<s> static bool mmix_rtx_costs ( rtx x ATTRIBUTE_UNUSED , int code ATTRIBUTE_UNUSED , int outer_code ATTRIBUTE_UNUSED , int * total ATTRIBUTE_UNUSED ) { return false ; } </s>


<s>
void
AArch64AppleInstPrinter
::
printInst
(
const
MCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
StringRef
Layout
,
Mnemonic
;
bool
IsTbx
;
if
(
isTblTbxInstruction
(
MI
->
getOpcode
(
)
,
Layout
,
IsTbx
)
)
{
O
<<
"\t"
<<
(
IsTbx
"tbx"
:
"tbl"
)
<<
Layout
<<
'\t'
<<
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
,
AArch64
::
vreg
)
<<
", "
;
unsigned
ListOpNum
=
IsTbx
2
:
1
;
printVectorList
(
MI
,
ListOpNum
,
STI
,
O
,
""
)
;
O
<<
", "
<<
getRegisterName
(
MI
->
getOperand
(
ListOpNum
+
1
)
.
getReg
(
)
,
AArch64
::
vreg
)
;
printAnnotation
(
O
,
Annot
)
;
return
;
}
if
(
LdStNInstrDesc
*
LdStDesc
=
getLdStNInstrDesc
(
Opcode
)
)
{
O
<<
"\t"
<<
LdStDesc
->
Mnemonic
<<
LdStDesc
->
Layout
<<
'\t'
;
int
OpNum
=
LdStDesc
->
ListOperand
;
printVectorList
(
MI
,
OpNum
++
,
STI
,
O
,
""
)
;
if
(
LdStDesc
->
HasLane
)
O
<<
'['
<<
MI
->
getOperand
(
OpNum
++
)
.
getImm
(
)
<<
']'
;
unsigned
AddrReg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
O
<<
", ["
<<
getRegisterName
(
AddrReg
)
<<
']'
;
if
(
LdStDesc
->
NaturalOffset
!=
0
)
{
unsigned
Reg
=
MI
->
getOperand
(
OpNum
++
)
.
getReg
(
)
;
if
(
Reg
!=
AArch64
::
XZR
)
O
<<
", "
<<
getRegisterName
(
Reg
)
;
else
{
assert
(
LdStDesc
->
NaturalOffset
&&
"no offset on post-inc instruction?"
)
;
O
<<
", #"
<<
LdStDesc
->
NaturalOffset
;
}
}
printAnnotation
(
O
,
Annot
)
;
return
;
}
AArch64InstPrinter
::
printInst
(
MI
,
O
,
Annot
,
STI
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> int arm_no_early_mul_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , 0 , 0 ) ; op = XEXP ( op , 1 ) ; return ( GET_CODE ( op ) == PLUS && ! reg_overlap_mentioned_p ( value , XEXP ( op , 0 ) ) ) ; } </s>

Return nonzero if the CONSUMER ( a mul or mac op ) does not have an early register mult dependency on the result of PRODUCER .


<s> void TeeRISCFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TeeRISCInstrInfo & TII = * static_cast < const TeeRISCInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TeeRISCMachineFunctionInfo * TFI = MF . getInfo < TeeRISCMachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; determineFrameLayout ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; int FPOffset = TFI -> getFPStackOffset ( ) ; int RAOffset = TFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TeeRISC :: ADD_IMM ) , TeeRISC :: SP ) . addReg ( TeeRISC :: SP ) . addImm ( StackSize ) ; if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( TeeRISC :: ST ) , TeeRISC :: SP ) . addReg ( TeeRISC :: LR ) . addImm ( RAOffset ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( TeeRISC :: ST ) , TeeRISC :: FP ) . addReg ( TeeRISC :: SP ) . addImm ( FPOffset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( TeeRISC :: ADD ) , TeeRISC :: FP ) . addReg ( TeeRISC :: SP ) . addReg ( TeeRISC :: ZERO ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC TeeRISC 0 TeeRISC::ADD_IMM TeeRISC::SP TeeRISC::SP TeeRISC::ST TeeRISC::SP TeeRISC::LR TeeRISC::ST TeeRISC::FP TeeRISC::SP TeeRISC::ADD TeeRISC::FP TeeRISC::SP TeeRISC::ZERO


<s> bool mips_dangerous_for_la25_p ( rtx x ) { HOST_WIDE_INT offset ; if ( TARGET_EXPLICIT_RELOCS ) return false ; mips_split_const ( x , & x , & offset ) ; return global_got_operand ( x , VOIDmode ) ; } </s>

Return true if X should not be moved directly into register $ 25 . We need this because many versions of GAS will treat `` la $ 25 , foo '' as part of a call sequence and so allow a global `` foo '' to be lazily bound .


<s> static rtx ix86_copy_addr_to_reg ( rtx addr ) { rtx reg ; if ( GET_MODE ( addr ) == Pmode || GET_MODE ( addr ) == VOIDmode ) { reg = copy_addr_to_reg ( addr ) ; REG_POINTER ( reg ) = 1 ; return reg ; } else { gcc_assert ( GET_MODE ( addr ) == DImode && Pmode == SImode ) ; reg = copy_to_mode_reg ( DImode , addr ) ; REG_POINTER ( reg ) = 1 ; return gen_rtx_SUBREG ( SImode , reg , 0 ) ; } } </s>

Copy the address to a Pmode register . This is used for x32 to truncate DImode TLS address to a SImode register .


<s> VE :: Fixups getFixupKind ( ) const { return getFixupKind ( Kind ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "sinl" , "sqrtl" , "truncl" } ; const char * const * End = LibCalls + array_lengthof ( LibCalls ) ; MipsTargetLowering :: LTStr Comp ; for ( const char * const * I = LibCalls ; I < End - 1 ; ++ I ) assert ( Comp ( * I , * ( I + 1 ) ) ) ; return std :: binary_search ( LibCalls , End , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy , Align Alignment ) { if ( ! ST -> hasAVX ( ) ) return false ; if ( isa < VectorType > ( DataTy ) && cast < FixedVectorType > ( DataTy ) -> getNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 || ( ( IntWidth == 8 || IntWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s> bool PPCPassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> void sparc64_initialize_trampoline ( rtx tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( gen_rtx_MEM ( SImode , tramp ) , GEN_INT ( trunc_int_for_mode ( 0x83414000 , SImode ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 4 ) ) , GEN_INT ( trunc_int_for_mode ( 0xca586018 , SImode ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 8 ) ) , GEN_INT ( trunc_int_for_mode ( 0x81c14000 , SImode ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( tramp , 12 ) ) , GEN_INT ( trunc_int_for_mode ( 0xca586010 , SImode ) ) ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , 16 ) ) , cxt ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( tramp , 24 ) ) , fnaddr ) ; emit_insn ( gen_flushdi ( validize_mem ( gen_rtx_MEM ( DImode , tramp ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 ) emit_insn ( gen_flushdi ( validize_mem ( gen_rtx_MEM ( DImode , plus_constant ( tramp , 8 ) ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , tramp , Pmode ) ; } </s>

The 64 bit version is simpler because it makes more sense to load the values as `` immediate '' data out of the trampoline . It 's also easier since we can read the PC without clobbering a register .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> void buildLoad ( Register Val , const CCValAssign & VA ) { MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ; MIRBuilder . buildLoad ( Val , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .


<s> void sh_emit_compare_and_branch ( rtx * operands , machine_mode mode ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; enum rtx_code branch_code ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx insn ; bool need_ccmpeq = false ; if ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { op0 = force_reg ( mode , op0 ) ; op1 = force_reg ( mode , op1 ) ; } else { if ( code != EQ || mode == DImode ) { op0 = force_reg ( mode , op0 ) ; if ( op1 != const0_rtx || code == GTU || code == GEU ) op1 = force_reg ( mode , op1 ) ; } } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( code == LT || ( code == LE && TARGET_IEEE && TARGET_SH2E ) || ( code == GE && ! ( TARGET_IEEE && TARGET_SH2E ) ) ) { std :: swap ( op0 , op1 ) ; code = swap_condition ( code ) ; } if ( code == GE ) { gcc_assert ( TARGET_IEEE && TARGET_SH2E ) ; need_ccmpeq = true ; code = GT ; } gcc_assert ( code == EQ || code == GT || code == NE || code == LE ) ; } switch ( code ) { case EQ : case GT : case GE : case GTU : case GEU : branch_code = code ; break ; case NE : case LT : case LE : case LTU : case LEU : branch_code = reverse_condition ( code ) ; break ; default : gcc_unreachable ( ) ; } insn = gen_rtx_SET ( get_t_reg_rtx ( ) , gen_rtx_fmt_ee ( branch_code , SImode , op0 , op1 ) ) ; sh_emit_set_t_insn ( insn , mode ) ; if ( need_ccmpeq ) sh_emit_set_t_insn ( gen_ieee_ccmpeqsf_t ( op0 , op1 ) , mode ) ; if ( branch_code == code ) emit_jump_insn ( gen_branch_true ( operands [ 3 ] ) ) ; else emit_jump_insn ( gen_branch_false ( operands [ 3 ] ) ) ; } </s>

Called from the md file , set up the operands of a compare instruction .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == ".ltorg" || IDVal == ".pool" ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) return parseDirectiveInst ( Loc ) ; } return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool needAddressOf ( ) const { return AddressOf ; } </s>

needAddressOf - Do we need to emit code to get the address of the variable/label ? Only valid when parsing MS-style inline assembly .


<s> bool ix86_expand_pinsr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 3 ] ; unsigned int size = INTVAL ( operands [ 1 ] ) ; unsigned int pos = INTVAL ( operands [ 2 ] ) ; if ( SUBREG_P ( dst ) ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } switch ( GET_MODE ( dst ) ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V1TImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; rtx d ; if ( ! int_mode_for_size ( size , 0 ) . exists ( & srcmode ) ) return false ; switch ( srcmode ) { case E_QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case E_HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case E_SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case E_DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } if ( pos & ( size - 1 ) ) return false ; if ( SUBREG_P ( src ) ) { unsigned int srcpos = SUBREG_BYTE ( src ) ; if ( srcpos > 0 ) { rtx extr_ops [ 4 ] ; extr_ops [ 0 ] = gen_reg_rtx ( srcmode ) ; extr_ops [ 1 ] = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; extr_ops [ 2 ] = GEN_INT ( size ) ; extr_ops [ 3 ] = GEN_INT ( srcpos * BITS_PER_UNIT ) ; if ( ! ix86_expand_pextr ( extr_ops ) ) return false ; src = extr_ops [ 0 ] ; } else src = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; } if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; emit_insn ( pinsr ( d , gen_lowpart ( dstmode , dst ) , gen_lowpart ( srcmode , src ) , GEN_INT ( 1 << ( pos / size ) ) ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an insert into a vector register through pinsr insn . Return true if successful .


<s> bool addPreISel ( ) override { return false ; } </s>


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void push_regs ( unsigned int high , unsigned int low ) { rtx insn ; if ( low == high ) insn = emit_insn ( gen_stack_push ( gen_rtx_REG ( SImode , low ) ) ) ; else insn = emit_insn ( gen_stack_pushm ( GEN_INT ( ( ( high - low ) + 1 ) * UNITS_PER_WORD ) , gen_rx_store_vector ( low , high ) ) ) ; mark_frame_related ( insn ) ; } </s>

Generate code to push the regs specified in the mask . remember that the mask is of the internal shape of the regs , not the external shape - so go through the renumber vector


<s> int ARMBaseInstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const { if ( ! Node -> isMachineOpcode ( ) ) return 1 ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return 1 ; unsigned Opcode = Node -> getMachineOpcode ( ) ; switch ( Opcode ) { default : return ItinData -> getStageLatency ( get ( Opcode ) . getSchedClass ( ) ) ; case ARM :: VLDMQIA : case ARM :: VSTMQIA : return 2 ; } } </s>

Compute the instruction latency of a given instruction .


<s> bool PPCTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { if ( DisablePPCUnaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != MVT :: v2f64 && VT != MVT :: v2i64 && VT != MVT :: v4f32 && VT != MVT :: v4i32 ) return false ; } else { return false ; } } if ( VT == MVT :: ppcf128 ) return false ; if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getELFSection ( ".sdata" , MCSectionELF :: SHT_PROGBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getELFSection ( ".sbss" , MCSectionELF :: SHT_NOBITS , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> bool PPCAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; case 'L' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + 1 == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + 1 ) . isReg ( ) ) return true ; ++ OpNo ; break ; case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << "i" ; return false ; case 'x' : if ( ! MI -> getOperand ( OpNo ) . isReg ( ) ) return true ; unsigned Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; if ( PPCInstrInfo :: isVRRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: V0 ) ; else if ( PPCInstrInfo :: isVFRegister ( Reg ) ) Reg = PPC :: VSX32 + ( Reg - PPC :: VF0 ) ; const char * RegName ; RegName = PPCInstPrinter :: getRegisterName ( Reg ) ; RegName = PPCRegisterInfo :: stripRegisterPrefix ( RegName ) ; O << RegName ; return false ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> uint32_t ARMMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const ARMSubtarget & Subtarget = TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget . isThumb2 ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , ARM :: fixup_t2_branch , Fixups ) ; return :: getBranchTargetOpValue ( MI , OpIdx , ARM :: fixup_arm_branch , Fixups ) ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .

ARM ARM ARM ARM ARM::fixup_t2_branch ARM::fixup_arm_branch


<s> unsigned VETargetLowering :: getMinimumJumpTableEntries ( ) const { if ( isJumpTableRelative ( ) ) return 8 ; return TargetLowering :: getMinimumJumpTableEntries ( ) ; } </s>


<s> rtx create_TOC_reference ( rtx symbol ) { if ( no_new_pseudos ) regs_ever_live [ TOC_REGISTER ] = 1 ; return gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , TOC_REGISTER ) , gen_rtx_CONST ( Pmode , gen_rtx_MINUS ( Pmode , symbol , gen_rtx_SYMBOL_REF ( Pmode , toc_label_name ) ) ) ) ; } </s>

Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> void iq2000_expand_epilogue ( void ) { HOST_WIDE_INT tsize = cfun -> machine -> total_size ; rtx tsize_rtx = GEN_INT ( tsize ) ; rtx tmp_rtx = ( rtx ) 0 ; if ( iq2000_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } if ( tsize > 32767 ) { tmp_rtx = gen_rtx_REG ( Pmode , IQ2000_TEMP1_REGNUM ) ; emit_move_insn ( tmp_rtx , tsize_rtx ) ; tsize_rtx = tmp_rtx ; } if ( tsize > 0 ) { if ( frame_pointer_needed ) { emit_insn ( gen_blockage ( ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } save_restore_insns ( 0 ) ; if ( current_function_calls_eh_return ) { rtx eh_ofs = EH_RETURN_STACKADJ_RTX ; emit_insn ( gen_addsi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; tsize_rtx = eh_ofs ; } emit_insn ( gen_blockage ( ) ) ; if ( tsize != 0 || current_function_calls_eh_return ) { emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; } } if ( current_function_calls_eh_return ) { emit_move_insn ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) , stack_pointer_rtx ) ; emit_insn ( gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ) ) ; emit_jump_insn ( gen_eh_return_internal ( ) ) ; } else emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + 31 ) ) ) ; } </s>

Expand the epilogue into a bunch of separate insns .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr & MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; SmallVector < unsigned , 1 > SrcOperandIds ; for ( unsigned i = 0 , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) ) return nullptr ; SrcOperandIds . push_back ( i ) ; } if ( SrcOperandIds . empty ( ) ) return nullptr ; if ( MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandIds , * DefMI ) ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> void AnalyzeReturn ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( Outs ) ; CCState :: AnalyzeReturn ( Outs , Fn ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeReturn - Analyze the returned values of a return , incorporating info about the result values into this state .


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_WIDE_INT : { int i ; flen = CONST_WIDE_INT_NUNITS ( k ) ; for ( i = 0 ; i < flen ; i ++ ) result = result * 613 + CONST_WIDE_INT_ELT ( k , i ) ; return result ; } case CONST_DOUBLE : if ( mode != VOIDmode ) return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; flen = 2 ; break ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( isLoad && usePartialVectorLoads ( N ) ) { return false ; } if ( VT . isVector ( ) ) { if ( ! Subtarget . hasQPX ( ) || ( VT != MVT :: v4f64 && VT != MVT :: v4f32 ) ) { return false ; } else if ( SelectAddressRegRegOnly ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } } if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 0 ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , 4 ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> void SparcTargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( ! Subtarget -> isTargetLinux ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s>
TargetLowering
::
AtomicExpansionKind
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
->
is64Bit
(
)
64
:
32
;
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
{
return
needsCmpXchgNb
(
MemType
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
}
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
AtomicExpansionKind
::
CmpXChg
:
AtomicExpansionKind
::
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
AtomicExpansionKind
::
CmpXChg
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static machine_mode zero_call_used_regno_mode ( const unsigned int regno ) { if ( GENERAL_REGNO_P ( regno ) ) return SImode ; else if ( SSE_REGNO_P ( regno ) ) return V4SFmode ; else if ( MASK_REGNO_P ( regno ) ) return HImode ; else if ( MMX_REGNO_P ( regno ) ) return V2SImode ; else gcc_unreachable ( ) ; } </s>

Return the machine_mode that is used to zero register REGNO .


<s> static void aarch64_add_cfa_expression ( rtx_insn * insn , unsigned int reg , rtx base , poly_int64 offset ) { rtx mem = gen_frame_mem ( DImode , plus_constant ( Pmode , base , offset ) ) ; add_reg_note ( insn , REG_CFA_EXPRESSION , gen_rtx_SET ( mem , regno_reg_rtx [ reg ] ) ) ; } </s>

Add a REG_CFA_EXPRESSION note to INSN to say that register REG is saved at BASE + OFFSET .


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s>
AArch64TargetLowering
::
ConstraintType
AArch64TargetLowering
::
getConstraintType
(
const
std
::
string
&
Constraint
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
default
:
break
;
case
'w'
:
return
C_RegisterClass
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'Y'
:
case
'Z'
:
return
C_Other
;
case
'Q'
:
return
C_Memory
;
case
'S'
:
return
C_Other
;
}
}
assert
(
Constraint
!=
"Ump"
&&
Constraint
!=
"Utf"
&&
Constraint
!=
"Usa"
&&
Constraint
!=
"Ush"
&&
"Unimplemented constraints"
)
;
return
TargetLowering
::
getConstraintType
(
Constraint
)
;
}
</s>

Given a constraint letter , return the type of constraint for this target .


<s> int moxie_initial_elimination_offset ( int from , int to ) { int ret ; if ( ( from ) == FRAME_POINTER_REGNUM && ( to ) == HARD_FRAME_POINTER_REGNUM ) { moxie_compute_frame ( ) ; ret = - cfun -> machine -> callee_saved_reg_size ; } else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == HARD_FRAME_POINTER_REGNUM ) ret = 0x00 ; else abort ( ) ; return ret ; } </s>

Implements the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s> static void restore_saved_cr ( rtx reg , int using_mfcr_multiple , bool exit_func ) { int count = 0 ; int i ; if ( using_mfcr_multiple ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) count ++ ; gcc_assert ( count ) ; } if ( using_mfcr_multiple && count > 1 ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = reg ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } else for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; add_reg_note ( insn , REG_CFA_RESTORE , cr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { MIB . addUse ( PhysReg , RegState :: Implicit ) ; Register ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


"OffsetRegShifted must imply OffsetIsReg!"

"Offset must exists unless register offset is used!"

"Cannot have shift amount without shifted register offset!"

"Cannot have expression offset and register offset!"


<s> virtual void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void output_deferred_profile_counters ( void ) { unsigned int i ; int align , n ; if ( funcdef_nos . is_empty ( ) ) return ; switch_to_section ( data_section ) ; align = MIN ( BIGGEST_ALIGNMENT , LONG_TYPE_SIZE ) ; ASM_OUTPUT_ALIGN ( asm_out_file , floor_log2 ( align / BITS_PER_UNIT ) ) ; for ( i = 0 ; funcdef_nos . iterate ( i , & n ) ; i ++ ) { targetm . asm_out . internal_label ( asm_out_file , "LP" , n ) ; assemble_integer ( const0_rtx , LONG_TYPE_SIZE / BITS_PER_UNIT , align , 1 ) ; } funcdef_nos . release ( ) ; } </s>


<s> static bool mep_repeat_loop_p ( struct mep_doloop * loop ) { struct mep_doloop_end * end ; rtx fallthrough ; if ( loop -> begin == 0 || loop -> end == 0 || loop -> begin -> next != 0 ) return false ; if ( prev_real_insn ( loop -> end -> label ) != loop -> begin -> insn ) return false ; fallthrough = loop -> end -> fallthrough ; for ( end = loop -> end -> next ; end != 0 ; end = end -> next ) if ( end -> label != loop -> end -> label || ! simplejump_p ( end -> fallthrough ) || next_real_insn ( JUMP_LABEL ( end -> fallthrough ) ) != fallthrough ) return false ; return true ; } </s>

Return true if LOOP can be converted into repeat/repeat_end form ( that is , if it matches cases ( 1 ) or ( 2 ) above ) .


"converted opcode should be the same except for cc_out"

"expect uninitialized optional cc_out operand"

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> static bool csky_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 2 * UNITS_PER_WORD ) ; } </s>

Implement TARGET_RETURN_IN_MEMORY to decide whether TYPE should be returned in memory ( true ) or in a register ( false ) . FNTYPE is the type of the function making the call .


"getBranchTarget21OpValue expects only expressions or immediates"

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


<s>
Register
PPCTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
bool
isPPC64
=
Subtarget
.
isPPC64
(
)
;
bool
IsDarwinABI
=
Subtarget
.
isDarwinABI
(
)
;
if
(
(
isPPC64
&&
VT
!=
MVT
::
i64
&&
VT
!=
MVT
::
i32
)
||
(
!
isPPC64
&&
VT
!=
MVT
::
i32
)
)
report_fatal_error
(
"Invalid register global variable type"
)
;
bool
is64Bit
=
isPPC64
&&
VT
==
MVT
::
i64
;
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"r1"
,
is64Bit
PPC
::
X1
:
PPC
::
R1
)
.
Case
(
"r2"
,
(
IsDarwinABI
||
isPPC64
)
Register
(
)
:
PPC
::
R2
)
.
Case
(
"r13"
,
(
!
isPPC64
&&
IsDarwinABI
)
Register
(
)
:
(
is64Bit
PPC
::
X13
:
PPC
::
R13
)
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) op = XEXP ( op , 1 ) ; else if ( strict ) return false ; } tocrel_base = op ; tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM Assembly / Object Emitter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"VE Assembly Printer"
;
}
</s>


<s>
bool
AArch64MIPeepholeOpt
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
static_cast
<
const
AArch64RegisterInfo
*
>
(
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
assert
(
MRI
->
isSSA
(
)
&&
"Expected to be run on SSA form!"
)
;
bool
Changed
=
false
;
SmallSetVector
<
MachineInstr
*
,
8
>
ToBeRemoved
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
ANDWrr
:
Changed
=
visitAND
<
uint32_t
>
(
AArch64
::
ANDWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ANDXrr
:
Changed
=
visitAND
<
uint64_t
>
(
AArch64
::
ANDXri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ORRWrs
:
Changed
=
visitORR
(
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDWrr
:
Changed
=
visitADDSUB
<
uint32_t
>
(
AArch64
::
ADDWri
,
AArch64
::
SUBWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBWrr
:
Changed
=
visitADDSUB
<
uint32_t
>
(
AArch64
::
SUBWri
,
AArch64
::
ADDWri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
ADDXrr
:
Changed
=
visitADDSUB
<
uint64_t
>
(
AArch64
::
ADDXri
,
AArch64
::
SUBXri
,
MI
,
ToBeRemoved
)
;
break
;
case
AArch64
::
SUBXrr
:
Changed
=
visitADDSUB
<
uint64_t
>
(
AArch64
::
SUBXri
,
AArch64
::
ADDXri
,
MI
,
ToBeRemoved
)
;
break
;
}
}
}
for
(
MachineInstr
*
MI
:
ToBeRemoved
)
MI
->
eraseFromParent
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool X86PassConfig :: addInstSelector ( ) { addPass ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( getX86Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; addPass ( createX86GlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
void
assignValueToAddress
(
Register
ValVReg
,
Register
Addr
,
uint64_t
Size
,
MachinePointerInfo
&
MPO
,
CCValAssign
&
VA
)
override
{
assert
(
(
Size
==
1
||
Size
==
2
||
Size
==
4
||
Size
==
8
)
&&
"Unsupported size"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
||
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
{
Size
=
4
;
assert
(
MRI
.
getType
(
ValVReg
)
.
isScalar
(
)
&&
"Only scalars supported atm"
)
;
auto
LoadVReg
=
buildLoad
(
LLT
::
scalar
(
32
)
,
Addr
,
Size
,
MPO
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
LoadVReg
)
;
}
else
{
buildLoad
(
ValVReg
,
Addr
,
Size
,
MPO
)
;
}
}
</s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) ) return new ARMFastISel ( funcInfo , libInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> static int nds32_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == HIGH_REGS || to == HIGH_REGS ) return 6 ; return 2 ; } </s>

Describing Relative Costs of Operations .


<s> int ix86_data_alignment ( tree type , int align ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= 256 || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < 256 ) return 256 ; if ( TARGET_64BIT ) { if ( AGGREGATE_TYPE_P ( type ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) >= 128 || TREE_INT_CST_HIGH ( TYPE_SIZE ( type ) ) ) && align < 128 ) return 128 ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < 64 ) return 64 ; if ( TYPE_MODE ( type ) == XCmode && align < 128 ) return 128 ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < 128 ) return 128 ; } else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) { if ( TYPE_MODE ( type ) == DFmode && align < 64 ) return 64 ; if ( ALIGN_MODE_128 ( TYPE_MODE ( type ) ) && align < 128 ) return 128 ; } return align ; } </s>

Compute the alignment for a static variable . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex , LiveIntervals * LIS ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .