<s> void VEInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & OS ) { if ( ! printAliasInstr ( MI , Address , STI , OS ) ) printInstruction ( MI , Address , STI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
static
rtx
pru_expand_builtin
(
tree
exp
,
rtx
target
,
rtx
subtarget
ATTRIBUTE_UNUSED
,
machine_mode
mode
,
int
ignore
ATTRIBUTE_UNUSED
)
{
tree
fndecl
=
TREE_OPERAND
(
CALL_EXPR_FN
(
exp
)
,
0
)
;
unsigned
int
fcode
=
DECL_MD_FUNCTION_CODE
(
fndecl
)
;
switch
(
fcode
)
{
case
PRU_BUILTIN_DELAY_CYCLES
:
{
rtx
arg1
=
expand_normal
(
CALL_EXPR_ARG
(
exp
,
0
)
)
;
return
pru_expand_delay_cycles
(
arg1
)
;
}
break
;
case
PRU_BUILTIN_HALT
:
{
emit_insn
(
gen_pru_halt
(
)
)
;
return
NULL_RTX
;
}
break
;
case
PRU_BUILTIN_LMBD
:
{
rtx
arg1
=
expand_normal
(
CALL_EXPR_ARG
(
exp
,
0
)
)
;
rtx
arg2
=
expand_normal
(
CALL_EXPR_ARG
(
exp
,
1
)
)
;
if
(
target
==
NULL_RTX
||
GET_MODE
(
target
)
!=
mode
)
{
target
=
gen_reg_rtx
(
mode
)
;
}
emit_insn
(
gen_pru_lmbd
(
mode
,
target
,
arg1
,
arg2
)
)
;
return
target
;
}
break
;
default
:
internal_error
(
"bad builtin code"
)
;
}
return
NULL_RTX
;
}
</s>

Implement TARGET_EXPAND_BUILTIN . Expand an expression EXP that calls a built-in function , with result going to TARGET if that 's convenient ( and in mode MODE if that 's convenient ) . SUBTARGET may be used as the target for computing one of EXP 's operands . IGNORE is nonzero if the value is to be ignored .


<s>
const
char
*
getPassName
(
)
const
{
return
"DCPU16 optimize conditional branches"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , IsO32 , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , getTargetMachine ( ) . Options . UseSoftFloat , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> EVT AArch64TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < VESubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> void createdInstr ( MachineInstr & MI ) override { InstList . insert ( & MI ) ; } </s>

An instruction has been created and inserted into the function .


<s> bool sh_legitimize_reload_address ( rtx * p , machine_mode mode , int opnum , int itype ) { enum reload_type type = ( enum reload_type ) itype ; const int mode_sz = GET_MODE_SIZE ( mode ) ; if ( sh_lra_p ( ) ) return false ; if ( GET_CODE ( * p ) == PLUS && CONST_INT_P ( XEXP ( * p , 1 ) ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( * p , 0 ) , true ) ) { const HOST_WIDE_INT offset = INTVAL ( XEXP ( * p , 1 ) ) ; struct disp_adjust adj = sh_find_mov_disp_adjust ( mode , offset ) ; if ( TARGET_SH2A && mode == DFmode && ( offset & 0x7 ) ) { push_reload ( * p , NULL_RTX , p , NULL , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , type ) ; return true ; } if ( TARGET_SH2E && mode == SFmode ) { * p = copy_rtx ( * p ) ; push_reload ( * p , NULL_RTX , p , NULL , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , type ) ; return true ; } if ( ( mode_sz == 4 || mode_sz == 8 ) && ! ( TARGET_SH4 && mode == DFmode ) && adj . offset_adjust != NULL_RTX && adj . mov_disp != NULL_RTX ) { rtx sum = gen_rtx_PLUS ( Pmode , XEXP ( * p , 0 ) , adj . offset_adjust ) ; * p = gen_rtx_PLUS ( Pmode , sum , adj . mov_disp ) ; push_reload ( sum , NULL_RTX , & XEXP ( * p , 0 ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , type ) ; return true ; } } if ( GET_CODE ( * p ) == PLUS && ( mode_sz == 4 || mode_sz == 8 ) && GET_CODE ( XEXP ( * p , 0 ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( * p , 0 ) , 1 ) ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( XEXP ( * p , 0 ) , 0 ) , true ) && CONST_INT_P ( XEXP ( * p , 1 ) ) && ! ( TARGET_SH2E && mode == SFmode ) ) { push_reload ( XEXP ( * p , 0 ) , NULL_RTX , & XEXP ( * p , 0 ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , type ) ; return true ; } return false ; } </s>

Attempt to replace * p , which is an address that needs reloading , with a valid memory address for an operand of mode MODE . Like for sh_legitimize_address , for the SH we try to get a normal form of the address . That will allow inheritance of the address reloads .


<s> static rtx pa_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { if ( ! TARGET_SOFT_FLOAT && ( mode == SFmode || mode == DFmode ) ) return gen_rtx_REG ( mode , 32 ) ; else return gen_rtx_REG ( mode , 28 ) ; } </s>

Implement the TARGET_LIBCALL_VALUE hook .


<s> unsigned CAHPInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return 0 ; if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) && ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 0 ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return 1 ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return 1 ; I -> eraseFromParent ( ) ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; return 2 ; } </s>

Remove the branching code at the end of the specific MBB .


<s>
unsigned
SHUXIInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
SHUXI
::
JMP
&&
I
->
getOpcode
(
)
!=
SHUXI
::
JCC
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

SHUXI
SHUXI
"code size not handled"
0
SHUXI::JMP
SHUXI::JCC


<s>
LLVM_DUMP_METHOD
void
ARMConstantPoolValue
::
dump
(
)
const
{
errs
(
)
<<
"  "
<<
*
this
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> static void vax_init_libfuncs ( void ) { set_optab_libfunc ( udiv_optab , SImode , TARGET_ELF ? "*__udiv" : "*udiv" ) ; set_optab_libfunc ( umod_optab , SImode , TARGET_ELF ? "*__urem" : "*urem" ) ; } </s>

We can use the BSD C library routines for the libgcc calls that are still generated , since that 's what they boil down to anyways . When ELF , avoid the user 's namespace .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; PPCSubTarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = PPCSubTarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>


<s> int nds32_can_use_return_insn ( void ) { int sp_adjust ; if ( ! reload_completed ) return 0 ; if ( cfun -> machine -> attr_naked_p && ! flag_ret_in_naked_func ) return 0 ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return 1 ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == 0 ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool ix86_expand_pinsr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 3 ] ; unsigned int size = INTVAL ( operands [ 1 ] ) ; unsigned int pos = INTVAL ( operands [ 2 ] ) ; if ( SUBREG_P ( dst ) ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } switch ( GET_MODE ( dst ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : case V1TImode : case TImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; rtx d ; srcmode = mode_for_size ( size , MODE_INT , 0 ) ; switch ( srcmode ) { case QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } if ( pos & ( size - 1 ) ) return false ; if ( SUBREG_P ( src ) ) { unsigned int srcpos = SUBREG_BYTE ( src ) ; if ( srcpos > 0 ) { rtx extr_ops [ 4 ] ; extr_ops [ 0 ] = gen_reg_rtx ( srcmode ) ; extr_ops [ 1 ] = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; extr_ops [ 2 ] = GEN_INT ( size ) ; extr_ops [ 3 ] = GEN_INT ( srcpos * BITS_PER_UNIT ) ; if ( ! ix86_expand_pextr ( extr_ops ) ) return false ; src = extr_ops [ 0 ] ; } else src = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; } if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; emit_insn ( pinsr ( d , gen_lowpart ( dstmode , dst ) , gen_lowpart ( srcmode , src ) , GEN_INT ( 1 << ( pos / size ) ) ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an insert into a vector register through pinsr insn . Return true if successful .


<s> Register Cpu0RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( Cpu0 :: FP ) : ( Cpu0 :: SP ) ; } </s>


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilderBase & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> unsigned AArch64RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const AArch64FrameLowering * TFI = getFrameLowering ( MF ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case AArch64 :: GPR32RegClassID : case AArch64 :: GPR32spRegClassID : case AArch64 :: GPR32allRegClassID : case AArch64 :: GPR64spRegClassID : case AArch64 :: GPR64allRegClassID : case AArch64 :: GPR64RegClassID : case AArch64 :: GPR32commonRegClassID : case AArch64 :: GPR64commonRegClassID : return 32 - 1 - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < AArch64Subtarget > ( ) . isX18Reserved ( ) - MF . getSubtarget < AArch64Subtarget > ( ) . isX20Reserved ( ) - hasBasePointer ( MF ) ; case AArch64 :: FPR8RegClassID : case AArch64 :: FPR16RegClassID : case AArch64 :: FPR32RegClassID : case AArch64 :: FPR64RegClassID : case AArch64 :: FPR128RegClassID : return 32 ; case AArch64 :: DDRegClassID : case AArch64 :: DDDRegClassID : case AArch64 :: DDDDRegClassID : case AArch64 :: QQRegClassID : case AArch64 :: QQQRegClassID : case AArch64 :: QQQQRegClassID : return 32 ; case AArch64 :: FPR128_loRegClassID : return 16 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } if ( getARMSubtarget ( ) . useConstIslands ( ) ) addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static enum sched_fusion_type fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset ) { rtx x , dest , src ; enum sched_fusion_type fusion = SCHED_FUSION_LD ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; if ( GET_MODE ( dest ) != SImode && GET_MODE ( dest ) != DImode && GET_MODE ( dest ) != SFmode && GET_MODE ( dest ) != DFmode ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , 0 ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return fusion ; } </s>

If INSN is a load or store of address in the form of [ base+offset ] , extract the two parts and set to BASE and OFFSET . IS_LOAD is set to TRUE if it 's a load . Return TRUE if INSN is such an instruction , otherwise return FALSE .


<s> const SICFrameLowering * SICFrameLowering :: create ( const SICSubtarget & ST ) { return new SICFrameLowering ( ST , ST . stackAlignment ( ) ) ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void arm_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , bool acq ) { rtx ( * gen ) ( rtx , rtx ) ; if ( acq ) { switch ( mode ) { case E_QImode : gen = gen_arm_load_acquire_exclusiveqi ; break ; case E_HImode : gen = gen_arm_load_acquire_exclusivehi ; break ; case E_SImode : gen = gen_arm_load_acquire_exclusivesi ; break ; case E_DImode : gen = gen_arm_load_acquire_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : gen = gen_arm_load_exclusiveqi ; break ; case E_HImode : gen = gen_arm_load_exclusivehi ; break ; case E_SImode : gen = gen_arm_load_exclusivesi ; break ; case E_DImode : gen = gen_arm_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen ( rval , mem ) ) ; } </s>

Emit the load-exclusive and store-exclusive instructions . Use acquire and release versions if necessary .


<s> static void mep_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { char flagchars [ 8 ] , * f = flagchars ; const char * type ; if ( ! ( flags & SECTION_DEBUG ) ) * f ++ = 'a' ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_SMALL ) * f ++ = 's' ; if ( flags & SECTION_MEP_VLIW ) * f ++ = 'v' ; * f = '\0' ; if ( flags & SECTION_BSS ) type = "nobits" ; else type = "progbits" ; fprintf ( asm_out_file , "\t.section\t%s,\"%s\",@%s\n" , name , flagchars , type ) ; if ( flags & SECTION_CODE ) fputs ( ( flags & SECTION_MEP_VLIW ? "\t.vliw\n" : "\t.core\n" ) , asm_out_file ) ; } </s>

Switch to an arbitrary section NAME with attributes as specified by FLAGS . ALIGN specifies any known alignment requirements for the section ; 0 if the default should be used . Differs from the standard ELF version only in support of VLIW mode .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { const MCInstrDesc & Desc = Info -> get ( Inst . getOpcode ( ) ) ; for ( unsigned OpNum = 0 ; OpNum < Desc . getNumOperands ( ) ; ++ OpNum ) { if ( Inst . getOperand ( OpNum ) . isImm ( ) && Desc . OpInfo [ OpNum ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( OpNum ) . getImm ( ) ; Target = ARM_MC :: evaluateBranchTarget ( Desc , Addr , Imm ) ; return true ; } } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> unsigned X86TTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasSSE1 ( ) ) return 0 ; if ( ST -> is64Bit ( ) ) return 16 ; return 8 ; } </s>


<s> static bool ix86_push_argument ( unsigned int npush ) { return ( ( ! TARGET_SSE2 || npush < ( TARGET_64BIT ? 16 : 8 ) ) && TARGET_PUSH_ARGS && ! ACCUMULATE_OUTGOING_ARGS ) ; } </s>


<s> void X86LinuxTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


"unknown parameter to option -mtune-ctrl: %s"

parse -mtune-ctrl= option . When DUMP is true , print the features that are explicitly set .


<s> void pru_expand_prologue ( void ) { int regno_start ; int total_frame_size ; int sp_offset ; int save_regs_base ; int save_offset ; total_frame_size = cfun -> machine -> total_size ; if ( flag_stack_usage_info ) current_function_static_stack_size = total_frame_size ; if ( ! UBYTE_INT ( total_frame_size ) ) { pru_add_to_sp ( cfun -> machine -> save_regs_offset - total_frame_size , REG_NOTE_MAX ) ; save_regs_base = 0 ; sp_offset = - cfun -> machine -> save_regs_offset ; } else if ( total_frame_size ) { pru_add_to_sp ( - total_frame_size , REG_NOTE_MAX ) ; save_regs_base = cfun -> machine -> save_regs_offset ; sp_offset = 0 ; } else save_regs_base = sp_offset = 0 ; regno_start = 0 ; save_offset = save_regs_base ; do regno_start = xbbo_next_reg_cluster ( regno_start , & save_offset , true ) ; while ( regno_start >= 0 ) ; if ( frame_pointer_needed ) { int fp_offset = total_frame_size - crtl -> args . pretend_args_size + sp_offset ; pru_add3_frame_adjust ( hard_frame_pointer_rtx , stack_pointer_rtx , fp_offset , REG_NOTE_MAX ) ; } if ( sp_offset ) pru_add_to_sp ( sp_offset , REG_FRAME_RELATED_EXPR ) ; if ( crtl -> profile ) emit_insn ( gen_blockage ( ) ) ; } </s>


<s> bool sh_cfun_attr_renesas_p ( void ) { return sh_attr_renesas_p ( current_function_decl ) ; } </s>

True if __attribute__ ( ( renesas ) ) or -mrenesas , for the current function .


<s> static int rs6000_compute_pressure_classes ( enum reg_class * pressure_classes ) { int n ; n = 0 ; pressure_classes [ n ++ ] = GENERAL_REGS ; if ( TARGET_VSX ) pressure_classes [ n ++ ] = VSX_REGS ; else { if ( TARGET_ALTIVEC ) pressure_classes [ n ++ ] = ALTIVEC_REGS ; if ( TARGET_HARD_FLOAT && TARGET_FPRS ) pressure_classes [ n ++ ] = FLOAT_REGS ; } pressure_classes [ n ++ ] = CR_REGS ; pressure_classes [ n ++ ] = SPECIAL_REGS ; return n ; } </s>

Compute register pressure classes . We implement the target hook to avoid IRA picking something like GEN_OR_FLOAT_REGS as a pressure class , which can lead to incorrect estimates of number of available registers and therefor increased register pressure/spill .


<s> bool ARM64PassConfig :: addILPOpts ( ) { if ( EnableCCMP ) addPass ( createARM64ConditionalCompares ( ) ) ; if ( EnableEarlyIfConvert ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createARM64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> bool DCPU16FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool SystemZFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>


<s> MCSymbol * DLXMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> void X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; EVT VT = TLI . getValueType ( DL , OrigArg . Ty ) ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } SmallVector < uint64_t , 4 > BitOffsets ; SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; PerformArgSplit ( Info . Reg , PartVT . getSizeInBits ( ) * i ) ; } } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


<s> TargetLowering :: ConstraintWeight ARMTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'l' : if ( type -> isIntegerTy ( ) ) { if ( Subtarget -> isThumb ( ) ) weight = CW_SpecificReg ; else weight = CW_Register ; } break ; case 'w' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool immed_offset_p ( rtx mem_rtx ) { gcc_assert ( MEM_P ( mem_rtx ) ) ; rtx addr_rtx = XEXP ( mem_rtx , 0 ) ; if ( REG_P ( addr_rtx ) ) return true ; if ( GET_CODE ( addr_rtx ) == PLUS && GET_CODE ( XEXP ( addr_rtx , 1 ) ) == CONST_INT ) return true ; return false ; } </s>

Check if the address of MEM_RTX consists of a base register and an immediate offset .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64Bit , const TargetInstrInfo & TII ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc = isSub ? ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: SUB64ri8 : X86 :: SUB32ri8 ) : ( Is64Bit ? X86 :: SUB64ri32 : X86 :: SUB32ri ) ) : ( ( Offset < 128 ) ? ( Is64Bit ? X86 :: ADD64ri8 : X86 :: ADD32ri8 ) : ( Is64Bit ? X86 :: ADD64ri32 : X86 :: ADD32ri ) ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> bool assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const override { std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dest , SDValue Src , MachinePointerInfo DestPtrInfo , MachinePointerInfo SrcPtrInfo , bool isStpcpy ) const { SDVTList VTs = DAG . getVTList ( Dest . getValueType ( ) , MVT :: Other ) ; SDValue EndDest = DAG . getNode ( SystemZISD :: STPCPY , DL , VTs , Chain , Dest , Src , DAG . getConstant ( 0 , MVT :: i32 ) ) ; return std :: make_pair ( isStpcpy ? EndDest : Dest , EndDest . getValue ( 1 ) ) ; } </s>

Emit target-specific code that performs a strcpy or stpcpy , in cases where that is faster than a libcall .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { if ( IsLittleEndian && Size == 4 && IsMicroMips ) { EmitInstruction ( Val >> 16 , 2 , OS ) ; EmitInstruction ( Val , 2 , OS ) ; } else { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> StringRef getPassName ( ) const override { return AARCH64_EXPAND_PSEUDO_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
k_Register
&&
"Invalid access!"
)
;
return
Reg
.
Num
;
}
</s>

Returns the register associated with this edge .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( const MCSubtargetInfo & STI ) const { if ( STI . hasFeature ( X86 :: Mode16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; case Mips :: SNZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_B ) ; case Mips :: SNZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_H ) ; case Mips :: SNZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_W ) ; case Mips :: SNZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_D ) ; case Mips :: SNZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_V ) ; case Mips :: SZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_B ) ; case Mips :: SZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_H ) ; case Mips :: SZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_W ) ; case Mips :: SZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_D ) ; case Mips :: SZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_V ) ; case Mips :: COPY_FW_PSEUDO : return emitCOPY_FW ( MI , BB ) ; case Mips :: COPY_FD_PSEUDO : return emitCOPY_FD ( MI , BB ) ; case Mips :: INSERT_FW_PSEUDO : return emitINSERT_FW ( MI , BB ) ; case Mips :: INSERT_FD_PSEUDO : return emitINSERT_FD ( MI , BB ) ; case Mips :: INSERT_B_VIDX_PSEUDO : case Mips :: INSERT_B_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 1 , false ) ; case Mips :: INSERT_H_VIDX_PSEUDO : case Mips :: INSERT_H_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 2 , false ) ; case Mips :: INSERT_W_VIDX_PSEUDO : case Mips :: INSERT_W_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , false ) ; case Mips :: INSERT_D_VIDX_PSEUDO : case Mips :: INSERT_D_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , false ) ; case Mips :: INSERT_FW_VIDX_PSEUDO : case Mips :: INSERT_FW_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , true ) ; case Mips :: INSERT_FD_VIDX_PSEUDO : case Mips :: INSERT_FD_VIDX64_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , true ) ; case Mips :: FILL_FW_PSEUDO : return emitFILL_FW ( MI , BB ) ; case Mips :: FILL_FD_PSEUDO : return emitFILL_FD ( MI , BB ) ; case Mips :: FEXP2_W_1_PSEUDO : return emitFEXP2_W_1 ( MI , BB ) ; case Mips :: FEXP2_D_1_PSEUDO : return emitFEXP2_D_1 ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool xxspltib_constant_p ( rtx op , machine_mode mode , int * num_insns_ptr , int * constant_ptr ) { size_t nunits = GET_MODE_NUNITS ( mode ) ; size_t i ; HOST_WIDE_INT value ; rtx element ; * num_insns_ptr = - 1 ; * constant_ptr = 256 ; if ( ! TARGET_P9_VECTOR ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) && GET_MODE ( op ) != VOIDmode ) return false ; if ( GET_CODE ( op ) == VEC_DUPLICATE ) { if ( mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode ) return false ; element = XEXP ( op , 0 ) ; if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; } else if ( GET_CODE ( op ) == CONST_VECTOR ) { if ( mode != V16QImode && mode != V8HImode && mode != V4SImode && mode != V2DImode ) return false ; element = CONST_VECTOR_ELT ( op , 0 ) ; if ( ! CONST_INT_P ( element ) ) return false ; value = INTVAL ( element ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; for ( i = 1 ; i < nunits ; i ++ ) { element = CONST_VECTOR_ELT ( op , i ) ; if ( ! CONST_INT_P ( element ) ) return false ; if ( value != INTVAL ( element ) ) return false ; } } else if ( CONST_INT_P ( op ) ) { if ( ! SCALAR_INT_MODE_P ( mode ) ) return false ; value = INTVAL ( op ) ; if ( ! IN_RANGE ( value , - 128 , 127 ) ) return false ; if ( ! IN_RANGE ( value , - 1 , 0 ) ) { if ( ! ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_VALID ) ) return false ; if ( EASY_VECTOR_15 ( value ) ) return false ; } } else return false ; if ( ( mode == V4SImode || mode == V8HImode ) && ! IN_RANGE ( value , - 1 , 0 ) && EASY_VECTOR_15 ( value ) ) return false ; if ( mode == V16QImode ) * num_insns_ptr = 1 ; else if ( IN_RANGE ( value , - 1 , 0 ) ) * num_insns_ptr = 1 ; else * num_insns_ptr = 2 ; * constant_ptr = ( int ) value ; return true ; } </s>

Return true if OP is of the given MODE and can be synthesized with ISA 3.0 instructions ( xxspltib , vupkhsb/vextsb2w/vextb2d ) . Return the number of instructions needed ( 1 or 2 ) into the address pointed via NUM_INSNS_PTR . Return the constant that is being split via CONSTANT_PTR .


<s> void SHUXIInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


"instruction requires a CPU feature not currently enabled"

"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ; f -> use_fast_prologue_epilogue_nregs = - 1 ; return f ; } </s>

Clear stack slot assignments remembered from previous functions . This is called from INIT_EXPANDERS once before RTL is emitted for each function .


<s> static bool arm_xscale_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case COMPARE : if ( GET_CODE ( XEXP ( x , 0 ) ) != MULT ) return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; * total = COSTS_N_INSNS ( 3 ) ; return false ; case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( mode == DImode ) { * total = COSTS_N_INSNS ( 5 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = INTVAL ( XEXP ( x , 1 ) ) ; int cost = 1 ; unsigned HOST_WIDE_INT masked_const ; if ( i & 0x80000000 ) i = ~ i ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; masked_const = i & 0xffff8000 ; if ( masked_const != 0 ) { cost ++ ; masked_const = i & 0xf8000000 ; if ( masked_const != 0 ) cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; return false ; } if ( mode == SImode ) { * total = COSTS_N_INSNS ( 3 ) ; return false ; } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; } } </s>

RTX cost for XScale CPUs . Thumb-2 is not supported on any xscale cores , so it can be ignored .


<s> StackOffset AArch64FrameLowering :: getNonLocalFrameIndexReference ( const MachineFunction & MF , int FI ) const { return StackOffset :: getFixed ( getSEHFrameIndexOffset ( MF , FI ) ) ; } </s>

getNonLocalFrameIndexReference - This method returns the offset used to reference a frame index location .


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
length
(
)
>
1
)
return
;
char
Letter
=
Constraint
[
0
]
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
int64_t
Value
=
CST
->
getSExtValue
(
)
;
EVT
TCVT
=
MVT
::
i64
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'J'
:
if
(
isShiftedUInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'L'
:
if
(
isShiftedInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'K'
:
if
(
isUInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'N'
:
if
(
Value
>
0
&&
isPowerOf2_64
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
case
'P'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
TCVT
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> static void moxie_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno ; int regs = 8 - * cum ; * pretend_size = regs < 0 ? 0 : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < 8 ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx slot = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( SImode , ARG_POINTER_REGNUM ) , GEN_INT ( UNITS_PER_WORD * ( 3 + ( regno - 2 ) ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , slot ) , reg ) ; } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


Returns assembly code to perform a DImode shift using a 64-bit global or out register on SPARC-V8+ .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_CCOut
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( CommentStream ) HasCustomInstComment = EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; unsigned Flags = MI -> getFlags ( ) ; if ( ( TSFlags & X86II :: LOCK ) || ( Flags & X86 :: IP_HAS_LOCK ) ) OS << "\tlock\t" ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( STI . getFeatureBits ( ) [ X86 :: Mode64Bit ] ) ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && ( STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) ) { MCInst Data32MI ( * MI ) ; Data32MI . setOpcode ( X86 :: DATA32_PREFIX ) ; printInstruction ( & Data32MI , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; } </s>


<s> bool AArch64RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s>
const
char
*
Cpu0AsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
static_cast
<
Cpu0TargetMachine
&
>
(
TM
)
.
getABI
(
)
.
GetEnumValue
(
)
)
{
case
Cpu0ABIInfo
::
ABI
::
O32
:
return
"abiO32"
;
case
Cpu0ABIInfo
::
ABI
::
S32
:
return
"abiS32"
;
default
:
llvm_unreachable
(
"Unknown Cpu0 ABI"
)
;
}
}
</s>


<s> unsigned MipsMCCodeEmitter :: getBranchTarget26OpValueMM ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> 1 ; return 0 ; } </s>

getBranchTarget26OpValueMM - Return binary encoding of the branch target operand .


<s> static bool ix86_class_likely_spilled_p ( reg_class_t rclass ) { switch ( rclass ) { case AREG : case DREG : case CREG : case BREG : case AD_REGS : case SIREG : case DIREG : case SSE_FIRST_REG : case FP_TOP_REG : case FP_SECOND_REG : return true ; default : break ; } return false ; } </s>


<s> static unsigned int mips_global_pointer ( void ) { unsigned int regno ; if ( ! TARGET_ABICALLS ) return GLOBAL_POINTER_REGNUM ; if ( ! TARGET_EXPLICIT_RELOCS ) return GLOBAL_POINTER_REGNUM ; if ( current_function_profile ) return GLOBAL_POINTER_REGNUM ; if ( current_function_has_nonlocal_goto ) return GLOBAL_POINTER_REGNUM ; if ( ! regs_ever_live [ GLOBAL_POINTER_REGNUM ] && ! current_function_uses_const_pool && ! mips_function_has_gp_insn ( ) ) return 0 ; if ( TARGET_NEWABI && current_function_is_leaf ) for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( ! regs_ever_live [ regno ] && call_used_regs [ regno ] && ! fixed_regs [ regno ] && regno != PIC_FUNCTION_ADDR_REGNUM ) return regno ; return GLOBAL_POINTER_REGNUM ; } </s>

Return the register that should be used as the global pointer within this function . Return 0 if the function does n't need a global pointer .


<s> static rtx rs6000_internal_arg_pointer ( void ) { if ( flag_split_stack && ( lookup_attribute ( "no_split_stack" , DECL_ATTRIBUTES ( cfun -> decl ) ) == NULL ) ) { if ( cfun -> machine -> split_stack_arg_pointer == NULL_RTX ) { rtx pat ; cfun -> machine -> split_stack_arg_pointer = gen_reg_rtx ( Pmode ) ; REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = 1 ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , 12 ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ; } rtx ret = plus_constant ( Pmode , cfun -> machine -> split_stack_arg_pointer , FIRST_PARM_OFFSET ( current_function_decl ) ) ; return copy_to_reg ( ret ) ; } return virtual_incoming_args_rtx ; } </s>

Return the internal arg pointer used for function incoming arguments . When -fsplit-stack , the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls and suchlike . We 'd really like to use a pseudo here for the internal arg pointer but data-flow analysis is not prepared to accept pseudos as live at the beginning of a function .


<s> bool AArch64AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { if ( ! parseAuthExpr ( Res , EndLoc ) ) return false ; return getParser ( ) . parsePrimaryExpr ( Res , EndLoc , nullptr ) ; } </s>


Generate and return a store pair instruction of mode MODE to store register REG1 to MEM1 and register REG2 to MEM2 .


<s> static void replace_swapped_aligned_load ( swap_web_entry * insn_entry , rtx swap_insn ) { unsigned uid = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && ! insn_entry [ uid ] . is_load ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( swap_insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; gcc_assert ( def_link && def_link -> ref && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) && ! def_link -> next ) ; rtx_insn * def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_SRC ( new_body ) ) ) ; basic_block bb = BLOCK_FOR_INSN ( def_insn ) ; set_block_for_insn ( new_insn , bb ) ; if ( cfun -> can_throw_non_call_exceptions && BB_END ( bb ) == def_insn ) { rtx note = find_reg_note ( def_insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) add_reg_note ( new_insn , REG_EH_REGION , XEXP ( note , 0 ) ) ; } df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted ( ) ; mark_swaps_for_removal ( insn_entry , uid ) ; replace_swap_with_copy ( insn_entry , uid ) ; } </s>

Given that SWAP_INSN represents a swap of an aligned load-with-swap , replace the load with an aligned load ( without swap ) and replace the swap with a copy insn .


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case E_DImode : case E_SCmode : case E_DCmode : case E_TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && ! FLOAT128_VECTOR_P ( mode ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || VECTOR_ALIGNMENT_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> X86Subtarget :: X86Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , unsigned StackAlignOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void output_indirect_thunk_function ( enum indirect_thunk_prefix need_prefix , unsigned int regno , bool ret_p ) { char name [ 32 ] ; tree decl ; indirect_thunk_name ( name , regno , need_prefix , ret_p ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = 1 ; TREE_STATIC ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; if ( TARGET_MACHO ) { switch_to_section ( darwin_sections [ picbase_thunk_section ] ) ; fputs ( "\t.weak_definition\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( "\n\t.private_extern\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = 1 ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , 0 ) ; switch_to_section ( get_named_section ( decl , NULL , 0 ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( "\t.hidden\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl ; allocate_struct_function ( decl , false ) ; init_function_start ( decl ) ; cfun -> is_thunk = true ; first_function_block_is_cold = false ; final_start_function ( emit_barrier ( ) , asm_out_file , 1 ) ; output_indirect_thunk ( regno ) ; final_end_function ( ) ; init_insn_lengths ( ) ; free_after_compilation ( cfun ) ; set_cfun ( NULL ) ; current_function_decl = NULL ; } </s>

Output a funtion with a call and return thunk for indirect branch . If BND_P is true , the BND prefix is needed . If REGNO ! = UNVALID_REGNUM , the function address is in REGNO . Otherwise , the function address is on the top of stack . Thunk is used for function return if RET_P is true .


<s>
const
char
*
output_fp_compare
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
eflags_p
,
bool
unordered_p
)
{
rtx
*
xops
=
eflags_p
&
operands
[
0
]
:
&
operands
[
1
]
;
bool
stack_top_dies
;
static
char
buf
[
40
]
;
const
char
*
p
;
gcc_assert
(
STACK_TOP_P
(
xops
[
0
]
)
)
;
stack_top_dies
=
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
)
;
if
(
eflags_p
)
{
p
=
unordered_p
"fucomi"
:
"fcomi"
;
strcpy
(
buf
,
p
)
;
p
=
"p\t{%y1, %0|%0, %y1}"
;
strcat
(
buf
,
p
+
!
stack_top_dies
)
;
return
buf
;
}
if
(
STACK_REG_P
(
xops
[
1
]
)
&&
stack_top_dies
&&
find_regno_note
(
insn
,
REG_DEAD
,
FIRST_STACK_REG
+
1
)
)
{
gcc_assert
(
REGNO
(
xops
[
1
]
)
==
FIRST_STACK_REG
+
1
)
;
p
=
unordered_p
"fucompp"
:
"fcompp"
;
strcpy
(
buf
,
p
)
;
}
else
if
(
const0_operand
(
xops
[
1
]
,
VOIDmode
)
)
{
gcc_assert
(
!
unordered_p
)
;
strcpy
(
buf
,
"ftst"
)
;
}
else
{
if
(
GET_MODE_CLASS
(
GET_MODE
(
xops
[
1
]
)
)
==
MODE_INT
)
{
gcc_assert
(
!
unordered_p
)
;
p
=
"ficom"
;
}
else
p
=
unordered_p
"fucom"
:
"fcom"
;
strcpy
(
buf
,
p
)
;
p
=
"p%Z2\t%y2"
;
strcat
(
buf
,
p
+
!
stack_top_dies
)
;
}
output_asm_insn
(
buf
,
operands
)
;
return
"fnstsw\t%0"
;
}
</s>

Output code for INSN to compare OPERANDS . EFLAGS_P is 1 when fcomi should be used and 2 when fnstsw should be used . UNORDERED_P is true when fucom should be used .


<s> void aarch64_sls_emit_shared_blr_thunks ( FILE * out_file ) { if ( ! aarch64_sls_shared_thunks_needed ) return ; for ( int regnum = 0 ; regnum < 30 ; ++ regnum ) { tree decl = aarch64_sls_shared_thunks [ regnum ] ; if ( ! decl ) continue ; const char * name = indirect_symbol_names [ regnum ] ; switch_to_section ( get_named_section ( decl , NULL , 0 ) ) ; ASM_OUTPUT_ALIGN ( out_file , 2 ) ; targetm . asm_out . globalize_label ( out_file , name ) ; targetm . asm_out . assemble_visibility ( decl , VISIBILITY_HIDDEN ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( out_file , name , "function" ) ; ASM_OUTPUT_LABEL ( out_file , name ) ; aarch64_sls_emit_function_stub ( out_file , regnum ) ; asm_fprintf ( out_file , "\tdsb\tsy\n\tisb\n" ) ; ASM_DECLARE_FUNCTION_SIZE ( out_file , name , decl ) ; } } </s>

Emit shared BLR stubs for the current compilation unit . Over the course of compiling this unit we may have converted some BLR instructions to a BL to a shared stub function . This is where we emit those stub functions . This function is for the stubs shared between different functions in this compilation unit . We share when optimizing for size instead of speed . This function is called through the TARGET_ASM_FILE_END hook .


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> static bool classof ( const ARM64MCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> unsigned MipsCodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned OpNo ) const { return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & TM . getSubtarget < X86Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
unsigned
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
AArch64
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void fixup_addr_diff_vecs ( rtx_insn * first ) { rtx_insn * insn ; for ( insn = first ; insn ; insn = NEXT_INSN ( insn ) ) { rtx vec_lab , pat , prevpat , x , braf_label ; rtx_insn * prev ; if ( ! JUMP_TABLE_DATA_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC ) continue ; pat = PATTERN ( insn ) ; vec_lab = XEXP ( XEXP ( pat , 0 ) , 0 ) ; for ( prev = as_a < rtx_insn * > ( vec_lab ) ; ; prev = PREV_INSN ( prev ) ) { if ( ! JUMP_P ( prev ) ) continue ; prevpat = PATTERN ( prev ) ; if ( GET_CODE ( prevpat ) != PARALLEL || XVECLEN ( prevpat , 0 ) != 2 ) continue ; x = XVECEXP ( prevpat , 0 , 1 ) ; if ( GET_CODE ( x ) != USE ) continue ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == LABEL_REF && XEXP ( x , 0 ) == vec_lab ) break ; } if ( ! prev ) continue ; braf_label = XEXP ( XEXP ( SET_SRC ( XVECEXP ( prevpat , 0 , 0 ) ) , 1 ) , 0 ) ; emit_label_after ( braf_label , prev ) ; XEXP ( XEXP ( pat , 0 ) , 0 ) = braf_label ; } } </s>


<s> MCDisassembler :: DecodeStatus X86GenericDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { CommentStream = & CStream ; InternalInstruction InternalInstr ; dlog_t LoggerFn = logger ; if ( & VStream == & nulls ( ) ) LoggerFn = nullptr ; Region R ( Bytes , Address ) ; int Ret = decodeInstruction ( & InternalInstr , regionReader , ( const void * ) & R , LoggerFn , ( void * ) & VStream , ( const void * ) MII . get ( ) , Address , fMode ) ; if ( Ret ) { Size = InternalInstr . readerCursor - Address ; return Fail ; } else { Size = InternalInstr . length ; bool Ret = translateInstruction ( Instr , InternalInstr , this ) ; if ( ! Ret ) { unsigned Flags = X86 :: IP_NO_PREFIX ; if ( InternalInstr . hasAdSize ) Flags |= X86 :: IP_HAS_AD_SIZE ; if ( ! InternalInstr . mandatoryPrefix ) { if ( InternalInstr . hasOpSize ) Flags |= X86 :: IP_HAS_OP_SIZE ; if ( InternalInstr . repeatPrefix == 0xf2 ) Flags |= X86 :: IP_HAS_REPEAT_NE ; else if ( InternalInstr . repeatPrefix == 0xf3 && InternalInstr . opcode != 0x90 ) Flags |= X86 :: IP_HAS_REPEAT ; if ( InternalInstr . hasLockPrefix ) Flags |= X86 :: IP_HAS_LOCK ; } Instr . setFlags ( Flags ) ; } return ( ! Ret ) ? Success : Fail ; } } </s>

Returns the disassembly of a single instruction .


<s> static tree winnt_d_handle_target_object_format ( void ) { const char * objfmt = "coff" ; return build_string_literal ( strlen ( objfmt ) + 1 , objfmt ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` objectFormat '' ) ' .


<s> MachineInstr * ARMBaseInstrInfo :: commuteInstructionImpl ( MachineInstr * MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case ARM :: MOVCCr : case ARM :: t2MOVCCr : { unsigned PredReg = 0 ; ARMCC :: CondCodes CC = getInstrPredicate ( * MI , PredReg ) ; if ( CC == ARMCC :: AL || PredReg != ARM :: CPSR ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return MI ; } } return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

ARM ARM ARM::MOVCCr ARM::t2MOVCCr 0 ARMCC::CondCodes ARMCC::AL ARM::CPSR ARMCC::getOppositeCondition


Implements TARGET_ASM_FILE_START . Output the assembly header .


<s>
TargetTransformInfo
MipsTargetMachine
::
getTargetTransformInfo
(
const
Function
&
F
)
const
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
LLVM_DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
</s>

Get a TargetTransformInfo implementation for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s>
bool
AArch64AddressTypePromotion
::
runOnFunction
(
Function
&
F
)
{
if
(
!
EnableAddressTypePromotion
||
F
.
isDeclaration
(
)
)
return
false
;
Func
=
&
F
;
ConsideredSExtType
=
Type
::
getInt64Ty
(
Func
->
getContext
(
)
)
;
DEBUG
(
dbgs
(
)
<<
"*** "
<<
getPassName
(
)
<<
": "
<<
Func
->
getName
(
)
<<
'\n'
)
;
Instructions
SExtInsts
;
analyzeSExtension
(
SExtInsts
)
;
return
propagateSignExtension
(
SExtInsts
)
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> X86TargetLowering :: ConstraintType X86TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'R' : case 'q' : case 'Q' : case 'f' : case 't' : case 'u' : case 'y' : case 'x' : case 'Y' : case 'l' : return C_RegisterClass ; case 'a' : case 'b' : case 'c' : case 'd' : case 'S' : case 'D' : case 'A' : return C_Register ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'G' : case 'C' : case 'e' : case 'Z' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool ix86_expand_int_vcond ( rtx operands [ ] ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; bool negate = false ; rtx x , cop0 , cop1 ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = cop0 , cop0 = cop1 , cop1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V4SImode : { rtx t1 , t2 , mask ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv4si3 ( t1 , cop0 , cop1 ) ) ; mask = GEN_INT ( - 0x80000000 ) ; mask = gen_rtx_CONST_VECTOR ( mode , gen_rtvec ( 4 , mask , mask , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_andv4si3 ( t2 , cop0 , mask ) ) ; x = gen_reg_rtx ( mode ) ; emit_insn ( gen_xorv4si3 ( x , t1 , t2 ) ) ; code = GT ; } break ; case V16QImode : case V8HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , cop0 , cop1 ) ) ) ; code = EQ ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } cop0 = x ; cop1 = CONST0_RTX ( mode ) ; } x = ix86_expand_sse_cmp ( operands [ 0 ] , code , cop0 , cop1 , operands [ 1 + negate ] , operands [ 2 - negate ] ) ; ix86_expand_sse_movcc ( operands [ 0 ] , x , operands [ 1 + negate ] , operands [ 2 - negate ] ) ; return true ; } </s>

Expand a signed integral vector conditional move .


<s> static void * mingw32_gt_pch_get_address ( size_t size , int ) { void * res ; res = VirtualAlloc ( NULL , size , MEM_RESERVE | MEM_TOP_DOWN , PAGE_NOACCESS ) ; if ( ! res ) w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "VirtualAlloc" ) ; else VirtualFree ( res , 0 , MEM_RELEASE ) ; return res ; } </s>

Identify an address that 's likely to be free in a subsequent invocation of the compiler . The area should be able to hold SIZE bytes . FD is an open file descriptor if the host would like to probe with mmap .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return Subtarget . is64Bit ( ) ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool AArch64TargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = static_cast < const yaml :: AArch64FunctionInfo & > ( MFI ) ; MachineFunction & MF = PFS . MF ; MF . getInfo < AArch64FunctionInfo > ( ) -> initializeBaseYamlFields ( YamlMFI ) ; return false ; } </s>

Parse out the target 's MachineFunctionInfo from the YAML reprsentation .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> static int loongarch_zero_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; } </s>

Return the cost of zero-extending OP to mode MODE , not including the cost of OP itself .


"inserting int3 after trailing call instruction:\n"

"inserting int3 in trailing empty MBB:\n"

runOnMachineFunction - Emit the function body .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI -> getOpcode ( ) ) ) if ( MI -> getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI -> getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> virtual const SystemZInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
rtx
rhs
=
SET_SRC
(
body
)
;
swap_const_vector_halves
(
rhs
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
case
SH_XXPERMDI
:
adjust_xxpermdi
(
insn
)
;
break
;
case
SH_CONCAT
:
adjust_concat
(
insn
)
;
break
;
case
SH_VPERM
:
adjust_vperm
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

rs6000
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & TuneCPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian , unsigned MinSVEVectorSizeInBitsOverride , unsigned MaxSVEVectorSizeInBitsOverride ) : AArch64GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , MinSVEVectorSizeInBits ( MinSVEVectorSizeInBitsOverride ) , MaxSVEVectorSizeInBits ( MaxSVEVectorSizeInBitsOverride ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU , TuneCPU ) ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void function_expander :: add_fixed_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 ) ; create_fixed_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an operand that must be X . The only way of legitimizing an invalid X is to reload the address of a MEM .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : case 'z' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; case 'z' : RC = & AArch64 :: ZPRRegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , AArch64 :: NoRegAltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; unsigned AltName = AArch64 :: NoRegAltName ; const TargetRegisterClass * RegClass ; if ( AArch64 :: ZPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: ZPRRegClass ; } else if ( AArch64 :: PPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: PPRRegClass ; } else { RegClass = & AArch64 :: FPR128RegClass ; AltName = AArch64 :: vreg ; } return printAsmRegInClass ( MO , RegClass , AltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"Frame offsets outside of the signed 16-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; rtx perm [ 16 ] ; for ( i = 0 ; i < nelt ; i ++ ) perm [ i ] = GEN_INT ( i * 2 ) ; rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , nelt , perm ) ; } </s>


<s> bool isMem ( RegisterKind RegKind , bool HasIndex ) const { return ( Kind == KindMem && Mem . RegKind == RegKind && ( HasIndex || ! Mem . Index ) ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) || ! STI . needsSwapsForVSXMemOps ( ) ) return false ; bool Changed = false ; initialize ( MF ) ; if ( gatherVectorInstructions ( ) ) { formWebs ( ) ; recordUnoptimizableWebs ( ) ; markSwapsForRemoval ( ) ; Changed = removeSwaps ( ) ; } delete EC ; return Changed ; } </s>


<s> bool X86InstrInfo :: isHighLatencyDef ( int opc ) const { switch ( opc ) { default : return false ; case X86 :: DIVSDrm : case X86 :: DIVSDrm_Int : case X86 :: DIVSDrr : case X86 :: DIVSDrr_Int : case X86 :: DIVSSrm : case X86 :: DIVSSrm_Int : case X86 :: DIVSSrr : case X86 :: DIVSSrr_Int : case X86 :: SQRTPDm : case X86 :: SQRTPDm_Int : case X86 :: SQRTPDr : case X86 :: SQRTPDr_Int : case X86 :: SQRTPSm : case X86 :: SQRTPSm_Int : case X86 :: SQRTPSr : case X86 :: SQRTPSr_Int : case X86 :: SQRTSDm : case X86 :: SQRTSDm_Int : case X86 :: SQRTSDr : case X86 :: SQRTSDr_Int : case X86 :: SQRTSSm : case X86 :: SQRTSSm_Int : case X86 :: SQRTSSr : case X86 :: SQRTSSr_Int : return true ; } } </s>

Return true if this opcode has high latency to its result .


<s> static bool pru_legitimate_address_p ( machine_mode mode , rtx operand , bool strict_p ) { switch ( GET_CODE ( operand ) ) { case SYMBOL_REF : case LABEL_REF : case CONST : case CONST_WIDE_INT : return false ; case CONST_INT : return ctable_addr_operand ( operand , VOIDmode ) ; case REG : return pru_regno_ok_for_base_p ( REGNO ( operand ) , strict_p ) ; case PLUS : { rtx op0 = XEXP ( operand , 0 ) ; rtx op1 = XEXP ( operand , 1 ) ; return pru_valid_addr_expr_p ( mode , op0 , op1 , strict_p ) ; } default : break ; } return false ; } </s>


<s>
static
unsigned
getOppositeBranchOpc
(
unsigned
Opcode
)
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown conditional branch!"
)
;
case
CSKY
::
BT32
:
return
CSKY
::
BF32
;
case
CSKY
::
BT16
:
return
CSKY
::
BF16
;
case
CSKY
::
BF32
:
return
CSKY
::
BT32
;
case
CSKY
::
BF16
:
return
CSKY
::
BT16
;
case
CSKY
::
BHZ32
:
return
CSKY
::
BLSZ32
;
case
CSKY
::
BHSZ32
:
return
CSKY
::
BLZ32
;
case
CSKY
::
BLZ32
:
return
CSKY
::
BHSZ32
;
case
CSKY
::
BLSZ32
:
return
CSKY
::
BHZ32
;
case
CSKY
::
BNEZ32
:
return
CSKY
::
BEZ32
;
case
CSKY
::
BEZ32
:
return
CSKY
::
BNEZ32
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> bool loongarch_small_data_pattern_p ( rtx op ) { return loongarch_small_data_pattern_1 ( op ) ; } </s>

Return true if OP refers to small data symbols directly .


<s> rtx mmix_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { machine_mode ccmode = SELECT_CC_MODE ( code , x , y ) ; return gen_reg_rtx ( ccmode ) ; } </s>

X and Y are two things to compare using CODE . Emit a compare insn if possible and return the rtx for the cc-reg in the proper mode , or NULL_RTX if this is not a valid comparison .


<s> virtual const DCPU16Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
const
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
It
;
return
CallPt
;
}
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
0
"No callee-saved register available?"
ARM::LR
ARM::LR
ARM::LR
ARM::LR


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
bool
X86ATTAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
Function
*
F
=
MF
.
getFunction
(
)
;
this
->
MF
=
&
MF
;
unsigned
CC
=
F
->
getCallingConv
(
)
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
if
(
CC
==
CallingConv
::
X86_StdCall
||
CC
==
CallingConv
::
X86_FastCall
)
FunctionInfoMap
[
F
]
=
*
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
if
(
F
->
hasDLLExportLinkage
(
)
)
DLLExportedFns
.
insert
(
Mang
->
makeNameProper
(
F
->
getName
(
)
,
""
)
)
;
emitFunctionHeader
(
MF
)
;
if
(
TAI
->
doesSupportDebugInformation
(
)
||
TAI
->
doesSupportExceptionHandling
(
)
)
DW
->
BeginFunction
(
&
MF
)
;
bool
hasAnyRealCode
=
false
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
I
->
pred_empty
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
IE
=
I
->
end
(
)
;
II
!=
IE
;
++
II
)
{
if
(
!
II
->
isLabel
(
)
)
hasAnyRealCode
=
true
;
printMachineInstruction
(
II
)
;
}
}
if
(
Subtarget
->
isTargetDarwin
(
)
&&
!
hasAnyRealCode
)
{
O
<<
"\tnop\n"
;
}
if
(
TAI
->
hasDotTypeDotSizeDirective
(
)
)
O
<<
"\t.size\t"
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
'\n'
;
if
(
TAI
->
doesSupportDebugInformation
(
)
)
DW
->
EndFunction
(
&
MF
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
O
.
flush
(
)
;
return
false
;
}
</s>


<s> virtual const PPCRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool is_indirect_tailcall_p ( rtx call ) { rtx pat = PATTERN ( call ) ; pat = XVECEXP ( pat , 0 , 0 ) ; if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ; pat = XEXP ( XEXP ( pat , 0 ) , 0 ) ; return REG_P ( pat ) ; } </s>

We do not know if r3 will be available because we do have an indirect tailcall happening in this particular case .


<s> bool Mips16RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; TII . copyPhysReg ( MBB , I , DL , Mips :: T0 , Reg , true ) ; TII . copyPhysReg ( MBB , UseMI , DL , Reg , Mips :: T0 , true ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


"Callee should be an llvm::Function object."

"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> bool PPCLoopDataPrefetch :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolution > ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; MadeChange |= runOnLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
StringRef
AArch64MCExpr
::
getVariantKindName
(
)
const
{
switch
(
static_cast
<
uint32_t
>
(
getKind
(
)
)
)
{
case
VK_CALL
:
return
""
;
case
VK_LO12
:
return
":lo12:"
;
case
VK_ABS_G3
:
return
":abs_g3:"
;
case
VK_ABS_G2
:
return
":abs_g2:"
;
case
VK_ABS_G2_S
:
return
":abs_g2_s:"
;
case
VK_ABS_G2_NC
:
return
":abs_g2_nc:"
;
case
VK_ABS_G1
:
return
":abs_g1:"
;
case
VK_ABS_G1_S
:
return
":abs_g1_s:"
;
case
VK_ABS_G1_NC
:
return
":abs_g1_nc:"
;
case
VK_ABS_G0
:
return
":abs_g0:"
;
case
VK_ABS_G0_S
:
return
":abs_g0_s:"
;
case
VK_ABS_G0_NC
:
return
":abs_g0_nc:"
;
case
VK_DTPREL_G2
:
return
":dtprel_g2:"
;
case
VK_DTPREL_G1
:
return
":dtprel_g1:"
;
case
VK_DTPREL_G1_NC
:
return
":dtprel_g1_nc:"
;
case
VK_DTPREL_G0
:
return
":dtprel_g0:"
;
case
VK_DTPREL_G0_NC
:
return
":dtprel_g0_nc:"
;
case
VK_DTPREL_HI12
:
return
":dtprel_hi12:"
;
case
VK_DTPREL_LO12
:
return
":dtprel_lo12:"
;
case
VK_DTPREL_LO12_NC
:
return
":dtprel_lo12_nc:"
;
case
VK_TPREL_G2
:
return
":tprel_g2:"
;
case
VK_TPREL_G1
:
return
":tprel_g1:"
;
case
VK_TPREL_G1_NC
:
return
":tprel_g1_nc:"
;
case
VK_TPREL_G0
:
return
":tprel_g0:"
;
case
VK_TPREL_G0_NC
:
return
":tprel_g0_nc:"
;
case
VK_TPREL_HI12
:
return
":tprel_hi12:"
;
case
VK_TPREL_LO12
:
return
":tprel_lo12:"
;
case
VK_TPREL_LO12_NC
:
return
":tprel_lo12_nc:"
;
case
VK_TLSDESC_LO12
:
return
":tlsdesc_lo12:"
;
case
VK_ABS_PAGE
:
return
""
;
case
VK_ABS_PAGE_NC
:
return
":pg_hi21_nc:"
;
case
VK_GOT_PAGE
:
return
":got:"
;
case
VK_GOT_LO12
:
return
":got_lo12:"
;
case
VK_GOTTPREL_PAGE
:
return
":gottprel:"
;
case
VK_GOTTPREL_LO12_NC
:
return
":gottprel_lo12:"
;
case
VK_GOTTPREL_G1
:
return
":gottprel_g1:"
;
case
VK_GOTTPREL_G0_NC
:
return
":gottprel_g0_nc:"
;
case
VK_TLSDESC
:
return
""
;
case
VK_TLSDESC_PAGE
:
return
":tlsdesc:"
;
case
VK_SECREL_LO12
:
return
":secrel_lo12:"
;
case
VK_SECREL_HI12
:
return
":secrel_hi12:"
;
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .


<s> static void init_window ( int window_num ) { int i ; dispatch_windows * new_list ; if ( window_num == 0 ) new_list = dispatch_window_list ; else new_list = dispatch_window_list1 ; new_list -> num_insn = 0 ; new_list -> num_uops = 0 ; new_list -> window_size = 0 ; new_list -> next = NULL ; new_list -> prev = NULL ; new_list -> window_num = window_num ; new_list -> num_imm = 0 ; new_list -> num_imm_32 = 0 ; new_list -> num_imm_64 = 0 ; new_list -> imm_size = 0 ; new_list -> num_loads = 0 ; new_list -> num_stores = 0 ; new_list -> violation = false ; for ( i = 0 ; i < MAX_INSN ; i ++ ) { new_list -> window [ i ] . insn = NULL ; new_list -> window [ i ] . group = disp_no_group ; new_list -> window [ i ] . path = no_path ; new_list -> window [ i ] . byte_len = 0 ; new_list -> window [ i ] . imm_bytes = 0 ; } return ; } </s>

This function initializes a dispatch window and the list container holding a pointer to the window .


<s> static void output_indirect_thunk_function ( enum indirect_thunk_prefix need_prefix , unsigned int regno , bool ret_p ) { char name [ 32 ] ; tree decl ; indirect_thunk_name ( name , regno , need_prefix , ret_p ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = 1 ; TREE_STATIC ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; if ( TARGET_MACHO ) { switch_to_section ( darwin_sections [ picbase_thunk_section ] ) ; fputs ( "\t.weak_definition\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( "\n\t.private_extern\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = 1 ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , 0 ) ; switch_to_section ( get_named_section ( decl , NULL , 0 ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( "\t.hidden\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl ; allocate_struct_function ( decl , false ) ; init_function_start ( decl ) ; cfun -> is_thunk = true ; first_function_block_is_cold = false ; final_start_function ( emit_barrier ( ) , asm_out_file , 1 ) ; output_indirect_thunk ( need_prefix , regno ) ; final_end_function ( ) ; init_insn_lengths ( ) ; free_after_compilation ( cfun ) ; set_cfun ( NULL ) ; current_function_decl = NULL ; } </s>

Output a funtion with a call and return thunk for indirect branch . If BND_P is true , the BND prefix is needed . If REGNO ! = UNVALID_REGNUM , the function address is in REGNO . Otherwise , the function address is on the top of stack . Thunk is used for function return if RET_P is true .


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; if ( Created ) Created -> push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> void AArch64TargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MF . getFrameInfo ( ) . computeMaxCallFrameSize ( MF ) ; TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> bool fp_zero_operand ( rtx op ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( op ) != SFmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; return REAL_VALUES_EQUAL ( r , dconst0 ) && ! REAL_VALUE_MINUS_ZERO ( r ) ; } </s>

Returns true if OP is a floating point value with value 0.0 .


<s> static bool mips_expand_vselect ( rtx target , rtx op0 , const unsigned char * perm , unsigned nelt ) { rtx rperm [ MAX_VECT_LEN ] , x ; rtx_insn * insn ; unsigned i ; for ( i = 0 ; i < nelt ; ++ i ) rperm [ i ] = GEN_INT ( perm [ i ] ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( nelt , rperm ) ) ; x = gen_rtx_VEC_SELECT ( GET_MODE ( target ) , op0 , x ) ; x = gen_rtx_SET ( target , x ) ; insn = emit_insn ( x ) ; if ( recog_memoized ( insn ) < 0 ) { remove_insn ( insn ) ; return false ; } return true ; } </s>

Construct ( set target ( vec_select op0 ( parallel perm ) ) ) and return true if that 's a valid instruction in the active ISA .


<s> MachineBasicBlock :: iterator eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const override { return MBB . erase ( MI ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool isEqualityCmpFoldedWithSignedCmp ( ) const override { return false ; } </s>

Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison .


<s> void vax_notice_update_cc ( rtx exp , rtx insn ATTRIBUTE_UNUSED ) { if ( GET_CODE ( exp ) == SET ) { if ( GET_CODE ( SET_SRC ( exp ) ) == CALL ) CC_STATUS_INIT ; else if ( GET_CODE ( SET_DEST ( exp ) ) != ZERO_EXTRACT && GET_CODE ( SET_DEST ( exp ) ) != PC ) { cc_status . flags = 0 ; switch ( GET_CODE ( SET_SRC ( exp ) ) ) { case NEG : if ( GET_MODE_CLASS ( GET_MODE ( exp ) ) == MODE_FLOAT ) break ; case AND : case IOR : case XOR : case NOT : case MEM : case REG : cc_status . flags = CC_NO_OVERFLOW ; break ; default : break ; } cc_status . value1 = SET_DEST ( exp ) ; cc_status . value2 = SET_SRC ( exp ) ; } } else if ( GET_CODE ( exp ) == PARALLEL && GET_CODE ( XVECEXP ( exp , 0 , 0 ) ) == SET ) { if ( GET_CODE ( SET_SRC ( XVECEXP ( exp , 0 , 0 ) ) ) == CALL ) CC_STATUS_INIT ; else if ( GET_CODE ( SET_DEST ( XVECEXP ( exp , 0 , 0 ) ) ) != PC ) { cc_status . flags = 0 ; cc_status . value1 = SET_DEST ( XVECEXP ( exp , 0 , 0 ) ) ; cc_status . value2 = SET_SRC ( XVECEXP ( exp , 0 , 0 ) ) ; } else CC_STATUS_INIT ; } else CC_STATUS_INIT ; if ( cc_status . value1 && GET_CODE ( cc_status . value1 ) == REG && cc_status . value2 && reg_overlap_mentioned_p ( cc_status . value1 , cc_status . value2 ) ) cc_status . value2 = 0 ; if ( cc_status . value1 && GET_CODE ( cc_status . value1 ) == MEM && cc_status . value2 && GET_CODE ( cc_status . value2 ) == MEM ) cc_status . value2 = 0 ; } </s>


<s> SparcTargetMachine :: SparcTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < SparcELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) { initAsmInfo ( ) ; } </s>


<s>
const
char
*
pru_output_sign_extend
(
rtx
*
operands
)
{
static
char
buf
[
512
]
;
int
bufi
;
const
int
dst_sz
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
;
const
int
src_sz
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
1
]
)
)
;
char
ext_start
;
switch
(
src_sz
)
{
case
1
:
ext_start
=
'y'
;
break
;
case
2
:
ext_start
=
'z'
;
break
;
default
:
gcc_unreachable
(
)
;
}
gcc_assert
(
dst_sz
>
src_sz
)
;
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"mov\t%%0, %%1\n\t"
"qbbc\t.+8, %%0, %d\n\t"
"fill\t%%%c0, %d"
,
sign_bit_position
(
operands
[
1
]
)
,
ext_start
,
dst_sz
src_sz
)
;
gcc_assert
(
bufi
>
0
)
;
gcc_assert
(
(
unsigned
int
)
bufi
<
sizeof
(
buf
)
)
;
return
buf
;
}
</s>

Output asm code for sign_extend operation .


<s> bool isMachineVerifierClean ( ) const override { return false ; } </s>

Returns true if the target is expected to pass all machine verifier checks .


<s> static enum flt_eval_method ix86_get_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; case EXCESS_PRECISION_TYPE_STANDARD : case EXCESS_PRECISION_TYPE_IMPLICIT : if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! ( TARGET_SSE && TARGET_SSE_MATH ) ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD in float.h . When using only the FPU , assume that the fpcw is set to extended precision ; when using only SSE , rounding is correct ; when using both SSE and the FPU , the rounding precision is indeterminate , since either may be chosen apparently at random .


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SystemZ Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx_insn * aarch64_speculation_clobber_sp ( ) { rtx sp = gen_rtx_REG ( DImode , SP_REGNUM ) ; rtx tracker = gen_rtx_REG ( DImode , SPECULATION_TRACKER_REGNUM ) ; rtx scratch = gen_rtx_REG ( DImode , SPECULATION_SCRATCH_REGNUM ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( scratch , sp ) ) ; emit_insn ( gen_anddi3 ( scratch , scratch , tracker ) ) ; emit_insn ( gen_rtx_SET ( sp , scratch ) ) ; rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } </s>

Generate a code sequence to clobber SP if speculating incorreclty .


<s> bool nds32_ls_333_p ( rtx rt , rtx ra , rtx imm , machine_mode mode ) { if ( REGNO_REG_CLASS ( REGNO ( rt ) ) == LOW_REGS && REGNO_REG_CLASS ( REGNO ( ra ) ) == LOW_REGS ) { if ( GET_MODE_SIZE ( mode ) == 4 ) return satisfies_constraint_Iu05 ( imm ) ; if ( GET_MODE_SIZE ( mode ) == 2 ) return satisfies_constraint_Iu04 ( imm ) ; if ( GET_MODE_SIZE ( mode ) == 1 ) return satisfies_constraint_Iu03 ( imm ) ; } return false ; } </s>

Function to test 333-form for load/store instructions . This is auxiliary extern function for auxiliary macro in nds32.h . Because it is a little complicated , we use function instead of macro .


<s> SDNode * LC3bDagToDagISel :: Select ( SDNode * n ) { return NULL ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( TM . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .


"getJumpTargetOpValue expects only expressions"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> void rs6000_emit_le_vsx_move ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( ! BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P ( mode ) && ! TARGET_P9_VECTOR && ! gpr_or_gpr_p ( dest , source ) && ( MEM_P ( source ) ^ MEM_P ( dest ) ) ) ; if ( MEM_P ( source ) ) { gcc_assert ( REG_P ( dest ) || GET_CODE ( dest ) == SUBREG ) ; rs6000_emit_le_vsx_load ( dest , source , mode ) ; } else { if ( ! REG_P ( source ) ) source = force_reg ( mode , source ) ; rs6000_emit_le_vsx_store ( dest , source , mode ) ; } } </s>

Emit a sequence representing a little-endian VSX load or store , moving data from SOURCE to DEST in mode MODE . This is done separately from rs6000_emit_move to ensure it is called only during expand . LE VSX loads and stores introduced later are handled with a split . The expand-time RTL generation allows us to optimize away redundant pairs of register-permutes .


<s> Register ( ) { PPCTargetMachine :: registerAsmPrinter ( createPPCAsmPrinterPass ) ; } </s>


<s> void OR1KTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Result ( 0 , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'J' : case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) == 0 ) { Result = DAG . getTargetConstant ( 0 , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'K' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isUInt < 16 > ( C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= 31 ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( isInt < 32 > ( Val ) ) && ( ( Val & 0xffff ) == 0 ) ) { Result = DAG . getTargetConstant ( Val , dl , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { int64_t Val = C -> getSExtValue ( ) ; if ( ( Val >= - 33554432 ) && ( Val <= 33554431 ) ) { Result = DAG . getTargetConstant ( Val , dl , Op . getValueType ( ) ) ; break ; } } return ; } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .


"X86 Speculative Execution Side Effect Suppression"


<s> bool ARMBaseInstrInfo :: areLoadsFromSameBasePtr ( SDNode * Load1 , SDNode * Load2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( Subtarget . isThumb1Only ( ) ) return false ; if ( ! Load1 -> isMachineOpcode ( ) || ! Load2 -> isMachineOpcode ( ) ) return false ; switch ( Load1 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRDi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } switch ( Load2 -> getMachineOpcode ( ) ) { default : return false ; case ARM :: LDRi12 : case ARM :: LDRBi12 : case ARM :: LDRD : case ARM :: LDRH : case ARM :: LDRSB : case ARM :: LDRSH : case ARM :: VLDRD : case ARM :: VLDRS : case ARM :: t2LDRi8 : case ARM :: t2LDRSHi8 : case ARM :: t2LDRi12 : case ARM :: t2LDRSHi12 : break ; } if ( Load1 -> getOperand ( 0 ) != Load2 -> getOperand ( 0 ) || Load1 -> getOperand ( 4 ) != Load2 -> getOperand ( 4 ) ) return false ; if ( Load1 -> getOperand ( 3 ) != Load2 -> getOperand ( 3 ) ) return false ; if ( isa < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) && isa < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) ) { Offset1 = cast < ConstantSDNode > ( Load1 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; Offset2 = cast < ConstantSDNode > ( Load2 -> getOperand ( 1 ) ) -> getSExtValue ( ) ; return true ; } return false ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s> bool MipsCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( Mips :: RetRA ) ; if ( Val != nullptr ) { return false ; } MIRBuilder . insertInstr ( Ret ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .