<s> static Mnode * add_minipool_forward_ref ( Mfix * fix ) { Mnode * max_mp = NULL ; HOST_WIDE_INT max_address = fix -> address + fix -> forwards - minipool_pad ; Mnode * mp ; if ( minipool_vector_head && ( fix -> address + get_attr_length ( fix -> insn ) >= minipool_vector_head -> max_address - fix -> fix_size ) ) return NULL ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { if ( GET_CODE ( fix -> value ) == GET_CODE ( mp -> value ) && fix -> mode == mp -> mode && ( ! LABEL_P ( fix -> value ) || ( CODE_LABEL_NUMBER ( fix -> value ) == CODE_LABEL_NUMBER ( mp -> value ) ) ) && rtx_equal_p ( fix -> value , mp -> value ) ) { mp -> refcount ++ ; return move_minipool_fix_forward_ref ( mp , max_mp , max_address ) ; } if ( max_mp == NULL && mp -> max_address > max_address ) max_mp = mp ; if ( ARM_DOUBLEWORD_ALIGN && max_mp == NULL && fix -> fix_size >= 8 && mp -> fix_size < 8 ) { max_mp = mp ; max_address = mp -> max_address ; } } mp = XNEW ( Mnode ) ; mp -> fix_size = fix -> fix_size ; mp -> mode = fix -> mode ; mp -> value = fix -> value ; mp -> refcount = 1 ; mp -> min_address = - 65536 ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp -> prev ; } return max_mp ; } </s>

Add a constant to the minipool for a forward reference . Returns the node added or NULL if the constant will not fit in this pool .


<s> RegisterBankInfo :: InstructionMapping X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : return getSameOperandsMapping ( MI , false ) ; break ; case TargetOpcode :: G_FADD : case TargetOpcode :: G_FSUB : case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : return getSameOperandsMapping ( MI , true ) ; break ; default : break ; } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return InstructionMapping ( ) ; return InstructionMapping { DefaultMappingID , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands } ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implements target hook array_mode_supported_p .


<s> virtual void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> virtual bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const LLVM_OVERRIDE { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> static void indirect_thunk_name ( char name [ 32 ] , unsigned int regno , enum indirect_thunk_prefix need_prefix , bool ret_p ) { if ( regno != INVALID_REGNUM && regno != CX_REG && ret_p ) gcc_unreachable ( ) ; if ( USE_HIDDEN_LINKONCE ) { const char * prefix ; if ( need_prefix == indirect_thunk_prefix_nt && regno != INVALID_REGNUM ) { prefix = "_nt" ; } else prefix = "" ; const char * ret = ret_p ? "return" : "indirect" ; if ( regno != INVALID_REGNUM ) { const char * reg_prefix ; if ( LEGACY_INT_REGNO_P ( regno ) ) reg_prefix = TARGET_64BIT ? "r" : "e" ; else reg_prefix = "" ; sprintf ( name , "__x86_%s_thunk%s_%s%s" , ret , prefix , reg_prefix , reg_names [ regno ] ) ; } else sprintf ( name , "__x86_%s_thunk%s" , ret , prefix ) ; } else { if ( regno != INVALID_REGNUM ) ASM_GENERATE_INTERNAL_LABEL ( name , "LITR" , regno ) ; else { if ( ret_p ) ASM_GENERATE_INTERNAL_LABEL ( name , "LRT" , 0 ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LIT" , 0 ) ; } } } </s>

Fills in the label name that should be used for the indirect thunk .


<s> static unsigned int rest_of_insert_bti ( void ) { timevar_push ( TV_MACH_DEP ) ; rtx bti_insn ; rtx_insn * insn ; basic_block bb ; bb = 0 ; FOR_EACH_BB_FN ( bb , cfun ) { for ( insn = BB_HEAD ( bb ) ; insn != NEXT_INSN ( BB_END ( bb ) ) ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - 1 ; j >= 0 ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , 0 ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch64_bti_j_insn_p ( next ) ) continue ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch64_pac_insn_p ( get_first_nonnote_insn ( ) ) ) { bti_insn = gen_bti_c ( ) ; emit_insn_before ( bti_insn , insn ) ; } } timevar_pop ( TV_MACH_DEP ) ; return 0 ; } </s>

This is implemented as a late RTL pass that runs before branch shortening and does the following .


<s> bool FPMover :: runOnMachineFunction ( MachineFunction & F ) { if ( TM . getSubtarget < SparcSubtarget > ( ) . isV9 ( ) ) return false ; bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned SystemZInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return isSimpleMove ( MI , FrameIndex , SystemZII :: SimpleBDXStore ) ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
DEBUG_FUNCTION
void
rs6000_debug_print_mode
(
ssize_t
m
)
{
ssize_t
rc
;
int
spaces
=
0
;
fprintf
(
stderr
,
"Mode: %-5s"
,
GET_MODE_NAME
(
m
)
)
;
for
(
rc
=
0
;
rc
<
N_RELOAD_REG
;
rc
++
)
fprintf
(
stderr
,
" %s: %s"
,
reload_reg_map
[
rc
]
.
name
,
rs6000_debug_addr_mask
(
reg_addr
[
m
]
.
addr_mask
[
rc
]
,
true
)
)
;
if
(
(
reg_addr
[
m
]
.
reload_store
!=
CODE_FOR_nothing
)
||
(
reg_addr
[
m
]
.
reload_load
!=
CODE_FOR_nothing
)
)
{
fprintf
(
stderr
,
"%*s  Reload=%c%c"
,
spaces
,
""
,
(
reg_addr
[
m
]
.
reload_store
!=
CODE_FOR_nothing
)
's'
:
'*'
,
(
reg_addr
[
m
]
.
reload_load
!=
CODE_FOR_nothing
)
'l'
:
'*'
)
;
spaces
=
0
;
}
else
spaces
+=
sizeof
(
"  Reload=sl"
)
1
;
if
(
reg_addr
[
m
]
.
scalar_in_vmx_p
)
{
fprintf
(
stderr
,
"%*s  Upper=y"
,
spaces
,
""
)
;
spaces
=
0
;
}
else
spaces
+=
sizeof
(
"  Upper=y"
)
1
;
if
(
rs6000_vector_unit
[
m
]
!=
VECTOR_NONE
||
rs6000_vector_mem
[
m
]
!=
VECTOR_NONE
)
{
fprintf
(
stderr
,
"%*s  vector: arith=%-10s mem=%s"
,
spaces
,
""
,
rs6000_debug_vector_unit
(
rs6000_vector_unit
[
m
]
)
,
rs6000_debug_vector_unit
(
rs6000_vector_mem
[
m
]
)
)
;
}
fputs
(
"\n"
,
stderr
)
;
}
</s>

Print the address masks in a human readble fashion .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) return new ARMHazardRecognizer ( II , DAG ) ; return TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> unsigned X86AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: EVEX ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: VEX ) return Match_Unsupported ; switch ( Opc ) { case X86 :: VCVTSD2SIZrm_Int : case X86 :: VCVTSD2SI64Zrm_Int : case X86 :: VCVTSS2SIZrm_Int : case X86 :: VCVTSS2SI64Zrm_Int : case X86 :: VCVTTSD2SIZrm : case X86 :: VCVTTSD2SIZrm_Int : case X86 :: VCVTTSD2SI64Zrm : case X86 :: VCVTTSD2SI64Zrm_Int : case X86 :: VCVTTSS2SIZrm : case X86 :: VCVTTSS2SIZrm_Int : case X86 :: VCVTTSS2SI64Zrm : case X86 :: VCVTTSS2SI64Zrm_Int : if ( ForcedVEXEncoding != VEXEncoding_EVEX ) return Match_Unsupported ; break ; } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> void addLOHDirective ( MCLOHType Kind , MILOHArgs Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args . end ( ) ) ; } </s>

Add a LOH directive of this Kind and this Args .


<s>
static
void
rs6000_sched_finish
(
FILE
*
dump
,
int
sched_verbose
)
{
int
n_groups
;
if
(
sched_verbose
)
fprintf
(
dump
,
"=== Finishing schedule.\n"
)
;
if
(
reload_completed
&&
rs6000_sched_groups
)
{
if
(
rs6000_sched_insert_nops
==
sched_finish_none
)
return
;
if
(
rs6000_sched_insert_nops
==
sched_finish_pad_groups
)
n_groups
=
pad_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
else
n_groups
=
redefine_groups
(
dump
,
sched_verbose
,
current_sched_info
->
prev_head
,
current_sched_info
->
next_tail
)
;
if
(
sched_verbose
>=
6
)
{
fprintf
(
dump
,
"ngroups = %d\n"
,
n_groups
)
;
print_rtl
(
dump
,
current_sched_info
->
prev_head
)
;
fprintf
(
dump
,
"Done finish_sched\n"
)
;
}
}
}
</s>

The following function is called at the end of scheduling BB . After reload , it inserts nops at insn group bundling .


<s> const TargetRegisterClass * PPCRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( Subtarget . hasVSX ( ) ) { if ( RC == & PPC :: F8RCRegClass ) return & PPC :: VSFRCRegClass ; else if ( RC == & PPC :: VRRCRegClass ) return & PPC :: VSRCRegClass ; } return TargetRegisterInfo :: getLargestLegalSuperClass ( RC ) ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

PowerPC PPC PPC::F8RCRegClass PPC::VSFRCRegClass PPC::VRRCRegClass PPC::VSRCRegClass


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , 0 ) , false ) ) return true ; if ( address_is_prefixed ( addr , mode , NON_PREFIXED_DS ) ) return true ; if ( TARGET_MACHO && GET_CODE ( addr ) == LO_SUM ) return darwin_rs6000_legitimate_lo_sum_const_p ( XEXP ( addr , 1 ) , mode ) ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = sext_hwi ( offset , 16 ) ; return SIGNED_16BIT_OFFSET_EXTRA_P ( offset , extra ) ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> unsigned getNumFixupKinds ( ) const override { return Mips :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAligned
}
,
{
"fixup_arm_pcrel_10"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_adr_pcrel_12"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_branch"
,
1
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_branch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAligned
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
1
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
16
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
16
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCCodeEmitter
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


Copy one MODE sized block from SRC to DST , then progress SRC and DST by MODE bytes .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) ) return AtomicExpansionKind :: None ; if ( getTargetMachine ( ) . getOptLevel ( ) == 0 ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: LLSC ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> bool PPCPassConfig :: addPreISel ( ) { if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoops ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>


<s> int mmix_initial_elimination_offset ( int fromreg , int toreg ) { int regno ; int fp_sp_offset = ( get_frame_size ( ) + crtl -> outgoing_args_size + 7 ) & ~ 7 ; if ( fromreg == MMIX_ARG_POINTER_REGNUM && toreg == MMIX_FRAME_POINTER_REGNUM ) return 0 ; for ( regno = MMIX_FIRST_GLOBAL_REGNUM ; regno <= 255 ; regno ++ ) if ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || IS_MMIX_EH_RETURN_DATA_REG ( regno ) ) fp_sp_offset += 8 ; return fp_sp_offset + ( MMIX_CFUN_HAS_LANDING_PAD ? 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? 8 : 0 ) ) + ( fromreg == MMIX_ARG_POINTER_REGNUM ? 0 : 8 ) ; } </s>

The difference between the ( imaginary ) frame pointer and the stack pointer . Used to eliminate the frame pointer .


"variadic functions must use the base AAPCS variant"

Get the PCS variant to use for this call . TYPE is the function 's type specification , DECL is the specific declartion . DECL may be null if the call could be indirect or if this is a library call .


<s> void SystemZPostRASchedStrategy :: advanceTo ( MachineBasicBlock :: iterator NextBegin ) { MachineBasicBlock :: iterator LastEmittedMI = HazardRec -> getLastEmittedMI ( ) ; MachineBasicBlock :: iterator I = ( ( LastEmittedMI != nullptr && LastEmittedMI -> getParent ( ) == MBB ) ? std :: next ( LastEmittedMI ) : MBB -> begin ( ) ) ; for ( ; I != NextBegin ; ++ I ) { if ( I -> isPosition ( ) || I -> isDebugValue ( ) ) continue ; HazardRec -> emitInstruction ( & * I ) ; } } </s>

advanceTo - Advance the specified iterator to point to the Segment containing the specified position , or end ( ) if the position is past the end of the range .


<s> static bool mips_legitimate_address_p ( machine_mode mode , rtx x , bool strict_p ) { struct mips_address_info addr ; return mips_classify_address ( & addr , x , mode , strict_p ) ; } </s>

This function is used to implement GO_IF_LEGITIMATE_ADDRESS . It returns a nonzero value if X is a legitimate address for a memory operand of the indicated MODE . STRICT is nonzero if this function is called during reload .


<s> int mmix_extra_constraint ( rtx x , int c , int strict ) { HOST_WIDEST_INT value ; if ( c == 'U' ) return strict ? strict_memory_address_p ( Pmode , x ) : memory_address_p ( Pmode , x ) ; if ( c == 'R' ) return GET_CODE ( x ) != CONST_INT && GET_CODE ( x ) != CONST_DOUBLE && mmix_constant_address_p ( x ) && ( ! TARGET_BASE_ADDRESSES || ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FLAG ( x ) ) ) ) ; if ( GET_CODE ( x ) != CONST_DOUBLE || GET_MODE ( x ) != VOIDmode ) return 0 ; value = mmix_intval ( x ) ; if ( c == 'S' ) return mmix_shiftable_wyde_value ( value ) ; else if ( c == 'T' ) return mmix_shiftable_wyde_value ( ~ value ) ; return 0 ; } </s>

EXTRA_CONSTRAINT . We need this since our constants are not always expressible as CONST_INT : s , but rather often as CONST_DOUBLE : s .


<s> static struct machine_function * ix86_init_machine_status ( void ) { struct machine_function * f ; f = ggc_cleared_alloc < machine_function > ( ) ; f -> call_abi = ix86_abi ; f -> stack_frame_required = true ; f -> silent_p = true ; return f ; } </s>

Clear stack slot assignments remembered from previous functions . This is called from INIT_EXPANDERS once before RTL is emitted for each function .


<s> static tree rs6000_builtin_reciprocal ( unsigned int fn , bool md_fn , bool sqrt ATTRIBUTE_UNUSED ) { if ( optimize_insn_for_size_p ( ) ) return NULL_TREE ; if ( md_fn ) switch ( fn ) { case VSX_BUILTIN_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_4SF ] ; default : return NULL_TREE ; } else switch ( fn ) { case BUILT_IN_SQRT : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BUILTIN_RSQRT ] ; case BUILT_IN_SQRTF : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ RS6000_BUILTIN_RSQRTF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( CMP ) ; OPCODE ( UCMP ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static void mmix_target_asm_function_prologue ( FILE * ) { cfun -> machine -> in_prologue = 1 ; } </s>

Emit the function prologue . For simplicity while the port is still in a flux , we do it as text rather than the now preferred RTL way , as ( define_insn `` function_prologue '' ) . FIXME : Translate to RTL and/or optimize some of the DWARF 2 stuff .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : case 'z' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; case 'z' : RC = & AArch64 :: ZPRRegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , AArch64 :: NoRegAltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { Register Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; if ( AArch64 :: GPR64x8ClassRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 't' , O ) ; unsigned AltName = AArch64 :: NoRegAltName ; const TargetRegisterClass * RegClass ; if ( AArch64 :: ZPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: ZPRRegClass ; } else if ( AArch64 :: PPRRegClass . contains ( Reg ) ) { RegClass = & AArch64 :: PPRRegClass ; } else { RegClass = & AArch64 :: FPR128RegClass ; AltName = AArch64 :: vreg ; } return printAsmRegInClass ( MO , RegClass , AltName , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SystemZ Comparison Elimination"
;
}
</s>

getPassName - Return a nice clean name for a pass .

SystemZ
"SystemZ Comparison Elimination"


<s> const MCPhysReg * SparcRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> static void arm_init_builtin ( unsigned int fcode , arm_builtin_datum * d , const char * prefix ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS ] = { 0 } ; char namebuf [ 60 ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - 1 ; int arg_num = d -> qualifiers [ 0 ] & qualifier_void ? op_num + 1 : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= 0 ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum arm_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ arg_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_predicate ) op_mode = HImode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; if ( qualifiers & qualifier_void_pointer ) eltype = qualifiers & qualifier_const ? const_ptr_type_node : ptr_type_node ; else { eltype = arm_simd_builtin_type ( op_mode , qualifiers ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; } if ( arg_num == 0 ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p && IN_RANGE ( fcode , ARM_BUILTIN_VFP_BASE , ARM_BUILTIN_ACLE_BASE - 1 ) ) snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s_%s" , prefix , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s" , prefix , d -> name ) ; fndecl = add_builtin_function ( namebuf , ftype , fcode , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ fcode ] = fndecl ; } </s>

Set up a builtin . It will use information stored in the argument struct D to derive the builtin 's type signature and name . It will append the name in D to the PREFIX passed and use these to create a builtin declaration that is then stored in 'arm_builtin_decls ' under index FCODE . This FCODE is also written back to D for future use .


<s> static char * detect_caches_freebsd ( void ) { unsigned l1_sizekb , l1_line , l1_assoc , l2_sizekb ; size_t len = 4 ; sysctlbyname ( "machdep.cacheline_size" , & l1_line , & len , NULL , 0 ) ; l1_sizekb = 32 ; l1_assoc = 0 ; l2_sizekb = 512 ; return describe_cache ( l1_sizekb , l1_line , l1_assoc , l2_sizekb ) ; } </s>

Returns the description of caches on FreeBSD PPC .


<s>
static
void
recombine_stvx_pattern
(
rtx_insn
*
insn
,
del_info
*
to_delete
)
{
rtx
body
=
PATTERN
(
insn
)
;
gcc_assert
(
GET_CODE
(
body
)
==
SET
&&
MEM_P
(
SET_DEST
(
body
)
)
&&
GET_CODE
(
SET_SRC
(
body
)
)
==
VEC_SELECT
)
;
rtx
mem
=
SET_DEST
(
body
)
;
rtx
base_reg
=
XEXP
(
mem
,
0
)
;
auto_vec
<
rtx_insn
*
>
and_insns
;
auto_vec
<
rtx
>
and_ops
;
bool
is_any_def_and
=
find_alignment_op
(
insn
,
base_reg
,
&
and_insns
,
&
and_ops
)
;
if
(
is_any_def_and
)
{
gcc_assert
(
and_insns
.
length
(
)
==
and_ops
.
length
(
)
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
df_ref
src_use
;
struct
df_insn_info
*
insn_info
=
DF_INSN_INFO_GET
(
insn
)
;
FOR_EACH_INSN_INFO_USE
(
src_use
,
insn_info
)
{
if
(
!
rtx_equal_p
(
DF_REF_REG
(
src_use
)
,
src_reg
)
)
continue
;
struct
df_link
*
link
=
DF_REF_CHAIN
(
src_use
)
;
if
(
!
link
||
link
->
next
)
break
;
rtx_insn
*
swap_insn
=
DF_REF_INSN
(
link
->
ref
)
;
if
(
!
insn_is_swap_p
(
swap_insn
)
||
insn_is_load_p
(
swap_insn
)
||
insn_is_store_p
(
swap_insn
)
)
break
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace
=
true
;
to_delete
[
INSN_UID
(
swap_insn
)
]
.
replace_insn
=
swap_insn
;
rtx
new_reg
=
0
;
rtx
and_mask
=
0
;
for
(
unsigned
i
=
0
;
i
<
and_insns
.
length
(
)
;
i
++
)
{
rtx_insn
*
and_insn
=
and_insns
[
i
]
;
rtx
and_op
=
and_ops
[
i
]
;
rtx
and_base
=
XEXP
(
and_op
,
0
)
;
if
(
!
new_reg
)
{
new_reg
=
gen_reg_rtx
(
GET_MODE
(
and_base
)
)
;
and_mask
=
XEXP
(
and_op
,
1
)
;
}
rtx
copy
=
gen_rtx_SET
(
new_reg
,
and_base
)
;
rtx_insn
*
new_insn
=
emit_insn_after
(
copy
,
and_insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
and_insn
)
)
;
df_insn_rescan
(
new_insn
)
;
}
XEXP
(
mem
,
0
)
=
gen_rtx_AND
(
GET_MODE
(
new_reg
)
,
new_reg
,
and_mask
)
;
SET_SRC
(
body
)
=
src_reg
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"stvx opportunity found at %d\n"
,
INSN_UID
(
insn
)
)
;
}
}
}
</s>

If INSN is the store for an stvx pattern , put it in canonical form .


<s> void rs6000_output_function_entry ( FILE * file , const char * fname ) { if ( fname [ 0 ] != '.' ) { switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , "L." ) ; break ; case ABI_V4 : case ABI_DARWIN : break ; } } if ( TARGET_AIX ) RS6000_OUTPUT_BASENAME ( file , fname ) ; else assemble_name ( file , fname ) ; } </s>


<s> bool ARMSubtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) && ! isThumb1Only ( ) ; } </s>

True if the subtarget should run the atomic expansion pass .


<s> bool isToken ( ) const { return Kind == k_Token ; } </s>


<s>
SDValue
PPCTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCRetInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCRetInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_PPC
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

PowerPC
PPC
ISD::InputArg
16
PPC
0
"Can only return in registers!"
1
2
"Unknown loc info!"
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


"FPDelta isn't aligned per the Win64 ABI!"

"VLAs and dynamic stack realign, but no FP?!"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> virtual const TeeRISCRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
SDValue
XNCMTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_XNCM
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
XNCMISD
::
RET_FLAG
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void ix86_add_reg_usage_to_vzerouppers ( void ) { basic_block bb ; rtx_insn * insn ; auto_bitmap live_regs ; df_analyze ( ) ; FOR_EACH_BB_FN ( bb , cfun ) { bitmap_copy ( live_regs , df_get_live_out ( bb ) ) ; df_simulate_initialize_backwards ( bb , live_regs ) ; FOR_BB_INSNS_REVERSE ( bb , insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( vzeroupper_pattern ( PATTERN ( insn ) , VOIDmode ) ) ix86_add_reg_usage_to_vzeroupper ( insn , live_regs ) ; df_simulate_one_insn_backwards ( bb , insn , live_regs ) ; } } } </s>

Walk the vzeroupper instructions in the function and annotate them with the effect that they have on the SSE registers .


runOnMachineFunction - Emit the function body .


<s> bool ARMAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { if ( getRelaxedOpcode ( Inst . getOpcode ( ) , STI ) != Inst . getOpcode ( ) ) return true ; return false ; } </s>


<s> void LanaiTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; } </s>

This method must be called before any actual lowering is done .


<s> static const char * ix86_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; switch ( TYPE_MODE ( type ) ) { case TFmode : return "g" ; case XFmode : return "e" ; default : return NULL ; } } </s>

Return the mangling of TYPE if it is an extended fundamental type .


<s> const char * mips_output_jump ( rtx * operands , int target_opno , int size_opno , bool link_p ) { static char buffer [ 300 ] ; char * s = buffer ; bool reg_p = REG_P ( operands [ target_opno ] ) ; const char * and_link = link_p ? "al" : "" ; const char * reg = reg_p ? "r" : "" ; const char * compact = "" ; const char * nop = "%/" ; const char * short_delay = link_p ? "%!" : "" ; const char * insn_name = TARGET_CB_NEVER || reg_p ? "j" : "b" ; if ( ! final_sequence && ( TARGET_CB_MAYBE || ( ISA_HAS_JRC && ! link_p && reg_p ) ) ) { compact = "c" ; nop = "" ; } if ( TARGET_USE_GOT && ! TARGET_EXPLICIT_RELOCS ) sprintf ( s , "%%*%s%s\t%%%d%%/" , insn_name , and_link , target_opno ) ; else { if ( ! reg_p && TARGET_ABICALLS_PIC2 ) s += sprintf ( s , ".option\tpic0\n\t" ) ; if ( reg_p && mips_get_pic_call_symbol ( operands , size_opno ) ) { s += sprintf ( s , "%%*.reloc\t1f,R_MIPS_JALR,%%%d\n1:\t" , size_opno ) ; short_delay = "" ; } else s += sprintf ( s , "%%*" ) ; s += sprintf ( s , "%s%s%s%s%s\t%%%d%s" , insn_name , and_link , reg , compact , short_delay , target_opno , nop ) ; if ( ! reg_p && TARGET_ABICALLS_PIC2 ) s += sprintf ( s , "\n\t.option\tpic2" ) ; } return buffer ; } </s>

Return the asm template for a call . OPERANDS are the operands , TARGET_OPNO is the operand number of the target . SIZE_OPNO is the operand number of the argument size operand that can optionally hold the call attributes . If SIZE_OPNO is not -1 and the call is indirect , use the function symbol from the call attributes to attach a R_MIPS_JALR relocation to the call . LINK_P indicates whether the jump is a call and needs to set the link register . When generating GOT code without explicit relocation operators , all calls should use assembly macros . Otherwise , all indirect calls should use `` jr '' or `` jalr '' ; we will arrange to restore $ gp afterwards if necessary . Finally , we can only generate direct calls for -mabicalls by temporarily switching to non-PIC mode . For microMIPS jal ( r ) , we try to generate jal ( r ) s when a 16-bit instruction is in the delay slot of jal ( r ) . Where compact branches are available , we try to use them if the delay slot has a NOP ( or equivalently delay slots were not enabled for the instruction anyway ) .


Generate RTL for 128-bit ( TImode ) subtraction with overflow . OP0 represents the TImode destination operand 0 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 UNSIGNED_P is true if the operation is being performed on unsigned values .


<s> MipsExprKind getKind ( ) const { return Kind ; } </s>


<s> void crx_expand_epilogue ( void ) { rtx return_reg ; int only_popret_RA = ( save_regs [ RETURN_ADDRESS_REGNUM ] && ( sum_regs == UNITS_PER_WORD ) ) ; return_reg = gen_rtx_REG ( Pmode , RETURN_ADDRESS_REGNUM ) ; if ( frame_pointer_needed ) emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; if ( size_for_adjusting_sp > 0 ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( size_for_adjusting_sp ) ) ) ; if ( crx_interrupt_function_p ( ) ) emit_jump_insn ( gen_interrupt_return ( ) ) ; else if ( last_reg_to_save == - 1 ) emit_jump_insn ( gen_indirect_jump_return ( ) ) ; else if ( only_popret_RA ) emit_jump_insn ( gen_popret_RA_return ( ) ) ; else emit_jump_insn ( gen_pop_and_popret_return ( GEN_INT ( sum_regs ) ) ) ; } </s>

Generate insn that updates the stack for local variables and padding for * registers we save . - Generate the appropriate return insn .


<s> static rtx_code_label * ix86_expand_sse_compare_and_jump ( enum rtx_code code , rtx op0 , rtx op1 , bool swap_operands ) { machine_mode fpcmp_mode = ix86_fp_compare_mode ( code ) ; rtx_code_label * label ; rtx tmp ; if ( swap_operands ) std :: swap ( op0 , op1 ) ; label = gen_label_rtx ( ) ; tmp = gen_rtx_REG ( fpcmp_mode , FLAGS_REG ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_COMPARE ( fpcmp_mode , op0 , op1 ) ) ) ; tmp = gen_rtx_fmt_ee ( code , VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; tmp = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; JUMP_LABEL ( tmp ) = label ; return label ; } </s>

Expands a comparison of OP0 with OP1 using comparison code CODE , swapping the operands if SWAP_OPERANDS is true . The expanded code is a forward jump to a newly created label in case the comparison is true . The generated label rtx is returned .


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; } </s>


<s> static bool general_scalar_to_vector_candidate_p ( rtx_insn * insn , enum machine_mode mode ) { rtx def_set = pseudo_reg_set ( insn ) ; if ( ! def_set ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn , mode ) ; if ( ( GET_MODE ( src ) != mode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != mode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , GET_MODE_BITSIZE ( mode ) - 1 ) ) return false ; break ; case SMAX : case SMIN : case UMAX : case UMIN : if ( ( mode == DImode && ! TARGET_AVX512VL ) || ( mode == SImode && ! TARGET_SSE4_1 ) ) return false ; case AND : case IOR : case XOR : case PLUS : case MINUS : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != mode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT ) break ; src = XEXP ( src , 0 ) ; case NOT : break ; case NEG : if ( GET_CODE ( XEXP ( src , 0 ) ) != ABS ) break ; src = XEXP ( src , 0 ) ; case ABS : if ( ( mode == DImode && ! TARGET_AVX512VL ) || ( mode == SImode && ! TARGET_SSSE3 ) ) return false ; break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != mode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; return true ; } </s>

The general version of scalar_to_vector_candidate_p .


<s> bool X86InstrInfo :: analyzeCompare ( const MachineInstr & MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI . getOpcode ( ) ) { default : break ; case X86 :: CMP64ri32 : case X86 :: CMP64ri8 : case X86 :: CMP32ri : case X86 :: CMP32ri8 : case X86 :: CMP16ri : case X86 :: CMP16ri8 : case X86 :: CMP8ri : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; return true ; case X86 :: SUB64rm : case X86 :: SUB32rm : case X86 :: SUB16rm : case X86 :: SUB8rm : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64rr : case X86 :: SUB32rr : case X86 :: SUB16rr : case X86 :: SUB8rr : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: SUB64ri32 : case X86 :: SUB64ri8 : case X86 :: SUB32ri : case X86 :: SUB32ri8 : case X86 :: SUB16ri : case X86 :: SUB16ri8 : case X86 :: SUB8ri : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = MI . getOperand ( 2 ) . getImm ( ) ; return true ; case X86 :: CMP64rr : case X86 :: CMP32rr : case X86 :: CMP16rr : case X86 :: CMP8rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case X86 :: TEST8rr : case X86 :: TEST16rr : case X86 :: TEST32rr : case X86 :: TEST64rr : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . getReg ( ) != SrcReg ) return false ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s>
static
void
mmix_output_octa
(
FILE
*
stream
,
HOST_WIDEST_INT
value
,
int
do_begin_end
)
{
char
hex_format
[
sizeof
(
HOST_WIDEST_INT_PRINT_HEX
)
]
;
if
(
do_begin_end
)
fprintf
(
stream
,
"\tOCTA "
)
;
strcpy
(
hex_format
,
HOST_WIDEST_INT_PRINT_HEX
)
;
hex_format
[
0
]
=
'#'
;
hex_format
[
1
]
=
'0'
;
if
(
(
value
<
(
HOST_WIDEST_INT
)
0
&&
value
>
(
HOST_WIDEST_INT
)
10000
)
||
(
value
>=
(
HOST_WIDEST_INT
)
0
&&
value
<=
(
HOST_WIDEST_INT
)
16384
)
)
fprintf
(
stream
,
"%d"
,
(
int
)
value
)
;
else
if
(
value
>
(
HOST_WIDEST_INT
)
0
&&
value
<
(
(
HOST_WIDEST_INT
)
1
<<
31
)
*
2
)
fprintf
(
stream
,
"#%x"
,
(
unsigned
int
)
value
)
;
else
fprintf
(
stream
,
hex_format
,
value
)
;
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Print a 64-bit value , optionally prefixed by assembly pseudo .


<s> bool AArch64FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; static const LoadStoreMethod PossibleClasses [ ] = { { & AArch64 :: GPR64RegClass , AArch64 :: LSPair64_LDR , AArch64 :: LS64_LDR } , { & AArch64 :: FPR64RegClass , AArch64 :: LSFPPair64_LDR , AArch64 :: LSFP64_LDR } , } ; const unsigned NumClasses = llvm :: array_lengthof ( PossibleClasses ) ; emitFrameMemOps ( false , MBB , MBBI , CSI , TRI , PossibleClasses , NumClasses ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static void moxie_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_or_fixed_reg_p ( regno ) ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


<s>
bool
FixupBWInstPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
FixupBWInsts
||
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
this
->
MF
=
&
MF
;
TII
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
.
getInstrInfo
(
)
;
TRI
=
MF
.
getRegInfo
(
)
.
getTargetRegisterInfo
(
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
PSI
=
&
getAnalysis
<
ProfileSummaryInfoWrapperPass
>
(
)
.
getPSI
(
)
;
MBFI
=
(
PSI
&&
PSI
->
hasProfileSummary
(
)
)
&
getAnalysis
<
LazyMachineBlockFrequencyInfoPass
>
(
)
.
getBFI
(
)
:
nullptr
;
LiveRegs
.
init
(
TII
->
getRegisterInfo
(
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupBWInsts\n"
;
)
;
for
(
auto
&
MBB
:
MF
)
processBasicBlock
(
MF
,
MBB
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupBWInsts\n"
;
)
;
return
true
;
}
</s>


<s> MachineBasicBlock :: iterator X86InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const { if ( MInfo . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( X86 :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ; } </s>

Insert a call to an outlined function into the program .


<s> bool PPCTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , unsigned CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( isVarArg ) return false ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = 0 ; i != Ins . size ( ) ; i ++ ) { ISD :: ArgFlagsTy Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

PowerPC PPC ISD::InputArg 0 ISD::ArgFlagsTy


<s>
MCSymbol
*
X86MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
const
Triple
&
TT
=
TM
.
getTargetTriple
(
)
;
if
(
MO
.
isGlobal
(
)
&&
TT
.
isOSBinFormatELF
(
)
)
return
AsmPrinter
.
getSymbolPreferLocal
(
*
MO
.
getGlobal
(
)
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
switch
(
MO
.
getTargetFlags
(
)
)
{
case
X86II
::
MO_DLLIMPORT
:
Name
+=
"__imp_"
;
break
;
case
X86II
::
MO_COFFSTUB
:
Name
+=
".refptr."
;
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
Suffix
=
"$non_lazy_ptr"
;
break
;
}
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
break
;
case
X86II
::
MO_COFFSTUB
:
{
MachineModuleInfoCOFF
&
MMICOFF
=
MF
.
getMMI
(
)
.
getObjFileInfo
<
MachineModuleInfoCOFF
>
(
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MMICOFF
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
true
)
;
}
break
;
}
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
break
;
}
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass || RC == ARM :: tcGPRRegisterClass || RC == ARM :: rGPRRegisterClass || RC == ARM :: GPRnopcRegisterClass ) { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .

ARM ARM::GPRRegisterClass ARM::tGPRRegisterClass ARM::tcGPRRegisterClass ARM::rGPRRegisterClass ARM::GPRnopcRegisterClass ARM::t2STRi12 0 ARM


<s> static bool ix86_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; if ( ix86_force_load_from_GOT_p ( x ) ) return false ; break ; CASE_CONST_SCALAR_INT : if ( ix86_endbr_immediate_operand ( x , VOIDmode ) ) return false ; switch ( mode ) { case E_TImode : if ( TARGET_64BIT ) return true ; case E_OImode : case E_XImode : if ( ! standard_sse_constant_p ( x , mode ) && GET_MODE_SIZE ( TARGET_AVX512F ? XImode : ( TARGET_AVX ? OImode : ( TARGET_SSE2 ? TImode : DImode ) ) ) < GET_MODE_SIZE ( mode ) ) return false ; default : break ; } break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> bool PPCPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
StringRef
getPassName
(
)
const
override
{
return
"PPC Generate Scalar MASS Entries"
;
}
</s>

getPassName - Return a nice clean name for a pass .

PowerPC
"PPC Generate Scalar MASS Entries"


"********** ARM MVE VPT Optimisations **********\n"

runOnMachineFunction - Emit the function body .


<s> int function_arg_boundary ( enum machine_mode mode , tree type ) { if ( DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE ( mode ) == 8 ) return 64 ; else if ( SPE_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= 8 && int_size_in_bytes ( type ) < 16 ) ) return 64 ; else if ( ALTIVEC_VECTOR_MODE ( mode ) || ( type && TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) >= 16 ) ) return 128 ; else if ( rs6000_darwin64_abi && mode == BLKmode && type && TYPE_ALIGN ( type ) > 64 ) return 128 ; else return PARM_BOUNDARY ; } </s>

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs to be double word aligned . Doubleword align SPE vectors . Quadword align Altivec vectors . Quadword align large synthetic vector types .


<s> bool X86TargetLowering :: isVectorClearMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const { unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == 2 ) return true ; if ( NumElts == 4 && VT . is128BitVector ( ) ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasFp256 ( ) ) || isSHUFPMask ( Mask , VT , Subtarget -> hasFp256 ( ) , true ) ) ; } return false ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < SystemZSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( ! isDarwin ( ) ) { if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; } else { if ( IDVal == ".machine" ) return ParseDarwinDirectiveMachine ( DirectiveID . getLoc ( ) ) ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void X86PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( new X86ExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createX86IndirectBranchTrackingPass ( ) ) ; addPass ( createX86IssueVZeroUpperPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupBWInsts ( ) ) ; addPass ( createX86PadShortFunctions ( ) ) ; addPass ( createX86FixupLEAs ( ) ) ; } addPass ( createX86EvexToVexInsts ( ) ) ; addPass ( createX86DiscriminateMemOpsPass ( ) ) ; addPass ( createX86InsertPrefetchPass ( ) ) ; addPass ( createX86InsertX87waitPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> SDValue ARMTargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { if ( N -> getOpcode ( ) != ISD :: SDIV ) return SDValue ( ) ; const auto & ST = static_cast < const ARMSubtarget & > ( DAG . getSubtarget ( ) ) ; const bool MinSize = ST . hasMinSize ( ) ; const bool HasDivide = ST . isThumb ( ) ? ST . hasDivideInThumbMode ( ) : ST . hasDivideInARMMode ( ) ; if ( N -> getOperand ( 0 ) . getValueType ( ) . isVector ( ) ) return SDValue ( ) ; if ( ! ( MinSize && HasDivide ) ) return SDValue ( ) ; if ( ! ST . isThumb ( ) ) return SDValue ( N , 0 ) ; if ( Divisor . sgt ( 128 ) ) return SDValue ( ) ; return SDValue ( N , 0 ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s>
unsigned
ARM64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
{
assert
(
MO
.
isImm
(
)
&&
"did not expect relocated expression"
)
;
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
0
&&
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


Targets may add passes immediately before machine code is emitted in this callback .


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_SPE ) ? RS6000_BTM_SPE : 0 ) | ( ( TARGET_PAIRED_FLOAT ) ? RS6000_BTM_PAIRED : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : 0 ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : 0 ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : 0 ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 ) ? RS6000_BTM_LDBL128 : 0 ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s> static void arm_init_mve_builtins ( void ) { volatile unsigned int i , fcode = ARM_BUILTIN_MVE_PATTERN_START ; arm_init_simd_builtin_scalar_types ( ) ; arm_init_simd_builtin_types ( ) ; tree get_fpscr_nzcvqc = build_function_type_list ( intSI_type_node , NULL ) ; tree set_fpscr_nzcvqc = build_function_type_list ( void_type_node , intSI_type_node , NULL ) ; arm_builtin_decls [ ARM_BUILTIN_GET_FPSCR_NZCVQC ] = add_builtin_function ( "__builtin_arm_get_fpscr_nzcvqc" , get_fpscr_nzcvqc , ARM_BUILTIN_GET_FPSCR_NZCVQC , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ ARM_BUILTIN_SET_FPSCR_NZCVQC ] = add_builtin_function ( "__builtin_arm_set_fpscr_nzcvqc" , set_fpscr_nzcvqc , ARM_BUILTIN_SET_FPSCR_NZCVQC , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = 0 ; i < ARRAY_SIZE ( mve_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & mve_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_mve" ) ; } } </s>

Set up all the MVE builtins mentioned in arm_mve_builtins.def file .


<s> Align ARMTargetLowering :: getABIAlignmentForCallingConv ( Type * ArgTy , DataLayout DL ) const { const Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ; return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ; } </s>

Return the correct alignment for the current calling convention .


"density %d%%, cost %d exceeds threshold, penalizing "

Test for likely overcommitment of vector hardware resources . If a loop iteration is relatively large , and too large a percentage of instructions in the loop are vectorized , the cost model may not adequately reflect delays from unavailable vector resources . Penalize the loop body cost for this case .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_bl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> bool sh_split_movrt_negc_to_movt_xor ( rtx_insn * curr_insn , rtx operands [ ] ) { if ( ! can_create_pseudo_p ( ) ) return false ; set_of_reg t_before_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , prev_nonnote_insn_bb ) ; set_of_reg t_after_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , next_nonnote_insn_bb ) ; if ( t_before_negc . set_rtx != NULL_RTX && t_after_negc . set_rtx != NULL_RTX && rtx_equal_p ( t_before_negc . set_rtx , t_after_negc . set_rtx ) && ! reg_used_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_insn_operands_modified_between_p ( t_before_negc . insn , t_before_negc . insn , t_after_negc . insn ) && ! modified_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_unspec_insn_p ( t_after_negc . insn ) && ! volatile_insn_p ( PATTERN ( t_after_negc . insn ) ) && ! side_effects_p ( PATTERN ( t_after_negc . insn ) ) && ! may_trap_or_fault_p ( PATTERN ( t_after_negc . insn ) ) ) { emit_insn ( gen_movrt_xor ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; set_insn_deleted ( t_after_negc . insn ) ; return true ; } else return false ; } </s>

Given the current insn , which is assumed to be a movrt_negc insn , try to figure out whether it should be converted into a movt-xor sequence in the movrt_negc splitter . Returns true if insns have been modified and the splitter has succeeded .


<s> rtx rs6000_address_for_altivec ( rtx x ) { gcc_assert ( MEM_P ( x ) ) ; if ( ! altivec_indexed_or_indirect_operand ( x , GET_MODE ( x ) ) ) { rtx addr = XEXP ( x , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indexed_address_p ( addr , strict_p ) && ! legitimate_indirect_address_p ( addr , strict_p ) ) addr = copy_to_mode_reg ( Pmode , addr ) ; addr = gen_rtx_AND ( Pmode , addr , GEN_INT ( - 16 ) ) ; x = change_address ( x , GET_MODE ( x ) , addr ) ; } return x ; } </s>

Given a memory reference , if it is not in the form for altivec memory reference instructions ( i.e . reg or reg+reg addressing with AND of -16 ) , convert to the altivec format .


<s> void iq2000_expand_epilogue ( void ) { HOST_WIDE_INT tsize = cfun -> machine -> total_size ; rtx tsize_rtx = GEN_INT ( tsize ) ; rtx tmp_rtx = ( rtx ) 0 ; if ( iq2000_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } if ( tsize > 32767 ) { tmp_rtx = gen_rtx_REG ( Pmode , IQ2000_TEMP1_REGNUM ) ; emit_move_insn ( tmp_rtx , tsize_rtx ) ; tsize_rtx = tmp_rtx ; } if ( tsize > 0 ) { if ( frame_pointer_needed ) { emit_insn ( gen_blockage ( ) ) ; emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } save_restore_insns ( 0 ) ; if ( crtl -> calls_eh_return ) { rtx eh_ofs = EH_RETURN_STACKADJ_RTX ; emit_insn ( gen_addsi3 ( eh_ofs , eh_ofs , tsize_rtx ) ) ; tsize_rtx = eh_ofs ; } emit_insn ( gen_blockage ( ) ) ; if ( tsize != 0 || crtl -> calls_eh_return ) { emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , tsize_rtx ) ) ; } } if ( crtl -> calls_eh_return ) { emit_move_insn ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) , stack_pointer_rtx ) ; emit_use ( gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ) ; emit_jump_insn ( gen_eh_return_internal ( ) ) ; } else emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , GP_REG_FIRST + 31 ) ) ) ; } </s>

Expand the epilogue into a bunch of separate insns .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


"\taddl r14 = @ltoff(@fptr(_mcount)), r1\n"

"\tbr.call.sptk.many b0 = _mcount\n\t;;\n"


"Can only put epilog before 'retl' instruction!"


<s> bool X86PassConfig :: addPostFastRegAllocRewrite ( ) { addPass ( createX86FastTileConfigPass ( ) ) ; return true ; } </s>

addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast register allocation is complete .


<s> unsigned Cpu0RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? ( Cpu0 :: FP ) : ( Cpu0 :: SP ) ; } </s>


<s> bool X86RegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? ( const TargetRegisterClass * ) & X86 :: GR64RegClass : ( const TargetRegisterClass * ) & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static void mips_init_builtins ( void ) { const struct mips_builtin_description * d ; unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) { d = & mips_builtins [ i ] ; if ( d -> avail ( ) ) { mips_builtin_decls [ i ] = add_builtin_function ( d -> name , mips_build_function_type ( d -> function_type ) , i , BUILT_IN_MD , NULL , NULL ) ; if ( mips_builtin_decls [ i ] && d -> is_pure ) DECL_PURE_P ( mips_builtin_decls [ i ] ) = 1 ; mips_get_builtin_decl_index [ d -> icode ] = i ; } } } </s>

Init builtin functions . This is called from TARGET_INIT_BUILTIN .


<s> unsigned getRsaSize ( ) const { return 176 ; } </s>

Get the size of RSA , return address , and frame pointer as described in VEFrameLowering.cpp .


<s> void pa_encode_label ( rtx sym ) { const char * str = XSTR ( sym , 0 ) ; int len = strlen ( str ) + 1 ; char * newstr , * p ; p = newstr = XALLOCAVEC ( char , len + 1 ) ; * p ++ = '@' ; strcpy ( p , str ) ; XSTR ( sym , 0 ) = ggc_alloc_string ( newstr , len ) ; } </s>

In HPUX 8.0 's shared library scheme , special relocations are needed for function labels if they might be passed to a function in a shared library ( because shared libraries do n't live in code space ) , and special magic is needed to construct their address .


<s> void ix86_call_abi_override ( const_tree fndecl ) { if ( fndecl == NULL_TREE ) cfun -> machine -> call_abi = ix86_abi ; else cfun -> machine -> call_abi = ix86_function_type_abi ( TREE_TYPE ( fndecl ) ) ; } </s>

Implementation of call abi switching target hook . Specific to FNDECL the specific call register sets are set . See also ix86_conditional_register_usage for more details .


<s> bool MipsRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { return PhysReg == Mips :: ZERO || PhysReg == Mips :: ZERO_64 || PhysReg == Mips :: CNULL ; } </s>

Returns true if PhysReg is unallocatable and constant throughout the function .

Mips Mips Mips::ZERO Mips::ZERO_64 Mips::CNULL


<s>
void
ARMInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
ARMFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
AFI
->
isThumbFunction
(
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
false
,
false
,
isKill
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
else
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
STR
)
)
.
addReg
(
SrcReg
,
false
,
false
,
isKill
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTD
)
)
.
addReg
(
SrcReg
,
false
,
false
,
isKill
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
SPRRegisterClass
&&
"Unknown regclass!"
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FSTS
)
)
.
addReg
(
SrcReg
,
false
,
false
,
isKill
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM
ARM::GPRRegisterClass
ARM
ARM
ARM::tSpill
0
ARM::STR
0
0
ARM::DPRRegisterClass
ARM::FSTD
0
ARM::SPRRegisterClass
"Unknown regclass!"
ARM::FSTS
0


<s> int nds32_adjust_insn_length ( rtx_insn * insn , int length ) { int adjust_value = 0 ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_call_internal : case CODE_FOR_call_value_internal : { if ( NDS32_ALIGN_P ( ) ) { rtx_insn * next_insn = next_active_insn ( insn ) ; if ( next_insn && get_attr_length ( next_insn ) != 2 ) adjust_value += 2 ; } if ( find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) { if ( TARGET_16_BIT ) adjust_value += 2 ; else adjust_value += 4 ; } } return length + adjust_value ; default : return length ; } } </s>

Computing the Length of an Insn . Modifies the length assigned to instruction INSN . LEN is the initially computed length of the insn .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . getMMI ( ) . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI -> getObjectOffset ( I ) ) ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI -> CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; MF . getWinEHFuncInfo ( ) -> UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static void nds32_encode_section_info ( tree decl , rtx rtl , int new_decl_p ) { default_encode_section_info ( decl , rtl , new_decl_p ) ; if ( MEM_P ( rtl ) && MEM_READONLY_P ( rtl ) ) { rtx addr = XEXP ( rtl , 0 ) ; if ( GET_CODE ( addr ) == SYMBOL_REF ) { SYMBOL_REF_FLAGS ( addr ) |= NDS32_SYMBOL_FLAG_RODATA ; } else if ( GET_CODE ( addr ) == CONST && GET_CODE ( XEXP ( addr , 0 ) ) == PLUS ) { rtx plus_op = XEXP ( addr , 0 ) ; rtx op0 = XEXP ( plus_op , 0 ) ; rtx op1 = XEXP ( plus_op , 1 ) ; if ( GET_CODE ( op0 ) == SYMBOL_REF && CONST_INT_P ( op1 ) ) SYMBOL_REF_FLAGS ( op0 ) |= NDS32_SYMBOL_FLAG_RODATA ; } } } </s>

If references to a symbol or a constant must be treated differently depending on something about the variable or function named by the symbol ( such as what section it is in ) , we use this hook to store flags in symbol_ref rtx .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! EnablePPCPreinc ) return false ; SDValue Ptr ; MVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { ST = ST ; Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> static const unsigned * lookup ( unsigned opcode , unsigned domain ) { for ( unsigned i = 0 , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - 1 ] == opcode ) return ReplaceableInstrs [ i ] ; return 0 ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> bool ARMFastISel :: isTypeLegal ( const Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > 128 ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ; return ( Subtarget -> hasLSE ( ) && Size < 128 ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: LLSC ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static HOST_WIDE_INT sparc_compute_frame_size ( HOST_WIDE_INT size , int leaf_function ) { HOST_WIDE_INT frame_size , apparent_frame_size ; int args_size , n_global_fp_regs = 0 ; bool save_local_in_regs_p = false ; unsigned int i ; if ( leaf_function && ! cfun -> calls_alloca ) args_size = 0 ; else args_size = crtl -> outgoing_args_size + REG_PARM_STACK_SPACE ( cfun -> decl ) ; if ( TARGET_ARCH64 ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_global_or_fp_reg_p ( i , 0 ) ) n_global_fp_regs += 2 ; } else { for ( i = 0 ; i < 8 ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; } if ( TARGET_FLAT ) for ( i = 16 ; i < 32 ; i ++ ) if ( save_local_or_in_reg_p ( i , leaf_function ) ) { save_local_in_regs_p = true ; break ; } for ( i = 32 ; i < ( TARGET_V9 ? 96 : 64 ) ; i += 2 ) if ( save_global_or_fp_reg_p ( i , 0 ) || save_global_or_fp_reg_p ( i + 1 , 0 ) ) n_global_fp_regs += 2 ; if ( size == 0 && n_global_fp_regs == 0 && args_size == 0 && ! save_local_in_regs_p ) frame_size = apparent_frame_size = 0 ; else { apparent_frame_size = ROUND_UP ( size , 8 ) + n_global_fp_regs * 4 ; frame_size = apparent_frame_size + ROUND_UP ( args_size , 8 ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; } sparc_frame_size = frame_size ; sparc_apparent_frame_size = apparent_frame_size ; sparc_n_global_fp_regs = n_global_fp_regs ; sparc_save_local_in_regs_p = save_local_in_regs_p ; return frame_size ; } </s>

Compute the frame size required by the function . This function is called during the reload pass and also by sparc_expand_prologue .


<s>
unsigned
getReg
(
)
const
{
assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;
return
Contents
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> void AArch64WinCOFFStreamer :: finishImpl ( ) { emitFrames ( nullptr ) ; emitWindowsUnwindTables ( ) ; MCWinCOFFStreamer :: finishImpl ( ) ; } </s>


<s> static void rs6000_darwin64_record_arg_recurse ( CUMULATIVE_ARGS * cum , const_tree type , HOST_WIDE_INT startbitpos , rtx rvec [ ] , int * k ) { tree f ; for ( f = TYPE_FIELDS ( type ) ; f ; f = DECL_CHAIN ( f ) ) if ( TREE_CODE ( f ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; tree ftype = TREE_TYPE ( f ) ; machine_mode mode ; if ( ftype == error_mark_node ) continue ; mode = TYPE_MODE ( ftype ) ; if ( DECL_SIZE ( f ) != 0 && tree_fits_uhwi_p ( bit_position ( f ) ) ) bitpos += int_bit_position ( f ) ; if ( TREE_CODE ( ftype ) == RECORD_TYPE ) rs6000_darwin64_record_arg_recurse ( cum , ftype , bitpos , rvec , k ) ; else if ( cum -> named && USE_FP_FOR_ARG_P ( cum , mode ) ) { unsigned n_fpreg = ( GET_MODE_SIZE ( mode ) + 7 ) >> 3 ; switch ( mode ) { case E_SCmode : mode = SFmode ; break ; case E_DCmode : mode = DFmode ; break ; case E_TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; if ( cum -> fregno + n_fpreg > FP_ARG_MAX_REG + 1 ) { gcc_assert ( cum -> fregno == FP_ARG_MAX_REG && ( mode == TFmode || mode == TDmode ) ) ; mode = DECIMAL_FLOAT_MODE_P ( mode ) ? DDmode : DFmode ; cum -> use_stack = 1 ; } rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( FLOAT128_2REG_P ( mode ) ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , 1 ) ) { rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> vregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; } else if ( cum -> intoffset == - 1 ) cum -> intoffset = bitpos ; } } </s>


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void X86TileConfig :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { if ( ExtVal . getValueType ( ) . isScalableVector ( ) ) return true ; return false ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s>
void
rs6000_aix_asm_output_dwarf_table_ref
(
char
*
frame_table_label
)
{
fprintf
(
asm_out_file
,
"\t.ref %s\n"
,
(
*
targetm
.
strip_name_encoding
)
(
frame_table_label
)
)
;
}
</s>

Issue assembly directives that create a reference to the given DWARF FRAME_TABLE_LABEL from the current function section .


<s> void SystemZELFFrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const SystemZInstrInfo * TII = static_cast < const SystemZInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ObjectsToAllocate . size ( ) <= 1 ) return ; SZFrameObjVec SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectSize = MFI . getObjectSize ( Obj ) ; } for ( auto & MBB : MF ) for ( auto & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; for ( unsigned I = 0 , E = MI . getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI . getOperand ( I ) ; if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) { if ( TII -> hasDisplacementPairInsn ( MI . getOpcode ( ) ) ) SortingObjects [ Index ] . DPairCount ++ ; else if ( ! ( MI . getDesc ( ) . TSFlags & SystemZII :: Has20BitOffset ) ) SortingObjects [ Index ] . D12Count ++ ; } } } auto CmpD12 = [ ] ( const SZFrameSortingObj & A , const SZFrameSortingObj & B ) { if ( ! A . IsValid || ! B . IsValid ) return A . IsValid ; if ( ! A . ObjectSize || ! B . ObjectSize ) return A . ObjectSize > 0 ; uint64_t ADensityCmp = A . D12Count * B . ObjectSize ; uint64_t BDensityCmp = B . D12Count * A . ObjectSize ; if ( ADensityCmp != BDensityCmp ) return ADensityCmp < BDensityCmp ; return A . DPairCount * B . ObjectSize < B . DPairCount * A . ObjectSize ; } ; std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , CmpD12 ) ; unsigned Idx = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ Idx ++ ] = Obj . ObjectIndex ; } } </s>


<s> static reg_class_t mmix_preferred_reload_class ( rtx x , reg_class_t rclass ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ? REMAINDER_REG : rclass ; } </s>

PREFERRED_RELOAD_CLASS . We need to extend the reload class of REMAINDER_REG and HIMULT_REG .


<s> int const_ok_for_arm ( HOST_WIDE_INT i ) { int lowbit ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != 0 && ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != ( ( ~ ( unsigned HOST_WIDE_INT ) 0 ) & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) ) ) return FALSE ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xff ) == 0 ) return TRUE ; lowbit = ( ffs ( ( int ) i ) - 1 ) & ~ 1 ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) 0xff ) << lowbit ) ) == 0 ) return TRUE ; else if ( lowbit <= 4 && ( ( i & ~ 0xc000003f ) == 0 || ( i & ~ 0xf000000f ) == 0 || ( i & ~ 0xfc000003 ) == 0 ) ) return TRUE ; return FALSE ; } </s>

Return TRUE if int I is a valid immediate ARM constant .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s>
const
char
*
CSKYTargetLowering
::
getTargetNodeName
(
unsigned
Opcode
)
const
{
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"unknown CSKYISD node"
)
;
case
CSKYISD
::
NIE
:
return
"CSKYISD::NIE"
;
case
CSKYISD
::
NIR
:
return
"CSKYISD::NIR"
;
case
CSKYISD
::
RET
:
return
"CSKYISD::RET"
;
case
CSKYISD
::
CALL
:
return
"CSKYISD::CALL"
;
case
CSKYISD
::
CALLReg
:
return
"CSKYISD::CALLReg"
;
case
CSKYISD
::
TAIL
:
return
"CSKYISD::TAIL"
;
case
CSKYISD
::
TAILReg
:
return
"CSKYISD::TAILReg"
;
case
CSKYISD
::
LOAD_ADDR
:
return
"CSKYISD::LOAD_ADDR"
;
case
CSKYISD
::
BITCAST_TO_LOHI
:
return
"CSKYISD::BITCAST_TO_LOHI"
;
case
CSKYISD
::
BITCAST_FROM_LOHI
:
return
"CSKYISD::BITCAST_FROM_LOHI"
;
}
}
</s>

getTargetNodeName - This method returns the name of a target specific

CSKY
CSKY
"unknown CSKYISD node"
CSKYISD::NIE
"CSKYISD::NIE"
CSKYISD::NIR
"CSKYISD::NIR"
CSKYISD::RET
"CSKYISD::RET"
CSKYISD::CALL
"CSKYISD::CALL"
CSKYISD::CALLReg
"CSKYISD::CALLReg"
CSKYISD::TAIL
"CSKYISD::TAIL"
CSKYISD::TAILReg
"CSKYISD::TAILReg"
CSKYISD::LOAD_ADDR
"CSKYISD::LOAD_ADDR"
CSKYISD::BITCAST_TO_LOHI
"CSKYISD::BITCAST_TO_LOHI"
CSKYISD::BITCAST_FROM_LOHI
"CSKYISD::BITCAST_FROM_LOHI"


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; SystemZMachineFunctionInfo * ZFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( "backchain" ) ; if ( ! usePackedStack ( MF ) || BackChain ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = 0 ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , Align ( 8 ) , false ) ) ; } if ( MF . front ( ) . isLiveIn ( SystemZ :: R6D ) && ZFI -> getRestoreGPRRegs ( ) . LowGPR != SystemZ :: R6D ) for ( auto & MO : MRI -> use_nodbg_operands ( SystemZ :: R6D ) ) MO . setIsKill ( false ) ; } </s>


<s> void AArch64PassConfig :: addPreRegBankSelect ( ) { bool IsOptNone = getOptLevel ( ) == CodeGenOpt :: None ; if ( ! IsOptNone ) addPass ( createAArch64PostLegalizerCombiner ( IsOptNone ) ) ; addPass ( createAArch64PostLegalizerLowering ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s> function_symbol_result function_symbol ( rtx target , const char * name , sh_function_kind kind ) { if ( kind != FUNCTION_ORDINARY ) name = IDENTIFIER_POINTER ( get_identifier ( name ) ) ; rtx sym = gen_rtx_SYMBOL_REF ( Pmode , name ) ; rtx lab = const0_rtx ; SYMBOL_REF_FLAGS ( sym ) = SYMBOL_FLAG_FUNCTION ; if ( flag_pic ) switch ( kind ) { case FUNCTION_ORDINARY : break ; case SFUNC_GOT : { rtx reg = target ? target : gen_reg_rtx ( Pmode ) ; emit_insn ( gen_symGOT2reg ( reg , sym ) ) ; sym = reg ; break ; } case SFUNC_STATIC : { rtx reg = target ? target : gen_reg_rtx ( Pmode ) ; if ( TARGET_FDPIC ) { lab = PATTERN ( gen_call_site ( ) ) ; emit_insn ( gen_sym_label2reg ( reg , sym , lab ) ) ; } else { emit_insn ( gen_symGOTOFF2reg ( reg , sym ) ) ; } sym = reg ; break ; } } if ( target && sym != target ) { emit_move_insn ( target , sym ) ; return function_symbol_result ( target , lab ) ; } return function_symbol_result ( sym , lab ) ; } </s>

Return an RTX pair for the address and call site label of a function NAME of kind KIND , placing the result in TARGET if not NULL . For SFUNC_STATIC , if FDPIC , the LAB member of result will be set to ( const_int 0 ) if jsr should be used , or a label_ref if bsrf should be used . For FDPIC , both SFUNC_GOT and SFUNC_STATIC will return the address of the function itself , not a function descriptor , so they can only be used with functions not using the FDPIC register that are known to be called directory without a PLT entry .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>


<s> bool isTarget64BitLP64 ( ) const { return In64BitMode && ( TargetTriple . getEnvironment ( ) != Triple :: GNUX32 && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s> rtx mips_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( valtype ) { tree fields [ 2 ] ; int unsignedp ; mode = TYPE_MODE ( valtype ) ; unsignedp = TYPE_UNSIGNED ( valtype ) ; mode = promote_mode ( valtype , mode , & unsignedp , 1 ) ; switch ( mips_fpr_return_fields ( valtype , fields ) ) { case 1 : return gen_rtx_REG ( mode , FP_RETURN ) ; case 2 : return mips_return_fpr_pair ( mode , TYPE_MODE ( TREE_TYPE ( fields [ 0 ] ) ) , int_byte_position ( fields [ 0 ] ) , TYPE_MODE ( TREE_TYPE ( fields [ 1 ] ) ) , int_byte_position ( fields [ 1 ] ) ) ; } if ( mips_return_in_msb ( valtype ) ) { HOST_WIDE_INT size = int_size_in_bytes ( valtype ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } if ( mips_abi != ABI_EABI && ! FLOAT_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , GP_RETURN ) ; } if ( ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE ) return gen_rtx_REG ( mode , FP_RETURN ) ; if ( mode == TFmode ) return mips_return_fpr_pair ( mode , DImode , 0 , DImode , GET_MODE_SIZE ( mode ) / 2 ) ; if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( mode ) <= UNITS_PER_HWFPVALUE * 2 ) return mips_return_fpr_pair ( mode , GET_MODE_INNER ( mode ) , 0 , GET_MODE_INNER ( mode ) , GET_MODE_SIZE ( mode ) / 2 ) ; return gen_rtx_REG ( mode , GP_RETURN ) ; } </s>

Implement FUNCTION_VALUE and LIBCALL_VALUE . For normal calls , VALTYPE is the return type and MODE is VOIDmode . For libcalls , VALTYPE is null and MODE is the mode of the return value .