<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
Orig
.
modifiesRegister
(
X86
::
EFLAGS
,
&
TRI
)
;
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
add
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; bool isLoad = true ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; isLoad = false ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Base , Offset , DAG ) ) { bool Swap = false ; if ( isa < FrameIndexSDNode > ( Base ) || isa < RegisterSDNode > ( Base ) ) Swap = true ; else if ( ! isLoad ) { SDValue Val = cast < StoreSDNode > ( N ) -> getValue ( ) ; if ( Val == Base || Base . getNode ( ) -> isPredecessorOf ( Val . getNode ( ) ) ) Swap = true ; } if ( Swap ) std :: swap ( Base , Offset ) ; AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , false ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG , true ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> bool MipsSETargetLowering :: isEligibleForTailCallOptimization ( const CCState & CCInfo , unsigned NextStackOffset , const MipsFunctionInfo & FI ) const { if ( ! UseMipsTailCalls ) return false ; if ( FI . isISR ( ) ) return false ; if ( CCInfo . getInRegsParamsCount ( ) > 0 || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ; } </s>

Returns true if the call can be lowered as a tail call .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> void AArch64TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: Win64 ) ; F -> addParamAttr ( 0 , Attribute :: AttrKind :: InReg ) ; } return ; } TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Align , RTLIB :: MEMSET ) ; } </s>

Emit target-specific code that performs a memset .


<s> static void aarch64_override_options_after_change ( void ) { if ( flag_omit_frame_pointer ) flag_omit_leaf_frame_pointer = false ; else if ( flag_omit_leaf_frame_pointer ) flag_omit_frame_pointer = true ; } </s>


<s> bool ARMPassConfig :: addPreEmitPass ( ) { if ( getARMSubtarget ( ) . isThumb2 ( ) ) { if ( ! getARMSubtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; } if ( FlagSfiDisableCP ) { assert ( getARMSubtarget ( ) . useMovt ( ) ) ; } addPass ( createARMConstantIslandPass ( ) ) ; if ( getARMSubtarget ( ) . isTargetNaCl ( ) ) { addPass ( createARMNaClRewritePass ( ) ) ; } return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> int Cpu0AsmParser :: tryParseRegister ( StringRef Mnemonic ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) { RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; } else { return RegNum ; } return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> static rtx crx_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , CRX_STRUCT_VALUE_REGNUM ) ; } </s>

Implements hook TARGET_STRUCT_VALUE_RTX .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s> const Thumb2RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void X86InsertPrefetch :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool mips_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM ) ; } </s>

Make sure that we 're not trying to eliminate to the wrong hard frame pointer .


<s> static const char * fp_const_from_val ( REAL_VALUE_TYPE * r ) { if ( ! fp_consts_inited ) init_fp_table ( ) ; gcc_assert ( real_equal ( r , & value_fp0 ) ) ; return "0" ; } </s>

As for fp_immediate_constant , but value is passed directly , not in rtx .


<s> void set ( size_type Idx ) { V . set ( Idx ) ; } </s>

Set the generated scalar V for Def and the given Instance .


<s> bool runOnMachineFunction ( MachineFunction & F ) { bool Changed = false ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>


Targets may add passes immediately before machine code is emitted in this callback .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_VE
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
BCvt
:
{
assert
(
VA
.
getLocVT
(
)
==
MVT
::
i64
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f32
)
;
SDValue
Undef
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
IMPLICIT_DEF
,
DL
,
MVT
::
i64
)
,
0
)
;
SDValue
Sub_f32
=
DAG
.
getTargetConstant
(
VE
::
sub_f32
,
DL
,
MVT
::
i32
)
;
OutVal
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
INSERT_SUBREG
,
DL
,
MVT
::
i64
,
Undef
,
OutVal
,
Sub_f32
)
,
0
)
;
break
;
}
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool PPCFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { return ( MF . getSubtarget < PPCSubtarget > ( ) . isSVR4ABI ( ) && MF . getSubtarget < PPCSubtarget > ( ) . isPPC64 ( ) ) ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s> TargetLowering :: ConstraintType SystemZTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'a' : case 'd' : case 'f' : case 'h' : case 'r' : case 'v' : return C_RegisterClass ; case 'Q' : case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : return C_Other ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>


<s> unsigned MipsTargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , CC , VT ) ; IntermediateVT = RegisterVT ; NumIntermediates = VT . getSizeInBits ( ) < RegisterVT . getSizeInBits ( ) ? VT . getVectorNumElements ( ) : VT . getSizeInBits ( ) / RegisterVT . getSizeInBits ( ) ; return NumIntermediates ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MCSymbol * LanaiMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { unsigned Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x18 , 257 ) ; } return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> static SDValue WidenVector ( SDValue V64Reg , SelectionDAG & DAG ) { EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = MVT :: getVectorVT ( EltTy , 2 * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( ISD :: INSERT_SUBVECTOR , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isPSHUFDMask ( M , SVT ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> int pa_mem_shadd_constant_p ( int val ) { if ( val == 2 || val == 4 || val == 8 ) return 1 ; else return 0 ; } </s>

Return 1 if the given constant is 2 , 4 , or 8 . These are the valid constants for a MULT embedded inside a memory address .


"No MachineFunctionInfo for this function!"


<s> bool PPCTargetMachine :: addPreEmitPass ( PassManagerBase & PM , bool Fast ) { PM . add ( createPPCBranchSelectionPass ( ) ) ; return false ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool rs6000_secondary_reload_move ( enum rs6000_reg_type to_type , enum rs6000_reg_type from_type , machine_mode mode , secondary_reload_info * sri , bool altivec_p ) { if ( to_type == NO_REG_TYPE || from_type == NO_REG_TYPE ) return false ; if ( ( to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE ) || ( to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( from_type ) ) || ( from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( to_type ) ) ) return true ; if ( to_type == from_type && IS_STD_REG_TYPE ( to_type ) ) return true ; if ( rs6000_secondary_reload_simple_move ( to_type , from_type , mode ) ) { if ( sri ) { sri -> icode = CODE_FOR_nothing ; sri -> extra_cost = 0 ; } return true ; } return rs6000_secondary_reload_direct_move ( to_type , from_type , mode , sri , altivec_p ) ; } </s>

Return whether a move between two register classes can be done either directly ( simple move ) or via a pattern that uses a single extra temporary ( using power8 's direct move in this case .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getX86TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool isLabel ( ) const { if ( ! isImm ( ) ) return false ; if ( dyn_cast < MCSymbolRefExpr > ( Imm . Val ) ) { return true ; } else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Val = CE -> getValue ( ) ; int64_t Min = - ( scale * ( 1LL << ( field_width - 1 ) ) ) ; int64_t Max = scale * ( ( 1LL << ( field_width - 1 ) ) - 1 ) ; return ( Val % scale ) == 0 && Val >= Min && Val <= Max ; } return false ; } </s>

Returns true if the MachineInstr represents a label .


<s> static bool pa_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == 8 ? "\t.dword\tP%" : "\t.word\tP%" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . This code handles aligned SI and DI integers specially , since function references must be preceded by P % .


<s> int SparcSubtarget :: getAdjustedFrameSize ( int frameSize ) const { if ( is64Bit ( ) ) { frameSize += 128 ; frameSize = RoundUpToAlignment ( frameSize , 16 ) ; } else { frameSize += 92 ; frameSize = RoundUpToAlignment ( frameSize , 8 ) ; } return frameSize ; } </s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


<s>
void
i386_pe_assemble_visibility
(
tree
decl
,
int
)
{
if
(
!
decl
||
!
lookup_attribute
(
"visibility"
,
DECL_ATTRIBUTES
(
decl
)
)
)
return
;
if
(
!
DECL_ARTIFICIAL
(
decl
)
)
warning
(
OPT_Wattributes
,
"visibility attribute not supported "
"in this configuration; ignored"
)
;
}
</s>

Emit an assembler directive to set symbol for DECL visibility to the visibility type VIS , which must not be VISIBILITY_DEFAULT . As for PE there is no hidden support in gas , we just warn for user-specified visibility attributes .

i386
"visibility"
"visibility attribute not supported "
"in this configuration; ignored"


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( ( unsigned ) Kind , Value ) ; int64_t SymOffset = MipsGetSymAndOffset ( Fixup ) . second ; if ( ! Value && ! SymOffset ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + 7 ) / 8 ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { case Mips :: fixup_Mips_16 : FullSize = 2 ; break ; case Mips :: fixup_Mips_64 : FullSize = 8 ; break ; default : FullSize = 4 ; break ; } uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= ( Value + SymOffset ) & Mask ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? i : ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool Dcpu16PassConfig :: addPreEmitPass ( ) { return false ; } </s>


<s> int avx_vpermilp_parallel ( rtx par , machine_mode mode ) { unsigned i , nelt = GET_MODE_NUNITS ( mode ) ; unsigned mask = 0 ; unsigned char ipar [ 16 ] = { } ; if ( XVECLEN ( par , 0 ) != ( int ) nelt ) return 0 ; for ( i = 0 ; i < nelt ; ++ i ) { rtx er = XVECEXP ( par , 0 , i ) ; unsigned HOST_WIDE_INT ei ; if ( ! CONST_INT_P ( er ) ) return 0 ; ei = INTVAL ( er ) ; if ( ei >= nelt ) return 0 ; ipar [ i ] = ei ; } switch ( mode ) { case E_V8DFmode : for ( i = 4 ; i < 6 ; ++ i ) { if ( ipar [ i ] < 4 || ipar [ i ] >= 6 ) return 0 ; mask |= ( ipar [ i ] - 4 ) << i ; } for ( i = 6 ; i < 8 ; ++ i ) { if ( ipar [ i ] < 6 ) return 0 ; mask |= ( ipar [ i ] - 6 ) << i ; } case E_V4DFmode : for ( i = 0 ; i < 2 ; ++ i ) { if ( ipar [ i ] >= 2 ) return 0 ; mask |= ipar [ i ] << i ; } for ( i = 2 ; i < 4 ; ++ i ) { if ( ipar [ i ] < 2 ) return 0 ; mask |= ( ipar [ i ] - 2 ) << i ; } break ; case E_V16SFmode : for ( i = 0 ; i < 8 ; ++ i ) if ( ipar [ i ] + 8 != ipar [ i + 8 ] ) return 0 ; case E_V8SFmode : for ( i = 0 ; i < 4 ; ++ i ) if ( ipar [ i ] + 4 != ipar [ i + 4 ] ) return 0 ; nelt = 4 ; case E_V2DFmode : case E_V4SFmode : for ( i = 0 ; i < nelt ; ++ i ) mask |= ipar [ i ] << ( i * ( nelt / 2 ) ) ; break ; default : gcc_unreachable ( ) ; } return mask + 1 ; } </s>

Helper for avx_vpermilps256_operand et al . This is also used by the expansion functions to turn the parallel back into a mask . The return value is 0 for no match and the imm8+1 for a match .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { FunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < ScalarEvolutionWrapperPass > ( ) ; AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < ScalarEvolutionWrapperPass > ( ) ; AU . addPreserved < GlobalsAAWrapperPass > ( ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86TTIImpl :: isLegalNTStore ( Type * DataType , Align Alignment ) { unsigned DataSize = DL . getTypeStoreSize ( DataType ) ; if ( ST -> hasSSE4A ( ) && ( DataType -> isFloatTy ( ) || DataType -> isDoubleTy ( ) ) ) return true ; if ( Alignment < DataSize || DataSize < 4 || DataSize > 32 || ! isPowerOf2_32 ( DataSize ) ) return false ; if ( DataSize == 32 ) return ST -> hasAVX ( ) ; if ( DataSize == 16 ) return ST -> hasSSE1 ( ) ; return true ; } </s>

Return true if the target supports nontemporal store .


<s> bool AArch64PassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> Align PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getCPUDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : case PPC :: DIR_PWR10 : case PPC :: DIR_PWR_FUTURE : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return Align ( 32 ) ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return Align ( 32 ) ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; bool IsCOFF = Format == MCObjectFileInfo :: IsCOFF ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == ".hword" ) return parseDirectiveWord ( 2 , Loc ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , Loc ) ; if ( IDVal == ".xword" ) return parseDirectiveWord ( 8 , Loc ) ; if ( IDVal == ".tlsdesccall" ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == ".ltorg" || IDVal == ".pool" ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( Loc ) ; if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == ".inst" ) return parseDirectiveInst ( Loc ) ; } return parseDirectiveLOH ( IDVal , Loc ) ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const MCExpr * PPC64LinuxTargetObjectFile :: getDebugThreadLocalSymbol ( const MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_PPC_DTPREL , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( 0x8000 , getContext ( ) ) , getContext ( ) ) ; } </s>

Describe a TLS variable address within debug info .


<s> void loongarch_move_integer ( rtx temp , rtx dest , unsigned HOST_WIDE_INT value ) { struct loongarch_integer_op codes [ LARCH_MAX_INTEGER_OPS ] ; machine_mode mode ; unsigned int i , num_ops ; rtx x ; mode = GET_MODE ( dest ) ; num_ops = loongarch_build_integer ( codes , value ) ; x = GEN_INT ( codes [ 0 ] . value ) ; for ( i = 1 ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo_p ( ) ) { emit_insn ( gen_rtx_SET ( temp , x ) ) ; x = temp ; } else x = force_reg ( mode , x ) ; switch ( codes [ i ] . method ) { case METHOD_NORMAL : x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ; break ; case METHOD_LU32I : emit_insn ( gen_rtx_SET ( x , gen_rtx_IOR ( DImode , gen_rtx_ZERO_EXTEND ( DImode , gen_rtx_SUBREG ( SImode , x , 0 ) ) , GEN_INT ( codes [ i ] . value ) ) ) ) ; break ; case METHOD_LU52I : emit_insn ( gen_lu52i_d ( x , x , GEN_INT ( 0xfffffffffffff ) , GEN_INT ( codes [ i ] . value ) ) ) ; break ; case METHOD_INSV : emit_insn ( gen_rtx_SET ( gen_rtx_ZERO_EXTRACT ( DImode , x , GEN_INT ( 20 ) , GEN_INT ( 32 ) ) , gen_rtx_REG ( DImode , 0 ) ) ) ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen_rtx_SET ( dest , x ) ) ; } </s>

Load VALUE into DEST . TEMP is as for loongarch_force_temporary .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < LC2200Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARMTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createARMISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static void rs6000_emit_prologue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; if ( bitmap_bit_p ( components , 0 ) ) { rtx lr = gen_rtx_REG ( reg_mode , LR_REGNO ) ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_move_insn ( reg , lr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( reg , lr ) ) ; int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx mem = copy_rtx ( SET_DEST ( single_set ( insn ) ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , lr ) ) ; } if ( bitmap_bit_p ( components , 2 ) ) { rtx reg = gen_rtx_REG ( reg_mode , TOC_REGNUM ) ; rtx sp_reg = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; emit_insn ( gen_frame_store ( reg , sp_reg , RS6000_TOC_SAVE_SLOT ) ) ; } int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += reg_size ; } offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; rtx set = copy_rtx ( single_set ( insn ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , set ) ; } offset += fp_reg_size ; } } </s>


<s> bool isFPVectorizationPotentiallyUnsafe ( ) { return ! ST -> isTargetDarwin ( ) ; } </s>

Indicate that it is potentially unsafe to automatically vectorize floating-point operations because the semantics of vector and scalar floating-point semantics may differ .


<s> enum reg_class mips_secondary_reload_class ( enum reg_class class , enum machine_mode mode , rtx x , int in_p ) { enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS ; int regno = - 1 ; int gp_reg_p ; if ( REG_P ( x ) || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; gp_reg_p = TARGET_MIPS16 ? M16_REG_P ( regno ) : GP_REG_P ( regno ) ; if ( mips_dangerous_for_la25_p ( x ) ) { gr_regs = LEA_REGS ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) class ] , 25 ) ) return gr_regs ; } if ( reg_class_subset_p ( class , ACC_REGS ) ) { if ( TARGET_MIPS16 && in_p ) { return M16_REGS ; } return gp_reg_p ? NO_REGS : gr_regs ; } if ( ACC_REG_P ( regno ) ) { if ( TARGET_MIPS16 && ! in_p ) { return M16_REGS ; } return class == gr_regs ? NO_REGS : gr_regs ; } if ( class == ST_REGS ) { if ( in_p ) return FP_REGS ; return gp_reg_p ? NO_REGS : gr_regs ; } if ( ST_REG_P ( regno ) ) { if ( ! in_p ) return FP_REGS ; return class == gr_regs ? NO_REGS : gr_regs ; } if ( class == FP_REGS ) { if ( MEM_P ( x ) ) { return NO_REGS ; } else if ( CONSTANT_P ( x ) && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { return NO_REGS ; } else if ( gp_reg_p || x == CONST0_RTX ( mode ) ) { return NO_REGS ; } else if ( FP_REG_P ( regno ) ) { return NO_REGS ; } else { return gr_regs ; } } </s>

This function returns the register class required for a secondary register when copying between one of the registers in CLASS , and X , using MODE . If IN_P is nonzero , the copy is going from X to the register , otherwise the register is the source . A return value of NO_REGS means that no secondary register is required .


<s> static rtx rs6000_spe_function_arg ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type ) { int gregno = cum -> sysv_gregno ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || mode == DCmode ) ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( mode == DFmode ) gregno += ( 1 - gregno ) & 1 ; if ( gregno + n_words - 1 > GP_ARG_MAX_REG ) return NULL_RTX ; return spe_build_register_parallel ( mode , gregno ) ; } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == 2 && ( gregno & 1 ) == 0 ) gregno += 1 ; if ( gregno + n_words - 1 <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; enum machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + 1 ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( 4 ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } else return NULL_RTX ; } else { if ( gregno <= GP_ARG_MAX_REG ) return gen_rtx_REG ( mode , gregno ) ; else return NULL_RTX ; } } </s>

Determine where to put a SIMD argument on the SPE .


<s> bool SystemZTTIImpl :: isLSRCostLess ( const TargetTransformInfo :: LSRCost & C1 , const TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


<s> static void ix86_emit_save_sse_regs_using_mov ( HOST_WIDE_INT cfa_offset ) { unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) { ix86_emit_save_reg_using_mov ( V4SFmode , regno , cfa_offset ) ; cfa_offset -= GET_MODE_SIZE ( V4SFmode ) ; } } </s>

Emit code to save SSE registers using MOV insns . First register is stored at CFA - CFA_OFFSET .


<s> void PPCAIXAsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! TM . getXCOFFTracebackTable ( ) ) return ; emitTracebackTable ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DCI ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: SELECT_CC : return performSelectCCCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static bool ix86_save_reg ( unsigned int regno , bool maybe_eh_return ) { if ( cfun -> machine -> no_caller_saved_registers ) { rtx reg = crtl -> return_rtx ; if ( reg ) { unsigned int i = REGNO ( reg ) ; unsigned int nregs = hard_regno_nregs [ i ] [ GET_MODE ( reg ) ] ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; reg = crtl -> return_bnd ; if ( reg ) { i = REGNO ( reg ) ; nregs = hard_regno_nregs [ i ] [ GET_MODE ( reg ) ] ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; } } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) && ! cfun -> machine -> no_drap_save_restore ) return true ; return ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s> int arith_operand ( rtx op , enum machine_mode mode ) { if ( GET_CODE ( op ) == CONST_INT && SMALL_INT ( op ) ) return 1 ; return register_operand ( op , mode ) ; } </s>

Return true if OP is a register , or is a CONST_INT that can fit in a signed 13 bit immediate field . This is an acceptable SImode operand for most 3 address instructions .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 || Directive == PPC :: DIR_A2 || Directive == PPC :: DIR_E500mc || Directive == PPC :: DIR_E5500 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new PPCScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> void xstormy16_expand_iorqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_set_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_iorqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( ! REG_P ( in ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! REG_P ( val ) && ! CONST_INT_P ( val ) ) val = copy_to_mode_reg ( QImode , val ) ; if ( ! REG_P ( out ) ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( ! CONST_INT_P ( val ) ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_iorhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>

Expand an 8-bit IOR . This either detects the one case we can actually do , or uses a 16-bit IOR .


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr * MI ) { unsigned Idx = isPairedLdSt ( MI ) ? 3 : 2 ; return MI -> getOperand ( Idx ) ; } </s>

Returns the immediate offset operator of a load/store .


<s> void sparc_emit_fixunsdi ( rtx * operands , enum machine_mode mode ) { rtx neglab , donelab , i0 , i1 , f0 , in , out , limit ; out = operands [ 0 ] ; in = force_reg ( mode , operands [ 1 ] ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; i0 = gen_reg_rtx ( DImode ) ; i1 = gen_reg_rtx ( DImode ) ; limit = gen_reg_rtx ( mode ) ; f0 = gen_reg_rtx ( mode ) ; emit_move_insn ( limit , CONST_DOUBLE_FROM_REAL_VALUE ( REAL_VALUE_ATOF ( "9223372036854775808.0" , mode ) , mode ) ) ; emit_cmp_and_jump_insns ( in , limit , GE , NULL_RTX , mode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , in ) ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , f0 , gen_rtx_MINUS ( mode , in , limit ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , i0 , gen_rtx_FIX ( DImode , gen_rtx_FIX ( mode , f0 ) ) ) ) ; emit_insn ( gen_movdi ( i1 , const1_rtx ) ) ; emit_insn ( gen_ashldi3 ( i1 , i1 , GEN_INT ( 63 ) ) ) ; emit_insn ( gen_xordi3 ( out , i0 , i1 ) ) ; emit_label ( donelab ) ; } </s>

Generate an FP to unsigned DImode conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> machine_mode mmix_select_cc_mode ( RTX_CODE op , rtx x , rtx y ATTRIBUTE_UNUSED ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { if ( op == ORDERED || op == UNORDERED || op == UNGE || op == UNGT || op == UNLE || op == UNLT ) return CC_FUNmode ; if ( op == EQ || op == NE ) return CC_FPEQmode ; return CC_FPmode ; } if ( op == GTU || op == LTU || op == GEU || op == LEU ) return CC_UNSmode ; return CCmode ; } </s>


<s> static bool nds32_needs_double_word_align ( machine_mode mode , const_tree type ) { unsigned int align ; align = NDS32_MODE_TYPE_ALIGN ( mode , type ) ; return ( align > PARM_BOUNDARY ) ; } </s>

Return true if MODE/TYPE need double word alignment .


<s> virtual MachineInstr * foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return 0 ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> int legitimate_pic_operand_p ( rtx x ) { if ( CONSTANT_P ( x ) && flag_pic && ( GET_CODE ( x ) == SYMBOL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF ) ) ) return 0 ; return 1 ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> bool arm_valid_symbolic_address_p ( rtx addr ) { rtx xop0 , xop1 = NULL_RTX ; rtx tmp = addr ; if ( GET_CODE ( tmp ) == SYMBOL_REF || GET_CODE ( tmp ) == LABEL_REF ) return true ; if ( GET_CODE ( addr ) == CONST ) tmp = XEXP ( addr , 0 ) ; if ( GET_CODE ( tmp ) == PLUS ) { xop0 = XEXP ( tmp , 0 ) ; xop1 = XEXP ( tmp , 1 ) ; if ( GET_CODE ( xop0 ) == SYMBOL_REF && CONST_INT_P ( xop1 ) ) return IN_RANGE ( INTVAL ( xop1 ) , - 0x8000 , 0x7fff ) ; } return false ; } </s>

Returns true if the pattern is a valid symbolic address , which is either a symbol_ref or ( symbol_ref + addend ) . According to the ARM ELF ABI , the initial addend of REL-type relocations processing MOVW and MOVT instructions is formed by interpreting the 16-bit literal field of the instruction as a 16-bit signed value in the range -32768 < = A < 32768 . In Thumb-1 mode , we use upper/lower relocations which have an 8-bit unsigned range of 0 < = A < 256 as described in the AAELF32 relocation handling documentation : REL-type relocations are encoded as unsigned in this case .


<s> unsigned LanaiMCCodeEmitter :: getMachineOpValue ( const MCInst & Inst , const MCOperand & MCOp , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { if ( MCOp . isReg ( ) ) return getLanaiRegisterNumbering ( MCOp . getReg ( ) ) ; if ( MCOp . isImm ( ) ) return static_cast < unsigned > ( MCOp . getImm ( ) ) ; assert ( MCOp . isExpr ( ) ) ; const MCExpr * Expr = MCOp . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * BinaryExpr = static_cast < const MCBinaryExpr * > ( Expr ) ; Expr = BinaryExpr -> getLHS ( ) ; } assert ( isa < LanaiMCExpr > ( Expr ) || Expr -> getKind ( ) == MCExpr :: SymbolRef ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , MCFixupKind ( FixupKind ( Expr ) ) ) ) ; return 0 ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool AArch64CompressJumpTables :: runOnMachineFunction ( MachineFunction & MFIn ) { bool Changed = false ; MF = & MFIn ; const auto & ST = MF -> getSubtarget < AArch64Subtarget > ( ) ; TII = ST . getInstrInfo ( ) ; if ( ST . force32BitJumpTables ( ) && ! MF -> getFunction ( ) . optForMinSize ( ) ) return false ; scanFunction ( ) ; for ( MachineBasicBlock & MBB : * MF ) { int Offset = BlockInfo [ MBB . getNumber ( ) ] ; for ( MachineInstr & MI : MBB ) { Changed |= compressJumpTable ( MI , Offset ) ; Offset += TII -> getInstSizeInBytes ( MI ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue AArch64TargetLowering :: getRecipEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & ExtraSteps ) const { return getEstimate ( * Subtarget , DCI , AArch64ISD :: FRECPE , Operand , ExtraSteps ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> static machine_mode select_block_compare_mode ( unsigned HOST_WIDE_INT offset , unsigned HOST_WIDE_INT bytes , unsigned HOST_WIDE_INT align ) { unsigned HOST_WIDE_INT maxread = ROUND_UP ( bytes , align ) ; int word_mode_ok = ! ( ! BYTES_BIG_ENDIAN && ! TARGET_LDBRX && word_mode == DImode ) ; if ( word_mode_ok && bytes >= UNITS_PER_WORD ) return word_mode ; else if ( bytes == GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes == GET_MODE_SIZE ( HImode ) ) return HImode ; else if ( bytes == GET_MODE_SIZE ( QImode ) ) return QImode ; else if ( bytes < GET_MODE_SIZE ( SImode ) && TARGET_EFFICIENT_OVERLAPPING_UNALIGNED && offset >= GET_MODE_SIZE ( SImode ) - bytes ) return SImode ; else if ( word_mode_ok && bytes < UNITS_PER_WORD && TARGET_EFFICIENT_OVERLAPPING_UNALIGNED && offset >= UNITS_PER_WORD - bytes ) return word_mode ; else if ( word_mode_ok && maxread >= UNITS_PER_WORD ) return word_mode ; else if ( maxread >= GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( SImode ) ) return SImode ; else if ( bytes > GET_MODE_SIZE ( HImode ) ) return HImode ; return QImode ; } </s>

Select the mode to be used for reading the next chunk of bytes in the compare . OFFSET is the current read offset from the beginning of the block . BYTES is the number of bytes remaining to be read . ALIGN is the minimum alignment of the memory blocks being compared in bytes .


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const SystemZSubtarget * Subtarget = & MF . getSubtarget < SystemZSubtarget > ( ) ; SystemZCallingConventionRegisters * Regs = Subtarget -> getSpecialRegisters ( ) ; return Regs -> getCallPreservedMask ( MF , CC ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void xstormy16_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( * cum < NUM_ARGUMENT_REGISTERS && ( * cum + XSTORMY16_WORD_SIZE ( arg . type , arg . mode ) > NUM_ARGUMENT_REGISTERS ) ) * cum = NUM_ARGUMENT_REGISTERS ; * cum += XSTORMY16_WORD_SIZE ( arg . type , arg . mode ) ; } </s>

Update CUM to advance past an argument in the argument list . The values MODE , TYPE and NAMED describe that argument . Once this is done , the variable CUM is suitable for analyzing the * following * argument with ` TARGET_FUNCTION_ARG ' , etc . This function need not do anything if the argument in question was passed on the stack . The compiler knows how to track the amount of stack space used for arguments without any special help . However , it makes life easier for xstormy16_build_va_list if it does update the word count .


<s> bool LanaiInstrInfo :: getMemOperandsWithOffsetWidth ( const MachineInstr & LdSt , SmallVectorImpl < const MachineOperand * > & BaseOps , int64_t & Offset , bool & OffsetIsScalable , unsigned & Width , const TargetRegisterInfo * TRI ) const { switch ( LdSt . getOpcode ( ) ) { default : return false ; case Lanai :: LDW_RI : case Lanai :: LDW_RR : case Lanai :: SW_RR : case Lanai :: SW_RI : case Lanai :: LDHs_RI : case Lanai :: LDHz_RI : case Lanai :: STH_RI : case Lanai :: LDBs_RI : case Lanai :: LDBz_RI : const MachineOperand * BaseOp ; OffsetIsScalable = false ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true ; } } </s>

Get zero or more base operands and the byte offset of an instruction that reads/writes memory .


<s> bool ARM64PassConfig :: addPreSched2 ( ) { addPass ( createARM64ExpandPseudoPass ( ) ) ; addPass ( createARM64LoadStoreOptimizationPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
void
emit_safe_across_calls
(
void
)
{
unsigned
int
rs
,
re
;
int
out_state
;
rs
=
1
;
out_state
=
0
;
while
(
1
)
{
while
(
rs
<
64
&&
call_used_or_fixed_reg_p
(
PR_REG
(
rs
)
)
)
rs
++
;
if
(
rs
>=
64
)
break
;
for
(
re
=
rs
+
1
;
re
<
64
&&
!
call_used_or_fixed_reg_p
(
PR_REG
(
re
)
)
;
re
++
)
continue
;
if
(
out_state
==
0
)
{
fputs
(
"\t.pred.safe_across_calls "
,
asm_out_file
)
;
out_state
=
1
;
}
else
fputc
(
','
,
asm_out_file
)
;
if
(
re
==
rs
+
1
)
fprintf
(
asm_out_file
,
"p%u"
,
rs
)
;
else
fprintf
(
asm_out_file
,
"p%u-p%u"
,
rs
,
re
1
)
;
rs
=
re
+
1
;
}
if
(
out_state
)
fputc
(
'\n'
,
asm_out_file
)
;
}
</s>


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


"immediate value expected for vector index"

tryParseRegister - parse one register if possible


<s> CCAssignFn * X86FastISel :: CCAssignFnForCall ( unsigned CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return CC_X86_Win64_C ; else if ( CC == CallingConv :: Fast && isTaillCall ) return CC_X86_64_TailCall ; else return CC_X86_64_C ; } if ( CC == CallingConv :: X86_FastCall ) return CC_X86_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_X86_32_FastCC ; else return CC_X86_32_C ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static bool sh_assemble_integer ( rtx value , unsigned int size , int aligned_p ) { if ( TARGET_FDPIC && size == UNITS_PER_WORD && GET_CODE ( value ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( value ) ) { fputs ( "\t.long\t" , asm_out_file ) ; output_addr_const ( asm_out_file , value ) ; fputs ( "@FUNCDESC\n" , asm_out_file ) ; return true ; } return default_assemble_integer ( value , size , aligned_p ) ; } </s>

Implementation of TARGET_ASM_INTEGER for SH . Pointers to functions need to be output as pointers to function descriptors for FDPIC .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsTargetMachine & TM ) { if ( TM . getSubtargetImpl ( ) -> inMips16Mode ( ) ) return llvm :: createMips16InstrInfo ( TM ) ; return llvm :: createMipsSEInstrInfo ( TM ) ; } </s>


"Unknown fence ordering in emitLeadingFence"


"failed to perform tail call elimination on a call "

This hook must be implemented to lower calls into the specified DAG .


<s> unsigned SparcCodeEmitter :: getBranchTargetOpValue ( const MachineInstr & MI , unsigned opIdx ) const { const MachineOperand MO = MI . getOperand ( opIdx ) ; return getMachineOpValue ( MI , MO ) ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> bool contains ( MachineInstr * MI ) { return liveInstrs . count ( MI ) ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CCmode , CC_REGNUM ) ; emit_insn ( gen ( bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } } </s>


<s> const PPCInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> void sparc_flat_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > get_stack_check_protect ( ) ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size - get_stack_check_protect ( ) ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == 0 ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed ) { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the GOT register if needed .


"CFGuard check mechanism only used on 32-bit X86"


<s>
void
\
toc_section
(
)
\
{
\
if
(
TARGET_MINIMAL_TOC
)
\
{
\
\
if
(
!
toc_initialized
)
\
{
\
fputs
(
"\t.toc\nLCTOC..1:\n"
,
asm_out_file
)
;
\
fputs
(
"\t.tc toc_table[TC],toc_table[RW]\n"
,
asm_out_file
)
;
\
toc_initialized
=
1
;
\
}
\
\
if
(
in_section
!=
toc
)
\
fprintf
(
asm_out_file
,
"\t.csect toc_table[RW]%s\n"
,
\
(
TARGET_32BIT
""
:
",3"
)
)
;
\
}
\
else
\
{
\
if
(
in_section
!=
toc
)
\
fputs
(
"\t.toc\n"
,
asm_out_file
)
;
\
}
\
in_section
=
toc
;
\
}
</s>

This is just a placeholder to make linking work without having to add this to the generic Darwin EXTRA_SECTIONS . If -mcall-aix is ever needed for Darwin ( not too likely ! ) this would have to get a real definition .


<s> virtual MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const LLVM_OVERRIDE { return createSystemZObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> yaml :: MachineFunctionInfo * AArch64TargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: AArch64FunctionInfo ( ) ; } </s>

Allocate and return a default initialized instance of the YAML representation for the MachineFunctionInfo .


<s> static void arm_option_restore ( struct gcc_options * , struct gcc_options * opts_set , struct cl_target_option * ptr ) { arm_configure_build_target ( & arm_active_target , ptr , opts_set , false ) ; } </s>


<s> bool Cpu0TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Cpu0 ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> static bool global_reg_mentioned_p ( rtx x ) { if ( INSN_P ( x ) ) { if ( CALL_P ( x ) ) { if ( ! RTL_CONST_OR_PURE_CALL_P ( x ) ) return true ; x = CALL_INSN_FUNCTION_USAGE ( x ) ; if ( x == 0 ) return false ; } else x = PATTERN ( x ) ; } subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( global_reg_mentioned_p_1 ( * iter ) ) return true ; return false ; } </s>

Returns nonzero if X mentions a global register .


<s> static rtx aarch64_strip_extend ( rtx x , bool strip_shift ) { scalar_int_mode mode ; rtx op = x ; if ( ! is_a < scalar_int_mode > ( GET_MODE ( op ) , & mode ) ) return op ; if ( ( GET_CODE ( op ) == ZERO_EXTRACT || GET_CODE ( op ) == SIGN_EXTRACT ) && XEXP ( op , 2 ) == const0_rtx && GET_CODE ( XEXP ( op , 0 ) ) == MULT && aarch64_is_extend_from_extract ( mode , XEXP ( XEXP ( op , 0 ) , 1 ) , XEXP ( op , 1 ) ) ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( GET_CODE ( op ) == AND && GET_CODE ( XEXP ( op , 0 ) ) == MULT && CONST_INT_P ( XEXP ( XEXP ( op , 0 ) , 1 ) ) && CONST_INT_P ( XEXP ( op , 1 ) ) && aarch64_uxt_size ( exact_log2 ( INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ) , INTVAL ( XEXP ( op , 1 ) ) ) != 0 ) return XEXP ( XEXP ( op , 0 ) , 0 ) ; if ( strip_shift && GET_CODE ( op ) == ASHIFT && CONST_INT_P ( XEXP ( op , 1 ) ) && ( ( unsigned HOST_WIDE_INT ) INTVAL ( XEXP ( op , 1 ) ) ) <= 4 ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == ZERO_EXTEND || GET_CODE ( op ) == SIGN_EXTEND ) op = XEXP ( op , 0 ) ; if ( op != x ) return op ; return x ; } </s>

Helper function for rtx cost calculation . Strip an extend expression from X . Returns the inner operand if successful , or the original expression on failure . We deal with a number of possible canonicalization variations here .


<s> unsigned SparcRegisterInfo :: getRARegister ( ) const { return SP :: I7 ; } </s>

This method should return the register where the return address can be found .


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask2 ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( ( ( mask2 == 0 || ( mask2 & ix86_isa_flags2 ) != 0 ) && ( mask == 0 || ( mask & ix86_isa_flags ) != 0 ) ) || ( ( mask & OPTION_MASK_ISA_MMX ) != 0 && TARGET_MMX_WITH_SSE ) || ( mask2 == OPTION_MASK_ISA2_AVXVNNI ) || ( mask2 == OPTION_MASK_ISA2_AVXIFMA ) || ( mask2 == ( OPTION_MASK_ISA2_AVXNECONVERT | OPTION_MASK_ISA2_AVX512BF16 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! Subtarget . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


"rs6000_builtin_md_vectorized_function (%s, %s, %s)\n"


<s> rtx rs6000_gen_lvx ( enum machine_mode mode , rtx dest_exp , rtx src_exp ) { rtx lvx ; if ( mode == V16QImode ) lvx = gen_altivec_lvx_v16qi ( dest_exp , src_exp ) ; else if ( mode == V8HImode ) lvx = gen_altivec_lvx_v8hi ( dest_exp , src_exp ) ; else if ( mode == V8HFmode ) lvx = gen_altivec_lvx_v8hf ( dest_exp , src_exp ) ; else if ( mode == V4SImode ) lvx = gen_altivec_lvx_v4si ( dest_exp , src_exp ) ; else if ( mode == V4SFmode ) lvx = gen_altivec_lvx_v4sf ( dest_exp , src_exp ) ; else if ( mode == V2DImode ) lvx = gen_altivec_lvx_v2di ( dest_exp , src_exp ) ; else if ( mode == V2DFmode ) lvx = gen_altivec_lvx_v2df ( dest_exp , src_exp ) ; else if ( mode == V1TImode ) lvx = gen_altivec_lvx_v1ti ( dest_exp , src_exp ) ; else gcc_unreachable ( ) ; rtx new_mem_exp = SET_SRC ( PATTERN ( lvx ) ) ; mimic_memory_attributes_and_flags ( new_mem_exp , src_exp ) ; return lvx ; } </s>

Generate an rtx expression to represent use of the lvx insn to load from memory SRC_EXP into register DEST_EXP with vector mode MODE .


<s> bool MVEGatherScatterLowering :: runOnFunction ( Function & F ) { if ( ! EnableMaskedGatherScatters ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < TargetMachine > ( ) ; auto * ST = & TM . getSubtarget < ARMSubtarget > ( F ) ; if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { Changed |= SimplifyInstructionsInBlock ( & BB ) ; for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 0 ) , II -> getParent ( ) , LI ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; Changed |= optimiseAddress ( II -> getArgOperand ( 1 ) , II -> getParent ( ) , LI ) ; } } } for ( unsigned i = 0 ; i < Gathers . size ( ) ; i ++ ) { IntrinsicInst * I = Gathers [ i ] ; Instruction * L = lowerGather ( I ) ; if ( L == nullptr ) continue ; SimplifyInstructionsInBlock ( L -> getParent ( ) ) ; Changed = true ; } for ( unsigned i = 0 ; i < Scatters . size ( ) ; i ++ ) { IntrinsicInst * I = Scatters [ i ] ; Instruction * S = lowerScatter ( I ) ; if ( S == nullptr ) continue ; SimplifyInstructionsInBlock ( S -> getParent ( ) ) ; Changed = true ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"invalid feature modifier %qs in %<-march=%s%>"

Validate a command-line -march option . Parse the arch and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results , if they are valid , in RES and ISA_FLAGS . Return whether the option is valid .


<s>
const
char
*
vax_output_int_move
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
*
operands
,
enum
machine_mode
mode
)
{
switch
(
mode
)
{
case
SImode
:
if
(
GET_CODE
(
operands
[
1
]
)
==
SYMBOL_REF
||
GET_CODE
(
operands
[
1
]
)
==
CONST
)
{
if
(
push_operand
(
operands
[
0
]
,
SImode
)
)
return
"pushab %a1"
;
return
"movab %a1,%0"
;
}
if
(
operands
[
1
]
==
const0_rtx
)
return
"clrl %0"
;
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
&&
(
unsigned
)
INTVAL
(
operands
[
1
]
)
>=
64
)
{
int
i
=
INTVAL
(
operands
[
1
]
)
;
if
(
(
unsigned
)
(
~
i
)
<
64
)
return
"mcoml %N1,%0"
;
if
(
(
unsigned
)
i
<
0x100
)
return
"movzbl %1,%0"
;
if
(
i
>=
0x80
&&
i
<
0
)
return
"cvtbl %1,%0"
;
if
(
(
unsigned
)
i
<
0x10000
)
return
"movzwl %1,%0"
;
if
(
i
>=
0x8000
&&
i
<
0
)
return
"cvtwl %1,%0"
;
}
if
(
push_operand
(
operands
[
0
]
,
SImode
)
)
return
"pushl %1"
;
return
"movl %1,%0"
;
case
HImode
:
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
{
int
i
=
INTVAL
(
operands
[
1
]
)
;
if
(
i
==
0
)
return
"clrw %0"
;
else
if
(
(
unsigned
int
)
i
<
64
)
return
"movw %1,%0"
;
else
if
(
(
unsigned
int
)
~
i
<
64
)
return
"mcomw %H1,%0"
;
else
if
(
(
unsigned
int
)
i
<
256
)
return
"movzbw %1,%0"
;
}
return
"movw %1,%0"
;
case
QImode
:
if
(
GET_CODE
(
operands
[
1
]
)
==
CONST_INT
)
{
int
i
=
INTVAL
(
operands
[
1
]
)
;
if
(
i
==
0
)
return
"clrb %0"
;
else
if
(
(
unsigned
int
)
~
i
<
64
)
return
"mcomb %B1,%0"
;
}
return
"movb %1,%0"
;
default
:
gcc_unreachable
(
)
;
}
}
</s>


<s> bool isReg ( ) const override { return isGPRAsmReg ( ) && RegIdx . Index == 0 ; } </s>


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


<s> bool ix86_dep_by_shift_count ( const_rtx set_insn , const_rtx use_insn ) { return ix86_dep_by_shift_count_body ( PATTERN ( set_insn ) , PATTERN ( use_insn ) ) ; } </s>

Return true if destination reg of SET_INSN is shift count of USE_INSN .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Mips ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool SystemZInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumCyclesT , unsigned ExtraPredCyclesT , MachineBasicBlock & FMBB , unsigned NumCyclesF , unsigned ExtraPredCyclesF , BranchProbability Probability ) const { return false ; } </s>


<s> void split_quadword_operands ( rtx * operands , rtx * low , int n ATTRIBUTE_UNUSED ) { int i ; low [ 0 ] = low [ 1 ] = low [ 2 ] = 0 ; for ( i = 0 ; i < 3 ; i ++ ) { if ( low [ i ] ) ; else if ( GET_CODE ( operands [ i ] ) == MEM && ( GET_CODE ( XEXP ( operands [ i ] , 0 ) ) == POST_INC ) ) { rtx addr = XEXP ( operands [ i ] , 0 ) ; operands [ i ] = low [ i ] = gen_rtx_MEM ( SImode , addr ) ; if ( which_alternative == 0 && i == 0 ) { addr = XEXP ( operands [ i ] , 0 ) ; operands [ i + 1 ] = low [ i + 1 ] = gen_rtx_MEM ( SImode , addr ) ; } } else { low [ i ] = operand_subword ( operands [ i ] , 0 , 0 , DImode ) ; operands [ i ] = operand_subword ( operands [ i ] , 1 , 0 , DImode ) ; } } } </s>

This is like nonimmediate_operand with a restriction on the type of MEM .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> static bool mips_small_register_classes_for_mode_p ( machine_mode mode ATTRIBUTE_UNUSED ) { return TARGET_MIPS16 ; } </s>

Implement target hook small_register_classes_for_mode_p .


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AArch64 Address Type Promotion"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"X86-64 PIC uses RIP relative addressing"

runOnMachineFunction - Emit the function body .


<s> bool AArch64FastISel :: isTypeLegal ( Type * Ty , MVT & VT ) { EVT evt = TLI . getValueType ( Ty , true ) ; if ( evt == MVT :: Other || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == MVT :: f128 ) return false ; return TLI . isTypeLegal ( VT ) ; } </s>


<s> int nds32_fp_as_gp_check_available ( void ) { return 0 ; } </s>

Function to determine whether it is worth to do fp_as_gp optimization . Return 0 : It is NOT worth to do fp_as_gp optimization . Return 1 : It is APPROXIMATELY worth to do fp_as_gp optimization . Note that if it is worth to do fp_as_gp optimization , we MUST set FP_REGNUM ever live in this function .


<s> bool supportSwiftError ( ) const override { return true ; } </s>

Return true if the target supports swifterror attribute .


<s> void CAHPInstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { O << getRegisterName ( RegNo ) ; } </s>


<s> void addDomain ( unsigned domain ) { AvailableDomains |= 1u << domain ; } </s>


<s>
static
rtx
mips_expand_builtin_insn
(
enum
insn_code
icode
,
unsigned
int
nops
,
struct
expand_operand
*
ops
,
bool
has_target_p
)
{
if
(
!
maybe_expand_insn
(
icode
,
nops
,
ops
)
)
{
error
(
"invalid argument to built-in function"
)
;
return
has_target_p
gen_reg_rtx
(
ops
[
0
]
.
mode
)
:
const0_rtx
;
}
return
has_target_p
ops
[
0
]
.
value
:
const0_rtx
;
}
</s>

Expand instruction ICODE as part of a built-in function sequence . Use the first NOPS elements of OPS as the instruction 's operands . HAS_TARGET_P is true if operand 0 is a target ; it is false if the instruction has no target . Return the target rtx if HAS_TARGET_P , otherwise return const0_rtx .


"***** AArch64SpeculationHardening - automatic insertion of "

"***** AArch64SpeculationHardening - track control flow *****\n"

"***** AArch64SpeculationHardening - Lowering "


<s> void ARMAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( EnableMCInst ) { printInstructionThroughMCStreamer ( MI ) ; return ; } if ( MI -> getOpcode ( ) == ARM :: CONSTPOOL_ENTRY ) EmitAlignment ( 2 ) ; SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; if ( MI -> getOpcode ( ) == ARM :: t2TBB ) EmitAlignment ( 1 ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void setFrameAdjustment ( MachineInstr & I , int64_t V ) const { assert ( isFrameInstr ( I ) ) ; I . getOperand ( 1 ) . setImm ( V ) ; } </s>

Sets the stack pointer adjustment made inside the frame made up by this instruction .


<s> static bool mips_vector_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case E_V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ; case E_V2HImode : case E_V4QImode : case E_V2HQmode : case E_V2UHQmode : case E_V2HAmode : case E_V2UHAmode : case E_V4QQmode : case E_V4UQQmode : return TARGET_DSP ; case E_V2SImode : case E_V4HImode : case E_V8QImode : return TARGET_LOONGSON_VECTORS ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Target hook for vector_mode_supported_p .


<s> static void emit_soft_tfmode_libcall ( const char * func_name , int nargs , rtx * operands ) { rtx ret_slot = NULL , arg [ 3 ] , func_sym ; int i ; gcc_assert ( nargs == 2 || nargs == 3 ) ; for ( i = 0 ; i < nargs ; ++ i ) { rtx this_arg = operands [ i ] ; rtx this_slot ; if ( GET_MODE ( this_arg ) == TFmode ) { int force_stack_temp ; force_stack_temp = 0 ; if ( TARGET_BUGGY_QP_LIB && i == 0 ) force_stack_temp = 1 ; if ( GET_CODE ( this_arg ) == MEM && ! force_stack_temp ) { tree expr = MEM_EXPR ( this_arg ) ; if ( expr ) mark_addressable ( expr ) ; this_arg = XEXP ( this_arg , 0 ) ; } else if ( CONSTANT_P ( this_arg ) && ! force_stack_temp ) { this_slot = force_const_mem ( TFmode , this_arg ) ; this_arg = XEXP ( this_slot , 0 ) ; } else { this_slot = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; if ( i > 0 ) emit_move_insn ( this_slot , this_arg ) ; else ret_slot = this_slot ; this_arg = XEXP ( this_slot , 0 ) ; } } arg [ i ] = this_arg ; } func_sym = gen_rtx_SYMBOL_REF ( Pmode , func_name ) ; if ( GET_MODE ( operands [ 0 ] ) == TFmode ) { if ( nargs == 2 ) emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; else emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) , arg [ 2 ] , GET_MODE ( arg [ 2 ] ) ) ; if ( ret_slot ) emit_move_insn ( operands [ 0 ] , ret_slot ) ; } else { rtx ret ; gcc_assert ( nargs == 2 ) ; ret = emit_library_call_value ( func_sym , operands [ 0 ] , LCT_NORMAL , GET_MODE ( operands [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; if ( ret != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , ret ) ; } } </s>

Generate a call to FUNC with OPERANDS . Operand 0 is the return value . Unlike normal calls , TFmode operands are passed by reference . It is assumed that no more than 3 operands are required .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: FRE : return "PPCISD::FRE" ; case PPCISD :: FRSQRTE : return "PPCISD::FRSQRTE" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: CALL : return "PPCISD::CALL" ; case PPCISD :: CALL_NOP : return "PPCISD::CALL_NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL : return "PPCISD::BCTRL" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: EH_SJLJ_SETJMP : return "PPCISD::EH_SJLJ_SETJMP" ; case PPCISD :: EH_SJLJ_LONGJMP : return "PPCISD::EH_SJLJ_LONGJMP" ; case PPCISD :: MFOCRF : return "PPCISD::MFOCRF" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: BDNZ : return "PPCISD::BDNZ" ; case PPCISD :: BDZ : return "PPCISD::BDZ" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; case PPCISD :: VADD_SPLAT : return "PPCISD::VADD_SPLAT" ; case PPCISD :: SC : return "PPCISD::SC" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool PPCRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ) { FrameIdx = MF . getInfo < PPCFunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> unsigned getNumFixupKinds ( ) const { return 7 ; } </s>

Get the number of target specific fixup kinds .


<s> inline bool isKMergeMasked ( uint64_t TSFlags ) { return isKMasked ( TSFlags ) && ( TSFlags & X86II :: EVEX_Z ) == 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-merge-masked opcodes .


<s> static tls_model or1k_tls_symbolic_operand ( rtx op ) { rtx sym , addend ; split_const ( op , & sym , & addend ) ; if ( SYMBOL_REF_P ( sym ) ) return SYMBOL_REF_TLS_MODEL ( sym ) ; return TLS_MODEL_NONE ; } </s>

Return the TLS type for TLS symbols , 0 otherwise .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget . hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s> static bool ia64_legitimate_constant_p ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case LABEL_REF : return true ; case CONST_DOUBLE : if ( GET_MODE ( x ) == VOIDmode || mode == SFmode || mode == DFmode ) return true ; return satisfies_constraint_G ( x ) ; case CONST : case SYMBOL_REF : if ( tls_symbolic_operand_type ( x ) == 0 ) { HOST_WIDE_INT addend = 0 ; rtx op = x ; if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST_INT ) { addend = INTVAL ( XEXP ( XEXP ( op , 0 ) , 1 ) ) ; op = XEXP ( XEXP ( op , 0 ) , 0 ) ; } if ( any_offset_symbol_operand ( op , mode ) || function_operand ( op , mode ) ) return true ; if ( aligned_offset_symbol_operand ( op , mode ) ) return ( addend & 0x3fff ) == 0 ; return false ; } return false ; case CONST_VECTOR : if ( mode == V2SFmode ) return satisfies_constraint_Y ( x ) ; return ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT && GET_MODE_SIZE ( mode ) <= 8 ) ; default : return false ; } } </s>

Return true if X is a constant that is valid for some immediate field in an instruction .


"List of x86 specific tuning parameter names:\n"

Helper function to set ix86_tune_features . IX86_TUNE is the processor type .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> void altivec_expand_stvx_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { rtx tmp = gen_reg_rtx ( mode ) ; rtx store = gen_rtx_SET ( VOIDmode , op0 , tmp ) ; rtx stvx = gen_rtx_UNSPEC ( mode , gen_rtvec ( 1 , const0_rtx ) , unspec ) ; rtx par = gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , store , stvx ) ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( par ) ; } </s>

Generate code for a `` stvx '' or `` stvxl '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || isLittleEndian ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'Y' : case 'Z' : return C_Immediate ; case 'z' : case 'S' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s>
void
ARMOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
CondCode
:
OS
<<
"<ARMCC::"
<<
ARMCondCodeToString
(
getCondCode
(
)
)
<<
">"
;
break
;
case
CCOut
:
OS
<<
"<ccout "
<<
getReg
(
)
<<
">"
;
break
;
case
CoprocNum
:
OS
<<
"<coprocessor number: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
CoprocReg
:
OS
<<
"<coprocessor register: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
MSRMask
:
OS
<<
"<mask: "
<<
getMSRMask
(
)
<<
">"
;
break
;
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
MemBarrierOpt
:
OS
<<
"<ARM_MB::"
<<
MemBOptToString
(
getMemBarrierOpt
(
)
)
<<
">"
;
break
;
case
Memory
:
OS
<<
"<memory "
<<
"base:"
<<
getMemBaseRegNum
(
)
;
if
(
getMemOffsetIsReg
(
)
)
{
OS
<<
" offset:<register "
<<
getMemOffsetRegNum
(
)
;
if
(
getMemOffsetRegShifted
(
)
)
{
OS
<<
" offset-shift-type:"
<<
getMemShiftType
(
)
;
OS
<<
" offset-shift-amount:"
<<
*
getMemShiftAmount
(
)
;
}
}
else
{
OS
<<
" offset:"
<<
*
getMemOffset
(
)
;
}
if
(
getMemOffsetIsReg
(
)
)
OS
<<
" (offset-is-reg)"
;
if
(
getMemPreindexed
(
)
)
OS
<<
" (pre-indexed)"
;
if
(
getMemPostindexed
(
)
)
OS
<<
" (post-indexed)"
;
if
(
getMemNegative
(
)
)
OS
<<
" (negative)"
;
if
(
getMemWriteback
(
)
)
OS
<<
" (writeback)"
;
OS
<<
">"
;
break
;
case
ProcIFlags
:
{
OS
<<
"<ARM_PROC::"
;
unsigned
IFlags
=
getProcIFlags
(
)
;
for
(
int
i
=
2
;
i
>=
0
;
i
)
if
(
IFlags
&
(
1
<<
i
)
)
OS
<<
ARM_PROC
::
IFlagsToString
(
1
<<
i
)
;
OS
<<
">"
;
break
;
}
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
Shifter
:
OS
<<
"<shifter "
<<
getShiftOpcStr
(
Shift
.
ShiftTy
)
<<
">"
;
break
;
case
RegisterList
:
case
DPRRegisterList
:
case
SPRRegisterList
:
{
OS
<<
"<register_list "
;
const
SmallVectorImpl
<
unsigned
>
&
RegList
=
getRegList
(
)
;
for
(
SmallVectorImpl
<
unsigned
>
::
const_iterator
I
=
RegList
.
begin
(
)
,
E
=
RegList
.
end
(
)
;
I
!=
E
;
)
{
OS
<<
*
I
;
if
(
++
I
<
E
)
OS
<<
", "
;
}
OS
<<
">"
;
break
;
}
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

ARM
ARM
"<ARMCC::"
ARM
">"
"<ccout "
">"
"<coprocessor number: "
">"
"<coprocessor register: "
">"
"<mask: "
">"
"<ARM_MB::"
">"
"<memory "
"base:"
" offset:<register "
" offset-shift-type:"
" offset-shift-amount:"
" offset:"
" (offset-is-reg)"
" (pre-indexed)"
" (post-indexed)"
" (negative)"
" (writeback)"
">"
"<ARM_PROC::"
2
0
1
ARM_PROC::IFlagsToString
1
">"
"<register "
">"
"<shifter "
">"
"<register_list "
", "
">"
"'"
"'"


<s>
void
MipsRegisterBankInfo
::
setRegBank
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
)
const
{
Register
Dest
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_STORE
:
break
;
case
TargetOpcode
::
G_CONSTANT
:
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_SELECT
:
case
TargetOpcode
::
G_PHI
:
case
TargetOpcode
::
G_IMPLICIT_DEF
:
{
assert
(
MRI
.
getType
(
Dest
)
==
LLT
::
scalar
(
32
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
case
TargetOpcode
::
G_PTR_ADD
:
{
assert
(
MRI
.
getType
(
Dest
)
.
isPointer
(
)
&&
"Unexpected operand type."
)
;
MRI
.
setRegBank
(
Dest
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected opcode."
)
;
}
}
</s>

RegBankSelect determined that s64 operand is better to be split into two s32 operands in gprb .

Mips
Mips
0
32
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected operand type."
Mips::GPRBRegBankID
"Unexpected opcode."


<s> bool AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> static void ix86_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx mem , fnaddr ; int opcode ; int offset = 0 ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; if ( TARGET_64BIT ) { int size ; if ( ptr_mode == SImode || x86_64_zext_immediate_operand ( fnaddr , VOIDmode ) ) { fnaddr = copy_addr_to_reg ( fnaddr ) ; mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0xbb41 , HImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + 2 ) ; emit_move_insn ( mem , gen_lowpart ( SImode , fnaddr ) ) ; offset += 6 ; } else { mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0xbb49 , HImode ) ) ; mem = adjust_address ( m_tramp , DImode , offset + 2 ) ; emit_move_insn ( mem , fnaddr ) ; offset += 10 ; } if ( ptr_mode == SImode ) { opcode = 0xba41 ; size = 6 ; } else { opcode = 0xba49 ; size = 10 ; } mem = adjust_address ( m_tramp , HImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , HImode ) ) ; mem = adjust_address ( m_tramp , ptr_mode , offset + 2 ) ; emit_move_insn ( mem , chain_value ) ; offset += size ; mem = adjust_address ( m_tramp , SImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0x90e3ff49 , SImode ) ) ; offset += 4 ; } else { rtx disp , chain ; chain = ix86_static_chain ( fndecl , true ) ; if ( REG_P ( chain ) ) { switch ( REGNO ( chain ) ) { case AX_REG : opcode = 0xb8 ; break ; case CX_REG : opcode = 0xb9 ; break ; default : gcc_unreachable ( ) ; } } else opcode = 0x68 ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( opcode , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + 1 ) ; emit_move_insn ( mem , chain_value ) ; offset += 5 ; mem = adjust_address ( m_tramp , QImode , offset ) ; emit_move_insn ( mem , gen_int_mode ( 0xe9 , QImode ) ) ; mem = adjust_address ( m_tramp , SImode , offset + 1 ) ; offset += 5 ; disp = expand_binop ( SImode , sub_optab , fnaddr , plus_constant ( Pmode , XEXP ( m_tramp , 0 ) , offset - ( MEM_P ( chain ) ? 1 : 0 ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; emit_move_insn ( mem , disp ) ; } gcc_assert ( offset <= TRAMPOLINE_SIZE ) ; if ( CHECK_EXECUTE_STACK_ENABLED ) emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , 1 , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNDECL is the decl of the target address ; M_TRAMP is a MEM for the trampoline , and CHAIN_VALUE is an RTX for the static chain to be passed to the target function .


<s> bool PPCPassConfig :: addInstSelector ( ) { addPass ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoopsVerify ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> uint64_t SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == TargetOpcode :: INLINEASM ) { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI -> getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> MCSection * LanaiTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align , const GlobalObject * GO ) const { if ( isConstantInSmallSection ( DL , C ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Align , GO ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
int
SystemZRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .