<s> SDValue ARMTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : return PerformADDCombine ( N , DCI ) ; case ISD :: SUB : return PerformSUBCombine ( N , DCI ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , Subtarget ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ARMISD :: VMOVRRD : return PerformVMOVRRDCombine ( N , DCI ) ; case ARMISD :: VDUPLANE : return PerformVDUPLANECombine ( N , DCI ) ; case ISD :: INTRINSIC_WO_CHAIN : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case ISD :: SELECT_CC : return PerformSELECT_CCCombine ( N , DCI . DAG , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

ARM ARM ISD::ADD ISD::SUB ISD::MUL ISD::OR ARMISD::VMOVRRD ARMISD::VDUPLANE ISD::INTRINSIC_WO_CHAIN ISD::SHL ISD::SRA ISD::SRL ISD::SIGN_EXTEND ISD::ZERO_EXTEND ISD::ANY_EXTEND ISD::SELECT_CC


<s> inline hashval_t wrapped_symbol_hasher :: hash ( const value_type * v ) { return htab_hash_string ( v ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> static void mips_swap_registers ( unsigned int i ) { int tmpi ; const char * tmps ; SWAP_INT ( fixed_regs [ i ] , fixed_regs [ i + 1 ] ) ; SWAP_INT ( call_used_regs [ i ] , call_used_regs [ i + 1 ] ) ; SWAP_INT ( call_really_used_regs [ i ] , call_really_used_regs [ i + 1 ] ) ; SWAP_STRING ( reg_names [ i ] , reg_names [ i + 1 ] ) ; } </s>

Swap the register information for registers I and I + 1 , which currently have the wrong endianness . Note that the registers ' fixedness and call-clobberedness might have been set on the command line .


<s> TargetLowering :: AtomicExpansionKind AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= 128 ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Mips OptimizePICCall"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> void rs6000_expand_vector_set ( rtx target , rtx val , int elt ) { machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx reg = gen_reg_rtx ( mode ) ; rtx mask , mem , x ; int width = GET_MODE_SIZE ( inner_mode ) ; int i ; if ( VECTOR_MEM_VSX_P ( mode ) && ( mode == V2DFmode || mode == V2DImode ) ) { rtx ( * set_func ) ( rtx , rtx , rtx , rtx ) = ( ( mode == V2DFmode ) ? gen_vsx_set_v2df : gen_vsx_set_v2di ) ; emit_insn ( set_func ( target , target , val , GEN_INT ( elt ) ) ) ; return ; } if ( GET_MODE_SIZE ( mode ) == GET_MODE_SIZE ( inner_mode ) && elt == 0 ) { emit_move_insn ( target , gen_lowpart ( mode , val ) ) ; return ; } mem = assign_stack_temp ( mode , GET_MODE_SIZE ( inner_mode ) ) ; emit_move_insn ( adjust_address_nv ( mem , inner_mode , 0 ) , val ) ; x = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LVE ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( reg , mem ) , x ) ) ) ; mask = gen_rtx_PARALLEL ( V16QImode , rtvec_alloc ( 16 ) ) ; for ( i = 0 ; i < 16 ; ++ i ) XVECEXP ( mask , 0 , i ) = GEN_INT ( i ) ; for ( i = 0 ; i < width ; ++ i ) XVECEXP ( mask , 0 , elt * width + i ) = GEN_INT ( i + 0x10 ) ; x = gen_rtx_CONST_VECTOR ( V16QImode , XVEC ( mask , 0 ) ) ; if ( BYTES_BIG_ENDIAN ) x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , target , reg , force_reg ( V16QImode , x ) ) , UNSPEC_VPERM ) ; else { rtx notx = gen_rtx_NOT ( V16QImode , force_reg ( V16QImode , x ) ) ; rtx iorx = ( TARGET_P8_VECTOR ? gen_rtx_IOR ( V16QImode , notx , notx ) : gen_rtx_AND ( V16QImode , notx , notx ) ) ; rtx tmp = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_rtx_SET ( tmp , iorx ) ) ; x = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , reg , target , tmp ) , UNSPEC_VPERM ) ; } emit_insn ( gen_rtx_SET ( target , x ) ) ; } </s>


<s> unsigned char X86Subtarget :: classifyGlobalFunctionReference ( const GlobalValue * GV , const Module & M ) const { if ( shouldAssumeDSOLocal ( TM . getRelocationModel ( ) , TargetTriple , M , GV ) ) return X86II :: MO_NO_FLAG ; assert ( ! isTargetCOFF ( ) ) ; if ( isTargetELF ( ) ) return X86II :: MO_PLT ; if ( is64Bit ( ) ) { auto * F = dyn_cast_or_null < Function > ( GV ) ; if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) return X86II :: MO_GOTPCREL ; return X86II :: MO_NO_FLAG ; } if ( ! getTargetTriple ( ) . isMacOSX ( ) || getTargetTriple ( ) . isMacOSXVersionLT ( 10 , 5 ) ) return X86II :: MO_DARWIN_STUB ; return X86II :: MO_NO_FLAG ; } </s>

Classify a global function reference for the current subtarget .


<s>
int
ARM64LoadStoreOpt
::
getMemSize
(
MachineInstr
*
MemMI
)
{
switch
(
MemMI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has has unknown size!"
)
;
case
ARM64
::
STRSui
:
case
ARM64
::
STURSi
:
return
4
;
case
ARM64
::
STRDui
:
case
ARM64
::
STURDi
:
return
8
;
case
ARM64
::
STRQui
:
case
ARM64
::
STURQi
:
return
16
;
case
ARM64
::
STRWui
:
case
ARM64
::
STURWi
:
return
4
;
case
ARM64
::
STRXui
:
case
ARM64
::
STURXi
:
return
8
;
case
ARM64
::
LDRSui
:
case
ARM64
::
LDURSi
:
return
4
;
case
ARM64
::
LDRDui
:
case
ARM64
::
LDURDi
:
return
8
;
case
ARM64
::
LDRQui
:
case
ARM64
::
LDURQi
:
return
16
;
case
ARM64
::
LDRWui
:
case
ARM64
::
LDURWi
:
return
4
;
case
ARM64
::
LDRXui
:
case
ARM64
::
LDURXi
:
return
8
;
}
}
</s>

Returns the size in bytes of the memory access .


<s> bool MipsTargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) { PM . add ( createMipsExpandPseudoPass ( * this ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"Don't replace SQRT with RSQRT for half type"

Hooks for building estimates in place of slower divisions and square roots .


"\t ! references to jmptbl section entries\n"

"\t ! references to vector section entries\n"

Function to emit isr reset handler content . Including all jmptbl/vector references , jmptbl section , vector section , nmi handler section , and warm handler section .


<s> static int ix86_mode_entry ( int entity ) { switch ( entity ) { case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC : case I387_FLOOR : case I387_CEIL : case I387_MASK_PM : return I387_CW_ANY ; default : gcc_unreachable ( ) ; } } </s>

Return a mode that ENTITY is assumed to be switched to at function entry .


<s> void OpenRISCFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s>
void
ia64_start_function
(
FILE
*
file
,
const
char
*
fnname
,
tree
decl
ATTRIBUTE_UNUSED
)
{
vms_start_function
(
fnname
)
;
fputs
(
"\t.proc "
,
file
)
;
assemble_name
(
file
,
fnname
)
;
fputc
(
'\n'
,
file
)
;
ASM_OUTPUT_LABEL
(
file
,
fnname
)
;
}
</s>

Output the textual info surrounding the prologue .


<s> bool MipsTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) && Type == MVT :: i32 ) return true ; return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


<s> bool enableInterleavedAccessVectorization ( ) { return true ; } </s>

Enable matching of interleaved access groups .


<s> static void ia64_h_i_d_extended ( void ) { if ( stops_p != NULL ) { int new_clocks_length = get_max_uid ( ) * 3 / 2 ; stops_p = ( char * ) xrecalloc ( stops_p , new_clocks_length , clocks_length , 1 ) ; clocks_length = new_clocks_length ; } } </s>

Implement targetm.sched.h_i_d_extended hook . Extend internal data structures .


<s> static void mips_prepare_builtin_arg ( struct expand_operand * op , tree exp , unsigned int argno ) { tree arg ; rtx value ; arg = CALL_EXPR_ARG ( exp , argno ) ; value = expand_normal ( arg ) ; create_input_operand ( op , value , TYPE_MODE ( TREE_TYPE ( arg ) ) ) ; } </s>

Take the head of argument list * ARGLIST and convert it into a form suitable for input operand OP of instruction ICODE . Return the value and point * ARGLIST at the next element of the list .


<s> static int mips_multipass_dfa_lookahead ( void ) { if ( TUNE_SB1 ) return 4 ; if ( TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A ) return 4 ; if ( TUNE_OCTEON ) return 2 ; if ( TUNE_P5600 || TUNE_I6400 ) return 4 ; return 0 ; } </s>


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void restore_saved_cr ( rtx reg , bool using_mfcr_multiple , bool exit_func ) { int count = 0 ; int i ; if ( using_mfcr_multiple ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) count ++ ; gcc_assert ( count ) ; } if ( using_mfcr_multiple && count > 1 ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = reg ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } else for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; add_reg_note ( insn , REG_CFA_RESTORE , cr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>


<s> bool mips_split_move_p ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_mult_move_p ( dest , src , split_type ) ) return false ; unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == 8 && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == 8 && ISA_HAS_LDC1_SDC1 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } return size > UNITS_PER_WORD ; } </s>

Return true if a move from SRC to DEST should be split into two . SPLIT_TYPE describes the split condition .


<s> Optional < DestSourcePair > X86InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


<s> void setType ( StringRef Type ) { CurType = Type ; } </s>


<s> void nds32_expand_epilogue_v3pop ( bool sibcall_p ) { int sp_adjust ; rtx Rb , Re ; rtx sp_adjust_insn ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) { nds32_emit_stack_v3pop ( Rb , Re , GEN_INT ( 14 ) , GEN_INT ( sp_adjust ) ) ; } else { if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - 1 * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = nds32_force_addi_stack_int ( sp_adjust ) ; if ( sp_adjust ) { sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; } } nds32_emit_stack_v3pop ( Rb , Re , GEN_INT ( 14 ) , GEN_INT ( 0 ) ) ; } emit_jump_insn ( gen_pop25return ( ) ) ; } </s>


<s> static dispatch_windows * allocate_next_window ( int window_num ) { if ( window_num == 0 ) { if ( dispatch_window_list -> next ) init_window ( 1 ) ; init_window ( 0 ) ; return dispatch_window_list ; } dispatch_window_list -> next = dispatch_window_list1 ; dispatch_window_list1 -> prev = dispatch_window_list ; return dispatch_window_list1 ; } </s>

Allocates a new dispatch window and adds it to WINDOW_LIST . WINDOW_NUM is either 0 or 1 . A maximum of two windows are generated for 48 bytes of instructions . Note that these windows are not dispatch windows that their sizes are DISPATCH_WINDOW_SIZE .


<s> static rtx arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx , insn ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; offset_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , orig , offset_rtx ) , UNSPEC_SYMBOL_OFFSET ) ; offset_rtx = gen_rtx_CONST ( Pmode , offset_rtx ) ; insn = emit_insn ( gen_pic_load_addr_unified ( reg , offset_rtx , labelno ) ) ; return insn ; } </s>

Generate code to load the address of a static var when flag_pic is set .


<s> bool Cpu0SEFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return isInt < 16 > ( MFI . getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI . hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , PPC :: G8RCRegisterClass ) ; return std :: make_pair ( 0U , PPC :: GPRCRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , PPC :: F4RCRegisterClass ) ; else if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , PPC :: F8RCRegisterClass ) ; break ; case 'v' : return std :: make_pair ( 0U , PPC :: VRRCRegisterClass ) ; case 'y' : return std :: make_pair ( 0U , PPC :: CRRCRegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static enum mips_symbol_type mips_classify_symbol ( const_rtx x , enum mips_symbol_context context ) { if ( TARGET_RTP_PIC ) return SYMBOL_GOT_DISP ; if ( GET_CODE ( x ) == LABEL_REF ) { if ( TARGET_MIPS16_SHORT_JUMP_TABLES && ! LABEL_REF_NONLOCAL_P ( x ) ) return SYMBOL_PC_RELATIVE ; if ( TARGET_ABICALLS && ! TARGET_ABSOLUTE_ABICALLS ) return SYMBOL_GOT_PAGE_OFST ; return SYMBOL_ABSOLUTE ; } gcc_assert ( GET_CODE ( x ) == SYMBOL_REF ) ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( CONSTANT_POOL_ADDRESS_P ( x ) ) { if ( TARGET_MIPS16_TEXT_LOADS ) return SYMBOL_PC_RELATIVE ; if ( TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM ) return SYMBOL_PC_RELATIVE ; if ( mips_rtx_constant_in_small_data_p ( get_pool_mode ( x ) ) ) return SYMBOL_GP_RELATIVE ; } if ( TARGET_GPOPT && SYMBOL_REF_SMALL_P ( x ) && ! SYMBOL_REF_WEAK ( x ) ) return SYMBOL_GP_RELATIVE ; if ( TARGET_ABICALLS_PIC2 && ! ( TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p ( x ) ) ) { if ( mips_global_symbol_p ( x ) ) return SYMBOL_GOT_DISP ; return SYMBOL_GOT_PAGE_OFST ; } return SYMBOL_ABSOLUTE ; } </s>

Classify symbol X , which must be a SYMBOL_REF or a LABEL_REF .


<s> static int xstormy16_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( 5 + memory_move_secondary_cost ( mode , rclass , in ) ) ; } </s>

Worker function for TARGET_MEMORY_MOVE_COST .


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode || mode == V4BFmode || mode == V8BFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; if ( TARGET_HAVE_MVE && ( mode == V2DImode || mode == V4SImode || mode == V8HImode || mode == V16QImode || mode == V16BImode || mode == V8BImode || mode == V4BImode ) ) return true ; if ( TARGET_HAVE_MVE_FLOAT && ( mode == V2DFmode || mode == V4SFmode || mode == V8HFmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> static enum mips_split_type mips_insn_split_type ( rtx insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; if ( bb ) { if ( optimize_bb_for_speed_p ( bb ) ) return SPLIT_FOR_SPEED ; else return SPLIT_FOR_SIZE ; } return SPLIT_IF_NECESSARY ; } </s>

Return the split type for instruction INSN .


<s> void TOYInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( TOY :: MOVrr ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } </s>


<s> static bool ia64_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == POINTER_SIZE / BITS_PER_UNIT && ! ( TARGET_NO_PIC || TARGET_AUTO_PIC ) && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) ) { static const char * const directive [ 2 ] [ 2 ] = { { "\tdata8.ua\t@fptr(" , "\tdata4.ua\t@fptr(" } , { "\tdata8\t@fptr(" , "\tdata4\t@fptr(" } } ; fputs ( directive [ ( aligned_p != 0 ) ] [ POINTER_SIZE == 32 ] , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( ")\n" , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . Handle word-sized aligned objects and detect the cases when @ fptr is needed .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { Value = adjustFixupValue ( Fixup . getKind ( ) , Value ) ; if ( ! Value ) return ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; unsigned Offset = Fixup . getOffset ( ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 ) - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> unsigned AArch64RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? AArch64 :: FP : AArch64 :: SP ; } </s>


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>


<s> static void mips_init_dfa_post_cycle_insn ( void ) { if ( TUNE_LOONGSON_2EF ) mips_ls2_init_dfa_post_cycle_insn ( ) ; } </s>

Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook . Init data used in mips_dfa_post_advance_cycle .


<s> bool equals ( const CSKYConstantPoolJT * A ) const { return JTI == A -> JTI && CSKYConstantPoolValue :: equals ( A ) ; } </s>

equals - Check for string equality , this is more efficient than compare ( ) when the relative ordering of inequal strings is n't needed .


<s> static void mips16e_mask_registers ( unsigned int * mask_ptr , const unsigned char * regs , unsigned int size , unsigned int * num_regs_ptr ) { unsigned int i ; i = mips16e_find_first_register ( * mask_ptr , regs , size ) ; for ( i ++ ; i < size ; i ++ ) if ( ! BITSET_P ( * mask_ptr , regs [ i ] ) ) { * num_regs_ptr += 1 ; * mask_ptr |= 1 << regs [ i ] ; } } </s>

* MASK_PTR is a mask of general-purpose registers and * NUM_REGS_PTR is the number of set bits . If * MASK_PTR contains REGS [ X ] for some X in [ 0 , SIZE ) , adjust * MASK_PTR and * NUM_REGS_PTR so that the same is true for all indexes ( X , SIZE ) .


<s> static rtx rx_function_value ( const_tree ret_type , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode = TYPE_MODE ( ret_type ) ; if ( GET_MODE_SIZE ( mode ) > 0 && GET_MODE_SIZE ( mode ) < 4 && ! COMPLEX_MODE_P ( mode ) && ! VECTOR_TYPE_P ( ret_type ) && ! VECTOR_MODE_P ( mode ) ) return gen_rtx_REG ( SImode , FUNC_RETURN_REGNUM ) ; return gen_rtx_REG ( mode , FUNC_RETURN_REGNUM ) ; } </s>

Return an RTL describing where a function return value of type RET_TYPE is held .


"MMIX Internal: %s is not a shiftable integer"

Print the presumed shiftable wyde argument shifted into place ( to be output with an operand ) .


"Can't break virtual register dependencies."

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> std :: pair < unsigned , const TargetRegisterClass * > ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb1Only ( ) ) return std :: make_pair ( 0U , ARM :: tGPRRegisterClass ) ; else return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'r' : return std :: make_pair ( 0U , ARM :: GPRRegisterClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , ARM :: SPRRegisterClass ) ; if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , ARM :: DPRRegisterClass ) ; break ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>


<s> const char * TeeRISCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case TeeRISC_ISD :: RET : return "TeeRISC_ISD::RET" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static int dispatch_function_versions ( tree dispatch_decl , void * fndecls_p , basic_block * empty_bb ) { tree default_decl ; gimple * ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = 0 ; unsigned int actual_versions = 0 ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= 2 ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - 1 ) ) ; default_decl = ( * fndecls ) [ 0 ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( ix86_builtins [ ( int ) IX86_BUILTIN_CPU_INIT ] , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = 1 ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority = priority ; actual_versions ++ ; } qsort ( function_version_info , actual_versions , sizeof ( struct _function_version_info ) , feature_compare ) ; for ( i = 0 ; i < actual_versions ; ++ i ) * empty_bb = add_condition_to_bb ( dispatch_decl , function_version_info [ i ] . version_decl , function_version_info [ i ] . predicate_chain , * empty_bb ) ; * empty_bb = add_condition_to_bb ( dispatch_decl , default_decl , NULL , * empty_bb ) ; free ( function_version_info ) ; return 0 ; } </s>

This function generates the dispatch function for multi-versioned functions . DISPATCH_DECL is the function which will contain the dispatch logic . FNDECLS are the function choices for dispatch , and is a tree chain . EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch code is generated .


<s> bool Mips16RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s>
static
void
nds32_emit_section_tail_template
(
char
symbol_name
[
]
)
{
fprintf
(
asm_out_file
,
"\t.size\t%s, .-%s\n"
,
symbol_name
,
symbol_name
)
;
}
</s>

A helper function to emit section tail template .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s> void reset ( ) override { MappingSymbolCounter = 0 ; MCELFStreamer :: reset ( ) ; LastMappingSymbols . clear ( ) ; LastEMS = EMS_None ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_SBFX
:
case
TargetOpcode
::
G_UBFX
:
return
legalizeBitfieldExtract
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ROTR
:
return
legalizeRotate
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTPOP
:
return
legalizeCTPOP
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpxchg128
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTTZ
:
return
legalizeCTTZ
(
MI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> static bool sparc_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { enum mode_class mclass1 , mclass2 ; unsigned short size1 , size2 ; if ( mode1 == mode2 ) return true ; mclass1 = GET_MODE_CLASS ( mode1 ) ; mclass2 = GET_MODE_CLASS ( mode2 ) ; if ( mclass1 != mclass2 ) return false ; if ( ! TARGET_V9 ) return true ; if ( mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT ) return true ; size1 = GET_MODE_SIZE ( mode1 ) ; size2 = GET_MODE_SIZE ( mode2 ) ; if ( ( size1 > 4 && size2 == 4 ) || ( size2 > 4 && size1 == 4 ) ) return false ; return true ; } </s>

Return TRUE if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2 . If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2 , for any hard reg , then this must be FALSE for correct output . For V9 we have to deal with the fact that only the lower 32 floating point registers are 32-bit addressable .


<s> bool PPCTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { return isInt < 16 > ( Imm ) || isUInt < 16 > ( Imm ) ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> bool ARMOptimizeBarriersPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - 1 ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == ARM :: DMB ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( 0 ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else { IsRemovableNextDMB = true ; DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else if ( ! CanMovePastDMB ( & MI ) ) { IsRemovableNextDMB = false ; } } } bool Changed = false ; for ( auto MI : ToRemove ) { MI -> eraseFromParent ( ) ; ++ NumDMBsRemoved ; Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
MachineInstr
*
PPCInstrInfo
::
commuteInstruction
(
MachineInstr
*
MI
,
bool
NewMI
)
const
{
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
if
(
MI
->
getOpcode
(
)
!=
PPC
::
RLWIMI
)
return
TargetInstrInfo
::
commuteInstruction
(
MI
,
NewMI
)
;
if
(
MI
->
getOperand
(
3
)
.
getImm
(
)
!=
0
)
return
0
;
unsigned
Reg0
=
MI
->
getOperand
(
0
)
.
getReg
(
)
;
unsigned
Reg1
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
Reg2
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
bool
Reg1IsKill
=
MI
->
getOperand
(
1
)
.
isKill
(
)
;
bool
Reg2IsKill
=
MI
->
getOperand
(
2
)
.
isKill
(
)
;
bool
ChangeReg0
=
false
;
if
(
Reg0
==
Reg1
)
{
assert
(
MI
->
getDesc
(
)
.
getOperandConstraint
(
0
,
MCOI
::
TIED_TO
)
&&
"Expecting a two-address instruction!"
)
;
Reg2IsKill
=
false
;
ChangeReg0
=
true
;
}
unsigned
MB
=
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
ME
=
MI
->
getOperand
(
5
)
.
getImm
(
)
;
if
(
NewMI
)
{
unsigned
Reg0
=
ChangeReg0
Reg2
:
MI
->
getOperand
(
0
)
.
getReg
(
)
;
bool
Reg0IsDead
=
MI
->
getOperand
(
0
)
.
isDead
(
)
;
return
BuildMI
(
MF
,
MI
->
getDebugLoc
(
)
,
MI
->
getDesc
(
)
)
.
addReg
(
Reg0
,
RegState
::
Define
|
getDeadRegState
(
Reg0IsDead
)
)
.
addReg
(
Reg2
,
getKillRegState
(
Reg2IsKill
)
)
.
addReg
(
Reg1
,
getKillRegState
(
Reg1IsKill
)
)
.
addImm
(
(
ME
+
1
)
&
31
)
.
addImm
(
(
MB
1
)
&
31
)
;
}
if
(
ChangeReg0
)
MI
->
getOperand
(
0
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setReg
(
Reg1
)
;
MI
->
getOperand
(
1
)
.
setReg
(
Reg2
)
;
MI
->
getOperand
(
2
)
.
setIsKill
(
Reg1IsKill
)
;
MI
->
getOperand
(
1
)
.
setIsKill
(
Reg2IsKill
)
;
MI
->
getOperand
(
4
)
.
setImm
(
(
ME
+
1
)
&
31
)
;
MI
->
getOperand
(
5
)
.
setImm
(
(
MB
1
)
&
31
)
;
return
MI
;
}
</s>

This method commutes the operands of the given machine instruction MI .


<s> static bool aarch64_return_in_memory_1 ( const_tree type ) { HOST_WIDE_INT size ; machine_mode ag_mode ; int count ; if ( ! AGGREGATE_TYPE_P ( type ) && TREE_CODE ( type ) != COMPLEX_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) return false ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & ag_mode , & count , NULL , false ) ) return false ; size = int_size_in_bytes ( type ) ; return ( size < 0 || size > 2 * UNITS_PER_WORD ) ; } </s>

Subroutine for aarch64_return_in_memory for types that are not returned in SVE registers .


<s> bool isToken ( ) const { return Kind == Token ; } </s>


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const Function * Fn = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || Fn -> needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < X86MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == 0 ) return ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( Fn -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } if ( DwarfCFI && ! hasFP ( MF ) ) { int CFAOffset = Amount ; if ( CFAOffset ) { CFAOffset = isDestroy ? - CFAOffset : CFAOffset ; BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , CFAOffset ) ) ; } } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> EVT AArch64TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { bool Fast ; const Function * F = MF . getFunction ( ) ; if ( Subtarget -> hasFPARMv8 ( ) && ! IsMemset && Size >= 16 && ! F -> hasFnAttribute ( Attribute :: NoImplicitFloat ) && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsMisalignedMemoryAccesses ( MVT :: f128 , 0 , 1 , & Fast ) && Fast ) ) ) return MVT :: f128 ; return Size >= 8 ? MVT :: i64 : MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DstReg
,
const
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
getCMovFromCond
(
(
X86
::
CondCode
)
Cond
[
0
]
.
getImm
(
)
,
MRI
.
getRegClass
(
DstReg
)
->
getSize
(
)
/
8
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> bool isCheapToSpeculateCtlz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic ctlz .


"Floating-point constant is not a positive zero."

Emit the floating-point constant +0.0 in a register using target- specific logic .


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_cpu_index
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_tune_index
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
rs6000_default_cpu
==
0
||
rs6000_default_cpu
[
0
]
==
'\0'
||
!
global_options_set
.
x_rs6000_cpu_index
)
{
fputs
(
"\t.machine "
,
asm_out_file
)
;
if
(
(
rs6000_isa_flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
fputs
(
"power8\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
fputs
(
"power7\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_CMPB
)
!=
0
)
fputs
(
"power6\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
fputs
(
"power5\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MFCRF
)
!=
0
)
fputs
(
"power4\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
fputs
(
"ppc64\n"
,
asm_out_file
)
;
else
fputs
(
"ppc\n"
,
asm_out_file
)
;
}
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
||
(
TARGET_ELF
&&
flag_pic
==
2
)
)
{
switch_to_section
(
toc_section
)
;
switch_to_section
(
text_section
)
;
}
}
</s>

Do anything needed at the start of the asm file .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . isPPC64 ( ) ? CSR_Darwin64_RegMask : CSR_Darwin32_RegMask ; return Subtarget . isPPC64 ( ) ? CSR_SVR464_RegMask : CSR_SVR432_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void MipsGOT :: reserve ( size_t pNum ) { for ( size_t i = 0 ; i < pNum ; ++ i ) createEntry ( 0 , m_SectionData ) ; } </s>

Grow the map so that it has at least Size buckets . Does not shrink .


<s>
char
*
aarch64_output_sve_ptrues
(
rtx
const_unspec
)
{
static
char
templ
[
40
]
;
struct
simd_immediate_info
info
;
bool
is_valid
=
aarch64_simd_valid_immediate
(
const_unspec
,
&
info
)
;
gcc_assert
(
is_valid
&&
info
.
insn
==
simd_immediate_info
::
PTRUE
)
;
char
element_char
=
sizetochar
(
GET_MODE_BITSIZE
(
info
.
elt_mode
)
)
;
snprintf
(
templ
,
sizeof
(
templ
)
,
"ptrues\t%%0.%c, %s"
,
element_char
,
svpattern_token
(
info
.
u
.
pattern
)
)
;
return
templ
;
}
</s>

Return the asm template for a PTRUES . CONST_UNSPEC is the aarch64_sve_ptrue_svpattern_immediate that describes the predicate pattern .


<s> static void mep_init_intrinsics ( void ) { size_t i ; mep_selected_isa = mep_configs [ 0 ] . isa ; if ( mep_config_string != 0 ) for ( i = 0 ; mep_configs [ i ] . config_name ; i ++ ) if ( strcmp ( mep_config_string , mep_configs [ i ] . config_name ) == 0 ) { mep_selected_isa = mep_configs [ i ] . isa ; break ; } for ( i = 0 ; i < ARRAY_SIZE ( mep_intrinsic_insn ) ; i ++ ) mep_intrinsic_insn [ i ] = - 1 ; for ( i = 0 ; i < ARRAY_SIZE ( cgen_insns ) ; i ++ ) if ( ( cgen_insns [ i ] . isas & mep_selected_isa ) != 0 ) { mep_intrinsic_chain [ i ] = mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ] ; mep_intrinsic_insn [ cgen_insns [ i ] . intrinsic ] = i ; } for ( i = 0 ; i < ARRAY_SIZE ( mep_cmov_insns ) ; i ++ ) if ( MEP_INTRINSIC_AVAILABLE_P ( mep_cmov_insns [ i ] ) ) mep_have_copro_copro_moves_p = true ; mep_have_core_copro_moves_p = ( MEP_INTRINSIC_AVAILABLE_P ( mep_cmov1 ) && MEP_INTRINSIC_AVAILABLE_P ( mep_cmov2 ) ) ; mep_have_core_copro_moves_p = 1 ; } </s>

Initialize the global intrinsics variables above .


<s> void PPCPostRASchedStrategy :: tryCandidate ( SchedCandidate & Cand , SchedCandidate & TryCand ) { if ( ! Cand . isValid ( ) ) { TryCand . Reason = NodeOrder ; return ; } if ( tryLess ( Top . getLatencyStallCycles ( TryCand . SU ) , Top . getLatencyStallCycles ( Cand . SU ) , TryCand , Cand , Stall ) ) return ; if ( tryGreater ( TryCand . SU == DAG -> getNextClusterSucc ( ) , Cand . SU == DAG -> getNextClusterSucc ( ) , TryCand , Cand , Cluster ) ) return ; if ( tryLess ( TryCand . ResDelta . CritResources , Cand . ResDelta . CritResources , TryCand , Cand , ResourceReduce ) ) return ; if ( tryGreater ( TryCand . ResDelta . DemandedResources , Cand . ResDelta . DemandedResources , TryCand , Cand , ResourceDemand ) ) return ; if ( Cand . Policy . ReduceLatency && tryLatency ( TryCand , Cand , Top ) ) { return ; } if ( TryCand . SU -> NodeNum < Cand . SU -> NodeNum ) TryCand . Reason = NodeOrder ; if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return ; if ( biasAddiCandidate ( Cand , TryCand ) ) return ; } </s>

Apply a set of heuristics to a new candidate .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; unsigned Flags = GV -> hasDLLImportStorageClass ( ) ? AArch64II :: MO_DLLIMPORT : AArch64II :: MO_NO_FLAG ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return AArch64II :: MO_GOT | Flags ; if ( useSmallAddressing ( ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT | Flags ; return Flags ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> RemoveOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . addOperand ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . addOperand ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s> static SDNode * getInt64 ( SelectionDAG * CurDAG , SDLoc dl , int64_t Imm ) { unsigned Count = getInt64CountDirect ( Imm ) ; if ( Count == 1 ) return getInt64Direct ( CurDAG , dl , Imm ) ; unsigned RMin = 0 ; int64_t MatImm ; unsigned MaskEnd ; for ( unsigned r = 1 ; r < 63 ; ++ r ) { uint64_t RImm = Rot64 ( Imm , r ) ; unsigned RCount = getInt64CountDirect ( RImm ) + 1 ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImm ; MaskEnd = 63 ; } unsigned LS = findLastSet ( RImm ) ; if ( LS != r - 1 ) continue ; uint64_t OnesMask = - ( int64_t ) ( UINT64_C ( 1 ) << ( LS + 1 ) ) ; uint64_t RImmWithOnes = RImm | OnesMask ; RCount = getInt64CountDirect ( RImmWithOnes ) + 1 ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImmWithOnes ; MaskEnd = LS ; } } if ( ! RMin ) return getInt64Direct ( CurDAG , dl , Imm ) ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , MVT :: i32 ) ; } ; SDValue Val = SDValue ( getInt64Direct ( CurDAG , dl , MatImm ) , 0 ) ; return CurDAG -> getMachineNode ( PPC :: RLDICR , dl , MVT :: i64 , Val , getI32Imm ( 64 - RMin ) , getI32Imm ( MaskEnd ) ) ; } </s>


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"


<s> int nds32_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( HARD_REGNO_NREGS ( regno , mode ) == 1 || ! ( ( regno ) & 1 ) ) return 1 ; return 0 ; } </s>


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < MipsSubtarget > ( ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


"This eliminateFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

"This code isn't needed if offset already handled!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool isMem ( ) const { return Kind == k_Memory ; } </s>


<s> void PPCLinuxAsmPrinter :: emitFunctionBodyStart ( ) { if ( Subtarget -> isELFv2ABI ( ) && ! MF -> getRegInfo ( ) . use_empty ( PPC :: X2 ) ) { const PPCFunctionInfo * PPCFI = MF -> getInfo < PPCFunctionInfo > ( ) ; MCSymbol * GlobalEntryLabel = PPCFI -> getGlobalEPSymbol ( ) ; OutStreamer -> emitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: create ( GlobalEntryLabel , OutContext ) ; if ( TM . getCodeModel ( ) != CodeModel :: Large ) { MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( ".TOC." ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = PPCMCExpr :: createHa ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: ADDIS ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X12 ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = PPCMCExpr :: createLo ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: ADDI ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X2 ) . addExpr ( TOCDeltaLo ) ) ; } else { MCSymbol * TOCOffset = PPCFI -> getTOCOffsetSymbol ( ) ; const MCExpr * TOCOffsetDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCOffset , OutContext ) , GlobalEntryLabelExp , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: LD ) . addReg ( PPC :: X2 ) . addExpr ( TOCOffsetDeltaExpr ) . addReg ( PPC :: X12 ) ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( PPC :: ADD8 ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X2 ) . addReg ( PPC :: X12 ) ) ; } MCSymbol * LocalEntryLabel = PPCFI -> getLocalEPSymbol ( ) ; OutStreamer -> emitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: create ( LocalEntryLabel , OutContext ) ; const MCExpr * LocalOffsetExp = MCBinaryExpr :: createSub ( LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ; PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitLocalEntry ( cast < MCSymbolELF > ( CurrentFnSym ) , LocalOffsetExp ) ; } } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> unsigned X86RegisterInfo :: getRARegister ( ) const { if ( Is64Bit ) return X86 :: RIP ; else return X86 :: EIP ; } </s>

This method should return the register where the return address can be found .


<s>
virtual
const
char
*
getPassName
(
)
const
override
{
return
"SIC Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Prefetch distance is not set for target"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool arm_slowmul_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = 30 ; return true ; } if ( GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 2 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost += 2 ; } * total = cost ; return true ; } * total = 30 + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : 4 ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : 4 ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>

RTX costs for cores with a slow MUL implementation . Thumb-2 is not supported on any `` slowmul '' cores , so it can be ignored .


<s>
void
AArch64InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MBBI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MBBI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
unsigned
Align
=
MFI
.
getObjectAlignment
(
FrameIdx
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
FrameIdx
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FrameIdx
)
,
Align
)
;
unsigned
StoreOp
=
0
;
if
(
RC
->
hasType
(
MVT
::
i64
)
||
RC
->
hasType
(
MVT
::
i32
)
)
{
switch
(
RC
->
getSize
(
)
)
{
case
4
:
StoreOp
=
AArch64
::
LS32_STR
;
break
;
case
8
:
StoreOp
=
AArch64
::
LS64_STR
;
break
;
default
:
llvm_unreachable
(
"Unknown size for regclass"
)
;
}
}
else
if
(
AArch64
::
FPR8RegClass
.
hasSubClassEq
(
RC
)
)
{
StoreOp
=
AArch64
::
LSFP8_STR
;
}
else
if
(
AArch64
::
FPR16RegClass
.
hasSubClassEq
(
RC
)
)
{
StoreOp
=
AArch64
::
LSFP16_STR
;
}
else
if
(
RC
->
hasType
(
MVT
::
f32
)
||
RC
->
hasType
(
MVT
::
f64
)
||
RC
->
hasType
(
MVT
::
f128
)
)
{
switch
(
RC
->
getSize
(
)
)
{
case
4
:
StoreOp
=
AArch64
::
LSFP32_STR
;
break
;
case
8
:
StoreOp
=
AArch64
::
LSFP64_STR
;
break
;
case
16
:
StoreOp
=
AArch64
::
LSFP128_STR
;
break
;
default
:
llvm_unreachable
(
"Unknown size for regclass"
)
;
}
}
else
{
if
(
AArch64
::
DPairRegClass
.
hasSubClassEq
(
RC
)
)
StoreOp
=
AArch64
::
ST1x2_8B
;
else
if
(
AArch64
::
DTripleRegClass
.
hasSubClassEq
(
RC
)
)
StoreOp
=
AArch64
::
ST1x3_8B
;
else
if
(
AArch64
::
DQuadRegClass
.
hasSubClassEq
(
RC
)
)
StoreOp
=
AArch64
::
ST1x4_8B
;
else
if
(
AArch64
::
QPairRegClass
.
hasSubClassEq
(
RC
)
)
StoreOp
=
AArch64
::
ST1x2_16B
;
else
if
(
AArch64
::
QTripleRegClass
.
hasSubClassEq
(
RC
)
)
StoreOp
=
AArch64
::
ST1x3_16B
;
else
if
(
AArch64
::
QQuadRegClass
.
hasSubClassEq
(
RC
)
)
StoreOp
=
AArch64
::
ST1x4_16B
;
else
llvm_unreachable
(
"Unknown reg class"
)
;
MachineInstrBuilder
NewMI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
StoreOp
)
)
;
NewMI
.
addFrameIndex
(
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addMemOperand
(
MMO
)
;
return
;
}
MachineInstrBuilder
NewMI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
get
(
StoreOp
)
)
;
NewMI
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIdx
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


runOnMachineFunction - Emit the function body .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
AsmVariant
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
printPCRelImm
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
printOperand
(
*
this
,
MI
,
OpNo
,
O
,
nullptr
,
AsmVariant
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
Register
||
Kind
==
CCOut
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> TargetPassConfig * X86TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new X86PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static void ix86_emit_save_regs ( void ) { unsigned int regno ; rtx_insn * insn ; for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno -- > 0 ; ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( word_mode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save registers in the prologue .


<s> static void computeKnownBits ( SelectionDAG & DAG , SDValue Op , APInt & KnownZero , APInt & KnownOne ) { if ( Op . getOpcode ( ) == ARMISD :: BFI ) { computeKnownBits ( DAG , Op . getOperand ( 0 ) , KnownZero , KnownOne ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; APInt Mask = CI -> getAPIntValue ( ) ; KnownZero &= Mask ; KnownOne &= Mask ; return ; } if ( Op . getOpcode ( ) == ARMISD :: CMOV ) { APInt KZ2 ( KnownZero . getBitWidth ( ) , 0 ) ; APInt KO2 ( KnownOne . getBitWidth ( ) , 0 ) ; computeKnownBits ( DAG , Op . getOperand ( 1 ) , KnownZero , KnownOne ) ; computeKnownBits ( DAG , Op . getOperand ( 2 ) , KZ2 , KO2 ) ; KnownZero &= KZ2 ; KnownOne &= KO2 ; return ; } return DAG . computeKnownBits ( Op , KnownZero , KnownOne ) ; } </s>

Determine which bits of Op are known to be either zero or one and return them in Known .


<s> bool aarch64_can_const_movi_rtx_p ( rtx x , machine_mode mode ) { if ( ! TARGET_SIMD ) return false ; machine_mode vmode ; scalar_int_mode imode ; unsigned HOST_WIDE_INT ival ; if ( CONST_DOUBLE_P ( x ) && SCALAR_FLOAT_MODE_P ( mode ) ) { if ( ! aarch64_reinterpret_float_as_int ( x , & ival ) ) return false ; if ( aarch64_float_const_zero_rtx_p ( x ) ) return true ; imode = int_mode_for_mode ( mode ) . require ( ) ; } else if ( CONST_INT_P ( x ) && is_a < scalar_int_mode > ( mode , & imode ) ) ival = INTVAL ( x ) ; else return false ; int width = GET_MODE_BITSIZE ( imode ) == 64 ? 128 : 64 ; vmode = aarch64_simd_container_mode ( imode , width ) ; rtx v_op = aarch64_simd_gen_const_vector_dup ( vmode , ival ) ; return aarch64_simd_valid_immediate ( v_op , NULL ) ; } </s>

Return TRUE if rtx X is immediate constant that fits in a single MOVI immediate operation .


<s> static rtx gen_compare_reg_1 ( enum rtx_code code , rtx x , rtx y ) { machine_mode mode ; rtx cc_reg ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_CC ) return x ; mode = SELECT_CC_MODE ( code , x , y ) ; if ( TARGET_V9 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { int reg ; static int next_fcc_reg = 0 ; static rtx prev_args [ 4 ] [ 2 ] ; for ( reg = 0 ; reg < 4 ; reg ++ ) if ( prev_args [ reg ] [ 0 ] == x && prev_args [ reg ] [ 1 ] == y ) break ; if ( reg == 4 ) { reg = next_fcc_reg ; prev_args [ reg ] [ 0 ] = x ; prev_args [ reg ] [ 1 ] = y ; next_fcc_reg = ( next_fcc_reg + 1 ) & 3 ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ; } cc_reg = gen_reg_rtx ( mode ) ; else if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) cc_reg = gen_rtx_REG ( mode , SPARC_FCC_REG ) ; else cc_reg = gen_rtx_REG ( mode , SPARC_ICC_REG ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ; return cc_reg ; } </s>

Emit the compare insn and return the CC reg for a CODE comparison with operands X and Y .


<s> bool isToken ( ) const override { return Kind == TOKEN ; } </s>


<s> CCAssignFn * MipsTargetLowering :: CCAssignFnForCall ( ) const { return CC_Mips_FixedArg ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
void
PPCHazardRecognizer970
::
EmitInstruction
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getGluedMachineNode
(
)
;
bool
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
;
PPCII
::
PPC970_Unit
InstrType
=
GetInstrType
(
Node
->
getOpcode
(
)
,
isFirst
,
isSingle
,
isCracked
,
isLoad
,
isStore
)
;
if
(
InstrType
==
PPCII
::
PPC970_Pseudo
)
return
;
unsigned
Opcode
=
Node
->
getMachineOpcode
(
)
;
if
(
Opcode
==
PPC
::
MTCTR
||
Opcode
==
PPC
::
MTCTR8
)
HasCTRSet
=
true
;
if
(
isStore
)
{
unsigned
ThisStoreSize
;
switch
(
Opcode
)
{
default
:
llvm_unreachable
(
"Unknown store instruction!"
)
;
case
PPC
::
STB
:
case
PPC
::
STB8
:
case
PPC
::
STBU
:
case
PPC
::
STBU8
:
case
PPC
::
STBX
:
case
PPC
::
STBX8
:
case
PPC
::
STVEBX
:
ThisStoreSize
=
1
;
break
;
case
PPC
::
STH
:
case
PPC
::
STH8
:
case
PPC
::
STHU
:
case
PPC
::
STHU8
:
case
PPC
::
STHX
:
case
PPC
::
STHX8
:
case
PPC
::
STVEHX
:
case
PPC
::
STHBRX
:
ThisStoreSize
=
2
;
break
;
case
PPC
::
STFS
:
case
PPC
::
STFSU
:
case
PPC
::
STFSX
:
case
PPC
::
STWX
:
case
PPC
::
STWX8
:
case
PPC
::
STWUX
:
case
PPC
::
STW
:
case
PPC
::
STW8
:
case
PPC
::
STWU
:
case
PPC
::
STVEWX
:
case
PPC
::
STFIWX
:
case
PPC
::
STWBRX
:
ThisStoreSize
=
4
;
break
;
case
PPC
::
STD_32
:
case
PPC
::
STDX_32
:
case
PPC
::
STD
:
case
PPC
::
STDU
:
case
PPC
::
STFD
:
case
PPC
::
STFDX
:
case
PPC
::
STDX
:
case
PPC
::
STDUX
:
ThisStoreSize
=
8
;
break
;
case
PPC
::
STVX
:
case
PPC
::
STVXL
:
ThisStoreSize
=
16
;
break
;
}
StoreSize
[
NumStores
]
=
ThisStoreSize
;
StorePtr1
[
NumStores
]
=
Node
->
getOperand
(
1
)
;
StorePtr2
[
NumStores
]
=
Node
->
getOperand
(
2
)
;
++
NumStores
;
}
if
(
InstrType
==
PPCII
::
PPC970_BRU
||
isSingle
)
NumIssued
=
4
;
++
NumIssued
;
if
(
isCracked
)
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { EnableVPU = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_CheriPureCap ( ) ) return CSR_Cheri_Purecap_RegMask ; if ( Subtarget . isCheri ( ) ) return CSR_N64_Cheri_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( ! isa < ScalableVectorType > ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF , I -> getFunction ( ) ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( ! isDarwin ( ) ) { if ( IDVal == ".word" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".tc" ) return ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".machine" ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; if ( IDVal == ".abiversion" ) return ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; if ( IDVal == ".localentry" ) return ParseDirectiveLocalEntry ( DirectiveID . getLoc ( ) ) ; } else { if ( IDVal == ".machine" ) return ParseDarwinDirectiveMachine ( DirectiveID . getLoc ( ) ) ; } return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Kind == 1 ) { if ( TM . isPPC64 ( ) ) return & PPC :: G8RC_NOX0RegClass ; return & PPC :: GPRC_NOR0RegClass ; } if ( TM . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s>
unsigned
CJGMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
if
(
MO
.
isExpr
(
)
)
{
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Constant
)
{
return
cast
<
MCConstantExpr
>
(
Expr
)
->
getValue
(
)
;
}
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
&&
"unknown MCExpr kind"
)
;
CJG
::
Fixups
FixupKind
=
CJG
::
Fixups
(
0
)
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_None
:
FixupKind
=
CJG
::
fixup_CJG_32
;
break
;
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool X86PassConfig :: addILPOpts ( ) { addPass ( & EarlyIfConverterID ) ; if ( EnableMachineCombinerPass ) addPass ( & MachineCombinerID ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function * F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F -> optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F -> optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> virtual EVT getSetCCResultType ( LLVMContext & , EVT ) const LLVM_OVERRIDE { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> void sparc_expand_vcond ( machine_mode mode , rtx * operands , int ccode , int fcode ) { rtx mask , cop0 , cop1 , fcmp , cmask , bshuf , gsr ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; mask = gen_reg_rtx ( Pmode ) ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( code == LT || code == GE ) { rtx t ; code = swap_condition ( code ) ; t = cop0 ; cop0 = cop1 ; cop1 = t ; } gsr = gen_rtx_REG ( DImode , SPARC_GSR_REG ) ; fcmp = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , gen_rtx_fmt_ee ( code , mode , cop0 , cop1 ) ) , fcode ) ; cmask = gen_rtx_UNSPEC ( DImode , gen_rtvec ( 2 , mask , gsr ) , ccode ) ; bshuf = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , operands [ 1 ] , operands [ 2 ] , gsr ) , UNSPEC_BSHUFFLE ) ; emit_insn ( gen_rtx_SET ( VOIDmode , mask , fcmp ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gsr , cmask ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , operands [ 0 ] , bshuf ) ) ; } </s>

Emit code to conditionally move a combination of OPERANDS [ 1 ] and OPERANDS [ 2 ] into OPERANDS [ 0 ] in MODE , depending on the outcome of the comparison of OPERANDS [ 4 ] and OPERANDS [ 5 ] . OPERANDS [ 3 ] is the operator of the condition . FCODE is the machine code to be used for OPERANDS [ 3 ] and CCODE the machine code to be used for the condition mask .


<s> rtx ia64_expand_compare ( enum rtx_code code , enum machine_mode mode ) { rtx op0 = ia64_compare_op0 , op1 = ia64_compare_op1 ; rtx cmp ; if ( GET_MODE ( op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && op1 == const0_rtx ) ; cmp = op0 ; } else if ( GET_MODE ( op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = 1 , QCMP_UNORD = 2 , QCMP_EQ = 4 , QCMP_LT = 8 , QCMP_GT = 16 } magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , 0 , LCT_CONST , DImode , 3 , op0 , TFmode , op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , op0 , op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( code , BImode , op0 , op1 ) ) ) ; code = NE ; } return gen_rtx_fmt_ee ( code , mode , cmp , const0_rtx ) ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode .


<s>
SDValue
SHUXITargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
if
(
IsVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SHUXI
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
SHUXIISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool DLXRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> bool LanaiInstrInfo :: expandPostRAPseudo ( MachineInstr & ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void ARMTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = KnownOne . getBitWidth ( ) ; KnownZero = KnownOne = APInt ( BitWidth , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case ARMISD :: ADDC : case ARMISD :: ADDE : case ARMISD :: SUBC : case ARMISD :: SUBE : if ( Op . getResNo ( ) == 0 ) break ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - 1 ) ; break ; case ARMISD :: CMOV : { DAG . computeKnownBits ( Op . getOperand ( 0 ) , KnownZero , KnownOne , Depth + 1 ) ; if ( KnownZero == 0 && KnownOne == 0 ) return ; APInt KnownZeroRHS , KnownOneRHS ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , KnownZeroRHS , KnownOneRHS , Depth + 1 ) ; KnownZero &= KnownZeroRHS ; KnownOne &= KnownOneRHS ; return ; } case ISD :: INTRINSIC_W_CHAIN : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case Intrinsic :: arm_ldaex : case Intrinsic :: arm_ldrex : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( TRI -> getSpillSize ( * RC ) , 16 ) ; bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> bool SystemZTargetLowering :: isTruncateFree ( EVT FromVT , EVT ToVT ) const { if ( ! FromVT . isInteger ( ) || ! ToVT . isInteger ( ) ) return false ; unsigned FromBits = FromVT . getFixedSizeInBits ( ) ; unsigned ToBits = ToVT . getFixedSizeInBits ( ) ; return FromBits > ToBits ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> bool mips_pad_reg_upward ( machine_mode mode , tree type ) { if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_pad_arg_upward ( mode , type ) ; } </s>

Likewise BLOCK_REG_PADDING ( MODE , TYPE , ... ) . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data . Return the opposite if the most significant byte does .


<s> static bool exact_store_load_dependency ( rtx_insn * store , rtx_insn * load ) { rtx set1 , set2 ; set1 = single_set ( store ) ; if ( ! set1 ) return false ; if ( ! MEM_P ( SET_DEST ( set1 ) ) ) return false ; set2 = single_set ( load ) ; if ( ! set2 ) return false ; if ( exact_dependency_1 ( SET_DEST ( set1 ) , SET_SRC ( set2 ) ) ) return true ; return false ; } </s>

Return true if there exists exact dependency for store & load , i.e . the same memory address is used in them .


<s> bool AArch64AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> const MCSection * MipsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( IsConstantInSmallSection ( C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool isTargetEHABICompatible ( ) const { return TargetTriple . isTargetEHABICompatible ( ) ; } </s>

Tests whether the target supports the EHABI exception handling standard .


<s> static void rs6000_finish_atomic_subword ( rtx narrow , rtx wide , rtx shift ) { wide = expand_simple_binop ( SImode , LSHIFTRT , wide , shift , wide , 1 , OPTAB_LIB_WIDEN ) ; emit_move_insn ( narrow , gen_lowpart ( GET_MODE ( narrow ) , wide ) ) ; } </s>

A subroutine of the various atomic expanders . For sub-word operands , extract WIDE to NARROW via SHIFT .


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> void MipsAsmPrinter :: emitFunctionEntryLabel ( ) { MipsTargetStreamer & TS = getTargetStreamer ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) emitAlignment ( std :: max ( MF -> getAlignment ( ) , MIPS_NACL_BUNDLE_ALIGN ) ) ; if ( Subtarget -> inMicroMipsMode ( ) ) { TS . emitDirectiveSetMicroMips ( ) ; TS . setUsesMicroMips ( ) ; TS . updateABIInfo ( * Subtarget ) ; } else TS . emitDirectiveSetNoMicroMips ( ) ; if ( Subtarget -> inMips16Mode ( ) ) TS . emitDirectiveSetMips16 ( ) ; else TS . emitDirectiveSetNoMips16 ( ) ; TS . emitDirectiveEnt ( * CurrentFnSym ) ; OutStreamer -> emitLabel ( CurrentFnSym ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> void LEGInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( LEG :: STR ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> TargetPassConfig * TOYTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TOYPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


Compute a bit mask of which core registers need to be saved on the stack for the current function .


<s> static bool sparc_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_FLAT ) return false ; return ! ( optimize > 0 && crtl -> is_leaf && only_leaf_regs_used ( ) ) ; } </s>


<s> TargetTransformInfo :: PopcntSupportKind FPGATTIImpl :: getPopcntSupport ( unsigned IntTyWidthInBit ) { return TTI :: PSK_FastHardware ; } </s>

Return hardware support for population count .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void scalar_chain :: convert_registers ( ) { bitmap_iterator bi ; unsigned id ; EXECUTE_IF_SET_IN_BITMAP ( defs_conv , 0 , id , bi ) { rtx chain_reg = gen_reg_rtx ( smode ) ; defs_map . put ( regno_reg_rtx [ id ] , chain_reg ) ; } EXECUTE_IF_SET_IN_BITMAP ( insns_conv , 0 , id , bi ) for ( df_ref ref = DF_INSN_UID_DEFS ( id ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( bitmap_bit_p ( defs_conv , DF_REF_REGNO ( ref ) ) ) make_vector_copies ( DF_REF_INSN ( ref ) , DF_REF_REAL_REG ( ref ) ) ; } </s>

Generate copies from defs used by the chain but not defined therein . Also populates defs_map which is used later by convert_insn .


<s> static void build_32_64 ( function_builder & b , const char * signature , const function_group_info & group , mode_suffix_index mode32 , mode_suffix_index mode64 , bool force_direct_overloads = false ) { for ( unsigned int pi = 0 ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) if ( group . types [ 0 ] [ 0 ] == NUM_TYPE_SUFFIXES ) { gcc_assert ( mode32 != MODE_none && mode64 != MODE_none ) ; build_one ( b , signature , group , mode32 , 0 , pi , force_direct_overloads ) ; build_one ( b , signature , group , mode64 , 0 , pi , force_direct_overloads ) ; } else for ( unsigned int ti = 0 ; group . types [ ti ] [ 0 ] != NUM_TYPE_SUFFIXES ; ++ ti ) { unsigned int bits = type_suffixes [ group . types [ ti ] [ 0 ] ] . element_bits ; gcc_assert ( bits == 32 || bits == 64 ) ; mode_suffix_index mode = bits == 32 ? mode32 : mode64 ; if ( mode != MODE_none ) build_one ( b , signature , group , mode , ti , pi , force_direct_overloads ) ; } } </s>

GROUP describes some sort of gather or scatter operation . There are two cases : - If the function has any type suffixes ( as for loads and stores ) , the first function type suffix specifies either a 32-bit or a 64-bit type , which in turn selects either MODE32 or MODE64 as the addressing mode . Add a function instance for every type and predicate combination in GROUP for which the associated addressing mode is not MODE_none . - If the function has no type suffixes ( as for prefetches ) , add one MODE32 form and one MODE64 form for each predication type . The other arguments are as for build_all .


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = Old . getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
void
Cpu0InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Cpu0
::
ADD
,
ZeroReg
=
Cpu0
::
ZERO
;
else
if
(
SrcReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MFLO
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
SW
)
Opc
=
Cpu0
::
ADD
,
ZeroReg
=
Cpu0
::
ZERO
;
}
else
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MTLO
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
SW
)
Opc
=
Cpu0
::
CMP
,
ZeroReg
=
Cpu0
::
ZERO
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static recpe_type get_recpe_type ( machine_mode mode ) { switch ( mode ) { case SFmode : return ( gen_aarch64_frecpesf ) ; case V2SFmode : return ( gen_aarch64_frecpev2sf ) ; case V4SFmode : return ( gen_aarch64_frecpev4sf ) ; case DFmode : return ( gen_aarch64_frecpedf ) ; case V2DFmode : return ( gen_aarch64_frecpev2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal initial estimate insn depending on machine mode .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( MipsTargetMachine & TM , const MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return llvm :: createMips16TargetLowering ( TM , STI ) ; return llvm :: createMipsSETargetLowering ( TM , STI ) ; } </s>


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isT ) : ARMArchVersion ( V4 ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( UseNEONFP ) , IsThumb ( isT ) , ThumbMode ( Thumb1 ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( UseMOVT ) , HasFP16 ( false ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == "generic" && ( FS . empty ( ) || FS == "generic" ) ) ARMArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + 2 && TT [ Idx + 1 ] == 't' ) ARMArchVersion = V4T ; else ARMArchVersion = V4 ; } } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( CPUString == "cortex-a8" ) { if ( UseNEONFP . getPosition ( ) == 0 ) UseNEONForSinglePrecisionFP = true ; } } </s>

This constructor initializes the data members to match that of the specified triple .


<s> unsigned internalKnownBits ( ) const { unsigned Bits = Unalign ? Unalign : KnownBits ; if ( Size & ( ( 1u << Bits ) - 1 ) ) Bits = countTrailingZeros ( Size ) ; return Bits ; } </s>

Compute the number of known offset bits internally to this block .


<s> int insvdi_rshift_rlwimi_p ( rtx sizeop , rtx startop , rtx shiftop ) { if ( INTVAL ( startop ) > 32 && INTVAL ( startop ) < 64 && INTVAL ( sizeop ) > 1 && INTVAL ( sizeop ) + INTVAL ( startop ) < 64 && INTVAL ( shiftop ) > 0 && INTVAL ( sizeop ) + INTVAL ( shiftop ) < 32 && ( 64 - ( INTVAL ( shiftop ) & 63 ) ) >= INTVAL ( sizeop ) ) return 1 ; return 0 ; } </s>

Return 1 if operands will generate a valid arguments to rlwimiinstruction for insert with right shift in 64-bit mode . The mask maynot start on the first bit or stop on the last bit because wrap-aroundeffects of instruction do not correspond to semantics of RTL insn .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TargetABI ( ARM_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new ARMFrameLowering ( * this ) : ( ARMFrameLowering * ) new Thumb1FrameLowering ( * this ) ) { } </s>

ARM ARM ARM ARM ARM ARM 4 ARM ARM ARM ARM ARM ARM ARM


"Not a machine_mode mode, legitimate address\n"

Return a nonzero value if XINSN is a legitimate address for a memory operand of the indicated MODE . STRICT is nonzero if this function is called during reload .


<s> bool AArch64TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool mem_operand_gpr ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( TARGET_POWERPC64 && ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

Return true if the MEM operand is a memory operand suitable for use with a ( full width , possibly multiple ) gpr load/store . On powerpc64 this means the offset must be divisible by 4 . Implements ' Y ' constraint . Accept direct , indexed , offset , lo_sum and tocref . Since this is a constraint function we know the operand has satisfied a suitable memory predicate . Offsetting a lo_sum should not be allowed , except where we know by alignment that a 32k boundary is not crossed . Note that by `` offsetting '' here we mean a further offset to access parts of the MEM . It 's fine to have a lo_sum where the inner address is offset from a sym , since the same sym+offset will appear in the high part of the address calculation .


<s> bool PPCInstrInfo :: analyzeLoop ( MachineLoop & L , MachineInstr * & IndVarInst , MachineInstr * & CmpInst ) const { MachineBasicBlock * LoopEnd = L . getBottomBlock ( ) ; MachineBasicBlock :: iterator I = LoopEnd -> getFirstTerminator ( ) ; if ( I != LoopEnd -> end ( ) && isBDNZ ( I -> getOpcode ( ) ) ) { IndVarInst = nullptr ; CmpInst = & * I ; return false ; } return true ; } </s>

Analyze the loop code , return true if it can not be understood .


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { IsFixed . resize ( Ins . size ( ) , true ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .