<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcodeBranch ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s> void AArch64TargetStreamer :: finish ( ) { if ( MarkBTIProperty ) emitNoteSection ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> void CSKYAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; if ( InConstantPool && MI -> getOpcode ( ) != CSKY :: CONSTPOOL_ENTRY ) { InConstantPool = false ; } if ( MI -> getOpcode ( ) == CSKY :: PseudoTLSLA32 ) return expandTLSLA ( MI ) ; if ( MI -> getOpcode ( ) == CSKY :: CONSTPOOL_ENTRY ) return emitCustomConstantPool ( MI ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

Targets should implement this to emit instructions .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> static void loongarch_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; bits = MIN ( BITS_PER_WORD , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) ) ; mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; loongarch_emit_move ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) loongarch_emit_move ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , ( enum memop_ret ) 0 ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


<s>
void
pru_function_profiler
(
FILE
*
file
,
int
labelno
ATTRIBUTE_UNUSED
)
{
fprintf
(
file
,
"\tmov\tr1, ra\n"
)
;
fprintf
(
file
,
"\tcall\t_mcount\n"
)
;
fprintf
(
file
,
"\tmov\tra, r1\n"
)
;
}
</s>

pru
"\tmov\tr1, ra\n"
"\tcall\t_mcount\n"
"\tmov\tra, r1\n"


"selected fp16 options are incompatible"

Reconfigure global status flags from the active_target.isa .


<s> void rs6000_expand_interleave ( rtx target , rtx op0 , rtx op1 , bool highp ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , high , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , 1 ) ; high = ( highp ? 0 : nelt / 2 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { perm . quick_push ( i + high ) ; perm . quick_push ( i + nelt + high ) ; } rs6000_do_expand_vec_perm ( target , op0 , op1 , vmode , perm ) ; } </s>


<s> const TargetRegisterClass * MipsSERegisterInfo :: intRegClass ( unsigned Size ) const { if ( Size == 4 ) return & Mips :: GPR32RegClass ; assert ( Size == 8 ) ; return & Mips :: GPR64RegClass ; } </s>


<s> void PPCPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) , false ) ; addPass ( createPPCBranchSelectionPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( size <= 7 * PROBE_INTERVAL ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = size & - PROBE_INTERVAL ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( ix86_gen_probe_stack_range ( sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static int compute_movmem_length ( rtx_insn * insn ) { rtx pat = PATTERN ( insn ) ; unsigned int align = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 7 ) , 0 ) ) ; unsigned long n_bytes = INTVAL ( XEXP ( XVECEXP ( pat , 0 , 6 ) , 0 ) ) ; unsigned int n_insns = 0 ; if ( align > ( TARGET_64BIT ? 8 : 4 ) ) align = ( TARGET_64BIT ? 8 : 4 ) ; n_insns = 6 ; if ( n_bytes % ( 2 * align ) != 0 ) { if ( ( n_bytes % ( 2 * align ) ) >= align ) n_insns += 2 ; if ( ( n_bytes % align ) != 0 ) n_insns += 2 ; } return n_insns * 4 ; } </s>

Count the number of insns necessary to handle this block move . Basic structure is the same as emit_block_move , except that we count insns rather than emit them .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
length
(
)
>
1
)
return
;
char
Letter
=
Constraint
[
0
]
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
SDLoc
dl
(
Op
)
;
int64_t
Value
=
CST
->
getSExtValue
(
)
;
EVT
TCVT
=
MVT
::
i64
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'J'
:
if
(
isShiftedUInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'L'
:
if
(
isShiftedInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'K'
:
if
(
isUInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'N'
:
if
(
Value
>
0
&&
isPowerOf2_64
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'P'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


<s> virtual bool ShouldShrinkFPConstant ( EVT VT ) const { return ! X86ScalarSSEf64 || VT == MVT :: f80 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> static bool pru_nongeneric_pointer_addrspace ( tree typ ) { while ( ARRAY_TYPE == TREE_CODE ( typ ) ) typ = TREE_TYPE ( typ ) ; if ( POINTER_TYPE_P ( typ ) ) { addr_space_t as ; tree target = TREE_TYPE ( typ ) ; if ( FUNCTION_TYPE == TREE_CODE ( target ) ) return pru_nongeneric_pointer_addrspace ( TREE_TYPE ( target ) ) ; while ( TREE_CODE ( target ) == ARRAY_TYPE ) target = TREE_TYPE ( target ) ; as = TYPE_ADDR_SPACE ( target ) ; if ( ! ADDR_SPACE_GENERIC_P ( as ) ) return true ; return pru_nongeneric_pointer_addrspace ( target ) ; } return false ; } </s>

Scan type TYP for pointer references to address space other than ADDR_SPACE_GENERIC . Return true if such reference is found . Much of this code was taken from the avr port .


<s> unsigned getNumFixupKinds ( ) const override { return ARM :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> virtual void initializePass ( ) override { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> SDValue X86TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget -> is64Bit ( ) ) return DAG . getNode ( X86ISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( ) ) ; return Table ; } </s>

Returns relocation base for the given PIC jumptable .


<s> static void mips_multi_set_operand ( unsigned int i , unsigned int op , rtx x ) { mips_multi_members [ i ] . operands [ op ] = x ; } </s>

Change the operand of an existing instruction in the current multi-insn sequence . I is the index of the instruction , OP is the index of the operand , and X is the new value .


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : 0 ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : 0 ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : 0 ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : 0 ) | ( ( TARGET_POWERPC64 ) ? RS6000_BTM_POWERPC64 : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 && TARGET_HARD_FLOAT && ! TARGET_IEEEQUAD ) ? RS6000_BTM_LDBL128 : 0 ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : 0 ) | ( ( TARGET_FLOAT128_HW ) ? RS6000_BTM_FLOAT128_HW : 0 ) | ( ( TARGET_MMA ) ? RS6000_BTM_MMA : 0 ) | ( ( TARGET_POWER10 ) ? RS6000_BTM_P10 : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s> void MMIXMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write ( OS , Bits , support :: big ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s>
TargetIRAnalysis
MipsTargetMachine
::
getTargetIRAnalysis
(
)
{
return
TargetIRAnalysis
(
[
this
]
(
Function
&
F
)
{
if
(
Subtarget
->
allowMixed16_32
(
)
)
{
DEBUG
(
errs
(
)
<<
"No Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
F
.
getParent
(
)
->
getDataLayout
(
)
)
;
}
DEBUG
(
errs
(
)
<<
"Target Transform Info Pass Added\n"
)
;
return
TargetTransformInfo
(
BasicTTIImpl
(
this
,
F
)
)
;
}
)
;
}
</s>

Get a TargetIRAnalysis appropriate for the target .

Mips
Mips
"No Target Transform Info Pass Added\n"
"Target Transform Info Pass Added\n"


<s>
void
X86InstrInfo
::
replaceBranchWithTailCall
(
MachineBasicBlock
&
MBB
,
SmallVectorImpl
<
MachineOperand
>
&
BranchCond
,
const
MachineInstr
&
TailCall
)
const
{
assert
(
canMakeTailCallConditional
(
BranchCond
,
TailCall
)
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
I
->
isBranch
(
)
)
assert
(
0
&&
"Can't find the branch to replace!"
)
;
X86
::
CondCode
CC
=
getCondFromBranchOpc
(
I
->
getOpcode
(
)
)
;
assert
(
BranchCond
.
size
(
)
==
1
)
;
if
(
CC
!=
BranchCond
[
0
]
.
getImm
(
)
)
continue
;
break
;
}
unsigned
Opc
=
TailCall
.
getOpcode
(
)
==
X86
::
TCRETURNdi
X86
::
TCRETURNdicc
:
X86
::
TCRETURNdi64cc
;
auto
MIB
=
BuildMI
(
MBB
,
I
,
MBB
.
findDebugLoc
(
I
)
,
get
(
Opc
)
)
;
MIB
->
addOperand
(
TailCall
.
getOperand
(
0
)
)
;
MIB
.
addImm
(
0
)
;
MIB
->
addOperand
(
BranchCond
[
0
]
)
;
MIB
.
copyImplicitOps
(
TailCall
)
;
I
->
eraseFromParent
(
)
;
}
</s>

Replace the conditional branch in MBB with a conditional tail call .


"%qs requires an integer constant expression"

An attribute callback for the `` arm_sve_vector_bits '' attribute .


<s> void AArch64PassConfig :: addPreEmitPass ( ) { if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Aggressive && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; if ( EnableA53Fix835769 ) addPass ( createAArch64A53Fix835769 ( ) ) ; if ( EnableBranchTargets ) addPass ( createAArch64BranchTargetsPass ( ) ) ; if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( createAArch64CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const char * output_mod_insn ( int unsignedp , rtx insn ) { if ( unsignedp ) { import_milli ( remU ) ; return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( SImode , "$$remU" ) ) ; } else { import_milli ( remI ) ; return output_millicode_call ( insn , gen_rtx_SYMBOL_REF ( SImode , "$$remI" ) ) ; } } </s>


<s> bool PPCInstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { int AltOpc = PPC :: getAltVSXFMAOpcode ( MI -> getOpcode ( ) ) ; if ( AltOpc == - 1 ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s>
void
AArch64FrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64Subtarget
&
Subtarget
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
;
const
AArch64RegisterInfo
*
RegInfo
=
Subtarget
.
getRegisterInfo
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
DebugLoc
DL
;
bool
IsTailCallReturn
=
false
;
if
(
MBB
.
end
(
)
!=
MBBI
)
{
DL
=
MBBI
->
getDebugLoc
(
)
;
unsigned
RetOpcode
=
MBBI
->
getOpcode
(
)
;
IsTailCallReturn
=
RetOpcode
==
AArch64
::
TCRETURNdi
||
RetOpcode
==
AArch64
::
TCRETURNri
;
}
int
NumBytes
=
MFI
->
getStackSize
(
)
;
const
AArch64FunctionInfo
*
AFI
=
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
if
(
MF
.
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
;
uint64_t
ArgumentPopSize
=
0
;
if
(
IsTailCallReturn
)
{
MachineOperand
&
StackAdjust
=
MBBI
->
getOperand
(
1
)
;
ArgumentPopSize
=
StackAdjust
.
getImm
(
)
;
}
else
{
ArgumentPopSize
=
AFI
->
getArgumentStackToRestore
(
)
;
}
NumBytes
+=
ArgumentPopSize
;
unsigned
NumRestores
=
0
;
MachineBasicBlock
::
iterator
LastPopI
=
MBB
.
getFirstTerminator
(
)
;
const
MCPhysReg
*
CSRegs
=
RegInfo
->
getCalleeSavedRegs
(
&
MF
)
;
MachineBasicBlock
::
iterator
Begin
=
MBB
.
begin
(
)
;
while
(
LastPopI
!=
Begin
)
{
LastPopI
;
unsigned
Restores
=
getNumCSRestores
(
*
LastPopI
,
CSRegs
)
;
NumRestores
+=
Restores
;
if
(
Restores
==
0
)
{
++
LastPopI
;
break
;
}
}
NumBytes
-=
NumRestores
*
8
;
assert
(
NumBytes
>=
0
&&
"Negative stack allocation size!?"
)
;
if
(
!
hasFP
(
MF
)
)
{
if
(
!
canUseRedZone
(
MF
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
NumBytes
,
TII
)
;
return
;
}
if
(
NumBytes
||
MFI
->
hasVarSizedObjects
(
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
FP
,
(
NumRestores
2
)
*
8
,
TII
,
MachineInstr
::
NoFlags
)
;
}
</s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ) { MachineBasicBlock & B = * I ++ ; Changed |= processBlock ( B ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


"%s instructions aren%'t allowed in a function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> bool X86AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { MCAsmParser & Parser = getParser ( ) ; if ( Parser . parsePrimaryExpr ( Res , EndLoc ) ) { SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; bool TryRegParse = getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) ) ; if ( ! TryRegParse || ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Parser . clearPendingErrors ( ) ; Res = X86MCExpr :: create ( RegNo , Parser . getContext ( ) ) ; return false ; } return false ; } </s>


<s> void X86LinuxNaClTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> static unsigned int rs6000_xcoff_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int align ; unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl && DECL_P ( decl ) && VAR_P ( decl ) && bss_initializer_p ( decl ) ) flags |= SECTION_BSS ; if ( ! decl || ! DECL_P ( decl ) ) align = MIN_UNITS_PER_WORD ; else if ( ( flags & SECTION_CODE ) != 0 ) align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , 32 ) ; else align = MAX ( ( DECL_ALIGN ( decl ) / BITS_PER_UNIT ) , int_size_in_bytes ( TREE_TYPE ( decl ) ) > MIN_UNITS_PER_WORD ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD ) ; return flags | ( exact_log2 ( align ) & SECTION_ENTSIZE ) ; } </s>

Section attributes . AIX is always PIC .


<s> static int arm_compute_static_chain_stack_bytes ( void ) { if ( cfun -> machine -> static_chain_stack_bytes != - 1 ) return cfun -> machine -> static_chain_stack_bytes ; if ( IS_NESTED ( arm_current_func_type ( ) ) && ( ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) || ( ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK || flag_stack_clash_protection ) && ! df_regs_ever_live_p ( LR_REGNUM ) ) ) && arm_r3_live_at_start_p ( ) && crtl -> args . pretend_args_size == 0 ) return 4 ; return 0 ; } </s>

Compute the number of bytes used to store the static chain register on the stack , above the stack frame . We need to know this accurately to get the alignment of the rest of the stack frame correct .


<s> enum reg_class aarch64_regno_regclass ( unsigned regno ) { if ( STUB_REGNUM_P ( regno ) ) return STUB_REGS ; if ( GP_REGNUM_P ( regno ) ) return GENERAL_REGS ; if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return ( FP_LO8_REGNUM_P ( regno ) ? FP_LO8_REGS : FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ) ; if ( PR_REGNUM_P ( regno ) ) return PR_LO_REGNUM_P ( regno ) ? PR_LO_REGS : PR_HI_REGS ; if ( regno == FFR_REGNUM || regno == FFRT_REGNUM ) return FFR_REGS ; return NO_REGS ; } </s>


<s> static void print_csky_value ( FILE * f , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; return ; case CONST_DOUBLE : fprintf ( f , "<0x%lx,0x%lx>" , ( long ) XWINT ( x , 2 ) , ( long ) XWINT ( x , 3 ) ) ; return ; case CONST_VECTOR : { int i ; fprintf ( f , "<" ) ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( CONST_VECTOR_ELT ( x , i ) ) ) ; if ( i < ( CONST_VECTOR_NUNITS ( x ) - 1 ) ) fputc ( ',' , f ) ; } fprintf ( f , ">" ) ; } return ; case CONST_STRING : fprintf ( f , "\"%s\"" , XSTR ( x , 0 ) ) ; return ; case SYMBOL_REF : fprintf ( f , "`%s'" , XSTR ( x , 0 ) ) ; return ; case LABEL_REF : fprintf ( f , "L%d" , INSN_UID ( XEXP ( x , 0 ) ) ) ; return ; case CONST : print_csky_value ( f , XEXP ( x , 0 ) ) ; return ; case PLUS : print_csky_value ( f , XEXP ( x , 0 ) ) ; fprintf ( f , "+" ) ; print_csky_value ( f , XEXP ( x , 1 ) ) ; return ; case PC : fprintf ( f , "pc" ) ; return ; default : fprintf ( f , "????" ) ; return ; } } </s>

Print a symbolic form of the constant X to the dump file F. This is used for dump output for -mconstpool in the target-dependent reorg pass .


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> rtx extract_branch_condition_rtx ( rtx_insn * insn ) { gcc_assert ( CALL_P ( insn ) || JUMP_P ( insn ) ) ; rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { rtx if_then_else_rtx = SET_SRC ( body ) ; if ( GET_CODE ( if_then_else_rtx ) == IF_THEN_ELSE ) return XEXP ( if_then_else_rtx , 0 ) ; return NULL_RTX ; } if ( GET_CODE ( body ) == COND_EXEC ) return XEXP ( body , 0 ) ; return NULL_RTX ; } </s>

Extract the rtx representing the branch condition to help recognize data hazards .


"Stack realignment in presence of dynamic allocas is not supported with"

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static void ia64_init_sched_context ( void * _sc , bool clean_p ) { ia64_sched_context_t sc = ( ia64_sched_context_t ) _sc ; sc -> prev_cycle_state = xmalloc ( dfa_state_size ) ; if ( clean_p ) { state_reset ( sc -> prev_cycle_state ) ; sc -> last_scheduled_insn = NULL ; memset ( sc -> rws_sum , 0 , sizeof ( rws_sum ) ) ; memset ( sc -> rws_insn , 0 , sizeof ( rws_insn ) ) ; sc -> first_instruction = 1 ; sc -> pending_data_specs = 0 ; sc -> current_cycle = 0 ; memset ( sc -> mem_ops_in_group , 0 , sizeof ( mem_ops_in_group ) ) ; } else { memcpy ( sc -> prev_cycle_state , prev_cycle_state , dfa_state_size ) ; sc -> last_scheduled_insn = last_scheduled_insn ; memcpy ( sc -> rws_sum , rws_sum , sizeof ( rws_sum ) ) ; memcpy ( sc -> rws_insn , rws_insn , sizeof ( rws_insn ) ) ; sc -> first_instruction = first_instruction ; sc -> pending_data_specs = pending_data_specs ; sc -> current_cycle = current_cycle ; memcpy ( sc -> mem_ops_in_group , mem_ops_in_group , sizeof ( mem_ops_in_group ) ) ; } } </s>

Initializes the _SC context with clean data , if CLEAN_P , and from the global context otherwise .


<s> inline hashval_t registered_function_hasher :: hash ( value_type value ) { return value -> instance . hash ( ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> CCAssignFn * ARMTargetLowering :: CCAssignFnForCall ( CallingConv :: ID CC , bool isVarArg ) const { return CCAssignFnForNode ( CC , false , isVarArg ) ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool canMergeStoresTo ( unsigned AddressSpace , EVT MemVT , const MachineFunction & MF ) const override { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> const char * getPassName ( ) const override { return STPSUPPRESS_PASS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static const char * getName ( ) { return DEBUG_TYPE ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> std :: pair < unsigned , unsigned > MipsInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return SystemZ :: R7D ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>


<s> static void mips_pop_asm_switch_1 ( struct mips_asm_switch * asm_switch , const char * prefix , const char * suffix ) { gcc_assert ( asm_switch -> nesting_level ) ; asm_switch -> nesting_level -- ; if ( asm_switch -> nesting_level == 0 ) fprintf ( asm_out_file , "%s.set\t%s%s" , prefix , asm_switch -> name , suffix ) ; } </s>


<s> bool ARMAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & 1 ) OW -> Write8 ( 0 ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> Write8 ( 0 ) ; break ; case 2 : OW -> Write16 ( 0 ) ; break ; case 3 : OW -> Write16 ( 0 ) ; OW -> Write8 ( 0xa0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
bool
TOYPreRegAlloc
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
DEBUG
(
dbgs
(
)
<<
"********* TOY PreRegAlloc *********\n"
)
;
bool
Changed
=
false
;
Changed
|=
peepholeOpt
(
MF
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

TOY
TOY
"********* TOY PreRegAlloc *********\n"


<s>
static
void
nds32_asm_function_epilogue
(
FILE
*
file
)
{
fprintf
(
file
,
"\t! END EPILOGUE\n"
)
;
}
</s>

The content produced from this function will be placed after epilogue body .


<s> bool mayNeedRelaxation ( const MCInst & ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static int attr_strcmp ( const void * v1 , const void * v2 ) { const char * c1 = * ( char * const * ) v1 ; const char * c2 = * ( char * const * ) v2 ; return strcmp ( c1 , c2 ) ; } </s>

Comparator function to be used in qsort routine to sort attribute specification strings to `` target '' .


<s> bool rx_is_restricted_memory_address ( rtx mem , machine_mode mode ) { if ( ! rx_is_legitimate_address ( mode , mem , reload_in_progress || reload_completed ) ) return false ; switch ( GET_CODE ( mem ) ) { case REG : return true ; case PRE_DEC : case POST_INC : return false ; case PLUS : { rtx base , index ; base = XEXP ( mem , 0 ) ; index = XEXP ( mem , 1 ) ; if ( ! RX_REG_P ( base ) || ! CONST_INT_P ( index ) ) return false ; return IN_RANGE ( INTVAL ( index ) , 0 , ( 0x10000 * GET_MODE_SIZE ( mode ) ) - 1 ) ; } case SYMBOL_REF : return true ; default : gcc_unreachable ( ) ; } } </s>

Returns TRUE for simple memory addreses , ie ones that do not involve register indirect addressing or pre/post increment/decrement .


<s> int ix86_return_in_memory ( tree type ) { int needed_intregs , needed_sseregs , size ; enum machine_mode mode = type_natural_mode ( type ) ; if ( TARGET_64BIT ) return ! examine_argument ( mode , type , 1 , & needed_intregs , & needed_sseregs ) ; if ( mode == BLKmode ) return 1 ; size = int_size_in_bytes ( type ) ; if ( MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P ( type ) && size <= 8 ) return 0 ; if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { if ( size < 8 ) return 0 ; if ( size == 8 ) return ( TARGET_MMX ? 0 : 1 ) ; if ( size == 16 ) return ( TARGET_SSE ? 0 : 1 ) ; } if ( mode == XFmode ) return 0 ; if ( size > 12 ) return 1 ; return 0 ; } </s>

Return false iff type is returned in memory .


<s> AArch64ELFStreamer & AArch64TargetELFStreamer :: getStreamer ( ) { return static_cast < AArch64ELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options . StackAlignmentOverride , is64Bit ) , FrameLowering ( * this , Subtarget ) , ELFWriterInfo ( is64Bit , true ) { if ( getRelocationModel ( ) == Reloc :: Static ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else { assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ; Subtarget . setPICStyle ( PICStyles :: StubDynamicNoPIC ) ; } } else if ( Subtarget . isTargetELF ( ) ) { Subtarget . setPICStyle ( PICStyles :: GOT ) ; } if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Hard ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; X86OutgoingValueAssigner Assigner ( CC_X86 ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool ia64_const_double_ok_for_letter_p ( rtx value , char c ) { switch ( c ) { case 'G' : return CONST_DOUBLE_OK_FOR_G ( value ) ; default : return false ; } } </s>


<s> const TargetRegisterClass * X86RegisterInfo :: getCrossCopyRegClass ( const TargetRegisterClass * RC ) const { if ( RC == & X86 :: CCRRegClass ) { if ( Is64Bit ) return & X86 :: GR64RegClass ; else return & X86 :: GR32RegClass ; } return NULL ; } </s>

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDepsFix ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) , nullptr ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv :: X86_FastCall ) ; SecurityCheckCookie -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static void ia64_output_function_end_prologue ( FILE * file ) { if ( ! flag_unwind_tables && ( ! flag_exceptions || USING_SJLJ_EXCEPTIONS ) ) return ; fputs ( "\t.body\n" , file ) ; } </s>

Emit the .body directive at the scheduled end of the prologue .


<s> void aarch64_register_pragmas ( void ) { targetm . target_option . pragma_parse = aarch64_pragma_target_parse ; } </s>


<s> static void loongarch_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; loongarch_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > 0 ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ; } </s>


<s> int neon_immediate_valid_for_logic ( rtx op , machine_mode mode , int inverse , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = simd_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ; if ( retval < 0 || retval > 5 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use in a VORR or VBIC instruction . If the immediate is valid , write a constant suitable for using as an operand to VORR/VBIC/VAND/VORN to * MODCONST and the corresponding element width to * ELEMENTWIDTH . See neon_valid_immediate for description of INVERSE .


<s> unsigned AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_DLLIMPORT ; if ( getTargetTriple ( ) . isOSWindows ( ) ) return AArch64II :: MO_GOT | AArch64II :: MO_COFFSTUB ; return AArch64II :: MO_GOT ; } if ( ( useSmallAddressing ( ) || TM . getCodeModel ( ) == CodeModel :: Tiny ) && GV -> hasExternalWeakLinkage ( ) ) return AArch64II :: MO_GOT ; if ( AllowTaggedGlobals && ! isa < FunctionType > ( GV -> getValueType ( ) ) ) return AArch64II :: MO_NC | AArch64II :: MO_TAGGED ; return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> tree gimple_folder :: load_store_cookie ( tree type ) { return build_int_cst ( build_pointer_type ( type ) , TYPE_ALIGN ( type ) ) ; } </s>

Return the alignment and TBAA argument to an internal load or store function like IFN_MASK_LOAD or IFN_MASK_STORE , given that it accesses memory elements of type TYPE .


<s> int get_dest_uid ( rtx_insn * label , int max_uid ) { rtx_insn * dest = next_real_insn ( label ) ; if ( ! dest ) return 0 ; int dest_uid = INSN_UID ( dest ) ; while ( dest_uid >= max_uid ) { dest = NEXT_INSN ( dest ) ; dest_uid = INSN_UID ( dest ) ; } if ( JUMP_P ( dest ) && GET_CODE ( PATTERN ( dest ) ) == RETURN ) return 0 ; return dest_uid ; } </s>

Return the UID of the insn that follows the specified label .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; MVT SVT = VT . getSimpleVT ( ) ; if ( VT . getSizeInBits ( ) == 64 ) return false ; if ( ( SVT . is128BitVector ( ) && Subtarget -> hasSSSE3 ( ) ) || ( SVT . is256BitVector ( ) && Subtarget -> hasInt256 ( ) ) ) { bool isLegal = true ; for ( unsigned I = 0 , E = M . size ( ) ; I != E ; ++ I ) { if ( M [ I ] >= ( int ) SVT . getVectorNumElements ( ) || ShuffleCrosses128bitLane ( SVT , I , M [ I ] ) ) { isLegal = false ; break ; } } if ( isLegal ) return true ; } return ( SVT . getVectorNumElements ( ) == 2 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isMOVLMask ( M , SVT ) || isSHUFPMask ( M , SVT ) || isPSHUFDMask ( M , SVT ) || isPSHUFHWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPSHUFLWMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isPALIGNRMask ( M , SVT , Subtarget ) || isUNPCKLMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKHMask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKL_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isUNPCKH_v_undef_Mask ( M , SVT , Subtarget -> hasInt256 ( ) ) || isBlendMask ( M , SVT , Subtarget -> hasSSE41 ( ) , Subtarget -> hasInt256 ( ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> const MCExpr * VEAsmParser :: parseIdentifier ( StringRef Identifier ) { StringRef Modifier ; size_t at = Identifier . rfind ( '@' ) ; if ( at != 0 || at != StringRef :: npos ) { std :: pair < StringRef , StringRef > Pair = Identifier . rsplit ( "@" ) ; if ( ! Pair . first . empty ( ) && ! Pair . second . empty ( ) ) { Identifier = Pair . first ; Modifier = Pair . second ; } } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; VEMCExpr :: VariantKind VK = VEMCExpr :: parseVariantKind ( Modifier ) ; if ( VK == VEMCExpr :: VK_VE_None ) { VEMCExpr :: VariantKind Kind = VEMCExpr :: VK_VE_REFLONG ; return VEMCExpr :: create ( Kind , Res , getContext ( ) ) ; } return VEMCExpr :: create ( VK , Res , getContext ( ) ) ; } </s>

Parse an identifier or string ( as a quoted identifier ) and set Res to the identifier contents .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineTraceMetrics > ( ) ; AU . addPreserved < MachineTraceMetrics > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isLikeA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool rs6000_builtin_type_compatible ( tree parmtype , tree argtype ) { if ( parmtype == error_mark_node ) return false ; if ( INTEGRAL_TYPE_P ( parmtype ) && INTEGRAL_TYPE_P ( argtype ) ) return true ; if ( TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 && is_float128_p ( parmtype ) && is_float128_p ( argtype ) ) return true ; if ( POINTER_TYPE_P ( parmtype ) && POINTER_TYPE_P ( argtype ) ) { parmtype = TREE_TYPE ( parmtype ) ; argtype = TREE_TYPE ( argtype ) ; if ( TYPE_READONLY ( argtype ) ) parmtype = build_qualified_type ( parmtype , TYPE_QUAL_CONST ) ; } return lang_hooks . types_compatible_p ( parmtype , argtype ) ; } </s>

Return true iff ARGTYPE can be compatibly passed as PARMTYPE .


<s> static rtx get_mem_base_reg ( rtx mem ) { const char * fmt ; while ( ! MEM_P ( mem ) ) { if ( GET_RTX_CLASS ( GET_CODE ( mem ) ) != RTX_UNARY || GET_CODE ( mem ) == BSWAP ) return NULL_RTX ; fmt = GET_RTX_FORMAT ( GET_CODE ( mem ) ) ; if ( fmt [ 0 ] != 'e' ) return NULL_RTX ; mem = XEXP ( mem , 0 ) ; if ( mem == NULL_RTX ) return NULL_RTX ; } if ( ! MEM_SIZE_KNOWN_P ( mem ) ) return NULL_RTX ; rtx addr_rtx = ( XEXP ( mem , 0 ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , 1 ) ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , 1 ) ) ) addr_rtx = XEXP ( addr_rtx , 0 ) ; if ( ! REG_P ( addr_rtx ) ) return NULL_RTX ; return addr_rtx ; } </s>

Return the register used as the base register of MEM , if the instruction has a pc-relative form . We look for BSWAP to rule out LFIWAX/LFIWZX/STFIWX , and ROTATE/VEC_SELECT are RTX_EXTRA not RTX_UNARY which rules out lxvd2x . This excludes instructions that do not have a pc-relative form .


<s>
bool
MipsConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
4
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
DEBUG
(
dbgs
(
)
<<
"Branch of destination BB#"
<<
DestBB
->
getNumber
(
)
<<
" from BB#"
<<
MI
->
getParent
(
)
->
getNumber
(
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

Mips
Mips
4
"Branch of destination BB#"
" from BB#"
" max delta="
" from "
" to "
" offset "
"\t"


<s> static rtx gen_frame_mem_offset ( machine_mode mode , rtx reg , int offset ) { rtx int_rtx , offset_rtx ; int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) { offset_rtx = gen_rtx_REG ( Pmode , FIXED_SCRATCH ) ; emit_move_insn ( offset_rtx , int_rtx ) ; } else offset_rtx = int_rtx ; return gen_frame_mem ( mode , gen_rtx_PLUS ( Pmode , reg , offset_rtx ) ) ; } </s>

Emit an offset memory reference suitable for a frame store , while converting to a valid addressing mode .


<s> void rs6000_emit_sISEL ( machine_mode mode ATTRIBUTE_UNUSED , rtx operands [ ] ) { rs6000_emit_int_cmove ( operands [ 0 ] , operands [ 1 ] , const1_rtx , const0_rtx ) ; } </s>


<s> rtx mmix_eh_return_stackadj_rtx ( void ) { return gen_rtx_REG ( Pmode , MMIX_EH_RETURN_STACKADJ_REGNUM ) ; } </s>


<s> bool CheckReturn ( const SmallVectorImpl < ISD :: OutputArg > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasF128 . clear ( ) ; return Return ; } </s>

CheckReturn - Analyze the return values of a function , returning true if the return can be performed without sret-demotion , and false otherwise .


Initialize fpsr fpcr getters and setters .


<s> aarch64_feature_flags get_flags_off ( aarch64_feature_flags mask ) { return ( 0 | ( feature_deps :: IDENT ( ) . enable & mask ? AARCH64_FL_ ## IDENT : 0 ) ) ; } </s>

Return the set of all features that would need to be disabled if the features in MASK are disabled . Note that the size of the expression varies linearly with the number of features , which means that invoking this function once per feature is quadratic in the number of features . However , collecting the same information at compiler start-up is likely to be quadratic too , so we 're better off paying the cost once per compiler build rather than once per compiler run .


<s> static void aarch64_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_aarch64_override_tune_string = opts -> x_aarch64_override_tune_string ; ptr -> x_aarch64_branch_protection_string = opts -> x_aarch64_branch_protection_string ; } </s>


<s> int symbol_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( SYMBOL_REF_P ( x ) ) return 1 ; if ( GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_TLS ) return 0 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && symbol_mentioned_p ( XEXP ( x , i ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if X references a SYMBOL_REF .


<s>
SDValue
VETargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
getReturnCC
(
CallConv
)
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
assert
(
!
VA
.
needsCustom
(
)
&&
"Unexpected custom lowering"
)
;
SDValue
OutVal
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
ZExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
AExt
:
OutVal
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
DL
,
VA
.
getLocVT
(
)
,
OutVal
)
;
break
;
case
CCValAssign
::
BCvt
:
{
assert
(
VA
.
getLocVT
(
)
==
MVT
::
i64
)
;
assert
(
VA
.
getValVT
(
)
==
MVT
::
f32
)
;
SDValue
Undef
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
IMPLICIT_DEF
,
DL
,
MVT
::
i64
)
,
0
)
;
SDValue
Sub_f32
=
DAG
.
getTargetConstant
(
VE
::
sub_f32
,
DL
,
MVT
::
i32
)
;
OutVal
=
SDValue
(
DAG
.
getMachineNode
(
TargetOpcode
::
INSERT_SUBREG
,
DL
,
MVT
::
i64
,
Undef
,
OutVal
,
Sub_f32
)
,
0
)
;
break
;
}
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVal
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
VEISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool SparcDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s>
void
X86AsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
bool
Is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Mode16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
Is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static bool aarch64_rtx_arith_op_extract_p ( rtx x , scalar_int_mode mode ) { if ( GET_CODE ( x ) == SIGN_EXTRACT || GET_CODE ( x ) == ZERO_EXTRACT ) { rtx op0 = XEXP ( x , 0 ) ; rtx op1 = XEXP ( x , 1 ) ; rtx op2 = XEXP ( x , 2 ) ; if ( GET_CODE ( op0 ) == MULT && CONST_INT_P ( op1 ) && op2 == const0_rtx && CONST_INT_P ( XEXP ( op0 , 1 ) ) && aarch64_is_extend_from_extract ( mode , XEXP ( op0 , 1 ) , op1 ) ) { return true ; } } else if ( GET_CODE ( x ) == SIGN_EXTEND || GET_CODE ( x ) == ZERO_EXTEND ) return REG_P ( XEXP ( x , 0 ) ) ; return false ; } </s>

Return true if X is a zero or sign extract usable in an ADD or SUB ( extended register ) instruction .


<s> static machine_mode mips_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_PAIRED_SINGLE_FLOAT && mode == SFmode ) return V2SFmode ; if ( ! ISA_HAS_MSA ) return word_mode ; switch ( mode ) { case QImode : return V16QImode ; case HImode : return V8HImode ; case SImode : return V4SImode ; case DImode : return V2DImode ; case SFmode : return V4SFmode ; case DFmode : return V2DFmode ; default : break ; } return word_mode ; } </s>


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicCmpXchgIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicCmpXchgInst
*
CI
,
Value
*
AlignedAddr
,
Value
*
CmpVal
,
Value
*
NewVal
,
Value
*
Mask
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
CmpVal
->
getType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
IntCmpXchg
=
Intrinsic
::
getDeclaration
(
M
,
Intrinsic
::
ppc_cmpxchg_i128
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
CmpLo
=
Builder
.
CreateTrunc
(
CmpVal
,
Int64Ty
,
"cmp_lo"
)
;
Value
*
CmpHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
CmpVal
,
64
)
,
Int64Ty
,
"cmp_hi"
)
;
Value
*
NewLo
=
Builder
.
CreateTrunc
(
NewVal
,
Int64Ty
,
"new_lo"
)
;
Value
*
NewHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
NewVal
,
64
)
,
Int64Ty
,
"new_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
emitLeadingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
IntCmpXchg
,
{
Addr
,
CmpLo
,
CmpHi
,
NewLo
,
NewHi
}
)
;
emitTrailingFence
(
Builder
,
CI
,
Ord
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> unsigned MipsTargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { RegisterVT = getRegisterTypeForCallingConv ( Context , CC , VT ) ; IntermediateVT = RegisterVT ; NumIntermediates = VT . getFixedSizeInBits ( ) < RegisterVT . getFixedSizeInBits ( ) ? VT . getVectorNumElements ( ) : divideCeil ( VT . getSizeInBits ( ) , RegisterVT . getSizeInBits ( ) ) ; return NumIntermediates ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> bool isThumb ( ) const { return isThumbMode ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> void SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) emitSPAdjustment ( MF , MBB , I , Size , SP :: ADDrr , SP :: ADDri ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN SP SP::ADDrr SP::ADDri


<s> bool AArch64SIMDInstrOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; const TargetSubtargetInfo & ST = MF . getSubtarget ( ) ; const AArch64InstrInfo * AAII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; if ( ! AAII ) return false ; SchedModel . init ( ST . getSchedModel ( ) , & ST , AAII ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) return false ; bool Changed = false ; for ( auto OptimizationKind : { VectorElem , Interleave } ) { if ( ! shouldExitEarly ( & MF , OptimizationKind ) ) { SmallVector < MachineInstr * , 8 > RemoveMIs ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator MII = MBB . begin ( ) , MIE = MBB . end ( ) ; MII != MIE ; ) { MachineInstr & MI = * MII ; bool InstRewrite ; if ( OptimizationKind == VectorElem ) InstRewrite = optimizeVectElement ( MI ) ; else InstRewrite = optimizeLdStInterleave ( MI ) ; if ( InstRewrite ) { RemoveMIs . push_back ( & MI ) ; Changed = true ; } ++ MII ; } } for ( MachineInstr * MI : RemoveMIs ) MI -> eraseFromParent ( ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCInstrInfo :: findCommutedOpIndices ( const MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { int AltOpc = PPC :: getAltVSXFMAOpcode ( MI . getOpcode ( ) ) ; if ( AltOpc == - 1 ) return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 2 , 3 ) ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { const MachineMemOperand * Dummy ; return MI -> getDesc ( ) . mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ; } </s>

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> static void expand_set_or_cpymem_via_rep ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx orig_value , rtx count , machine_mode mode , bool issetmem ) { rtx destexp ; rtx srcexp ; rtx countreg ; HOST_WIDE_INT rounded_count ; if ( mode == QImode && CONST_INT_P ( count ) && ! ( INTVAL ( count ) & 3 ) && ! TARGET_PREFER_KNOWN_REP_MOVSB_STOSB && ( ! issetmem || orig_value == const0_rtx ) ) mode = SImode ; if ( destptr != XEXP ( destmem , 0 ) || GET_MODE ( destmem ) != BLKmode ) destmem = adjust_automodify_address_nv ( destmem , BLKmode , destptr , 0 ) ; countreg = ix86_zero_extend_to_Pmode ( scale_counter ( count , GET_MODE_SIZE ( mode ) ) ) ; if ( mode != QImode ) { destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , 0 ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , 0 ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode , srcexp , srcptr ) ; } else srcexp = gen_rtx_PLUS ( Pmode , srcptr , countreg ) ; if ( CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; srcmem = shallow_copy_rtx ( srcmem ) ; set_mem_size ( srcmem , rounded_count ) ; } else { if ( MEM_SIZE_KNOWN_P ( srcmem ) ) clear_mem_size ( srcmem ) ; } emit_insn ( gen_rep_mov ( destptr , destmem , srcptr , srcmem , countreg , destexp , srcexp ) ) ; } } </s>

Output `` rep ; mov '' or `` rep ; stos '' instruction depending on ISSETMEM argument . When ISSETMEM is true , arguments SRCMEM and SRCPTR are ignored . When ISSETMEM is false , arguments VALUE and ORIG_VALUE are ignored . For setmem case , VALUE is a promoted to a wider size ORIG_VALUE . ORIG_VALUE is the original value passed to memset to fill the memory with . Other arguments have same meaning as for previous function .


<s> bool mips_linked_madd_p ( rtx prev , rtx insn ) { rtx x ; x = single_set ( insn ) ; if ( x == 0 ) return false ; x = SET_SRC ( x ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == MULT && reg_set_p ( XEXP ( x , 1 ) , prev ) ) return true ; if ( GET_CODE ( x ) == MINUS && GET_CODE ( XEXP ( x , 1 ) ) == MULT && reg_set_p ( XEXP ( x , 0 ) , prev ) ) return true ; return false ; } </s>

Return true if INSN is a multiply-add or multiply-subtract instruction and PREV assigns to the accumulator operand .


<s>
bool
X86FrameLowering
::
canUseAsPrologue
(
const
MachineBasicBlock
&
MBB
)
const
{
assert
(
MBB
.
getParent
(
)
&&
"Block is not attached to a function!"
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
if
(
!
MBB
.
isLiveIn
(
X86
::
EFLAGS
)
)
return
true
;
const
X86MachineFunctionInfo
*
X86FI
=
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
;
return
!
TRI
->
needsStackRealignment
(
MF
)
&&
!
X86FI
->
hasSwiftAsyncContext
(
)
;
}
</s>

Check whether or not the given MBB can be used as a prologue for the target .


<s> virtual void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> void ARMBaseInstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , unsigned SubIdx , const MachineInstr & Orig , const TargetRegisterInfo & TRI ) const { unsigned Opcode = Orig . getOpcode ( ) ; switch ( Opcode ) { default : { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MI -> substituteRegister ( Orig . getOperand ( 0 ) . getReg ( ) , DestReg , SubIdx , TRI ) ; MBB . insert ( I , MI ) ; break ; } case ARM :: tLDRpci_pic : case ARM :: t2LDRpci_pic : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( 1 ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) . cloneMemRefs ( Orig ) ; break ; } } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> rtx function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { if ( TARGET_64BIT ) { rtx loc [ 2 ] ; int i , offset = 0 ; int ub = int_size_in_bytes ( valtype ) <= UNITS_PER_WORD ? 1 : 2 ; for ( i = 0 ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 + i ) , GEN_INT ( offset ) ) ; offset += 8 ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( int_size_in_bytes ( valtype ) > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( 1 , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE ( valtype ) ; if ( TREE_CODE ( valtype ) == REAL_TYPE && ! AGGREGATE_TYPE_P ( valtype ) && TYPE_MODE ( valtype ) != TFmode && ! TARGET_SOFT_FLOAT ) return gen_rtx_REG ( valmode , 32 ) ; return gen_rtx_REG ( valmode , 28 ) ; } </s>

Handle FUNCTION_VALUE , FUNCTION_OUTGOING_VALUE , and LIBCALL_VALUE macros . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> static void aarch64_output_mi_thunk ( FILE * file , tree thunk ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = R0_REGNUM ; rtx this_rtx , temp0 , temp1 , addr , funexp ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( vcall_offset == 0 ) aarch64_add_constant ( Pmode , this_regno , IP1_REGNUM , delta ) ; else { gcc_assert ( ( vcall_offset & ( POINTER_BYTES - 1 ) ) == 0 ) ; this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; temp0 = gen_rtx_REG ( Pmode , IP0_REGNUM ) ; temp1 = gen_rtx_REG ( Pmode , IP1_REGNUM ) ; addr = this_rtx ; if ( delta != 0 ) { if ( delta >= - 256 && delta < 256 ) addr = gen_rtx_PRE_MODIFY ( Pmode , this_rtx , plus_constant ( Pmode , this_rtx , delta ) ) ; else aarch64_add_constant ( Pmode , this_regno , IP1_REGNUM , delta ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp0 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp0 , gen_rtx_ZERO_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; if ( vcall_offset >= - 256 && vcall_offset < 4096 * POINTER_BYTES ) addr = plus_constant ( Pmode , temp0 , vcall_offset ) ; else { aarch64_internal_mov_immediate ( temp1 , GEN_INT ( vcall_offset ) , true , Pmode ) ; addr = gen_rtx_PLUS ( Pmode , temp0 , temp1 ) ; } if ( Pmode == ptr_mode ) aarch64_emit_move ( temp1 , gen_rtx_MEM ( ptr_mode , addr ) ) ; else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


"  Skipping pass: no machine model present.\n"


<s> int direct_return ( ) { return ( reload_completed && xstormy16_compute_stack_layout ( ) . frame_size == 0 ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


"MMIX Internal: This is not a constant:"

Return the bit-value for a const_int or const_double .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s>
std
::
pair
<
unsigned
,
const
TargetRegisterClass
*
>
MipsTargetLowering
::
getRegForInlineAsmConstraint
(
const
std
::
string
&
Constraint
,
EVT
VT
)
const
{
if
(
Constraint
.
size
(
)
==
1
)
{
switch
(
Constraint
[
0
]
)
{
case
'd'
:
case
'y'
:
case
'r'
:
if
(
VT
==
MVT
::
i32
||
VT
==
MVT
::
i16
||
VT
==
MVT
::
i8
)
{
if
(
Subtarget
->
inMips16Mode
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU16RegsRegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
}
if
(
VT
==
MVT
::
i64
&&
!
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPURegsRegClass
)
;
if
(
VT
==
MVT
::
i64
&&
HasMips64
)
return
std
::
make_pair
(
0U
,
&
Mips
::
CPU64RegsRegClass
)
;
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
case
'f'
:
if
(
VT
==
MVT
::
f32
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR32RegClass
)
;
if
(
(
VT
==
MVT
::
f64
)
&&
(
!
Subtarget
->
isSingleFloat
(
)
)
)
{
if
(
Subtarget
->
isFP64bit
(
)
)
return
std
::
make_pair
(
0U
,
&
Mips
::
FGR64RegClass
)
;
return
std
::
make_pair
(
0U
,
&
Mips
::
AFGR64RegClass
)
;
}
break
;
case
'c'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9
,
&
Mips
::
CPURegsRegClass
)
;
assert
(
VT
==
MVT
::
i64
&&
"Unexpected type."
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
T9_64
,
&
Mips
::
CPU64RegsRegClass
)
;
case
'l'
:
if
(
VT
==
MVT
::
i32
)
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO
,
&
Mips
::
HILORegClass
)
;
return
std
::
make_pair
(
(
unsigned
)
Mips
::
LO64
,
&
Mips
::
HILO64RegClass
)
;
case
'x'
:
return
std
::
make_pair
(
0u
,
static_cast
<
const
TargetRegisterClass
*
>
(
0
)
)
;
}
}
return
TargetLowering
::
getRegForInlineAsmConstraint
(
Constraint
,
VT
)
;
}
</s>

Given a physical register constraint ( e.g .


<s> static const char * elf_platform ( void ) { int fd ; fd = open ( "/proc/self/auxv" , O_RDONLY ) ; if ( fd != - 1 ) { char buf [ 1024 ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > 0 ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_PLATFORM : return ( const char * ) av -> a_un . a_val ; default : break ; } } } </s>

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> void LEGInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void Cpu0SEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Cpu0MachineFunctionInfo * Cpu0FI = MF . getInfo < Cpu0MachineFunctionInfo > ( ) ; const Cpu0SEInstrInfo & TII = * static_cast < const Cpu0SEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const Cpu0RegisterInfo & RegInfo = * static_cast < const Cpu0SERegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; Cpu0ABIInfo ABI = STI . getABI ( ) ; unsigned SP = Cpu0 :: SP ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


<s> bool X86IndirectBranchTrackingPass :: runOnMachineFunction ( MachineFunction & MF ) { const X86Subtarget & SubTarget = MF . getSubtarget < X86Subtarget > ( ) ; auto & MMI = MF . getMMI ( ) ; Metadata * isCFProtectionSupported = MMI . getModule ( ) -> getModuleFlag ( "cf-protection-branch" ) ; Metadata * FineIBT = MMI . getModule ( ) -> getModuleFlag ( "cf-protection-fine" ) ; const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? X86 :: ENDBR64 : X86 :: ENDBR32 ; if ( FineIBT ) { Changed |= applyFineIBT ( MF ) ; FixICalls ( MF ) ; FixDCalls ( MF ) ; } else { Changed |= applyCoarseIBT ( MF ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( 0 ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) { MCSymbol * Sym = I -> getOperand ( 0 ) . getMCSymbol ( ) ; if ( ! MF . hasCallSiteLandingPad ( Sym ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } else if ( MBB . isEHPad ( ) ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isEHLabel ( ) ) continue ; Changed |= addENDBR ( MBB , std :: next ( I ) ) ; break ; } } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AssertZext : return performAssertZextCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::AssertZext


<s> bool ix86_expand_int_vcond ( rtx operands [ ] ) { machine_mode data_mode = GET_MODE ( operands [ 0 ] ) ; machine_mode mode = GET_MODE ( operands [ 4 ] ) ; enum rtx_code code = GET_CODE ( operands [ 3 ] ) ; bool negate = false ; rtx x , cop0 , cop1 ; cop0 = operands [ 4 ] ; cop1 = operands [ 5 ] ; if ( ( code == LT || code == GE ) && data_mode == mode && cop1 == CONST0_RTX ( mode ) && operands [ 1 + ( code == LT ) ] == CONST0_RTX ( data_mode ) && GET_MODE_UNIT_SIZE ( data_mode ) > 1 && GET_MODE_UNIT_SIZE ( data_mode ) <= 8 && ( GET_MODE_SIZE ( data_mode ) == 16 || ( TARGET_AVX2 && GET_MODE_SIZE ( data_mode ) == 32 ) ) ) { rtx negop = operands [ 2 - ( code == LT ) ] ; int shift = GET_MODE_UNIT_BITSIZE ( data_mode ) - 1 ; if ( negop == CONST1_RTX ( data_mode ) ) { rtx res = expand_simple_binop ( mode , LSHIFTRT , cop0 , GEN_INT ( shift ) , operands [ 0 ] , 1 , OPTAB_DIRECT ) ; if ( res != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , res ) ; return true ; } else if ( GET_MODE_INNER ( data_mode ) != DImode && vector_all_ones_operand ( negop , data_mode ) ) { rtx res = expand_simple_binop ( mode , ASHIFTRT , cop0 , GEN_INT ( shift ) , operands [ 0 ] , 0 , OPTAB_DIRECT ) ; if ( res != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , res ) ; return true ; } } if ( ! nonimmediate_operand ( cop1 , mode ) ) cop1 = force_reg ( mode , cop1 ) ; if ( ! general_operand ( operands [ 1 ] , data_mode ) ) operands [ 1 ] = force_reg ( data_mode , operands [ 1 ] ) ; if ( ! general_operand ( operands [ 2 ] , data_mode ) ) operands [ 2 ] = force_reg ( data_mode , operands [ 2 ] ) ; x = ix86_expand_int_sse_cmp ( operands [ 0 ] , code , cop0 , cop1 , operands [ 1 ] , operands [ 2 ] , & negate ) ; if ( ! x ) return false ; ix86_expand_sse_movcc ( operands [ 0 ] , x , operands [ 1 + negate ] , operands [ 2 - negate ] ) ; return true ; } </s>

Expand a signed integral vector conditional move .


<s> static unsigned getFramePointerSaveOffset ( bool LP64 , bool isMacho ) { if ( isMacho ) return LP64 ? 40 : 20 ; return - 4U ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s> bool wext_odd_dep_p ( rtx insn , rtx def_reg ) { rtx shift_rtx = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; rtx use_reg = XEXP ( shift_rtx , 0 ) ; rtx pos_rtx = XEXP ( shift_rtx , 1 ) ; if ( REG_P ( pos_rtx ) && reg_overlap_p ( def_reg , pos_rtx ) ) return true ; if ( GET_MODE ( def_reg ) == DImode ) return reg_overlap_p ( def_reg , use_reg ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; gcc_assert ( REG_P ( use_reg ) || GET_CODE ( use_reg ) == SUBREG ) ; if ( REG_P ( def_reg ) ) { if REG_P ( use_reg ) { if ( ! TARGET_BIG_ENDIAN ) return REGNO ( def_reg ) == REGNO ( use_reg ) + 1 ; else return REGNO ( def_reg ) == REGNO ( use_reg ) ; } else return true ; } if ( GET_CODE ( def_reg ) == SUBREG ) { if ( ! reg_overlap_p ( def_reg , use_reg ) ) return false ; if ( GET_CODE ( use_reg ) == SUBREG ) return true ; if ( ! TARGET_BIG_ENDIAN ) return SUBREG_BYTE ( def_reg ) == 4 ; else return SUBREG_BYTE ( def_reg ) == 0 ; } return false ; } </s>

Check if INSN is a wext insn consuming DEF_REG .


<s> RegisterBankInfo :: InstructionMappings X86RegisterBankInfo :: getInstrAlternativeMappings ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_IMPLICIT_DEF : { unsigned Size = getSizeInBits ( MI . getOperand ( 0 ) . getReg ( ) , MRI , TRI ) ; if ( Size != 32 && Size != 64 ) break ; unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < PartialMappingIdx , 4 > OpRegBankIdx ( NumOperands ) ; getInstrPartialMappingIdxs ( MI , MRI , true , OpRegBankIdx ) ; SmallVector < const ValueMapping * , 8 > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) break ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstructionMapping ( 1 , 1 , getOperandsMapping ( OpdsMapping ) , NumOperands ) ; InstructionMappings AltMappings ; AltMappings . push_back ( & Mapping ) ; return AltMappings ; } default : break ; } return RegisterBankInfo :: getInstrAlternativeMappings ( MI ) ; } </s>


<s> const char * FISCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case FISCISD :: RET_FLAG : return "RetFlag" ; case FISCISD :: LOAD_SYM : return "LOAD_SYM" ; case FISCISD :: MOVEi64 : return "MOVEi64" ; case FISCISD :: CALL : return "CALL" ; case FISCISD :: SELECT_CC : return "SELECT_CC" ; case FISCISD :: CMP : return "CMP" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> unsigned Mips16InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
bool
MipsAsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
StringRef
IDVal
=
DirectiveID
.
getString
(
)
;
if
(
IDVal
==
".cpload"
)
return
parseDirectiveCPLoad
(
DirectiveID
.
getLoc
(
)
)
;
if
(
IDVal
==
".dword"
)
{
parseDataDirective
(
8
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".ent"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".end"
)
{
Parser
.
Lex
(
)
;
return
false
;
}
if
(
IDVal
==
".frame"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".set"
)
{
return
parseDirectiveSet
(
)
;
}
if
(
IDVal
==
".fmask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".mask"
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
false
;
}
if
(
IDVal
==
".nan"
)
return
parseDirectiveNaN
(
)
;
if
(
IDVal
==
".gpword"
)
{
parseDirectiveGpWord
(
)
;
return
false
;
}
if
(
IDVal
==
".gpdword"
)
{
parseDirectiveGpDWord
(
)
;
return
false
;
}
if
(
IDVal
==
".word"
)
{
parseDataDirective
(
4
,
DirectiveID
.
getLoc
(
)
)
;
return
false
;
}
if
(
IDVal
==
".option"
)
return
parseDirectiveOption
(
)
;
if
(
IDVal
==
".abicalls"
)
{
getTargetStreamer
(
)
.
emitDirectiveAbiCalls
(
)
;
if
(
Parser
.
getTok
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
Error
(
Parser
.
getTok
(
)
.
getLoc
(
)
,
"unexpected token in directive"
)
;
Parser
.
eatToEndOfStatement
(
)
;
}
return
false
;
}
if
(
IDVal
==
".cpsetup"
)
return
parseDirectiveCPSetup
(
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static rtx_insn * mips_break_sequence ( rtx_insn * insn ) { rtx_insn * before = PREV_INSN ( insn ) ; rtx_insn * branch = SEQ_BEGIN ( insn ) ; rtx_insn * ds = SEQ_END ( insn ) ; remove_insn ( insn ) ; add_insn_after ( ds , before , NULL ) ; add_insn_after ( branch , ds , NULL ) ; return ds ; } </s>

Remove a SEQUENCE and replace it with the delay slot instruction followed by the branch and return the instruction in the delay slot . Return the first of the two new instructions . Subroutine of mips_reorg_process_insns .


<s> bool isLegalMaskedGather ( Type * Ty , MaybeAlign Alignment ) { return false ; } </s>

Return true if the target supports masked gather .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>


"Basic block should contain at least a RET but is empty"


<s> static rtx nds32_expand_triopimm_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p , const char * name ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; rtx op2 = nds32_read_argument ( exp , 2 ) ; int op0_num = return_p ? 1 : 0 ; int op1_num = return_p ? 2 : 1 ; int op2_num = return_p ? 3 : 2 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op2_num , op2 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; op2 = nds32_legitimize_argument ( icode , op2_num , op2 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 , op2 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take three operands and the third is immediate .


<s> static bool aarch64_evpc_zip ( struct expand_vec_perm_d * d ) { unsigned int high ; poly_uint64 nelt = d -> perm . length ( ) ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; poly_uint64 first = d -> perm [ 0 ] ; if ( ( maybe_ne ( first , 0U ) && maybe_ne ( first * 2 , nelt ) ) || ! d -> perm . series_p ( 0 , 2 , first , 1 ) || ! d -> perm . series_p ( 1 , 2 , first + nelt , 1 ) ) return false ; high = maybe_ne ( first , 0U ) ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ; high = ! high ; } out = d -> target ; emit_set_insn ( out , gen_rtx_UNSPEC ( vmode , gen_rtvec ( 2 , in0 , in1 ) , high ? UNSPEC_ZIP2 : UNSPEC_ZIP1 ) ) ; return true ; } </s>

Recognize patterns suitable for the ZIP instructions .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const char * arm_strip_name_encoding ( const char * name ) { int skip ; while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ; return name ; } </s>

Return a pointer to a function 's name with any and all prefix encodings stripped from it .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool X86TTIImpl :: supportsEfficientVectorElementLoadStore ( ) const { return false ; } </s>

If target has efficient vector element load/store instructions , it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store .


<s> static recps_type get_recps_type ( machine_mode mode ) { switch ( mode ) { case SFmode : return ( gen_aarch64_frecpssf ) ; case V2SFmode : return ( gen_aarch64_frecpsv2sf ) ; case V4SFmode : return ( gen_aarch64_frecpsv4sf ) ; case DFmode : return ( gen_aarch64_frecpsdf ) ; case V2DFmode : return ( gen_aarch64_frecpsv2df ) ; default : gcc_unreachable ( ) ; } } </s>

Select reciprocal series step insn depending on machine mode .


<s> const Cpu0TargetMachine & getTargetMachine ( ) { return static_cast < const Cpu0TargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> static void pa_hpux_file_end ( void ) { unsigned int i ; extern_symbol * p ; if ( ! NO_DEFERRED_PROFILE_COUNTERS ) output_deferred_profile_counters ( ) ; output_deferred_plabels ( ) ; for ( i = 0 ; vec_safe_iterate ( extern_symbols , i , & p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , 0 ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } vec_free ( extern_symbols ) ; } </s>

Output text required at the end of an assembler file . This includes deferred plabels and .import directives for all external symbols that were actually referenced .


<s>
const
char
*
output_move_quad
(
rtx
*
operands
)
{
if
(
REG_P
(
operands
[
0
]
)
)
{
if
(
MEM_P
(
operands
[
1
]
)
)
{
switch
(
GET_CODE
(
XEXP
(
operands
[
1
]
,
0
)
)
)
{
case
REG
:
output_asm_insn
(
"ldmia%?\t%m1, %M0"
,
operands
)
;
break
;
case
LABEL_REF
:
case
CONST
:
output_asm_insn
(
"adr%?\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldmia%?\t%0, %M0"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
{
rtx
ops
[
2
]
;
int
dest
,
src
,
i
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
dest
=
REGNO
(
operands
[
0
]
)
;
src
=
REGNO
(
operands
[
1
]
)
;
if
(
dest
<
src
)
for
(
i
=
0
;
i
<
4
;
i
++
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
else
for
(
i
=
3
;
i
>=
0
;
i
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
}
}
else
{
gcc_assert
(
MEM_P
(
operands
[
0
]
)
)
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
gcc_assert
(
!
reg_overlap_mentioned_p
(
operands
[
1
]
,
operands
[
0
]
)
)
;
switch
(
GET_CODE
(
XEXP
(
operands
[
0
]
,
0
)
)
)
{
case
REG
:
output_asm_insn
(
"stm%?\t%m0, %M1"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
return
""
;
}
</s>

Output assembler code to perform a quadword move insn with operands OPERANDS .


<s>
void
LoongArchDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
MVT
GRLenVT
=
Subtarget
->
getGRLenVT
(
)
;
SDLoc
DL
(
Node
)
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
Constant
:
{
int64_t
Imm
=
cast
<
ConstantSDNode
>
(
Node
)
->
getSExtValue
(
)
;
SDNode
*
Result
=
nullptr
;
SDValue
SrcReg
=
CurDAG
->
getRegister
(
LoongArch
::
R0
,
GRLenVT
)
;
for
(
LoongArchMatInt
::
Inst
&
Inst
:
LoongArchMatInt
::
generateInstSeq
(
Imm
)
)
{
SDValue
SDImm
=
CurDAG
->
getTargetConstant
(
Inst
.
Imm
,
DL
,
GRLenVT
)
;
if
(
Inst
.
Opc
==
LoongArch
::
LU12I_W
)
Result
=
CurDAG
->
getMachineNode
(
LoongArch
::
LU12I_W
,
DL
,
GRLenVT
,
SDImm
)
;
else
Result
=
CurDAG
->
getMachineNode
(
Inst
.
Opc
,
DL
,
GRLenVT
,
SrcReg
,
SDImm
)
;
SrcReg
=
SDValue
(
Result
,
0
)
;
}
ReplaceNode
(
Node
,
Result
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> bool X86CallFrameOptimization :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! isLegal ( MF ) ) return false ; int FrameSetupOpcode = TII -> getCallFrameSetupOpcode ( ) ; bool Changed = false ; ContextMap CallSeqMap ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) { CallContext & Context = CallSeqMap [ I ] ; collectCallInfo ( MF , * BB , I , Context ) ; } if ( ! isProfitable ( MF , CallSeqMap ) ) return false ; for ( auto CC : CallSeqMap ) if ( CC . second . UsePush ) Changed |= adjustCallSequence ( MF , CC . first , CC . second ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MipsSEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned BP = ABI . IsN64 ( ) ? Mips :: S7_64 : Mips :: S7 ; if ( hasFP ( MF ) ) setAliasRegs ( MF , SavedRegs , FP ) ; if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( MipsFI -> callsEhReturn ( ) ) MipsFI -> createEhDataRegsFI ( ) ; if ( MipsFI -> isISR ( ) ) MipsFI -> createISRRegFI ( ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass * RC = STI . hasMips64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = MF . getInfo < MipsFunctionInfo > ( ) -> getIncomingArgSize ( ) + estimateStackSize ( MF ) ; if ( isInt < 16 > ( MaxSPOffset ) ) return ; const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; int FI = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static int supersparc_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type ; if ( recog_memoized ( insn ) < 0 ) return cost ; insn_type = get_attr_type ( insn ) ; if ( dep_type == 0 ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + 3 ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + 3 ; } if ( insn_type == TYPE_SHIFT ) return cost + 3 ; } else { if ( insn_type == TYPE_IALU || insn_type == TYPE_SHIFT ) return 0 ; } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; switch ( VA . getLocInfo ( ) ) { default : MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; break ; case CCValAssign :: LocInfo :: SExt : case CCValAssign :: LocInfo :: ZExt : case CCValAssign :: LocInfo :: AExt : { auto Copy = MIRBuilder . buildCopy ( LLT { VA . getLocVT ( ) } , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; break ; } } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .