<s> bool ix86_expand_fp_vec_cmp ( rtx operands [ ] ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx cmp ; code = ix86_prepare_sse_fp_compare_args ( operands [ 0 ] , code , & operands [ 2 ] , & operands [ 3 ] ) ; if ( code == UNKNOWN ) { rtx temp ; switch ( GET_CODE ( operands [ 1 ] ) ) { case LTGT : temp = ix86_expand_sse_cmp ( operands [ 0 ] , ORDERED , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , NE , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; code = AND ; break ; case UNEQ : temp = ix86_expand_sse_cmp ( operands [ 0 ] , UNORDERED , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; cmp = ix86_expand_sse_cmp ( operands [ 0 ] , EQ , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; code = IOR ; break ; default : gcc_unreachable ( ) ; } cmp = expand_simple_binop ( GET_MODE ( cmp ) , code , temp , cmp , cmp , 1 , OPTAB_DIRECT ) ; } else cmp = ix86_expand_sse_cmp ( operands [ 0 ] , code , operands [ 2 ] , operands [ 3 ] , NULL , NULL ) ; if ( operands [ 0 ] != cmp ) emit_move_insn ( operands [ 0 ] , cmp ) ; return true ; } </s>


<s> bool n8_consumed_by_ex_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : if ( movd44_even_dep_p ( consumer , def_reg ) ) return true ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_BRANCH : use_rtx = extract_branch_condition_rtx ( consumer ) ; break ; case TYPE_STORE : if ( ! post_update_insn_p ( consumer ) && ! immed_offset_p ( extract_mem_rtx ( consumer ) ) ) return false ; use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_STORE_MULTIPLE : use_rtx = extract_nth_access_rtx ( consumer , 0 ) ; break ; default : gcc_unreachable ( ) ; } return reg_overlap_p ( def_reg , use_rtx ) ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void SystemZPostRASchedStrategy :: releaseTopNode ( SUnit * SU ) { const MCSchedClassDesc * SC = HazardRec -> getSchedClass ( SU ) ; bool AffectsGrouping = ( SC -> isValid ( ) && ( SC -> BeginGroup || SC -> EndGroup ) ) ; SU -> isScheduleHigh = ( AffectsGrouping || SU -> isUnbuffered ) ; Available . insert ( SU ) ; } </s>

SU has had all predecessor dependencies resolved .


<s> std :: pair < SDValue , SDValue > SystemZSelectionDAGInfo :: EmitTargetCodeForStrcmp ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src1 , SDValue Src2 , MachinePointerInfo Op1PtrInfo , MachinePointerInfo Op2PtrInfo ) const { SDVTList VTs = DAG . getVTList ( Src1 . getValueType ( ) , MVT :: i32 , MVT :: Other ) ; SDValue Unused = DAG . getNode ( SystemZISD :: STRCMP , DL , VTs , Chain , Src2 , Src1 , DAG . getConstant ( 0 , DL , MVT :: i32 ) ) ; SDValue CCReg = Unused . getValue ( 1 ) ; Chain = Unused . getValue ( 2 ) ; return std :: make_pair ( addIPMSequence ( DL , CCReg , DAG ) , Chain ) ; } </s>

Emit target-specific code that performs a strcmp , in cases where that is faster than a libcall .


<s> bool SVEIntrinsicOpts :: runOnModule ( Module & M ) { bool Changed = false ; SmallSetVector < Function * , 4 > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: aarch64_sve_convert_from_svbool : case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : for ( auto I = F . user_begin ( ) , E = F . user_end ( ) ; I != E ; ) { auto * Inst = dyn_cast < Instruction > ( * I ++ ) ; Functions . insert ( Inst -> getFunction ( ) ) ; } break ; default : break ; } } if ( ! Functions . empty ( ) ) Changed |= optimizeFunctions ( Functions ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"AArch64 pseudo instruction expansion pass"

getPassName - Return a nice clean name for a pass .


<s> bool CSKYFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void initialize ( ScheduleDAGMI * dag ) override { } </s>

Initialize the strategy after building the DAG for a new region .


<s> unsigned char PPCSubtarget :: classifyGlobalReference ( const GlobalValue * GV ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return PPCII :: MO_PIC_FLAG | PPCII :: MO_NLP_FLAG ; if ( TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return PPCII :: MO_PIC_FLAG ; return PPCII :: MO_PIC_FLAG | PPCII :: MO_NLP_FLAG ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> void function_arg_advance ( CUMULATIVE_ARGS * cum , enum machine_mode mode , tree type , int named ) { struct mips_arg_info info ; mips_arg_info ( cum , mode , type , named , & info ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < 2 && info . fpr_p ) cum -> fp_code += ( mode == SFmode ? 1 : 2 ) << ( ( cum -> arg_number - 1 ) * 2 ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset + info . reg_words ; else if ( info . reg_words > 0 ) cum -> num_fprs += FP_INC ; if ( info . stack_words > 0 ) cum -> stack_words = info . stack_offset + info . stack_words ; cum -> arg_number ++ ; } </s>

Handle the FUNCTION_ARG_ADVANCE macro . Update the data in CUM to advance over an argument of mode MODE and data type TYPE . TYPE is null for libcalls where that information may not be available .


<s>
void
Cpu0DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> const uint32_t * MMIXRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ; } </s>

Return a register mask that clobbers everything .


<s> static bool arm_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ? caller_tree : target_option_default_node ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ? callee_tree : target_option_default_node ) ; const struct arm_fpu_desc * caller_fpu = & all_fpus [ caller_opts -> x_arm_fpu_index ] ; const struct arm_fpu_desc * callee_fpu = & all_fpus [ callee_opts -> x_arm_fpu_index ] ; if ( ( caller_fpu -> features & callee_fpu -> features ) != callee_fpu -> features ) return false ; if ( callee_fpu -> model != caller_fpu -> model || callee_fpu -> regs != callee_fpu -> regs ) return false ; return true ; } </s>

Hook to determine if one function can safely inline another .


<s> void LEGDAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : SelectMoveImmediate ( N ) ; return ; case ISD :: BR_CC : SelectConditionalBranch ( N ) ; return ; } SelectCode ( N ) ; } </s>


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
bool
X86TargetLowering
::
shouldReduceLoadWidth
(
SDNode
*
Load
,
ISD
::
LoadExtType
ExtTy
,
EVT
NewVT
)
const
{
assert
(
cast
<
LoadSDNode
>
(
Load
)
->
isSimple
(
)
&&
"illegal to narrow"
)
;
SDValue
BasePtr
=
cast
<
LoadSDNode
>
(
Load
)
->
getBasePtr
(
)
;
if
(
BasePtr
.
getOpcode
(
)
==
X86ISD
::
WrapperRIP
)
if
(
const
auto
*
GA
=
dyn_cast
<
GlobalAddressSDNode
>
(
BasePtr
.
getOperand
(
0
)
)
)
return
GA
->
getTargetFlags
(
)
!=
X86II
::
MO_GOTTPOFF
;
EVT
VT
=
Load
->
getValueType
(
0
)
;
if
(
(
VT
.
is256BitVector
(
)
||
VT
.
is512BitVector
(
)
)
&&
!
Load
->
hasOneUse
(
)
)
{
for
(
auto
UI
=
Load
->
use_begin
(
)
,
UE
=
Load
->
use_end
(
)
;
UI
!=
UE
;
++
UI
)
{
if
(
UI
.
getUse
(
)
.
getResNo
(
)
!=
0
)
continue
;
if
(
UI
->
getOpcode
(
)
!=
ISD
::
EXTRACT_SUBVECTOR
||
!
UI
->
hasOneUse
(
)
||
UI
->
use_begin
(
)
->
getOpcode
(
)
!=
ISD
::
STORE
)
return
true
;
}
return
false
;
}
return
true
;
}
</s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> int ARMTTIImpl :: getFPOpCost ( Type * Ty ) { if ( ST -> hasVFP2 ( ) && ! ST -> isThumb1Only ( ) ) { if ( Ty -> isFloatTy ( ) ) { return TargetTransformInfo :: TCC_Basic ; } if ( Ty -> isDoubleTy ( ) ) { return ST -> isFPOnlySP ( ) ? TargetTransformInfo :: TCC_Expensive : TargetTransformInfo :: TCC_Basic ; } } return TargetTransformInfo :: TCC_Expensive ; } </s>

Return the expected cost of supporting the floating point operation of the specified type .


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen_neon_vuzp_internal ( d -> vmode , out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasByValOrInAllocaAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RIOS1 : case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : return 2 ; case CPU_RIOS2 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : return 5 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> void hppa_encode_label ( rtx sym ) { const char * str = XSTR ( sym , 0 ) ; int len = strlen ( str ) + 1 ; char * newstr , * p ; p = newstr = alloca ( len + 1 ) ; * p ++ = '@' ; strcpy ( p , str ) ; XSTR ( sym , 0 ) = ggc_alloc_string ( newstr , len ) ; } </s>

In HPUX 8.0 's shared library scheme , special relocations are needed for function labels if they might be passed to a function in a shared library ( because shared libraries do n't live in code space ) , and special magic is needed to construct their address .


<s> bool X86TargetLowering :: isGAPlusOffset ( SDNode * N , GlobalValue * & GA , int64_t & Offset ) const { if ( N -> getOpcode ( ) == X86ISD :: Wrapper ) { if ( isa < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) ) { GA = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getGlobal ( ) ; Offset = cast < GlobalAddressSDNode > ( N -> getOperand ( 0 ) ) -> getOffset ( ) ; return true ; } } return TargetLowering :: isGAPlusOffset ( N , GA , Offset ) ; } </s>

Returns true ( and the GlobalValue and the offset ) if the node is a GlobalAddress + offset .


"argument to %qs must be a 2-bit unsigned literal"


<s> bool ARMRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ; } </s>


<s> bool aarch64_emit_approx_div ( rtx quo , rtx num , rtx den ) { machine_mode mode = GET_MODE ( quo ) ; if ( GET_MODE_INNER ( mode ) == HFmode ) return false ; bool use_approx_division_p = ( flag_mlow_precision_div || ( aarch64_tune_params . approx_modes -> division & AARCH64_APPROX_MODE ( mode ) ) ) ; if ( ! flag_finite_math_only || flag_trapping_math || ! flag_unsafe_math_optimizations || optimize_function_for_size_p ( cfun ) || ! use_approx_division_p ) return false ; rtx xrcp = gen_reg_rtx ( mode ) ; emit_insn ( ( * get_recpe_type ( mode ) ) ( xrcp , den ) ) ; int iterations = ( GET_MODE_INNER ( mode ) == DFmode ) ? 3 : 2 ; if ( flag_mlow_precision_div ) iterations -- ; rtx xtmp = gen_reg_rtx ( mode ) ; while ( iterations -- ) { emit_insn ( ( * get_recps_type ( mode ) ) ( xtmp , xrcp , den ) ) ; if ( iterations > 0 ) emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; } if ( num != CONST1_RTX ( mode ) ) { rtx xnum = force_reg ( mode , num ) ; emit_set_insn ( xrcp , gen_rtx_MULT ( mode , xrcp , xnum ) ) ; } emit_set_insn ( quo , gen_rtx_MULT ( mode , xrcp , xtmp ) ) ; return true ; } </s>

Emit the instruction sequence to compute the approximation for the division of NUM by DEN in QUO and return whether the sequence was emitted or not .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; unsigned NumCopies = 0 ; SDNode * Copies [ 2 ] ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == ISD :: CopyToReg ) { Copies [ NumCopies ++ ] = Use ; } else if ( Use -> getOpcode ( ) == ARMISD :: VMOVRRD ) { for ( SDNode :: use_iterator UI = Use -> use_begin ( ) , UE = Use -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies [ UI . getUse ( ) . getResNo ( ) ] = * UI ; ++ NumCopies ; } } else if ( Use -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Use = * Use -> use_begin ( ) ; if ( Use -> getOpcode ( ) != ISD :: CopyToReg || ! Use -> hasNUsesOfValue ( 1 , 0 ) ) return false ; Copies [ NumCopies ++ ] = Use ; } else { return false ; } if ( NumCopies != 1 && NumCopies != 2 ) return false ; bool HasRet = false ; for ( unsigned i = 0 ; i < NumCopies ; ++ i ) { SDNode * Copy = Copies [ i ] ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == ISD :: CopyToReg ) { SDNode * Use = * UI ; if ( Use == Copies [ 0 ] || Use == Copies [ 1 ] ) continue ; return false ; } if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG ) return false ; HasRet = true ; } } return HasRet ; } </s>

Return true if result of the specified node is used by a return node only .


<s> static bool aarch64_macro_fusion_p ( void ) { return aarch64_tune_params . fusible_ops != AARCH64_FUSE_NOTHING ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_P . Return true if target supports instruction fusion of some sort .


<s> llvm :: FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; if ( Subtarget -> isTargetIOS ( ) && ! Subtarget -> isThumb1Only ( ) && ! DisableARMFastISel ) return new ARMFastISel ( funcInfo ) ; return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .

ARM ARM::createFastISel ARM ARM ARM ARM 0


<s> virtual const LC3bInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> static void ia64_asm_init_sections ( void ) { exception_section = get_unnamed_section ( 0 , output_section_asm_op , "\t.handlerdata" ) ; } </s>


<s> unsigned OR1KMachineFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & OR1K :: GPRRegClass ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> unsigned ARMScalarTargetTransformImpl :: getIntImmCost ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return 4 ; int32_t SImmVal = Imm . getSExtValue ( ) ; uint32_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! Subtarget -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return Subtarget -> hasV6T2Ops ( ) ? 2 : 3 ; } else if ( Subtarget -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return Subtarget -> hasV6T2Ops ( ) ? 2 : 3 ; } else { if ( SImmVal >= 0 && SImmVal < 256 ) return 1 ; if ( ( ~ ZImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } return 2 ; } </s>

Calculate the cost of materializing a 64-bit value .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> unsigned LEGInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static void fusion_split_address ( rtx addr , rtx * p_hi , rtx * p_lo ) { rtx hi , lo ; if ( GET_CODE ( addr ) == UNSPEC && XINT ( addr , 1 ) == UNSPEC_FUSION_ADDIS ) { lo = XVECEXP ( addr , 0 , 0 ) ; hi = gen_rtx_HIGH ( Pmode , lo ) ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) { hi = XEXP ( addr , 0 ) ; lo = XEXP ( addr , 1 ) ; } else gcc_unreachable ( ) ; * p_hi = hi ; * p_lo = lo ; } </s>

Given an address , convert it into the addis and load offset parts . Addresses created during the peephole2 process look like : ( lo_sum ( high ( unspec [ ( sym ) ] UNSPEC_TOCREL ) ) ( unspec [ ( ... ) ] UNSPEC_TOCREL ) )


<s> bool nds32_isr_function_p ( tree func ) { tree t_intr ; tree t_excp ; tree t_reset ; tree attrs ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; attrs = DECL_ATTRIBUTES ( func ) ; t_intr = lookup_attribute ( "interrupt" , attrs ) ; t_excp = lookup_attribute ( "exception" , attrs ) ; t_reset = lookup_attribute ( "reset" , attrs ) ; return ( ( t_intr != NULL_TREE ) || ( t_excp != NULL_TREE ) || ( t_reset != NULL_TREE ) ) ; } </s>


<s> static void crx_compute_save_regs ( void ) { unsigned int regno ; last_reg_to_save = - 1 ; if ( FUNC_IS_NORETURN_P ( current_function_decl ) ) return ; sum_regs = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { if ( fixed_regs [ regno ] ) { save_regs [ regno ] = 0 ; continue ; } if ( crx_interrupt_function_p ( ) ) { if ( ! current_function_is_leaf && call_used_regs [ regno ] ) save_regs [ regno ] = 1 ; else if ( regs_ever_live [ regno ] ) save_regs [ regno ] = 1 ; else save_regs [ regno ] = 0 ; } else { if ( regs_ever_live [ regno ] && ( ! call_used_regs [ regno ] || regno == RETURN_ADDRESS_REGNUM ) ) save_regs [ regno ] = 1 ; else save_regs [ regno ] = 0 ; } } for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( save_regs [ regno ] == 1 ) { last_reg_to_save = regno ; sum_regs += UNITS_PER_WORD ; } } </s>

Compute values for the array save_regs and the variable sum_regs . The index * of save_regs is numbers of register , each will get 1 if we need to save it * in the current function , 0 if not . sum_regs is the total sum of the * registers being saved .


<s> virtual bool shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) override { ( void ) adjustFixupValue ( Fixup , Target . getConstant ( ) ) ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; int ZeroOperandPosition = - 1 ; bool BranchWithZeroOperand = false ; if ( I -> isBranch ( ) && ! I -> isPseudo ( ) ) { auto TRI = I -> getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; ZeroOperandPosition = I -> findRegisterUseOperandIdx ( Mips :: ZERO , false , TRI ) ; BranchWithZeroOperand = ZeroOperandPosition != - 1 ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case Mips :: BEQC : NewOpc = Mips :: BEQZC ; break ; case Mips :: BNEC : NewOpc = Mips :: BNEZC ; break ; case Mips :: BGEC : NewOpc = Mips :: BGEZC ; break ; case Mips :: BLTC : NewOpc = Mips :: BLTZC ; break ; case Mips :: BEQC64 : NewOpc = Mips :: BEQZC64 ; break ; case Mips :: BNEC64 : NewOpc = Mips :: BNEZC64 ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == Mips :: JIC || NewOpc == Mips :: JIALC || NewOpc == Mips :: JIC64 || NewOpc == Mips :: JIALC64 ) { if ( NewOpc == Mips :: JIALC || NewOpc == Mips :: JIALC64 ) MIB -> removeOperand ( 0 ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( 0 ) ; for ( unsigned J = I -> getDesc ( ) . getNumOperands ( ) , E = I -> getNumOperands ( ) ; J < E ; ++ J ) { const MachineOperand & MO = I -> getOperand ( J ) ; if ( MO . isMCSymbol ( ) && ( MO . getTargetFlags ( ) & MipsII :: MO_JALR ) ) MIB . addSym ( MO . getMCSymbol ( ) , MipsII :: MO_JALR ) ; } } else { for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ; MIB . cloneMemRefs ( * I ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


<s>
void
TOYMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
EmitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

TOY
TOY
4
"Unexpected instruction size!"


<s> const MINA32Subtarget * MINA32TargetMachine :: getSubtargetImpl ( const Function & ) const { return & SubTarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static int group_barrier_needed ( rtx_insn * insn ) { rtx pat ; int need_barrier = 0 ; struct reg_flags flags ; memset ( & flags , 0 , sizeof ( flags ) ) ; switch ( GET_CODE ( insn ) ) { case NOTE : case DEBUG_INSN : break ; case BARRIER : break ; case CODE_LABEL : memset ( rws_insn , 0 , sizeof ( rws_insn ) ) ; return 1 ; case CALL_INSN : flags . is_branch = 1 ; flags . is_sibcall = SIBLING_CALL_P ( insn ) ; memset ( rws_insn , 0 , sizeof ( rws_insn ) ) ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = 1 ; break ; } need_barrier = rtx_needs_barrier ( PATTERN ( insn ) , flags , 0 ) ; break ; case JUMP_INSN : if ( ! ia64_spec_check_p ( insn ) ) flags . is_branch = 1 ; if ( ( pat = prev_active_insn ( insn ) ) && CALL_P ( pat ) ) { need_barrier = 1 ; break ; } case INSN : if ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) break ; pat = PATTERN ( insn ) ; switch ( recog_memoized ( insn ) ) { case CODE_FOR_epilogue_deallocate_stack : case CODE_FOR_prologue_allocate_stack : pat = XVECEXP ( pat , 0 , 0 ) ; break ; case CODE_FOR_doloop_end_internal : pat = XVECEXP ( pat , 0 , 1 ) ; break ; case CODE_FOR_pred_rel_mutex : case CODE_FOR_prologue_use : return 0 ; default : break ; } memset ( rws_insn , 0 , sizeof ( rws_insn ) ) ; need_barrier = rtx_needs_barrier ( pat , flags , 0 ) ; if ( ! need_barrier ) need_barrier = rws_access_regno ( REG_VOLATILE , flags , 0 ) ; break ; default : gcc_unreachable ( ) ; } if ( first_instruction && important_for_bundling_p ( insn ) ) { need_barrier = 0 ; first_instruction = 0 ; } return need_barrier ; } </s>

Given the current state , determine whether a group barrier ( a stop bit ) is necessary before INSN . Return nonzero if so . This modifies the state to include the effects of INSN as a side-effect .


Determine whether a memory reference takes one ( based off of the GP pointer ) , two ( normal ) , or three ( label + reg ) instructions , and bump the appropriate counter for -mstats .


<s> static rtx neon_vdup_constant ( rtx vals , bool generate ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > 4 ) return NULL_RTX ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; if ( ! generate ) return x ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_vec_duplicate ( mode , x ) ; } </s>

Return a non-NULL RTX iff VALS is a vector constant that can be loaded into a register using VDUP . If this is the case , and GENERATE is set , we also generate instructions to do this and return an RTX to assign to the register .


<s> static void winnt_d_os_builtins ( void ) { d_add_builtin_version ( "Windows" ) ; d_add_builtin_version ( "MinGW" ) ; if ( TARGET_64BIT && ix86_abi == MS_ABI ) d_add_builtin_version ( "Win64" ) ; else if ( ! TARGET_64BIT ) d_add_builtin_version ( "Win32" ) ; d_add_builtin_version ( "CRuntime_Microsoft" ) ; } </s>

Implement TARGET_D_OS_VERSIONS for Windows targets .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void ARMConstantPoolMBB :: print ( raw_ostream & O ) const { ARMConstantPoolValue :: print ( O ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s> int rs6000_store_data_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set ; rtx out_pat , in_pat ; rtx out_exp , in_exp ; int i , j ; in_set = single_set ( in_insn ) ; if ( in_set ) { if ( MEM_P ( SET_DEST ( in_set ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) == PARALLEL ) { for ( i = 0 ; i < XVECLEN ( out_pat , 0 ) ; i ++ ) { out_exp = XVECEXP ( out_pat , 0 , i ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } else { in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( i = 0 ; i < XVECLEN ( in_pat , 0 ) ; i ++ ) { in_exp = XVECEXP ( in_pat , 0 , i ) ; if ( ( GET_CODE ( in_exp ) == CLOBBER ) || ( GET_CODE ( in_exp ) == USE ) ) continue ; else if ( GET_CODE ( in_exp ) != SET ) return false ; if ( MEM_P ( SET_DEST ( in_exp ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) != PARALLEL ) return false ; for ( j = 0 ; j < XVECLEN ( out_pat , 0 ) ; j ++ ) { out_exp = XVECEXP ( out_pat , 0 , j ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } return store_data_bypass_p ( out_insn , in_insn ) ; } </s>

Given that there exists at least one variable that is set ( produced ) by OUT_INSN and read ( consumed ) by IN_INSN , return true iff IN_INSN represents one or more memory store operations and none of the variables set by OUT_INSN is used by IN_INSN as the address of a store operation . If either IN_INSN or OUT_INSN does not represent a `` single '' RTL SET expression ( as loosely defined by the implementation of the single_set function ) or a PARALLEL with only SETs , CLOBBERs , and USEs inside , this function returns false . This rs6000-specific version of store_data_bypass_p checks for certain conditions that result in assertion failures ( and internal compiler errors ) in the generic store_data_bypass_p function and returns false rather than calling store_data_bypass_p if one of the problematic conditions is detected .


<s> void mt_expand_epilogue ( enum epilogue_type eh_mode ) { rtx size_rtx , insn ; unsigned frame_size ; mt_compute_frame_size ( get_frame_size ( ) ) ; if ( TARGET_DEBUG_STACK ) mt_debug_stack ( & current_frame_info ) ; frame_size = current_frame_info . total_size ; if ( CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) size_rtx = GEN_INT ( frame_size ) ; else { gcc_assert ( ! interrupt_handler ) ; size_rtx = gen_rtx_REG ( SImode , GPR_R9 ) ; insn = emit_move_insn ( size_rtx , GEN_INT ( frame_size & 0xffff0000 ) ) ; insn = emit_insn ( gen_iorsi3 ( size_rtx , size_rtx , GEN_INT ( frame_size & 0x0000ffff ) ) ) ; emit_insn ( gen_addsi3 ( size_rtx , size_rtx , stack_pointer_rtx ) ) ; } if ( frame_pointer_needed ) insn = emit_move_insn ( stack_pointer_rtx , frame_pointer_rtx ) ; mt_emit_save_fp ( FROM_MEM_TO_PROCESSOR , current_frame_info ) ; mt_emit_save_regs ( FROM_MEM_TO_PROCESSOR , current_frame_info ) ; if ( frame_size ) { if ( CONST_OK_FOR_LETTER_P ( frame_size , 'O' ) ) insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , size_rtx ) ) ; else insn = emit_move_insn ( stack_pointer_rtx , gen_rtx_REG ( SImode , GPR_R9 ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( SImode , stack_pointer_rtx , GEN_INT ( frame_size ) ) ) , REG_NOTES ( insn ) ) ; } if ( cfun -> machine && cfun -> machine -> eh_stack_adjust != NULL_RTX ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , cfun -> machine -> eh_stack_adjust ) ) ; if ( eh_mode == EH_EPILOGUE ) { emit_jump_insn ( gen_eh_return_internal ( ) ) ; emit_barrier ( ) ; } else if ( interrupt_handler ) emit_jump_insn ( gen_return_interrupt_internal ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; interrupt_handler = 0 ; current_frame_info = zero_frame_info ; if ( cfun -> machine ) cfun -> machine -> eh_stack_adjust = NULL_RTX ; } </s>

Generate epilogue . EH_MODE is NORMAL_EPILOGUE when generating a function epilogue , or EH_EPILOGUE when generating an EH epilogue .


<s> static bool pa_expand_compare_and_swap_loop ( rtx mem , rtx old_reg , rtx new_reg , rtx seq ) { machine_mode mode = GET_MODE ( mem ) ; rtx_code_label * label ; rtx cmp_reg , success , oldval ; label = gen_label_rtx ( ) ; cmp_reg = gen_reg_rtx ( mode ) ; emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; emit_move_insn ( old_reg , cmp_reg ) ; if ( seq ) emit_insn ( seq ) ; success = NULL_RTX ; oldval = cmp_reg ; if ( ! expand_atomic_compare_and_swap ( & success , & oldval , mem , old_reg , new_reg , false , MEMMODEL_SYNC_SEQ_CST , MEMMODEL_RELAXED ) ) return false ; if ( oldval != cmp_reg ) emit_move_insn ( cmp_reg , oldval ) ; emit_cmp_and_jump_insns ( success , const0_rtx , EQ , const0_rtx , GET_MODE ( success ) , 1 , label , 0 ) ; return true ; } </s>

This is a helper function for the other atomic operations . This function emits a loop that contains SEQ that iterates until a compare-and-swap operation at the end succeeds . MEM is the memory to be modified . SEQ is a set of instructions that takes a value from OLD_REG as an input and produces a value in NEW_REG as an output . Before SEQ , OLD_REG will be set to the current contents of MEM . After SEQ , a compare-and-swap will attempt to update MEM with NEW_REG . The function returns true when the loop was generated successfully .


<s> bool MipsTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMipsDelaySlotFillerPass ( * this ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool sh_is_nott_insn ( const rtx_insn * i ) { return i != NULL && GET_CODE ( PATTERN ( i ) ) == SET && t_reg_operand ( XEXP ( PATTERN ( i ) , 0 ) , VOIDmode ) && negt_reg_operand ( XEXP ( PATTERN ( i ) , 1 ) , VOIDmode ) ; } </s>

Given an insn , determine whether it 's a 'nott ' insn , i.e . an insn that negates the T bit and stores the result in the T bit .


<s>
bool
WinEHStatePass
::
runOnFunction
(
Function
&
F
)
{
if
(
!
F
.
hasPersonalityFn
(
)
)
return
false
;
PersonalityFn
=
dyn_cast
<
Function
>
(
F
.
getPersonalityFn
(
)
->
stripPointerCasts
(
)
)
;
if
(
!
PersonalityFn
)
return
false
;
Personality
=
classifyEHPersonality
(
PersonalityFn
)
;
if
(
!
isFuncletEHPersonality
(
Personality
)
)
return
false
;
bool
HasPads
=
false
;
for
(
BasicBlock
&
BB
:
F
)
{
if
(
BB
.
isEHPad
(
)
)
{
HasPads
=
true
;
break
;
}
}
if
(
!
HasPads
)
return
false
;
F
.
addFnAttr
(
"no-frame-pointer-elim"
,
"true"
)
;
emitExceptionRegistrationRecord
(
&
F
)
;
auto
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
std
::
unique_ptr
<
WinEHFuncInfo
>
FuncInfoPtr
;
if
(
!
MMI
)
FuncInfoPtr
.
reset
(
new
WinEHFuncInfo
(
)
)
;
WinEHFuncInfo
&
FuncInfo
=
*
(
MMI
&
MMI
->
getWinEHFuncInfo
(
&
F
)
:
FuncInfoPtr
.
get
(
)
)
;
FuncInfo
.
EHRegNode
=
RegNode
;
switch
(
Personality
)
{
default
:
llvm_unreachable
(
"unexpected personality function"
)
;
case
EHPersonality
::
MSVC_CXX
:
addCXXStateStores
(
F
,
FuncInfo
)
;
break
;
case
EHPersonality
::
MSVC_X86SEH
:
addSEHStateStores
(
F
,
FuncInfo
)
;
break
;
}
PersonalityFn
=
nullptr
;
Personality
=
EHPersonality
::
Unknown
;
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned int nds32_dbx_register_number ( unsigned int regno ) { if ( NDS32_IS_FPR_REGNUM ( regno ) ) return regno + 4 ; return regno ; } </s>

Map internal gcc register numbers to DWARF2 register numbers .


<s> void fma_forest :: merge_forest ( fma_forest * other_forest ) { std :: list < fma_root_node * > * other_roots ; std :: list < fma_root_node * > :: iterator other_root_iter ; if ( this == other_forest ) return ; other_roots = other_forest -> m_roots ; for ( other_root_iter = other_roots -> begin ( ) ; other_root_iter != other_roots -> end ( ) ; ++ other_root_iter ) ( * other_root_iter ) -> set_forest ( this ) ; this -> m_globals -> remove_forest ( other_forest ) ; this -> m_roots -> splice ( this -> m_roots -> begin ( ) , * other_roots ) ; this -> m_nb_nodes += other_forest -> m_nb_nodes ; delete other_forest ; } </s>

Merge REF_FOREST and OTHER_FOREST together , making REF_FOREST the canonical fma_forest object to represent both .


<s>
static
void
adjust_extract
(
rtx_insn
*
insn
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
rtx
src
=
SET_SRC
(
pattern
)
;
rtx
sel
=
GET_CODE
(
src
)
==
VEC_DUPLICATE
XEXP
(
src
,
0
)
:
src
;
rtx
par
=
XEXP
(
sel
,
1
)
;
int
half_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
XEXP
(
sel
,
0
)
)
)
>>
1
;
int
lane
=
INTVAL
(
XVECEXP
(
par
,
0
,
0
)
)
;
lane
=
lane
>=
half_elts
lane
half_elts
:
lane
+
half_elts
;
XVECEXP
(
par
,
0
,
0
)
=
GEN_INT
(
lane
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lane for extract %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a vector extract operation , adjust the index of the extracted lane to account for the doubleword swap .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_lo16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_ha16"
,
16
,
16
,
0
}
,
{
"fixup_ppc_lo14"
,
16
,
14
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
TargetAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { Type * MemType = LI -> getType ( ) ; bool NoImplicitFloatOps = LI -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( MemType -> getPrimitiveSizeInBits ( ) == 64 && ! Subtarget . is64Bit ( ) && ! Subtarget . useSoftFloat ( ) && ! NoImplicitFloatOps && ( Subtarget . hasSSE1 ( ) || Subtarget . hasX87 ( ) ) ) return AtomicExpansionKind :: None ; return needsCmpXchgNb ( MemType ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> DecodeStatus SystemZDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { uint8_t Bytes [ 6 ] ; Size = 0 ; if ( Region . readBytes ( Address , 2 , Bytes ) == - 1 ) return MCDisassembler :: Fail ; const uint8_t * Table ; if ( Bytes [ 0 ] < 0x40 ) { Size = 2 ; Table = DecoderTable16 ; } else if ( Bytes [ 0 ] < 0xc0 ) { Size = 4 ; Table = DecoderTable32 ; } else { Size = 6 ; Table = DecoderTable48 ; } if ( Size > 2 && Region . readBytes ( Address + 2 , Size - 2 , Bytes + 2 ) == - 1 ) return MCDisassembler :: Fail ; uint64_t Inst = 0 ; for ( uint64_t I = 0 ; I < Size ; ++ I ) Inst = ( Inst << 8 ) | Bytes [ I ] ; return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s> void AArch64ConditionOptimizer :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void X86FrameLowering :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , int64_t NumBytes , bool InEpilogue ) const { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = 0 ; if ( isSub && ! isEAXLiveIn ( MBB ) ) Reg = ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = Is64Bit ? X86 :: MOV64ri : X86 :: MOV32ri ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64Bit ) : getADDrrOpcode ( Is64Bit ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; Offset = 0 ; continue ; } } uint64_t ThisVal = std :: min ( Offset , Chunk ) ; if ( ThisVal == ( Is64Bit ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64Bit ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64Bit ) ; if ( Reg ) { unsigned Opc = isSub ? ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64Bit ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; else MI -> setFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; continue ; } } MachineInstrBuilder MI = BuildStackAdjustment ( MBB , MBBI , DL , isSub ? - ThisVal : ThisVal , InEpilogue ) ; if ( isSub ) MI . setMIFlag ( MachineInstr :: FrameSetup ) ; else MI . setMIFlag ( MachineInstr :: FrameDestroy ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> static int length_fp_args ( rtx_insn * insn ) { int length = 0 ; rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , 1 ) ) { int arg_mode , regno ; rtx use = XEXP ( link , 0 ) ; if ( ! ( GET_CODE ( use ) == USE && GET_CODE ( XEXP ( use , 0 ) ) == REG && FUNCTION_ARG_REGNO_P ( REGNO ( XEXP ( use , 0 ) ) ) ) ) continue ; arg_mode = GET_MODE ( XEXP ( use , 0 ) ) ; regno = REGNO ( XEXP ( use , 0 ) ) ; if ( regno >= 32 && regno <= 39 ) { if ( arg_mode == SFmode ) length += 8 ; else length += 12 ; } } return length ; } </s>

Compute length of the FP argument copy sequence for INSN .


<s> bool ARMBaseInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) ( int ) Cond [ 0 ] . getImm ( ) ; Cond [ 0 ] . setImm ( ARMCC :: getOppositeCondition ( CC ) ) ; return false ; } </s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .

ARM ARM ARMCC::CondCodes ARMCC::CondCodes 0 0 ARMCC::getOppositeCondition


<s> static bool noncall_uses_reg ( rtx reg , rtx_insn * insn , rtx * set ) { rtx pattern , reg2 ; * set = NULL_RTX ; reg2 = sfunc_uses_reg ( insn ) ; if ( reg2 && REGNO ( reg2 ) == REGNO ( reg ) ) { pattern = single_set ( insn ) ; if ( pattern && REG_P ( SET_DEST ( pattern ) ) && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) * set = pattern ; return false ; } if ( ! CALL_P ( insn ) ) { pattern = single_set ( insn ) ; if ( pattern && REG_P ( SET_DEST ( pattern ) ) && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) { rtx par , part ; int i ; * set = pattern ; par = PATTERN ( insn ) ; if ( GET_CODE ( par ) == PARALLEL ) for ( i = XVECLEN ( par , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( par , 0 , i ) ; if ( GET_CODE ( part ) != SET && reg_mentioned_p ( reg , part ) ) return true ; } return reg_mentioned_p ( reg , SET_SRC ( pattern ) ) ; } return true ; } pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { int i ; for ( i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) if ( reg_mentioned_p ( reg , XVECEXP ( pattern , 0 , i ) ) ) return true ; pattern = XVECEXP ( pattern , 0 , 0 ) ; } if ( GET_CODE ( pattern ) == SET ) { if ( reg_mentioned_p ( reg , SET_DEST ( pattern ) ) ) { if ( ! REG_P ( SET_DEST ( pattern ) ) || REGNO ( reg ) != REGNO ( SET_DEST ( pattern ) ) ) return true ; * set = pattern ; } pattern = SET_SRC ( pattern ) ; } if ( GET_CODE ( pattern ) != CALL || ! MEM_P ( XEXP ( pattern , 0 ) ) || ! rtx_equal_p ( reg , XEXP ( XEXP ( pattern , 0 ) , 0 ) ) ) return true ; return false ; } </s>

See if the only way in which INSN uses REG is by calling it , or by setting it while calling it . Set * SET to a SET rtx if the register is set by INSN .


<s> bool forceScalarizeMaskedGather ( VectorType * VTy , Align Alignment ) { return true ; } </s>

Return true if the target forces scalarizing of llvm.masked.gather intrinsics .


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasSSE1
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
,
2
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool mem_locations_overlap ( rtx mem1 , rtx mem2 ) { rtx reg1 , reg2 ; HOST_WIDE_INT off1 , size1 , off2 , size2 ; if ( get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) ) return ( ( REGNO ( reg1 ) == REGNO ( reg2 ) ) && ( ( ( off1 <= off2 ) && ( off1 + size1 > off2 ) ) || ( ( off2 <= off1 ) && ( off2 + size2 > off1 ) ) ) ) ; return false ; } </s>

This function returns true if it can be determined that the two MEM locations overlap by at least 1 byte based on base reg/offset/size .


<s> const AArch64GNULDBackend & getTarget ( ) const { return m_Target ; } </s>

getTarget - Return the target machine this machine code is compiled with


<s> bool PPCExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; TII = static_cast < const PPCInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { MachineBasicBlock & MBB = * I ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , MBBE = MBB . end ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Changed |= expandMI ( MBB , MI , NMBBI ) ; MBBI = NMBBI ; } } if ( Changed ) MF . RenumberBlocks ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void setKind ( BaseKind K ) { Kind = K ; } </s>


<s> static void aarch64_restore_callee_saves ( machine_mode mode , poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { rtx base_rtx = stack_pointer_rtx ; unsigned regno ; unsigned regno2 ; poly_int64 offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; int offset_diff ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; offset_diff = cfun -> machine -> frame . reg_offset [ regno2 ] - cfun -> machine -> frame . reg_offset [ regno ] ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && known_eq ( GET_MODE_SIZE ( mode ) , offset_diff ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else emit_move_insn ( reg , mem ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s>
bool
X86TargetMachine
::
isNoopAddrSpaceCast
(
unsigned
SrcAS
,
unsigned
DestAS
)
const
{
assert
(
SrcAS
!=
DestAS
&&
"Expected different address spaces!"
)
;
if
(
getPointerSize
(
SrcAS
)
!=
getPointerSize
(
DestAS
)
)
return
false
;
return
SrcAS
<
256
&&
DestAS
<
256
;
}
</s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> bool mips_pad_reg_upward ( enum machine_mode mode , tree type ) { if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_pad_arg_upward ( mode , type ) ; } </s>

Likewise BLOCK_REG_PADDING ( MODE , TYPE , ... ) . Return ! BYTES_BIG_ENDIAN if the least significant byte of the register has useful data . Return the opposite if the most significant byte does .


<s> void or1k_expand_eh_return ( rtx eh_addr ) { rtx lraddr ; lraddr = gen_frame_mem ( Pmode , plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ) ; MEM_VOLATILE_P ( lraddr ) = true ; emit_move_insn ( lraddr , eh_addr ) ; } </s>

Expand the `` eh_return '' pattern . Used for defining __builtin_eh_return , this will emit RTX to override the current function 's return address stored on the stack . The emitted RTX is inserted before the epilogue so we ca n't just update the link register . This is used when handling exceptions to jump into the exception handler catch block upon return from _Unwind_RaiseException .


<s> bool PPCSubtarget :: useAA ( ) const { return needsAggressiveScheduling ( DarwinDirective ) ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Result = decodeInstruction ( DecoderTableMips32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>


<s>
bool
dump_insn_list
(
const
rtx
&
t
,
const
insn_info_list_t
&
insn_info
,
void
*
unused
ATTRIBUTE_UNUSED
)
{
gcc_assert
(
dump_file
)
;
fprintf
(
dump_file
,
"Tag 0x%lx ::\n"
,
INTVAL
(
t
)
)
;
for
(
unsigned
i
=
0
;
i
<
insn_info
.
length
(
)
;
i
++
)
dump_insn_slim
(
dump_file
,
insn_info
[
i
]
->
insn
)
;
fprintf
(
dump_file
,
"\n"
)
;
return
true
;
}
</s>

Callback invoked for each name-value pair ( T , INSN_INFO ) to dump the insn list INSN_INFO for tag T .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool ARMConstantPoolValue :: hasSameValue ( ARMConstantPoolValue * ACPV ) { if ( ACPV -> Kind == Kind && ACPV -> PCAdjust == PCAdjust && ACPV -> Modifier == Modifier && ACPV -> LabelId == LabelId && ACPV -> AddCurrentAddress == AddCurrentAddress ) { if ( Kind == ARMCP :: CPValue || Kind == ARMCP :: CPExtSymbol ) return true ; } return false ; } </s>

hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as another ARM constpool value .

ARM ARM ARM ARMCP::CPValue ARMCP::CPExtSymbol


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> int AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"\nrs6000_address_cost, return = %d, speed = %s, x:\n"

Debug form of ADDRESS_COST that is selected if -mdebug=cost .


<s> virtual const TeeRISCSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
Register
LanaiTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
,
const
MachineFunction
&
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"pc"
,
Lanai
::
PC
)
.
Case
(
"sp"
,
Lanai
::
SP
)
.
Case
(
"fp"
,
Lanai
::
FP
)
.
Case
(
"rr1"
,
Lanai
::
RR1
)
.
Case
(
"r10"
,
Lanai
::
R10
)
.
Case
(
"rr2"
,
Lanai
::
RR2
)
.
Case
(
"r11"
,
Lanai
::
R11
)
.
Case
(
"rca"
,
Lanai
::
RCA
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s> int mmix_eh_return_data_regno ( int n ) { if ( n >= 0 && n < 4 ) return MMIX_EH_RETURN_DATA_REGNO_START + n ; return INVALID_REGNUM ; } </s>


<s> rtx aarch64_stack_protect_canary_mem ( machine_mode mode , rtx decl_rtl , aarch64_salt_type salt_type ) { rtx addr ; if ( aarch64_stack_protector_guard == SSP_GLOBAL ) { gcc_assert ( MEM_P ( decl_rtl ) ) ; addr = XEXP ( decl_rtl , 0 ) ; poly_int64 offset ; rtx base = strip_offset_and_salt ( addr , & offset ) ; if ( ! SYMBOL_REF_P ( base ) ) return decl_rtl ; rtvec v = gen_rtvec ( 2 , base , GEN_INT ( salt_type ) ) ; addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_SALT_ADDR ) ; addr = gen_rtx_CONST ( Pmode , addr ) ; addr = plus_constant ( Pmode , addr , offset ) ; } else { rtx salt = GEN_INT ( salt_type ) ; addr = gen_reg_rtx ( mode ) ; if ( mode == DImode ) emit_insn ( gen_reg_stack_protect_address_di ( addr , salt ) ) ; else { emit_insn ( gen_reg_stack_protect_address_si ( addr , salt ) ) ; addr = convert_memory_address ( Pmode , addr ) ; } addr = plus_constant ( Pmode , addr , aarch64_stack_protector_guard_offset ) ; } return gen_rtx_MEM ( mode , force_reg ( Pmode , addr ) ) ; } </s>

Return the MEM rtx that provides the canary value that should be used for stack-smashing protection . MODE is the mode of the memory . For SSP_GLOBAL , DECL_RTL is the MEM rtx for the canary variable ( __stack_chk_guard ) , otherwise it has no useful value . SALT_TYPE indicates whether the caller is performing a SET or a TEST operation .


<s> rtx aarch64_final_eh_return_addr ( void ) { HOST_WIDE_INT fp_offset ; aarch64_layout_frame ( ) ; fp_offset = cfun -> machine -> frame . frame_size - cfun -> machine -> frame . hard_fp_offset ; if ( cfun -> machine -> frame . reg_offset [ LR_REGNUM ] < 0 ) return gen_rtx_REG ( DImode , LR_REGNUM ) ; if ( frame_pointer_needed ) { if ( fp_offset ) return gen_frame_mem ( DImode , plus_constant ( Pmode , hard_frame_pointer_rtx , UNITS_PER_WORD ) ) ; else return gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , UNITS_PER_WORD ) ) ; } return gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , fp_offset + cfun -> machine -> frame . saved_regs_size - 2 * UNITS_PER_WORD ) ) ; } </s>

Return the place to copy the exception unwinding return address to . This will probably be a stack slot , but could ( in theory be the return register ) .


<s>
SDValue
SystemZTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .

SystemZ
SystemZ
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s>
void
MipsRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
->
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
->
getObjectOffset
(
FrameIndex
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

Mips
Mips
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"


<s>
bool
Emitter
<
CodeEmitter
>
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DEBUG
(
dbgs
(
)
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx ia64_gen_spec_load ( rtx insn , ds_t ts , int mode_no ) { rtx pat , new_pat ; gen_func_t gen_load ; gen_load = get_spec_load_gen_function ( ts , mode_no ) ; new_pat = gen_load ( copy_rtx ( recog_data . operand [ 0 ] ) , copy_rtx ( recog_data . operand [ 1 ] ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == COND_EXEC ) new_pat = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( COND_EXEC_TEST ( pat ) ) , new_pat ) ; return new_pat ; } </s>

If GEN_P is true , calculate the index of needed speculation check and return speculative pattern for INSN with speculative mode TS , machine mode MODE_NO and with ZERO_EXTEND ( if EXTEND_P is true ) . If GEN_P is false , just calculate the index of needed speculation check .


<s> static rtx loongarch_got_load_tls_le ( rtx dest , rtx sym ) { return gen_got_load_tls_le ( Pmode , dest , sym ) ; } </s>

Add in the thread pointer for a TLS LE access .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK2
:
\
case
TYPE_VK4
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
case
TYPE_VK32
:
\
case
TYPE_VK64
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
assert
(
0
&&
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .

Mips
0
"RelaxInstruction() unimplemented"


<s> void tool_cleanup ( bool from_signal ATTRIBUTE_UNUSED ) { for ( int i = 0 ; i < num_temps ; i ++ ) maybe_unlink ( temp_files [ i ] ) ; } </s>


<s> static void mips_avoid_hazard ( rtx after , rtx insn , int * hilo_delay , rtx * delayed_reg , rtx lo_reg ) { rtx pattern , set ; int nops , ninsns ; if ( ! INSN_P ( insn ) ) return ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == ASM_INPUT || asm_noperands ( pattern ) >= 0 ) cfun -> machine -> all_noreorder_p = false ; ninsns = get_attr_length ( insn ) / 4 ; if ( ninsns == 0 ) return ; if ( * hilo_delay < 2 && reg_set_p ( lo_reg , pattern ) ) nops = 2 - * hilo_delay ; else if ( * delayed_reg != 0 && reg_referenced_p ( * delayed_reg , pattern ) ) nops = 1 ; else nops = 0 ; * hilo_delay += nops ; while ( nops -- > 0 ) emit_insn_after ( gen_hazard_nop ( ) , after ) ; * hilo_delay += ninsns ; * delayed_reg = 0 ; if ( INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_HILO : * hilo_delay = 0 ; break ; case HAZARD_DELAY : set = single_set ( insn ) ; gcc_assert ( set != 0 ) ; * delayed_reg = SET_DEST ( set ) ; break ; } } </s>

Subroutine of mips_reorg . If there is a hazard between INSN and a previous instruction , avoid it by inserting nops after instruction AFTER . * DELAYED_REG and * HILO_DELAY describe the hazards that apply at this point . If * DELAYED_REG is non-null , INSN must wait a cycle before using the value of that register . * HILO_DELAY counts the number of instructions since the last hilo hazard ( that is , the number of instructions since the last mflo or mfhi ) . After inserting nops for INSN , update * DELAYED_REG and * HILO_DELAY for the next instruction . LO_REG is an rtx for the LO register , used in dependence checking .


<s> static void sparc_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { rtx g1 = gen_rtx_REG ( Pmode , 1 ) ; if ( size <= PROBE_INTERVAL ) { emit_move_insn ( g1 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , g1 , - size ) ) ; } else if ( size <= 4 * PROBE_INTERVAL ) { HOST_WIDE_INT i ; emit_move_insn ( g1 , GEN_INT ( first + PROBE_INTERVAL ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_stack_probe ( g1 ) ; for ( i = 2 * PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { emit_insn ( gen_rtx_SET ( g1 , plus_constant ( Pmode , g1 , - PROBE_INTERVAL ) ) ) ; emit_stack_probe ( g1 ) ; } emit_stack_probe ( plus_constant ( Pmode , g1 , ( i - PROBE_INTERVAL ) - size ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx g4 = gen_rtx_REG ( Pmode , 4 ) ; emit_move_insn ( g1 , GEN_INT ( first ) ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_move_insn ( g4 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( g1 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , g1 ) ) ) ; emit_insn ( gen_rtx_SET ( g4 , gen_rtx_MINUS ( Pmode , g1 , g4 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , g1 , g1 , g4 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , g4 , rounded_size - size ) ) ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer . Note that we do n't use the REG+REG addressing mode for the probes because of the stack bias in 64-bit mode . And it does n't really buy us anything so the advantages of having a single code win here .


<s>
unsigned
AArch64TTIImpl
::
getGatherScatterOpCost
(
unsigned
Opcode
,
Type
*
DataTy
,
const
Value
*
Ptr
,
bool
VariableMask
,
Align
Alignment
,
TTI
::
TargetCostKind
CostKind
,
const
Instruction
*
I
)
{
if
(
!
isa
<
ScalableVectorType
>
(
DataTy
)
)
return
BaseT
::
getGatherScatterOpCost
(
Opcode
,
DataTy
,
Ptr
,
VariableMask
,
Alignment
,
CostKind
,
I
)
;
auto
*
VT
=
cast
<
VectorType
>
(
DataTy
)
;
auto
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
DataTy
)
;
ElementCount
LegalVF
=
LT
.
second
.
getVectorElementCount
(
)
;
Optional
<
unsigned
>
MaxNumVScale
=
getMaxVScale
(
)
;
assert
(
MaxNumVScale
&&
"Expected valid max vscale value"
)
;
unsigned
MemOpCost
=
getMemoryOpCost
(
Opcode
,
VT
->
getElementType
(
)
,
Alignment
,
0
,
CostKind
,
I
)
;
unsigned
MaxNumElementsPerGather
=
MaxNumVScale
.
getValue
(
)
*
LegalVF
.
getKnownMinValue
(
)
;
return
LT
.
first
*
MaxNumElementsPerGather
*
MemOpCost
;
}
</s>

Calculate the cost of Gather / Scatter operation .


<s> const char * arithmetic_instr ( rtx op , int shift_first_arg ) { switch ( GET_CODE ( op ) ) { case PLUS : return "add" ; case MINUS : return shift_first_arg ? "rsb" : "sub" ; case IOR : return "orr" ; case XOR : return "eor" ; case AND : return "and" ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : case ROTATERT : return arm_shift_nmem ( GET_CODE ( op ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return the appropriate ARM instruction for the operation code . The returned result should not be overwritten . OP is the rtx of the operation . SHIFT_FIRST_ARG is TRUE if the first argument of the operator was shifted .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; const TargetFrameLowering * TFI = TM -> getFrameLowering ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; X86MachineFunctionInfo * FuncInfo = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned StackAlignment = TFI -> getStackAlignment ( ) ; for ( unsigned i = 0 , e = RI . getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( ( RI . getRegClass ( Reg ) -> getAlignment ( ) / 8 ) > StackAlignment ) { FuncInfo -> setForceFramePointer ( true ) ; return true ; } } return false ; } </s>


<s> static void push_csky_minipool_barrier ( rtx_insn * insn , HOST_WIDE_INT address ) { Mfix * fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * fix ) ) ; fix -> insn = insn ; fix -> address = address ; fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail -> next = fix ; else minipool_fix_head = fix ; minipool_fix_tail = fix ; } </s>

Record that there is a natural barrier in the insn stream at ADDRESS .


<s> int ARMTTIImpl :: getIntImmCodeSizeCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( Imm . isNonNegative ( ) && Imm . getLimitedValue ( ) < 256 ) return 0 ; return 1 ; } </s>

Return the expected cost for the given integer when optimising for size .


<s> MCObjectWriter * OR1KAsmBackend :: createObjectWriter ( raw_ostream & OS ) const { return createOR1KELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> unsigned PPCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( ! Subtarget . isPPC64 ( ) ) return TFI -> hasFP ( MF ) ? PPC :: R31 : PPC :: R1 ; else return TFI -> hasFP ( MF ) ? PPC :: X31 : PPC :: X1 ; } </s>


<s>
static
rtx
arm_expand_vfp_builtin
(
int
fcode
,
tree
exp
,
rtx
target
)
{
if
(
fcode
>=
ARM_BUILTIN_VFP_BASE
&&
!
TARGET_HARD_FLOAT
)
{
fatal_error
(
input_location
,
"You must enable VFP instructions"
" to use these intrinsics."
)
;
return
const0_rtx
;
}
arm_builtin_datum
*
d
=
&
vfp_builtin_data
[
fcode
ARM_BUILTIN_VFP_PATTERN_START
]
;
return
arm_expand_builtin_1
(
fcode
,
exp
,
target
,
d
)
;
}
</s>

Expand a VFP builtin . These builtins are treated like neon builtins except that the data is looked up in table VFP_BUILTIN_DATA .

arm
"You must enable VFP instructions"
" to use these intrinsics."


<s>
const
MCFixupKindInfo
&
DLXAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
static
const
MCFixupKindInfo
Infos
[
DLX
::
NumTargetFixupKinds
]
=
{
{
"FIXUP_DLX_NONE"
,
0
,
32
,
0
}
,
{
"FIXUP_DLX_21"
,
16
,
16
,
0
}
,
{
"FIXUP_DLX_21_F"
,
16
,
16
,
0
}
,
{
"FIXUP_DLX_25"
,
7
,
25
,
0
}
,
{
"FIXUP_DLX_32"
,
0
,
32
,
0
}
,
{
"FIXUP_DLX_HI16"
,
16
,
16
,
0
}
,
{
"FIXUP_DLX_LO16"
,
16
,
16
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM MVE VPT Optimisation Pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
void
CSKYDAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
SDLoc
Dl
(
N
)
;
unsigned
Opcode
=
N
->
getOpcode
(
)
;
bool
IsSelected
=
false
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
ADDCARRY
:
IsSelected
=
selectAddCarry
(
N
)
;
break
;
case
ISD
::
SUBCARRY
:
IsSelected
=
selectSubCarry
(
N
)
;
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
{
Register
GP
=
Subtarget
->
getInstrInfo
(
)
->
getGlobalBaseReg
(
*
MF
)
;
ReplaceNode
(
N
,
CurDAG
->
getRegister
(
GP
,
N
->
getValueType
(
0
)
)
.
getNode
(
)
)
;
IsSelected
=
true
;
break
;
}
case
ISD
::
FrameIndex
:
{
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
Dl
,
MVT
::
i32
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
N
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i32
)
;
ReplaceNode
(
N
,
CurDAG
->
getMachineNode
(
Subtarget
->
hasE2
(
)
CSKY
::
ADDI32
:
CSKY
::
ADDI16XZ
,
Dl
,
MVT
::
i32
,
TFI
,
Imm
)
)
;
IsSelected
=
true
;
break
;
}
case
CSKYISD
::
BITCAST_TO_LOHI
:
IsSelected
=
selectBITCAST_TO_LOHI
(
N
)
;
break
;
case
ISD
::
INLINEASM
:
case
ISD
::
INLINEASM_BR
:
IsSelected
=
selectInlineAsm
(
N
)
;
break
;
}
if
(
IsSelected
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static inline int and_xor_ior_costs ( rtx x , int code ) { const int cost_scale = ! TARGET_SHMEDIA && GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 * cost_scale ; int i = INTVAL ( XEXP ( x , 1 ) ) ; if ( TARGET_SHMEDIA ) { if ( satisfies_constraint_I10 ( XEXP ( x , 1 ) ) || satisfies_constraint_J16 ( XEXP ( x , 1 ) ) ) return 1 ; else return 1 + rtx_cost ( XEXP ( x , 1 ) , GET_MODE ( x ) , AND , 1 , ! optimize_size ) ; } if ( ( i == 0xff || i == 0xffff ) && code == AND ) return 1 * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return 2 * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return 2 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an AND/XOR/IOR operation .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> rtx function_arg ( const struct sparc_args * cum , enum machine_mode mode , tree type , int named , int incoming_p ) { int regbase = ( incoming_p ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno , regno , padding ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; rtx reg ; slotno = function_arg_slotno ( cum , mode , type , named , incoming_p , & regno , & padding ) ; if ( slotno == - 1 ) return 0 ; if ( TARGET_ARCH32 ) { reg = gen_rtx_REG ( mode , regno ) ; return reg ; } if ( type && TREE_CODE ( type ) == RECORD_TYPE ) { gcc_assert ( int_size_in_bytes ( type ) <= 16 ) ; return function_arg_record_value ( type , mode , slotno , named , regbase ) ; } else if ( type && TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; return function_arg_union_value ( size , mode , slotno , regno ) ; } else if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 16 ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , TYPE_MODE ( TREE_TYPE ( type ) ) , SPARC_FP_ARG_FIRST + 2 * slotno ) ; else mclass = MODE_FLOAT ; } if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) { if ( ( regno - SPARC_FP_ARG_FIRST ) >= SPARC_INT_ARG_MAX * 2 ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ) ) ; else return reg ; } else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * 2 ) { int intreg ; if ( incoming_p ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / 2 ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , v0 , v1 ) ) ; } } } else { reg = gen_rtx_REG ( mode , regno ) ; } return reg ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s> int arm_coproc_mem_operand_no_writeback ( rtx op ) { return arm_coproc_mem_operand_wb ( op , 0 ) ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern in a context in which no writeback address modes are allowed .


<s> const CSKYMCExpr * CSKYMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) CSKYMCExpr ( Kind , Expr ) ; } </s>


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


"Only base registers and frame indices are supported."

"getMemOperandWithOffsetWidth return incorrect base op"

Returns true if the two given memory operations should be scheduled adjacent .


<s> void SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MachineInstr & MI = * I ; DebugLoc dl = MI . getDebugLoc ( ) ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; const SparcInstrInfo & TII = * static_cast < const SparcInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( Size ) BuildMI ( MBB , I , dl , TII . get ( SP :: ADDri ) , SP :: O6 ) . addReg ( SP :: O6 ) . addImm ( Size ) ; MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Sparc Sparc 0 SP::ADJCALLSTACKDOWN Sparc Sparc SP::ADDri SP::O6 SP::O6


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI -> definesRegister ( SystemZ :: CC ) ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( MI -> readsRegister ( SystemZ :: CC ) && CompleteCCUsers ) CCUsers . push_back ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ 4 SystemZ::CC SystemZ::CC


"Memory Tagging Extension does not support %<-mabi=ilp32%>"

"argument %d must be a constant immediate "

Expand an expression EXP that calls a MEMTAG built-in FCODE with result going to TARGET .


"\t>> Failed to rename destination in insn %d\n\t>>"

The actual reallocation logic . For each vector of collisions V , try to resolve the collision by attempting to rename the destination register of all but one of the loads . This is a callback that is invoked for each name-value pair ( T , V ) in TAG_MAP . The function returns true whenever it returns unchanged and false otherwise to halt traversal .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> const uint16_t * Cpu0RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ; } </s>


<s>
SDValue
X86TargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
Is64Bit
=
Subtarget
->
is64Bit
(
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_X86
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
EVT
CopyVT
=
VA
.
getValVT
(
)
;
if
(
(
CopyVT
==
MVT
::
f32
||
CopyVT
==
MVT
::
f64
)
&&
(
(
Is64Bit
||
Ins
[
i
]
.
Flags
.
isInReg
(
)
)
&&
!
Subtarget
->
hasXMM
(
)
)
)
{
report_fatal_error
(
"SSE register return with SSE disabled"
)
;
}
SDValue
Val
;
if
(
VA
.
getLocReg
(
)
==
X86
::
ST0
||
VA
.
getLocReg
(
)
==
X86
::
ST1
)
{
if
(
isScalarFPTypeInSSEReg
(
VA
.
getValVT
(
)
)
)
CopyVT
=
MVT
::
f80
;
SDValue
Ops
[
]
=
{
Chain
,
InFlag
}
;
Chain
=
SDValue
(
DAG
.
getMachineNode
(
X86
::
FpPOP_RETVAL
,
dl
,
CopyVT
,
MVT
::
Other
,
MVT
::
Glue
,
Ops
,
2
)
,
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
if
(
CopyVT
!=
VA
.
getValVT
(
)
)
Val
=
DAG
.
getNode
(
ISD
::
FP_ROUND
,
dl
,
VA
.
getValVT
(
)
,
Val
,
DAG
.
getIntPtrConstant
(
1
)
)
;
}
else
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
CopyVT
,
InFlag
)
.
getValue
(
1
)
;
Val
=
Chain
.
getValue
(
0
)
;
}
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> virtual const DLXRegisterInfo & getRegisterInfo ( ) const { return RegisterInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static std :: unique_ptr < MINA32Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < MINA32Operand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> bool PPCInstrInfo :: FoldImmediate ( MachineInstr & UseMI , MachineInstr & DefMI , Register Reg , MachineRegisterInfo * MRI ) const { bool Changed = onlyFoldImmediate ( UseMI , DefMI , Reg ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) DefMI . eraseFromParent ( ) ; return Changed ; } </s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> bool isConditionalBranch ( const MCInst & Inst ) const override { if ( Inst . getOpcode ( ) == ARM :: Bcc && Inst . getOperand ( 1 ) . getImm ( ) == ARMCC :: AL ) return false ; return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s> static rtx load_cr_save ( int regno , rtx frame_reg_rtx , int offset , bool exit_func ) { rtx mem = gen_frame_mem_offset ( SImode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx_insn * insn = emit_move_insn ( reg , mem ) ; if ( ! exit_func && DEFAULT_ABI == ABI_V4 ) { rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; rtx set = gen_rtx_SET ( VOIDmode , reg , cr ) ; add_reg_note ( insn , REG_CFA_REGISTER , set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return reg ; } </s>

Restoring cr is a two step process : loading a reg from the frame save , then moving the reg to cr . For ABI_V4 we must let the unwinder know that the stack location is no longer valid at or before the stack deallocation , but we ca n't emit a cfa_restore for cr at the stack deallocation like we do for other registers . The trouble is that it is possible for the move to cr to be scheduled after the stack deallocation . So say exactly where cr is located on each of the two insns .


<s> void PPCAIXAsmPrinter :: emitFunctionEntryLabel ( ) { if ( ! TM . getFunctionSections ( ) ) PPCAsmPrinter :: emitFunctionEntryLabel ( ) ; llvm :: for_each ( GOAliasMap [ & MF -> getFunction ( ) ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getObjFileLowering ( ) . getFunctionEntryPointSymbol ( Alias , TM ) ) ; } ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> const VETargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static int rs6000_use_sched_lookahead ( void ) { switch ( rs6000_cpu_attr ) { case CPU_PPC8540 : case CPU_PPC8548 : return 4 ; case CPU_CELL : return ( reload_completed ? 8 : 0 ) ; default : return 0 ; } } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool ix86_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( POINTER_BOUNDS_MODE_P ( GET_MODE ( x ) ) ) return false ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return false ; x = XEXP ( x , 0 ) ; } if ( TARGET_MACHO && darwin_local_data_pic ( x ) ) return true ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : return TARGET_64BIT ; case UNSPEC_TPOFF : case UNSPEC_NTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_DTPOFF : x = XVECEXP ( x , 0 , 0 ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) ; default : return false ; } if ( GET_CODE ( x ) == LABEL_REF ) return true ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; if ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P ( x ) ) return false ; if ( MACHO_DYNAMIC_NO_PIC_P ) return machopic_symbol_defined_p ( x ) ; if ( ix86_force_load_from_GOT_p ( x ) ) return false ; break ; CASE_CONST_SCALAR_INT : switch ( mode ) { case TImode : if ( TARGET_64BIT ) return true ; case OImode : case XImode : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } break ; case CONST_VECTOR : if ( ! standard_sse_constant_p ( x , mode ) ) return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> static void init_insn_group_barriers ( ) { memset ( rws_sum , 0 , sizeof ( rws_sum ) ) ; first_instruction = 1 ; } </s>

Clear out the state for group_barrier_needed_p at the start of a sequence of insns .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC


"getJumpTargetOpValue expects only expressions or an immediate"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> static rtx mips16e_save_restore_reg ( bool restore_p , bool reg_parm_p , HOST_WIDE_INT offset , unsigned int regno ) { rtx reg , mem ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( restore_p ) { mips_add_cfa_restore ( reg ) ; return gen_rtx_SET ( VOIDmode , reg , mem ) ; } if ( reg_parm_p ) return gen_rtx_SET ( VOIDmode , mem , reg ) ; return mips_frame_set ( mem , reg ) ; } </s>

Return a move between register REGNO and memory location SP + OFFSET . REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE . Make the move a load if RESTORE_P , otherwise make it a store .


<s> bool LC2200PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> static bool mips_hard_regno_mode_ok_uncached ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 2 == 0 ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 4 == 0 ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode && ! MSA_SUPPORTED_MODE_P ( mode ) ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && MSA_SUPPORTED_MODE_P ( mode ) ) return true ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == 0 || ( MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= 4 && ( regno & 1 ) != 0 ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & 1 ) != 0 ) ; if ( TARGET_LOONGSON_MMI && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * 2 ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * 2 && ( ( regno - DSP_ACC_REG_FIRST ) & 1 ) == 0 ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return mclass == MODE_INT && size <= UNITS_PER_WORD ; if ( regno == GOT_VERSION_REGNUM ) return mode == SImode ; return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in mips_hard_regno_mode_ok .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( getARMSubtarget ( ) . restrictIT ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; if ( ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( & IfConverterID ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


"instructions, but the target does not support ARM mode execution."

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> const MCPhysReg * PPCRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const PPCSubtarget & Subtarget = MF -> getSubtarget < PPCSubtarget > ( ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_SaveList ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_SaveList ; return CSR_64_AllRegs_SaveList ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . isPPC64 ( ) && MF -> getInfo < PPCFunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( PPC :: X2 ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) { if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList : CSR_SVR64_ColdCC_Altivec_SaveList ; return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList : CSR_SVR64_ColdCC_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR32_ColdCC_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR32_ColdCC_SPE_SaveList ; return CSR_SVR32_ColdCC_SaveList ; } if ( TM . isPPC64 ( ) ) { if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : CSR_SVR464_Altivec_SaveList ; return SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList ; } if ( Subtarget . hasAltivec ( ) ) return CSR_SVR432_Altivec_SaveList ; else if ( Subtarget . hasSPE ( ) ) return CSR_SVR432_SPE_SaveList ; return CSR_SVR432_SaveList ; } </s>

PowerPC PPC PPC PPC PPC PPC PPC PPC::X2 PPC PPC