<s> unsigned ARMFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


<s> static void ix86_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! ix86_use_pseudo_pic_reg ( ) ) return ; start_sequence ( ) ; if ( TARGET_64BIT ) { if ( ix86_cmodel == CM_LARGE_PIC ) ix86_init_large_pic_reg ( R11_REG ) ; else emit_insn ( gen_set_got_rex64 ( pic_offset_table_rtx ) ) ; } else { rtx reg = crtl -> profile ? gen_rtx_REG ( Pmode , REAL_PIC_OFFSET_TABLE_REGNUM ) : pic_offset_table_rtx ; rtx_insn * insn = emit_insn ( gen_set_got ( reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( crtl -> profile ) emit_move_insn ( pic_offset_table_rtx , reg ) ; add_reg_note ( insn , REG_CFA_FLUSH_QUEUE , NULL_RTX ) ; } seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>

Create and initialize PIC register if required .


<s> static bool indexable_address_p ( rtx xfoo0 , rtx xfoo1 , machine_mode mode , bool strict ) { if ( ! CONSTANT_ADDRESS_P ( xfoo0 ) ) return false ; if ( BASE_REGISTER_P ( xfoo1 , strict ) ) return ! flag_pic || mode == QImode ; if ( flag_pic && symbolic_operand ( xfoo0 , SImode ) ) return false ; return reg_plus_index_p ( xfoo1 , mode , strict ) ; } </s>

Return true if xfoo0 and xfoo1 constitute a valid indexed address .


<s> void ARMAsmPrinter :: emitInlineAsmEnd ( const MCSubtargetInfo & StartInfo , const MCSubtargetInfo * EndInfo ) const { const bool WasThumb = isThumb ( StartInfo ) ; if ( ! EndInfo || WasThumb != isThumb ( * EndInfo ) ) { OutStreamer . EmitAssemblerFlag ( WasThumb ? MCAF_Code16 : MCAF_Code32 ) ; } } </s>

Let the target do anything it needs to do after emitting inlineasm .


<s> unsigned int LC2200AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { return MCTargetAsmParser :: validateTargetOperandClass ( Op , Kind ) ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static bool mips_truly_noop_truncation ( poly_uint64 outprec , poly_uint64 inprec ) { return ! TARGET_64BIT || inprec <= 32 || outprec > 32 ; } </s>


<s> static bool mips_lx_address_p ( rtx addr , machine_mode mode ) { if ( GET_CODE ( addr ) != PLUS || ! REG_P ( XEXP ( addr , 0 ) ) || ! REG_P ( XEXP ( addr , 1 ) ) ) return false ; if ( ISA_HAS_LBX && mode == QImode ) return true ; if ( ISA_HAS_LHX && mode == HImode ) return true ; if ( ISA_HAS_LWX && mode == SImode ) return true ; if ( ISA_HAS_LDX && mode == DImode ) return true ; return false ; } </s>

Return true if ADDR matches the pattern for the L { B , H , W , D } { , U } X load indexed address instruction . Note that such addresses are not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense , because their use is so restricted .


<s> static const char * getOpcodeName ( unsigned Opcode ) { const char * Name = "<unknown>" ; switch ( Opcode ) { default : break ; case AArch64 :: B : Name = "AArch64::B" ; break ; case AArch64 :: Bcc : Name = "AArch64::Bcc" ; break ; case AArch64 :: BR : Name = "AArch64::BR" ; break ; case AArch64 :: BRAA : Name = "AArch64::BRAA" ; break ; case AArch64 :: BRAAZ : Name = "AArch64::BRAAZ" ; break ; case AArch64 :: BRAB : Name = "AArch64::BRAB" ; break ; case AArch64 :: BRABZ : Name = "AArch64::BRABZ" ; break ; case AArch64 :: BL : Name = "AArch64::BL" ; break ; case AArch64 :: BLR : Name = "AArch64::BLR" ; break ; case AArch64 :: BLRAA : Name = "AArch64::BLRAA" ; break ; case AArch64 :: BLRAAZ : Name = "AArch64::BLRAAZ" ; break ; case AArch64 :: BLRAB : Name = "AArch64::BLRAB" ; break ; case AArch64 :: BLRABZ : Name = "AArch64::BLRABZ" ; break ; case AArch64 :: CBZW : Name = "AArch64::CBZW" ; break ; case AArch64 :: CBZX : Name = "AArch64::CBZX" ; break ; case AArch64 :: CBNZW : Name = "AArch64::CBNZW" ; break ; case AArch64 :: CBNZX : Name = "AArch64::CBNZX" ; break ; case AArch64 :: CCMPWr : Name = "AArch64::CCMPWr" ; break ; case AArch64 :: CCMPXr : Name = "AArch64::CCMPXr" ; break ; case AArch64 :: G_FCMP : Name = "AArch64::G_FCMP" ; break ; case AArch64 :: G_ICMP : Name = "AArch64::G_ICMP" ; break ; case AArch64 :: TBZW : Name = "AArch64::TBZW" ; break ; case AArch64 :: TBZX : Name = "AArch64::TBZX" ; break ; case AArch64 :: TBNZW : Name = "AArch64::TBNZW" ; break ; case AArch64 :: TBNZX : Name = "AArch64::TBNZX" ; break ; case AArch64 :: RET : Name = "AArch64::RET" ; break ; case AArch64 :: RETAA : Name = "AArch64::RETAA" ; break ; case AArch64 :: RETAB : Name = "AArch64::RETAB" ; break ; case AArch64 :: SVC : Name = "AArch64::SVC" ; break ; } return Name ; } </s>

Return a string representation for an opcode .


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { enum machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) { tmp = if_true ; if_true = if_false ; if_false = tmp ; } else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || ! flag_unsafe_math_optimizations ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ; rtvec v ; if_true = force_reg ( mode , if_true ) ; v = gen_rtvec ( 2 , if_true , if_false ) ; tmp = gen_rtx_UNSPEC ( mode , v , u ) ; } else { code = is_min ? SMIN : SMAX ; tmp = gen_rtx_fmt_ee ( code , mode , if_true , if_false ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , tmp ) ) ; return true ; } </s>

Detect conditional moves that exactly match min/max operational semantics . Note that this is IEEE safe , as long as we do n't interchange the operands . Returns FALSE if this conditional move does n't match a MIN/MAX , and TRUE if the operation is successful and instructions are emitted .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Arg
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
AExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
ZExt
:
Arg
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
case
CCValAssign
::
SExt
:
Arg
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Arg
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Arg
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; else if ( ( StringRef ( constraint ) == "wa" || StringRef ( constraint ) == "wd" || StringRef ( constraint ) == "wf" ) && type -> isVectorTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "wi" && type -> isIntegerTy ( 64 ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ws" && type -> isDoubleTy ( ) ) return CW_Register ; else if ( StringRef ( constraint ) == "ww" && type -> isFloatTy ( ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .

PowerPC PPC "wc" 1 "wa" "wd" "wf" "wi" 64 "ws" "ww"


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; if ( FlagSfiBranch ) { NaclAlignAllJumpTargetsAndConstantPools ( MF ) ; } return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


"Legal fp imm: materialize 0 using the zero register\n"

Returns true if the target can instruction select the specified FP immediate natively .


";; %smode fixup for i%d; addr %lu, range (%ld,%ld): "

Record INSN , which will need fixing up to load a value from the minipool . ADDRESS is the offset of the insn since the start of the function ; LOC is a pointer to the part of the insn which requires fixing ; VALUE is the constant that must be loaded , which is of type MODE .


<s>
static
void
rs6000_print_options_internal
(
FILE
*
file
,
int
indent
,
const
char
*
string
,
HOST_WIDE_INT
flags
,
const
char
*
prefix
,
const
struct
rs6000_opt_mask
*
opts
,
size_t
num_elements
)
{
size_t
i
;
size_t
start_column
=
0
;
size_t
cur_column
;
size_t
max_column
=
120
;
size_t
prefix_len
=
strlen
(
prefix
)
;
size_t
comma_len
=
0
;
const
char
*
comma
=
""
;
if
(
indent
)
start_column
+=
fprintf
(
file
,
"%*s"
,
indent
,
""
)
;
if
(
!
flags
)
{
fprintf
(
stderr
,
DEBUG_FMT_S
,
string
,
"<none>"
)
;
return
;
}
start_column
+=
fprintf
(
stderr
,
DEBUG_FMT_WX
,
string
,
flags
)
;
cur_column
=
start_column
;
for
(
i
=
0
;
i
<
num_elements
;
i
++
)
{
bool
invert
=
opts
[
i
]
.
invert
;
const
char
*
name
=
opts
[
i
]
.
name
;
const
char
*
no_str
=
""
;
HOST_WIDE_INT
mask
=
opts
[
i
]
.
mask
;
size_t
len
=
comma_len
+
prefix_len
+
strlen
(
name
)
;
if
(
!
invert
)
{
if
(
(
flags
&
mask
)
==
0
)
{
no_str
=
"no-"
;
len
+=
sizeof
(
"no-"
)
1
;
}
flags
&=
~
mask
;
}
else
{
if
(
(
flags
&
mask
)
!=
0
)
{
no_str
=
"no-"
;
len
+=
sizeof
(
"no-"
)
1
;
}
flags
|=
mask
;
}
cur_column
+=
len
;
if
(
cur_column
>
max_column
)
{
fprintf
(
stderr
,
", \\\n%*s"
,
(
int
)
start_column
,
""
)
;
cur_column
=
start_column
+
len
;
comma
=
""
;
}
fprintf
(
file
,
"%s%s%s%s"
,
comma
,
prefix
,
no_str
,
name
)
;
comma
=
", "
;
comma_len
=
sizeof
(
", "
)
1
;
}
fputs
(
"\n"
,
file
)
;
}
</s>

Helper function to print the current isa or misc options on a line .


<s> bool X86TargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f16 : return Subtarget . hasFP16 ( ) ; case MVT :: f32 : case MVT :: f64 : return true ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> int nds32_can_use_bitci_p ( int ival ) { return ( TARGET_ISA_V3 && ( ival < 0 ) && satisfies_constraint_Iu15 ( gen_int_mode ( ~ ival , SImode ) ) ) ; } </s>

Function to check if 'bitci ' instruction can be used with IVAL .


<s> static unsigned HOST_WIDE_INT mips_asan_shadow_offset ( void ) { if ( mips_abi == ABI_N32 ) return ( HOST_WIDE_INT_1 << 29 ) ; if ( POINTER_SIZE == 64 ) return ( HOST_WIDE_INT_1 << 37 ) ; else return HOST_WIDE_INT_C ( 0x0aaa0000 ) ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> bool PPCFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , true ) ; } </s>

Check whether or not the given MBB can be used as a epilogue for the target .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8mr : case X86 :: MOV16mr : case X86 :: MOV32mr : case X86 :: MOV64mr : case X86 :: ST_FpP64m : case X86 :: MOVSSmr : case X86 :: MOVSDmr : case X86 :: MOVAPSmr : case X86 :: MOVAPDmr : case X86 :: MOVDQAmr : case X86 :: MMX_MOVD64mr : case X86 :: MMX_MOVQ64mr : case X86 :: MMX_MOVNTQmr : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 1 && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( X86AddrNumOperands ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
MF
=
&
Func
;
TM
=
&
MF
->
getTarget
(
)
;
TII
=
TM
->
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

X86
"Start X86FixupLEAs\n"
"End X86FixupLEAs\n"


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"NEON register pre-allocation pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"attribute %<target%> argument not a string"

"invalid fpu for attribute(target(\"%s\"))"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> Register OutgoingValueHandler :: getStackAddress ( const CCValAssign & VA , MachineMemOperand * & MMO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( Mips :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; unsigned Offset = VA . getLocMemOffset ( ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , 8 ) / 8 ; unsigned Align = MinAlign ( TFL -> getStackAlignment ( ) , Offset ) ; MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , Align ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const OR1KTargetMachine & getTargetMachine ( ) { return static_cast < const OR1KTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , ARMProcClass ( None ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( ARM_ABI_UNKNOWN ) { initializeEnvironment ( ) ; resetSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool sh_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { return ( 1 && ( ! TARGET_SHCOMPACT || crtl -> args . info . stack_regs == 0 ) && ! sh_cfun_interrupt_handler_p ( ) && ( ! flag_pic || TARGET_FDPIC || ( decl && ! ( TREE_PUBLIC ( decl ) || DECL_WEAK ( decl ) ) ) || ( decl && DECL_VISIBILITY ( decl ) != VISIBILITY_DEFAULT ) ) ) ; } </s>

If PIC , we can not make sibling calls to global functions because the PLT requires r12 to be live .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
InfosBE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
6
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
16
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
const
static
MCFixupKindInfo
InfosLE
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
2
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
2
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_br24abs"
,
2
,
24
,
0
}
,
{
"fixup_ppc_brcond14abs"
,
2
,
14
,
0
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
2
,
14
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
(
IsLittleEndian
InfosLE
:
InfosBE
)
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void TeeRISCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TeeRISCInstrInfo & TII = * static_cast < const TeeRISCInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; int Amount = Old -> getOperand ( 0 ) . getImm ( ) + 4 ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == TeeRISC :: ADJCALLSTACKDOWN ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( TeeRISC :: ADD_IMM ) , TeeRISC :: SP ) . addReg ( TeeRISC :: SP ) . addImm ( - Amount ) ; } else { assert ( Old -> getOpcode ( ) == TeeRISC :: ADJCALLSTACKUP ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( TeeRISC :: ADD_IMM ) , TeeRISC :: SP ) . addReg ( TeeRISC :: SP ) . addImm ( Amount ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMachObjectWriter ( OS , true , object :: mach :: CTM_x86_64 , object :: mach :: CSX86_ALL , true ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
KnownBits
&
Known
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
KnownBits
Known2
;
Known
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Depth
+
1
)
;
Known2
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
Depth
+
1
)
;
Known
=
KnownBits
::
commonBits
(
Known
,
Known2
)
;
break
;
}
case
AArch64ISD
::
LOADgot
:
case
AArch64ISD
::
ADDlow
:
{
if
(
!
Subtarget
->
isTargetILP32
(
)
)
break
;
Known
.
Zero
=
APInt
::
getHighBitsSet
(
64
,
32
)
;
break
;
}
case
AArch64ISD
::
ASSERT_ZEXT_BOOL
:
{
Known
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Depth
+
1
)
;
Known
.
Zero
|=
APInt
(
Known
.
getBitWidth
(
)
,
0xFE
)
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
Known
.
Zero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
Known
.
Zero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
Known
.
Zero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> unsigned getNumFixupKinds ( ) const override { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s> bool MipsPassConfig :: addInstSelector ( ) { addPass ( createMipsModuleISelDagPass ( getMipsTargetMachine ( ) ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) , getOptLevel ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const X86TargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned LEGInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( MBB . empty ( ) ) return 0 ; unsigned NumRemoved = 0 ; auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I -> getOpcode ( ) ; if ( ( Opc == LEG :: B ) || ( Opc == LEG :: Bcc ) ) { auto ToDelete = I ; ++ I ; MBB . erase ( ToDelete ) ; NumRemoved ++ ; } } while ( I != MBB . begin ( ) ) ; return NumRemoved ; } </s>

Remove the branching code at the end of the specific MBB .


Before rtl epilogue has been expanded , this function is used .


<s> static void moxie_compute_frame ( void ) { int stack_alignment = STACK_BOUNDARY / BITS_PER_UNIT ; int padding_locals ; int regno ; cfun -> machine -> local_vars_size = get_frame_size ( ) ; padding_locals = cfun -> machine -> local_vars_size % stack_alignment ; if ( padding_locals ) padding_locals = stack_alignment - padding_locals ; cfun -> machine -> local_vars_size += padding_locals ; cfun -> machine -> callee_saved_reg_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += 4 ; cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; } </s>

Compute the size of the local area and the size to be adjusted by the * prologue and epilogue .


<s> void timode_scalar_chain :: fix_debug_reg_uses ( rtx reg ) { if ( ! flag_var_tracking ) return ; df_ref ref , next ; for ( ref = DF_REG_USE_CHAIN ( REGNO ( reg ) ) ; ref ; ref = next ) { rtx_insn * insn = DF_REF_INSN ( ref ) ; next = DF_REF_NEXT_REG ( ref ) ; while ( next && DF_REF_INSN ( next ) == insn ) next = DF_REF_NEXT_REG ( next ) ; if ( DEBUG_INSN_P ( insn ) ) { bool changed = false ; for ( ; ref != next ; ref = DF_REF_NEXT_REG ( ref ) ) { rtx * loc = DF_REF_LOC ( ref ) ; if ( REG_P ( * loc ) && GET_MODE ( * loc ) == V1TImode ) { * loc = gen_rtx_SUBREG ( TImode , * loc , 0 ) ; changed = true ; } } if ( changed ) df_insn_rescan ( insn ) ; } } } </s>

Fix uses of converted REG in debug insns .


<s> bool isCheapToSpeculateCttz ( ) const override { return true ; } </s>

Return true if it is cheap to speculate a call to intrinsic cttz .


<s> static bool ia64_libgcc_floating_mode_supported_p ( machine_mode mode ) { switch ( mode ) { case SFmode : case DFmode : return true ; case XFmode : return false ; return true ; case TFmode : return false ; return true ; default : return false ; } } </s>


<s>
bool
WaitInsert
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
MF
.
getFunction
(
)
.
hasFnAttribute
(
Attribute
::
StrictFP
)
)
return
false
;
const
X86Subtarget
&
ST
=
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
const
X86InstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
Changed
=
false
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MBB
.
begin
(
)
;
MI
!=
MBB
.
end
(
)
;
++
MI
)
{
if
(
!
X86
::
isX87Instruction
(
*
MI
)
)
continue
;
if
(
!
(
MI
->
mayRaiseFPException
(
)
||
MI
->
mayLoadOrStore
(
)
)
||
isX87ControlInstruction
(
*
MI
)
)
continue
;
MachineBasicBlock
::
iterator
AfterMI
=
std
::
next
(
MI
)
;
if
(
AfterMI
!=
MBB
.
end
(
)
&&
X86
::
isX87Instruction
(
*
AfterMI
)
&&
!
isX87NonWaitingControlInstruction
(
*
AfterMI
)
)
continue
;
BuildMI
(
MBB
,
AfterMI
,
MI
->
getDebugLoc
(
)
,
TII
->
get
(
X86
::
WAIT
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"\nInsert wait after:\t"
<<
*
MI
)
;
++
MI
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool splitFramePushPop ( const MachineFunction & MF ) const { return ( getFramePointerReg ( ) == ARM :: R7 && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ; } </s>

Returns true if the frame setup is split into two separate pushes ( first r0-r7 , lr then r8-r11 ) , principally so that the frame pointer is adjacent to lr .


<s> void ARMPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( - 1 , [ this ] ( const Function & F ) { const auto & ST = this -> TM -> getSubtarget < ARMSubtarget > ( F ) ; return ST . hasAnyDataBarrier ( ) && ! ST . isThumb1Only ( ) ; } ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int ARMTTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( ~ Imm , Ty ) ) ; if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty ) , getIntImmCost ( - Imm , Ty ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } return getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s>
static
void
nds32_emit_section_head_template
(
char
section_name
[
]
,
char
symbol_name
[
]
,
int
align_value
,
bool
object_p
)
{
const
char
*
flags_str
;
const
char
*
type_str
;
flags_str
=
(
object_p
)
"\"a\""
:
"\"ax\""
;
type_str
=
(
object_p
)
"@object"
:
"@function"
;
fprintf
(
asm_out_file
,
"\t.section\t%s, %s\n"
,
section_name
,
flags_str
)
;
fprintf
(
asm_out_file
,
"\t.align\t%d\n"
,
align_value
)
;
fprintf
(
asm_out_file
,
"\t.global\t%s\n"
,
symbol_name
)
;
fprintf
(
asm_out_file
,
"\t.type\t%s, %s\n"
,
symbol_name
,
type_str
)
;
fprintf
(
asm_out_file
,
"%s:\n"
,
symbol_name
)
;
}
</s>

A helper function to emit section head template .


<s> virtual void emitSparcRegisterIgnore ( unsigned reg ) { } </s>

Emit `` .register < reg > , # ignore '' .


<s> static pad_direction mips_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return PAD_UPWARD ; if ( type != 0 ? ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || FIXED_POINT_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) ) return PAD_DOWNWARD ; if ( mips_abi == ABI_O64 ) if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return PAD_DOWNWARD ; if ( mips_abi != ABI_EABI ) return PAD_UPWARD ; if ( mode != BLKmode ? GET_MODE_BITSIZE ( mode ) >= PARM_BOUNDARY : int_size_in_bytes ( type ) >= ( PARM_BOUNDARY / BITS_PER_UNIT ) ) return PAD_UPWARD ; return PAD_DOWNWARD ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING ; return PAD_UPWARD if the first byte of the stack slot has useful data , PAD_DOWNWARD if the last byte does .


<s> Optional < ExtAddrMode > AArch64InstrInfo :: getAddrModeFromMemoryOp ( const MachineInstr & MemI , const TargetRegisterInfo * TRI ) const { const MachineOperand * Base ; int64_t Offset ; bool OffsetIsScalable ; if ( ! getMemOperandWithOffset ( MemI , Base , Offset , OffsetIsScalable , TRI ) ) return None ; if ( ! Base -> isReg ( ) ) return None ; ExtAddrMode AM ; AM . BaseReg = Base -> getReg ( ) ; AM . Displacement = Offset ; AM . ScaledReg = 0 ; return AM ; } </s>

Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory .


<s> static void arm_init_neon_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_NEON_PATTERN_START ; arm_init_simd_builtin_types ( ) ; arm_init_simd_builtin_scalar_types ( ) ; tree lane_check_fpr = build_function_type_list ( void_type_node , intSI_type_node , intSI_type_node , NULL ) ; arm_builtin_decls [ ARM_BUILTIN_NEON_LANE_CHECK ] = add_builtin_function ( "__builtin_arm_lane_check" , lane_check_fpr , ARM_BUILTIN_NEON_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = 0 ; i < ARRAY_SIZE ( neon_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & neon_builtin_data [ i ] ; arm_init_builtin ( fcode , d , "__builtin_neon" ) ; } } </s>

Set up all the NEON builtins , even builtins for instructions that are not in the current target ISA to allow the user to compile particular modules with different target specific options that differ from the command line options . Such builtins will be rejected in arm_expand_builtin .


<s>
void
MipsInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Mips
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Mips
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
ADDu
,
ZeroReg
=
Mips
::
ZERO
;
else
if
(
Mips
::
CCRRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
CFC1
;
else
if
(
Mips
::
FGR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MFC1
;
else
if
(
SrcReg
==
Mips
::
HI
)
Opc
=
Mips
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Mips
::
LO
)
Opc
=
Mips
::
MFLO
,
SrcReg
=
0
;
}
else
if
(
Mips
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
Mips
::
CCRRegClass
.
contains
(
DestReg
)
)
Opc
=
Mips
::
CTC1
;
else
if
(
Mips
::
FGR32RegClass
.
contains
(
DestReg
)
)
Opc
=
Mips
::
MTC1
;
else
if
(
DestReg
==
Mips
::
HI
)
Opc
=
Mips
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Mips
::
LO
)
Opc
=
Mips
::
MTLO
,
DestReg
=
0
;
}
else
if
(
Mips
::
FGR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
Mips
::
FMOV_S
;
else
if
(
Mips
::
AFGR64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
Mips
::
FMOV_D32
;
else
if
(
Mips
::
CCRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
Opc
=
Mips
::
MOVCCRToCCR
;
else
if
(
Mips
::
CPU64RegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Mips
::
CPU64RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
DADDu
,
ZeroReg
=
Mips
::
ZERO_64
;
else
if
(
SrcReg
==
Mips
::
HI64
)
Opc
=
Mips
::
MFHI64
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Mips
::
LO64
)
Opc
=
Mips
::
MFLO64
,
SrcReg
=
0
;
}
else
if
(
Mips
::
CPU64RegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Mips
::
HI64
)
Opc
=
Mips
::
MTHI64
,
DestReg
=
0
;
else
if
(
DestReg
==
Mips
::
LO64
)
Opc
=
Mips
::
MTLO64
,
DestReg
=
0
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


"getJumpTargetOpValue expects only expressions"

"unexpect opcode in getJumpAbsoluteTargetOpValue()"

getJumpTargetOpValue - Return binary encoding of the jump target operand .


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > SplitArgInfos ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArgInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArgInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArgInfo , SplitArgInfos , MF ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgInfos , ArgHandler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static SDValue WidenVector ( SDValue V64Reg , SelectionDAG & DAG ) { EVT VT = V64Reg . getValueType ( ) ; unsigned NarrowSize = VT . getVectorNumElements ( ) ; MVT EltTy = VT . getVectorElementType ( ) . getSimpleVT ( ) ; MVT WideTy = MVT :: getVectorVT ( EltTy , 2 * NarrowSize ) ; SDLoc DL ( V64Reg ) ; return DAG . getNode ( ISD :: INSERT_SUBVECTOR , DL , WideTy , DAG . getUNDEF ( WideTy ) , V64Reg , DAG . getConstant ( 0 , DL , MVT :: i64 ) ) ; } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> void PPCSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { Policy . OnlyBottomUp = false ; Policy . ShouldTrackPressure = true ; } </s>

Override generic scheduling policy within a region .


"passing %qT to argument %d of %qE, which"

" expects a single SVE vector rather than a tuple"

"passing single vector %qT to argument %d"

" of %qE, which expects a tuple of %d vectors"

Require argument ARGNO to be a single vector or a tuple of NUM_VECTORS vectors ; NUM_VECTORS is 1 for the former . Return the associated type suffix on success , using TYPE_SUFFIX_b for predicates . Report an error and return NUM_TYPE_SUFFIXES on failure .


<s> bool SystemZElimCompare :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; switch ( MI . getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: MOVi16_ga_pcrel : case ARM :: MOVTi16_ga_pcrel : case ARM :: t2MOVi16_ga_pcrel : case ARM :: t2MOVTi16_ga_pcrel : return 4 ; case ARM :: MOVi32imm : case ARM :: t2MOVi32imm : return 8 ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: Int_eh_sjlj_longjmp : return 16 ; case ARM :: tInt_eh_sjlj_longjmp : return 10 ; case ARM :: tInt_WIN_eh_sjlj_longjmp : return 12 ; case ARM :: Int_eh_sjlj_setjmp : case ARM :: Int_eh_sjlj_setjmp_nofp : return 20 ; case ARM :: tInt_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp_nofp : return 12 ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; case ARM :: INLINEASM : case ARM :: INLINEASM_BR : { unsigned Size = getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < ARMFunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , 4 ) ; return Size ; } case ARM :: SpeculationBarrierISBDSBEndBB : case ARM :: t2SpeculationBarrierISBDSBEndBB : return 8 ; case ARM :: SpeculationBarrierSBEndBB : case ARM :: t2SpeculationBarrierSBEndBB : return 4 ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'h' : return std :: make_pair ( 0U , & SystemZ :: GRH32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } if ( Constraint . size ( ) > 0 && Constraint [ 0 ] == '{' ) { if ( Constraint [ 1 ] == 'r' ) { if ( VT == MVT :: i32 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR32BitRegClass , SystemZMC :: GR32Regs ) ; if ( VT == MVT :: i128 ) return parseRegisterNumber ( Constraint , & SystemZ :: GR128BitRegClass , SystemZMC :: GR128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: GR64BitRegClass , SystemZMC :: GR64Regs ) ; } if ( Constraint [ 1 ] == 'f' ) { if ( VT == MVT :: f32 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP32BitRegClass , SystemZMC :: FP32Regs ) ; if ( VT == MVT :: f128 ) return parseRegisterNumber ( Constraint , & SystemZ :: FP128BitRegClass , SystemZMC :: FP128Regs ) ; return parseRegisterNumber ( Constraint , & SystemZ :: FP64BitRegClass , SystemZMC :: FP64Regs ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> int SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; int64_t Offset = ( MFFrame . getObjectOffset ( FI ) + MFFrame . getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize ( MF ) ; return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> const TargetRegisterClass * TeeRISCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & TeeRISC :: IntRegsRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void build_v_base ( function_builder & b , const char * signature , const function_group_info & group , bool force_direct_overloads = false ) { build_32_64 ( b , signature , group , MODE_u32base , MODE_u64base , force_direct_overloads ) ; } </s>

For every type and predicate combination in GROUP , add a function that takes a vector base address and no displacement . The vector base has the same element size as the first type suffix . The other arguments are as for build_all .


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
,
OptimizationRemarkEmitter
*
ORE
)
{
UP
.
UpperBound
=
true
;
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
,
ORE
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
unsigned
UnrollCount
=
4
;
if
(
ST
->
isThumb1Only
(
)
)
{
unsigned
ExitingValues
=
0
;
SmallVector
<
BasicBlock
*
,
4
>
ExitBlocks
;
L
->
getExitBlocks
(
ExitBlocks
)
;
for
(
auto
*
Exit
:
ExitBlocks
)
{
unsigned
LiveOuts
=
count_if
(
Exit
->
phis
(
)
,
[
]
(
auto
&
PH
)
{
return
PH
.
getNumOperands
(
)
!=
1
||
!
isa
<
GetElementPtrInst
>
(
PH
.
getOperand
(
0
)
)
;
}
)
;
ExitingValues
=
ExitingValues
<
LiveOuts
LiveOuts
:
ExitingValues
;
}
if
(
ExitingValues
)
UnrollCount
/=
ExitingValues
;
if
(
UnrollCount
<=
1
)
return
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Default Runtime Unroll Count: "
<<
UnrollCount
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
UnrollCount
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static bool is_cracked_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups && ( rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 ) ) { enum attr_type type = get_attr_type ( insn ) ; if ( ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_NO ) || ( type == TYPE_LOAD && get_attr_sign_extend ( insn ) == SIGN_EXTEND_NO && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( type == TYPE_STORE && get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_NO ) || ( ( type == TYPE_FPLOAD || type == TYPE_FPSTORE ) && get_attr_update ( insn ) == UPDATE_YES ) || type == TYPE_DELAYED_CR || ( type == TYPE_EXTS && get_attr_dot ( insn ) == DOT_YES ) || ( type == TYPE_SHIFT && get_attr_dot ( insn ) == DOT_YES && get_attr_var_shift ( insn ) == VAR_SHIFT_NO ) || ( type == TYPE_MUL && get_attr_dot ( insn ) == DOT_YES ) || type == TYPE_DIV || ( type == TYPE_INSERT && get_attr_size ( insn ) == SIZE_32 ) ) return true ; } return false ; } </s>

The function returns true if INSN is cracked into 2 instructions by the processor ( and therefore occupies 2 issue slots ) .


<s> int xstormy16_splittable_below100_operand ( rtx x , enum machine_mode mode ) { if ( GET_CODE ( x ) == MEM && MEM_VOLATILE_P ( x ) ) return 0 ; return xstormy16_below100_operand ( x , mode ) ; } </s>

Likewise , but only for non-volatile MEMs , for patterns where the MEM will get split into smaller sized accesses .


<s> static rtx mips_legitimize_tls_address ( rtx loc ) { rtx dest , v0 , tp , tmp1 , tmp2 , eqv , offset ; enum tls_model model ; model = SYMBOL_REF_TLS_MODEL ( loc ) ; if ( ! TARGET_ABICALLS ) model = TLS_MODEL_LOCAL_EXEC ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSGD , v0 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , dest , v0 , loc ) ; break ; } case TLS_MODEL_LOCAL_DYNAMIC : { v0 = gen_rtx_REG ( Pmode , GP_RETURN ) ; rtx_insn * insn = mips_call_tls_get_addr ( loc , SYMBOL_TLSLDM , v0 ) ; tmp1 = gen_reg_rtx ( Pmode ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLS_LDM ) ; emit_libcall_block ( insn , tmp1 , v0 , eqv ) ; offset = mips_unspec_address ( loc , SYMBOL_DTPREL ) ; if ( mips_split_p [ SYMBOL_DTPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_DTPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; } case TLS_MODEL_INITIAL_EXEC : tp = mips_get_tp ( ) ; tmp1 = gen_reg_rtx ( Pmode ) ; tmp2 = mips_unspec_address ( loc , SYMBOL_GOTTPREL ) ; if ( Pmode == DImode ) emit_insn ( gen_load_gotdi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; else emit_insn ( gen_load_gotsi ( tmp1 , pic_offset_table_rtx , tmp2 ) ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tmp1 = mips_get_tp ( ) ; offset = mips_unspec_address ( loc , SYMBOL_TPREL ) ; if ( mips_split_p [ SYMBOL_TPREL ] ) { tmp2 = mips_unspec_offset_high ( NULL , tmp1 , loc , SYMBOL_TPREL ) ; dest = gen_rtx_LO_SUM ( Pmode , tmp2 , offset ) ; } else dest = expand_binop ( Pmode , add_optab , tmp1 , offset , 0 , 0 , OPTAB_DIRECT ) ; break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread local SYMBOL_REF . The return value will be a valid address and move_operand ( either a REG or a LO_SUM ) .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

Reset options between modes that the user has specified .


<s> static enum sched_fusion_type fusion_load_store ( rtx_insn * insn , rtx * base , rtx * offset ) { rtx x , dest , src ; enum sched_fusion_type fusion = SCHED_FUSION_LD ; gcc_assert ( INSN_P ( insn ) ) ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) != SET ) return SCHED_FUSION_NONE ; src = SET_SRC ( x ) ; dest = SET_DEST ( x ) ; machine_mode dest_mode = GET_MODE ( dest ) ; if ( ! aarch64_mode_valid_for_sched_fusion_p ( dest_mode ) ) return SCHED_FUSION_NONE ; if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , 0 ) ; if ( ! MEM_P ( src ) || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , 0 ) ; if ( ! MEM_P ( src ) || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( MEM_P ( src ) && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( MEM_P ( dest ) && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return fusion ; } </s>

If INSN is a load or store of address in the form of [ base+offset ] , extract the two parts and set to BASE and OFFSET . IS_LOAD is set to TRUE if it 's a load . Return TRUE if INSN is such an instruction , otherwise return FALSE .


Generate compact unwind encoding for the function based on the CFI instructions .


<s>
static
void
rs6000_xcoff_file_start
(
void
)
{
rs6000_gen_section_name
(
&
xcoff_bss_section_name
,
main_input_filename
,
".bss_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_data_section_name
,
main_input_filename
,
".rw_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_rodata_section_name
,
main_input_filename
,
".rop_"
)
;
rs6000_gen_section_name
(
&
xcoff_read_only_section_name
,
main_input_filename
,
".ro_"
)
;
rs6000_gen_section_name
(
&
xcoff_tls_data_section_name
,
main_input_filename
,
".tls_"
)
;
fputs
(
"\t.file\t"
,
asm_out_file
)
;
output_quoted_string
(
asm_out_file
,
main_input_filename
)
;
fputc
(
'\n'
,
asm_out_file
)
;
if
(
write_symbols
!=
NO_DEBUG
)
switch_to_section
(
private_data_section
)
;
switch_to_section
(
toc_section
)
;
switch_to_section
(
text_section
)
;
if
(
profile_flag
)
fprintf
(
asm_out_file
,
"\t.extern %s\n"
,
RS6000_MCOUNT
)
;
rs6000_file_start
(
)
;
}
</s>

Output at beginning of assembler file . Initialize the section names for the RS/6000 at this point . Specify filename , including full path , to assembler . We want to go into the TOC section so at least one .toc will be emitted . Also , in order to output proper .bs/.es pairs , we need at least one static [ RW ] section emitted . Finally , declare mcount when profiling to make the assembler happy .


<s> static int ix86_vec_cost ( machine_mode mode , int cost , bool parallel ) { if ( ! VECTOR_MODE_P ( mode ) ) return cost ; if ( ! parallel ) return cost * GET_MODE_NUNITS ( mode ) ; if ( GET_MODE_BITSIZE ( mode ) == 128 && TARGET_SSE_SPLIT_REGS ) return cost * 2 ; if ( GET_MODE_BITSIZE ( mode ) > 128 && TARGET_AVX128_OPTIMAL ) return cost * GET_MODE_BITSIZE ( mode ) / 128 ; return cost ; } </s>

Return cost of vector operation in MODE given that scalar version has COST . If PARALLEL is true assume that CPU has more than one unit performing the operation .


<s> virtual SMLoc getEndLoc ( ) const LLVM_OVERRIDE { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> static tree arm_promoted_type ( const_tree t ) { if ( SCALAR_FLOAT_TYPE_P ( t ) && TYPE_PRECISION ( t ) == 16 ) return float_type_node ; return NULL_TREE ; } </s>


<s> MVT X86TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return RegisterVT ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return MVT :: v8f16 ; if ( ( VT == MVT :: f64 || VT == MVT :: f80 ) && ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) return MVT :: i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool ARMAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) return parseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb" ) return parseDirectiveThumb ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arm" ) return parseDirectiveARM ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".thumb_func" ) return parseDirectiveThumbFunc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".code" ) return parseDirectiveCode ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".syntax" ) return parseDirectiveSyntax ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".unreq" ) return parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".arch" ) return parseDirectiveArch ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".eabi_attribute" ) return parseDirectiveEabiAttr ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".cpu" ) return parseDirectiveCPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fpu" ) return parseDirectiveFPU ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fnstart" ) return parseDirectiveFnStart ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".fnend" ) return parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".cantunwind" ) return parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".personality" ) return parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".handlerdata" ) return parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".setfp" ) return parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".pad" ) return parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".save" ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == ".vsave" ) return parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s>
bool
PPCInstrInfo
::
getMemOperandWithOffsetWidth
(
const
MachineInstr
&
LdSt
,
const
MachineOperand
*
&
BaseReg
,
int64_t
&
Offset
,
unsigned
&
Width
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
LdSt
.
mayLoadOrStore
(
)
&&
"Expected a memory operation."
)
;
if
(
LdSt
.
getNumExplicitOperands
(
)
!=
3
)
return
false
;
if
(
!
LdSt
.
getOperand
(
1
)
.
isImm
(
)
||
!
LdSt
.
getOperand
(
2
)
.
isReg
(
)
)
return
false
;
if
(
!
LdSt
.
hasOneMemOperand
(
)
)
return
false
;
Width
=
(
*
LdSt
.
memoperands_begin
(
)
)
->
getSize
(
)
;
Offset
=
LdSt
.
getOperand
(
1
)
.
getImm
(
)
;
BaseReg
=
&
LdSt
.
getOperand
(
2
)
;
return
true
;
}
</s>

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> int paired_emit_vector_cond_expr ( rtx dest , rtx op1 , rtx op2 , rtx cond , rtx cc_op0 , rtx cc_op1 ) { enum rtx_code rcode = GET_CODE ( cond ) ; if ( ! TARGET_PAIRED_FLOAT ) return 0 ; paired_emit_vector_compare ( rcode , dest , op1 , op2 , cc_op0 , cc_op1 ) ; return 1 ; } </s>

Emit vector conditional expression . DEST is destination . OP1 and OP2 are two VEC_COND_EXPR operands . CC_OP0 and CC_OP1 are the two operands for the relation operation COND .


<s>
bool
ARMBaseInstrInfo
::
getRegSequenceLikeInputs
(
const
MachineInstr
&
MI
,
unsigned
DefIdx
,
SmallVectorImpl
<
RegSubRegPairAndIdx
>
&
InputRegs
)
const
{
assert
(
DefIdx
<
MI
.
getDesc
(
)
.
getNumDefs
(
)
&&
"Invalid definition index"
)
;
assert
(
MI
.
isRegSequenceLike
(
)
&&
"Invalid kind of instruction"
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
ARM
::
VMOVDRR
:
const
MachineOperand
*
MOReg
=
&
MI
.
getOperand
(
1
)
;
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_0
)
)
;
MOReg
=
&
MI
.
getOperand
(
2
)
;
InputRegs
.
push_back
(
RegSubRegPairAndIdx
(
MOReg
->
getReg
(
)
,
MOReg
->
getSubReg
(
)
,
ARM
::
ssub_1
)
)
;
return
true
;
}
llvm_unreachable
(
"Target dependent opcode missing"
)
;
}
</s>

Target-dependent implementation of getRegSequenceInputs .


<s> void init_cumulative_args ( CUMULATIVE_ARGS * cum , tree fntype , rtx libname , tree fndecl , int caller ) { struct cgraph_local_info * i = NULL ; struct cgraph_node * target = NULL ; memset ( cum , 0 , sizeof ( * cum ) ) ; if ( fndecl ) { target = cgraph_node :: get ( fndecl ) ; if ( target ) { target = target -> function_symbol ( ) ; i = cgraph_node :: local_info ( target -> decl ) ; cum -> call_abi = ix86_function_abi ( target -> decl ) ; } else cum -> call_abi = ix86_function_abi ( fndecl ) ; } else cum -> call_abi = ix86_function_type_abi ( fntype ) ; cum -> caller = caller ; cum -> nregs = ix86_regparm ; if ( TARGET_64BIT ) { cum -> nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; } if ( TARGET_SSE ) { cum -> sse_nregs = SSE_REGPARM_MAX ; if ( TARGET_64BIT ) { cum -> sse_nregs = ( cum -> call_abi == SYSV_ABI ? X86_64_SSE_REGPARM_MAX : X86_64_MS_SSE_REGPARM_MAX ) ; } } if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_avx512f = true ; cum -> warn_avx = true ; cum -> warn_sse = true ; cum -> warn_mmx = true ; if ( i && i -> local && i -> can_change_signature ) fntype = TREE_TYPE ( target -> decl ) ; cum -> stdarg = stdarg_p ( fntype ) ; cum -> maybe_vaarg = ( fntype ? ( ! prototype_p ( fntype ) || stdarg_p ( fntype ) ) : ! libname ) ; cum -> bnd_regno = FIRST_BND_REG ; cum -> bnds_in_bt = 0 ; cum -> force_bnd_pass = 0 ; cum -> decl = fndecl ; if ( ! TARGET_64BIT ) { if ( stdarg_p ( fntype ) ) { cum -> nregs = 0 ; cfun -> machine -> arg_reg_available = true ; cum -> sse_nregs = 0 ; cum -> mmx_nregs = 0 ; cum -> warn_avx512f = false ; cum -> warn_avx = false ; cum -> warn_sse = false ; cum -> warn_mmx = false ; return ; } if ( fntype ) { unsigned int ccvt = ix86_get_callcvt ( fntype ) ; if ( ( ccvt & IX86_CALLCVT_THISCALL ) != 0 ) { cum -> nregs = 1 ; cum -> fastcall = 1 ; } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != 0 ) { cum -> nregs = 2 ; cum -> fastcall = 1 ; } else cum -> nregs = ix86_function_regparm ( fntype , fndecl ) ; } cum -> float_in_sse = ix86_function_sseregparm ( fntype , fndecl , true ) ; } cfun -> machine -> arg_reg_available = ( cum -> nregs > 0 ) ; } </s>

Handle the INIT_CUMULATIVE_ARGS macro . Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE . For a library call , FNTYPE is 0 .


<s> void ia64_split_tmode_move ( rtx operands [ ] ) { rtx in [ 2 ] , out [ 2 ] , insn ; rtx fixup [ 2 ] ; bool dead = false ; bool reversed = false ; if ( GET_CODE ( operands [ 1 ] ) == MEM && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) ) { rtx base = XEXP ( operands [ 1 ] , 0 ) ; while ( GET_CODE ( base ) != REG ) base = XEXP ( base , 0 ) ; if ( REGNO ( base ) == REGNO ( operands [ 0 ] ) ) reversed = true ; if ( refers_to_regno_p ( REGNO ( operands [ 0 ] ) , REGNO ( operands [ 0 ] ) + 2 , base , 0 ) ) dead = true ; } if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == REG && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) + 1 ) reversed = true ; fixup [ 0 ] = ia64_split_tmode ( in , operands [ 1 ] , reversed , dead ) ; fixup [ 1 ] = ia64_split_tmode ( out , operands [ 0 ] , reversed , dead ) ; if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , 0 ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_DEC ) ) \ add_reg_note ( insn , REG_INC , XEXP ( XEXP ( EXP , 0 ) , 0 ) ) insn = emit_insn ( gen_rtx_SET ( out [ 0 ] , in [ 0 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 0 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 0 ] ) ; insn = emit_insn ( gen_rtx_SET ( out [ 1 ] , in [ 1 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 1 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 1 ] ) ; if ( fixup [ 0 ] ) emit_insn ( fixup [ 0 ] ) ; if ( fixup [ 1 ] ) emit_insn ( fixup [ 1 ] ) ; } </s>

Split a TImode or TFmode move instruction after reload . This is used by * movtf_internal and * movti_internal .


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
HOST_WIDE_INT
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
MASK_PPC_GPOPT
|
MASK_MFCRF
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
darwin_file_start
(
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_default_cpu
;
if
(
global_options_set
.
x_rs6000_cpu_index
)
cpu_id
=
processor_target_table
[
rs6000_cpu_index
]
.
name
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
rs6000_isa_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .


<s> static bool arm_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return arg . type && TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST ; } </s>

Variable sized types are passed by reference . This is a GCC extension to the ARM ABI .


<s> void X86AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { X86MCInstLower MCInstLowering ( Mang , * MF , * this ) ; switch ( MI -> getOpcode ( ) ) { case TargetOpcode :: DBG_VALUE : if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { std :: string TmpStr ; raw_string_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; case X86 :: Int_MemBarrier : if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( "\t#MEMBARRIER" ) ) ; return ; case X86 :: TAILJMPr : case X86 :: TAILJMPd : case X86 :: TAILJMPd64 : OutStreamer . AddComment ( "TAILCALL" ) ; break ; case X86 :: MOVPC32r : { MCInst TmpInst ; MCSymbol * PICBase = MCInstLowering . GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( X86 :: CALLpcrel32 ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( PICBase , OutContext ) ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( X86 :: POP32r ) ; TmpInst . getOperand ( 0 ) = MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } case X86 :: ADD32ri : { if ( MI -> getOperand ( 2 ) . getTargetFlags ( ) != X86II :: MO_GOT_ABSOLUTE_ADDRESS ) break ; MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; MCSymbol * OpSym = MCInstLowering . GetSymbolFromOperand ( MI -> getOperand ( 2 ) ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; const MCExpr * PICBase = MCSymbolRefExpr :: Create ( MCInstLowering . GetPICBaseSymbol ( ) , OutContext ) ; DotExpr = MCBinaryExpr :: CreateSub ( DotExpr , PICBase , OutContext ) ; DotExpr = MCBinaryExpr :: CreateAdd ( MCSymbolRefExpr :: Create ( OpSym , OutContext ) , DotExpr , OutContext ) ; MCInst TmpInst ; TmpInst . setOpcode ( X86 :: ADD32ri ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( 1 ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( DotExpr ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; return ; } } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return elements + 1 ; else return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> static rtx ix86_expand_sse_comi ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; if ( d -> flag & BUILTIN_DESC_SWAP_OPERANDS ) std :: swap ( op0 , op1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ 1 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx ) ) ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of comi insns .


<s> static bool arm_cxx_cdtor_returns_this ( void ) { return TARGET_AAPCS_BASED ; } </s>

The EABI says constructors and destructors should return a pointer to the object constructed/destroyed .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"optimise barriers pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_SystemZ_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_RegMask : CSR_SystemZ_AllRegs_RegMask ; if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_RegMask ; return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> bool AArch64InstrInfo :: isThroughputPattern ( MachineCombinerPattern Pattern ) const { switch ( Pattern ) { default : break ; case MachineCombinerPattern :: FMULADDH_OP1 : case MachineCombinerPattern :: FMULADDH_OP2 : case MachineCombinerPattern :: FMULSUBH_OP1 : case MachineCombinerPattern :: FMULSUBH_OP2 : case MachineCombinerPattern :: FMULADDS_OP1 : case MachineCombinerPattern :: FMULADDS_OP2 : case MachineCombinerPattern :: FMULSUBS_OP1 : case MachineCombinerPattern :: FMULSUBS_OP2 : case MachineCombinerPattern :: FMULADDD_OP1 : case MachineCombinerPattern :: FMULADDD_OP2 : case MachineCombinerPattern :: FMULSUBD_OP1 : case MachineCombinerPattern :: FMULSUBD_OP2 : case MachineCombinerPattern :: FNMULSUBH_OP1 : case MachineCombinerPattern :: FNMULSUBS_OP1 : case MachineCombinerPattern :: FNMULSUBD_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLAv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP2 : case MachineCombinerPattern :: FMLAv4f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP1 : case MachineCombinerPattern :: FMLAv8f16_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP2 : case MachineCombinerPattern :: FMLAv2f32_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP1 : case MachineCombinerPattern :: FMLAv2f64_OP2 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP1 : case MachineCombinerPattern :: FMLAv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLAv4f32_OP1 : case MachineCombinerPattern :: FMLAv4f32_OP2 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP1 : case MachineCombinerPattern :: FMLAv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv4i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP1 : case MachineCombinerPattern :: FMLSv8i16_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv1i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv2i64_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f16_OP1 : case MachineCombinerPattern :: FMLSv4f16_OP2 : case MachineCombinerPattern :: FMLSv8f16_OP1 : case MachineCombinerPattern :: FMLSv8f16_OP2 : case MachineCombinerPattern :: FMLSv2f32_OP2 : case MachineCombinerPattern :: FMLSv2f64_OP2 : case MachineCombinerPattern :: FMLSv4i32_indexed_OP2 : case MachineCombinerPattern :: FMLSv4f32_OP2 : return true ; } return false ; } </s>

Return true when a code sequence can improve throughput .


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> inline static bool isMem ( const MachineInstr * MI , unsigned Op ) { if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + X86 :: AddrNumOperands <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + X86 :: AddrSegmentReg ) . isReg ( ) && isLeaMem ( MI , Op ) ; } </s>


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_UMULH : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_FCONSTANT : { LLT Ty = MRI . getType ( MI . getOperand ( 0 ) . getReg ( ) ) ; unsigned Size = Ty . getSizeInBits ( ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == 32 ? & Mips :: ValueMappings [ Mips :: SPRIdx ] : & Mips :: ValueMappings [ Mips :: DPRIdx ] ; OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ; break ; } case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 0 32 Mips::ValueMappings Mips::SPRIdx Mips::ValueMappings Mips::DPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> bool VZeroUpperInserter :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool EverMadeChange = false ; bool YMMUsed = false ; const TargetRegisterClass * RC = & X86 :: VR256RegClass ; for ( TargetRegisterClass :: iterator i = RC -> begin ( ) , e = RC -> end ( ) ; i != e ; i ++ ) { if ( ! MRI . reg_nodbg_empty ( * i ) ) { YMMUsed = true ; break ; } } if ( ! YMMUsed ) return EverMadeChange ; FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , 0 ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , 0 ) ; while ( 1 ) { bool MadeChange = false ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ; if ( ! MadeChange ) break ; EverMadeChange = true ; } BBState . clear ( ) ; BBSolved . clear ( ) ; return EverMadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s>
MCSymbol
*
TeeRISCMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

TeeRISC
TeeRISC
"Unknown target flag on GV operand"
0


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> virtual const Cpu0Subtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static rtx altivec_expand_vec_init_builtin ( tree type , tree exp , rtx target ) { machine_mode tmode = TYPE_MODE ( type ) ; machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; gcc_assert ( n_elt == call_expr_nargs ( exp ) ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( n_elt == 1 && GET_MODE_SIZE ( tmode ) == GET_MODE_SIZE ( inner_mode ) ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; emit_move_insn ( target , gen_lowpart ( tmode , x ) ) ; } else { rtvec v = rtvec_alloc ( n_elt ) ; for ( i = 0 ; i < n_elt ; ++ i ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , i ) ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } rs6000_expand_vector_init ( target , gen_rtx_PARALLEL ( tmode , v ) ) ; } return target ; } </s>


<s> bool Mips16RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> unsigned mmix_debugger_regno ( unsigned regno ) { regno = MMIX_OUTPUT_REGNO ( regno ) ; return regno >= 224 ? ( regno - 224 ) : ( regno + 48 ) ; } </s>


<s> int SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; FrameReg = RI -> getFrameRegister ( MF ) ; int64_t Offset = ( MFFrame -> getObjectOffset ( FI ) + MFFrame -> getOffsetAdjustment ( ) ) ; Offset -= getOffsetOfLocalArea ( ) ; Offset += getAllocatedStackSize ( MF ) ; return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
MachineInstr
*
LanaiInstrInfo
::
optimizeSelect
(
MachineInstr
&
MI
,
SmallPtrSetImpl
<
MachineInstr
*
>
&
SeenMIs
,
bool
)
const
{
assert
(
MI
.
getOpcode
(
)
==
Lanai
::
SELECT
&&
"unknown select instruction"
)
;
MachineRegisterInfo
&
MRI
=
MI
.
getParent
(
)
->
getParent
(
)
->
getRegInfo
(
)
;
MachineInstr
*
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
1
)
.
getReg
(
)
,
MRI
)
;
bool
Invert
=
!
DefMI
;
if
(
!
DefMI
)
DefMI
=
canFoldIntoSelect
(
MI
.
getOperand
(
2
)
.
getReg
(
)
,
MRI
)
;
if
(
!
DefMI
)
return
nullptr
;
MachineOperand
FalseReg
=
MI
.
getOperand
(
Invert
1
:
2
)
;
unsigned
DestReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
const
TargetRegisterClass
*
PreviousClass
=
MRI
.
getRegClass
(
FalseReg
.
getReg
(
)
)
;
if
(
!
MRI
.
constrainRegClass
(
DestReg
,
PreviousClass
)
)
return
nullptr
;
MachineInstrBuilder
NewMI
=
BuildMI
(
*
MI
.
getParent
(
)
,
MI
,
MI
.
getDebugLoc
(
)
,
DefMI
->
getDesc
(
)
,
DestReg
)
;
const
MCInstrDesc
&
DefDesc
=
DefMI
->
getDesc
(
)
;
for
(
unsigned
i
=
1
,
e
=
DefDesc
.
getNumOperands
(
)
;
i
!=
e
&&
!
DefDesc
.
OpInfo
[
i
]
.
isPredicate
(
)
;
++
i
)
NewMI
.
add
(
DefMI
->
getOperand
(
i
)
)
;
unsigned
CondCode
=
MI
.
getOperand
(
3
)
.
getImm
(
)
;
if
(
Invert
)
NewMI
.
addImm
(
getOppositeCondition
(
LPCC
::
CondCode
(
CondCode
)
)
)
;
else
NewMI
.
addImm
(
CondCode
)
;
NewMI
.
copyImplicitOps
(
MI
)
;
FalseReg
.
setImplicit
(
)
;
NewMI
.
add
(
FalseReg
)
;
NewMI
->
tieOperands
(
0
,
NewMI
->
getNumOperands
(
)
1
)
;
SeenMIs
.
insert
(
NewMI
)
;
SeenMIs
.
erase
(
DefMI
)
;
if
(
DefMI
->
getParent
(
)
!=
MI
.
getParent
(
)
)
NewMI
->
clearKillInfo
(
)
;
DefMI
->
eraseFromParent
(
)
;
return
NewMI
;
}
</s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s> TargetLowering :: AtomicExpansionKind SparcTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> getOperation ( ) == AtomicRMWInst :: Xchg && AI -> getType ( ) -> getPrimitiveSizeInBits ( ) == 32 ) return AtomicExpansionKind :: None ; return AtomicExpansionKind :: CmpXChg ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


Return an array that contains the direct target flag values and their names .

PowerPC PPC PPC "ppc-lo" "ppc-ha" "ppc-tprel-lo" "ppc-tprel-ha" "ppc-dtprel-lo" "ppc-tlsld-lo" "ppc-toc-lo" "ppc-tls"


<s> Optional < MCFixupKind > ARMAsmBackendELF :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_ARM_NONE ) . Case ( "BFD_RELOC_8" , ELF :: R_ARM_ABS8 ) . Case ( "BFD_RELOC_16" , ELF :: R_ARM_ABS16 ) . Case ( "BFD_RELOC_32" , ELF :: R_ARM_ABS32 ) . Default ( - 1u ) ; if ( Type == - 1u ) return None ; return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> bool ARMFrameLowering :: enableShrinkWrapping ( const MachineFunction & MF ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < ARMFunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) return false ; if ( MF . getInfo < ARMFunctionInfo > ( ) -> shouldSignReturnAddress ( false ) ) return false ; return true ; } </s>

Returns true if the target will correctly handle shrink wrapping .


"getMemOperandWithOffset only supports base "

"operands of type register or frame index."

Return true if get the base operand , byte offset of an instruction and the memory width .


<s> void PPCTTI :: getUnrollingPreferences ( const Function * F , Loop * L , UnrollingPreferences & UP ) const { if ( TM -> getSubtarget < PPCSubtarget > ( F ) . getDarwinDirective ( ) == PPC :: DIR_A2 ) { UP . Partial = UP . Runtime = true ; } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static rtx ix86_expand_vec_set_builtin ( tree arglist ) { enum machine_mode tmode , mode1 ; tree arg0 , arg1 , arg2 ; int elt ; rtx op0 , op1 ; arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; arg2 = TREE_VALUE ( TREE_CHAIN ( TREE_CHAIN ( arglist ) ) ) ; tmode = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; mode1 = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , tmode , 0 ) ; op1 = expand_expr ( arg1 , NULL_RTX , mode1 , 0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg2 ) ; if ( GET_MODE ( op1 ) != mode1 && GET_MODE ( op1 ) != VOIDmode ) op1 = convert_modes ( mode1 , GET_MODE ( op1 ) , op1 , true ) ; op0 = force_reg ( tmode , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; ix86_expand_vector_set ( true , op0 , op1 , elt ) ; return op0 ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_set . They would be redundant ( for non-MMX ) if we had a language-level syntax for referencing vector elements .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstFlags ( MI , OS ) ; if ( MI -> getOpcode ( ) == X86 :: DATA16_PREFIX && STI . getFeatureBits ( ) [ X86 :: Mode16Bit ] ) { OS << "\tdata32" ; } else if ( ! printAliasInstr ( MI , OS ) && ! printVecCompareInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , MII ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI . getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; Value = 0 ; Mask = 0 ; return true ; } } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static bool rs6000_parm_needs_stack ( cumulative_args_t args_so_far , tree type ) { int unsignedp ; rtx entry_parm ; if ( type == NULL || type == error_mark_node ) return true ; if ( TYPE_MODE ( type ) == VOIDmode ) return false ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) return ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) || rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( type ) ) ) ; if ( ( TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == RECORD_TYPE ) && TYPE_TRANSPARENT_AGGR ( type ) ) type = TREE_TYPE ( first_field ( type ) ) ; function_arg_info arg ( type , true ) ; apply_pass_by_reference_rules ( get_cumulative_args ( args_so_far ) , arg ) ; unsignedp = TYPE_UNSIGNED ( type ) ; arg . mode = promote_mode ( arg . type , arg . mode , & unsignedp ) ; if ( rs6000_must_pass_in_stack ( arg ) ) return true ; entry_parm = rs6000_function_arg ( args_so_far , arg ) ; if ( entry_parm == NULL ) return true ; if ( GET_CODE ( entry_parm ) == PARALLEL && XEXP ( XVECEXP ( entry_parm , 0 , 0 ) , 0 ) == NULL_RTX ) return true ; if ( rs6000_arg_partial_bytes ( args_so_far , arg ) != 0 ) return true ; rs6000_function_arg_advance ( args_so_far , arg ) ; return false ; } </s>

Process parameter of type TYPE after ARGS_SO_FAR parameters were already processes . Return true if the parameter must be passed ( fully or partially ) on the stack .


<s> static bool arm_bfi_1_p ( rtx op0 , rtx op1 , rtx * sub0 , rtx * sub1 ) { unsigned HOST_WIDE_INT const1 ; unsigned HOST_WIDE_INT const2 = 0 ; if ( ! CONST_INT_P ( XEXP ( op0 , 1 ) ) ) return false ; const1 = UINTVAL ( XEXP ( op0 , 1 ) ) ; if ( ! CONST_INT_P ( XEXP ( op1 , 1 ) ) || ~ UINTVAL ( XEXP ( op1 , 1 ) ) != const1 ) return false ; if ( GET_CODE ( XEXP ( op0 , 0 ) ) == ASHIFT && CONST_INT_P ( XEXP ( XEXP ( op0 , 0 ) , 1 ) ) ) { const2 = UINTVAL ( XEXP ( XEXP ( op0 , 0 ) , 1 ) ) ; * sub0 = XEXP ( XEXP ( op0 , 0 ) , 0 ) ; } else * sub0 = XEXP ( op0 , 0 ) ; if ( const2 >= GET_MODE_BITSIZE ( GET_MODE ( op0 ) ) ) return false ; * sub1 = XEXP ( op1 , 0 ) ; return exact_log2 ( const1 + ( HOST_WIDE_INT_1U << const2 ) ) >= 0 ; } </s>


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> unsigned AArch64FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return materializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return materializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return materializeGV ( GV ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static void mmix_encode_section_info ( tree decl , rtx rtl , int first ) { if ( ( TREE_CODE ( decl ) == VAR_DECL && ( DECL_EXTERNAL ( decl ) || TREE_PUBLIC ( decl ) ) ) || ( TREE_CODE ( decl ) == FUNCTION_DECL && TREE_PUBLIC ( decl ) ) ) ; else if ( first && DECL_P ( decl ) ) { const char * str = XSTR ( XEXP ( rtl , 0 ) , 0 ) ; int len = strlen ( str ) ; char * newstr = XALLOCAVEC ( char , len + 2 ) ; newstr [ 0 ] = '@' ; strcpy ( newstr + 1 , str ) ; XSTR ( XEXP ( rtl , 0 ) , 0 ) = ggc_alloc_string ( newstr , len + 1 ) ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL || TREE_CONSTANT ( decl ) || ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && ( ! DECL_INITIAL ( decl ) || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , 0 ) ) = 1 ; } </s>


<s>
const
ArrayRef
<
MCPhysReg
>
SICABIInfo
::
GetByValArgRegs
(
)
const
{
if
(
IsO32
(
)
)
return
makeArrayRef
(
O32IntRegs
)
;
if
(
IsS32
(
)
)
return
makeArrayRef
(
S32IntRegs
)
;
llvm_unreachable
(
"Unhandled ABI"
)
;
}
</s>

The registers to use for byval arguments .


<s> int rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops_log ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > 4 && ninsns <= 8 && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 || rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 ) ) return 5 ; else return align_loops_log ; } </s>


<s>
bool
MipsAsmPrinter
::
doInitialization
(
Module
&
M
)
{
Mang
=
new
Mangler
(
M
,
""
,
TAI
->
getPrivateGlobalPrefix
(
)
)
;
O
<<
"\t.section .mdebug."
<<
emitCurrentABIString
(
)
<<
'\n'
;
if
(
Subtarget
->
isABI_EABI
(
)
)
O
<<
"\t.section .gcc_compiled_long"
<<
(
Subtarget
->
isGP32bit
(
)
"32"
:
"64"
)
<<
'\n'
;
O
<<
"\t.previous"
<<
'\n'
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ; } </s>


<s> static unsigned int aarch64_dwarf_poly_indeterminate_value ( unsigned int i , unsigned int * factor , int * offset ) { gcc_assert ( i == 1 ) ; * factor = 2 ; * offset = 1 ; return AARCH64_DWARF_VG ; } </s>

Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook .


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; switch ( mode ) { case E_QImode : fn = gen_load_lockedqi ; break ; case E_HImode : fn = gen_load_lockedhi ; break ; case E_SImode : if ( GET_MODE ( mem ) == QImode ) fn = gen_load_lockedqi_si ; else if ( GET_MODE ( mem ) == HImode ) fn = gen_load_lockedhi_si ; else fn = gen_load_lockedsi ; break ; case E_DImode : fn = gen_load_lockeddi ; break ; case E_TImode : fn = gen_load_lockedti ; break ; default : gcc_unreachable ( ) ; } emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s>
bool
Emitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
II
=
TM
.
getInstrInfo
(
)
;
TD
=
TM
.
getTargetData
(
)
;
Is64BitMode
=
TM
.
getSubtarget
<
X86Subtarget
>
(
)
.
is64Bit
(
)
;
IsPIC
=
TM
.
getRelocationModel
(
)
==
Reloc
::
PIC_
;
do
{
DOUT
<<
"JITTing function '"
<<
MF
.
getFunction
(
)
->
getName
(
)
<<
"'\n"
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
const_iterator
I
=
MBB
->
begin
(
)
,
E
=
MBB
->
end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetInstrDesc
&
Desc
=
I
->
getDesc
(
)
;
emitInstruction
(
*
I
,
&
Desc
)
;
if
(
Desc
.
getOpcode
(
)
==
X86
::
MOVPC32r
)
emitInstruction
(
*
I
,
&
II
->
get
(
X86
::
POP32r
)
)
;
NumEmitted
++
;
}
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool X86TargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . flags = MachineMemOperand :: MONone ; Info . offset = 0 ; switch ( IntrData -> Type ) { case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 0 ) ; MVT VT = MVT :: getVT ( I . getArgOperand ( 1 ) -> getType ( ) ) ; MVT ScalarVT = MVT :: INVALID_SIMPLE_VALUE_TYPE ; if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = MVT :: i8 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI16 ) ScalarVT = MVT :: i16 ; else if ( IntrData -> Type == TRUNCATE_TO_MEM_VI32 ) ScalarVT = MVT :: i32 ; Info . memVT = MVT :: getVectorVT ( ScalarVT , VT . getVectorNumElements ( ) ) ; Info . align = Align ( 1 ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case GATHER : case GATHER_AVX2 : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align ( 1 ) ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case SCATTER : { Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = nullptr ; MVT DataVT = MVT :: getVT ( I . getArgOperand ( 3 ) -> getType ( ) ) ; MVT IndexVT = MVT :: getVT ( I . getArgOperand ( 2 ) -> getType ( ) ) ; unsigned NumElts = std :: min ( DataVT . getVectorNumElements ( ) , IndexVT . getVectorNumElements ( ) ) ; Info . memVT = MVT :: getVectorVT ( DataVT . getVectorElementType ( ) , NumElts ) ; Info . align = Align ( 1 ) ; Info . flags |= MachineMemOperand :: MOStore ; break ; } default : return false ; } return true ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .