<s> Value * AArch64TargetLowering :: getSafeStackPointerLocation ( IRBuilderBase & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , 0x48 ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - 0x8 ) ; return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> const unsigned * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned SingleFloatOnlyCalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F21 , Mips :: F22 , Mips :: F23 , Mips :: F24 , Mips :: F25 , Mips :: F26 , Mips :: F27 , Mips :: F28 , Mips :: F29 , Mips :: F30 , 0 } ; static const unsigned BitMode32CalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F22 , Mips :: F24 , Mips :: F26 , Mips :: F28 , Mips :: F30 , Mips :: D10 , Mips :: D11 , Mips :: D12 , Mips :: D13 , Mips :: D14 , Mips :: D15 , 0 } ; if ( Subtarget . isSingleFloat ( ) ) return SingleFloatOnlyCalleeSavedRegs ; else return BitMode32CalleeSavedRegs ; } </s>


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: DIR_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: DIR_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


";;\tatom sched_reorder: put %d insn on top\n"

";;\tslm sched_reorder: swap %d and %d insns\n"

Perform possible reodering of ready list for Atom/Silvermont only . Return issue rate .


<s> bool Thumb1RegisterInfo :: saveScavengerRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , MachineBasicBlock :: iterator & UseMI , const TargetRegisterClass * RC , unsigned Reg ) const { DebugLoc DL ; BuildMI ( MBB , I , DL , TII . get ( ARM :: tMOVtgpr2gpr ) ) . addReg ( ARM :: R12 , RegState :: Define ) . addReg ( Reg , RegState :: Kill ) ; bool done = false ; for ( MachineBasicBlock :: iterator II = I ; ! done && II != UseMI ; ++ II ) { if ( II -> isDebugValue ( ) ) continue ; for ( unsigned i = 0 , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == ARM :: R12 ) { UseMI = II ; done = true ; break ; } } } BuildMI ( MBB , UseMI , DL , TII . get ( ARM :: tMOVgpr2tgpr ) ) . addReg ( Reg , RegState :: Define ) . addReg ( ARM :: R12 , RegState :: Kill ) ; return true ; } </s>

Spill the register so it can be used by the register scavenger .


<s> MVT ARM64TargetLowering :: getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i64 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> int empty_delay_slot ( rtx_insn * insn ) { rtx seq ; if ( PREV_INSN ( insn ) == NULL ) return 1 ; seq = NEXT_INSN ( PREV_INSN ( insn ) ) ; if ( GET_CODE ( PATTERN ( seq ) ) == SEQUENCE ) return 0 ; return 1 ; } </s>

Return non-zero if a branch or call instruction will be emitting a nop into its delay slot .


<s> pa_asm_output_aligned_local ( FILE , NAME , SIZE , ALIGN ) { rtx addr = ADDR ; \ switch ( GET_CODE ( addr ) ) \ { \ case REG : \ fprintf ( FILE , "0(%s)" , reg_names [ REGNO ( addr ) ] ) ; \ break ; \ case PLUS : \ gcc_assert ( GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT ) ; \ fprintf ( FILE , "%d(%s)" , ( int ) INTVAL ( XEXP ( addr , 1 ) ) , \ reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; \ break ; \ case LO_SUM : \ if ( ! symbolic_operand ( XEXP ( addr , 1 ) , VOIDmode ) ) \ fputs ( "R'" , FILE ) ; \ else if ( flag_pic == 0 ) \ fputs ( "RR'" , FILE ) ; \ else \ fputs ( "RT'" , FILE ) ; \ pa_output_global_address ( FILE , XEXP ( addr , 1 ) , 0 ) ; \ fputs ( "(" , FILE ) ; \ output_operand ( XEXP ( addr , 0 ) , 0 ) ; \ fputs ( ")" , FILE ) ; \ break ; \ case CONST_INT : \ fprintf ( FILE , HOST_WIDE_INT_PRINT_DEC "(%%r0)" , INTVAL ( addr ) ) ; \ break ; \ default : \ output_addr_const ( FILE , addr ) ; \ } } </s>

We ca n't use .comm for local common storage as the SOM linker effectively treats the symbol as universal and uses the same storage for local symbols with the same name in different object files . The .block directive reserves an uninitialized block of storage . However , it 's not common storage . Fortunately , GCC never requests common storage with the same name in any given translation unit .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
const
MachineInstr
&
MIa
,
const
MachineInstr
&
MIb
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
const
MachineOperand
*
BaseOpA
=
nullptr
,
*
BaseOpB
=
nullptr
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
WidthA
=
0
,
WidthB
=
0
;
bool
OffsetAIsScalable
=
false
,
OffsetBIsScalable
=
false
;
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getMemOperandWithOffsetWidth
(
MIa
,
BaseOpA
,
OffsetA
,
OffsetAIsScalable
,
WidthA
,
TRI
)
&&
getMemOperandWithOffsetWidth
(
MIb
,
BaseOpB
,
OffsetB
,
OffsetBIsScalable
,
WidthB
,
TRI
)
)
{
if
(
BaseOpA
->
isIdenticalTo
(
*
BaseOpB
)
&&
OffsetAIsScalable
==
OffsetBIsScalable
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> void ARMHazardRecognizer :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isDebugValue ( ) ) { LastMI = MI ; FpMLxStalls = 0 ; } ScoreboardHazardRecognizer :: EmitInstruction ( SU ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void AArch64InstPrinter :: printImm ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; O << "#" << formatImm ( Op . getImm ( ) ) ; } </s>

Implement target specific printing for machine operand immediate value , so that we can have more meaningful mnemonic than a 64-bit integer .


<s> bool Warning ( SMLoc L , const Twine & Msg , SMRange Range = None ) { return getParser ( ) . Warning ( L , Msg , Range ) ; } </s>

Emit a warning at the location L , with the message Msg .


<s> std :: pair < unsigned , const TargetRegisterClass * > XNCMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : if ( VT == MVT :: i8 ) return std :: make_pair ( 0U , XNCM :: GR8RegisterClass ) ; return std :: make_pair ( 0U , XNCM :: GR16RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool AArch64MIPeepholeOpt :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> isSSA ( ) ) return false ; bool Changed = false ; SmallSetVector < MachineInstr * , 8 > ToBeRemoved ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: ANDWrr : Changed = visitAND < uint32_t > ( MI , ToBeRemoved ) ; break ; case AArch64 :: ANDXrr : Changed = visitAND < uint64_t > ( MI , ToBeRemoved ) ; break ; } } } for ( MachineInstr * MI : ToBeRemoved ) MI -> eraseFromParent ( ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static tree aarch64_lookup_simd_type_in_table ( machine_mode mode , enum aarch64_type_qualifiers qualifiers ) { int i ; int nelts = ARRAY_SIZE ( aarch64_simd_types ) ; int q = qualifiers & ( qualifier_poly | qualifier_unsigned ) ; for ( i = 0 ; i < nelts ; i ++ ) { if ( aarch64_simd_types [ i ] . mode == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_types [ i ] . itype ; if ( aarch64_simd_tuple_types [ i ] [ 0 ] != NULL_TREE ) for ( int j = 0 ; j < 3 ; j ++ ) if ( aarch64_simd_tuple_modes [ i ] [ j ] == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_tuple_types [ i ] [ j ] ; } return NULL_TREE ; } </s>

Helper function for aarch64_simd_builtin_type .


<s>
bool
SystemZAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
,
MCStreamer
&
Out
,
unsigned
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
MatchResult
=
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
;
switch
(
MatchResult
)
{
default
:
break
;
case
Match_Success
:
Inst
.
setLoc
(
IDLoc
)
;
Out
.
EmitInstruction
(
Inst
,
STI
)
;
return
false
;
case
Match_MissingFeature
:
{
assert
(
ErrorInfo
&&
"Unknown missing feature!"
)
;
std
::
string
Msg
=
"instruction requires:"
;
unsigned
Mask
=
1
;
for
(
unsigned
I
=
0
;
I
<
sizeof
(
ErrorInfo
)
*
8
1
;
++
I
)
{
if
(
ErrorInfo
&
Mask
)
{
Msg
+=
" "
;
Msg
+=
getSubtargetFeatureName
(
ErrorInfo
&
Mask
)
;
}
Mask
<<=
1
;
}
return
Error
(
IDLoc
,
Msg
)
;
}
case
Match_InvalidOperand
:
{
SMLoc
ErrorLoc
=
IDLoc
;
if
(
ErrorInfo
!=
~
0U
)
{
if
(
ErrorInfo
>=
Operands
.
size
(
)
)
return
Error
(
IDLoc
,
"too few operands for instruction"
)
;
ErrorLoc
=
(
(
SystemZOperand
*
)
Operands
[
ErrorInfo
]
)
->
getStartLoc
(
)
;
if
(
ErrorLoc
==
SMLoc
(
)
)
ErrorLoc
=
IDLoc
;
}
return
Error
(
ErrorLoc
,
"invalid operand for instruction"
)
;
}
case
Match_MnemonicFail
:
return
Error
(
IDLoc
,
"invalid instruction"
)
;
}
llvm_unreachable
(
"Unexpected match type"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMSubtarget & STI = static_cast < const ARMSubtarget & > ( MF . getSubtarget ( ) ) ; const TargetMachine & TM = MF . getTarget ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = STI . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM . getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = STI . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = STI . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( GenerateSgxCode ) { addPass ( createSgxMCPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; return ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } addPass ( createX86WinAllocaExpander ( ) ) ; addPass ( createMachineInstPrint ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> rtx extract_mac_non_acc_rtx ( rtx_insn * insn ) { rtx exp = SET_SRC ( PATTERN ( insn ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MAC : case TYPE_DMAC : if ( REG_P ( XEXP ( exp , 0 ) ) ) return XEXP ( exp , 1 ) ; else return XEXP ( exp , 0 ) ; default : gcc_unreachable ( ) ; } } </s>

Extract the rtx representing non-accumulation operands of a MAC insn .


<s> bool mips_legitimize_move ( machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { mips_emit_move ( dest , force_reg ( mode , src ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { mips_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid instruction , emit an equivalent sequence that is valid .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
case
PPC
::
XXSETACCZ
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static void find_constant ( rtx in_rtx , imm_info * imm_values ) { if ( INSN_P ( in_rtx ) ) in_rtx = PATTERN ( in_rtx ) ; subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , in_rtx , ALL ) if ( const_rtx x = * iter ) switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case CONST_INT : ( imm_values -> imm ) ++ ; if ( x86_64_immediate_operand ( CONST_CAST_RTX ( x ) , SImode ) ) ( imm_values -> imm32 ) ++ ; else ( imm_values -> imm64 ) ++ ; break ; case CONST_DOUBLE : ( imm_values -> imm ) ++ ; ( imm_values -> imm64 ) ++ ; break ; case CODE_LABEL : if ( LABEL_KIND ( x ) == LABEL_NORMAL ) { ( imm_values -> imm ) ++ ; ( imm_values -> imm32 ) ++ ; } break ; default : break ; } } </s>

Compute number of immediate operands of an instruction .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( TFI -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> unsigned getNumberOfRegisters ( bool Vector ) const { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 32 ; } </s>


<s>
static
void
rs6000_print_options_internal
(
FILE
*
file
,
int
indent
,
const
char
*
string
,
HOST_WIDE_INT
flags
,
const
char
*
prefix
,
const
struct
rs6000_opt_mask
*
opts
,
size_t
num_elements
)
{
size_t
i
;
size_t
start_column
=
0
;
size_t
cur_column
;
size_t
max_column
=
76
;
const
char
*
comma
=
""
;
if
(
indent
)
start_column
+=
fprintf
(
file
,
"%*s"
,
indent
,
""
)
;
if
(
!
flags
)
{
fprintf
(
stderr
,
DEBUG_FMT_S
,
string
,
"<none>"
)
;
return
;
}
start_column
+=
fprintf
(
stderr
,
DEBUG_FMT_WX
,
string
,
flags
)
;
cur_column
=
start_column
;
for
(
i
=
0
;
i
<
num_elements
;
i
++
)
{
if
(
(
flags
&
opts
[
i
]
.
mask
)
!=
0
)
{
const
char
*
no_str
=
rs6000_opt_masks
[
i
]
.
invert
"no-"
:
""
;
size_t
len
=
(
strlen
(
comma
)
+
strlen
(
prefix
)
+
strlen
(
no_str
)
+
strlen
(
rs6000_opt_masks
[
i
]
.
name
)
)
;
cur_column
+=
len
;
if
(
cur_column
>
max_column
)
{
fprintf
(
stderr
,
", \\\n%*s"
,
(
int
)
start_column
,
""
)
;
cur_column
=
start_column
+
len
;
comma
=
""
;
}
fprintf
(
file
,
"%s%s%s%s"
,
comma
,
prefix
,
no_str
,
rs6000_opt_masks
[
i
]
.
name
)
;
flags
&=
~
opts
[
i
]
.
mask
;
comma
=
", "
;
}
}
fputs
(
"\n"
,
file
)
;
}
</s>

Helper function to print the current isa or misc options on a line .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & TuneCPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian , unsigned MinSVEVectorSizeInBitsOverride , unsigned MaxSVEVectorSizeInBitsOverride ) : AArch64GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , MinSVEVectorSizeInBits ( MinSVEVectorSizeInBitsOverride ) , MaxSVEVectorSizeInBits ( MaxSVEVectorSizeInBitsOverride ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU , TuneCPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; AArch64PreLegalizerCombinerInfo PCInfo ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>


Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const MCExpr * X86TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( Subtarget -> isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ; } </s>

This returns the relocation base for the given PIC jumptable , the same as getPICJumpTableRelocBase , but as an MCExpr .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s>
unsigned
MINA32MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
assert
(
MO
.
isImm
(
)
&&
"did not expect relocated expression"
)
;
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> unsigned getNumberOfRegisters ( unsigned ClassID ) const { return 64 ; } </s>


<s> bool PPCTargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; return ! ( BitSize == 0 || BitSize > 64 ) ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool LanaiAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OS . write ( "\x15\0\0\0" , 4 ) ; return true ; } </s>


<s> static void rs6000_emit_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_movesi_from_cr ( reg ) ) ; } </s>

Emit code to store CR fields that need to be saved into REG .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; bool hasAVX2 = Subtarget . hasAVX2 ( ) ; uint16_t validDomains = 0 ; if ( domain && lookup ( MI -> getOpcode ( ) , domain ) ) validDomains = 0xe ; else if ( domain && lookupAVX2 ( MI -> getOpcode ( ) , domain ) ) validDomains = hasAVX2 ? 0xe : 0x6 ; return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { UseSoftMulDiv = false ; IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; IsVIS2 = false ; IsVIS3 = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasNoFSMULD = false ; HasNoFMULS = false ; HasLeonCasa = false ; HasUmacSmac = false ; InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , 0 ) ; source = gen_lowpart ( V2DImode , source ) ; } rtx tmp = gen_reg_rtx_and_attrs ( source ) ; rs6000_emit_le_vsx_permute ( tmp , source , mode ) ; rs6000_emit_le_vsx_permute ( dest , tmp , mode ) ; } </s>

Emit a little-endian store to vector memory location DEST from VSX register SOURCE in mode MODE . The store is done with two permuting insn 's that represent an xxpermdi and an stxvd2x .


<s> void get_ppc476_thunk_name ( char name [ 32 ] ) { gcc_assert ( TARGET_LINK_STACK ) ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__ppc476.get_thunk" ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LPPC476_" , 0 ) ; } </s>

Fills in the label name that should be used for a 476 link stack thunk .


<s> AArch64Subtarget :: AArch64Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV8_1aOps ( false ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , IsLittle ( LittleEndian ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( TM . getDataLayout ( ) ) , TLInfo ( TM , * this ) { } </s>


<s> bool aarch64_sve_same_pred_for_ptest_p ( rtx * pred1 , rtx * pred2 ) { machine_mode mode = GET_MODE ( pred1 [ 0 ] ) ; gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && mode == GET_MODE ( pred2 [ 0 ] ) && aarch64_sve_ptrue_flag ( pred1 [ 1 ] , SImode ) && aarch64_sve_ptrue_flag ( pred2 [ 1 ] , SImode ) ) ; bool ptrue1_p = ( pred1 [ 0 ] == CONSTM1_RTX ( mode ) || INTVAL ( pred1 [ 1 ] ) == SVE_KNOWN_PTRUE ) ; bool ptrue2_p = ( pred2 [ 0 ] == CONSTM1_RTX ( mode ) || INTVAL ( pred2 [ 1 ] ) == SVE_KNOWN_PTRUE ) ; return ( ptrue1_p && ptrue2_p ) || rtx_equal_p ( pred1 [ 0 ] , pred2 [ 0 ] ) ; } </s>

PRED1 [ 0 ] is a PTEST predicate and PRED1 [ 1 ] is an aarch64_sve_ptrue_flag for it . PRED2 [ 0 ] is the predicate for the instruction whose result is tested by the PTEST and PRED2 [ 1 ] is again an aarch64_sve_ptrue_flag for it . Return true if we can prove that the two predicates are equivalent for PTEST purposes ; that is , if we can replace PRED2 [ 0 ] with PRED1 [ 0 ] without changing behavior .


<s> static int mingw32_gt_pch_use_address ( void * addr , size_t size , int fd , size_t offset ) { void * mmap_addr ; HANDLE mmap_handle ; char * object_name = NULL ; OSVERSIONINFO version_info ; int r ; version_info . dwOSVersionInfoSize = sizeof ( version_info ) ; if ( size == 0 ) return 0 ; if ( ( offset & ( va_granularity - 1 ) ) != 0 || size > pch_VA_max_size ) return - 1 ; GetVersionEx ( & version_info ) ; if ( version_info . dwMajorVersion > 4 ) { char local_object_name [ sizeof ( OBJECT_NAME_FMT ) + sizeof ( DWORD ) * 2 ] ; snprintf ( local_object_name , sizeof ( local_object_name ) , OBJECT_NAME_FMT "%lx" , GetCurrentProcessId ( ) ) ; object_name = local_object_name ; } mmap_handle = CreateFileMappingA ( ( HANDLE ) _get_osfhandle ( fd ) , NULL , PAGE_WRITECOPY | SEC_COMMIT , 0 , 0 , object_name ) ; if ( mmap_handle == NULL ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "CreateFileMapping" ) ; return - 1 ; } for ( r = 0 ; r < 5 ; r ++ ) { mmap_addr = MapViewOfFileEx ( mmap_handle , FILE_MAP_COPY , 0 , offset , size , addr ) ; if ( mmap_addr == addr ) break ; if ( r != 4 ) Sleep ( 500 ) ; } if ( mmap_addr != addr ) { w32_error ( __FUNCTION__ , __FILE__ , __LINE__ , "MapViewOfFileEx" ) ; CloseHandle ( mmap_handle ) ; return - 1 ; } return 1 ; } </s>

ADDR is an address returned by gt_pch_get_address . Attempt to allocate SIZE bytes at the same address and load it with the data from FD at OFFSET . Return -1 if we could n't allocate memory at ADDR , return 0 if the memory is allocated but the data not loaded , return 1 if done .


<s>
StackOffset
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
StackOffset
::
getFixed
(
MFI
.
getObjectOffset
(
FI
)
)
;
}
if
(
MFI
.
hasVarSizedObjects
(
)
||
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
->
getStackSizeSVE
(
)
||
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
->
hasStackRealignment
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
FrameReg
=
AArch64
::
SP
;
return
getStackOffset
(
MF
,
MFI
.
getObjectOffset
(
FI
)
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> rtx rs6000_adjust_vec_address ( rtx scalar_reg , rtx mem , rtx element , rtx base_tmp , machine_mode scalar_mode ) { unsigned scalar_size = GET_MODE_SIZE ( scalar_mode ) ; rtx addr = XEXP ( mem , 0 ) ; rtx new_addr ; gcc_assert ( ! reg_mentioned_p ( base_tmp , addr ) ) ; gcc_assert ( ! reg_mentioned_p ( base_tmp , element ) ) ; gcc_assert ( GET_RTX_CLASS ( GET_CODE ( addr ) ) != RTX_AUTOINC ) ; rtx element_offset = get_vector_offset ( mem , element , base_tmp , scalar_size ) ; if ( element_offset == const0_rtx ) new_addr = addr ; else if ( REG_P ( addr ) || SUBREG_P ( addr ) ) new_addr = gen_rtx_PLUS ( Pmode , addr , element_offset ) ; else if ( pcrel_local_address ( addr , Pmode ) && CONST_INT_P ( element_offset ) ) new_addr = adjust_vec_address_pcrel ( addr , element_offset , base_tmp ) ; else if ( GET_CODE ( addr ) == PLUS ) { rtx op0 = XEXP ( addr , 0 ) ; rtx op1 = XEXP ( addr , 1 ) ; gcc_assert ( REG_P ( op0 ) || SUBREG_P ( op0 ) ) ; if ( CONST_INT_P ( op1 ) && CONST_INT_P ( element_offset ) ) { gcc_assert ( reg_or_subregno ( op0 ) != 0 ) ; HOST_WIDE_INT offset = INTVAL ( op1 ) + INTVAL ( element_offset ) ; rtx offset_rtx = GEN_INT ( offset ) ; new_addr = gen_rtx_PLUS ( Pmode , op0 , offset_rtx ) ; } else { emit_insn ( gen_rtx_SET ( base_tmp , gen_rtx_PLUS ( Pmode , op0 , op1 ) ) ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } } else { emit_move_insn ( base_tmp , addr ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } enum insn_form iform = address_to_insn_form ( new_addr , scalar_mode , reg_to_non_prefixed ( scalar_reg , scalar_mode ) ) ; if ( iform == INSN_FORM_BAD ) { emit_move_insn ( base_tmp , new_addr ) ; new_addr = base_tmp ; } return change_address ( mem , scalar_mode , new_addr ) ; } </s>

Adjust a memory address ( MEM ) of a vector type to point to a scalar field within the vector ( ELEMENT ) with a mode ( SCALAR_MODE ) . Use a base register temporary ( BASE_TMP ) to fixup the address . Return the new memory address that is valid for reads or writes to a given register ( SCALAR_REG ) . This function is expected to be called after reload is completed when we are splitting insns . The temporary BASE_TMP might be set multiple times with this code .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { bool fp = false ; machine_mode mode = TImode ; int index ; if ( vectype != NULL ) { fp = FLOAT_TYPE_P ( vectype ) ; mode = TYPE_MODE ( vectype ) ; } switch ( type_of_cost ) { case scalar_stmt : return fp ? ix86_cost -> addss : COSTS_N_INSNS ( 1 ) ; case scalar_load : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_load [ 0 ] : ix86_cost -> int_load [ 2 ] ) / 2 ; case scalar_store : return COSTS_N_INSNS ( fp ? ix86_cost -> sse_store [ 0 ] : ix86_cost -> int_store [ 2 ] ) / 2 ; case vector_stmt : return ix86_vec_cost ( mode , fp ? ix86_cost -> addss : ix86_cost -> sse_op , true ) ; case vector_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_load [ index ] ) / 2 , true ) ; case vector_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_store [ index ] ) / 2 , true ) ; case vec_to_scalar : case scalar_to_vec : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case unaligned_load : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_load [ index ] ) / 2 , true ) ; case unaligned_store : index = sse_store_index ( mode ) ; if ( index < 0 ) index = 2 ; return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> sse_unaligned_store [ index ] ) / 2 , true ) ; case vector_gather_load : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> gather_static + ix86_cost -> gather_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 , true ) ; case vector_scatter_store : return ix86_vec_cost ( mode , COSTS_N_INSNS ( ix86_cost -> scatter_static + ix86_cost -> scatter_per_elt * TYPE_VECTOR_SUBPARTS ( vectype ) ) / 2 , true ) ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; case vec_construct : { int cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , false ) ; if ( GET_MODE_BITSIZE ( mode ) == 256 ) cost += ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; else if ( GET_MODE_BITSIZE ( mode ) == 512 ) cost += 3 * ix86_vec_cost ( mode , ix86_cost -> addss , true ) ; return cost ; } default : gcc_unreachable ( ) ; } } </s>


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( Register :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> static void ix86_reorg ( void ) { if ( TARGET_ATHLON_K8 && optimize && ! optimize_size ) ix86_pad_returns ( ) ; if ( TARGET_FOUR_JUMP_LIMIT && optimize && ! optimize_size ) ix86_avoid_jump_misspredicts ( ) ; } </s>

Implement machine specific optimizations . We implement padding of returns for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window .


<s> static void aarch64_autovectorize_vector_sizes ( vector_sizes * sizes ) { if ( TARGET_SVE ) sizes -> safe_push ( BYTES_PER_SVE_VECTOR ) ; sizes -> safe_push ( 16 ) ; sizes -> safe_push ( 8 ) ; } </s>

Return a list of possible vector sizes for the vectorizer to iterate over .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; if ( flag_pic && crtl -> uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


"MMIX Internal: %s is not a shiftable integer"

Print operator suitable for doing something with a shiftable wyde . The type of operator is passed as an asm output modifier .


<s> void AArch64PreLegalizerCombiner :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ; AU . setPreservesCFG ( ) ; getSelectionDAGFallbackAnalysisUsage ( AU ) ; AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static rtx mips16_stub_call_address ( mips_one_only_stub * stub ) { rtx fn = mips16_stub_function ( stub -> get_name ( ) ) ; SYMBOL_REF_FLAGS ( fn ) |= SYMBOL_FLAG_LOCAL ; if ( ! call_insn_operand ( fn , VOIDmode ) ) fn = force_reg ( Pmode , fn ) ; return fn ; } </s>

Return a legitimate call address for STUB , given that STUB is a MIPS16 support function .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createNEONMoveFixPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) { PM . add ( createThumb2ITBlockPass ( ) ) ; PM . add ( createThumb2SizeReductionPass ( ) ) ; } PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; if ( ! MF ) return RegList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ; } </s>


<s> void print_operand_address ( FILE * stream , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : fprintf ( stream , "@%s" , reg_names [ true_regnum ( x ) ] ) ; break ; case PLUS : { rtx base = XEXP ( x , 0 ) ; rtx index = XEXP ( x , 1 ) ; switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , "@(%d,%s)" , ( int ) INTVAL ( index ) , reg_names [ true_regnum ( base ) ] ) ; break ; case REG : case SUBREG : { int base_num = true_regnum ( base ) ; int index_num = true_regnum ( index ) ; fprintf ( stream , "@(r0,%s)" , reg_names [ MAX ( base_num , index_num ) ] ) ; break ; } default : gcc_unreachable ( ) ; } } break ; case PRE_DEC : fprintf ( stream , "@-%s" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( stream , "@%s+" , reg_names [ true_regnum ( XEXP ( x , 0 ) ) ] ) ; break ; default : x = mark_constant_pool_use ( x ) ; output_addr_const ( stream , x ) ; break ; } } </s>

Print the operand address represented by the rtx addr


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> const OR1KSubtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getSubtargetImpl
(
)
->
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
Triple
(
TM
.
getTargetTriple
(
)
)
.
isOSDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Sparc Sparc 0 SPISD::CMPICC "SPISD::CMPICC" SPISD::CMPFCC "SPISD::CMPFCC" SPISD::BRICC "SPISD::BRICC" SPISD::BRFCC "SPISD::BRFCC" SPISD::SELECT_ICC "SPISD::SELECT_ICC" SPISD::SELECT_FCC "SPISD::SELECT_FCC" SPISD::Hi "SPISD::Hi" SPISD::Lo "SPISD::Lo" SPISD::FTOI "SPISD::FTOI" SPISD::ITOF "SPISD::ITOF" SPISD::CALL "SPISD::CALL" SPISD::RET_FLAG "SPISD::RET_FLAG"


"********** ARM MVE VPT Optimisations **********\n"

runOnMachineFunction - Emit the function body .


<s> virtual bool isVerboseAsm ( ) const { return IsVerboseAsm ; } </s>

Return true if this streamer supports verbose assembly and if it is enabled .


<s> static void mips_ls2_variable_issue ( rtx_insn * insn ) { if ( mips_ls2 . alu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu1_core_unit_code ) ) mips_ls2 . alu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . alu2_core_unit_code ) ) mips_ls2 . alu1_turn_p = true ; } if ( mips_ls2 . falu1_turn_p ) { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu1_core_unit_code ) ) mips_ls2 . falu1_turn_p = false ; } else { if ( cpu_unit_reservation_p ( curr_state , mips_ls2 . falu2_core_unit_code ) ) mips_ls2 . falu1_turn_p = true ; } if ( recog_memoized ( insn ) >= 0 ) mips_ls2 . cycle_has_multi_p |= ( get_attr_type ( insn ) == TYPE_MULTI ) ; } </s>

Update round-robin counters for ALU1/2 and FALU1/2 .


<s> const LanaiMCExpr * LanaiMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) LanaiMCExpr ( Kind , Expr ) ; } </s>


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ; return true ; } </s>

True if the stack can be realigned for the target .


<s> static rtx loongarch_pass_fpr_single ( machine_mode type_mode , unsigned regno , machine_mode value_mode , HOST_WIDE_INT offset ) { rtx x = gen_rtx_REG ( value_mode , regno ) ; if ( type_mode != value_mode ) { x = gen_rtx_EXPR_LIST ( VOIDmode , x , GEN_INT ( offset ) ) ; x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( 1 , x ) ) ; } return x ; } </s>

Return the representation of an argument passed or returned in an FPR when the value has mode VALUE_MODE and the type has TYPE_MODE . The two modes may be different for structures like : struct __attribute__ ( ( packed ) ) foo { float f ; } where the SFmode value `` f '' is passed in REGNO but the struct itself has mode BLKmode .


<s> bool MipsTargetLowering :: hasBitTest ( SDValue X , SDValue Y ) const { if ( auto * C = dyn_cast < ConstantSDNode > ( Y ) ) return C -> getAPIntValue ( ) . ule ( 15 ) ; return false ; } </s>

Return true if the target has a bit-test instruction : ( X & ( 1 < < Y ) ) ==/ ! = 0 This knowledge can be used to prevent breaking the pattern , or creating it if it could be recognized .


<s> tree resolve ( function_resolver & r ) const OVERRIDE { unsigned int i , nargs ; type_suffix_index type ; if ( ! r . check_gp_argument ( 1 , i , nargs ) || ( type = r . infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; if ( type == TYPE_SUFFIX_b ) return r . resolve_to ( r . mode_suffix_id , type ) ; if ( type_suffixes [ type ] . integer_p && type_suffixes [ type ] . element_bits < 64 ) { type_suffix_index wide_suffix = find_type_suffix ( type_suffixes [ type ] . tclass , type_suffixes [ type ] . element_bits * 2 ) ; if ( tree res = r . lookup_form ( r . mode_suffix_id , wide_suffix ) ) return res ; } return r . report_no_such_form ( type ) ; } </s>

If the call is erroneous , report an appropriate error and return error_mark_node . Otherwise , if the function is overloaded , return the decl of the non-overloaded function . Return NULL_TREE otherwise , indicating that the call should be processed in the normal way .


<s>
bool
AArch64InstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
*
MIa
,
MachineInstr
*
MIb
,
AliasAnalysis
*
AA
)
const
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int
OffsetA
=
0
,
OffsetB
=
0
;
int
WidthA
=
0
,
WidthB
=
0
;
assert
(
MIa
&&
MIa
->
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
&&
MIb
->
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
->
hasUnmodeledSideEffects
(
)
||
MIb
->
hasUnmodeledSideEffects
(
)
||
MIa
->
hasOrderedMemoryRef
(
)
||
MIb
->
hasOrderedMemoryRef
(
)
)
return
false
;
if
(
getLdStBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getLdStBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
OffsetA
<
OffsetB
OffsetA
:
OffsetB
;
int
HighOffset
=
OffsetA
<
OffsetB
OffsetB
:
OffsetA
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> const uint32_t * CSKYRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const CSKYSubtarget & STI = MF . getSubtarget < CSKYSubtarget > ( ) ; if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64_RegMask ; if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32_RegMask ; return CSR_I32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SMLoc getEndLoc ( ) const { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
else
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> unsigned X86TargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & , unsigned Depth ) const { if ( Op . getOpcode ( ) == X86ISD :: SETCC_CARRY ) return Op . getValueType ( ) . getScalarType ( ) . getSizeInBits ( ) ; return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
Register
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
&
ARM
::
tGPRRegClass
||
(
Register
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlign
(
FI
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegClass
ARM
"Unknown regclass!"
ARM::tGPRRegClass
ARM
ARM::tSTRspi
0
ARMCC::AL


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void X86TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) || Subtarget . getTargetTriple ( ) . isWindowsItaniumEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; auto * SecurityCheckCookie = cast < Function > ( M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ) ; SecurityCheckCookie -> setCallingConv ( CallingConv :: X86_FastCall ) ; SecurityCheckCookie -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; return ; } if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) return ; TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


<s> static const char * ia64_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == float128_type_node || type == float64x_type_node ) return NULL ; if ( ! TARGET_HPUX && TYPE_MODE ( type ) == TFmode ) return "g" ; if ( TYPE_MODE ( type ) == XFmode ) return TARGET_HPUX ? "u9__float80" : "e" ; if ( TYPE_MODE ( type ) == RFmode ) return "u7__fpreg" ; return NULL ; } </s>

Return the mangling of TYPE if it is an extended fundamental type .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) . getReg ( 0 ) ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> void arm_output_fn_unwind ( FILE * f , bool prologue ) { if ( ! ARM_EABI_UNWIND_TABLES ) return ; if ( prologue ) fputs ( "\t.fnstart\n" , f ) ; else fputs ( "\t.fnend\n" , f ) ; } </s>

Output unwind directives for the start/end of a function .


<s> static rtx aarch64_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ; int count ; machine_mode ag_mode ; mode = TYPE_MODE ( type ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; if ( aarch64_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = int_mode_for_size ( size * BITS_PER_UNIT , 0 ) . require ( ) ; } } if ( aarch64_vfp_is_call_or_return_candidate ( mode , type , & ag_mode , & count , NULL ) ) { if ( ! aarch64_composite_type_p ( type , mode ) ) { gcc_assert ( count == 1 && mode == ag_mode ) ; return gen_rtx_REG ( mode , V0_REGNUM ) ; } else { int i ; rtx par ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , V0_REGNUM + i ) ; rtx offset = gen_int_mode ( i * GET_MODE_SIZE ( ag_mode ) , Pmode ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , offset ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } } else return gen_rtx_REG ( mode , R0_REGNUM ) ; } </s>

Implement TARGET_FUNCTION_VALUE . Define how to find the value returned by a function .


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel" "ppc-got" "ppc-opt-pcrel" "ppc-tlsgd" "ppc-tlsld" "ppc-tprel" "ppc-got-tlsgd-pcrel" "ppc-got-tlsld-pcrel" "ppc-got-tprel-pcrel"


<s> void Cpu0MCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> static bool cortex_a9_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int * cost ) { switch ( dep_type ) { case REG_DEP_ANTI : * cost = 0 ; return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - 3 ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( dep_type == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + 1 ; else * cost = insn_default_latency ( dep ) ; } return false ; } } } } break ; default : gcc_unreachable ( ) ; } return true ; } </s>


<s> const AArch64Subtarget * getSubtarget ( ) const { return & getTargetMachine ( ) . getSubtarget < AArch64Subtarget > ( ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> TargetTransformInfo VETargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( VETTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain ) { for ( unsigned i = 0 , e = array_lengthof ( ReplaceableInstrs ) ; i != e ; ++ i ) if ( ReplaceableInstrs [ i ] [ domain - 1 ] == opcode ) return ReplaceableInstrs [ i ] ; return nullptr ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> void emitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) override { emitDataMappingSymbol ( ) ; MCELFStreamer :: emitValueImpl ( Value , Size , Loc ) ; } </s>

Overriding these functions allows us to dismiss all labels that are candidates for marking as microMIPS when .word/.long/.4byte etc directives are emitted .


<s> static bool iq2000_handle_option ( size_t code , const char * arg , int value ATTRIBUTE_UNUSED ) { switch ( code ) { case OPT_mcpu_ : if ( strcmp ( arg , "iq10" ) == 0 ) iq2000_tune = PROCESSOR_IQ10 ; else if ( strcmp ( arg , "iq2000" ) == 0 ) iq2000_tune = PROCESSOR_IQ2000 ; else return false ; return true ; case OPT_march_ : return ( strcmp ( arg , "default" ) == 0 || strcmp ( arg , "DEFAULT" ) == 0 || strcmp ( arg , "iq2000" ) == 0 ) ; default : return true ; } } </s>


<s> SDNode * SICDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < SICFunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool arm_can_output_mi_thunk ( const_tree , HOST_WIDE_INT , HOST_WIDE_INT vcall_offset , const_tree ) { if ( vcall_offset && TARGET_THUMB1 ) return false ; return true ; } </s>

Can output mi_thunk for all cases except for non-zero vcall_offset in Thumb1 .


<s> bool ia64_extra_constraint ( rtx value , char c ) { switch ( c ) { case 'Q' : return memory_operand ( value , VOIDmode ) && ! MEM_VOLATILE_P ( value ) ; case 'R' : return ( GET_CODE ( value ) == CONST_INT && INTVAL ( value ) >= 1 && INTVAL ( value ) <= 4 ) ; case 'S' : return ( GET_CODE ( value ) == MEM && GET_RTX_CLASS ( GET_CODE ( XEXP ( value , 0 ) ) ) != RTX_AUTOINC && ( reload_in_progress || memory_operand ( value , VOIDmode ) ) ) ; case 'T' : return small_addr_symbolic_operand ( value , VOIDmode ) ; case 'U' : return value == CONST0_RTX ( GET_MODE ( value ) ) ; case 'W' : if ( GET_CODE ( value ) == CONST_VECTOR && GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_VECTOR_INT ) { value = simplify_subreg ( DImode , value , GET_MODE ( value ) , 0 ) ; return ia64_const_ok_for_letter_p ( INTVAL ( value ) , 'J' ) ; } return false ; case 'Y' : return ( GET_CODE ( value ) == CONST_VECTOR && GET_MODE ( value ) == V2SFmode && ia64_const_double_ok_for_letter_p ( XVECEXP ( value , 0 , 0 ) , 'G' ) && ia64_const_double_ok_for_letter_p ( XVECEXP ( value , 0 , 1 ) , 'G' ) ) ; default : return false ; } } </s>


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const ARMSubtarget & Subtarget = DAG . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; if ( ! Subtarget . isAAPCS_ABI ( ) || Subtarget . isTargetMachO ( ) || Subtarget . isTargetWindows ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; addPass ( createX86LowerAMXIntrinsicsPass ( ) ) ; addPass ( createX86LowerAMXTypePass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) addPass ( createX86PreAMXConfigPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createX86PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ; } else { addPass ( createCFGuardCheckPass ( ) ) ; } } if ( TM -> Options . JMCInstrument ) addPass ( createJMCInstrumenterPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void x86_order_regs_for_local_alloc ( void ) { int pos = 0 ; int i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && call_used_or_fixed_reg_p ( i ) ) reg_alloc_order [ pos ++ ] = i ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( GENERAL_REGNO_P ( i ) && ! call_used_or_fixed_reg_p ( i ) ) reg_alloc_order [ pos ++ ] = i ; if ( ! TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_SSE_REG ; i <= LAST_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; if ( TARGET_SSE_MATH ) for ( i = FIRST_STACK_REG ; i <= LAST_STACK_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; for ( i = FIRST_MMX_REG ; i <= LAST_MMX_REG ; i ++ ) reg_alloc_order [ pos ++ ] = i ; while ( pos < FIRST_PSEUDO_REGISTER ) reg_alloc_order [ pos ++ ] = 0 ; } </s>

Order the registers for register allocator .


"The .note.gnu.property is not emitted because it is already present."

Callback used to implement the .note.gnu.property section .


<s> const ThumbRegisterInfo & getRegisterInfo ( ) const override { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static int gen_v9_scc ( rtx dest , enum rtx_code compare_code , rtx x , rtx y ) { if ( ! TARGET_ARCH64 && ( GET_MODE ( x ) == DImode || GET_MODE ( dest ) == DImode ) ) return 0 ; if ( TARGET_ARCH64 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_INT && y == const0_rtx && v9_regcmp_p ( compare_code ) ) { rtx op0 = x ; rtx temp ; if ( compare_code == NE && GET_MODE ( dest ) == DImode && rtx_equal_p ( op0 , dest ) ) { emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( DImode , gen_rtx_fmt_ee ( compare_code , DImode , op0 , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } if ( reg_overlap_mentioned_p ( dest , op0 ) ) { op0 = gen_reg_rtx ( GET_MODE ( x ) ) ; emit_move_insn ( op0 , x ) ; } emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; if ( GET_MODE ( op0 ) != DImode ) { temp = gen_reg_rtx ( DImode ) ; convert_move ( temp , op0 , 0 ) ; } else temp = op0 ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , DImode , temp , const0_rtx ) , const1_rtx , dest ) ) ) ; return 1 ; } else { x = gen_compare_reg_1 ( compare_code , x , y ) ; y = const0_rtx ; gcc_assert ( GET_MODE ( x ) != CC_NOOVmode && GET_MODE ( x ) != CCX_NOOVmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IF_THEN_ELSE ( GET_MODE ( dest ) , gen_rtx_fmt_ee ( compare_code , GET_MODE ( x ) , x , y ) , const1_rtx , dest ) ) ) ; return 1 ; } } </s>

This function is used for v9 only . CODE is the code for an Scc 's comparison . OPERANDS [ 0 ] is the target of the Scc insn . OPERANDS [ 1 ] is the value we compare against const0_rtx ( which has n't been generated yet ) . This function is needed to turn ( set ( reg : SI 110 ) ( gt ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) into ( set ( reg : SI 110 ) ( gt : DI ( reg : CCX 100 % icc ) ( const_int 0 ) ) ) IE : The instruction recognizer needs to see the mode of the comparison to find the right instruction . We could use `` gt : DI '' right in the define_expand , but leaving it out allows us to handle DI , SI , etc . We refer to the global sparc compare operands sparc_compare_op0 and sparc_compare_op1 .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> unsigned X86FastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return X86MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return X86MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return X86MaterializeGV ( GV , VT ) ; else if ( isa < UndefValue > ( C ) ) { unsigned Opc = 0 ; switch ( VT . SimpleTy ) { default : break ; case MVT :: f32 : if ( ! X86ScalarSSEf32 ) Opc = X86 :: LD_Fp032 ; break ; case MVT :: f64 : if ( ! X86ScalarSSEf64 ) Opc = X86 :: LD_Fp064 ; break ; case MVT :: f80 : Opc = X86 :: LD_Fp080 ; break ; } if ( Opc ) { Register ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ; } } return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s> static section * pa_elf_select_rtx_section ( machine_mode mode , rtx x , unsigned HOST_WIDE_INT align ) { if ( function_label_operand ( x , VOIDmode ) ) { tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl || ( DECL_P ( decl ) && DECL_COMDAT_GROUP ( decl ) ) ) return get_named_section ( NULL , ".data.rel.ro.local" , 1 ) ; } return default_elf_select_rtx_section ( mode , x , align ) ; } </s>

Implement pa_elf_select_rtx_section . If X is a function label operand and the function is in a COMDAT group , place the plabel reference in the .data.rel.ro.local section . The linker ignores references to symbols in discarded sections from this section .


<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmaxl" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "roundl" , "sinl" , "sqrtl" , "truncl" } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < 0 ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
AsmVariant
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
printSymbolOperand
(
*
this
,
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
case
'V'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
printOperand
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
printPCRelImm
(
*
this
,
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
printOperand
(
*
this
,
MI
,
OpNo
,
O
,
nullptr
,
AsmVariant
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: EXTRACT_VECTOR_ELT : return PerformEXTRACT_VECTOR_ELTCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; case X86ISD :: SHUFPS : case X86ISD :: SHUFPD : case X86ISD :: PALIGN : case X86ISD :: PUNPCKHBW : case X86ISD :: PUNPCKHWD : case X86ISD :: PUNPCKHDQ : case X86ISD :: PUNPCKHQDQ : case X86ISD :: UNPCKHPS : case X86ISD :: UNPCKHPD : case X86ISD :: PUNPCKLBW : case X86ISD :: PUNPCKLWD : case X86ISD :: PUNPCKLDQ : case X86ISD :: PUNPCKLQDQ : case X86ISD :: UNPCKLPS : case X86ISD :: UNPCKLPD : case X86ISD :: MOVHLPS : case X86ISD :: MOVLHPS : case X86ISD :: PSHUFD : case X86ISD :: PSHUFHW : case X86ISD :: PSHUFLW : case X86ISD :: MOVSS : case X86ISD :: MOVSD : case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void ix86_initialize_callee_abi ( unsigned int abi_id ) { gcc_assert ( abi_id == ABI_VZEROUPPER ) ; predefined_function_abi & vzeroupper_abi = function_abis [ abi_id ] ; if ( ! vzeroupper_abi . initialized_p ( ) ) { HARD_REG_SET full_reg_clobbers ; CLEAR_HARD_REG_SET ( full_reg_clobbers ) ; vzeroupper_abi . initialize ( ABI_VZEROUPPER , full_reg_clobbers ) ; } } </s>

Initialize function_abis with corresponding abi_id , currently only handle vzeroupper .


doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
Register
OutgoingValueHandler
::
extendRegister
(
Register
ValReg
,
const
CCValAssign
&
VA
)
{
LLT
LocTy
{
VA
.
getLocVT
(
)
}
;
switch
(
VA
.
getLocInfo
(
)
)
{
case
CCValAssign
::
SExt
:
{
Register
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildSExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
ZExt
:
{
Register
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildZExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
AExt
:
{
Register
ExtReg
=
MRI
.
createGenericVirtualRegister
(
LocTy
)
;
MIRBuilder
.
buildAnyExt
(
ExtReg
,
ValReg
)
;
return
ExtReg
;
}
case
CCValAssign
::
Full
:
return
ValReg
;
default
:
break
;
}
llvm_unreachable
(
"unable to extend register"
)
;
}
</s>

Extend a register to the location type given in VA , capped at extending to at most MaxSize bits .


<s> rtx mve_bool_vec_to_const ( rtx const_vec ) { int n_elts = GET_MODE_NUNITS ( GET_MODE ( const_vec ) ) ; int repeat = 16 / n_elts ; int i ; int hi_val = 0 ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( const_vec , i ) ; unsigned HOST_WIDE_INT elpart ; gcc_assert ( CONST_INT_P ( el ) ) ; elpart = INTVAL ( el ) ; for ( int j = 0 ; j < repeat ; j ++ ) hi_val |= elpart << ( i * repeat + j ) ; } return gen_int_mode ( hi_val , HImode ) ; } </s>

Return a HI representation of CONST_VEC suitable for MVE predicates .


<s> int X86FrameLowering :: mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , bool doMergeWithPrevious ) const { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? std :: prev ( MBBI ) : MBBI ; PI = skipDebugInstructionsBackward ( PI , MBB . begin ( ) ) ; if ( doMergeWithPrevious && PI != MBB . begin ( ) && PI -> isCFIInstruction ( ) ) PI = std :: prev ( PI ) ; unsigned Opc = PI -> getOpcode ( ) ; int Offset = 0 ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = PI -> getOperand ( 2 ) . getImm ( ) ; } else if ( ( Opc == X86 :: LEA32r || Opc == X86 :: LEA64_32r ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr && PI -> getOperand ( 1 ) . getReg ( ) == StackPtr && PI -> getOperand ( 2 ) . getImm ( ) == 1 && PI -> getOperand ( 3 ) . getReg ( ) == X86 :: NoRegister && PI -> getOperand ( 5 ) . getReg ( ) == X86 :: NoRegister ) { Offset = PI -> getOperand ( 4 ) . getImm ( ) ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { assert ( PI -> getOperand ( 1 ) . getReg ( ) == StackPtr ) ; Offset = - PI -> getOperand ( 2 ) . getImm ( ) ; } else return 0 ; PI = MBB . erase ( PI ) ; if ( PI != MBB . end ( ) && PI -> isCFIInstruction ( ) ) PI = MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = skipDebugInstructionsForward ( PI , MBB . end ( ) ) ; return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = NULL ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , ELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> unsigned PPCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == PPC :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { return MI . getOperand ( 1 ) . getImm ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getMetaOper ( PatchPointOpers :: NBytesPos ) . getImm ( ) ; } else { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> int nds32_target_alignment ( rtx_insn * label ) { rtx_insn * insn ; if ( ! NDS32_ALIGN_P ( ) ) return 0 ; insn = next_active_insn ( label ) ; if ( insn == 0 || ( get_attr_length ( insn ) == 2 && ! JUMP_P ( insn ) && ! CALL_P ( insn ) ) ) return 0 ; else return 2 ; } </s>

Return align 2 ( log base 2 ) if the next instruction of LABEL is 4 byte .


<s>
virtual
const
X86InstrInfo
*
getInstrInfo
(
)
const
{
llvm_unreachable
(
"getInstrInfo not implemented"
)
;
}
</s>


<s> static bool or1k_cannot_force_const_mem ( machine_mode , rtx x ) { rtx_code code = GET_CODE ( x ) ; return ( code == SYMBOL_REF || code == LABEL_REF || code == CONST || code == HIGH ) ; } </s>

Worker for TARGET_CANNOT_FORCE_CONST_MEM . Primarily this is required for TLS symbols , but given that our move patterns * ought * to be able to handle any symbol at any time , we should never be spilling symbolic operands to the constant pool , ever .


<s> static size_t find_field ( const std :: string & field , const std :: string & key ) { size_t key_pos , sep_pos ; key_pos = field . find ( key ) ; if ( key_pos == std :: string :: npos ) return std :: string :: npos ; sep_pos = field . find ( ":" , key_pos + 1 ) ; if ( sep_pos == std :: string :: npos ) return std :: string :: npos ; return sep_pos ; } </s>

Returns the index of the ' : ' inside the FIELD which must be found after the value of KEY . Returns string : :npos if line does not contain a field .


<s> const char * function_resolver :: get_scalar_type_name ( type_suffix_index type ) { return vector_types [ type_suffixes [ type ] . vector_type ] . acle_name + 2 ; } </s>

Return the < stdint.h > name associated with TYPE . Using the < stdint.h > name should be more user-friendly than the underlying canonical type , since it makes the signedness and bitwidth explicit .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> MCSymbol * AArch64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ 0 ] ) return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> bool mips_dangerous_for_la25_p ( rtx x ) { return ( ! TARGET_EXPLICIT_RELOCS && TARGET_USE_GOT && GET_CODE ( x ) == SYMBOL_REF && mips_global_symbol_p ( x ) ) ; } </s>

Return true if X should not be moved directly into register $ 25 . We need this because many versions of GAS will treat `` la $ 25 , foo '' as part of a call sequence and so allow a global `` foo '' to be lazily bound .


<s> rtx pru_expand_fp_compare ( rtx comparison , machine_mode mode ) { enum rtx_code code = GET_CODE ( comparison ) ; rtx op0 = XEXP ( comparison , 0 ) ; rtx op1 = XEXP ( comparison , 1 ) ; rtx cmp ; enum rtx_code jump_code = code ; machine_mode op_mode = GET_MODE ( op0 ) ; rtx_insn * insns ; rtx libfunc ; gcc_assert ( op_mode == DFmode || op_mode == SFmode ) ; if ( code == UNGE ) { code = LT ; jump_code = EQ ; } else if ( code == UNLE ) { code = GT ; jump_code = EQ ; } else jump_code = NE ; switch ( code ) { case EQ : libfunc = op_mode == DFmode ? eqdf_libfunc : eqsf_libfunc ; break ; case NE : libfunc = op_mode == DFmode ? nedf_libfunc : nesf_libfunc ; break ; case GT : libfunc = op_mode == DFmode ? gtdf_libfunc : gtsf_libfunc ; break ; case GE : libfunc = op_mode == DFmode ? gedf_libfunc : gesf_libfunc ; break ; case LT : libfunc = op_mode == DFmode ? ltdf_libfunc : ltsf_libfunc ; break ; case LE : libfunc = op_mode == DFmode ? ledf_libfunc : lesf_libfunc ; break ; default : gcc_unreachable ( ) ; } start_sequence ( ) ; cmp = emit_library_call_value ( libfunc , 0 , LCT_CONST , SImode , op0 , op_mode , op1 , op_mode ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) ; return gen_rtx_fmt_ee ( jump_code , mode , cmp , const0_rtx ) ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode . Return the comparison that should be used in the jump insn .


<s> bool mem_operand_ds_form ( rtx op , machine_mode mode ) { unsigned HOST_WIDE_INT offset ; int extra ; rtx addr = XEXP ( op , 0 ) ; if ( ! offsettable_address_p ( false , mode , addr ) ) return false ; op = address_offset ( addr ) ; if ( op == NULL_RTX ) return true ; offset = INTVAL ( op ) ; if ( ( offset & 3 ) != 0 ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < 0 ) extra = 0 ; if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; return offset + 0x8000 < 0x10000u - extra ; } </s>

As above , but for DS-FORM VSX insns . Unlike mem_operand_gpr , enforce an offset divisible by 4 even for 32-bit .


<s> void OpenRISCAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { OpenRISCMCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static int sparc_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { bool need_memory = false ; if ( from == NO_REGS || to == NO_REGS ) return 100 ; if ( from == FPCC_REGS || to == FPCC_REGS ) need_memory = true ; else if ( ( FP_REG_CLASS_P ( from ) && general_or_i64_p ( to ) ) || ( general_or_i64_p ( from ) && FP_REG_CLASS_P ( to ) ) ) { if ( TARGET_VIS3 ) { int size = GET_MODE_SIZE ( mode ) ; if ( size == 8 || size == 4 ) { if ( ! TARGET_ARCH32 || size == 4 ) return 4 ; else return 6 ; } } need_memory = true ; } if ( need_memory ) { if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA || sparc_cpu == PROCESSOR_NIAGARA2 || sparc_cpu == PROCESSOR_NIAGARA3 || sparc_cpu == PROCESSOR_NIAGARA4 || sparc_cpu == PROCESSOR_NIAGARA7 || sparc_cpu == PROCESSOR_M8 ) return 12 ; return 6 ; } return 2 ; } </s>


<s> bool func_fma_steering :: put_node ( fma_node * node ) { return this -> m_insn_fma_head_map -> put ( node -> get_insn ( ) , node ) ; } </s>

Memorize the mapping of this instruction to its fma_node object and return whether such a mapping existed .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) && Subtarget -> getStackAlignment ( ) >= 16 ) { if ( Subtarget -> hasAVX ( ) && Subtarget -> getStackAlignment ( ) >= 32 ) return MVT :: v8f32 ; if ( Subtarget -> hasXMMInt ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasXMM ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= 8 && Subtarget -> hasXMMInt ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static inline bool fp_valid_at ( HOST_WIDE_INT cfa_offset ) { const struct machine_frame_state & fs = cfun -> machine -> fs ; if ( fs . sp_realigned && cfa_offset > fs . sp_realigned_fp_last ) { gcc_assert ( cfa_offset >= fs . sp_realigned_offset ) ; return false ; } return fs . fp_valid ; } </s>

Determine if the frame pointer is valid for accessing the CFA_OFFSET in the frame save area . The register is saved at CFA - CFA_OFFSET .


<s> void mips16_expand_set_fcsr ( rtx newval ) { if ( ! mips16_set_fcsr_stub ) mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ( ) ; rtx fn = mips16_stub_call_address ( mips16_set_fcsr_stub ) ; emit_move_insn ( gen_rtx_REG ( SImode , SET_FCSR_REGNUM ) , newval ) ; emit_insn ( PMODE_INSN ( gen_mips_set_fcsr_mips16 , ( fn ) ) ) ; } </s>

Implement __builtin_mips_set_fcsr ( TARGET ) for MIPS16 , using a stub .


<s>
static
void
arm_unwind_emit
(
FILE
*
out_file
,
rtx_insn
*
insn
)
{
rtx
note
,
pat
;
bool
handled_one
=
false
;
if
(
arm_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
if
(
!
(
flag_unwind_tables
||
crtl
->
uses_eh_lsda
)
&&
(
TREE_NOTHROW
(
current_function_decl
)
||
crtl
->
all_throwers_are_sibcalls
)
)
return
;
if
(
NOTE_P
(
insn
)
||
!
RTX_FRAME_RELATED_P
(
insn
)
)
return
;
for
(
note
=
REG_NOTES
(
insn
)
;
note
;
note
=
XEXP
(
note
,
1
)
)
{
switch
(
REG_NOTE_KIND
(
note
)
)
{
case
REG_FRAME_RELATED_EXPR
:
pat
=
XEXP
(
note
,
0
)
;
goto
found
;
case
REG_CFA_REGISTER
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
{
pat
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pat
)
==
PARALLEL
)
pat
=
XVECEXP
(
pat
,
0
,
0
)
;
}
{
rtx
dest
,
src
;
unsigned
reg
;
src
=
SET_SRC
(
pat
)
;
dest
=
SET_DEST
(
pat
)
;
gcc_assert
(
src
==
stack_pointer_rtx
)
;
reg
=
REGNO
(
dest
)
;
asm_fprintf
(
out_file
,
"\t.unwind_raw 0, 0x%x @ vsp = r%d\n"
,
reg
+
0x90
,
reg
)
;
}
handled_one
=
true
;
break
;
case
REG_CFA_DEF_CFA
:
case
REG_CFA_ADJUST_CFA
:
case
REG_CFA_RESTORE
:
return
;
case
REG_CFA_EXPRESSION
:
case
REG_CFA_OFFSET
:
gcc_unreachable
(
)
;
default
:
break
;
}
}
if
(
handled_one
)
return
;
pat
=
PATTERN
(
insn
)
;
found
:
switch
(
GET_CODE
(
pat
)
)
{
case
SET
:
arm_unwind_emit_set
(
out_file
,
pat
)
;
break
;
case
SEQUENCE
:
arm_unwind_emit_sequence
(
out_file
,
pat
)
;
break
;
default
:
abort
(
)
;
}
}
</s>

Emit unwind directives for the given insn .


<s>
void
Mips16InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOLoad
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
LwRxSpImmX16
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> void gen_conditional_branch ( rtx operands [ ] , machine_mode mode ) { enum rtx_code test_code = GET_CODE ( operands [ 0 ] ) ; rtx cmp0 = operands [ 1 ] ; rtx cmp1 = operands [ 2 ] ; rtx reg ; int invert ; rtx label1 , label2 ; invert = 0 ; reg = gen_int_relational ( test_code , NULL_RTX , cmp0 , cmp1 , & invert ) ; if ( reg ) { cmp0 = reg ; cmp1 = const0_rtx ; test_code = NE ; } else if ( GET_CODE ( cmp1 ) == CONST_INT && INTVAL ( cmp1 ) != 0 ) cmp1 = force_reg ( mode , cmp1 ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; label2 = pc_rtx ; if ( invert ) { label2 = label1 ; label1 = pc_rtx ; } emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) , label1 , label2 ) ) ) ; } </s>

Emit the common code for doing conditional branches . operand [ 0 ] is the label to jump to . The comparison operands are saved away by cmp { si , di , sf , df } .


<s> static rtx mips_expand_builtin_movtf ( enum mips_builtin_type type , enum insn_code icode , enum mips_fp_condition cond , rtx target , tree arglist ) { rtx cmp_result , op0 , op1 ; cmp_result = mips_prepare_builtin_target ( icode , 0 , 0 ) ; op0 = mips_prepare_builtin_arg ( icode , 1 , & arglist ) ; op1 = mips_prepare_builtin_arg ( icode , 2 , & arglist ) ; emit_insn ( GEN_FCN ( icode ) ( cmp_result , op0 , op1 , GEN_INT ( cond ) ) ) ; icode = CODE_FOR_mips_cond_move_tf_ps ; target = mips_prepare_builtin_target ( icode , 0 , target ) ; if ( type == MIPS_BUILTIN_MOVT ) { op1 = mips_prepare_builtin_arg ( icode , 2 , & arglist ) ; op0 = mips_prepare_builtin_arg ( icode , 1 , & arglist ) ; } else { op0 = mips_prepare_builtin_arg ( icode , 1 , & arglist ) ; op1 = mips_prepare_builtin_arg ( icode , 2 , & arglist ) ; } emit_insn ( gen_mips_cond_move_tf_ps ( target , op0 , op1 , cmp_result ) ) ; return target ; } </s>

Expand a __builtin_mips_movt_ * _ps ( ) or __builtin_mips_movf_ * _ps ( ) function ( TYPE says which ) . ARGLIST is the list of arguments to the function , ICODE is the instruction that should be used to compare the first two arguments , and COND is the condition it should test . TARGET , if nonnull , suggests a good place to put the result .


<s> static void emit_constant_insn ( rtx cond , rtx pattern ) { if ( cond ) pattern = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , pattern ) ; emit_insn ( pattern ) ; } </s>

Emit an instruction with the indicated PATTERN . If COND is non-NULL , conditionalize the execution of the instruction on COND being true .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
,
bool
isVarArg
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
if
(
Subtarget
->
hasVFP2
(
)
&&
!
isVarArg
)
{
if
(
!
Subtarget
->
isAAPCS_ABI
(
)
)
return
(
Return
RetFastCC_ARM_APCS
:
FastCC_ARM_APCS
)
;
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
}
LLVM_FALLTHROUGH
;
case
CallingConv
::
C
:
case
CallingConv
::
CXX_FAST_TLS
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
TM
.
Options
.
FloatABIType
==
FloatABI
::
Hard
&&
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
{
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
case
CallingConv
::
ARM_AAPCS_VFP
:
case
CallingConv
::
Swift
:
if
(
!
isVarArg
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
LLVM_FALLTHROUGH
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
GHC
:
if
(
Return
)
llvm_unreachable
(
"Can't return in GHC call convention"
)
;
else
return
CC_ARM_APCS_GHC
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
"Can't return in GHC call convention"
ARM


<s> void PPCPassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCBoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( createPPCLowerMASSVEntriesPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnablePPCGenScalarMASSEntries ) { TM -> Options . PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries ; addPass ( createPPCGenScalarMASSEntriesPass ( ) ) ; } if ( EnablePrefetch . getNumOccurrences ( ) > 0 ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .