<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , const DebugLoc & dl , const ThumbRegisterInfo & MRI , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


"X86-specific target pass should not be run without a target "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool nds32_n10_last_load_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; return n10_consumed_by_ex_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to EX .


Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
bool
FISCDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
OutOps
.
push_back
(
Op
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

FISC
FISC
"Unexpected asm memory constraint"


<s> SDValue OR1KTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_OR1K32 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static rtx aarch64_function_value ( const_tree type , const_tree func , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; int unsignedp ; int count ; machine_mode ag_mode ; mode = TYPE_MODE ( type ) ; if ( INTEGRAL_TYPE_P ( type ) ) mode = promote_function_mode ( type , mode , & unsignedp , func , 1 ) ; if ( aarch64_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != 0 ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = mode_for_size ( size * BITS_PER_UNIT , MODE_INT , 0 ) ; } } if ( aarch64_vfp_is_call_or_return_candidate ( mode , type , & ag_mode , & count , NULL ) ) { if ( ! aarch64_composite_type_p ( type , mode ) ) { gcc_assert ( count == 1 && mode == ag_mode ) ; return gen_rtx_REG ( mode , V0_REGNUM ) ; } else { int i ; rtx par ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , V0_REGNUM + i ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } } else return gen_rtx_REG ( mode , R0_REGNUM ) ; } </s>

Implement TARGET_FUNCTION_VALUE . Define how to find the value returned by a function .


<s> void PPCHazardRecognizer970 :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugValue ( ) ) return ; unsigned Opcode = MI -> getOpcode ( ) ; LastWasBL8_ELF = ( Opcode == PPC :: BL8_ELF ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; PPCII :: PPC970_Unit InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == PPCII :: PPC970_Pseudo ) return ; if ( Opcode == PPC :: MTCTR || Opcode == PPC :: MTCTR8 ) HasCTRSet = true ; if ( isStore && NumStores < 4 && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO -> getSize ( ) ; StoreOffset [ NumStores ] = MO -> getOffset ( ) ; StoreValue [ NumStores ] = MO -> getValue ( ) ; ++ NumStores ; } if ( InstrType == PPCII :: PPC970_BRU || isSingle ) NumIssued = 4 ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == 5 ) EndDispatchGroup ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"getBranchTargetOpValuePC10 expects only expressions or immediates"

getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand .


<s> const node_value_type & getValue ( ) const { return Value ; } </s>


<s> static void get_pc_thunk_name ( char name [ 32 ] , unsigned int regno ) { gcc_assert ( ! TARGET_64BIT ) ; if ( USE_HIDDEN_LINKONCE ) sprintf ( name , "__x86.get_pc_thunk.%s" , reg_names [ regno ] ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , "LPR" , regno ) ; } </s>

Fills in the label name that should be used for a pc thunk for the given register .


<s> void aarch64_expand_mov_immediate ( rtx dest , rtx imm ) { machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( mode == SImode || mode == DImode ) ; if ( GET_CODE ( imm ) == SYMBOL_REF || GET_CODE ( imm ) == LABEL_REF || GET_CODE ( imm ) == CONST ) { rtx mem , base , offset ; enum aarch64_symbol_type sty ; split_const ( imm , & base , & offset ) ; sty = aarch64_classify_symbol ( base , offset ) ; switch ( sty ) { case SYMBOL_FORCE_TO_MEM : if ( offset != const0_rtx && targetm . cannot_force_const_mem ( mode , imm ) ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } mem = force_const_mem ( ptr_mode , imm ) ; gcc_assert ( mem ) ; if ( ! aarch64_pcrelative_literal_loads ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = gen_reg_rtx ( ptr_mode ) ; aarch64_expand_mov_immediate ( base , XEXP ( mem , 0 ) ) ; mem = gen_rtx_MEM ( ptr_mode , base ) ; } if ( mode != ptr_mode ) mem = gen_rtx_ZERO_EXTEND ( mode , mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; return ; case SYMBOL_SMALL_TLSGD : case SYMBOL_SMALL_TLSDESC : case SYMBOL_SMALL_TLSIE : case SYMBOL_SMALL_GOT_28K : case SYMBOL_SMALL_GOT_4G : case SYMBOL_TINY_GOT : case SYMBOL_TINY_TLSIE : if ( offset != const0_rtx ) { gcc_assert ( can_create_pseudo_p ( ) ) ; base = aarch64_force_temporary ( mode , dest , base ) ; base = aarch64_add_offset ( mode , NULL , base , INTVAL ( offset ) ) ; aarch64_emit_move ( dest , base ) ; return ; } case SYMBOL_SMALL_ABSOLUTE : case SYMBOL_TINY_ABSOLUTE : case SYMBOL_TLSLE12 : case SYMBOL_TLSLE24 : case SYMBOL_TLSLE32 : case SYMBOL_TLSLE48 : aarch64_load_symref_appropriately ( dest , imm , sty ) ; return ; default : gcc_unreachable ( ) ; } } if ( ! CONST_INT_P ( imm ) ) { if ( GET_CODE ( imm ) == HIGH ) emit_insn ( gen_rtx_SET ( dest , imm ) ) ; else { rtx mem = force_const_mem ( mode , imm ) ; gcc_assert ( mem ) ; emit_insn ( gen_rtx_SET ( dest , mem ) ) ; } return ; } aarch64_internal_mov_immediate ( dest , imm , true , GET_MODE ( dest ) ) ; } </s>

Set DEST to immediate IMM . For SVE vector modes , GEN_VEC_DUPLICATE is a pattern that can be used to set DEST to a replicated scalar element .


<s> static rtx mips_builtin_branch_and_move ( rtx condition , rtx target , rtx value_if_true , rtx value_if_false ) { rtx_code_label * true_label , * done_label ; true_label = gen_label_rtx ( ) ; done_label = gen_label_rtx ( ) ; mips_emit_move ( target , value_if_false ) ; emit_jump_insn ( gen_condjump ( condition , true_label ) ) ; emit_jump_insn ( gen_jump ( done_label ) ) ; emit_barrier ( ) ; emit_label ( true_label ) ; mips_emit_move ( target , value_if_true ) ; emit_label ( done_label ) ; return target ; } </s>

Move VALUE_IF_TRUE into TARGET if CONDITION is true ; move VALUE_IF_FALSE into TARGET otherwise . Return TARGET .


<s> CCAssignFn * AArch64FastISel :: CCAssignFnForCall ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: WebKit_JS ) return CC_AArch64_WebKit_JS ; return Subtarget -> isTargetDarwin ( ) ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> TargetLowering :: ConstraintWeight PPCTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; if ( StringRef ( constraint ) == "wc" && type -> isIntegerTy ( 1 ) ) return CW_Register ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'd' : if ( type -> isDoubleTy ( ) ) weight = CW_Register ; break ; case 'v' : if ( type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'y' : weight = CW_Register ; break ; case 'Z' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> void aarch64_split_simd_combine ( rtx dst , rtx src1 , rtx src2 ) { machine_mode src_mode = GET_MODE ( src1 ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; gcc_assert ( register_operand ( dst , dst_mode ) && register_operand ( src1 , src_mode ) && register_operand ( src2 , src_mode ) ) ; rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( src_mode ) { case E_V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case E_V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case E_V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case E_V4HFmode : gen = gen_aarch64_simd_combinev4hf ; break ; case E_V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case E_DImode : gen = gen_aarch64_simd_combinedi ; break ; case E_DFmode : gen = gen_aarch64_simd_combinedf ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src1 , src2 ) ) ; return ; } </s>


<s> bool aarch64_sve_arith_immediate_p ( machine_mode mode , rtx x , bool negate_p ) { rtx elt = unwrap_const_vec_duplicate ( x ) ; if ( ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ; val &= GET_MODE_MASK ( GET_MODE_INNER ( mode ) ) ; if ( val & 0xff ) return IN_RANGE ( val , 0 , 0xff ) ; return IN_RANGE ( val , 0 , 0xff00 ) ; } </s>

Return true if X is a valid immediate for the SVE ADD and SUB instructions . Negate X first if NEGATE_P is true .


<s> static bool is_store_insn ( rtx insn , rtx * str_mem ) { if ( ! insn || ! INSN_P ( insn ) ) return false ; return is_store_insn1 ( PATTERN ( insn ) , str_mem ) ; } </s>


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
KnownBits
&
Known
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
KnownBits
Known2
;
Known
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Depth
+
1
)
;
Known2
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
Depth
+
1
)
;
Known
=
KnownBits
::
commonBits
(
Known
,
Known2
)
;
break
;
}
case
AArch64ISD
::
LOADgot
:
case
AArch64ISD
::
ADDlow
:
{
if
(
!
Subtarget
->
isTargetILP32
(
)
)
break
;
Known
.
Zero
=
APInt
::
getHighBitsSet
(
64
,
32
)
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
Known
.
Zero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
Known
.
Zero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
Known
.
Zero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool ARMAsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcode ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ) return true ; return false ; } </s>


<s> bool SystemZTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return false ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> void SystemZPostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DEBUG ( HazardRec -> dumpState ( ) ; ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> bool XNCMTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { LoadSDNode * LD = cast < LoadSDNode > ( N ) ; if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) return false ; EVT VT = LD -> getMemoryVT ( ) ; if ( VT != MVT :: i8 && VT != MVT :: i16 ) return false ; if ( Op -> getOpcode ( ) != ISD :: ADD ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) return false ; Base = Op -> getOperand ( 0 ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = ISD :: POST_INC ; return true ; } return false ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , 0 , "_GLOBAL_OFFSET_TABLE_" ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; ARMConstantPoolValue * CPV = ARMConstantPoolConstant :: Create ( GV , Id ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( GV -> getType ( ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM 0 "_GLOBAL_OFFSET_TABLE_" ARM ARM ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { addPass ( createX86ProtectJTSupport ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; AU . addRequired < MachineModuleInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
static
void
replace_swap_with_copy
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
rtx
src_reg
=
XEXP
(
SET_SRC
(
body
)
,
0
)
;
rtx
copy
=
gen_rtx_SET
(
VOIDmode
,
SET_DEST
(
body
)
,
src_reg
)
;
rtx_insn
*
new_insn
=
emit_insn_before
(
copy
,
insn
)
;
set_block_for_insn
(
new_insn
,
BLOCK_FOR_INSN
(
insn
)
)
;
df_insn_rescan
(
new_insn
)
;
if
(
dump_file
)
{
unsigned
int
new_uid
=
INSN_UID
(
new_insn
)
;
fprintf
(
dump_file
,
"Replacing swap %d with copy %d\n"
,
i
,
new_uid
)
;
}
df_insn_delete
(
insn
)
;
remove_insn
(
insn
)
;
insn
->
set_deleted
(
)
;
}
</s>

Find the insn from the Ith table entry , which is known to be a register swap Y = SWAP ( X ) . Replace it with a copy Y = X .


<s> static bool iq2000_pass_by_reference ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size ; if ( cum && targetm . calls . must_pass_in_stack ( mode , type ) ) { CUMULATIVE_ARGS temp ; temp = * cum ; if ( iq2000_function_arg ( pack_cumulative_args ( & temp ) , mode , type , named ) != 0 ) return 1 ; } if ( type == NULL_TREE || mode == DImode || mode == DFmode ) return 0 ; size = int_size_in_bytes ( type ) ; return size == - 1 || size > UNITS_PER_WORD ; } </s>

Return true when an argument must be passed by reference .


<s> int crx_function_arg_regno_p ( int n ) { return ( n <= MAX_REG_FOR_PASSING_ARGS && n >= MIN_REG_FOR_PASSING_ARGS ) ; } </s>

Implements the macro FUNCTION_ARG_REGNO_P defined in crx.h . Return nonzero * if N is a register used for passing parameters .


<s> void LanaiPassConfig :: addPreSched2 ( ) { addPass ( createLanaiMemAluCombinerPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> bool KudeyarTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const KudeyarSubtarget & Subtarget = TM . getSubtarget < KudeyarSubtarget > ( ) ; if ( Subtarget . isLinux ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s>
static
void
arm_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\t.syntax unified\n"
)
;
if
(
TARGET_FDPIC
)
{
if
(
TARGET_ARM
)
fprintf
(
f
,
"\t.arm\n"
)
;
else
if
(
TARGET_THUMB2
)
fprintf
(
f
,
"\t.thumb\n"
)
;
else
gcc_unreachable
(
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #%d]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
,
TARGET_THUMB2
8
:
4
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #%d]\n"
,
PIC_OFFSET_TABLE_REGNUM
,
PC_REGNUM
,
TARGET_THUMB2
8
:
4
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #%d]\n"
,
PC_REGNUM
,
PC_REGNUM
,
TARGET_THUMB2
8
:
4
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
else
if
(
TARGET_ARM
)
{
fprintf
(
f
,
"\t.arm\n"
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
if
(
TARGET_THUMB2
)
{
fprintf
(
f
,
"\t.thumb\n"
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
{
ASM_OUTPUT_ALIGN
(
f
,
2
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
fprintf
(
f
,
".Ltrampoline_start:\n"
)
;
asm_fprintf
(
f
,
"\tpush\t{r0, r1}\n"
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tmov\t%r, r0\n"
,
STATIC_CHAIN_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tstr\tr0, [%r, #4]\n"
,
SP_REGNUM
)
;
asm_fprintf
(
f
,
"\tpop\t{r0, %r}\n"
,
PC_REGNUM
)
;
}
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . On the ARM , ( if r8 is the static chain regnum , and remembering that referencing pc adds an offset of 8 ) the trampoline looks like : ldr r8 , [ pc , # 0 ] ldr pc , [ pc ] .word static chain value .word function 's address XXX FIXME : When the trampoline returns , r8 will be clobbered .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , TargetABI ( computeTargetABI ( Triple ( TT ) , CPU , Options ) ) , DL ( computeDataLayout ( Triple ( TT ) , TargetABI , isLittle ) ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> unsigned getNumberOfRegisters ( bool Vector ) const override { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 31 ; } </s>


<s> const MCPhysReg * CAHPRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> void mips_emit_save_slot_move ( rtx dest , rtx src , rtx temp ) { unsigned int regno ; rtx mem ; if ( REG_P ( src ) ) { regno = REGNO ( src ) ; mem = dest ; } else { regno = REGNO ( dest ) ; mem = src ; } if ( regno == cfun -> machine -> global_pointer && ! mips_must_initialize_gp_p ( ) ) { if ( TARGET_64BIT ) emit_insn ( gen_move_gpdi ( dest , src ) ) ; else emit_insn ( gen_move_gpsi ( dest , src ) ) ; return ; } if ( regno == HI_REGNUM ) { if ( REG_P ( dest ) ) { mips_emit_move ( temp , src ) ; if ( TARGET_64BIT ) emit_insn ( gen_mthisi_di ( gen_rtx_REG ( TImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( DImode , LO_REGNUM ) ) ) ; else emit_insn ( gen_mthisi_di ( gen_rtx_REG ( DImode , MD_REG_FIRST ) , temp , gen_rtx_REG ( SImode , LO_REGNUM ) ) ) ; } else { if ( TARGET_64BIT ) emit_insn ( gen_mfhidi_ti ( temp , gen_rtx_REG ( TImode , MD_REG_FIRST ) ) ) ; else emit_insn ( gen_mfhisi_di ( temp , gen_rtx_REG ( DImode , MD_REG_FIRST ) ) ) ; mips_emit_move ( dest , temp ) ; } } else if ( mips_direct_save_slot_move_p ( regno , mem , mem == src ) ) mips_emit_move ( dest , src ) ; else { gcc_assert ( ! reg_overlap_mentioned_p ( dest , temp ) ) ; mips_emit_move ( temp , src ) ; mips_emit_move ( dest , temp ) ; } if ( MEM_P ( dest ) ) mips_set_frame_expr ( mips_frame_set ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST , given that one of them is a register save slot and that the other is a register . TEMP is a temporary GPR of the same mode that is available if need be .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


Create the va_list data type . We keep 3 pointers , and two offsets . Two pointers are to the overflow area , which starts at the CFA . One of these is constant , for addressing into the GPR save area below it . The other is advanced up the stack through the overflow region . The third pointer is to the GPR save area . Since the FPR save area is just below it , we can address FPR slots off this pointer . We also keep two one-byte offsets , which are to be subtracted from the constant pointers to yield addresses in the GPR and FPR save areas . These are downcounted as float or non-float arguments are used , and when they get to zero , the argument must be obtained from the overflow region . If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT , then no FPR save area exists , and a single pointer is enough . It 's started at the GPR save area , and is advanced , period . Note that the GPR save area is not constant size , due to optimization in the prologue . Hence , we ca n't use a design with two pointers and two offsets , although we could have designed this with two pointers and three offsets .


<s> static int ix86_register_move_cost ( machine_mode mode , reg_class_t class1_i , reg_class_t class2_i ) { enum reg_class class1 = ( enum reg_class ) class1_i ; enum reg_class class2 = ( enum reg_class ) class2_i ; if ( inline_secondary_memory_needed ( mode , class1 , class2 , false ) ) { int cost = 1 ; cost += inline_memory_move_cost ( mode , class1 , 2 ) ; cost += inline_memory_move_cost ( mode , class2 , 2 ) ; if ( GET_MODE_BITSIZE ( mode ) > BITS_PER_WORD && TARGET_MEMORY_MISMATCH_STALL && targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += 20 ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += 20 ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) ) gcc_unreachable ( ) ; if ( SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return ( SSE_CLASS_P ( class1 ) ? ix86_cost -> hard_register . sse_to_integer : ix86_cost -> hard_register . integer_to_sse ) ; if ( MASK_CLASS_P ( class1 ) != MASK_CLASS_P ( class2 ) ) { return ( MASK_CLASS_P ( class1 ) ? ix86_cost -> hard_register . mask_to_integer : ix86_cost -> hard_register . integer_to_mask ) ; } if ( MASK_CLASS_P ( class1 ) && MASK_CLASS_P ( class2 ) ) return ix86_cost -> hard_register . mask_move ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> hard_register . fp_move ; if ( MAYBE_SSE_CLASS_P ( class1 ) ) { if ( GET_MODE_BITSIZE ( mode ) <= 128 ) return ix86_cost -> hard_register . xmm_move ; if ( GET_MODE_BITSIZE ( mode ) <= 256 ) return ix86_cost -> hard_register . ymm_move ; return ix86_cost -> hard_register . zmm_move ; } if ( MAYBE_MMX_CLASS_P ( class1 ) ) return ix86_cost -> hard_register . mmx_move ; return 2 ; } </s>

Return the cost of moving data from a register in class CLASS1 to one in class CLASS2 . It is not required that the cost always equal 2 when FROM is the same as TO ; on some machines it is expensive to move between registers if they are not general registers .


<s> static void mips_init_print_operand_punct ( void ) { const char * p ; for ( p = "()[]<>*#/?~.@^+$:!" ; * p ; p ++ ) mips_print_operand_punct [ ( unsigned char ) * p ] = true ; } </s>


<s> void OR1KFrameLowering :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned StackAlign = TRI -> needsStackRealignment ( MF ) ? MFI -> getMaxAlignment ( ) : MF . getSubtarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = alignTo ( maxCallFrameSize , StackAlign ) ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; if ( ! ( hasReservedCallFrame ( MF ) && MFI -> adjustsStack ( ) ) ) FrameSize += maxCallFrameSize ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


"Tiny codesize model not supported on X86"

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> ix86_dependencies_evaluation_hook static int ix86_reassociation_width ( unsigned int op , machine_mode mode ) { int width = 1 ; if ( VECTOR_MODE_P ( mode ) ) { int div = 1 ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == 1 ) return 1 ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return 1 ; if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 128 ) div = GET_MODE_BITSIZE ( mode ) / 128 ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 64 ) div = GET_MODE_BITSIZE ( mode ) / 64 ; width = ( width + div - 1 ) / div ; } else if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_fp ; if ( ! TARGET_64BIT && width > 2 ) width = 2 ; return width ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> ARMELFStreamer & ARMTargetELFStreamer :: getStreamer ( ) { ARMELFStreamer * S = static_cast < ARMELFStreamer * > ( Streamer ) ; return * S ; } </s>

Return the output streamer for the assembler .


<s> static void rs6000_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( first + size <= 32768 ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , 12 ) ; rtx r0 = gen_rtx_REG ( Pmode , 0 ) ; gcc_assert ( first <= 32768 ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , stack_pointer_rtx , - first ) ) ) ; if ( rounded_size > 32768 ) { emit_move_insn ( r0 , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r0 , gen_rtx_PLUS ( Pmode , r12 , r0 ) ) ) ; } else emit_insn ( gen_rtx_SET ( r0 , plus_constant ( Pmode , r12 , - rounded_size ) ) ) ; if ( TARGET_64BIT ) emit_insn ( gen_probe_stack_rangedi ( r12 , r12 , stack_pointer_rtx , r0 ) ) ; else emit_insn ( gen_probe_stack_rangesi ( r12 , r12 , stack_pointer_rtx , r0 ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; } } </s>

Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE , inclusive . These are offsets from the current stack pointer .


<s> static const char * output_multi_immediate ( rtx * operands , const char * instr1 , const char * instr2 , int immed_op , HOST_WIDE_INT n ) { n &= 0xffffffff ; if ( n == 0 ) { operands [ immed_op ] = const0_rtx ; output_asm_insn ( instr1 , operands ) ; } else { int i ; const char * instr = instr1 ; for ( i = 0 ; i < 32 ; i += 2 ) { if ( n & ( 3 << i ) ) { operands [ immed_op ] = GEN_INT ( n & ( 255 << i ) ) ; output_asm_insn ( instr , operands ) ; instr = instr2 ; i += 6 ; } } } return "" ; } </s>

Output a multiple immediate operation . OPERANDS is the vector of operands referred to in the output patterns . INSTR1 is the output pattern to use for the first constant . INSTR2 is the output pattern to use for subsequent constants . IMMED_OP is the index of the constant slot in OPERANDS . N is the constant value .


<s> static void arm_override_options_after_change ( void ) { arm_override_options_after_change_1 ( & global_options , & global_options_set ) ; } </s>


<s> void mips_expand_conditional_trap ( rtx comparison ) { rtx op0 , op1 ; machine_mode mode ; enum rtx_code code ; code = GET_CODE ( comparison ) ; switch ( code ) { case GT : case LE : case GTU : case LEU : code = swap_condition ( code ) ; op0 = XEXP ( comparison , 1 ) ; op1 = XEXP ( comparison , 0 ) ; break ; default : op0 = XEXP ( comparison , 0 ) ; op1 = XEXP ( comparison , 1 ) ; break ; } mode = GET_MODE ( XEXP ( comparison , 0 ) ) ; op0 = force_reg ( mode , op0 ) ; if ( ! ( ISA_HAS_COND_TRAPI ? arith_operand ( op1 , mode ) : reg_or_0_operand ( op1 , mode ) ) ) op1 = force_reg ( mode , op1 ) ; emit_insn ( gen_rtx_TRAP_IF ( VOIDmode , gen_rtx_fmt_ee ( code , mode , op0 , op1 ) , const0_rtx ) ) ; } </s>

Perform the comparison in COMPARISON , then trap if the condition holds .


<s> static void mips_sim_reset ( struct mips_sim * state ) { curr_state = state -> dfa_state ; state -> time = 0 ; state -> insns_left = state -> issue_rate ; memset ( & state -> last_set , 0 , sizeof ( state -> last_set ) ) ; state_reset ( curr_state ) ; targetm . sched . init ( 0 , false , 0 ) ; advance_state ( curr_state ) ; } </s>

Reset STATE to the initial simulation state .


<s> static bool use_rsqrt_p ( ) { return ( TARGET_SSE_MATH && flag_finite_math_only && ! flag_trapping_math && flag_unsafe_math_optimizations ) ; } </s>

Return true if it is safe to use the rsqrt optabs to optimize 1.0/sqrt .


"Dangerous instruction in branch delay slot!"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
PPCInstrInfo
::
SubsumesPredicate
(
const
SmallVectorImpl
<
MachineOperand
>
&
Pred1
,
const
SmallVectorImpl
<
MachineOperand
>
&
Pred2
)
const
{
assert
(
Pred1
.
size
(
)
==
2
&&
"Invalid PPC first predicate"
)
;
assert
(
Pred2
.
size
(
)
==
2
&&
"Invalid PPC second predicate"
)
;
if
(
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred1
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR8
||
Pred2
[
1
]
.
getReg
(
)
==
PPC
::
CTR
)
return
false
;
if
(
Pred1
[
1
]
.
getReg
(
)
!=
Pred2
[
1
]
.
getReg
(
)
)
return
false
;
PPC
::
Predicate
P1
=
(
PPC
::
Predicate
)
Pred1
[
0
]
.
getImm
(
)
;
PPC
::
Predicate
P2
=
(
PPC
::
Predicate
)
Pred2
[
0
]
.
getImm
(
)
;
if
(
P1
==
P2
)
return
true
;
if
(
P1
==
PPC
::
PRED_LE
&&
(
P2
==
PPC
::
PRED_LT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
if
(
P1
==
PPC
::
PRED_GE
&&
(
P2
==
PPC
::
PRED_GT
||
P2
==
PPC
::
PRED_EQ
)
)
return
true
;
return
false
;
}
</s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> static unsigned getReturnSaveOffset ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI ) return isPPC64 ? 16 : 8 ; return isPPC64 ? 16 : 4 ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> unsigned X86AsmBackend :: getMaximumNopSize ( ) const { if ( STI . hasFeature ( X86 :: Mode16Bit ) ) return 4 ; if ( ! STI . hasFeature ( X86 :: FeatureNOPL ) && ! STI . hasFeature ( X86 :: Mode64Bit ) ) return 1 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast7ByteNOP ] ) return 7 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast15ByteNOP ] ) return 15 ; if ( STI . getFeatureBits ( ) [ X86 :: TuningFast11ByteNOP ] ) return 11 ; return 10 ; } </s>

Returns the maximum size of a nop in bytes on this target .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = TM . getInstrInfo ( ) ; TRI = TM . getRegisterInfo ( ) ; RS = new RegScavenger ( ) ; isThumb2 = AFI -> isThumb2Function ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; } delete RS ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
isRegNumber
(
)
&&
"Invalid access!"
)
;
return
(
unsigned
)
Imm
.
Val
;
}
</s>

Returns the register associated with this edge .


<s> const uint32_t * DLXRegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return nullptr ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool ARMBaseRegisterInfo :: canSimplifyCallFramePseudos ( MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>


<s>
static
void
thumb_pop
(
FILE
*
f
,
unsigned
long
mask
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
fprintf
(
f
,
"\tpop\t{"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
}
}
if
(
mask
&
(
1
<<
PC_REGNUM
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
crtl
->
calls_eh_return
||
IS_CMSE_ENTRY
(
arm_current_func_type
(
)
)
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to pop .


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED ) { rtx l1 , labelno , pic_tmp , pic_tmp2 , pic_rtx ; rtx global_offset_table ; if ( current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; pic_tmp = plus_constant ( l1 , TARGET_ARM ? 8 : 4 ) ; if ( GOT_PCREL ) pic_tmp2 = gen_rtx_CONST ( VOIDmode , gen_rtx_PLUS ( Pmode , global_offset_table , pc_rtx ) ) ; else pic_tmp2 = gen_rtx_CONST ( VOIDmode , global_offset_table ) ; pic_rtx = gen_rtx_CONST ( Pmode , gen_rtx_MINUS ( Pmode , pic_tmp2 , pic_tmp ) ) ; if ( TARGET_ARM ) { emit_insn ( gen_pic_load_addr_arm ( pic_offset_table_rtx , pic_rtx ) ) ; emit_insn ( gen_pic_add_dot_plus_eight ( pic_offset_table_rtx , pic_offset_table_rtx , labelno ) ) ; } else { if ( REGNO ( pic_offset_table_rtx ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; } else emit_insn ( gen_pic_load_addr_thumb ( pic_offset_table_rtx , pic_rtx ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_offset_table_rtx , pic_offset_table_rtx , labelno ) ) ; } emit_insn ( gen_rtx_USE ( VOIDmode , pic_offset_table_rtx ) ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


<s> rtx rs6000_allocate_stack_temp ( machine_mode mode , bool offsettable_p , bool reg_reg_p ) { rtx stack = assign_stack_temp ( mode , GET_MODE_SIZE ( mode ) ) ; rtx addr = XEXP ( stack , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indirect_address_p ( addr , strict_p ) ) { if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; } return stack ; } </s>

Allocate a stack temp and fixup the address so it meets the particular memory requirements ( either offetable or REG+REG addressing ) .


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( mode ) { case E_QImode : gen = gen_aarch64_load_exclusiveqi ; break ; case E_HImode : gen = gen_aarch64_load_exclusivehi ; break ; case E_SImode : gen = gen_aarch64_load_exclusivesi ; break ; case E_DImode : gen = gen_aarch64_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , model_rtx ) ) ; } </s>


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; } </s>


<s> unsigned SystemZInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case SystemZ :: MOV32mr : case SystemZ :: MOV32mry : case SystemZ :: MOV64mr : case SystemZ :: MOV32m8r : case SystemZ :: MOV32m8ry : case SystemZ :: MOV32m16r : case SystemZ :: MOV32m16ry : case SystemZ :: MOV64m8r : case SystemZ :: MOV64m8ry : case SystemZ :: MOV64m16r : case SystemZ :: MOV64m16ry : case SystemZ :: MOV64m32r : case SystemZ :: MOV64m32ry : case SystemZ :: FMOV32mr : case SystemZ :: FMOV32mry : case SystemZ :: FMOV64mr : case SystemZ :: FMOV64mry : case SystemZ :: MOV64Pmr : case SystemZ :: MOV64Pmry : case SystemZ :: MOV128mr : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 0 && MI -> getOperand ( 2 ) . getReg ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 3 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AsmPrinter :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static bool ix86_legitimate_combined_insn ( rtx_insn * insn ) { int i ; gcc_assert ( INSN_CODE ( insn ) >= 0 ) ; extract_insn ( insn ) ; preprocess_constraints ( insn ) ; int n_operands = recog_data . n_operands ; int n_alternatives = recog_data . n_alternatives ; for ( i = 0 ; i < n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; machine_mode mode = GET_MODE ( op ) ; const operand_alternative * op_alt ; int offset = 0 ; bool win ; int j ; if ( UNARY_P ( op ) ) op = XEXP ( op , 0 ) ; if ( SUBREG_P ( op ) ) { if ( REG_P ( SUBREG_REG ( op ) ) && REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) offset = subreg_regno_offset ( REGNO ( SUBREG_REG ( op ) ) , GET_MODE ( SUBREG_REG ( op ) ) , SUBREG_BYTE ( op ) , GET_MODE ( op ) ) ; op = SUBREG_REG ( op ) ; } if ( ! ( REG_P ( op ) && HARD_REGISTER_P ( op ) ) ) continue ; op_alt = recog_op_alt ; win = ! n_alternatives ; alternative_mask preferred = get_preferred_alternatives ( insn ) ; for ( j = 0 ; j < n_alternatives ; j ++ , op_alt += n_operands ) { if ( ! TEST_BIT ( preferred , j ) ) continue ; if ( op_alt [ i ] . anything_ok || ( op_alt [ i ] . matches != - 1 && operands_match_p ( recog_data . operand [ i ] , recog_data . operand [ op_alt [ i ] . matches ] ) ) || reg_fits_class_p ( op , op_alt [ i ] . cl , offset , mode ) ) { win = true ; break ; } } if ( ! win ) return false ; } return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


<s> bool AArch64TargetLowering :: isMaskAndCmp0FoldingBeneficial ( const Instruction & AndI ) const { ConstantInt * Mask = dyn_cast < ConstantInt > ( AndI . getOperand ( 1 ) ) ; if ( ! Mask ) return false ; return Mask -> getValue ( ) . isPowerOf2 ( ) ; } </s>

Return if the target supports combining a chain like :


<s> static inline enum insn_code rs6000_htm_spr_icode ( bool nonvoid ) { if ( nonvoid ) return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si ; else return ( TARGET_POWERPC64 ) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si ; } </s>

Return the correct ICODE value depending on whether we are setting or reading the HTM SPRs .


<s> bool ARMCodeGenPrepare :: doFinalization ( Module & M ) { delete Promoter ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool VEPassConfig :: addInstSelector ( ) { addPass ( createVEISelDag ( getVETargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static rtx mips_call_expr_from_insn ( rtx_insn * insn , rtx * second_call ) { rtx x ; rtx x2 ; if ( ! CALL_P ( insn ) ) return NULL_RTX ; x = PATTERN ( insn ) ; if ( GET_CODE ( x ) == PARALLEL ) { x2 = XVECEXP ( x , 0 , 1 ) ; if ( GET_CODE ( x2 ) == SET ) x2 = XEXP ( x2 , 1 ) ; if ( GET_CODE ( x2 ) == CALL ) * second_call = x2 ; x = XVECEXP ( x , 0 , 0 ) ; } if ( GET_CODE ( x ) == SET ) x = XEXP ( x , 1 ) ; gcc_assert ( GET_CODE ( x ) == CALL ) ; return x ; } </s>

If INSN is a call , return the underlying CALL expr . Return NULL_RTX otherwise . If INSN has two call rtx , then store the second one in SECOND_CALL .


<s> bool isMem ( ) const override { return Kind == k_Memory ; } </s>


<s> static void seh_emit_push ( FILE * f , struct seh_frame_state * seh , rtx reg ) { const unsigned int regno = REGNO ( reg ) ; gcc_checking_assert ( GENERAL_REGNO_P ( regno ) ) ; seh -> sp_offset += UNITS_PER_WORD ; seh -> reg_offset [ regno ] = seh -> sp_offset ; if ( seh -> cfa_reg == stack_pointer_rtx ) seh -> cfa_offset += UNITS_PER_WORD ; fputs ( "\t.seh_pushreg\t" , f ) ; print_reg ( reg , 0 , f ) ; fputc ( '\n' , f ) ; } </s>

Emit an assembler directive to save REG via a PUSH .


<s> bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s> void xstormy16_expand_epilogue ( void ) { struct xstormy16_stack_layout layout ; rtx mem_pop_rtx , insn ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_pop_rtx = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; mem_pop_rtx = gen_rtx_MEM ( HImode , mem_pop_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . locals_size ) { if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; else { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx dwarf ; insn = emit_move_insn ( gen_rtx_REG ( HImode , regno ) , mem_pop_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( stack_pointer_rtx , - GET_MODE_SIZE ( Pmode ) ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( insn ) ) ; } if ( layout . stdarg_save_size ) { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . stdarg_save_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( ifun ) emit_jump_insn ( gen_return_internal_interrupt ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> bool ARMBaseRegisterInfo :: getRegAllocationHints ( Register VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < Register , Register > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } Register Paired = Hint . second ; if ( ! Paired ) return false ; Register PairedPhys ; if ( Paired . isPhysical ( ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( MCPhysReg Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; MCPhysReg Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } return false ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s>
ScheduleHazardRecognizer
*
PPCInstrInfo
::
CreateTargetHazardRecognizer
(
const
TargetMachine
*
TM
,
const
ScheduleDAG
*
DAG
)
const
{
const
TargetInstrInfo
*
TII
=
TM
->
getInstrInfo
(
)
;
assert
(
TII
&&
"No InstrInfo?"
)
;
unsigned
Directive
=
TM
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getDarwinDirective
(
)
;
if
(
Directive
==
PPC
::
DIR_440
)
{
const
InstrItineraryData
*
II
=
TM
->
getInstrItineraryData
(
)
;
return
new
PPCHazardRecognizer440
(
II
,
DAG
)
;
}
else
{
return
new
PPCHazardRecognizer970
(
*
TII
)
;
}
}
</s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .

PowerPC
PPC
"No InstrInfo?"
PPC
PPC::DIR_440
PPC
PPC


<s> bool AArch64AsmBackend :: fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { return int64_t ( Value ) != int64_t ( int8_t ( Value ) ) ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool ARMFrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s>
void
mmix_asm_output_skip
(
FILE
*
stream
,
int
nbytes
)
{
fprintf
(
stream
,
"\tLOC @+%d\n"
,
nbytes
)
;
}
</s>


<s> void SystemZPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void X86CmovConverterPass :: getAnalysisUsage ( AnalysisUsage & AU ) const { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineLoopInfo > ( ) ; } </s>


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Unknown ValueType for f-register-type!"

"Unknown ValueType for e-register-type!"

Given a physical register constraint ( e.g .


<s> static bool quad_aligned_load_p ( swap_web_entry * insn_entry , rtx_insn * insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || ! ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) || ! MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; return ( ( REG_P ( base_reg ) || rs6000_sum_of_two_registers_p ( base_reg ) ) && MEM_ALIGN ( mem ) >= 128 ) ? true : false ; } </s>

Return TRUE if INSN represents a swap of a swapped load from memory and the memory address is quad-word aligned .


<s> static bool has_part_mult ( rtx_insn * insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return false ; rtx src = SET_SRC ( body ) ; if ( GET_CODE ( src ) != SUBREG ) return false ; rtx inner = XEXP ( src , 0 ) ; return ( GET_CODE ( inner ) == MULT ) ; } </s>

INSN is known to contain a SUBREG , which we can normally handle , but if the SUBREG itself contains a MULT then we need to leave it alone to avoid turning a mult_hipart into a mult_lopart , for example .


<s> int aarch_crypto_can_dual_issue ( rtx_insn * producer_insn , rtx_insn * consumer_insn ) { rtx producer_set , consumer_set ; rtx producer_src , consumer_src ; producer_set = single_set ( producer_insn ) ; consumer_set = single_set ( consumer_insn ) ; producer_src = producer_set ? SET_SRC ( producer_set ) : NULL ; consumer_src = consumer_set ? SET_SRC ( consumer_set ) : NULL ; if ( producer_src && consumer_src && GET_CODE ( producer_src ) == UNSPEC && GET_CODE ( consumer_src ) == UNSPEC && ( ( XINT ( producer_src , 1 ) == UNSPEC_AESE && XINT ( consumer_src , 1 ) == UNSPEC_AESMC ) || ( XINT ( producer_src , 1 ) == UNSPEC_AESD && XINT ( consumer_src , 1 ) == UNSPEC_AESIMC ) ) ) { unsigned int regno = REGNO ( SET_DEST ( producer_set ) ) ; return REGNO ( SET_DEST ( consumer_set ) ) == regno && REGNO ( XVECEXP ( consumer_src , 0 , 0 ) ) == regno ; } return 0 ; } </s>

In ARMv8-A there 's a general expectation that AESE/AESMC and AESD/AESIMC sequences of the form : AESE Vn , _ AESMC Vn , Vn will issue both instructions in a single cycle on super-scalar implementations . This function identifies such pairs .


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; rtx sym , addend ; if ( GET_CODE ( addr ) == CONST ) { split_const ( addr , & sym , & addend ) ; if ( GET_CODE ( sym ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( sym ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s> static void arm_expand_vec_perm_1 ( rtx target , rtx op0 , rtx op1 , rtx sel ) { machine_mode vmode = GET_MODE ( target ) ; bool one_vector_p = rtx_equal_p ( op0 , op1 ) ; gcc_checking_assert ( vmode == V8QImode || vmode == V16QImode ) ; gcc_checking_assert ( GET_MODE ( op0 ) == vmode ) ; gcc_checking_assert ( GET_MODE ( op1 ) == vmode ) ; gcc_checking_assert ( GET_MODE ( sel ) == vmode ) ; gcc_checking_assert ( TARGET_NEON ) ; if ( one_vector_p ) { if ( vmode == V8QImode ) emit_insn ( gen_neon_vtbl1v8qi ( target , op0 , sel ) ) ; else emit_insn ( gen_neon_vtbl1v16qi ( target , op0 , sel ) ) ; } else { rtx pair ; if ( vmode == V8QImode ) { pair = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_neon_vcombinev8qi ( pair , op0 , op1 ) ) ; pair = gen_lowpart ( TImode , pair ) ; emit_insn ( gen_neon_vtbl2v8qi ( target , pair , sel ) ) ; } else { pair = gen_reg_rtx ( OImode ) ; emit_insn ( gen_neon_vcombinev16qi ( pair , op0 , op1 ) ) ; emit_insn ( gen_neon_vtbl2v16qi ( target , pair , sel ) ) ; } } } </s>


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( known_eq ( TYPE_VECTOR_SUBPARTS ( vectype ) , 2u ) ? ! TARGET_USE_SCATTER_2PARTS : ( known_eq ( TYPE_VECTOR_SUBPARTS ( vectype ) , 4u ) ? ! TARGET_USE_SCATTER_4PARTS : ! TARGET_USE_SCATTER ) ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DF : IX86_BUILTIN_SCATTERDIV4DF ; else return NULL_TREE ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DI : IX86_BUILTIN_SCATTERDIV4DI ; else return NULL_TREE ; break ; case E_V8SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SF : IX86_BUILTIN_SCATTERALTDIV8SF ; else return NULL_TREE ; break ; case E_V8SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV8SI : IX86_BUILTIN_SCATTERALTDIV8SI ; else return NULL_TREE ; break ; case E_V2DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DF : IX86_BUILTIN_SCATTERDIV2DF ; else return NULL_TREE ; break ; case E_V2DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV2DI : IX86_BUILTIN_SCATTERDIV2DI ; else return NULL_TREE ; break ; case E_V4SFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SF : IX86_BUILTIN_SCATTERALTDIV4SF ; else return NULL_TREE ; break ; case E_V4SImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERSIV4SI : IX86_BUILTIN_SCATTERALTDIV4SI ; else return NULL_TREE ; break ; default : return NULL_TREE ; } return get_ix86_builtin ( code ) ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s>
void
dump
(
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Reduction:\n"
;
for
(
auto
*
Add
:
Adds
)
LLVM_DEBUG
(
dbgs
(
)
<<
*
Add
<<
"\n"
)
;
for
(
auto
&
Mul
:
Muls
)
LLVM_DEBUG
(
dbgs
(
)
<<
*
Mul
->
Root
<<
"\n"
<<
"  "
<<
*
Mul
->
LHS
<<
"\n"
<<
"  "
<<
*
Mul
->
RHS
<<
"\n"
)
;
LLVM_DEBUG
(
if
(
Acc
)
dbgs
(
)
<<
"Acc in: "
<<
*
Acc
<<
"\n"
)
)
;
}
</s>

Dump the plan to stderr ( for debugging ) .


<s> ConstantPool * AssemblerConstantPools :: getConstantPool ( const MCSection * Section ) { ConstantPoolMapTy :: iterator CP = ConstantPools . find ( Section ) ; if ( CP == ConstantPools . end ( ) ) return 0 ; return & CP -> second ; } </s>

Return a pseudo source value referencing the constant pool .


<s> rtx rs6000_address_for_altivec ( rtx x ) { gcc_assert ( MEM_P ( x ) ) ; if ( ! altivec_indexed_or_indirect_operand ( x , GET_MODE ( x ) ) ) { rtx addr = XEXP ( x , 0 ) ; int strict_p = ( reload_in_progress || reload_completed ) ; if ( ! legitimate_indexed_address_p ( addr , strict_p ) && ! legitimate_indirect_address_p ( addr , strict_p ) ) addr = copy_to_mode_reg ( Pmode , addr ) ; addr = gen_rtx_AND ( Pmode , addr , GEN_INT ( - 16 ) ) ; x = change_address ( x , GET_MODE ( x ) , addr ) ; } return x ; } </s>

Given a memory reference , if it is not in the form for altivec memory reference instructions ( i.e . reg or reg+reg addressing with AND of -16 ) , convert to the altivec format .


<s> void TOYFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = TOY :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: ADDrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( TOY :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>


"For each split Type there should be exactly one VReg."

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static void build_all ( function_builder & b , const char * signature , const function_group_info & group , mode_suffix_index mode_suffix_id , bool force_direct_overloads = false ) { for ( unsigned int pi = 0 ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) for ( unsigned int ti = 0 ; ti == 0 || group . types [ ti ] [ 0 ] != NUM_TYPE_SUFFIXES ; ++ ti ) build_one ( b , signature , group , mode_suffix_id , ti , pi , force_direct_overloads ) ; } </s>

Add a function instance for every operand & & predicate & & args combination in GROUP . Take the function base name from GROUP & & operand suffix from operand_suffixes & & mode suffix from type_suffixes & & predication suffix from predication_suffixes . Use apply_predication to add in the predicate .


<s> bool LanaiAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] ) return true ; switch ( ExtraCode [ 0 ] ) { case 'H' : { if ( OpNo == 0 ) return true ; const MachineOperand & FlagsOP = MI -> getOperand ( OpNo - 1 ) ; if ( ! FlagsOP . isImm ( ) ) return true ; unsigned Flags = FlagsOP . getImm ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; if ( NumVals != 2 ) return true ; unsigned RegOp = OpNo + 1 ; if ( RegOp >= MI -> getNumOperands ( ) ) return true ; const MachineOperand & MO = MI -> getOperand ( RegOp ) ; if ( ! MO . isReg ( ) ) return true ; unsigned Reg = MO . getReg ( ) ; O << LanaiInstPrinter :: getRegisterName ( Reg ) ; return false ; } default : return true ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ; if ( Kind == FK_NONE ) return true ; if ( Kind == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; AArch64MCExpr :: VariantKind RefKind = static_cast < AArch64MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; AArch64MCExpr :: VariantKind SymLoc = AArch64MCExpr :: getSymbolLoc ( RefKind ) ; if ( Kind == AArch64 :: fixup_aarch64_ldr_pcrel_imm19 && SymLoc == AArch64MCExpr :: VK_GOT ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


"-target-abi option != target-abi module flag"


<s>
bool
PPCInstrInfo
::
shouldReduceRegisterPressure
(
MachineBasicBlock
*
MBB
,
RegisterClassInfo
*
RegClassInfo
)
const
{
if
(
!
EnableFMARegPressureReduction
)
return
false
;
if
(
!
(
Subtarget
.
isPPC64
(
)
&&
Subtarget
.
hasP9Vector
(
)
&&
Subtarget
.
getTargetMachine
(
)
.
getCodeModel
(
)
==
CodeModel
::
Medium
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
MachineRegisterInfo
*
MRI
=
&
MF
->
getRegInfo
(
)
;
auto
GetMBBPressure
=
[
&
]
(
MachineBasicBlock
*
MBB
)
->
std
::
vector
<
unsigned
>
{
RegionPressure
Pressure
;
RegPressureTracker
RPTracker
(
Pressure
)
;
RPTracker
.
init
(
MBB
->
getParent
(
)
,
RegClassInfo
,
nullptr
,
MBB
,
MBB
->
end
(
)
,
false
,
true
)
;
for
(
MachineBasicBlock
::
iterator
MII
=
MBB
->
instr_end
(
)
,
MIE
=
MBB
->
instr_begin
(
)
;
MII
!=
MIE
;
MII
)
{
MachineInstr
&
MI
=
*
std
::
prev
(
MII
)
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
isDebugLabel
(
)
)
continue
;
RegisterOperands
RegOpers
;
RegOpers
.
collect
(
MI
,
*
TRI
,
*
MRI
,
false
,
false
)
;
RPTracker
.
recedeSkipDebugValues
(
)
;
assert
(
&
*
RPTracker
.
getPos
(
)
==
&
MI
&&
"RPTracker sync error!"
)
;
RPTracker
.
recede
(
RegOpers
)
;
}
RPTracker
.
closeRegion
(
)
;
return
RPTracker
.
getPressure
(
)
.
MaxSetPressure
;
}
;
unsigned
VSSRCLimit
=
TRI
->
getRegPressureSetLimit
(
*
MBB
->
getParent
(
)
,
PPC
::
RegisterPressureSets
::
VSSRC
)
;
return
GetMBBPressure
(
MBB
)
[
PPC
::
RegisterPressureSets
::
VSSRC
]
>
(
float
)
VSSRCLimit
*
FMARPFactor
;
}
</s>

Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB .

PowerPC
PPC
PPC
"RPTracker sync error!"
PPC::RegisterPressureSets
PPC::RegisterPressureSets


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> void MipsPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; if ( getMipsSubtarget ( ) . os16 ( ) ) addPass ( createMipsOs16 ( getMipsTargetMachine ( ) ) ) ; if ( getMipsSubtarget ( ) . inMips16HardFloat ( ) ) addPass ( createMips16HardFloat ( getMipsTargetMachine ( ) ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> rtx gen_easy_altivec_constant ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx val = CONST_VECTOR_ELT ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; unsigned step = nunits / 4 ; unsigned copies = 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , val ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , val ) ) ; if ( step == 1 ) copies <<= 1 ; else step >>= 1 ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V16QImode , gen_lowpart ( QImode , val ) ) ; gcc_unreachable ( ) ; } </s>

Generate a VEC_DUPLICATE representing a vspltis [ bhw ] instruction whose result is OP . Abort if it is not possible .


<s>
bool
ARM64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> unsigned getDstReg ( ) const { return Dst ; } </s>

Get the definition register of the loaded value .


<s> bool AZPRFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> SDValue OpenRISCTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_OpenRISC ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> EVT X86TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


"getBranchTarget21OpValue expects only expressions or immediates"

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK2
:
\
case
TYPE_VK4
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
case
TYPE_VK32
:
\
case
TYPE_VK64
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> bool MipsRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>


<s> static tree ix86_fn_abi_va_list ( tree fndecl ) { if ( ! TARGET_64BIT ) return va_list_type_node ; gcc_assert ( fndecl != NULL_TREE ) ; if ( ix86_function_abi ( ( const_tree ) fndecl ) == MS_ABI ) return ms_va_list_type_node ; else return sysv_va_list_type_node ; } </s>

This function returns the calling abi specific va_list type node . It returns the FNDECL specific va_list type .


<s>
bool
X86CallFrameOptimization
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
STI
=
&
MF
.
getSubtarget
<
X86Subtarget
>
(
)
;
TII
=
STI
->
getInstrInfo
(
)
;
TFL
=
STI
->
getFrameLowering
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
const
X86RegisterInfo
&
RegInfo
=
*
static_cast
<
const
X86RegisterInfo
*
>
(
STI
->
getRegisterInfo
(
)
)
;
SlotSize
=
RegInfo
.
getSlotSize
(
)
;
assert
(
isPowerOf2_32
(
SlotSize
)
&&
"Expect power of 2 stack slot size"
)
;
Log2SlotSize
=
Log2_32
(
SlotSize
)
;
if
(
skipFunction
(
MF
.
getFunction
(
)
)
||
!
isLegal
(
MF
)
)
return
false
;
unsigned
FrameSetupOpcode
=
TII
->
getCallFrameSetupOpcode
(
)
;
bool
Changed
=
false
;
ContextVector
CallSeqVector
;
for
(
auto
&
MBB
:
MF
)
for
(
auto
&
MI
:
MBB
)
if
(
MI
.
getOpcode
(
)
==
FrameSetupOpcode
)
{
CallContext
Context
;
collectCallInfo
(
MF
,
MBB
,
MI
,
Context
)
;
CallSeqVector
.
push_back
(
Context
)
;
}
if
(
!
isProfitable
(
MF
,
CallSeqVector
)
)
return
false
;
for
(
const
auto
&
CC
:
CallSeqVector
)
{
if
(
CC
.
UsePush
)
{
adjustCallSequence
(
MF
,
CC
)
;
Changed
=
true
;
}
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void mips_set_return_address ( rtx address , rtx scratch ) { rtx slot_address ; gcc_assert ( BITSET_P ( cfun -> machine -> frame . mask , RETURN_ADDR_REGNUM ) ) ; slot_address = mips_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; mips_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ; } </s>

Emit code to change the current function 's return address to ADDRESS . SCRATCH is available as a scratch register , if needed . ADDRESS and SCRATCH are both word-mode GPRs .


<s> static rtx altivec_expand_st_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 ; machine_mode mode0 , mode1 ; rtx pat , op0 , op1 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_ST_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_store_v16qi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_store_v8hi ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4si : icode = CODE_FOR_vector_altivec_store_v4si ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_store_v4sf ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2df : icode = CODE_FOR_vector_altivec_store_v2df ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_2di : icode = CODE_FOR_vector_altivec_store_v2di ; break ; case ALTIVEC_BUILTIN_ST_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_store_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; op1 = expand_normal ( arg1 ) ; mode0 = insn_data [ icode ] . operand [ 0 ] . mode ; mode1 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ; * expandedp = true ; return NULL_RTX ; } </s>


<s> bool ARMTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { EVT VT = getValueType ( Ty , true ) ; if ( ! isLegalAddressImmediate ( AM . BaseOffs , VT , Subtarget ) ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( Subtarget -> isThumb1Only ( ) ) return false ; default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i1 : case MVT :: i8 : case MVT :: i32 : if ( Scale < 0 ) Scale = - Scale ; if ( Scale == 1 ) return true ; return isPowerOf2_32 ( Scale & ~ 1 ) ; case MVT :: i16 : case MVT :: i64 : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= 2 ) return true ; return false ; case MVT :: isVoid : if ( Scale & 1 ) return false ; return isPowerOf2_32 ( Scale ) ; } } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void mt_expand_eh_return ( rtx * operands ) { if ( GET_CODE ( operands [ 0 ] ) != REG || REGNO ( operands [ 0 ] ) != EH_RETURN_STACKADJ_REGNO ) { rtx sp = EH_RETURN_STACKADJ_RTX ; emit_move_insn ( sp , operands [ 0 ] ) ; operands [ 0 ] = sp ; } emit_insn ( gen_eh_epilogue ( operands [ 0 ] ) ) ; } </s>

Generate code for the `` eh_return '' pattern .


<s> bool nds32_n13_last_load_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx last_def_reg = extract_nth_access_reg ( producer , - 1 ) ; return n13_consumed_by_e1_dep_p ( consumer , last_def_reg ) ; } </s>

Check dependencies from LMW ( N , N ) to E1 .


<s> static int rs6000_use_sched_lookahead ( void ) { if ( rs6000_cpu_attr == CPU_PPC8540 ) return 4 ; return 0 ; } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> TargetLowering :: ConstraintWeight SystemZTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'r' : if ( CallOperandVal -> getType ( ) -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'J' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) weight = CW_Constant ; break ; case 'K' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'L' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; break ; case 'M' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> MachineBasicBlock :: iterator MipsFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . GetStackPtr ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( 0 ) . getImm ( ) ; if ( ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKDOWN ) || ( I -> getOpcode ( ) == Mips :: ADJCALLSTACKCAPDOWN ) ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ; } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

Mips Mips 0 Mips::ADJCALLSTACKDOWN Mips::ADJCALLSTACKCAPDOWN


<s> static inline int regno_or_subregno ( rtx op ) { if ( REG_P ( op ) ) return REGNO ( op ) ; else if ( SUBREG_P ( op ) ) return subreg_regno ( op ) ; else gcc_unreachable ( ) ; } </s>

Helper function to return the register number of a RTX .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static int ia64_sched_reorder ( FILE * dump , int sched_verbose , rtx_insn * * ready , int * pn_ready , int clock_var ) { return ia64_dfa_sched_reorder ( dump , sched_verbose , ready , pn_ready , clock_var , 0 ) ; } </s>

We are about to being issuing insns for this clock cycle . Override the default sort algorithm to better slot instructions .


<s> void aarch64_override_options_internal ( struct gcc_options * opts ) { aarch64_tune_flags = selected_tune -> flags ; aarch64_tune = selected_tune -> sched_core ; aarch64_tune_params = * ( selected_tune -> tune ) ; aarch64_architecture_version = selected_arch -> architecture_version ; if ( opts -> x_aarch64_override_tune_string ) aarch64_parse_override_string ( opts -> x_aarch64_override_tune_string , & aarch64_tune_params ) ; if ( opts -> x_flag_strict_volatile_bitfields < 0 && abi_version_at_least ( 2 ) ) opts -> x_flag_strict_volatile_bitfields = 1 ; initialize_aarch64_code_model ( opts ) ; initialize_aarch64_tls_size ( opts ) ; int queue_depth = 0 ; switch ( aarch64_tune_params . autoprefetcher_model ) { case tune_params :: AUTOPREFETCHER_OFF : queue_depth = - 1 ; break ; case tune_params :: AUTOPREFETCHER_WEAK : queue_depth = 0 ; break ; case tune_params :: AUTOPREFETCHER_STRONG : queue_depth = max_insn_queue_index + 1 ; break ; default : gcc_unreachable ( ) ; } maybe_set_param_value ( PARAM_SCHED_AUTOPREF_QUEUE_DEPTH , queue_depth , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> num_slots > 0 ) maybe_set_param_value ( PARAM_SIMULTANEOUS_PREFETCHES , aarch64_tune_params . prefetch -> num_slots , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l1_cache_size >= 0 ) maybe_set_param_value ( PARAM_L1_CACHE_SIZE , aarch64_tune_params . prefetch -> l1_cache_size , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l1_cache_line_size >= 0 ) maybe_set_param_value ( PARAM_L1_CACHE_LINE_SIZE , aarch64_tune_params . prefetch -> l1_cache_line_size , opts -> x_param_values , global_options_set . x_param_values ) ; if ( aarch64_tune_params . prefetch -> l2_cache_size >= 0 ) maybe_set_param_value ( PARAM_L2_CACHE_SIZE , aarch64_tune_params . prefetch -> l2_cache_size , opts -> x_param_values , global_options_set . x_param_values ) ; maybe_set_param_value ( PARAM_SCHED_PRESSURE_ALGORITHM , SCHED_PRESSURE_MODEL , opts -> x_param_values , global_options_set . x_param_values ) ; if ( opts -> x_flag_prefetch_loop_arrays < 0 && ! opts -> x_optimize_size && aarch64_tune_params . prefetch -> default_opt_level >= 0 && opts -> x_optimize >= aarch64_tune_params . prefetch -> default_opt_level ) opts -> x_flag_prefetch_loop_arrays = 1 ; aarch64_override_options_after_change_1 ( opts ) ; } </s>

'Unpack ' up the internal tuning structs and update the options in OPTS . The caller must have set up selected_tune and selected_arch as all the other target-specific codegen decisions are derived from them .


<s> static inline bool mode_supports_vsx_dform_quad ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in VSX registers . This addressing is more limited than normal d-form addressing in that the offset must be aligned on a 16-byte boundary .


<s> const char * LanaiTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case LanaiISD :: ADJDYNALLOC : return "LanaiISD::ADJDYNALLOC" ; case LanaiISD :: RET_FLAG : return "LanaiISD::RET_FLAG" ; case LanaiISD :: CALL : return "LanaiISD::CALL" ; case LanaiISD :: SELECT_CC : return "LanaiISD::SELECT_CC" ; case LanaiISD :: SETCC : return "LanaiISD::SETCC" ; case LanaiISD :: SUBBF : return "LanaiISD::SUBBF" ; case LanaiISD :: SET_FLAG : return "LanaiISD::SET_FLAG" ; case LanaiISD :: BR_CC : return "LanaiISD::BR_CC" ; case LanaiISD :: Wrapper : return "LanaiISD::Wrapper" ; case LanaiISD :: HI : return "LanaiISD::HI" ; case LanaiISD :: LO : return "LanaiISD::LO" ; case LanaiISD :: SMALL : return "LanaiISD::SMALL" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Lanai Lanai LanaiISD::ADJDYNALLOC "LanaiISD::ADJDYNALLOC" LanaiISD::RET_FLAG "LanaiISD::RET_FLAG" LanaiISD::CALL "LanaiISD::CALL" LanaiISD::SELECT_CC "LanaiISD::SELECT_CC" LanaiISD::SETCC "LanaiISD::SETCC" LanaiISD::SUBBF "LanaiISD::SUBBF" LanaiISD::SET_FLAG "LanaiISD::SET_FLAG" LanaiISD::BR_CC "LanaiISD::BR_CC" LanaiISD::Wrapper "LanaiISD::Wrapper" LanaiISD::HI "LanaiISD::HI" LanaiISD::LO "LanaiISD::LO" LanaiISD::SMALL "LanaiISD::SMALL"


<s> TargetIRAnalysis PPCTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; F . addFnAttr ( "no-frame-pointer-elim" , "true" ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void MipsFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? Mips :: SP_64 : Mips :: SP ; unsigned FP = STI . isABI_N64 ( ) ? Mips :: FP_64 : Mips :: FP ; unsigned ZERO = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; unsigned ADDu = STI . isABI_N64 ( ) ? Mips :: DADDu : Mips :: ADDu ; unsigned ADDiu = STI . isABI_N64 ( ) ? Mips :: DADDiu : Mips :: ADDiu ; unsigned StackSize = MFI -> getStackSize ( ) ; unsigned NewReg = 0 ; int NewImm = 0 ; bool ATUsed = false ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( StackSize ) { ATUsed = expandRegLargeImmPair ( SP , StackSize , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( NewReg ) . addImm ( NewImm ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: ATMACRO ) ) ; } } </s>

Mips Mips Mips Mips Mips::SP_64 Mips::SP Mips::FP_64 Mips::FP Mips::ZERO_64 Mips::ZERO Mips::DADDu Mips::ADDu Mips::DADDiu Mips::ADDiu 0 0 0 Mips::ATMACRO


<s> bool ProtectSpillSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { const X86InstrInfo * TII = static_cast < const X86InstrInfo * > ( Func . getTarget ( ) . getInstrInfo ( ) ) ; bool modified = false ; SmallVector < CJEItem , 8 > worklist ; for ( auto MBBI = Func . begin ( ) , MBBE = Func . end ( ) ; MBBI != MBBE ; ++ MBBI ) { for ( auto MI = MBBI -> begin ( ) , ME = MBBI -> end ( ) ; MI != ME ; ++ MI ) { CJEItem item ; if ( isCJEOpcode ( MI -> getOpcode ( ) , item . NativeOpcode , item . isFrameSetup ) ) { item . MI = MI ; item . isEFLAGSlive = TII -> isRegLiveAtMI ( X86 :: EFLAGS , MI ) ; item . isRAXlive = isRAXLiveAtMI ( MI ) ; worklist . push_back ( item ) ; } } } modified = ! worklist . empty ( ) ; while ( ! worklist . empty ( ) ) { CJEItem item = worklist . pop_back_val ( ) ; transformCJE ( item . MI , item . NativeOpcode , item . isFrameSetup , item . isEFLAGSlive , item . isRAXlive ) ; } return modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool LC3FrameLowering :: hasFP ( const MachineFunction & MF ) const { return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> int mips_can_use_return_insn ( ) { if ( ! reload_completed ) return 0 ; if ( regs_ever_live [ 31 ] || current_function_profile ) return 0 ; if ( TARGET_MIPS16 && mips16_hard_float && ! aggregate_value_p ( DECL_RESULT ( current_function_decl ) ) && ( GET_MODE_CLASS ( DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ) == MODE_FLOAT ) && ( ! TARGET_SINGLE_FLOAT || ( GET_MODE_SIZE ( DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ) <= 4 ) ) ) return 0 ; if ( current_frame_info . initialized ) return current_frame_info . total_size == 0 ; return compute_frame_size ( get_frame_size ( ) ) == 0 ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> bool PPCSubtarget :: enableMachinePipeliner ( ) const { return getSchedModel ( ) . hasInstrSchedModel ( ) && EnableMachinePipeliner ; } </s>

True if the subtarget should run MachinePipeliner .


<s> void ix86_register_pragmas ( void ) { targetm . target_option . pragma_parse = ix86_pragma_target_parse ; REGISTER_SUBTARGET_PRAGMAS ( ) ; } </s>

Register target pragmas . We need to add the hook for parsing # pragma GCC option here rather than in i386.cc since it will pull in various preprocessor functions , and those are not present in languages like fortran without a preprocessor .


<s> AArch64Subtarget :: AArch64Subtarget ( StringRef TT , StringRef CPU , StringRef FS , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , TargetTriple ( TT ) , CPUString ( CPU ) , IsLittleEndian ( LittleEndian ) { initializeSubtargetFeatures ( CPU , FS ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void ARMBankConflictHazardRecognizer :: RecedeCycle ( ) { Accesses . clear ( ) ; } </s>

RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


"Basic block should contain at least a RET but is empty"


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
if
(
!
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
ArrayRef
<
unsigned
>
Regs
)
{
MIRBuilder
.
buildUnmerge
(
Regs
,
VReg
)
;
}
)
)
return
false
;
OutgoingValueHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static rtx alignment_mask ( rtx_insn * insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != AND || ! REG_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 0 ; rtx mask = XEXP ( SET_SRC ( body ) , 1 ) ; if ( CONST_INT_P ( mask ) ) { if ( INTVAL ( mask ) == - 16 ) return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; else return 0 ; } if ( ! REG_P ( mask ) ) return 0 ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; rtx real_mask = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( use ) , mask ) ) continue ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return 0 ; rtx_insn * const_insn = DF_REF_INSN ( def_link -> ref ) ; rtx const_body = PATTERN ( const_insn ) ; if ( GET_CODE ( const_body ) != SET ) return 0 ; real_mask = SET_SRC ( const_body ) ; if ( ! CONST_INT_P ( real_mask ) || INTVAL ( real_mask ) != - 16 ) return 0 ; } if ( real_mask == 0 ) return 0 ; return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; } </s>

Check whether an rtx is an alignment mask , and if so , return a fully-expanded rtx for the masking operation .