<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const X86Subtarget & STI = MF . getSubtarget < X86Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const X86RegisterInfo & RegInfo = * STI . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; MachineInstr * New = nullptr ; Amount -= InternalAmt ; if ( Amount ) { if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( IsLP64 , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned Opc = getADDriOpcode ( IsLP64 , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } return ; } if ( Opcode == TII . getCallFrameDestroyOpcode ( ) && InternalAmt ) { unsigned Opc = getSUBriOpcode ( IsLP64 , InternalAmt ) ; MachineInstr * New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( InternalAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; MBB . insert ( I , New ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void gen_ashift ( int type , int n , rtx reg ) { rtx n_rtx ; if ( n < 0 ) { if ( type == ASHIFT ) type = LSHIFTRT ; else type = ASHIFT ; n = - n ; } n_rtx = GEN_INT ( n ) ; gcc_assert ( satisfies_constraint_P27 ( n_rtx ) ) ; switch ( type ) { case ASHIFTRT : emit_insn ( gen_ashrsi3_k ( reg , reg , n_rtx ) ) ; break ; case LSHIFTRT : if ( n == 1 ) emit_insn ( gen_shlr ( reg , reg ) ) ; else emit_insn ( gen_lshrsi3_k ( reg , reg , n_rtx ) ) ; break ; case ASHIFT : emit_insn ( gen_ashlsi3_k ( reg , reg , n_rtx ) ) ; break ; default : gcc_unreachable ( ) ; } } </s>


<s> MCInst X86InstrInfo :: getNop ( ) const { MCInst Nop ; Nop . setOpcode ( X86 :: NOOP ) ; return Nop ; } </s>

Return the noop instruction to use for a noop .


<s> static bool ix86_function_value_regno_p ( const unsigned int regno ) { switch ( regno ) { case AX_REG : return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_abi != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_abi != MS_ABI ; case FIRST_BND_REG : return chkp_function_instrumented_p ( current_function_decl ) ; case ST0_REG : case ST1_REG : if ( TARGET_64BIT && ix86_abi == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ; } return false ; } </s>

Return true if N is a possible register number of function value .


<s> static void replace_swapped_aligned_store ( swap_web_entry * insn_entry , rtx_insn * store_insn ) { unsigned uid = INSN_UID ( store_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && insn_entry [ uid ] . is_store ) ; rtx body = PATTERN ( store_insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , 0 ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , 0 ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= 128 ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && ( GET_CODE ( SET_DEST ( new_body ) ) == MEM ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( store_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( store_insn ) ; remove_insn ( store_insn ) ; store_insn -> set_deleted ( ) ; uid2 = INSN_UID ( swap_insn ) ; mark_swaps_for_removal ( insn_entry , uid2 ) ; replace_swap_with_copy ( insn_entry , uid2 ) ; } </s>

Given that STORE_INSN represents an aligned store-with-swap of a swapped value , replace the store with an aligned store ( without swap ) and replace the swap with a copy insn .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_WrappedRegister
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s>
DEBUG_FUNCTION
char
*
rs6000_debug_addr_mask
(
addr_mask_type
mask
,
bool
keep_spaces
)
{
static
char
ret
[
8
]
;
char
*
p
=
ret
;
if
(
(
mask
&
RELOAD_REG_VALID
)
!=
0
)
*
p
++
=
'v'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_MULTIPLE
)
!=
0
)
*
p
++
=
'm'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_INDEXED
)
!=
0
)
*
p
++
=
'i'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_QUAD_OFFSET
)
!=
0
)
*
p
++
=
'O'
;
else
if
(
(
mask
&
RELOAD_REG_OFFSET
)
!=
0
)
*
p
++
=
'o'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_INCDEC
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_MODIFY
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_AND_M16
)
!=
0
)
*
p
++
=
'&'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
*
p
=
'\0'
;
return
ret
;
}
</s>

Inner function printing just the address mask for a particular reload register class .


<s> static void ix86_seh_fixup_eh_fallthru ( void ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , EXIT_BLOCK_PTR_FOR_FN ( cfun ) -> preds ) { rtx_insn * insn , * next ; for ( insn = BB_END ( e -> src ) ; insn != NULL ; insn = PREV_INSN ( insn ) ) if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_EPILOGUE_BEG ) break ; if ( insn == NULL ) continue ; insn = prev_active_insn ( insn ) ; if ( insn == NULL || ! can_throw_internal ( insn ) ) continue ; for ( next = NEXT_INSN ( insn ) ; next != NULL ; next = NEXT_INSN ( next ) ) if ( NOTE_P ( next ) && NOTE_KIND ( next ) == NOTE_INSN_VAR_LOCATION ) insn = next ; else break ; emit_insn_after ( gen_nops ( const1_rtx ) , insn ) ; } } </s>

Fix up a Windows system unwinder issue . If an EH region falls through into the epilogue , the Windows system unwinder will apply epilogue logic and produce incorrect offsets . This can be avoided by adding a nop between the last insn that can throw and the first insn of the epilogue .


"stack re-alignment, but LLVM couldn't handle it "

"(probably because it has a dynamic alloca)."

"SP has to be saved in order to align variable sized stack object!"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Switch should handle all register classes"


<s> static bool mips_use_shadow_register_set_p ( tree type ) { return lookup_attribute ( "use_shadow_register_set" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Check if the attribute to use shadow register set is set for a function .


<s> bool MipsAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; return AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s>
static
void
rs6000_print_options_internal
(
FILE
*
file
,
int
indent
,
const
char
*
string
,
HOST_WIDE_INT
flags
,
const
char
*
prefix
,
const
struct
rs6000_opt_mask
*
opts
,
size_t
num_elements
)
{
size_t
i
;
size_t
start_column
=
0
;
size_t
cur_column
;
size_t
max_column
=
120
;
size_t
prefix_len
=
strlen
(
prefix
)
;
size_t
comma_len
=
0
;
const
char
*
comma
=
""
;
if
(
indent
)
start_column
+=
fprintf
(
file
,
"%*s"
,
indent
,
""
)
;
if
(
!
flags
)
{
fprintf
(
stderr
,
DEBUG_FMT_S
,
string
,
"<none>"
)
;
return
;
}
start_column
+=
fprintf
(
stderr
,
DEBUG_FMT_WX
,
string
,
flags
)
;
cur_column
=
start_column
;
for
(
i
=
0
;
i
<
num_elements
;
i
++
)
{
bool
invert
=
opts
[
i
]
.
invert
;
const
char
*
name
=
opts
[
i
]
.
name
;
const
char
*
no_str
=
""
;
HOST_WIDE_INT
mask
=
opts
[
i
]
.
mask
;
size_t
len
=
comma_len
+
prefix_len
+
strlen
(
name
)
;
if
(
!
invert
)
{
if
(
(
flags
&
mask
)
==
0
)
{
no_str
=
"no-"
;
len
+=
sizeof
(
"no-"
)
1
;
}
flags
&=
~
mask
;
}
else
{
if
(
(
flags
&
mask
)
!=
0
)
{
no_str
=
"no-"
;
len
+=
sizeof
(
"no-"
)
1
;
}
flags
|=
mask
;
}
cur_column
+=
len
;
if
(
cur_column
>
max_column
)
{
fprintf
(
stderr
,
", \\\n%*s"
,
(
int
)
start_column
,
""
)
;
cur_column
=
start_column
+
len
;
comma
=
""
;
}
fprintf
(
file
,
"%s%s%s%s"
,
comma
,
prefix
,
no_str
,
name
)
;
comma
=
", "
;
comma_len
=
sizeof
(
", "
)
1
;
}
fputs
(
"\n"
,
file
)
;
}
</s>

Helper function to print the current isa or misc options on a line .


<s> bool isFPImm ( ) const { return Kind == k_FPImm ; } </s>

isFPImm - Tests if this is a MO_FPImmediate operand .


<s> static void rs6000_emit_dot_insn ( rtx dst , rtx src , int dot , rtx ccreg ) { if ( dot == 0 ) { emit_move_insn ( dst , src ) ; return ; } if ( cc_reg_not_cr0_operand ( ccreg , CCmode ) ) { emit_move_insn ( dst , src ) ; emit_move_insn ( ccreg , gen_rtx_COMPARE ( CCmode , dst , const0_rtx ) ) ; return ; } rtx ccset = gen_rtx_SET ( ccreg , gen_rtx_COMPARE ( CCmode , src , const0_rtx ) ) ; if ( dot == 1 ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , dst ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , clobber ) ) ) ; } else { rtx set = gen_rtx_SET ( dst , src ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , ccset , set ) ) ) ; } } </s>

Emit a potentially record-form instruction , setting DST from SRC . If DOT is 0 , that is all ; otherwise , set CCREG to the result of the signed comparison of DST with zero . If DOT is 1 , the generated RTL does n't care about the DST result ; if DOT is 2 , it does . If CCREG is CR0 do a single dot insn ( as a PARALLEL ) ; otherwise , do a SET and a separate COMPARE .


<s> bool useAA ( ) const override { return true ; } </s>

Enable use of alias analysis during code generation ( during MI scheduling , DAGCombine , etc . ) .


<s> static void sh_trampoline_init ( rtx tramp_mem , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx tramp = force_reg ( Pmode , XEXP ( tramp_mem , 0 ) ) ; if ( TARGET_FDPIC ) { rtx a = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( tramp_mem , 0 ) , 8 ) ) ; sh_emit_storesi ( tramp_mem , 0 , a ) ; sh_emit_storesi ( tramp_mem , 4 , sh_get_fdpic_reg_initial_val ( ) ) ; sh_emit_storehi ( tramp_mem , 8 , 0xd302 , 0xd203 ) ; sh_emit_storehi ( tramp_mem , 12 , 0x6122 , 0x5c21 ) ; sh_emit_storehi ( tramp_mem , 16 , 0x412b , 0x0009 ) ; sh_emit_storesi ( tramp_mem , 20 , cxt ) ; sh_emit_storesi ( tramp_mem , 24 , fnaddr ) ; } else { sh_emit_storehi ( tramp_mem , 0 , 0xd202 , 0xd301 ) ; sh_emit_storehi ( tramp_mem , 4 , 0x422b , 0x0009 ) ; sh_emit_storesi ( tramp_mem , 8 , cxt ) ; sh_emit_storesi ( tramp_mem , 12 , fnaddr ) ; } if ( TARGET_HARD_SH4 ) { if ( ! TARGET_INLINE_IC_INVALIDATE || ( ! ( TARGET_SH4A || TARGET_SH4_300 ) && TARGET_USERMODE ) ) emit_library_call ( function_symbol ( NULL , "__ic_invalidate" , FUNCTION_ORDINARY ) . sym , LCT_NORMAL , VOIDmode , 1 , tramp , SImode ) ; else emit_insn ( gen_ic_invalidate_line ( tramp ) ) ; } } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> const uint32_t * MipsRegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; return CSR_O32_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static unsigned getIntrinsicID ( const SDNode * N ) { unsigned Opcode = N -> getOpcode ( ) ; switch ( Opcode ) { default : return Intrinsic :: not_intrinsic ; case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; if ( IID < Intrinsic :: num_intrinsics ) return IID ; return Intrinsic :: not_intrinsic ; } } } </s>

Return the target intrinsic ID of a function , or 0 .


<s> bool SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcFPMoverPass ( getSparcTargetMachine ( ) ) ) ; addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const FPGASubtarget * FPGATargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute FPGAAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef FPGA = ! FPGAAttr . hasAttribute ( Attribute :: None ) ? FPGAAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( FPGA . size ( ) + FS . size ( ) ) ; Key += FPGA ; Key += FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < FPGASubtarget > ( TargetTriple , FPGA , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

FPGA FPGA FPGA FPGA "target-cpu" "target-features" FPGA FPGA FPGA 512 FPGA FPGA FPGA FPGA


<s> static void csky_add_gc_roots ( void ) { gcc_obstack_init ( & minipool_obstack ) ; minipool_startobj = ( char * ) obstack_alloc ( & minipool_obstack , 0 ) ; } </s>

Allow GC scanning of the minipool obstack .


<s> rtx aarch64_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return const0_rtx ; return aarch64_return_addr_rtx ( ) ; } </s>

Implement RETURN_ADDR_RTX . We do not support moving back to a previous frame .


<s> int rx_adjust_insn_length ( rtx_insn * insn , int current_length ) { rtx extend , mem , offset ; bool zero ; int factor ; if ( ! INSN_P ( insn ) ) return current_length ; switch ( INSN_CODE ( insn ) ) { default : return current_length ; case CODE_FOR_plussi3_zero_extendhi : case CODE_FOR_andsi3_zero_extendhi : case CODE_FOR_iorsi3_zero_extendhi : case CODE_FOR_xorsi3_zero_extendhi : case CODE_FOR_divsi3_zero_extendhi : case CODE_FOR_udivsi3_zero_extendhi : case CODE_FOR_minussi3_zero_extendhi : case CODE_FOR_smaxsi3_zero_extendhi : case CODE_FOR_sminsi3_zero_extendhi : case CODE_FOR_multsi3_zero_extendhi : case CODE_FOR_comparesi3_zero_extendhi : zero = true ; factor = 2 ; break ; case CODE_FOR_plussi3_sign_extendhi : case CODE_FOR_andsi3_sign_extendhi : case CODE_FOR_iorsi3_sign_extendhi : case CODE_FOR_xorsi3_sign_extendhi : case CODE_FOR_divsi3_sign_extendhi : case CODE_FOR_udivsi3_sign_extendhi : case CODE_FOR_minussi3_sign_extendhi : case CODE_FOR_smaxsi3_sign_extendhi : case CODE_FOR_sminsi3_sign_extendhi : case CODE_FOR_multsi3_sign_extendhi : case CODE_FOR_comparesi3_sign_extendhi : zero = false ; factor = 2 ; break ; case CODE_FOR_plussi3_zero_extendqi : case CODE_FOR_andsi3_zero_extendqi : case CODE_FOR_iorsi3_zero_extendqi : case CODE_FOR_xorsi3_zero_extendqi : case CODE_FOR_divsi3_zero_extendqi : case CODE_FOR_udivsi3_zero_extendqi : case CODE_FOR_minussi3_zero_extendqi : case CODE_FOR_smaxsi3_zero_extendqi : case CODE_FOR_sminsi3_zero_extendqi : case CODE_FOR_multsi3_zero_extendqi : case CODE_FOR_comparesi3_zero_extendqi : zero = true ; factor = 1 ; break ; case CODE_FOR_plussi3_sign_extendqi : case CODE_FOR_andsi3_sign_extendqi : case CODE_FOR_iorsi3_sign_extendqi : case CODE_FOR_xorsi3_sign_extendqi : case CODE_FOR_divsi3_sign_extendqi : case CODE_FOR_udivsi3_sign_extendqi : case CODE_FOR_minussi3_sign_extendqi : case CODE_FOR_smaxsi3_sign_extendqi : case CODE_FOR_sminsi3_sign_extendqi : case CODE_FOR_multsi3_sign_extendqi : case CODE_FOR_comparesi3_sign_extendqi : zero = false ; factor = 1 ; break ; } extend = single_set ( insn ) ; gcc_assert ( extend != NULL_RTX ) ; extend = SET_SRC ( extend ) ; if ( GET_CODE ( XEXP ( extend , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( extend , 0 ) ) == SIGN_EXTEND ) extend = XEXP ( extend , 0 ) ; else extend = XEXP ( extend , 1 ) ; gcc_assert ( ( zero && ( GET_CODE ( extend ) == ZERO_EXTEND ) ) || ( ! zero && ( GET_CODE ( extend ) == SIGN_EXTEND ) ) ) ; mem = XEXP ( extend , 0 ) ; gcc_checking_assert ( MEM_P ( mem ) ) ; if ( REG_P ( XEXP ( mem , 0 ) ) ) return ( zero && factor == 1 ) ? 2 : 3 ; gcc_checking_assert ( GET_CODE ( XEXP ( mem , 0 ) ) == PLUS ) ; gcc_checking_assert ( REG_P ( XEXP ( XEXP ( mem , 0 ) , 0 ) ) ) ; offset = XEXP ( XEXP ( mem , 0 ) , 1 ) ; gcc_checking_assert ( GET_CODE ( offset ) == CONST_INT ) ; if ( IN_RANGE ( INTVAL ( offset ) , 0 , 255 * factor ) ) return ( zero && factor == 1 ) ? 3 : 4 ; return ( zero && factor == 1 ) ? 4 : 5 ; } </s>

Compute the real length of the extending load-and-op instructions .


Return true if the function body might clobber register REGNO . We know that REGNO is call-saved .


<s> static int rs6000_use_sched_lookahead ( void ) { switch ( rs6000_tune ) { case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : return 4 ; case PROCESSOR_CELL : return ( reload_completed ? 8 : 0 ) ; default : return 0 ; } } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> rtx find_addr_reg ( rtx addr ) { while ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == REG && REGNO ( XEXP ( addr , 0 ) ) != 0 ) addr = XEXP ( addr , 0 ) ; else if ( GET_CODE ( XEXP ( addr , 1 ) ) == REG && REGNO ( XEXP ( addr , 1 ) ) != 0 ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 0 ) ) ) addr = XEXP ( addr , 1 ) ; else if ( CONSTANT_P ( XEXP ( addr , 1 ) ) ) addr = XEXP ( addr , 0 ) ; else gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( addr ) == REG && REGNO ( addr ) != 0 ) ; return addr ; } </s>

Return a REG that occurs in ADDR with coefficient 1 . ADDR can be effectively incremented by incrementing REG . r0 is special and we must not select it as an address register by this routine since our caller will try to increment the returned register via an `` la '' instruction .


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; aarch64_layout_frame ( ) ; return known_eq ( cfun -> machine -> frame . frame_size , 0 ) ; } </s>

Return TRUE if we can use a simple_return insn . This function checks whether the callee saved stack is empty , which means no restore actions are need . The pro_and_epilogue will use this to check whether shrink-wrapping opt is feasible .


<s> virtual ~ SystemZCallingConventionRegisters ( ) { } </s>


<s> const MCPhysReg * SystemZRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( MF -> getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_SaveList ; return CSR_SystemZ_SaveList ; } </s>


<s> unsigned getMinPrefetchStride ( ) { return 2048 ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR16_loRegClassID
:
case
AArch64
::
FPR32_with_hsub_in_FPR16_loRegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; splat_val = val ; msb_val = val >= 0 ? 0 : - 1 ; if ( val == 0 && step > 1 ) { for ( i = 1 ; i < nunits ; ++ i ) { unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; HOST_WIDE_INT elt_val = const_vector_elt_as_int ( op , elt ) ; if ( ( i & ( step - 1 ) ) == step - 1 ) { if ( ! EASY_VECTOR_MSB ( elt_val , inner ) ) break ; } else if ( elt_val ) break ; } if ( i == nunits ) return true ; } for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( HOST_WIDE_INT ) ( ( unsigned HOST_WIDE_INT ) small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; inner = smallest_int_mode_for_size ( bitsize ) ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else if ( EASY_VECTOR_MSB ( splat_val , inner ) && step == 1 ) ; else return false ; for ( i = 1 ; i < nunits ; ++ i ) { HOST_WIDE_INT desired_val ; unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; if ( ( i & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != const_vector_elt_as_int ( op , elt ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


"Both vector needs to be equally scalable"

Try to calculate op costs for min/max reduction operations .


<s> bool addRange ( uint64_t Start , uint64_t End , Instruction * Inst ) { auto I = std :: lower_bound ( Ranges . begin ( ) , Ranges . end ( ) , Start , [ ] ( const Range & LHS , uint64_t RHS ) { return LHS . End <= RHS ; } ) ; if ( I != Ranges . end ( ) && End > I -> Start ) { return false ; } Ranges . insert ( I , { Start , End , Inst } ) ; return true ; } </s>

addRange - Add an address range to the list of ranges for this unit .


<s> bool ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { bool hasAtomicCmpXchg = ! Subtarget -> isThumb ( ) || Subtarget -> hasV8MBaselineOps ( ) ; return getTargetMachine ( ) . getOptLevel ( ) != 0 && hasAtomicCmpXchg ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


Function to tell the preprocessor about the defines for the current target .


"considering end of repeat loop at insn %d\n"

Figure out where to put LABEL , which is the label for a repeat loop . If INCLUDING , LAST_INSN is the last instruction in the loop , otherwise the loop ends just before LAST_INSN . If SHARED , insns other than the `` repeat '' might use LABEL to jump to the loop 's continuation point . Return the last instruction in the adjusted loop .


<s>
SDValue
CSKYTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented op"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

CSKY
CSKY
"unimplemented op"
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::GlobalTLSAddress
ISD::JumpTable
ISD::BlockAddress
ISD::VASTART
ISD::FRAMEADDR
ISD::RETURNADDR


<s>
void
AArch64TargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this"
)
;
case
ISD
::
BITCAST
:
ReplaceBITCASTResults
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
VECREDUCE_ADD
:
case
ISD
::
VECREDUCE_SMAX
:
case
ISD
::
VECREDUCE_SMIN
:
case
ISD
::
VECREDUCE_UMAX
:
case
ISD
::
VECREDUCE_UMIN
:
Results
.
push_back
(
LowerVECREDUCE
(
SDValue
(
N
,
0
)
,
DAG
)
)
;
return
;
case
AArch64ISD
::
SADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
SADDV
)
;
return
;
case
AArch64ISD
::
UADDV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
ADD
,
AArch64ISD
::
UADDV
)
;
return
;
case
AArch64ISD
::
SMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMIN
,
AArch64ISD
::
SMINV
)
;
return
;
case
AArch64ISD
::
UMINV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMIN
,
AArch64ISD
::
UMINV
)
;
return
;
case
AArch64ISD
::
SMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
SMAX
,
AArch64ISD
::
SMAXV
)
;
return
;
case
AArch64ISD
::
UMAXV
:
ReplaceReductionResults
(
N
,
Results
,
DAG
,
ISD
::
UMAX
,
AArch64ISD
::
UMAXV
)
;
return
;
case
ISD
::
FP_TO_UINT
:
case
ISD
::
FP_TO_SINT
:
assert
(
N
->
getValueType
(
0
)
==
MVT
::
i128
&&
"unexpected illegal conversion"
)
;
return
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_128Results
(
N
,
Results
,
DAG
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


Return true if X is a legitimate address with a 14-bit offset shifted 2 . MODE is the mode of the value being accessed .


<s>
static
void
mips_output_filename
(
FILE
*
stream
,
const
char
*
name
)
{
if
(
dwarf_debuginfo_p
(
)
)
return
;
else
if
(
mips_output_filename_first_time
)
{
mips_output_filename_first_time
=
0
;
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
else
if
(
write_symbols
==
DBX_DEBUG
)
return
;
else
if
(
name
!=
current_function_file
&&
strcmp
(
name
,
current_function_file
)
!=
0
)
{
num_source_filenames
+=
1
;
current_function_file
=
name
;
fprintf
(
stream
,
"\t.file\t%d "
,
num_source_filenames
)
;
output_quoted_string
(
stream
,
name
)
;
putc
(
'\n'
,
stream
)
;
}
}
</s>

Emit a new filename to a stream . If we are smuggling stabs , try to put out a MIPS ECOFF file and a stab .


<s> static machine_mode hfa_element_mode ( const_tree type , bool nested ) { machine_mode element_mode = VOIDmode ; machine_mode mode ; enum tree_code code = TREE_CODE ( type ) ; int know_element_mode = 0 ; tree t ; if ( ! nested && ( ! TYPE_SIZE ( type ) || integer_zerop ( TYPE_SIZE ( type ) ) ) ) return VOIDmode ; switch ( code ) { case VOID_TYPE : case INTEGER_TYPE : case ENUMERAL_TYPE : case BOOLEAN_TYPE : case POINTER_TYPE : case OFFSET_TYPE : case REFERENCE_TYPE : case METHOD_TYPE : case LANG_TYPE : case FUNCTION_TYPE : return VOIDmode ; case COMPLEX_TYPE : if ( GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_COMPLEX_FLOAT && TYPE_MODE ( type ) != TCmode ) return GET_MODE_INNER ( TYPE_MODE ( type ) ) ; else return VOIDmode ; case REAL_TYPE : if ( nested && TYPE_MODE ( type ) != TFmode ) return TYPE_MODE ( type ) ; else return VOIDmode ; case ARRAY_TYPE : return hfa_element_mode ( TREE_TYPE ( type ) , 1 ) ; case RECORD_TYPE : case UNION_TYPE : case QUAL_UNION_TYPE : for ( t = TYPE_FIELDS ( type ) ; t ; t = DECL_CHAIN ( t ) ) { if ( TREE_CODE ( t ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( t ) ) continue ; mode = hfa_element_mode ( TREE_TYPE ( t ) , 1 ) ; if ( know_element_mode ) { if ( mode != element_mode ) return VOIDmode ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT ) return VOIDmode ; else { know_element_mode = 1 ; element_mode = mode ; } } return element_mode ; default : return VOIDmode ; } return VOIDmode ; } </s>

Check whether TYPE is a homogeneous floating point aggregate . If it is , return the mode of the floating point type that appears in all leafs . If it is not , return VOIDmode . An aggregate is a homogeneous floating point aggregate is if all fields/elements in it have the same floating point type ( e.g , SFmode ) . 128-bit quad-precision floats are excluded .


<s> std :: pair < unsigned , const TargetRegisterClass * > PPCTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'b' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RC_NOX0RegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRC_NOR0RegClass ) ; case 'r' : if ( VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) ) return std :: make_pair ( 0U , & PPC :: G8RCRegClass ) ; return std :: make_pair ( 0U , & PPC :: GPRCRegClass ) ; case 'f' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return std :: make_pair ( 0U , & PPC :: F4RCRegClass ) ; if ( VT == MVT :: f64 || VT == MVT :: i64 ) return std :: make_pair ( 0U , & PPC :: F8RCRegClass ) ; break ; case 'v' : return std :: make_pair ( 0U , & PPC :: VRRCRegClass ) ; case 'y' : return std :: make_pair ( 0U , & PPC :: CRRCRegClass ) ; } } else if ( Constraint == "wc" ) { return std :: make_pair ( 0U , & PPC :: CRBITRCRegClass ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . first && VT == MVT :: i64 && PPCSubTarget . isPPC64 ( ) && PPC :: GPRCRegClass . contains ( R . first ) ) { const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , PPC :: sub_32 , & PPC :: G8RCRegClass ) , & PPC :: G8RCRegClass ) ; } return R ; } </s>

Given a physical register constraint ( e.g .


<s> unsigned X86InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex , unsigned & MemBytes ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) , MemBytes ) ) if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 1 , FrameIndex ) ) return MI . getOperand ( 0 ) . getReg ( ) ; return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
MipsInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\t.set\tpush\n"
;
O
<<
"\t.set\tmips32r2\n"
;
break
;
case
Mips
::
Save16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
SaveX16
:
O
<<
"\tsave\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
"\n"
;
return
;
case
Mips
::
Restore16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
" # 16 bit inst\n"
;
return
;
case
Mips
::
RestoreX16
:
O
<<
"\trestore\t"
;
printSaveRestore
(
MI
,
STI
,
O
)
;
O
<<
"\n"
;
return
;
}
if
(
!
printAliasInstr
(
MI
,
Address
,
STI
,
O
)
&&
!
printAlias
(
*
MI
,
Address
,
STI
,
O
)
)
printInstruction
(
MI
,
Address
,
STI
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
Mips
::
RDHWR
:
case
Mips
::
RDHWR64
:
O
<<
"\n\t.set\tpop"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool aarch64_legitimize_address_displacement ( rtx * offset1 , rtx * offset2 , poly_int64 orig_offset , machine_mode mode ) { HOST_WIDE_INT size ; if ( GET_MODE_SIZE ( mode ) . is_constant ( & size ) ) { HOST_WIDE_INT const_offset , second_offset ; const_offset = orig_offset . coeffs [ 0 ] - orig_offset . coeffs [ 1 ] ; if ( mode == TImode || mode == TFmode ) second_offset = ( ( const_offset + 0x100 ) & 0x1f8 ) - 0x100 ; else if ( ( const_offset & ( size - 1 ) ) != 0 ) second_offset = ( ( const_offset + 0x100 ) & 0x1ff ) - 0x100 ; else second_offset = const_offset & ( size < 4 ? 0xfff : 0x3ffc ) ; if ( second_offset == 0 || known_eq ( orig_offset , second_offset ) ) return false ; * offset1 = gen_int_mode ( orig_offset - second_offset , Pmode ) ; * offset2 = gen_int_mode ( second_offset , Pmode ) ; return true ; } else { unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; machine_mode step_mode = ( vec_flags & VEC_STRUCT ) != 0 ? SVE_BYTE_MODE : mode ; HOST_WIDE_INT factor = GET_MODE_SIZE ( step_mode ) . coeffs [ 1 ] ; HOST_WIDE_INT vnum = orig_offset . coeffs [ 1 ] / factor ; if ( vec_flags & VEC_SVE_DATA ) vnum = ( ( vnum + 128 ) & 255 ) - 128 ; else vnum = ( ( vnum + 256 ) & 511 ) - 256 ; if ( vnum == 0 ) return false ; poly_int64 second_offset = GET_MODE_SIZE ( step_mode ) * vnum ; if ( known_eq ( second_offset , orig_offset ) ) return false ; * offset1 = gen_int_mode ( orig_offset - second_offset , Pmode ) ; * offset2 = gen_int_mode ( second_offset , Pmode ) ; return true ; } } </s>

Split an out-of-range address displacement into a base and offset . Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise to increase opportunities for sharing the base address of different sizes . For unaligned accesses and TI/TF mode use the signed 9-bit range .


<s> pure_scalable_type_info :: analysis_result pure_scalable_type_info :: analyze_array ( const_tree type ) { pure_scalable_type_info element_info ; analysis_result result = element_info . analyze ( TREE_TYPE ( type ) ) ; if ( result != IS_PST ) return result ; tree nelts_minus_one = array_type_nelts ( type ) ; if ( ! tree_fits_uhwi_p ( nelts_minus_one ) ) return DOESNT_MATTER ; unsigned HOST_WIDE_INT count = tree_to_uhwi ( nelts_minus_one ) ; if ( count > MAX_PIECES ) return DOESNT_MATTER ; count += 1 ; if ( count * element_info . pieces . length ( ) > MAX_PIECES ) return DOESNT_MATTER ; poly_uint64 element_bytes ; if ( ! poly_int_tree_p ( TYPE_SIZE_UNIT ( TREE_TYPE ( type ) ) , & element_bytes ) ) gcc_unreachable ( ) ; gcc_assert ( ! element_info . pieces . is_empty ( ) ) ; for ( unsigned int i = 0 ; i < count ; ++ i ) for ( unsigned int j = 0 ; j < element_info . pieces . length ( ) ; ++ j ) { piece p = element_info . pieces [ j ] ; p . offset += i * element_bytes ; add_piece ( p ) ; } return IS_PST ; } </s>

Subroutine of analyze for handling ARRAY_TYPEs .


Returns assembly code to perform a DImode shift using a 64-bit global or out register on SPARC-V8+ .


<s> int nds32_can_use_bset_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) ) ; return ( TARGET_PERF_EXT && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bset ' instruction can be used with IVAL .


<s> bool SparcPassConfig :: addPreEmitPass ( ) { addPass ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned getNumFixupKinds ( ) const { return PPC :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> int direct_return ( void ) { if ( reload_completed ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == 32 && info -> first_fp_reg_save == 64 && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_size == 0 && ! info -> push_p ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> uint64_t SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static bool aarch64_evpc_trn ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT odd ; poly_uint64 nelt = d -> perm . length ( ) ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( ! d -> perm [ 0 ] . is_constant ( & odd ) || ( odd != 0 && odd != 1 ) || ! d -> perm . series_p ( 0 , 2 , odd , 2 ) || ! d -> perm . series_p ( 1 , 2 , nelt + odd , 2 ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; emit_set_insn ( out , gen_rtx_UNSPEC ( vmode , gen_rtvec ( 2 , in0 , in1 ) , odd ? UNSPEC_TRN2 : UNSPEC_TRN1 ) ) ; return true ; } </s>

Recognize patterns suitable for the TRN instructions .


<s> static unsigned HOST_WIDE_INT mips_shift_truncation_mask ( machine_mode mode ) { if ( TARGET_LOONGSON_VECTORS && VECTOR_MODE_P ( mode ) ) return 0 ; return GET_MODE_BITSIZE ( mode ) - 1 ; } </s>

Implement TARGET_SHIFT_TRUNCATION_MASK . We want to keep the default behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even when TARGET_LOONGSON_VECTORS is true .


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int Cost = 0 ; if ( isWideningInstruction ( Ty , Opcode , Args ) ) Cost += ST -> getWideningBaseCost ( ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return Cost + BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: SDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { Cost += getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } LLVM_FALLTHROUGH ; case ISD :: UDIV : if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( ISD :: MULHU , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * 2 + AddCost * 2 + ShrCost * 2 + 1 ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return ( Cost + 1 ) * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static int mips_fpr_return_fields ( const_tree valtype , tree * fields , bool * has_cxx_zero_width_bf , bool * has_cxx17_empty_base ) { tree field ; int i ; if ( ! TARGET_NEWABI ) return 0 ; if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return 0 ; i = 0 ; for ( field = TYPE_FIELDS ( valtype ) ; field != 0 ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) != FIELD_DECL ) continue ; if ( cxx17_empty_base_field_p ( field ) ) { * has_cxx17_empty_base = true ; continue ; } if ( DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD ( field ) ) { * has_cxx_zero_width_bf = true ; continue ; } if ( ! SCALAR_FLOAT_TYPE_P ( TREE_TYPE ( field ) ) ) return 0 ; if ( i == 2 ) return 0 ; fields [ i ++ ] = field ; } return i ; } </s>

See whether VALTYPE is a record whose fields should be returned in floating-point registers . If so , return the number of fields and list them in FIELDS ( which should have two elements ) . Return 0 otherwise . For n32 & n64 , a structure with one or two fields is returned in floating-point registers as long as every field has a floating-point type . The C++ FE used to remove zero-width bit-fields in GCC 11 and earlier . To make a proper diagnostic , this function will set HAS_CXX_ZERO_WIDTH_BF to true once a C++ zero-width bit-field shows up , and then ignore it . We had failed to ignore C++17 empty bases in GCC 7 , 8 , 9 , 10 , and 11 . This caused an ABI incompatibility between C++14 and C++17 . This is fixed now and to make a proper diagnostic , this function will set HAS_CXX17_EMPTY_BASE to true once a C++17 empty base shows up , and then ignore it . The caller should use the value of HAS_CXX17_EMPTY_BASE and/or HAS_CXX_ZERO_WIDTH_BF to emit a proper -Wpsabi inform .


<s> static rtx gen_rx_rtsd_vector ( unsigned int adjust , unsigned int low , unsigned int high ) { unsigned int i ; unsigned int bias = 3 ; unsigned int count = ( high - low ) + bias ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , adjust ) ) ; for ( i = 0 ; i < count - 2 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == 0 ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; XVECEXP ( vector , 0 , count - 1 ) = ret_rtx ; return vector ; } </s>

Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned SparcInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: LDri || MI -> getOpcode ( ) == SP :: LDFri || MI -> getOpcode ( ) == SP :: LDDFri ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>


<s> bool operands_ok_ldrd_strd ( rtx rt , rtx rt2 , rtx rn , HOST_WIDE_INT offset , bool wback , bool load ) { unsigned int t , t2 , n ; if ( ! reload_completed ) return true ; if ( ! offset_ok_for_ldrd_strd ( offset ) ) return false ; t = REGNO ( rt ) ; t2 = REGNO ( rt2 ) ; n = REGNO ( rn ) ; if ( ( TARGET_THUMB2 ) && ( ( wback && ( n == t || n == t2 ) ) || ( t == SP_REGNUM ) || ( t == PC_REGNUM ) || ( t2 == SP_REGNUM ) || ( t2 == PC_REGNUM ) || ( ! load && ( n == PC_REGNUM ) ) || ( load && ( t == t2 ) ) || ( ! wback && load && fix_cm3_ldrd && ( n == t ) ) ) ) return false ; if ( ( TARGET_ARM ) && ( ( wback && ( n == t || n == t2 ) ) || ( t2 == PC_REGNUM ) || ( t % 2 != 0 ) || ( t2 != t + 1 ) || ( n == PC_REGNUM ) ) ) return false ; return true ; } </s>

Checks whether the operands are valid for use in an LDRD/STRD instruction . Assumes that RT , RT2 , and RN are REG . This is guaranteed by the patterns . Assumes that the address in the base register RN is word aligned . Pattern guarantees that both memory accesses use the same base register , the offsets are constants within the range , and the gap between the offsets is 4 . If preload complete then check that registers are legal . WBACK indicates whether address is updated . LOAD indicates whether memory access is load or store .


<s>
void
AArch64FrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
AArch64Subtarget
&
Subtarget
=
MF
.
getSubtarget
<
AArch64Subtarget
>
(
)
;
const
TargetInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
DebugLoc
DL
;
bool
IsTailCallReturn
=
false
;
if
(
MBB
.
end
(
)
!=
MBBI
)
{
DL
=
MBBI
->
getDebugLoc
(
)
;
unsigned
RetOpcode
=
MBBI
->
getOpcode
(
)
;
IsTailCallReturn
=
RetOpcode
==
AArch64
::
TCRETURNdi
||
RetOpcode
==
AArch64
::
TCRETURNri
;
}
int
NumBytes
=
MFI
->
getStackSize
(
)
;
const
AArch64FunctionInfo
*
AFI
=
MF
.
getInfo
<
AArch64FunctionInfo
>
(
)
;
if
(
MF
.
getFunction
(
)
->
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
;
uint64_t
ArgumentPopSize
=
0
;
if
(
IsTailCallReturn
)
{
MachineOperand
&
StackAdjust
=
MBBI
->
getOperand
(
1
)
;
ArgumentPopSize
=
StackAdjust
.
getImm
(
)
;
}
else
{
ArgumentPopSize
=
AFI
->
getArgumentStackToRestore
(
)
;
}
MachineBasicBlock
::
iterator
LastPopI
=
MBB
.
getFirstTerminator
(
)
;
MachineBasicBlock
::
iterator
Begin
=
MBB
.
begin
(
)
;
while
(
LastPopI
!=
Begin
)
{
LastPopI
;
if
(
!
LastPopI
->
getFlag
(
MachineInstr
::
FrameDestroy
)
)
{
++
LastPopI
;
break
;
}
}
NumBytes
-=
AFI
->
getCalleeSavedStackSize
(
)
;
assert
(
NumBytes
>=
0
&&
"Negative stack allocation size!?"
)
;
if
(
!
hasFP
(
MF
)
)
{
bool
RedZone
=
canUseRedZone
(
MF
)
;
if
(
RedZone
&&
ArgumentPopSize
==
0
)
return
;
bool
NoCalleeSaveRestore
=
AFI
->
getCalleeSavedStackSize
(
)
==
0
;
int
StackRestoreBytes
=
RedZone
0
:
NumBytes
;
if
(
NoCalleeSaveRestore
)
StackRestoreBytes
+=
ArgumentPopSize
;
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
StackRestoreBytes
,
TII
,
MachineInstr
::
FrameDestroy
)
;
if
(
NoCalleeSaveRestore
||
ArgumentPopSize
==
0
)
return
;
NumBytes
=
0
;
}
if
(
NumBytes
||
MFI
->
hasVarSizedObjects
(
)
)
emitFrameOffset
(
MBB
,
LastPopI
,
DL
,
AArch64
::
SP
,
AArch64
::
FP
,
AFI
->
getCalleeSavedStackSize
(
)
+
16
,
TII
,
MachineInstr
::
FrameDestroy
)
;
if
(
ArgumentPopSize
)
emitFrameOffset
(
MBB
,
MBB
.
getFirstTerminator
(
)
,
DL
,
AArch64
::
SP
,
AArch64
::
SP
,
ArgumentPopSize
,
TII
,
MachineInstr
::
FrameDestroy
)
;
}
</s>


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


"parameter passing for argument of type "

Implement FUNCTION_ARG_BOUNDARY . Every parameter gets at least PARM_BOUNDARY bits of alignment , but will be given anything up to STACK_BOUNDARY bits if the type requires it . This makes sure that both before and after the layout of each argument , the Next Stacked Argument Address ( NSAA ) will have a minimum alignment of 8 bytes .


"We have a different number of location and args?!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static void expand_set_or_movmem_via_rep ( rtx destmem , rtx srcmem , rtx destptr , rtx srcptr , rtx value , rtx orig_value , rtx count , machine_mode mode , bool issetmem ) { rtx destexp ; rtx srcexp ; rtx countreg ; HOST_WIDE_INT rounded_count ; if ( mode == QImode && CONST_INT_P ( count ) && ! ( INTVAL ( count ) & 3 ) && ( ! issetmem || orig_value == const0_rtx ) ) mode = SImode ; if ( destptr != XEXP ( destmem , 0 ) || GET_MODE ( destmem ) != BLKmode ) destmem = adjust_automodify_address_nv ( destmem , BLKmode , destptr , 0 ) ; countreg = ix86_zero_extend_to_Pmode ( scale_counter ( count , GET_MODE_SIZE ( mode ) ) ) ; if ( mode != QImode ) { destexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; destexp = gen_rtx_PLUS ( Pmode , destexp , destptr ) ; } else destexp = gen_rtx_PLUS ( Pmode , destptr , countreg ) ; if ( ( ! issetmem || orig_value == const0_rtx ) && CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; destmem = shallow_copy_rtx ( destmem ) ; set_mem_size ( destmem , rounded_count ) ; } else if ( MEM_SIZE_KNOWN_P ( destmem ) ) clear_mem_size ( destmem ) ; if ( issetmem ) { value = force_reg ( mode , gen_lowpart ( mode , value ) ) ; emit_insn ( gen_rep_stos ( destptr , countreg , destmem , value , destexp ) ) ; } else { if ( srcptr != XEXP ( srcmem , 0 ) || GET_MODE ( srcmem ) != BLKmode ) srcmem = adjust_automodify_address_nv ( srcmem , BLKmode , srcptr , 0 ) ; if ( mode != QImode ) { srcexp = gen_rtx_ASHIFT ( Pmode , countreg , GEN_INT ( exact_log2 ( GET_MODE_SIZE ( mode ) ) ) ) ; srcexp = gen_rtx_PLUS ( Pmode , srcexp , srcptr ) ; } else srcexp = gen_rtx_PLUS ( Pmode , srcptr , countreg ) ; if ( CONST_INT_P ( count ) ) { rounded_count = ROUND_DOWN ( INTVAL ( count ) , ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) ) ; srcmem = shallow_copy_rtx ( srcmem ) ; set_mem_size ( srcmem , rounded_count ) ; } else { if ( MEM_SIZE_KNOWN_P ( srcmem ) ) clear_mem_size ( srcmem ) ; } emit_insn ( gen_rep_mov ( destptr , destmem , srcptr , srcmem , countreg , destexp , srcexp ) ) ; } } </s>

Output `` rep ; mov '' or `` rep ; stos '' instruction depending on ISSETMEM argument . When ISSETMEM is true , arguments SRCMEM and SRCPTR are ignored . When ISSETMEM is false , arguments VALUE and ORIG_VALUE are ignored . For setmem case , VALUE is a promoted to a wider size ORIG_VALUE . ORIG_VALUE is the original value passed to memset to fill the memory with . Other arguments have same meaning as for previous function .


<s> bool AArch64InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: PTEST_PP : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWrr : case AArch64 :: SUBSWrs : case AArch64 :: SUBSWrx : case AArch64 :: SUBSXrr : case AArch64 :: SUBSXrs : case AArch64 :: SUBSXrx : case AArch64 :: ADDSWrr : case AArch64 :: ADDSWrs : case AArch64 :: ADDSWrx : case AArch64 :: ADDSXrr : case AArch64 :: ADDSXrs : case AArch64 :: ADDSXrx : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWri : case AArch64 :: ADDSWri : case AArch64 :: SUBSXri : case AArch64 :: ADDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) ; return true ; case AArch64 :: ANDSWri : case AArch64 :: ANDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( AArch64_AM :: decodeLogicalImmediate ( MI -> getOperand ( 2 ) . getImm ( ) , MI -> getOpcode ( ) == AArch64 :: ANDSWri ? 32 : 64 ) != 0 ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { if ( isARM ) emitARMRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , ARMCC :: AL , 0 , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , ARMCC :: AL , 0 , TII , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARM ARM ARM::SP ARM::SP ARMCC::AL 0 ARM::SP ARM::SP ARMCC::AL 0


<s> unsigned getNumFixupKinds ( ) const { return Mips :: NumTargetFixupKinds ; } </s>


<s> void Thumb1RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitSPUpdate ( MBB , I , TII , dl , * this , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , TII , dl , * this , Amount ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static bool rs6000_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return true ; else if ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) && ! FLOAT128_IEEE_P ( mode ) ) return true ; else return false ; } </s>

Target hook for vector_mode_supported_p .


<s> machine_mode rx_select_cc_mode ( enum rtx_code cmp_code , rtx x , rtx y ) { if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) return CC_Fmode ; if ( y != const0_rtx ) return CCmode ; return mode_from_flags ( flags_from_code ( cmp_code ) ) ; } </s>

Return the minimal CC mode needed to implement ( CMP_CODE X Y ) .


<s> const ARMSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool AArch64FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static machine_mode rs6000_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VSX ) switch ( mode ) { case E_DFmode : return V2DFmode ; default : ; } if ( TARGET_ALTIVEC || TARGET_VSX ) switch ( mode ) { case E_SFmode : return V4SFmode ; case E_TImode : return V1TImode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } return word_mode ; } </s>


<s> bool AArch64TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , bool * Fast ) const { if ( Subtarget -> requiresStrictAlign ( ) ) return false ; if ( Fast ) { * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || VT . getStoreSize ( ) != 16 || Align <= 2 || VT == MVT :: v2i64 ; } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; if ( auto * C = dyn_cast < ConstantInt > ( AI -> getValOperand ( ) ) ) if ( AI -> getOperation ( ) == AtomicRMWInst :: Or && C -> isZero ( ) && AI -> use_empty ( ) ) return nullptr ; IRBuilder < > Builder ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , Align ( AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> bool ix86_check_no_addr_space ( rtx insn ) { subrtx_var_iterator :: array_type array ; FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( insn ) , ALL ) { rtx x = * iter ; if ( MEM_P ( x ) && ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( x ) ) ) return false ; } return true ; } </s>

Return false if INSN contains a MEM with a non-default address space .


<s> bool MipsBranchExpansion :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; IsPIC = TM . isPositionIndependent ( ) ; ABI = static_cast < const MipsTargetMachine & > ( TM ) . getABI ( ) ; STI = & MF . getSubtarget < MipsSubtarget > ( ) ; TII = static_cast < const MipsInstrInfo * > ( STI -> getInstrInfo ( ) ) ; if ( IsPIC && ABI . IsO32 ( ) && MF . getInfo < MipsFunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( MF , TII ) ; MFp = & MF ; ForceLongBranchFirstPass = ForceLongBranch ; bool longBranchChanged = handlePossibleLongBranch ( ) ; bool forbiddenSlotChanged = handleForbiddenSlot ( ) ; bool fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; bool loadDelaySlotChanged = handleLoadDelaySlot ( ) ; bool Changed = longBranchChanged || forbiddenSlotChanged || fpuDelaySlotChanged || loadDelaySlotChanged ; while ( forbiddenSlotChanged ) { longBranchChanged = handlePossibleLongBranch ( ) ; fpuDelaySlotChanged = handleFPUDelaySlot ( ) ; loadDelaySlotChanged = handleLoadDelaySlot ( ) ; if ( ! longBranchChanged && ! fpuDelaySlotChanged && ! loadDelaySlotChanged ) break ; forbiddenSlotChanged = handleForbiddenSlot ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".word" ) ParseDirectiveWord ( 2 , DirectiveID ) ; else if ( IDVal == ".llong" ) ParseDirectiveWord ( 8 , DirectiveID ) ; else if ( IDVal == ".tc" ) ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID ) ; else if ( IDVal == ".machine" ) ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".abiversion" ) ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".localentry" ) ParseDirectiveLocalEntry ( DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( ".gnu_attribute" ) ) ParseGNUAttribute ( DirectiveID . getLoc ( ) ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

PowerPC PPC PPC "target-cpu" "target-features" PPC


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> bool X86PassConfig :: addPreRegAlloc ( ) { addPass ( createX86MaxStackAlignmentHeuristicPass ( ) ) ; return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void AArch64TTIImpl :: getPeelingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: PeelingPreferences & PP ) { BaseT :: getPeelingPreferences ( L , SE , PP ) ; } </s>

Get target-customized preferences for the generic loop peeling transformation .


<s> bool aarch64_sve_cmp_immediate_p ( rtx x , bool signed_p ) { x = unwrap_const_vec_duplicate ( x ) ; return ( CONST_INT_P ( x ) && ( signed_p ? IN_RANGE ( INTVAL ( x ) , - 16 , 15 ) : IN_RANGE ( INTVAL ( x ) , 0 , 127 ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE CMP instruction . SIGNED_P says whether the operand is signed rather than unsigned .


"Cannot get the value of a constant bit"


<s> static bool aarch64_print_vector_float_operand ( FILE * f , rtx x , bool negate ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) ) return false ; REAL_VALUE_TYPE r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst0 ) ) asm_fprintf ( f , "0.0" ) ; else if ( real_equal ( & r , & dconst2 ) ) asm_fprintf ( f , "2.0" ) ; else if ( real_equal ( & r , & dconst1 ) ) asm_fprintf ( f , "1.0" ) ; else if ( real_equal ( & r , & dconsthalf ) ) asm_fprintf ( f , "0.5" ) ; else { const int buf_size = 20 ; char float_buf [ buf_size ] = { '\0' } ; real_to_decimal_for_mode ( float_buf , & r , buf_size , buf_size , 1 , GET_MODE ( elt ) ) ; asm_fprintf ( f , "%s" , float_buf ) ; } return true ; } </s>

Print floating-point vector immediate operand X to F , negating it first if NEGATE is true . Return true on success , false if it is n't a constant we can handle .


<s> static bool aarch64_optab_supported_p ( int op , machine_mode , machine_mode , optimization_type opt_type ) { switch ( op ) { case rsqrt_optab : return opt_type == OPTIMIZE_FOR_SPEED && use_rsqrt_p ( ) ; default : return true ; } } </s>

Implement the TARGET_OPTAB_SUPPORTED_P hook .


<s> static int ix86_division_cost ( const struct processor_costs * cost , enum machine_mode mode ) { machine_mode inner_mode = mode ; if ( VECTOR_MODE_P ( mode ) ) inner_mode = GET_MODE_INNER ( mode ) ; if ( SSE_FLOAT_MODE_SSEMATH_OR_HF_P ( mode ) ) return inner_mode == DFmode ? cost -> divsd : cost -> divss ; else if ( X87_FLOAT_MODE_P ( mode ) ) return cost -> fdiv ; else if ( FLOAT_MODE_P ( mode ) ) return ix86_vec_cost ( mode , inner_mode == DFmode ? cost -> divsd : cost -> divss ) ; else return cost -> divide [ MODE_INDEX ( mode ) ] ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AArch64 Conditional Compares"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
SDValue
X86TargetLowering
::
BuildSDIVPow2
(
SDNode
*
N
,
const
APInt
&
Divisor
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDNode
*
>
&
Created
)
const
{
AttributeList
Attr
=
DAG
.
getMachineFunction
(
)
.
getFunction
(
)
.
getAttributes
(
)
;
if
(
isIntDivCheap
(
N
->
getValueType
(
0
)
,
Attr
)
)
return
SDValue
(
N
,
0
)
;
assert
(
(
Divisor
.
isPowerOf2
(
)
||
Divisor
.
isNegatedPowerOf2
(
)
)
&&
"Unexpected divisor!"
)
;
if
(
!
Subtarget
.
canUseCMOV
(
)
)
return
SDValue
(
)
;
EVT
VT
=
N
->
getValueType
(
0
)
;
if
(
VT
!=
MVT
::
i16
&&
VT
!=
MVT
::
i32
&&
!
(
Subtarget
.
is64Bit
(
)
&&
VT
==
MVT
::
i64
)
)
return
SDValue
(
)
;
unsigned
Lg2
=
Divisor
.
countTrailingZeros
(
)
;
if
(
Lg2
==
1
)
return
SDValue
(
)
;
SDLoc
DL
(
N
)
;
SDValue
N0
=
N
->
getOperand
(
0
)
;
SDValue
Zero
=
DAG
.
getConstant
(
0
,
DL
,
VT
)
;
APInt
Lg2Mask
=
APInt
::
getLowBitsSet
(
VT
.
getSizeInBits
(
)
,
Lg2
)
;
SDValue
Pow2MinusOne
=
DAG
.
getConstant
(
Lg2Mask
,
DL
,
VT
)
;
SDValue
Cmp
=
DAG
.
getSetCC
(
DL
,
MVT
::
i8
,
N0
,
Zero
,
ISD
::
SETLT
)
;
SDValue
Add
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
VT
,
N0
,
Pow2MinusOne
)
;
SDValue
CMov
=
DAG
.
getNode
(
ISD
::
SELECT
,
DL
,
VT
,
Cmp
,
Add
,
N0
)
;
Created
.
push_back
(
Cmp
.
getNode
(
)
)
;
Created
.
push_back
(
Add
.
getNode
(
)
)
;
Created
.
push_back
(
CMov
.
getNode
(
)
)
;
SDValue
SRA
=
DAG
.
getNode
(
ISD
::
SRA
,
DL
,
VT
,
CMov
,
DAG
.
getConstant
(
Lg2
,
DL
,
MVT
::
i8
)
)
;
if
(
Divisor
.
isNonNegative
(
)
)
return
SRA
;
Created
.
push_back
(
SRA
.
getNode
(
)
)
;
return
DAG
.
getNode
(
ISD
::
SUB
,
DL
,
VT
,
Zero
,
SRA
)
;
}
</s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> unsigned X86InstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameLoadOpcode ( MI . getOpcode ( ) ) ) { unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ; return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ; } return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; case ISD :: ATOMIC_FENCE : return PerformATOMIC_FENCECombine ( N , DCI ) ; case ISD :: ATOMIC_STORE : return PerformATOMIC_STORECombine ( N , DCI ) ; case ISD :: OR : return PerformORCombine ( N , DCI , Subtarget ) ; case ISD :: SRA : return PerformSRACombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void aarch64_split_simd_combine ( rtx dst , rtx src1 , rtx src2 ) { machine_mode src_mode = GET_MODE ( src1 ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src1 ) && REG_P ( src2 ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( src_mode ) { case V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case DImode : gen = gen_aarch64_simd_combinedi ; break ; case DFmode : gen = gen_aarch64_simd_combinedf ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src1 , src2 ) ) ; return ; } } </s>


<s> X86DCFunction & getParent ( ) { return static_cast < X86DCFunction & > ( DCBasicBlock :: getParent ( ) ) ; } </s>

getParent - Return the last analyzed interval .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( REG_P ( addr ) ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , 0 ) ) == REG && CONST_INT_P ( XEXP ( addr , 1 ) ) ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return true ; } * base = NULL_RTX ; * offset = NULL_RTX ; return false ; } </s>

If MEM is in the form of `` base+offset '' , extract the two parts of address and set to BASE and OFFSET , otherwise return false after clearing BASE and OFFSET .


<s> ScheduleHazardRecognizer * ARMBaseInstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAG * DAG ) const { MultiHazardRecognizer * MHR = new MultiHazardRecognizer ( ) ; if ( Subtarget . isThumb2 ( ) || Subtarget . hasVFP2Base ( ) ) MHR -> AddHazardRecognizer ( std :: make_unique < ARMHazardRecognizerFPMLx > ( ) ) ; auto BHR = TargetInstrInfo :: CreateTargetPostRAHazardRecognizer ( II , DAG ) ; if ( BHR ) MHR -> AddHazardRecognizer ( std :: unique_ptr < ScheduleHazardRecognizer > ( BHR ) ) ; return MHR ; } </s>

Allocate and return a hazard recognizer to use for by non-scheduling passes .


<s> virtual const ARMSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
OperandType
type
,
\
uint8_t
index
,
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_VK_PAIR
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0_K1
+
(
index
/
2
)
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> unsigned getFirstDomain ( ) const { return CountTrailingZeros_32 ( AvailableDomains ) ; } </s>


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> unsigned MipsSEInstrInfo :: loadImmediate ( int64_t Imm , MachineBasicBlock & MBB , MachineBasicBlock :: iterator II , const DebugLoc & DL , unsigned * NewImm ) const { MipsAnalyzeImmediate AnalyzeImm ; const MipsSubtarget & STI = Subtarget ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Size = STI . isABI_N64 ( ) ? 64 : 32 ; unsigned LUi = STI . isABI_N64 ( ) ? Mips :: LUi64 : Mips :: LUi ; unsigned ZEROReg = STI . isABI_N64 ( ) ? Mips :: ZERO_64 : Mips :: ZERO ; const TargetRegisterClass * RC = STI . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; bool LastInstrIsADDiu = NewImm ; const MipsAnalyzeImmediate :: InstSeq & Seq = AnalyzeImm . Analyze ( Imm , Size , LastInstrIsADDiu ) ; MipsAnalyzeImmediate :: InstSeq :: const_iterator Inst = Seq . begin ( ) ; assert ( Seq . size ( ) && ( ! LastInstrIsADDiu || ( Seq . size ( ) > 1 ) ) ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; if ( Inst -> Opc == LUi ) BuildMI ( MBB , II , DL , get ( LUi ) , Reg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; else BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( ZEROReg ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; for ( ++ Inst ; Inst != Seq . end ( ) - LastInstrIsADDiu ; ++ Inst ) BuildMI ( MBB , II , DL , get ( Inst -> Opc ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( SignExtend64 < 16 > ( Inst -> ImmOpnd ) ) ; if ( LastInstrIsADDiu ) * NewImm = Inst -> ImmOpnd ; return Reg ; } </s>

Emit a series of instructions to load an immediate .


<s> void MipsInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\t.set\tpush\n" ; O << "\t.set\tmips32r2\n" ; } if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; switch ( MI -> getOpcode ( ) ) { default : break ; case Mips :: RDHWR : case Mips :: RDHWR64 : O << "\n\t.set\tpop" ; } } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
static
const
char
*
arm_invalid_return_type
(
const_tree
t
)
{
if
(
SCALAR_FLOAT_TYPE_P
(
t
)
&&
TYPE_PRECISION
(
t
)
==
16
)
return
N_
(
"functions cannot return __fp16 type"
)
;
return
;
}
</s>

arm
16
"functions cannot return __fp16 type"


<s> unsigned getNumRegisters ( LLVMContext & Context , EVT VT , Optional < MVT > RegisterVT ) const override { if ( VT == MVT :: i128 && RegisterVT . hasValue ( ) && RegisterVT . getValue ( ) == MVT :: Untyped ) return 1 ; return TargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Return the number of registers that this ValueType will eventually require .


<s>
static
SDValue
getTargetNode
(
SDValue
Op
,
SelectionDAG
&
DAG
,
unsigned
Flag
)
{
EVT
Ty
=
Op
.
getValueType
(
)
;
if
(
GlobalAddressSDNode
*
N
=
dyn_cast
<
GlobalAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetGlobalAddress
(
N
->
getGlobal
(
)
,
Op
.
getDebugLoc
(
)
,
Ty
,
0
,
Flag
)
;
if
(
ExternalSymbolSDNode
*
N
=
dyn_cast
<
ExternalSymbolSDNode
>
(
Op
)
)
return
DAG
.
getTargetExternalSymbol
(
N
->
getSymbol
(
)
,
Ty
,
Flag
)
;
if
(
BlockAddressSDNode
*
N
=
dyn_cast
<
BlockAddressSDNode
>
(
Op
)
)
return
DAG
.
getTargetBlockAddress
(
N
->
getBlockAddress
(
)
,
Ty
,
0
,
Flag
)
;
if
(
JumpTableSDNode
*
N
=
dyn_cast
<
JumpTableSDNode
>
(
Op
)
)
return
DAG
.
getTargetJumpTable
(
N
->
getIndex
(
)
,
Ty
,
Flag
)
;
if
(
ConstantPoolSDNode
*
N
=
dyn_cast
<
ConstantPoolSDNode
>
(
Op
)
)
return
DAG
.
getTargetConstantPool
(
N
->
getConstVal
(
)
,
Ty
,
N
->
getAlignment
(
)
,
N
->
getOffset
(
)
,
Flag
)
;
llvm_unreachable
(
"Unexpected node type."
)
;
return
SDValue
(
)
;
}
</s>

Retrieve the target node this edge connects to .


<s> static void rbt_left_rotate ( struct rbt_strings * t , struct rbt_string_node * node ) { struct rbt_string_node * right = node -> right ; assert ( right ) ; node -> right = right -> left ; if ( right -> left != t -> rbt_nil ) right -> left -> par = node ; right -> par = node -> par ; if ( node -> par == t -> rbt_nil ) t -> rbt_root = right ; else if ( node == node -> par -> left ) node -> par -> left = right ; else node -> par -> right = right ; right -> left = node ; node -> par = right ; } </s>

Perform a left-rotate operation on NODE in the red-black tree .


<s> bool mips_cfun_has_cprestore_slot_p ( void ) { return ( cfun -> machine -> global_pointer != INVALID_REGNUM && cfun -> machine -> frame . cprestore_size > 0 ) ; } </s>

Return true if the current function has a cprestore slot .


<s> unsigned MipsTargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? 32 : 64 ) ) , 1U ) ; return MipsTargetLowering :: getNumRegisters ( Context , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


Return an array that contains the direct target flag values and their names .

Mips Mips Mips "mips-got" "mips-got-call" "mips-gprel" "mips-abs-hi" "mips-abs-lo" "mips-tlsgd" "mips-tlsldm" "mips-dtprel-hi" "mips-dtprel-lo" "mips-gottprel" "mips-tprel-hi" "mips-tprel-lo" "mips-gpoff-hi" "mips-gpoff-lo" "mips-got-disp" "mips-got-page" "mips-got-ofst" "mips-higher" "mips-highest" "mips-got-hi16" "mips-got-lo16" "mips-call-hi16" "mips-call-lo16" "mips-jalr"


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool ARMBaseTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( getTargetLowering ( ) ) ) ; return false ; } </s>


<s> bool SparcTargetLowering :: IsEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF ) const { auto & Outs = CLI . Outs ; auto & Caller = MF . getFunction ( ) ; if ( Caller . getFnAttribute ( "disable-tail-calls" ) . getValueAsString ( ) == "true" ) return false ; if ( CCInfo . getNextStackOffset ( ) != 0 ) return false ; if ( ! Outs . empty ( ) && Caller . hasStructRetAttr ( ) != Outs [ 0 ] . Flags . isSRet ( ) ) return false ; for ( auto & Arg : Outs ) if ( Arg . Flags . isByVal ( ) ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

Sparc Sparc "disable-tail-calls" "true" 0 0


<s> bool AArch64TargetLowering :: isExtractSubvectorCheap ( EVT ResVT , EVT SrcVT , unsigned Index ) const { if ( ! isOperationLegalOrCustom ( ISD :: EXTRACT_SUBVECTOR , ResVT ) ) return false ; return ( Index == 0 || Index == ResVT . getVectorNumElements ( ) ) ; } </s>

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index .


<s> bool KudeyarPassConfig :: addInstSelector ( ) { addPass ( createKudeyarISelDag ( getKudeyarTargetMachine ( ) , getOptLevel ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> rtx assign_386_stack_local ( machine_mode mode , enum ix86_stack_slot n ) { struct stack_local_entry * s ; gcc_assert ( n < MAX_386_STACK_LOCALS ) ; for ( s = ix86_stack_locals ; s ; s = s -> next ) if ( s -> mode == mode && s -> n == n ) return validize_mem ( copy_rtx ( s -> rtl ) ) ; s = ggc_alloc < stack_local_entry > ( ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE ( mode ) , 0 ) ; s -> next = ix86_stack_locals ; ix86_stack_locals = s ; return validize_mem ( copy_rtx ( s -> rtl ) ) ; } </s>

Return a MEM corresponding to a stack slot with mode MODE . Allocate a new slot if necessary . The RTL for a function can have several slots available : N is which slot to use .


<s> int SystemZHazardRecognizer :: groupingCost ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return 0 ; if ( SC -> BeginGroup ) { if ( CurrGroupSize ) return 3 - CurrGroupSize ; return - 1 ; } if ( SC -> EndGroup ) { unsigned resultingGroupSize = ( CurrGroupSize + getNumDecoderSlots ( SU ) ) ; if ( resultingGroupSize < 3 ) return ( 3 - resultingGroupSize ) ; return - 1 ; } if ( CurrGroupSize == 2 && has4RegOps ( SU -> getInstr ( ) ) ) return 1 ; return 0 ; } </s>

Return the cost of decoder grouping for SU .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { return CSR_PCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static int ix86_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int ) { switch ( type_of_cost ) { case scalar_stmt : return ix86_cost -> scalar_stmt_cost ; case scalar_load : return ix86_cost -> scalar_load_cost ; case scalar_store : return ix86_cost -> scalar_store_cost ; case vector_stmt : return ix86_cost -> vec_stmt_cost ; case vector_load : return ix86_cost -> vec_align_load_cost ; case vector_store : return ix86_cost -> vec_store_cost ; case vec_to_scalar : return ix86_cost -> vec_to_scalar_cost ; case scalar_to_vec : return ix86_cost -> scalar_to_vec_cost ; case unaligned_load : case unaligned_store : return ix86_cost -> vec_unalign_load_cost ; case cond_branch_taken : return ix86_cost -> cond_taken_branch_cost ; case cond_branch_not_taken : return ix86_cost -> cond_not_taken_branch_cost ; case vec_perm : case vec_promote_demote : return ix86_cost -> vec_stmt_cost ; case vec_construct : return ix86_cost -> vec_stmt_cost * ( TYPE_VECTOR_SUBPARTS ( vectype ) - 1 ) ; default : gcc_unreachable ( ) ; } } </s>


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA15 ( ) && getARMSubtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
bool
ARM64AsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
assert
(
MO
.
isReg
(
)
&&
"unexpected inline asm memory operand"
)
;
O
<<
"["
<<
ARM64InstPrinter
::
getRegisterName
(
MO
.
getReg
(
)
)
<<
"]"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( getAvailableFeatures ( ) & X86 :: Mode64Bit ) != 0 ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool X86TargetLowering :: hasAndNotCompare ( SDValue Y ) const { if ( ! Subtarget . hasBMI ( ) ) return false ; EVT VT = Y . getValueType ( ) ; if ( VT != MVT :: i32 && VT != MVT :: i64 ) return false ; return true ; } </s>

Return true if the target should transform : ( X & Y ) == Y � ? ( ~X & Y ) == 0 ( X & Y ) ! = Y � ? ( ~X & Y ) ! = 0 .


"Offset type is not a multiple of bytes"


<s> bool X86TargetLowering :: needsFixedCatchObjects ( ) const { return Subtarget . isTargetWin64 ( ) ; } </s>


<s> static int ix86_fp_cmp_code_to_pcmp_immediate ( enum rtx_code code ) { switch ( code ) { case EQ : return 0x00 ; case NE : return 0x04 ; case GT : return 0x0e ; case LE : return 0x02 ; case GE : return 0x0d ; case LT : return 0x01 ; case UNLE : return 0x0a ; case UNLT : return 0x09 ; case UNGE : return 0x05 ; case UNGT : return 0x06 ; case UNEQ : return 0x18 ; case LTGT : return 0x0c ; case ORDERED : return 0x07 ; case UNORDERED : return 0x03 ; default : gcc_unreachable ( ) ; } } </s>

Helper for ix86_cmp_code_to_pcmp_immediate for fp modes .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static tree gen_stdcall_or_fastcall_decoration ( tree decl , char prefix ) { unsigned total = 0 ; const char * asmname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; char * newsym ; tree formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return NULL_TREE ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - 1 ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size ; formal_type = TREE_CHAIN ( formal_type ) ; } } newsym = alloca ( 1 + strlen ( asmname ) + 1 + 10 + 1 ) ; return get_identifier_with_length ( newsym , sprintf ( newsym , "%c%s@%u" , prefix , asmname , total / BITS_PER_UNIT ) ) ; } </s>

Return string which is the former assembler name modified with an underscore prefix and a suffix consisting of an atsign ( @ ) followed by the number of bytes of arguments


<s> void function_expander :: add_fixed_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + 1 , true ) ; create_fixed_operand ( & m_ops . last ( ) , x ) ; } </s>

Add an operand that must be X . The only way of legitimizing an invalid X is to reload the address of a MEM .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> bool SystemZTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( ! isInt < 20 > ( AM . BaseOffs ) ) return false ; bool RequireD12 = Subtarget . hasVector ( ) && Ty -> isVectorTy ( ) ; AddressingMode SupportedAM ( ! RequireD12 , true ) ; if ( I != nullptr ) SupportedAM = supportedAddressingMode ( I , Subtarget . hasVector ( ) ) ; if ( ! SupportedAM . LongDisplacement && ! isUInt < 12 > ( AM . BaseOffs ) ) return false ; if ( ! SupportedAM . IndexReg ) return AM . Scale == 0 ; else return AM . Scale == 0 || AM . Scale == 1 ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return SP :: I1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static void ultra_flush_pipeline ( ) { ultra_cur_hist = ( ultra_cur_hist + 1 ) & ( ULTRA_NUM_HIST - 1 ) ; ultra_cycles_elapsed += 1 ; memset ( ( char * ) & ultra_pipe , 0 , sizeof ultra_pipe ) ; ultra_pipe . free_slot_mask = 0xf ; } </s>


<s> static int get_vec_cmp_insn ( enum rtx_code code , enum machine_mode dest_mode , enum machine_mode op_mode ) { if ( ! TARGET_ALTIVEC ) return INSN_NOT_AVAILABLE ; switch ( code ) { case EQ : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPEQUB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPEQUH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPEQUW ; if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPEQFP ; break ; case GE : if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPGEFP ; case GT : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPGTSB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPGTSH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPGTSW ; if ( dest_mode == V4SImode && op_mode == V4SFmode ) return UNSPEC_VCMPGTFP ; break ; case GTU : if ( dest_mode == V16QImode && op_mode == V16QImode ) return UNSPEC_VCMPGTUB ; if ( dest_mode == V8HImode && op_mode == V8HImode ) return UNSPEC_VCMPGTUH ; if ( dest_mode == V4SImode && op_mode == V4SImode ) return UNSPEC_VCMPGTUW ; break ; default : break ; } return INSN_NOT_AVAILABLE ; } </s>

Return insn index for the vector compare instruction for given CODE , and DEST_MODE , OP_MODE . Return -1 if valid insn is not available .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .