<s> void nds32_construct_isr_vectors_information ( tree func_attrs , const char * func_name ) { tree save_all , partial_save ; tree nested , not_nested , nested_ready ; tree intr , excp , reset ; save_all = lookup_attribute ( "save_all" , func_attrs ) ; partial_save = lookup_attribute ( "partial_save" , func_attrs ) ; nested = lookup_attribute ( "nested" , func_attrs ) ; not_nested = lookup_attribute ( "not_nested" , func_attrs ) ; nested_ready = lookup_attribute ( "nested_ready" , func_attrs ) ; intr = lookup_attribute ( "interrupt" , func_attrs ) ; excp = lookup_attribute ( "exception" , func_attrs ) ; reset = lookup_attribute ( "reset" , func_attrs ) ; if ( ! intr && ! excp && ! reset ) return ; if ( intr || excp ) { tree id_list ; id_list = ( intr ) ? ( TREE_VALUE ( intr ) ) : ( TREE_VALUE ( excp ) ) ; while ( id_list ) { tree id ; int vector_id ; unsigned int vector_number_offset ; vector_number_offset = ( intr ) ? ( 9 ) : ( 0 ) ; id = TREE_VALUE ( id_list ) ; vector_id = TREE_INT_CST_LOW ( id ) + vector_number_offset ; nds32_isr_vectors [ vector_id ] . category = ( intr ) ? ( NDS32_ISR_INTERRUPT ) : ( NDS32_ISR_EXCEPTION ) ; strcpy ( nds32_isr_vectors [ vector_id ] . func_name , func_name ) ; if ( save_all ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_SAVE_ALL ; else if ( partial_save ) nds32_isr_vectors [ vector_id ] . save_reg = NDS32_PARTIAL_SAVE ; if ( nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED ; else if ( not_nested ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NOT_NESTED ; else if ( nested_ready ) nds32_isr_vectors [ vector_id ] . nested_type = NDS32_NESTED_READY ; id_list = TREE_CHAIN ( id_list ) ; } } else { tree id_list ; tree id ; tree nmi , warm ; nds32_isr_vectors [ 0 ] . category = NDS32_ISR_RESET ; id_list = TREE_VALUE ( reset ) ; id = TREE_VALUE ( id_list ) ; nds32_isr_vectors [ 0 ] . total_n_vectors = TREE_INT_CST_LOW ( id ) + 8 + 1 ; strcpy ( nds32_isr_vectors [ 0 ] . func_name , func_name ) ; nmi = lookup_attribute ( "nmi" , func_attrs ) ; warm = lookup_attribute ( "warm" , func_attrs ) ; if ( nmi != NULL_TREE ) { tree nmi_func_list ; tree nmi_func ; nmi_func_list = TREE_VALUE ( nmi ) ; nmi_func = TREE_VALUE ( nmi_func_list ) ; strcpy ( nds32_isr_vectors [ 0 ] . nmi_name , IDENTIFIER_POINTER ( nmi_func ) ) ; } if ( warm != NULL_TREE ) { tree warm_func_list ; tree warm_func ; warm_func_list = TREE_VALUE ( warm ) ; warm_func = TREE_VALUE ( warm_func_list ) ; strcpy ( nds32_isr_vectors [ 0 ] . warm_name , IDENTIFIER_POINTER ( warm_func ) ) ; } } } </s>

Function to construct isr vectors information array . We DO NOT HAVE TO check if the attributes are valid because those works are supposed to be done on nds32_merge_decl_attributes ( ) and nds32_insert_attributes ( ) .


<s> void CAHPInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void X86DAGToDAGISel :: PreprocessISelDAG ( ) { OptForSize = MF -> getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( ( N -> getOpcode ( ) == X86ISD :: CALL && ! Subtarget -> callRegIndirect ( ) ) || ( N -> getOpcode ( ) == X86ISD :: TC_RETURN && ( Subtarget -> is64Bit ( ) || getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == X86ISD :: CALL ; SDValue Chain = N -> getOperand ( 0 ) ; SDValue Load = N -> getOperand ( 1 ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , 0 ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != ISD :: FP_ROUND && N -> getOpcode ( ) != ISD :: FP_EXTEND ) continue ; EVT SrcVT = N -> getOperand ( 0 ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( 0 ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; X86TargetLowering * X86Lowering = ( X86TargetLowering * ) getTargetLowering ( ) ; bool SrcIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = X86Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == ISD :: FP_EXTEND ) continue ; if ( N -> getConstantOperandVal ( 1 ) ) continue ; } EVT MemVT ; if ( N -> getOpcode ( ) == ISD :: FP_ROUND ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( 0 ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; SDValue Result = CurDAG -> getExtLoad ( ISD :: EXTLOAD , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , 0 ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , 0 ) , Result ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } } </s>

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void recombine_lvx_stvx_patterns ( function * fun ) { int i ; basic_block bb ; rtx_insn * insn ; int num_insns = get_max_uid ( ) ; del_info * to_delete = XCNEWVEC ( del_info , num_insns ) ; FOR_ALL_BB_FN ( bb , fun ) FOR_BB_INSNS ( bb , insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( insn_is_load_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_lvx_pattern ( insn , to_delete ) ; else if ( insn_is_store_p ( insn ) && insn_is_swap_p ( insn ) ) recombine_stvx_pattern ( insn , to_delete ) ; } for ( i = 0 ; i < num_insns ; i ++ ) if ( to_delete [ i ] . replace ) { rtx swap_body = PATTERN ( to_delete [ i ] . replace_insn ) ; rtx src_reg = XEXP ( SET_SRC ( swap_body ) , 0 ) ; rtx copy = gen_rtx_SET ( SET_DEST ( swap_body ) , src_reg ) ; rtx_insn * new_insn = emit_insn_before ( copy , to_delete [ i ] . replace_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( to_delete [ i ] . replace_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( to_delete [ i ] . replace_insn ) ; remove_insn ( to_delete [ i ] . replace_insn ) ; to_delete [ i ] . replace_insn -> set_deleted ( ) ; } free ( to_delete ) ; } </s>

Look for patterns created from builtin lvx and stvx calls , and canonicalize them to be properly recognized as such .


<s> rtx loongarch_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl ; unsigned int fcode , avail ; const struct loongarch_builtin_description * d ; fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; gcc_assert ( fcode < ARRAY_SIZE ( loongarch_builtins ) ) ; d = & loongarch_builtins [ fcode ] ; avail = d -> avail ( ) ; gcc_assert ( avail != 0 ) ; switch ( d -> builtin_type ) { case LARCH_BUILTIN_DIRECT : return loongarch_expand_builtin_direct ( d -> icode , target , exp , true ) ; case LARCH_BUILTIN_DIRECT_NO_TARGET : return loongarch_expand_builtin_direct ( d -> icode , target , exp , false ) ; } gcc_unreachable ( ) ; } </s>


<s> static bool arm_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { bool ret = true ; struct gcc_options func_options ; tree cur_tree , new_optimize ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options ) ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; finalize_options_struct ( & func_options ) ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> unsigned char ix86_memtag_tag_size ( ) { return IX86_HWASAN_TAG_SIZE ; } </s>


<s> SDValue Cpu0TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Cpu0 Cpu0 ISD::BRCOND ISD::BlockAddress ISD::JumpTable ISD::GlobalAddress ISD::SELECT


"Didn't find MI in its own basic block?"

getOffsetOf - Return the current offset of the specified machine instruction from the start of the function .


<s> static MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; bool isPPC64 = TheTriple . getArch ( ) == Triple :: ppc64 ; if ( TheTriple . getOS ( ) == Triple :: Darwin ) return new PPCMCAsmInfoDarwin ( isPPC64 ) ; return new PPCLinuxMCAsmInfo ( isPPC64 ) ; } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s>
unsigned
PPCInstrInfo
::
lookThruCopyLike
(
unsigned
SrcReg
,
const
MachineRegisterInfo
*
MRI
)
{
while
(
true
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"Bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
CopySrcReg
)
)
return
CopySrcReg
;
SrcReg
=
CopySrcReg
;
}
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


This routine handles output of long unconditional branches that exceed the maximum range of a simple branch instruction . Since we do n't have a register available for the branch , we save register % r1 in the frame marker , load the branch destination DEST into % r1 , execute the branch , and restore % r1 in the delay slot of the branch . Since long branches may have an insn in the delay slot and the delay slot is used to restore % r1 , we in general need to extract this insn and execute it before the branch . However , to facilitate use of this function by conditional branches , we also provide an option to not extract the delay insn so that it will be emitted after the long branch . So , if there is an insn in the delay slot , it is extracted if XDELAY is nonzero . The lengths of the various long-branch sequences are 20 , 16 and 24 bytes for the portable runtime , non-PIC and PIC cases , respectively .


<s> static void function_arg_record_value_2 ( const_tree type , HOST_WIDE_INT startbitpos , struct function_arg_record_value_parms * parms , bool packed_p ) { tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != 0 ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( tree_fits_uhwi_p ( bit_position ( field ) ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_2 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { int this_slotno = parms -> slotno + bitpos / BITS_PER_WORD ; int regno , nregs , pos ; machine_mode mode = DECL_MODE ( field ) ; rtx reg ; function_arg_record_value_3 ( bitpos , parms ) ; if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; regno = SPARC_FP_ARG_FIRST + this_slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 && ( bitpos & 32 ) != 0 ) regno ++ ; reg = gen_rtx_REG ( mode , regno ) ; pos = bitpos / BITS_PER_UNIT ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; while ( -- nregs > 0 ) { regno += GET_MODE_SIZE ( mode ) / 4 ; reg = gen_rtx_REG ( mode , regno ) ; pos += GET_MODE_SIZE ( mode ) ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; } } else { if ( parms -> intoffset == - 1 ) parms -> intoffset = bitpos ; } } } } </s>

A subroutine of function_arg_record_value . Traverse the structure recursively and assign bits to floating point registers . Track which bits in between need integer registers ; invoke function_arg_record_value_3 to make that happen .


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) , StringRef SymName = StringRef ( ) , void * OpDecl = 0 ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; return Res ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void VEInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { unsigned AltIdx = VE :: AsmName ; if ( MRI . getRegClass ( VE :: MISCRegClassID ) . contains ( RegNo ) ) AltIdx = VE :: NoRegAltName ; OS << '%' << getRegisterName ( RegNo , AltIdx ) ; } </s>

VE VE VE::AsmName VE::MISCRegClassID VE::NoRegAltName


<s> void emitBytes ( StringRef Data ) override { emitDataMappingSymbol ( ) ; MCELFStreamer :: emitBytes ( Data ) ; } </s>

Emit the bytes in Data into the output .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static bool umips_build_save_restore ( mips_save_restore_fn fn , unsigned * mask , HOST_WIDE_INT * offset ) { int nregs ; unsigned int i , j ; rtx pattern , set , reg , mem ; HOST_WIDE_INT this_offset ; rtx this_base ; for ( i = 0 ; i < ARRAY_SIZE ( umips_swm_mask ) ; i ++ ) if ( ( * mask & 0xffff0000 ) == umips_swm_mask [ i ] ) break ; if ( i == ARRAY_SIZE ( umips_swm_mask ) ) return false ; nregs = ( umips_swm_encoding [ i ] & 0xf ) + ( umips_swm_encoding [ i ] >> 4 ) ; this_offset = * offset - UNITS_PER_WORD * ( nregs - 1 ) ; if ( ! UMIPS_12BIT_OFFSET_P ( this_offset ) ) return false ; pattern = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs ) ) ; this_base = stack_pointer_rtx ; for ( j = 0 ; j < ( umips_swm_encoding [ i ] & 0xf ) ; j ++ ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; unsigned int regno = ( j != 8 ) ? 16 + j : 30 ; * mask &= ~ ( 1 << regno ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( VOIDmode , reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } if ( umips_swm_encoding [ i ] >> 4 ) { HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD ; * mask &= ~ ( 1 << 31 ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , this_base , offset ) ) ; reg = gen_rtx_REG ( SImode , 31 ) ; if ( fn == mips_save_reg ) set = mips_frame_set ( mem , reg ) ; else { set = gen_rtx_SET ( VOIDmode , reg , mem ) ; mips_add_cfa_restore ( reg ) ; } XVECEXP ( pattern , 0 , j ) = set ; } pattern = emit_insn ( pattern ) ; if ( fn == mips_save_reg ) RTX_FRAME_RELATED_P ( pattern ) = 1 ; * offset -= UNITS_PER_WORD * nregs ; return true ; } </s>

Try to use a microMIPS LWM or SWM instruction to save or restore as many GPRs in * MASK as possible . * OFFSET is the offset from the stack pointer of the topmost save slot . Remove from * MASK all registers that were handled using LWM and SWM . Update * OFFSET so that it points to the first unused save slot .


<s>
MachineBasicBlock
*
SparcTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
,
DenseMap
<
MachineBasicBlock
*
,
MachineBasicBlock
*
>
*
EM
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
unsigned
BROpcode
;
unsigned
CC
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown SELECT_CC!"
)
;
case
SP
::
SELECT_CC_Int_ICC
:
case
SP
::
SELECT_CC_FP_ICC
:
case
SP
::
SELECT_CC_DFP_ICC
:
BROpcode
=
SP
::
BCOND
;
break
;
case
SP
::
SELECT_CC_Int_FCC
:
case
SP
::
SELECT_CC_FP_FCC
:
case
SP
::
SELECT_CC_DFP_FCC
:
BROpcode
=
SP
::
FBCOND
;
break
;
}
CC
=
(
SPCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
BROpcode
)
)
.
addMBB
(
sinkMBB
)
.
addImm
(
CC
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
I
=
BB
->
succ_begin
(
)
,
E
=
BB
->
succ_end
(
)
;
I
!=
E
;
++
I
)
{
EM
->
insert
(
std
::
make_pair
(
*
I
,
sinkMBB
)
)
;
sinkMBB
->
addSuccessor
(
*
I
)
;
}
while
(
!
BB
->
succ_empty
(
)
)
BB
->
removeSuccessor
(
BB
->
succ_begin
(
)
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SP
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> unsigned OpenRISCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? OpenRISC :: FP : OpenRISC :: SP ; } </s>

OpenRISC OpenRISC OpenRISC::FP OpenRISC::SP


<s>
SDValue
MipsTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
,
TargetLowering
::
CallLoweringInfo
&
CLI
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MipsCCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Mips
,
CLI
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
RVLocs
[
i
]
.
getLocReg
(
)
,
RVLocs
[
i
]
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
if
(
VA
.
isUpperBitsInLoc
(
)
)
{
unsigned
ValSizeInBits
=
Ins
[
i
]
.
ArgVT
.
getSizeInBits
(
)
;
unsigned
LocSizeInBits
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
unsigned
Shift
=
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExtUpper
ISD
::
SRL
:
ISD
::
SRA
;
Val
=
DAG
.
getNode
(
Shift
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getConstant
(
LocSizeInBits
ValSizeInBits
,
VA
.
getLocVT
(
)
)
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
case
CCValAssign
::
AExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
case
CCValAssign
::
ZExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
case
CCValAssign
::
SExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

Mips
Mips
ISD::InputArg
16
Mips
Mips
0
"Can only return in registers!"
1
2
ISD::SRL
ISD::SRA
"Unknown loc info!"
ISD::BITCAST
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Mips :: ZERO ) ; Reserved . set ( Mips :: AT ) ; Reserved . set ( Mips :: K0 ) ; Reserved . set ( Mips :: K1 ) ; Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: SP ) ; Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: RA ) ; if ( ! Subtarget . isSingleFloat ( ) ) for ( unsigned FReg = ( Mips :: F0 ) + 1 ; FReg < Mips :: F30 ; FReg += 2 ) Reserved . set ( FReg ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool runOnMachineFunction ( MachineFunction & F ) { if ( SkipDelaySlotFiller ) return false ; bool Changed = false ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> TargetPassConfig * Comet2TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new Comet2PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> Register CSKYTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { return CSKY :: R1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> bool Thumb1FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( ARM :: tPUSH ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; bool isKill = true ; if ( Reg == ARM :: LR ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) . isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; } MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> virtual const MCObjectFormat & getObjectFormat ( ) const { return Format ; } </s>


<s> static unsigned HOST_WIDE_INT compute_current_alignment ( unsigned HOST_WIDE_INT base_align , unsigned HOST_WIDE_INT offset ) { if ( offset == 0 ) return base_align ; return min ( base_align , offset & - offset ) ; } </s>

Compute the alignment of pointer+OFFSET where the original alignment of pointer was BASE_ALIGN .


<s>
Value
*
PPCTargetLowering
::
emitMaskedAtomicRMWIntrinsic
(
IRBuilderBase
&
Builder
,
AtomicRMWInst
*
AI
,
Value
*
AlignedAddr
,
Value
*
Incr
,
Value
*
Mask
,
Value
*
ShiftAmt
,
AtomicOrdering
Ord
)
const
{
assert
(
EnableQuadwordAtomics
&&
Subtarget
.
hasQuadwordAtomics
(
)
&&
"Only support quadword now"
)
;
Module
*
M
=
Builder
.
GetInsertBlock
(
)
->
getParent
(
)
->
getParent
(
)
;
Type
*
ValTy
=
Incr
->
getType
(
)
;
assert
(
ValTy
->
getPrimitiveSizeInBits
(
)
==
128
)
;
Function
*
RMW
=
Intrinsic
::
getDeclaration
(
M
,
getIntrinsicForAtomicRMWBinOp128
(
AI
->
getOperation
(
)
)
)
;
Type
*
Int64Ty
=
Type
::
getInt64Ty
(
M
->
getContext
(
)
)
;
Value
*
IncrLo
=
Builder
.
CreateTrunc
(
Incr
,
Int64Ty
,
"incr_lo"
)
;
Value
*
IncrHi
=
Builder
.
CreateTrunc
(
Builder
.
CreateLShr
(
Incr
,
64
)
,
Int64Ty
,
"incr_hi"
)
;
Value
*
Addr
=
Builder
.
CreateBitCast
(
AlignedAddr
,
Type
::
getInt8PtrTy
(
M
->
getContext
(
)
)
)
;
Value
*
LoHi
=
Builder
.
CreateCall
(
RMW
,
{
Addr
,
IncrLo
,
IncrHi
}
)
;
Value
*
Lo
=
Builder
.
CreateExtractValue
(
LoHi
,
0
,
"lo"
)
;
Value
*
Hi
=
Builder
.
CreateExtractValue
(
LoHi
,
1
,
"hi"
)
;
Lo
=
Builder
.
CreateZExt
(
Lo
,
ValTy
,
"lo64"
)
;
Hi
=
Builder
.
CreateZExt
(
Hi
,
ValTy
,
"hi64"
)
;
return
Builder
.
CreateOr
(
Lo
,
Builder
.
CreateShl
(
Hi
,
ConstantInt
::
get
(
ValTy
,
64
)
)
,
"val64"
)
;
}
</s>

Perform a masked atomicrmw using a target-specific intrinsic .


"sh_find_extending_set_of_reg: reg %d is "

"explicitly sign/zero extended in insn %d\n"

Given a reg and the current insn , see if the value of the reg originated from a sign or zero extension and return the discovered information .


<s> bool ia64_expand_vecint_minmax ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx xops [ 6 ] ; if ( mode == V8QImode && ( code == UMIN || code == UMAX ) ) return false ; if ( mode == V4HImode && ( code == SMIN || code == SMAX ) ) return false ; if ( mode == V4HImode && code == UMAX ) { rtx x , tmp = gen_reg_rtx ( mode ) ; x = gen_rtx_US_MINUS ( mode , operands [ 1 ] , operands [ 2 ] ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , x ) ) ; emit_insn ( gen_addv4hi3 ( operands [ 0 ] , tmp , operands [ 2 ] ) ) ; return true ; } xops [ 0 ] = operands [ 0 ] ; xops [ 4 ] = xops [ 1 ] = operands [ 1 ] ; xops [ 5 ] = xops [ 2 ] = operands [ 2 ] ; switch ( code ) { case UMIN : code = LTU ; break ; case UMAX : code = GTU ; break ; case SMIN : code = LT ; break ; case SMAX : code = GT ; break ; default : gcc_unreachable ( ) ; } xops [ 3 ] = gen_rtx_fmt_ee ( code , VOIDmode , operands [ 1 ] , operands [ 2 ] ) ; ia64_expand_vecint_cmov ( xops ) ; return true ; } </s>

Emit an integral vector min or max operation . Return true if all done .


"constant halfword load operand out of range"

Detect and error out on out-of-range constants for movhi .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; Register FIReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildFrameIndex ( FIReg , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg ; } Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( AArch64 :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildPtrAdd ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static int ix86_function_regparm ( tree type , tree decl ) { tree attr ; int regparm = ix86_regparm ; bool user_convention = false ; if ( ! TARGET_64BIT ) { attr = lookup_attribute ( "regparm" , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; user_convention = true ; } if ( lookup_attribute ( "fastcall" , TYPE_ATTRIBUTES ( type ) ) ) { regparm = 2 ; user_convention = true ; } if ( ! TARGET_64BIT && ! user_convention && decl && flag_unit_at_a_time && ! profile_flag ) { struct cgraph_local_info * i = cgraph_local_info ( decl ) ; if ( i && i -> local ) { int local_regparm , globals = 0 , regno ; for ( local_regparm = 0 ; local_regparm < 3 ; local_regparm ++ ) if ( global_regs [ local_regparm ] ) break ; if ( local_regparm == 3 && decl_function_context ( decl ) && ! DECL_NO_STATIC_CHAIN ( decl ) ) local_regparm = 2 ; for ( regno = 0 ; regno < 6 ; regno ++ ) if ( global_regs [ regno ] ) globals ++ ; local_regparm = globals < local_regparm ? local_regparm - globals : 0 ; if ( local_regparm > regparm ) regparm = local_regparm ; } } } return regparm ; } </s>

Return the regparm value for a function with the indicated TYPE and DECL . DECL may be NULL when calling function indirectly or considering a libcall .


<s> static bool mips_return_in_msb ( tree valtype ) { tree fields [ 2 ] ; return ( TARGET_NEWABI && TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && mips_fpr_return_fields ( valtype , fields ) == 0 ) ; } </s>

Implement TARGET_RETURN_IN_MSB . For n32 & n64 , we should return a value in the most significant part of $ 2/ $ 3 if : - the target is big-endian ; - the value has a structure or union type ( we generalize this to cover aggregates from other languages too ) ; and - the structure is not returned in floating-point registers .


<s> unsigned getNumberOfRegisters ( bool Vector ) { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 16 ; if ( ST -> hasMVEIntegerOps ( ) ) return 8 ; return 0 ; } if ( ST -> isThumb1Only ( ) ) return 8 ; return 13 ; } </s>


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void expand_fusion_p9_store ( rtx * operands ) { rtx tmp_reg = operands [ 0 ] ; rtx addis_value = operands [ 1 ] ; rtx orig_mem = operands [ 2 ] ; rtx src = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset , set , clobber , insn , new_src ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( orig_mem ) ; machine_mode ptr_mode = Pmode ; gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; new_src = gen_rtx_UNSPEC ( target_mode , gen_rtvec ( 1 , src ) , UNSPEC_FUSION_P9 ) ; set = gen_rtx_SET ( new_mem , new_src ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , tmp_reg ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ; emit_insn ( insn ) ; return ; } </s>

During the peephole2 pass , adjust and expand the insns for an extended fusion store sequence . The operands are : operands [ 0 ] register set with addis operands [ 1 ] value set via addis operands [ 2 ] target D-form memory being stored to operands [ 3 ] register being stored This is similar to the fusion introduced with power8 , except it scales to both loads/stores and does not require the result register to be the same as the base register . At the moment , we only do this if register set with addis is dead .


<s> Cpu0ExprKind getKind ( ) const { return Kind ; } </s>


<s> int arm_coproc_mem_operand ( rtx op , bool wb ) { return arm_coproc_mem_operand_wb ( op , wb ? 2 : 1 ) ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern . WB if true if writeback address modes are allowed .


<s> static void mips_save_reg ( rtx reg , rtx mem ) { if ( GET_MODE ( reg ) == DFmode && ( ! TARGET_FLOAT64 || mips_abi == ABI_32 ) ) { rtx x1 , x2 ; mips_emit_move_or_split ( mem , reg , SPLIT_IF_NECESSARY ) ; x1 = mips_frame_set ( mips_subword ( mem , false ) , mips_subword ( reg , false ) ) ; x2 = mips_frame_set ( mips_subword ( mem , true ) , mips_subword ( reg , true ) ) ; mips_set_frame_expr ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x1 , x2 ) ) ) ; } else mips_emit_save_slot_move ( mem , reg , MIPS_PROLOGUE_TEMP ( GET_MODE ( reg ) ) ) ; } </s>

Save register REG to MEM . Make the instruction frame-related .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


"ARM64 Collect Linker Optimization Hint (LOH)"

getPassName - Return a nice clean name for a pass .


<s> BitVector Comet2RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , Comet2 :: FR ) ; markSuperRegs ( Reserved , Comet2 :: SP ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const X86Subtarget & Subtarget = MF . getSubtarget < X86Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; switch ( CC ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_RegMask ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; return CSR_64_AllRegs_RegMask ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_RegMask ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_RegMask ; return CSR_64_RT_AllRegs_RegMask ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return CSR_64_TLS_Darwin_RegMask ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_RegMask ; case CallingConv :: X86_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_RegMask : CSR_Win64_RegCall_NoSSE_RegMask ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_RegMask : CSR_SysV64_RegCall_NoSSE_RegMask ) ; } } else { return ( HasSSE ? CSR_32_RegCall_RegMask : CSR_32_RegCall_NoSSE_RegMask ) ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_RegMask ; break ; case CallingConv :: Win64 : return CSR_Win64_RegMask ; case CallingConv :: X86_64_SysV : return CSR_64_RegMask ; case CallingConv :: X86_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_64_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_64_AllRegs_RegMask ; return CSR_64_AllRegs_NoSSE_RegMask ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_RegMask ; if ( HasAVX ) return CSR_32_AllRegs_AVX_RegMask ; if ( HasSSE ) return CSR_32_AllRegs_SSE_RegMask ; return CSR_32_AllRegs_RegMask ; } default : break ; } if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; bool IsSwiftCC = Subtarget . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ; if ( IsSwiftCC ) return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask ; return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask ; } return CSR_32_RegMask ; } </s>


<s>
void
dump
(
const
llvm
::
SelectionDAG
*
DAG
)
{
errs
(
)
<<
"SystemZAddressingMode "
<<
this
<<
'\n'
;
errs
(
)
<<
" Base "
;
if
(
Base
.
getNode
(
)
)
Base
.
getNode
(
)
->
dump
(
DAG
)
;
else
errs
(
)
<<
"null\n"
;
if
(
hasIndexField
(
)
)
{
errs
(
)
<<
" Index "
;
if
(
Index
.
getNode
(
)
)
Index
.
getNode
(
)
->
dump
(
DAG
)
;
else
errs
(
)
<<
"null\n"
;
}
errs
(
)
<<
" Disp "
<<
Disp
;
if
(
IncludesDynAlloc
)
errs
(
)
<<
" + ADJDYNALLOC"
;
errs
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

SystemZ
"SystemZAddressingMode "
" Base "
"null\n"
" Index "
"null\n"
" Disp "
" + ADJDYNALLOC"


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
Suffix
=
"$stub"
;
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> static bool aarch64_evpc_ins ( struct expand_vec_perm_d * d ) { machine_mode mode = d -> vmode ; unsigned HOST_WIDE_INT nelt ; if ( d -> vec_flags != VEC_ADVSIMD ) return false ; nelt = d -> perm . length ( ) . to_constant ( ) ; rtx insv = d -> op0 ; HOST_WIDE_INT idx = - 1 ; for ( unsigned HOST_WIDE_INT i = 0 ; i < nelt ; i ++ ) { HOST_WIDE_INT elt ; if ( ! d -> perm [ i ] . is_constant ( & elt ) ) return false ; if ( elt == ( HOST_WIDE_INT ) i ) continue ; if ( idx != - 1 ) { idx = - 1 ; break ; } idx = i ; } if ( idx == - 1 ) { insv = d -> op1 ; for ( unsigned HOST_WIDE_INT i = 0 ; i < nelt ; i ++ ) { if ( d -> perm [ i ] . to_constant ( ) == ( HOST_WIDE_INT ) ( i + nelt ) ) continue ; if ( idx != - 1 ) return false ; idx = i ; } if ( idx == - 1 ) return false ; } if ( d -> testing_p ) return true ; gcc_assert ( idx != - 1 ) ; unsigned extractindex = d -> perm [ idx ] . to_constant ( ) ; rtx extractv = d -> op0 ; if ( extractindex >= nelt ) { extractv = d -> op1 ; extractindex -= nelt ; } gcc_assert ( extractindex < nelt ) ; emit_move_insn ( d -> target , insv ) ; insn_code icode = code_for_aarch64_simd_vec_copy_lane ( mode ) ; expand_operand ops [ 5 ] ; create_output_operand ( & ops [ 0 ] , d -> target , mode ) ; create_input_operand ( & ops [ 1 ] , d -> target , mode ) ; create_integer_operand ( & ops [ 2 ] , 1 << idx ) ; create_input_operand ( & ops [ 3 ] , extractv , mode ) ; create_integer_operand ( & ops [ 4 ] , extractindex ) ; expand_insn ( icode , 5 , ops ) ; return true ; } </s>

Recognize patterns suitable for the INS instructions .


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
TRI
=
ST
.
getRegisterInfo
(
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
ML
->
isOutermost
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> void flushPendingInstructions ( MCStreamer & Out ) override { if ( ! inImplicitITBlock ( ) ) { assert ( PendingConditionalInsts . size ( ) == 0 ) ; return ; } unsigned Mask = getITMaskEncoding ( ) ; MCInst ITInst ; ITInst . setOpcode ( ARM :: t2IT ) ; ITInst . addOperand ( MCOperand :: createImm ( ITState . Cond ) ) ; ITInst . addOperand ( MCOperand :: createImm ( Mask ) ) ; Out . EmitInstruction ( ITInst , getSTI ( ) ) ; assert ( PendingConditionalInsts . size ( ) <= 4 ) ; for ( MCInst Inst : PendingConditionalInsts ) { Out . EmitInstruction ( Inst , getSTI ( ) ) ; } PendingConditionalInsts . clear ( ) ; ITState . Mask = 0 ; ITState . CurPosition = ~ 0U ; } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> void clear ( ) { BBInfo . clear ( ) ; } </s>


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( const GlobalValue * Val ) { std :: unique_ptr < const MipsCallEntry > & E = GlobalCallEntries [ Val ] ; if ( ! E ) E = llvm :: make_unique < MipsCallEntry > ( Val ) ; return MachinePointerInfo ( E . get ( ) ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s>
bool
AArch64InstrInfo
::
isCandidateToMergeOrPair
(
MachineInstr
&
MI
)
const
{
if
(
MI
.
hasOrderedMemoryRef
(
)
)
return
false
;
assert
(
MI
.
getOperand
(
1
)
.
isReg
(
)
&&
"Expected a reg operand."
)
;
if
(
!
MI
.
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
unsigned
BaseReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
if
(
MI
.
modifiesRegister
(
BaseReg
,
TRI
)
)
return
false
;
if
(
isLdStPairSuppressed
(
MI
)
)
return
false
;
if
(
Subtarget
.
isPaired128Slow
(
)
)
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDURQi
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDRQui
:
case
AArch64
::
STRQui
:
return
false
;
}
}
return
true
;
}
</s>

Return true if this is a load/store that can be potentially paired/merged .


"Assembler does not support -mabi=ilp32"


<s> static machine_mode sparc_preferred_simd_mode ( machine_mode mode ) { if ( TARGET_VIS ) switch ( mode ) { case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : ; } return word_mode ; } </s>

Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook .


<s> static bool compute_int_layout ( HOST_WIDE_INT bitpos , assign_data_t * data , int * pnregs ) { if ( data -> intoffset < 0 ) return false ; const int intoffset = data -> intoffset ; data -> intoffset = - 1 ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; const unsigned int startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; const unsigned int endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; int nregs = ( endbit - startbit ) / BITS_PER_WORD ; if ( nregs > 0 && nregs > SPARC_INT_ARG_MAX - this_slotno ) { nregs = SPARC_INT_ARG_MAX - this_slotno ; data -> stack = 1 ; } if ( nregs <= 0 ) return false ; * pnregs = nregs ; return true ; } </s>

A subroutine of function_arg_record_value . Compute the number of integer registers to be assigned between PARMS- > intoffset and BITPOS . Return true if at least one integer register is assigned or false otherwise .


<s>
unsigned
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .

ARM
ARM
"sp"
ARM::SP
0
"Invalid register name global variable"


<s> static bool rs6000_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , 0 ) , 0 ) ) != 0 ) return true ; return TARGET_ELF && tls_referenced_p ( x ) ; } </s>


<s> void function_builder :: add_overloaded_function ( const function_instance & instance , uint64_t required_extensions ) { char * name = get_name ( instance , true ) ; if ( registered_function * * map_value = m_overload_names . get ( name ) ) gcc_assert ( ( * map_value ) -> instance == instance && ( ( * map_value ) -> required_extensions & ~ required_extensions ) == 0 ) ; else { registered_function & rfn = add_function ( instance , name , m_overload_type , NULL_TREE , required_extensions , true ) ; const char * permanent_name = IDENTIFIER_POINTER ( DECL_NAME ( rfn . decl ) ) ; m_overload_names . put ( permanent_name , & rfn ) ; } obstack_free ( & m_string_obstack , name ) ; } </s>

Add one function decl for INSTANCE , to be used with manual overload resolution . REQUIRED_EXTENSIONS are the set of architecture extensions that the function requires . For simplicity , deal with duplicate attempts to add the same function , including cases in which the new function requires more features than the original one did . In that case we 'll check whether the required features are available as part of resolving the function to the relevant unique function .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static tree ix86_vectorize_builtin_scatter ( const_tree vectype , const_tree index_type , int scale ) { bool si ; enum ix86_builtins code ; if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= 0 || scale > 8 || ( scale & ( scale - 1 ) ) != 0 ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; default : return NULL_TREE ; } return ix86_builtins [ code ] ; } </s>

Returns a decl of a function that implements scatter store with register type VECTYPE and index type INDEX_TYPE and SCALE . Return NULL_TREE if it is not available .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ; poly_int64 offset ; addr = strip_offset_and_salt ( addr , & offset ) ; if ( SYMBOL_REF_P ( addr ) ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s>
bool
X86AsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
if
(
Subtarget
->
isTargetCOFF
(
)
)
{
const
Function
*
F
=
MF
.
getFunction
(
)
;
O
<<
"\t.def\t "
<<
*
CurrentFnSym
<<
";\t.scl\t"
<<
(
F
->
hasInternalLinkage
(
)
COFF
::
C_STAT
:
COFF
::
C_EXT
)
<<
";\t.type\t"
<<
(
COFF
::
DT_FCN
<<
COFF
::
N_BTSHFT
)
<<
";\t.endef\n"
;
}
EmitFunctionHeader
(
)
;
EmitFunctionBody
(
)
;
return
false
;
}
</s>


<s> unsigned AArch64TTIImpl :: getIntImmCost ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; switch ( IID ) { default : return TTI :: TCC_Free ; case Intrinsic :: sadd_with_overflow : case Intrinsic :: uadd_with_overflow : case Intrinsic :: ssub_with_overflow : case Intrinsic :: usub_with_overflow : case Intrinsic :: smul_with_overflow : case Intrinsic :: umul_with_overflow : if ( Idx == 1 ) { unsigned NumConstants = ( BitSize + 63 ) / 64 ; unsigned Cost = AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < unsigned > ( TTI :: TCC_Free ) : Cost ; } break ; case Intrinsic :: experimental_stackmap : if ( ( Idx < 2 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; case Intrinsic :: experimental_patchpoint_void : case Intrinsic :: experimental_patchpoint_i64 : if ( ( Idx < 4 ) || ( Imm . getBitWidth ( ) <= 64 && isInt < 64 > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ; break ; } return AArch64TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> unsigned X86TargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { if ( Subtarget . is64Bit ( ) ) { Align TyAlign = DL . getABITypeAlign ( Ty ) ; if ( TyAlign > 8 ) return TyAlign . value ( ) ; return 8 ; } Align Alignment ( 4 ) ; if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty , Alignment ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Encode Literals"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void build_mask64_2_operands ( rtx in , rtx * out ) { unsigned HOST_WIDE_INT c , lsb , m1 , m2 ; int shift ; gcc_assert ( GET_CODE ( in ) == CONST_INT ) ; c = INTVAL ( in ) ; if ( c & 1 ) { c = ~ c ; lsb = c & - c ; m1 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 <<= 64 - shift ; m1 = ~ m1 ; m2 = ~ c ; } else { lsb = c & - c ; m2 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = 0 ; while ( ( lsb >>= 1 ) != 0 ) shift ++ ; m1 = ~ c ; m1 >>= shift ; m1 = ~ m1 ; } out [ 0 ] = GEN_INT ( 64 - shift ) ; out [ 1 ] = GEN_INT ( m1 ) ; out [ 2 ] = GEN_INT ( shift ) ; out [ 3 ] = GEN_INT ( m2 ) ; ( void ) in ; ( void ) out ; gcc_unreachable ( ) ; } </s>

Generates shifts and masks for a pair of rldicl or rldicr insns to implement ANDing by the mask IN .


<s> bool X86RegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Reg == FramePtr && hasFP ( MF ) ) { FrameIdx = MF . getFrameInfo ( ) -> getObjectIndexBegin ( ) ; return true ; } return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s> bool X86TTIImpl :: isLegalMaskedStore ( Type * DataType , MaybeAlign Alignment ) { return isLegalMaskedLoad ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


<s>
SDNode
*
DCPU16DAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
DebugLoc
dl
=
Node
->
getDebugLoc
(
)
;
DEBUG
(
errs
(
)
<<
"Selecting: "
)
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
return
;
}
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
assert
(
Node
->
getValueType
(
0
)
==
MVT
::
i16
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i16
)
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
DCPU16
::
ADD16ri
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
return
CurDAG
->
getMachineNode
(
DCPU16
::
ADD16ri
,
dl
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Node
)
;
DEBUG
(
errs
(
)
<<
"=> "
)
;
if
(
ResNode
==
||
ResNode
==
Node
)
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DEBUG
(
errs
(
)
<<
"\n"
)
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static void iq2000_annotate_frame_insn ( rtx insn , rtx dwarf_pattern ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf_pattern , REG_NOTES ( insn ) ) ; } </s>

Make INSN frame related and note that it performs the frame-related operation DWARF_PATTERN .


<s> MCSymbol * LanaiMCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const { return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; } </s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> bool X86InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern :: MC_PATTERN > & Patterns ) const { if ( ! Root . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ) return false ; bool Commute ; if ( isReassocCandidate ( Root , Commute ) ) { if ( Commute ) { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_YB ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_YB ) ; } else { Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_AX_BY ) ; Patterns . push_back ( MachineCombinerPattern :: MC_REASSOC_XA_BY ) ; } return true ; } return false ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> const LanaiRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static opt_scalar_float_mode rs6000_floatn_mode ( int n , bool extended ) { if ( extended ) { switch ( n ) { case 32 : return DFmode ; case 64 : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return opt_scalar_float_mode ( ) ; case 128 : return opt_scalar_float_mode ( ) ; default : gcc_unreachable ( ) ; } } else { switch ( n ) { case 32 : return SFmode ; case 64 : return DFmode ; case 128 : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return opt_scalar_float_mode ( ) ; default : return opt_scalar_float_mode ( ) ; } } } </s>


<s> int sh_loop_align ( rtx_insn * label ) { rtx_insn * next = label ; if ( ! optimize || optimize_size ) return 0 ; do next = next_nonnote_insn ( next ) ; while ( next && LABEL_P ( next ) ) ; if ( ! next || ! INSN_P ( next ) || recog_memoized ( next ) == CODE_FOR_consttable_2 ) return 0 ; return align_loops . levels [ 0 ] . log ; } </s>

If we are inside a phony loop , almost any kind of label can turn up as the first one in the loop . Aligning a braf label causes incorrect switch destination addresses ; we can detect braf labels because they are followed by a BARRIER . Applying loop alignment to small constant or switch tables is a waste of space , so we suppress this too .


<s> WidenVector ( SelectionDAG & DAG ) : DAG ( DAG ) { } </s>

Widen the vector up to the next power of two using INSERT_SUBVECTOR .


<s> void ARMBaseInstrInfo :: mergeOutliningCandidateAttributes ( Function & F , std :: vector < outliner :: Candidate > & Candidates ) const { outliner :: Candidate & C = Candidates . front ( ) ; const Function & CFn = C . getMF ( ) -> getFunction ( ) ; if ( CFn . hasFnAttribute ( "branch-target-enforcement" ) ) F . addFnAttr ( CFn . getFnAttribute ( "branch-target-enforcement" ) ) ; ARMGenInstrInfo :: mergeOutliningCandidateAttributes ( F , Candidates ) ; } </s>

Optional target hook to create the LLVM IR attributes for the outlined function .

ARM ARM "branch-target-enforcement" "branch-target-enforcement" ARM


<s> unsigned ARM64InstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case ARM64 :: LDRWui : case ARM64 :: LDRXui : case ARM64 :: LDRBui : case ARM64 :: LDRHui : case ARM64 :: LDRSui : case ARM64 :: LDRDui : case ARM64 :: LDRQui : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAArch64WinCOFFObjectWriter ( OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const void * Decoder ) { const MCDisassembler * Dis = static_cast < const MCDisassembler * > ( Decoder ) ; return Dis -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool PPCTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_lvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_lvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_lvewx : VT = MVT :: i32 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = 1 ; Info . vol = false ; Info . readMem = true ; Info . writeMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : { EVT VT ; switch ( Intrinsic ) { case Intrinsic :: ppc_altivec_stvebx : VT = MVT :: i8 ; break ; case Intrinsic :: ppc_altivec_stvehx : VT = MVT :: i16 ; break ; case Intrinsic :: ppc_altivec_stvewx : VT = MVT :: i32 ; break ; default : VT = MVT :: v4i32 ; break ; } Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . offset = - VT . getStoreSize ( ) + 1 ; Info . size = 2 * VT . getStoreSize ( ) - 1 ; Info . align = 1 ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer . EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer . EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

ARM ARM ARM ARM 1 0 ARM::tBX ARMCC::AL 0


<s> void Cpu0SEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = Cpu0 :: ADDu ; unsigned ADDiu = Cpu0 :: ADDiu ; if ( isInt < 16 > ( Amount ) ) { BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; } else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> static void bounds_check ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high , const char * err ) { HOST_WIDE_INT lane ; gcc_assert ( CONST_INT_P ( operand ) ) ; lane = INTVAL ( operand ) ; if ( lane < low || lane >= high ) error ( err ) ; } </s>

Ensure OPERAND lies between LOW ( inclusive ) and HIGH ( exclusive ) . Raise ERR if it does n't . FIXME : NEON bounds checks occur late in compilation , so reported source locations are bogus .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle , bool MinSize ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , OptMinSize ( MinSize ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new ARMCallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new ARMLegalizerInfo ( * this ) ) ; auto * RBI = new ARMRegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createARMInstructionSelector ( * static_cast < const ARMBaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s> unsigned PPCRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const unsigned DefaultSafety = 1 ; switch ( RC -> getID ( ) ) { default : return 0 ; case PPC :: G8RC_NOX0RegClassID : case PPC :: GPRC_NOR0RegClassID : case PPC :: G8RCRegClassID : case PPC :: GPRCRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 32 - FP - DefaultSafety ; } case PPC :: F8RCRegClassID : case PPC :: F4RCRegClassID : case PPC :: VRRCRegClassID : case PPC :: VFRCRegClassID : case PPC :: VSLRCRegClassID : case PPC :: VSHRCRegClassID : return 32 - DefaultSafety ; case PPC :: VSRCRegClassID : case PPC :: VSFRCRegClassID : return 64 - DefaultSafety ; case PPC :: CRRCRegClassID : return 8 - DefaultSafety ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> static rtx_insn * arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; offset_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , orig , offset_rtx ) , UNSPEC_SYMBOL_OFFSET ) ; offset_rtx = gen_rtx_CONST ( Pmode , offset_rtx ) ; return emit_insn ( gen_pic_load_addr_unified ( reg , offset_rtx , labelno ) ) ; } </s>

Generate code to load the address of a static var when flag_pic is set .


<s> void ix86_expand_copysign ( rtx operands [ ] ) { machine_mode mode , vmode ; rtx dest , vdest , op0 , op1 , mask , op2 , op3 ; mode = GET_MODE ( operands [ 0 ] ) ; if ( mode == HFmode ) vmode = V8HFmode ; else if ( mode == SFmode ) vmode = V4SFmode ; else if ( mode == DFmode ) vmode = V2DFmode ; else if ( mode == TFmode ) vmode = mode ; else gcc_unreachable ( ) ; if ( rtx_equal_p ( operands [ 1 ] , operands [ 2 ] ) ) { emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; return ; } dest = operands [ 0 ] ; vdest = lowpart_subreg ( vmode , dest , mode ) ; if ( vdest == NULL_RTX ) vdest = gen_reg_rtx ( vmode ) ; else dest = NULL_RTX ; op1 = lowpart_subreg ( vmode , force_reg ( mode , operands [ 2 ] ) , mode ) ; mask = ix86_build_signbit_mask ( vmode , 0 , 0 ) ; if ( CONST_DOUBLE_P ( operands [ 1 ] ) ) { op0 = simplify_unary_operation ( ABS , mode , operands [ 1 ] , mode ) ; if ( op0 == CONST0_RTX ( mode ) ) { emit_move_insn ( vdest , gen_rtx_AND ( vmode , mask , op1 ) ) ; if ( dest ) emit_move_insn ( dest , lowpart_subreg ( mode , vdest , vmode ) ) ; return ; } if ( GET_MODE_SIZE ( mode ) < 16 ) op0 = ix86_build_const_vector ( vmode , false , op0 ) ; op0 = force_reg ( vmode , op0 ) ; } else op0 = lowpart_subreg ( vmode , force_reg ( mode , operands [ 1 ] ) , mode ) ; op2 = gen_reg_rtx ( vmode ) ; op3 = gen_reg_rtx ( vmode ) ; emit_move_insn ( op2 , gen_rtx_AND ( vmode , gen_rtx_NOT ( vmode , mask ) , op0 ) ) ; emit_move_insn ( op3 , gen_rtx_AND ( vmode , mask , op1 ) ) ; emit_move_insn ( vdest , gen_rtx_IOR ( vmode , op2 , op3 ) ) ; if ( dest ) emit_move_insn ( dest , lowpart_subreg ( mode , vdest , vmode ) ) ; } </s>

Expand a copysign operation . Special case operand 0 being a constant .


<s> static machine_mode rs6000_promote_function_mode ( const_tree type ATTRIBUTE_UNUSED , machine_mode mode , int * punsignedp ATTRIBUTE_UNUSED , const_tree , int ) { PROMOTE_MODE ( mode , * punsignedp , type ) ; return mode ; } </s>

On rs6000 , function arguments are promoted , as are function return values .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> enum aarch64_symbol_type aarch64_classify_symbol ( rtx x , HOST_WIDE_INT offset ) { if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - 0x10000 , 0x10000 ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - 0x100000 , 0x100000 ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_TINY_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_TINY_GOT ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_SPIC : case AARCH64_CMODEL_SMALL_PIC : if ( ! aarch64_symbol_binds_local_p ( x ) ) return ( aarch64_cmodel == AARCH64_CMODEL_SMALL_SPIC ? SYMBOL_SMALL_GOT_28K : SYMBOL_SMALL_GOT_4G ) ; return SYMBOL_SMALL_ABSOLUTE ; case AARCH64_CMODEL_LARGE : if ( ! aarch64_pcrelative_literal_loads && CONSTANT_POOL_ADDRESS_P ( x ) ) return SYMBOL_SMALL_ABSOLUTE ; else return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } return SYMBOL_FORCE_TO_MEM ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .


<s> static void * ix86_init_cost ( class loop * ) { unsigned * cost = XNEWVEC ( unsigned , 3 ) ; cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = 0 ; return cost ; } </s>


<s> static tree rs6000_d_handle_target_object_format ( void ) { const char * objfmt = NULL ; if ( TARGET_ELF ) objfmt = "elf" ; else if ( TARGET_MACHO ) objfmt = "macho" ; else if ( TARGET_XCOFF ) objfmt = "coff" ; if ( objfmt == NULL ) return NULL_TREE ; return build_string_literal ( strlen ( objfmt ) + 1 , objfmt ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` objectFormat '' ) ' .


<s> bool mep_reuse_lo_p ( rtx lo , rtx gpr , rtx_insn * insn , bool gpr_dead_p ) { bool result = mep_reuse_lo_p_1 ( lo , gpr , insn , gpr_dead_p ) ; extract_insn ( insn ) ; return result ; } </s>

A wrapper around mep_reuse_lo_p_1 that preserves recog_data .


"Can only put epilog before 'retl' instruction!"


<s> static bool ix86_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( CC_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( GET_MODE_CLASS ( mode ) == MODE_CC || GET_MODE_CLASS ( mode ) == MODE_RANDOM || GET_MODE_CLASS ( mode ) == MODE_PARTIAL_INT ) return false ; if ( STACK_REGNO_P ( regno ) ) return VALID_FP_MODE_P ( mode ) ; if ( MASK_REGNO_P ( regno ) ) return ( VALID_MASK_REG_MODE ( mode ) || ( TARGET_AVX512BW && VALID_MASK_AVX512BW_MODE ( mode ) ) ) ; if ( BND_REGNO_P ( regno ) ) return VALID_BND_REG_MODE ( mode ) ; if ( SSE_REGNO_P ( regno ) ) { if ( TARGET_AVX512F && ( mode == XImode || VALID_AVX512F_REG_MODE ( mode ) || VALID_AVX512F_SCALAR_MODE ( mode ) ) ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SFmode ) return true ; if ( ( TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW ) && MOD4_SSE_REGNO_P ( regno ) && mode == V64SImode ) return true ; if ( TARGET_AVX512VL && ( mode == OImode || mode == TImode || VALID_AVX256_REG_MODE ( mode ) || VALID_AVX512VL_128_REG_MODE ( mode ) ) ) return true ; if ( EXT_REX_SSE_REGNO_P ( regno ) ) return false ; return ( ( TARGET_AVX && VALID_AVX256_REG_OR_OI_MODE ( mode ) ) || VALID_SSE_REG_MODE ( mode ) || VALID_SSE2_REG_MODE ( mode ) || VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( MMX_REGNO_P ( regno ) ) { return ( VALID_MMX_REG_MODE ( mode ) || VALID_MMX_REG_MODE_3DNOW ( mode ) ) ; } if ( mode == QImode ) { if ( ANY_QI_REGNO_P ( regno ) ) return true ; if ( ! TARGET_PARTIAL_REG_STALL ) return true ; if ( lra_in_progress ) return true ; return ! can_create_pseudo_p ( ) ; } else if ( VALID_INT_MODE_P ( mode ) ) return true ; else if ( VALID_FP_MODE_P ( mode ) ) return true ; else if ( VALID_DFP_MODE_P ( mode ) ) return true ; else if ( VALID_MMX_REG_MODE_3DNOW ( mode ) || VALID_MMX_REG_MODE ( mode ) ) return true ; return false ; } </s>

Return TRUE if hard register REGNO can hold a value of machine-mode MODE .


<s> void setReg ( MCRegister PhysReg ) { Reg . RegNum = PhysReg ; } </s>

Assigns the associated register for this edge .


"missing name in %<target(\"cpu=\")%> pragma or attribute"

"invalid name (\"%s\") in %<target(\"cpu=\")%> pragma or attribute"

"invalid feature modifier %s of value (\"%s\") in "

Handle the argument CPU_STR to the cpu= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> const Comet2InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool gen_ldm_seq ( rtx * operands , int nops , bool sort_regs ) { int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == 0 ) return false ; if ( sort_regs ) for ( i = 0 ; i < nops - 1 ; i ++ ) for ( j = i + 1 ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( peep2_reg_dead_p ( nops , base_reg_rtx ) ) ; gcc_assert ( ldm_case == 1 || ldm_case == 5 ) ; write_back = TRUE ; } if ( ldm_case == 5 ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ 0 ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; if ( ! TARGET_THUMB1 ) { base_reg = regs [ 0 ] ; base_reg_rtx = newbase ; } } for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of loads into an LDM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate loads we are trying to combine . SORT_REGS is true if we can reorder the registers because they are used commutatively subsequently . Returns true iff we could generate a new instruction .


<s> static rtx rs6000_load_constant_and_splat ( machine_mode mode , REAL_VALUE_TYPE dconst ) { rtx reg ; if ( mode == SFmode || mode == DFmode ) { rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , SFmode ) ; rtvec v = gen_rtvec ( 4 , d , d , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else if ( mode == V2DFmode ) { rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , DFmode ) ; rtvec v = gen_rtvec ( 2 , d , d ) ; reg = gen_reg_rtx ( mode ) ; rs6000_expand_vector_init ( reg , gen_rtx_PARALLEL ( mode , v ) ) ; } else gcc_unreachable ( ) ; return reg ; } </s>

Load up a constant . If the mode is a vector mode , splat the value across all of the vector elements .


<s> static bool hasLiveCondCodeDef ( MachineInstr * MI ) { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == X86 :: EFLAGS && ! MO . isDead ( ) ) { return true ; } } return false ; } </s>

True if MI has a condition code def , e.g .


<s> const ARMSubtarget * ARMBaseTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; Attribute SFAttr = F . getFnAttribute ( "use-soft-float" ) ; bool SoftFloat = ! SFAttr . hasAttribute ( Attribute :: None ) ? SFAttr . getValueAsString ( ) == "true" : Options . UseSoftFloat ; auto & I = SubtargetMap [ CPU + FS + ( SoftFloat ? "use-soft-float=true" : "use-soft-float=false" ) ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < ARMSubtarget > ( TargetTriple , CPU , FS , * this , isLittle ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

ARM ARM ARM "target-cpu" "target-features" "use-soft-float" "true" "use-soft-float=true" "use-soft-float=false" ARM


"Requesting 64-bit offset in 32-bit immediate!"


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( p0 , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( 0 ) ; } if ( ! SPReg ) SPReg = MIRBuilder . buildCopy ( p0 , Register ( AArch64 :: SP ) ) . getReg ( 0 ) ; auto OffsetReg = MIRBuilder . buildConstant ( s64 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return IN_RANGE ( val , - 1020 , 1020 ) && ( val & 3 ) == 0 ; else return IN_RANGE ( val , - 255 , 4095 - 4 ) ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Name
+=
AP
.
MAI
->
getGlobalPrefix
(
)
;
Name
+=
MO
.
getSymbolName
(
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
bool
isImplicitlyPrivate
=
false
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
||
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
)
isImplicitlyPrivate
=
true
;
AP
.
Mang
->
getNameWithPrefix
(
Name
,
GV
,
isImplicitlyPrivate
)
;
}
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
{
Name
+=
"$stub"
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
Name
.
erase
(
Name
.
end
(
)
5
,
Name
.
end
(
)
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
Name
+=
"$non_lazy_ptr"
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
==
0
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; bool IsNaCl = TM . getSubtarget < X86Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn ) return CSR_NaCl64EHRet_SaveList ; return CSR_NaCl64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


"***** AArch64SpeculationHardening - automatic insertion of "

"***** AArch64SpeculationHardening - track control flow *****\n"

runOnMachineFunction - Emit the function body .


<s> static rtx loongarch_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! IMM12_OPERAND ( offset ) ) { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ; high = loongarch_force_temporary ( temp , high ) ; reg = loongarch_force_temporary ( temp , gen_rtx_PLUS ( Pmode , high , reg ) ) ; } return plus_constant ( Pmode , reg , offset ) ; } </s>

Return a legitimate address for REG + OFFSET . TEMP is as for loongarch_force_temporary ; it is only needed when OFFSET is not a IMM12_OPERAND .


<s>
void
output_ascii
(
FILE
*
file
,
const
char
*
p
,
int
n
)
{
char
c
;
int
i
,
count_string
;
const
char
*
for_string
=
"\t.byte \""
;
const
char
*
for_decimal
=
"\t.byte "
;
const
char
*
to_close
=
;
count_string
=
0
;
for
(
i
=
0
;
i
<
n
;
i
++
)
{
c
=
*
p
++
;
if
(
c
>=
' '
&&
c
<
0177
)
{
if
(
for_string
)
fputs
(
for_string
,
file
)
;
putc
(
c
,
file
)
;
if
(
c
==
'"'
)
{
putc
(
c
,
file
)
;
++
count_string
;
}
for_string
=
;
for_decimal
=
"\"\n\t.byte "
;
to_close
=
"\"\n"
;
++
count_string
;
if
(
count_string
>=
512
)
{
fputs
(
to_close
,
file
)
;
for_string
=
"\t.byte \""
;
for_decimal
=
"\t.byte "
;
to_close
=
;
count_string
=
0
;
}
}
else
{
if
(
for_decimal
)
fputs
(
for_decimal
,
file
)
;
fprintf
(
file
,
"%d"
,
c
)
;
for_string
=
"\n\t.byte \""
;
for_decimal
=
", "
;
to_close
=
"\n"
;
count_string
=
0
;
}
}
if
(
to_close
)
fputs
(
to_close
,
file
)
;
}
</s>

Output an assembler pseudo-op to write an ASCII string of N characters starting at P to FILE . On the RS/6000 , we have to do this using the .byte operation and write out special characters outside the quoted string . Also , the assembler is broken ; very long strings are truncated , so we must artificially break them up early .


<s> bool MipsTargetLowering :: IsGlobalInSmallSection ( GlobalValue * GV ) { const TargetData * TD = getTargetData ( ) ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypeAllocSize ( Ty ) ; if ( GVA -> hasInitializer ( ) && GV -> hasLocalLinkage ( ) ) { Constant * C = GVA -> getInitializer ( ) ; const ConstantArray * CVA = dyn_cast < ConstantArray > ( C ) ; if ( CVA && CVA -> isCString ( ) ) return false ; } return IsInSmallSection ( Size ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s>
bool
ARMCodeGenPrepare
::
runOnFunction
(
Function
&
F
)
{
if
(
skipFunction
(
F
)
||
DisableCGP
)
return
false
;
auto
*
TPC
=
&
getAnalysis
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
return
false
;
const
TargetMachine
&
TM
=
TPC
->
getTM
<
TargetMachine
>
(
)
;
ST
=
&
TM
.
getSubtarget
<
ARMSubtarget
>
(
F
)
;
bool
MadeChange
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Running on "
<<
F
.
getName
(
)
<<
"\n"
)
;
for
(
BasicBlock
&
BB
:
F
)
{
auto
&
Insts
=
BB
.
getInstList
(
)
;
for
(
auto
&
I
:
Insts
)
{
if
(
AllVisited
.
count
(
&
I
)
)
continue
;
if
(
isa
<
ICmpInst
>
(
I
)
)
{
auto
&
CI
=
cast
<
ICmpInst
>
(
I
)
;
if
(
CI
.
isSigned
(
)
||
!
isa
<
IntegerType
>
(
CI
.
getOperand
(
0
)
->
getType
(
)
)
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM CGP: Searching from: "
<<
CI
<<
"\n"
)
;
for
(
auto
&
Op
:
CI
.
operands
(
)
)
{
if
(
auto
*
I
=
dyn_cast
<
Instruction
>
(
Op
)
)
MadeChange
|=
TryToPromote
(
I
)
;
}
}
}
Promoter
->
Cleanup
(
)
;
LLVM_DEBUG
(
if
(
verifyFunction
(
F
,
&
dbgs
(
)
)
)
{
dbgs
(
)
;
report_fatal_error
(
"Broken function after type promotion"
)
;
}
)
;
}
if
(
MadeChange
)
LLVM_DEBUG
(
dbgs
(
)
<<
"After ARMCodeGenPrepare: "
<<
F
<<
"\n"
)
;
return
MadeChange
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

ARM
ARM
ARM
"ARM CGP: Running on "
"\n"
0
"ARM CGP: Searching from: "
"\n"
"Broken function after type promotion"
"After ARMCodeGenPrepare: "
"\n"


<s> void PPCRegisterInfo :: adjustStackMapLiveOutMask ( uint32_t * Mask ) const { for ( unsigned PseudoReg : { PPC :: ZERO , PPC :: ZERO8 , PPC :: RM } ) Mask [ PseudoReg / 32 ] &= ~ ( 1u << ( PseudoReg % 32 ) ) ; } </s>

Prior to adding the live-out mask to a stackmap or patchpoint instruction , provide the target the opportunity to adjust it ( mainly to remove pseudo-registers that should be ignored ) .


<s> static bool mips_hard_regno_mode_ok_p ( unsigned int regno , machine_mode mode ) { unsigned int size ; enum mode_class mclass ; if ( mode == CCV2mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 2 == 0 ) ; if ( mode == CCV4mode ) return ( ISA_HAS_8CC && ST_REG_P ( regno ) && ( regno - ST_REG_FIRST ) % 4 == 0 ) ; if ( mode == CCmode ) return ISA_HAS_8CC ? ST_REG_P ( regno ) : regno == FPSW_REGNUM ; size = GET_MODE_SIZE ( mode ) ; mclass = GET_MODE_CLASS ( mode ) ; if ( GP_REG_P ( regno ) && mode != CCFmode ) return ( ( regno - GP_REG_FIRST ) & 1 ) == 0 || size <= UNITS_PER_WORD ; if ( FP_REG_P ( regno ) && ( ( ( regno - FP_REG_FIRST ) % MAX_FPRS_PER_FMT ) == 0 || ( MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG ) ) ) { if ( TARGET_O32_FP64A_ABI && size <= 4 && ( regno & 1 ) != 0 ) return false ; if ( mode == CCFmode ) return ! ( TARGET_FLOATXX && ( regno & 1 ) != 0 ) ; if ( TARGET_LOONGSON_VECTORS && ( mode == V2SImode || mode == V4HImode || mode == V8QImode || mode == DImode ) ) return true ; if ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT ) return size <= UNITS_PER_FPVALUE ; if ( mclass == MODE_INT ) return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG ; } if ( ACC_REG_P ( regno ) && ! VECTOR_MODE_P ( mode ) && ( INTEGRAL_MODE_P ( mode ) || ALL_FIXED_POINT_MODE_P ( mode ) ) ) { if ( MD_REG_P ( regno ) ) { if ( size <= UNITS_PER_WORD * 2 ) return regno == ( size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST ) ; } else { if ( size <= UNITS_PER_WORD ) return true ; if ( size <= UNITS_PER_WORD * 2 && ( ( regno - DSP_ACC_REG_FIRST ) & 1 ) == 0 ) return true ; } } if ( ALL_COP_REG_P ( regno ) ) return mclass == MODE_INT && size <= UNITS_PER_WORD ; if ( regno == GOT_VERSION_REGNUM ) return mode == SImode ; return false ; } </s>

Return true if register REGNO can store a value of mode MODE . The result of this function is cached in mips_hard_regno_mode_ok .


<s> void CSKYMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; uint32_t Bin = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint16_t LO16 = static_cast < uint16_t > ( Bin ) ; uint16_t HI16 = static_cast < uint16_t > ( Bin >> 16 ) ; if ( Size == 4 ) support :: endian :: write < uint16_t > ( OS , HI16 , support :: little ) ; support :: endian :: write < uint16_t > ( OS , LO16 , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .

CSKY CSKY 16 4 support::endian support::little support::endian support::little


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> bool X86TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget -> ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget -> is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
Ctx
,
IsLittleEndian
,
true
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> alias_set_type ix86_GOT_alias_set ( void ) { static alias_set_type set = - 1 ; if ( set == - 1 ) set = new_alias_set ( ) ; return set ; } </s>

Return an unique alias set for the GOT .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
setCanHaveModuleDir
(
false
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
NameLoc
,
"Unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
ParseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
ParseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"Unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> bool ShouldShrinkFPConstant ( EVT VT ) const { return VT != MVT :: f128 ; } </s>

If true , then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime .