<s> static void emit_predicate_relation_info ( ) { int i ; for ( i = n_basic_blocks - 1 ; i >= 0 ; -- i ) { basic_block bb = BASIC_BLOCK ( i ) ; int r ; rtx head = bb -> head ; if ( GET_CODE ( head ) != CODE_LABEL ) continue ; if ( GET_CODE ( NEXT_INSN ( head ) ) == NOTE && NOTE_LINE_NUMBER ( NEXT_INSN ( head ) ) == NOTE_INSN_BASIC_BLOCK ) head = NEXT_INSN ( head ) ; for ( r = PR_REG ( 0 ) ; r < PR_REG ( 64 ) ; r += 2 ) if ( REGNO_REG_SET_P ( bb -> global_live_at_start , r ) ) { rtx p = gen_rtx_REG ( BImode , r ) ; rtx n = emit_insn_after ( gen_pred_rel_mutex ( p ) , head ) ; if ( head == bb -> end ) bb -> end = n ; head = n ; } } for ( i = n_basic_blocks - 1 ; i >= 0 ; -- i ) { basic_block bb = BASIC_BLOCK ( i ) ; rtx insn = bb -> head ; while ( 1 ) { if ( GET_CODE ( insn ) == CALL_INSN && GET_CODE ( PATTERN ( insn ) ) == COND_EXEC && find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) { rtx b = emit_insn_before ( gen_safe_across_calls_all ( ) , insn ) ; rtx a = emit_insn_after ( gen_safe_across_calls_normal ( ) , insn ) ; if ( bb -> head == insn ) bb -> head = b ; if ( bb -> end == insn ) bb -> end = a ; } if ( insn == bb -> end ) break ; insn = NEXT_INSN ( insn ) ; } } } </s>

Emit pseudo-ops for the assembler to describe predicate relations . At present this assumes that we only consider predicate pairs to be mutex , and that the assembler can deduce proper values from straight-line code .


<s> void addPostRegAlloc ( ) override { if ( getMipsSubtarget ( ) . isCheri ( ) ) addPass ( createCheriInvalidatePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"FMA or FMUL at insn %d but destination "

"register (%s) has different parity from expected to "

"Destination register of insn %d could not be "

"renamed. Dependent FMA insns will use this parity from "

Rename the destination register of a single FMUL or FMADD/FMSUB instruction represented by FMA_NODE to a register that respect the target parity for FOREST or with same parity of the instruction represented by its parent node if it has one .


<s> SDValue SystemZTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_SystemZ ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( 1 ) ; SDValue RetValue = Chain . getValue ( 0 ) ; InFlag = Chain . getValue ( 2 ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( ISD :: AssertSext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( ISD :: AssertZext , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( ISD :: TRUNCATE , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 pseudo instruction expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned getStackAlignment ( ) const { return StackAlign ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void PPCInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getCPUDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = PPC :: NOP ; break ; case PPC :: DIR_PWR6 : Opcode = PPC :: NOP_GT_PWR6 ; break ; case PPC :: DIR_PWR7 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR8 : Opcode = PPC :: NOP_GT_PWR7 ; break ; case PPC :: DIR_PWR9 : Opcode = PPC :: NOP_GT_PWR7 ; break ; } DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s>
SDValue
SystemZTargetLowering
::
joinRegisterPartsIntoValue
(
SelectionDAG
&
DAG
,
const
SDLoc
&
DL
,
const
SDValue
*
Parts
,
unsigned
NumParts
,
MVT
PartVT
,
EVT
ValueVT
,
Optional
<
CallingConv
::
ID
>
CC
)
const
{
assert
(
(
ValueVT
!=
MVT
::
i128
||
(
(
NumParts
==
1
&&
PartVT
==
MVT
::
Untyped
)
||
(
NumParts
==
2
&&
PartVT
==
MVT
::
i64
)
)
)
&&
"Unknown handling of i128 value."
)
;
if
(
ValueVT
==
MVT
::
i128
&&
NumParts
==
1
)
return
lowerGR128ToI128
(
DAG
,
Parts
[
0
]
)
;
return
SDValue
(
)
;
}
</s>

Target-specific combining of register parts into its original value .


<s> SDValue SystemZTargetLowering :: prepareVolatileOrAtomicLoad ( SDValue Chain , const SDLoc & DL , SelectionDAG & DAG ) const { return DAG . getNode ( SystemZISD :: SERIALIZE , DL , MVT :: Other , Chain ) ; } </s>

This callback is used to prepare for a volatile or atomic load .

SystemZ SystemZ SystemZISD::SERIALIZE MVT::Other


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


"Caller should have checked for a comparison"

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { MF = & Fn ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TL = STI -> getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RegClassInfoValid = false ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; if ( isThumb1 ) Modified |= CombineMovBx ( MBB ) ; } Allocator . DestroyAll ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool arm_change_mode_p ( tree func ) { if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( func ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; int flags = callee_opts -> x_target_flags ; return ( TARGET_THUMB_P ( flags ) != TARGET_THUMB ) ; } </s>

Check that FUNC is called with a different mode .


<s>
static
void
pru_file_start
(
void
)
{
default_file_start
(
)
;
fprintf
(
asm_out_file
,
"\t.set no_warn_regname_label\n"
)
;
}
</s>


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override { return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ; } </s>

Overflow nodes should get combined/lowered to optimal instructions ( they should allow eliminating explicit compares by getting flags from math ops ) .


<s>
bool
LVLGen
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Begin LVLGen **********\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Function: "
<<
F
.
getName
(
)
<<
'\n'
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
bool
Changed
=
false
;
const
VESubtarget
&
Subtarget
=
F
.
getSubtarget
<
VESubtarget
>
(
)
;
TII
=
Subtarget
.
getInstrInfo
(
)
;
TRI
=
Subtarget
.
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
FI
=
F
.
begin
(
)
,
FE
=
F
.
end
(
)
;
FI
!=
FE
;
++
FI
)
Changed
|=
runOnMachineBasicBlock
(
*
FI
)
;
if
(
Changed
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"********** End LVLGen **********\n"
)
;
return
Changed
;
}
</s>


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize ) ) ; } return false ; } </s>


" is allocatable: function has no frame pointer"

Return the register ID of the name passed in .


<s> static void arm_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr , mem , a_tramp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 8 : 12 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 12 : 16 ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp , 0 ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__clear_cache" ) , LCT_NORMAL , VOIDmode , a_tramp , Pmode , plus_constant ( Pmode , a_tramp , TRAMPOLINE_SIZE ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline .


<s> bool X86TargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( ! VT . isSimple ( ) ) return false ; if ( VT . getSimpleVT ( ) . getScalarType ( ) == MVT :: i1 ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == 64 ) return false ; return isTypeLegal ( VT . getSimpleVT ( ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> bool VEAsmParser :: ParseDirective ( AsmToken DirectiveID ) { std :: string IDVal = DirectiveID . getIdentifier ( ) . lower ( ) ; if ( IDVal == ".word" ) return parseLiteralValues ( 4 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".long" ) return parseLiteralValues ( 8 , DirectiveID . getLoc ( ) ) ; if ( IDVal == ".llong" ) return parseLiteralValues ( 8 , DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool rs6000_overloaded_builtin_p ( enum rs6000_builtins fncode ) { return ( rs6000_builtin_info [ ( int ) fncode ] . attr & RS6000_BTC_OVERLOADED ) != 0 ; } </s>

Return true if a builtin function is overloaded .


<s> static enum insn_code aarch64_constant_pool_reload_icode ( machine_mode mode ) { switch ( mode ) { case E_SFmode : return CODE_FOR_aarch64_reload_movcpsfdi ; case E_DFmode : return CODE_FOR_aarch64_reload_movcpdfdi ; case E_TFmode : return CODE_FOR_aarch64_reload_movcptfdi ; case E_V8QImode : return CODE_FOR_aarch64_reload_movcpv8qidi ; case E_V16QImode : return CODE_FOR_aarch64_reload_movcpv16qidi ; case E_V4HImode : return CODE_FOR_aarch64_reload_movcpv4hidi ; case E_V8HImode : return CODE_FOR_aarch64_reload_movcpv8hidi ; case E_V2SImode : return CODE_FOR_aarch64_reload_movcpv2sidi ; case E_V4SImode : return CODE_FOR_aarch64_reload_movcpv4sidi ; case E_V2DImode : return CODE_FOR_aarch64_reload_movcpv2didi ; case E_V2DFmode : return CODE_FOR_aarch64_reload_movcpv2dfdi ; default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; } </s>

Return the reload icode required for a constant pool in mode .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new ARMCallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new ARMLegalizerInfo ( * this ) ) ; auto * RBI = new ARMRegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createARMInstructionSelector ( * static_cast < const ARMBaseTargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AdvSIMD Scalar Operation Optimization"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void Cpu0MCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static short find_insn_regmode_weight ( rtx insn , machine_mode mode ) { short reg_weight = 0 ; rtx x ; x = PATTERN ( insn ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; if ( GET_CODE ( x ) == PARALLEL ) { int j ; for ( j = XVECLEN ( x , 0 ) - 1 ; j >= 0 ; j -- ) { x = XVECEXP ( PATTERN ( insn ) , 0 , j ) ; reg_weight += find_set_regmode_weight ( x , mode ) ; } } for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , 1 ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , 0 ) ; if ( REG_P ( note ) && GET_MODE ( note ) == mode ) reg_weight -- ; } } return reg_weight ; } </s>


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> SDValue SICTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; SICCC SICCCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; SICCCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> rtx ix86_split_stack_guard ( void ) { int offset ; addr_space_t as = DEFAULT_TLS_SEG_REG ; rtx r ; gcc_assert ( flag_split_stack ) ; offset = TARGET_THREAD_SPLIT_STACK_OFFSET ; gcc_unreachable ( ) ; r = GEN_INT ( offset ) ; r = gen_const_mem ( Pmode , r ) ; set_mem_addr_space ( r , as ) ; return r ; } </s>

Return location of the stack guard value in the TLS block .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_RegMask ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
FixupKind
==
FK_NONE
)
return
true
;
if
(
FixupKind
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool MandarinPassConfig :: addPreEmitPass ( ) { return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI . getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI . getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : return fixCommutedOpIndices ( SrcOpIdx1 , SrcOpIdx2 , 1 , 2 ) ; } return false ; } default : if ( isFMA3 ( MI . getOpcode ( ) ) ) return findFMA3CommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } return false ; } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> static void aarch64_emit_mult ( rtx dst , rtx ptrue , rtx src1 , rtx src2 ) { if ( ptrue ) emit_insn ( gen_aarch64_pred ( UNSPEC_COND_FMUL , GET_MODE ( dst ) , dst , ptrue , src1 , src2 , gen_int_mode ( SVE_RELAXED_GP , SImode ) ) ) ; else emit_set_insn ( dst , gen_rtx_MULT ( GET_MODE ( dst ) , src1 , src2 ) ) ; } </s>

Emit code to perform the floating-point operation : DST = SRC1 * SRC2 where all three operands are already known to be registers . If the operation is an SVE one , PTRUE is a suitable all-true predicate .


"sorry, I don't know how to store this sort of reg in the stack\n"

Store the specified register of the given register class to the specified stack frame index .


<s> bool mep_store_data_bypass_p ( rtx_insn * prev , rtx_insn * insn ) { return INSN_P ( insn ) ? mep_store_data_bypass_1 ( prev , PATTERN ( insn ) ) : false ; } </s>

Return true if INSN is a store instruction and if the store address has no true dependence on PREV .


<s> static rtx gen_rx_rtsd_vector ( unsigned int adjust , unsigned int low , unsigned int high ) { unsigned int i ; unsigned int bias = 3 ; unsigned int count = ( high - low ) + bias ; rtx vector ; vector = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; XVECEXP ( vector , 0 , 0 ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , adjust ) ) ; for ( i = 0 ; i < count - 2 ; i ++ ) XVECEXP ( vector , 0 , i + 1 ) = gen_rtx_SET ( gen_rtx_REG ( SImode , low + i ) , gen_rtx_MEM ( SImode , i == 0 ? stack_pointer_rtx : plus_constant ( Pmode , stack_pointer_rtx , i * UNITS_PER_WORD ) ) ) ; XVECEXP ( vector , 0 , count - 1 ) = ret_rtx ; return vector ; } </s>

Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate .


<s> AArch64TargetMachine :: AArch64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , LittleEndian ) , DL ( Subtarget . isTargetMachO ( ) ? "e-m:o-i64:64-i128:128-n32:64-S128" : ( LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128" : "E-m:e-i64:64-i128:128-n32:64-S128" ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , FrameLowering ( * this , Subtarget ) , TSInfo ( * this ) { initAsmInfo ( ) ; } </s>


<s> uint64_t evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size ) const { if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ 0 ] . OperandType != MCOI :: OPERAND_PCREL ) return - 1ULL ; int64_t Imm = Inst . getOperand ( 0 ) . getImm ( ) ; return Addr + Imm + 8 ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> static rtx nds32_expand_unopimm_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p , const char * name ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; int op0_num = return_p ? 1 : 0 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op0_num , op0 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 ) ; else pat = GEN_FCN ( icode ) ( op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take one operands and the first is immediate .


<s> bool AArch64PassConfig :: addPreRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAdvSIMDScalar ) addPass ( createAArch64AdvSIMDScalar ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> int AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) . getBytes ( ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> int ia64_move_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != MEM ) return 1 ; if ( GET_CODE ( src ) == MEM ) return 0 ; if ( register_operand ( src , VOIDmode ) ) return 1 ; if ( INTEGRAL_MODE_P ( GET_MODE ( dst ) ) ) return src == const0_rtx ; else return GET_CODE ( src ) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G ( src ) ; } </s>

Return 1 if the operands of a move are ok .


More limited version of SimplifyDemandedBits that can be used to `` look through '' ops that do n't contribute to the DemandedBits/DemandedElts - bitwise ops etc .


<s> static void mt_emit_save_regs ( enum save_direction direction , struct mt_frame_info info ) { rtx base_reg ; int regno ; int reg_mask = info . reg_mask & ~ ( FP_MASK | LINK_MASK ) ; int offset = info . total_size ; int stack_offset = info . total_size ; if ( ! info . save_fp && ! info . save_lr && ! reg_mask ) return ; if ( CONST_OK_FOR_LETTER_P ( offset , 'O' ) ) base_reg = stack_pointer_rtx ; else { base_reg = gen_rtx_REG ( SImode , GPR_R9 ) ; offset = 0 ; } if ( info . save_fp ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; } if ( info . save_lr ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , GPR_LINK ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } for ( regno = GPR_R0 ; regno <= GPR_LAST ; regno ++ ) { if ( ( reg_mask & ( 1 << regno ) ) != 0 ) { offset -= UNITS_PER_WORD ; stack_offset -= UNITS_PER_WORD ; mt_emit_save_restore ( direction , gen_rtx_REG ( SImode , regno ) , gen_rtx_MEM ( SImode , gen_rtx_PLUS ( SImode , base_reg , GEN_INT ( offset ) ) ) , stack_offset ) ; } } } </s>

Emit code to save registers in the prologue and restore register in epilogue .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
Outs
[
i
]
.
Val
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , Subtarget , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget . abiUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool Cpu0TargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const Cpu0Subtarget & Subtarget = TM . getSubtarget < Cpu0Subtarget > ( ) ; if ( ! Subtarget . useSmallSection ( ) ) return false ; const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s>
bool
AArch64InstrInfo
::
isFPRCopy
(
const
MachineInstr
&
MI
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
COPY
:
{
unsigned
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
return
(
AArch64
::
FPR64RegClass
.
contains
(
DstReg
)
||
AArch64
::
FPR128RegClass
.
contains
(
DstReg
)
)
;
}
case
AArch64
::
ORRv16i8
:
if
(
MI
.
getOperand
(
1
)
.
getReg
(
)
==
MI
.
getOperand
(
2
)
.
getReg
(
)
)
{
assert
(
MI
.
getDesc
(
)
.
getNumOperands
(
)
==
3
&&
MI
.
getOperand
(
0
)
.
isReg
(
)
&&
"invalid ORRv16i8 operands"
)
;
return
true
;
}
break
;
}
return
false
;
}
</s>

Does this instruction rename an FPR without modifying bits ?


"mips16 and nomips16 specified on the same function"

Reset the subtarget for the Mips target .


<s> void Mips16FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MipsInstrInfo & TII = * static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; if ( isInt < 16 > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: SaveRaF16 ) ) . addImm ( StackSize ) ; if ( hasFP ( MF ) ) BuildMI ( MBB , MBBI , dl , TII . get ( Mips :: MoveR3216 ) , Mips :: S0 ) . addReg ( Mips :: SP ) ; } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static int mips_address_cost ( rtx addr ) { return mips_address_insns ( addr , SImode ) ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> static inline tree def_builtin ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = NULL_TREE ; if ( ! ( mask & OPTION_MASK_ISA_64BIT ) || TARGET_64BIT ) { ix86_builtins_isa [ ( int ) code ] . isa = mask ; ix86_builtins_isa [ ( int ) code ] . isa2 = mask2 ; mask &= ~ OPTION_MASK_ISA_64BIT ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL ) && mask != OPTION_MASK_ISA_AVX512VL ) mask &= ~ OPTION_MASK_ISA_AVX512VL ; if ( ( mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW ) && mask != OPTION_MASK_ISA_AVX512BW ) mask &= ~ OPTION_MASK_ISA_AVX512BW ; if ( ( ( mask2 == 0 || ( mask2 & ix86_isa_flags2 ) != 0 ) && ( mask == 0 || ( mask & ix86_isa_flags ) != 0 ) ) || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type = ix86_get_builtin_func_type ( tcode ) ; decl = add_builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values |= mask ; deferred_isa_values2 |= mask2 ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . const_p = false ; ix86_builtins_isa [ ( int ) code ] . pure_p = false ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = true ; } } return decl ; } </s>

Add a SPARC builtin function with NAME , ICODE , CODE and TYPE . Return the function decl or NULL_TREE if the builtin was not added .


<s> bool PPCTTIImpl :: getTgtMemIntrinsic ( IntrinsicInst * Inst , MemIntrinsicInfo & Info ) { switch ( Inst -> getIntrinsicID ( ) ) { case Intrinsic :: ppc_altivec_lvx : case Intrinsic :: ppc_altivec_lvxl : case Intrinsic :: ppc_altivec_lvebx : case Intrinsic :: ppc_altivec_lvehx : case Intrinsic :: ppc_altivec_lvewx : case Intrinsic :: ppc_vsx_lxvd2x : case Intrinsic :: ppc_vsx_lxvw4x : case Intrinsic :: ppc_vsx_lxvd2x_be : case Intrinsic :: ppc_vsx_lxvw4x_be : case Intrinsic :: ppc_vsx_lxvl : case Intrinsic :: ppc_vsx_lxvll : case Intrinsic :: ppc_vsx_lxvp : { Info . PtrVal = Inst -> getArgOperand ( 0 ) ; Info . ReadMem = true ; Info . WriteMem = false ; return true ; } case Intrinsic :: ppc_altivec_stvx : case Intrinsic :: ppc_altivec_stvxl : case Intrinsic :: ppc_altivec_stvebx : case Intrinsic :: ppc_altivec_stvehx : case Intrinsic :: ppc_altivec_stvewx : case Intrinsic :: ppc_vsx_stxvd2x : case Intrinsic :: ppc_vsx_stxvw4x : case Intrinsic :: ppc_vsx_stxvd2x_be : case Intrinsic :: ppc_vsx_stxvw4x_be : case Intrinsic :: ppc_vsx_stxvl : case Intrinsic :: ppc_vsx_stxvll : case Intrinsic :: ppc_vsx_stxvp : { Info . PtrVal = Inst -> getArgOperand ( 1 ) ; Info . ReadMem = false ; Info . WriteMem = true ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void aarch64_gen_atomic_cas ( rtx rval , rtx mem , rtx expected , rtx desired , rtx model ) { rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; machine_mode mode ; mode = GET_MODE ( mem ) ; switch ( mode ) { case E_QImode : gen = gen_aarch64_atomic_casqi ; break ; case E_HImode : gen = gen_aarch64_atomic_cashi ; break ; case E_SImode : gen = gen_aarch64_atomic_cassi ; break ; case E_DImode : gen = gen_aarch64_atomic_casdi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen_rtx_SET ( rval , expected ) ) ; emit_insn ( gen ( rval , mem , desired , model ) ) ; aarch64_gen_compare_reg ( EQ , rval , expected ) ; } </s>

Emit an atomic compare-and-swap operation . RVAL is the destination register for the data in memory . EXPECTED is the value expected to be in memory . DESIRED is the value to store to memory . MEM is the memory location . MODEL is the memory ordering to use .


<s> static void mimic_memory_attributes_and_flags ( rtx new_mem_exp , const_rtx original_mem_exp ) { RTX_FLAG ( new_mem_exp , jump ) = RTX_FLAG ( original_mem_exp , jump ) ; RTX_FLAG ( new_mem_exp , call ) = RTX_FLAG ( original_mem_exp , call ) ; RTX_FLAG ( new_mem_exp , unchanging ) = RTX_FLAG ( original_mem_exp , unchanging ) ; RTX_FLAG ( new_mem_exp , volatil ) = RTX_FLAG ( original_mem_exp , volatil ) ; RTX_FLAG ( new_mem_exp , frame_related ) = RTX_FLAG ( original_mem_exp , frame_related ) ; RTX_FLAG ( new_mem_exp , in_struct ) = RTX_FLAG ( original_mem_exp , in_struct ) ; RTX_FLAG ( new_mem_exp , return_val ) = RTX_FLAG ( original_mem_exp , return_val ) ; struct mem_attrs original_attrs = * get_mem_attrs ( original_mem_exp ) ; alias_set_type set = original_attrs . alias ; set_mem_alias_set ( new_mem_exp , set ) ; addr_space_t addrspace = original_attrs . addrspace ; set_mem_addr_space ( new_mem_exp , addrspace ) ; unsigned int align = original_attrs . align ; set_mem_align ( new_mem_exp , align ) ; tree expr = original_attrs . expr ; set_mem_expr ( new_mem_exp , expr ) ; if ( original_attrs . offset_known_p ) { HOST_WIDE_INT offset = original_attrs . offset ; set_mem_offset ( new_mem_exp , offset ) ; } else clear_mem_offset ( new_mem_exp ) ; if ( original_attrs . size_known_p ) { HOST_WIDE_INT size = original_attrs . size ; set_mem_size ( new_mem_exp , size ) ; } else clear_mem_size ( new_mem_exp ) ; } </s>

Make NEW_MEM_EXP 's attributes and flags resemble those of ORIGINAL_MEM_EXP .


<s> void changeSection ( MCSection * Section , const MCExpr * Subsection ) override { LastMappingSymbols [ getCurrentSection ( ) . first ] = std :: move ( LastEMSInfo ) ; MCELFStreamer :: changeSection ( Section , Subsection ) ; auto LastMappingSymbol = LastMappingSymbols . find ( Section ) ; if ( LastMappingSymbol != LastMappingSymbols . end ( ) ) { LastEMSInfo = std :: move ( LastMappingSymbol -> second ) ; return ; } LastEMSInfo . reset ( new ElfMappingSymbolInfo ( SMLoc ( ) , nullptr , 0 ) ) ; } </s>

Update streamer for a new active section .


<s>
bool
PPCAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
true
;
case
'y'
:
{
const
char
*
RegName
=
"r0"
;
if
(
!
Subtarget
->
isDarwin
(
)
)
RegName
=
PPCRegisterInfo
::
stripRegisterPrefix
(
RegName
)
;
O
<<
RegName
<<
", "
;
printOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
case
'U'
:
case
'X'
:
{
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
return
false
;
}
}
}
assert
(
MI
->
getOperand
(
OpNo
)
.
isReg
(
)
)
;
O
<<
"0("
;
printOperand
(
MI
,
OpNo
,
O
)
;
O
<<
")"
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool SystemZTTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . SetupCost ) ; } </s>

Return true if LSR cost of C1 is lower than C2 .


" is allocatable: function has no frame pointer"

Return the register ID of the name passed in .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; case AArch64ISD :: NEON_BSL : return "AArch64ISD::NEON_BSL" ; case AArch64ISD :: NEON_MOVIMM : return "AArch64ISD::NEON_MOVIMM" ; case AArch64ISD :: NEON_MVNIMM : return "AArch64ISD::NEON_MVNIMM" ; case AArch64ISD :: NEON_FMOVIMM : return "AArch64ISD::NEON_FMOVIMM" ; case AArch64ISD :: NEON_CMP : return "AArch64ISD::NEON_CMP" ; case AArch64ISD :: NEON_CMPZ : return "AArch64ISD::NEON_CMPZ" ; case AArch64ISD :: NEON_TST : return "AArch64ISD::NEON_TST" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> int aarch64_branch_cost ( bool speed_p , bool predictable_p ) { const struct cpu_branch_cost * branch_costs = aarch64_tune_params . branch_costs ; if ( ! speed_p || predictable_p ) return branch_costs -> predictable ; else return branch_costs -> unpredictable ; } </s>

Return the cost of a branch . If SPEED_P is true then the compiler is optimizing for speed . If PREDICTABLE_P is true then the branch is predicted to be taken .


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = countPopulation ( I ) ; Pos = countTrailingZeros ( I ) ; return true ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


<s> bool Mips16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"\n\n// br.call targets referenced (and not defined) above: \n"

"\n\n// (external) symbols referenced (and not defined) above: \n"

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static int rs6000_compute_pressure_classes ( enum reg_class * pressure_classes ) { int n ; n = 0 ; pressure_classes [ n ++ ] = GENERAL_REGS ; if ( TARGET_ALTIVEC ) pressure_classes [ n ++ ] = ALTIVEC_REGS ; if ( TARGET_VSX ) pressure_classes [ n ++ ] = VSX_REGS ; else { if ( TARGET_HARD_FLOAT ) pressure_classes [ n ++ ] = FLOAT_REGS ; } pressure_classes [ n ++ ] = CR_REGS ; pressure_classes [ n ++ ] = SPECIAL_REGS ; return n ; } </s>

Compute register pressure classes . We implement the target hook to avoid IRA picking something like GEN_OR_FLOAT_REGS as a pressure class , which can lead to incorrect estimates of number of available registers and therefor increased register pressure/spill .


<s> static rtx iq2000_add_large_offset_to_sp ( HOST_WIDE_INT offset ) { rtx reg = gen_rtx_REG ( Pmode , IQ2000_TEMP2_REGNUM ) ; rtx offset_rtx = GEN_INT ( offset ) ; emit_move_insn ( reg , offset_rtx ) ; emit_insn ( gen_addsi3 ( reg , reg , stack_pointer_rtx ) ) ; return reg ; } </s>

Emit instructions to load the value ( SP + OFFSET ) into IQ2000_TEMP2_REGNUM and return an rtl expression for the register . Write the assembly instructions directly to FILE if it is not null , otherwise emit them as rtl . This function is a subroutine of save_restore_insns . It is used when OFFSET is too large to add in a single instruction .


<s> EVT X86TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { if ( Size >= 16 && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == 0 || DstAlign >= 16 ) && ( SrcAlign == 0 || SrcAlign >= 16 ) ) ) ) { if ( Size >= 32 ) { if ( Subtarget -> hasInt256 ( ) ) return MVT :: v8i32 ; if ( Subtarget -> hasFp256 ( ) ) return MVT :: v8f32 ; } if ( Subtarget -> hasSSE2 ( ) ) return MVT :: v4i32 ; if ( Subtarget -> hasSSE1 ( ) ) return MVT :: v4f32 ; } else if ( ! MemcpyStrSrc && Size >= 8 && ! Subtarget -> is64Bit ( ) && Subtarget -> hasSSE2 ( ) ) { return MVT :: f64 ; } } if ( Subtarget -> is64Bit ( ) && Size >= 8 ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void PPCAIXAsmPrinter :: SetupMachineFunction ( MachineFunction & MF ) { CurrentFnDescSym = getSymbol ( & MF . getFunction ( ) ) ; MCSectionXCOFF * FnDescSec = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForFunctionDescriptor ( CurrentFnDescSym ) ) ; cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> setContainingCsect ( FnDescSec ) ; return AsmPrinter :: SetupMachineFunction ( MF ) ; } </s>

This should be called when a new MachineFunction is being processed from runOnMachineFunction .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperLarge : return "AArch64ISD::WrapperLarge" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; default : return NULL ; } } </s>


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return PerformOrCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: MEMBARRIER : return PerformMEMBARRIERCombine ( N , DAG ) ; case ISD :: ZERO_EXTEND : return PerformZExtCombine ( N , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool enableEarlyIfConversion ( ) const override { return true ; } </s>

Enable the use of the early if conversion pass .


<s> bool aarch64_sve_vector_inc_dec_immediate_p ( rtx x ) { return aarch64_sve_vector_inc_dec_immediate_p ( x , NULL , NULL ) ; } </s>

Return true if X is a valid immediate for an SVE vector INC or DEC instruction .


<s> virtual const MipsRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool AArch64TargetLowering :: isExtFreeImpl ( const Instruction * Ext ) const { if ( isa < FPExtInst > ( Ext ) ) return false ; if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( 1 ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; std :: advance ( GTI , U . getOperandNo ( ) ) ; Type * IdxTy = * GTI ; uint64_t ShiftAmt = countTrailingZeros ( getDataLayout ( ) -> getTypeStoreSizeInBits ( IdxTy ) ) - 3 ; if ( ShiftAmt == 0 || ShiftAmt > 4 ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( 0 ) -> getType ( ) ) continue ; default : return false ; } } return true ; } </s>

Return true if the extension represented by I is free .


<s> ScheduleHazardRecognizer * PPCInstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_440 ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new PPCHazardRecognizer440 ( II , DAG ) ; } return TargetInstrInfoImpl :: CreateTargetHazardRecognizer ( TM , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> static ARMOperand * CreateMem ( unsigned BaseRegNum , const MCConstantExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E , SMLoc AlignmentLoc = SMLoc ( ) ) { ARMOperand * Op = new ARMOperand ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ; } </s>


<s> void x86_emit_floatuns ( rtx operands [ 2 ] ) { rtx neglab , donelab , i0 , i1 , f0 , in , out ; enum machine_mode mode , inmode ; inmode = GET_MODE ( operands [ 1 ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ 0 ] ; in = force_reg ( inmode , operands [ 1 ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; i1 = gen_reg_rtx ( Pmode ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , Pmode , 0 , neglab ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_FLOAT ( mode , in ) ) ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( Pmode , LSHIFTRT , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( Pmode , AND , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( Pmode , IOR , i0 , i1 , i0 , 1 , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , 0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode/SImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


<s> void ix86_expand_round_sse4 ( rtx op0 , rtx op1 ) { machine_mode mode = GET_MODE ( op0 ) ; rtx e1 , e2 , res , half ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; rtx ( * gen_copysign ) ( rtx , rtx , rtx ) ; rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; half = const_double_from_real_value ( pred_half , mode ) ; e1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_copysign ( e1 , half , op1 ) ) ; e2 = expand_simple_binop ( mode , PLUS , op1 , e1 , NULL_RTX , 0 , OPTAB_DIRECT ) ; res = gen_reg_rtx ( mode ) ; emit_insn ( gen_round ( res , e2 , GEN_INT ( ROUND_TRUNC ) ) ) ; emit_move_insn ( op0 , res ) ; } </s>

Expand SSE sequence for computing round from OP1 storing into OP0 using sse4 round insn .


<s> bool ARMTargetLowering :: SimplifyDemandedBitsForTargetNode ( SDValue Op , const APInt & OriginalDemandedBits , const APInt & OriginalDemandedElts , KnownBits & Known , TargetLoweringOpt & TLO , unsigned Depth ) const { unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case ARMISD :: ASRL : case ARMISD :: LSRL : { if ( Op . getResNo ( ) == 0 && ! Op -> hasAnyUseOfValue ( 1 ) && isa < ConstantSDNode > ( Op -> getOperand ( 2 ) ) ) { unsigned ShAmt = Op -> getConstantOperandVal ( 2 ) ; if ( ShAmt < 32 && OriginalDemandedBits . isSubsetOf ( APInt :: getAllOnes ( 32 ) << ( 32 - ShAmt ) ) ) return TLO . CombineTo ( Op , TLO . DAG . getNode ( ISD :: SHL , SDLoc ( Op ) , MVT :: i32 , Op . getOperand ( 1 ) , TLO . DAG . getConstant ( 32 - ShAmt , SDLoc ( Op ) , MVT :: i32 ) ) ) ; } break ; } } return TargetLowering :: SimplifyDemandedBitsForTargetNode ( Op , OriginalDemandedBits , OriginalDemandedElts , Known , TLO , Depth ) ; } </s>

Attempt to simplify any target nodes based on the demanded bits/elts , returning true on success .


<s> tree loongarch_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( loongarch_builtins ) ) return error_mark_node ; return loongarch_builtin_decls [ code ] ; } </s>


<s>
void
PPCMIPeephole
::
initialize
(
MachineFunction
&
MFParm
)
{
MF
=
&
MFParm
;
MRI
=
&
MF
->
getRegInfo
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
TII
=
MF
->
getSubtarget
<
PPCSubtarget
>
(
)
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** PowerPC MI peephole pass ***\n\n"
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
}
</s>

Initialize the strategy after building the DAG for a new region .

PowerPC
PPC
PPC
"*** PowerPC MI peephole pass ***\n\n"


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s>
std
::
string
str
(
)
const
{
std
::
string
S
;
raw_string_ostream
OS
(
S
)
;
OS
<<
"{"
;
StartInst
->
print
(
OS
,
true
)
;
OS
<<
" -> "
;
LastInst
->
print
(
OS
,
true
)
;
if
(
KillInst
)
{
OS
<<
" (kill @ "
;
KillInst
->
print
(
OS
,
true
)
;
OS
<<
")"
;
}
OS
<<
"}"
;
return
OS
.
str
(
)
;
}
</s>

Return the twine contents as a std : :string .


<s> static void do_load_for_compare_from_addr ( machine_mode mode , rtx dest , rtx addr , rtx orig_addr ) { rtx mem = gen_rtx_MEM ( mode , addr ) ; MEM_COPY_ATTRIBUTES ( mem , orig_addr ) ; set_mem_size ( mem , GET_MODE_SIZE ( mode ) ) ; do_load_for_compare ( dest , mem , mode ) ; return ; } </s>

Prepare address and then do a load . MODE is the mode to use for the load . DEST is the destination register for the data . ADDR is the address to be loaded . ORIG_ADDR is the original address expression .


<s>
bool
X86InstrInfo
::
expandPostRAPseudo
(
MachineBasicBlock
::
iterator
MI
)
const
{
bool
HasAVX
=
Subtarget
.
hasAVX
(
)
;
MachineInstrBuilder
MIB
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
XOR32rr
)
)
;
case
X86
::
MOV32r1
:
return
expandMOV32r1
(
MIB
,
*
this
,
false
)
;
case
X86
::
MOV32r_1
:
return
expandMOV32r1
(
MIB
,
*
this
,
true
)
;
case
X86
::
MOV32ImmSExti8
:
case
X86
::
MOV64ImmSExti8
:
return
ExpandMOVImmSExti8
(
MIB
)
;
case
X86
::
SETB_C8r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB8rr
)
)
;
case
X86
::
SETB_C16r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB16rr
)
)
;
case
X86
::
SETB_C32r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB32rr
)
)
;
case
X86
::
SETB_C64r
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
SBB64rr
)
)
;
case
X86
::
V_SET0
:
case
X86
::
FsFLD0SS
:
case
X86
::
FsFLD0SD
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VXORPSrr
:
X86
::
XORPSrr
)
)
;
case
X86
::
AVX_SET0
:
assert
(
HasAVX
&&
"AVX not supported"
)
;
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VXORPSYrr
)
)
;
case
X86
::
AVX512_512_SET0
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPXORDZrr
)
)
;
case
X86
::
V_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
HasAVX
X86
::
VPCMPEQDrr
:
X86
::
PCMPEQDrr
)
)
;
case
X86
::
AVX2_SETALLONES
:
return
Expand2AddrUndef
(
MIB
,
get
(
X86
::
VPCMPEQDYrr
)
)
;
case
X86
::
TEST8ri_NOREX
:
MI
->
setDesc
(
get
(
X86
::
TEST8ri
)
)
;
return
true
;
case
X86
::
KSET0B
:
case
X86
::
KSET0W
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORWrr
)
,
X86
::
K0
)
;
case
X86
::
KSET0D
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORDrr
)
,
X86
::
K0
)
;
case
X86
::
KSET0Q
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXORQrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1B
:
case
X86
::
KSET1W
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORWrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1D
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORDrr
)
,
X86
::
K0
)
;
case
X86
::
KSET1Q
:
return
Expand2AddrKreg
(
MIB
,
get
(
X86
::
KXNORQrr
)
,
X86
::
K0
)
;
case
TargetOpcode
::
LOAD_STACK_GUARD
:
expandLoadStackGuard
(
MIB
,
*
this
)
;
return
true
;
}
return
false
;
}
</s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void Cpu0FrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const { } </s>


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
if
(
!
IsVarArg
)
return
CC_AArch64_DarwinPCS
;
return
Subtarget
->
isTargetILP32
(
)
CC_AArch64_DarwinPCS_ILP32_VarArg
:
CC_AArch64_DarwinPCS_VarArg
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
CFGuard_Check
:
return
CC_AArch64_Win64_CFGuard_Check
;
case
CallingConv
::
AArch64_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> inline void count_registers ( const_tree field , int bitpos , bool fp , assign_data_t * data ) { if ( fp ) { int nregs ; machine_mode mode ; if ( compute_int_layout ( bitpos , data , & nregs ) ) data -> nregs += nregs ; if ( compute_fp_layout ( field , bitpos , data , & nregs , & mode ) ) data -> nregs += nregs ; } else { if ( data -> intoffset < 0 ) data -> intoffset = bitpos ; } } </s>

A subroutine of function_arg_record_value . Count the number of registers to be assigned for FIELD and between PARMS- > intoffset and BITPOS .


<s> void emitBytes ( const uint8_t * Opcode , size_t Size ) { Ops . insert ( Ops . end ( ) , Opcode , Opcode + Size ) ; OpBegins . push_back ( OpBegins . back ( ) + Size ) ; } </s>

Emit the bytes in Data into the output .


<s> static void arm_print_value ( FILE * f , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; return ; case CONST_DOUBLE : fprintf ( f , "<0x%lx,0x%lx>" , ( long ) XWINT ( x , 2 ) , ( long ) XWINT ( x , 3 ) ) ; return ; case CONST_VECTOR : { int i ; fprintf ( f , "<" ) ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( CONST_VECTOR_ELT ( x , i ) ) ) ; if ( i < ( CONST_VECTOR_NUNITS ( x ) - 1 ) ) fputc ( ',' , f ) ; } fprintf ( f , ">" ) ; } return ; case CONST_STRING : fprintf ( f , "\"%s\"" , XSTR ( x , 0 ) ) ; return ; case SYMBOL_REF : fprintf ( f , "`%s'" , XSTR ( x , 0 ) ) ; return ; case LABEL_REF : fprintf ( f , "L%d" , INSN_UID ( XEXP ( x , 0 ) ) ) ; return ; case CONST : arm_print_value ( f , XEXP ( x , 0 ) ) ; return ; case PLUS : arm_print_value ( f , XEXP ( x , 0 ) ) ; fprintf ( f , "+" ) ; arm_print_value ( f , XEXP ( x , 1 ) ) ; return ; case PC : fprintf ( f , "pc" ) ; return ; default : fprintf ( f , "????" ) ; return ; } } </s>

Print a symbolic form of X to the debug file , F .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( ! MF . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> static rtx aarch64_move_pointer ( rtx pointer , poly_int64 amount ) { rtx next = plus_constant ( Pmode , XEXP ( pointer , 0 ) , amount ) ; return adjust_automodify_address ( pointer , GET_MODE ( pointer ) , next , amount ) ; } </s>

Return a new RTX holding the result of moving POINTER forward by AMOUNT bytes .


<s>
void
SystemZTargetLowering
::
LowerOperationWrapper
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ATOMIC_LOAD
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_LOAD_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
break
;
}
case
ISD
::
ATOMIC_STORE
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_STORE_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
if
(
cast
<
AtomicSDNode
>
(
N
)
->
getSuccessOrdering
(
)
==
AtomicOrdering
::
SequentiallyConsistent
)
Res
=
SDValue
(
DAG
.
getMachineNode
(
SystemZ
::
Serialize
,
DL
,
MVT
::
Other
,
Res
)
,
0
)
;
Results
.
push_back
(
Res
)
;
break
;
}
case
ISD
::
ATOMIC_CMP_SWAP_WITH_SUCCESS
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
i32
,
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
3
)
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_CMP_SWAP_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
SDValue
Success
=
emitSETCC
(
DAG
,
DL
,
Res
.
getValue
(
1
)
,
SystemZ
::
CCMASK_CS
,
SystemZ
::
CCMASK_CS_EQ
)
;
Success
=
DAG
.
getZExtOrTrunc
(
Success
,
DL
,
N
->
getValueType
(
1
)
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Success
)
;
Results
.
push_back
(
Res
.
getValue
(
2
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> StackOffset SystemZFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { StackOffset Offset = TargetFrameLowering :: getFrameIndexReference ( MF , FI , FrameReg ) ; return Offset + StackOffset :: getFixed ( SystemZMC :: ELFCallFrameSize ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> int X86TTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> int sparc_initial_elimination_offset ( int to ) { int offset ; if ( to == STACK_POINTER_REGNUM ) offset = sparc_compute_frame_size ( get_frame_size ( ) , crtl -> is_leaf ) ; else offset = 0 ; offset += SPARC_STACK_BIAS ; return offset ; } </s>

Implement the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s> static void fixup_errata ( ) { rtx insn ; if ( ! TARGET_B_STEP ) return ; group_idx = 0 ; memset ( last_group , 0 , sizeof last_group ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ; if ( ia64_safe_type ( insn ) == TYPE_S ) { group_idx ^= 1 ; memset ( last_group + group_idx , 0 , sizeof last_group [ group_idx ] ) ; } else errata_emit_nops ( insn ) ; } } </s>

Emit extra nops if they are required to work around hardware errata .


<s>
void
X86InstrInfo
::
reMaterialize
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
unsigned
SubIdx
,
const
MachineInstr
&
Orig
,
const
TargetRegisterInfo
&
TRI
)
const
{
bool
ClobbersEFLAGS
=
false
;
for
(
const
MachineOperand
&
MO
:
Orig
.
operands
(
)
)
{
if
(
MO
.
isReg
(
)
&&
MO
.
isDef
(
)
&&
MO
.
getReg
(
)
==
X86
::
EFLAGS
)
{
ClobbersEFLAGS
=
true
;
break
;
}
}
if
(
ClobbersEFLAGS
&&
!
isSafeToClobberEFLAGS
(
MBB
,
I
)
)
{
int
Value
;
switch
(
Orig
.
getOpcode
(
)
)
{
case
X86
::
MOV32r0
:
Value
=
0
;
break
;
case
X86
::
MOV32r1
:
Value
=
1
;
break
;
case
X86
::
MOV32r_1
:
Value
=
1
;
break
;
default
:
llvm_unreachable
(
"Unexpected instruction!"
)
;
}
const
DebugLoc
&
DL
=
Orig
.
getDebugLoc
(
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
X86
::
MOV32ri
)
)
.
addOperand
(
Orig
.
getOperand
(
0
)
)
.
addImm
(
Value
)
;
}
else
{
MachineInstr
*
MI
=
MBB
.
getParent
(
)
->
CloneMachineInstr
(
&
Orig
)
;
MBB
.
insert
(
I
,
MI
)
;
}
MachineInstr
&
NewMI
=
*
std
::
prev
(
I
)
;
NewMI
.
substituteRegister
(
Orig
.
getOperand
(
0
)
.
getReg
(
)
,
DestReg
,
SubIdx
,
TRI
)
;
}
</s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s> unsigned MipsRegisterInfo :: getRARegister ( ) const { return Mips :: RA ; } </s>

This method should return the register where the return address can be found .


<s> static bool rs6000_builtin_valid_without_lhs ( enum rs6000_builtins fn_code ) { switch ( fn_code ) { case ALTIVEC_BUILTIN_STVX_V16QI : case ALTIVEC_BUILTIN_STVX_V8HI : case ALTIVEC_BUILTIN_STVX_V4SI : case ALTIVEC_BUILTIN_STVX_V4SF : case ALTIVEC_BUILTIN_STVX_V2DI : case ALTIVEC_BUILTIN_STVX_V2DF : return true ; default : return false ; } } </s>

Helper function to sort out which built-ins may be valid without having a LHS .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Dead register definitions"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned FPGATTIImpl :: getNumberOfRegisters ( bool Vector ) { return std :: numeric_limits < unsigned > :: max ( ) >> 2 ; } </s>


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static bool ix86_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; unsigned HOST_WIDE_INT always_inline_safe_mask = ( MASK_USE_8BIT_IDIV | MASK_ACCUMULATE_OUTGOING_ARGS | MASK_NO_ALIGN_STRINGOPS | MASK_AVX256_SPLIT_UNALIGNED_LOAD | MASK_AVX256_SPLIT_UNALIGNED_STORE | MASK_CLD | MASK_NO_FANCY_MATH_387 | MASK_IEEE_FP | MASK_INLINE_ALL_STRINGOPS | MASK_INLINE_STRINGOPS_DYNAMICALLY | MASK_RECIP | MASK_STACK_PROBE | MASK_STV | MASK_TLS_DIRECT_SEG_REFS | MASK_VZEROUPPER | MASK_NO_PUSH_ARGS | MASK_OMIT_LEAF_FRAME_POINTER ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; if ( ! caller_tree ) caller_tree = target_option_default_node ; if ( callee_tree == caller_tree ) return true ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ) ; bool ret = false ; bool always_inline = ( DECL_DISREGARD_INLINE_LIMITS ( callee ) && lookup_attribute ( "always_inline" , DECL_ATTRIBUTES ( callee ) ) ) ; if ( TARGET_GENERAL_REGS_ONLY_P ( callee_opts -> x_ix86_target_flags ) ) always_inline_safe_mask |= MASK_80387 ; cgraph_node * callee_node = cgraph_node :: get ( callee ) ; if ( ( ( caller_opts -> x_ix86_isa_flags & callee_opts -> x_ix86_isa_flags ) != callee_opts -> x_ix86_isa_flags ) || ( ( caller_opts -> x_ix86_isa_flags2 & callee_opts -> x_ix86_isa_flags2 ) != callee_opts -> x_ix86_isa_flags2 ) ) ret = false ; else if ( ( ! always_inline && caller_opts -> x_target_flags != callee_opts -> x_target_flags ) || ( caller_opts -> x_target_flags & ~ always_inline_safe_mask ) != ( callee_opts -> x_target_flags & ~ always_inline_safe_mask ) ) ret = false ; else if ( caller_opts -> arch != callee_opts -> arch ) ret = false ; else if ( ! always_inline && caller_opts -> tune != callee_opts -> tune ) ret = false ; else if ( caller_opts -> x_ix86_fpmath != callee_opts -> x_ix86_fpmath && ( ! ipa_fn_summaries || ipa_fn_summaries -> get ( callee_node ) == NULL || ipa_fn_summaries -> get ( callee_node ) -> fp_expressions ) ) ret = false ; else if ( ! always_inline && caller_opts -> branch_cost != callee_opts -> branch_cost ) ret = false ; else ret = true ; return ret ; } </s>

Hook to determine if one function can safely inline another .


<s> unsigned CAHPInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : return get ( Opcode ) . getSize ( ) ; case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const auto & TM = static_cast < const CAHPTargetMachine & > ( MF . getTarget ( ) ) ; return getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool ARMBaseInstrInfo :: hasLowDefLatency ( const InstrItineraryData * ItinData , const MachineInstr * DefMI , unsigned DefIdx ) const { if ( ! ItinData || ItinData -> isEmpty ( ) ) return false ; unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( DDomain == ARMII :: DomainGeneral ) { unsigned DefClass = DefMI -> getDesc ( ) . getSchedClass ( ) ; int DefCycle = ItinData -> getOperandCycle ( DefClass , DefIdx ) ; return ( DefCycle != - 1 && DefCycle <= 2 ) ; } return false ; } </s>

Compute operand latency of a def of 'Reg ' .

ARM ARM ARMII::DomainMask ARMII::DomainGeneral 1 2


<s> static bool cortexa7_older_only ( rtx_insn * insn ) { if ( recog_memoized ( insn ) < 0 ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_ALU_DSP_REG : case TYPE_ALU_SREG : case TYPE_ALUS_SREG : case TYPE_LOGIC_REG : case TYPE_LOGICS_REG : case TYPE_ADC_REG : case TYPE_ADCS_REG : case TYPE_ADR : case TYPE_BFM : case TYPE_REV : case TYPE_MVN_REG : case TYPE_SHIFT_IMM : case TYPE_SHIFT_REG : case TYPE_LOAD_BYTE : case TYPE_LOAD_4 : case TYPE_STORE_4 : case TYPE_FFARITHS : case TYPE_FADDS : case TYPE_FFARITHD : case TYPE_FADDD : case TYPE_FMOV : case TYPE_F_CVT : case TYPE_FCMPS : case TYPE_FCMPD : case TYPE_FCONSTS : case TYPE_FCONSTD : case TYPE_FMULS : case TYPE_FMACS : case TYPE_FMULD : case TYPE_FMACD : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_F_MRC : case TYPE_F_MRRC : case TYPE_F_FLAG : case TYPE_F_LOADS : case TYPE_F_STORES : return true ; default : return false ; } } </s>

Return true if and only if this insn can dual-issue only as older .


<s> void rs6000_scale_v2df ( rtx tgt , rtx src , int scale ) { HOST_WIDE_INT hwi_scale ( scale ) ; REAL_VALUE_TYPE r_pow ; rtvec v = rtvec_alloc ( 2 ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = const_double_from_real_value ( r_pow , DFmode ) ; RTVEC_ELT ( v , 0 ) = elt ; RTVEC_ELT ( v , 1 ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt , src , scale_vec ) ) ; } </s>

Scale a V2DF vector SRC by two to the SCALE and place in TGT .


<s> unsigned char AArch64Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ) isDecl = true ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return AArch64II :: MO_GOT ; if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) { if ( TM . getRelocationModel ( ) == Reloc :: Static ) return AArch64II :: MO_CONSTPOOL ; else return AArch64II :: MO_GOT ; } if ( TM . getRelocationModel ( ) != Reloc :: Static && GV -> hasDefaultVisibility ( ) ) { if ( isTargetMachO ( ) ) return ( isDecl || GV -> isWeakForLinker ( ) ) ? AArch64II :: MO_GOT : AArch64II :: MO_NO_FLAG ; else return GV -> hasLocalLinkage ( ) ? AArch64II :: MO_NO_FLAG : AArch64II :: MO_GOT ; } return AArch64II :: MO_NO_FLAG ; } </s>

ClassifyGlobalReference - Find the target operand flags that describe how a global value should be referenced for the current subtarget .


<s> const char * iq2000_fill_delay_slot ( const char * ret , enum delay_type type , rtx operands [ ] , rtx_insn * cur_insn ) { rtx set_reg ; machine_mode mode ; rtx_insn * next_insn = cur_insn ? NEXT_INSN ( cur_insn ) : NULL ; int num_nops ; if ( type == DELAY_LOAD || type == DELAY_FCMP ) num_nops = 1 ; else num_nops = 0 ; next_insn = NEXT_INSN ( cur_insn ) ; while ( next_insn != 0 && ( NOTE_P ( next_insn ) || LABEL_P ( next_insn ) ) ) next_insn = NEXT_INSN ( next_insn ) ; dslots_load_total += num_nops ; if ( TARGET_DEBUG_C_MODE || type == DELAY_NONE || operands == 0 || cur_insn == 0 || next_insn == 0 || LABEL_P ( next_insn ) || ( set_reg = operands [ 0 ] ) == 0 ) { dslots_number_nops = 0 ; iq2000_load_reg = 0 ; iq2000_load_reg2 = 0 ; iq2000_load_reg3 = 0 ; iq2000_load_reg4 = 0 ; return ret ; } set_reg = operands [ 0 ] ; if ( set_reg == 0 ) return ret ; while ( GET_CODE ( set_reg ) == SUBREG ) set_reg = SUBREG_REG ( set_reg ) ; mode = GET_MODE ( set_reg ) ; dslots_number_nops = num_nops ; iq2000_load_reg = set_reg ; if ( GET_MODE_SIZE ( mode ) > ( unsigned ) ( UNITS_PER_WORD ) ) iq2000_load_reg2 = gen_rtx_REG ( SImode , REGNO ( set_reg ) + 1 ) ; else iq2000_load_reg2 = 0 ; return ret ; } </s>

Returns an operand string for the given instruction 's delay slot , after updating filled delay slot statistics . We assume that operands [ 0 ] is the target register that is set . In order to check the next insn , most of this functionality is moved to FINAL_PRESCAN_INSN , and we just set the global variables that it needs .


<s> static rtx legitimize_tls_address ( rtx addr ) { rtx ret , tmp , t1 , t2 , tp ; rtx_insn * insn ; if ( GET_CODE ( addr ) != SYMBOL_REF ) return addr ; switch ( SYMBOL_REF_TLS_MODEL ( addr ) ) { case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_reg_rtx ( Pmode ) ; if ( flag_pic ) emit_insn ( gen_tgd_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tgd_load ( tmp , addr ) ) ; ret = hppa_tls_call ( tmp ) ; break ; case TLS_MODEL_LOCAL_DYNAMIC : ret = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( Pmode ) ; start_sequence ( ) ; if ( flag_pic ) emit_insn ( gen_tld_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tld_load ( tmp , addr ) ) ; t1 = hppa_tls_call ( tmp ) ; insn = get_insns ( ) ; end_sequence ( ) ; t2 = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insn , t2 , t1 , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_TLSLDBASE ) ) ; emit_insn ( gen_tld_offset_load ( ret , addr , t2 ) ) ; break ; case TLS_MODEL_INITIAL_EXEC : tp = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( Pmode ) ; ret = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tp_load ( tp ) ) ; if ( flag_pic ) emit_insn ( gen_tie_load_pic ( tmp , addr ) ) ; else emit_insn ( gen_tie_load ( tmp , addr ) ) ; emit_move_insn ( ret , gen_rtx_PLUS ( Pmode , tp , tmp ) ) ; break ; case TLS_MODEL_LOCAL_EXEC : tp = gen_reg_rtx ( Pmode ) ; ret = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tp_load ( tp ) ) ; emit_insn ( gen_tle_load ( ret , addr , tp ) ) ; break ; default : gcc_unreachable ( ) ; } return ret ; } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> bool PPCTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createPPCISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void AArch64AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MCInst TmpInst ; LowerAArch64MachineInstrToMCInst ( MI , TmpInst , * this ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> const char * standard_80387_constant_opcode ( rtx x ) { switch ( standard_80387_constant_p ( x ) ) { case 1 : return "fldz" ; case 2 : return "fld1" ; case 3 : return "fldlg2" ; case 4 : return "fldln2" ; case 5 : return "fldl2e" ; case 6 : return "fldl2t" ; case 7 : return "fldpi" ; default : gcc_unreachable ( ) ; } } </s>

Return the opcode of the special instruction to be used to load the constant X .


<s> static bool noncall_uses_reg ( rtx reg , rtx_insn * insn , rtx * set ) { * set = NULL_RTX ; rtx reg2 = sfunc_uses_reg ( insn ) ; if ( reg2 && REGNO ( reg2 ) == REGNO ( reg ) ) { rtx pattern = single_set ( insn ) ; if ( pattern && REG_P ( SET_DEST ( pattern ) ) && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) * set = pattern ; return false ; } if ( ! CALL_P ( insn ) ) { rtx pattern = single_set ( insn ) ; if ( pattern && REG_P ( SET_DEST ( pattern ) ) && REGNO ( reg ) == REGNO ( SET_DEST ( pattern ) ) ) { rtx par , part ; int i ; * set = pattern ; par = PATTERN ( insn ) ; if ( GET_CODE ( par ) == PARALLEL ) for ( i = XVECLEN ( par , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( par , 0 , i ) ; if ( GET_CODE ( part ) != SET && reg_mentioned_p ( reg , part ) ) return true ; } return reg_mentioned_p ( reg , SET_SRC ( pattern ) ) ; } return true ; } rtx pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) { for ( int i = XVECLEN ( pattern , 0 ) - 1 ; i >= 1 ; i -- ) if ( reg_mentioned_p ( reg , XVECEXP ( pattern , 0 , i ) ) ) return true ; pattern = XVECEXP ( pattern , 0 , 0 ) ; } if ( GET_CODE ( pattern ) == SET ) { if ( reg_mentioned_p ( reg , SET_DEST ( pattern ) ) ) { if ( ! REG_P ( SET_DEST ( pattern ) ) || REGNO ( reg ) != REGNO ( SET_DEST ( pattern ) ) ) return true ; * set = pattern ; } pattern = SET_SRC ( pattern ) ; } if ( GET_CODE ( pattern ) != CALL || ! MEM_P ( XEXP ( pattern , 0 ) ) || ! rtx_equal_p ( reg , XEXP ( XEXP ( pattern , 0 ) , 0 ) ) ) return true ; return false ; } </s>

See if the only way in which INSN uses REG is by calling it , or by setting it while calling it . Set * SET to a SET rtx if the register is set by INSN .


<s> bool ARMBaseTargetMachine :: addPreRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None && ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ExpandMLx && OptLevel != CodeGenOpt :: None && Subtarget . hasVFP2 ( ) ) PM . add ( createMLxExpansionPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> void arm_order_regs_for_local_alloc ( void ) { const int arm_reg_alloc_order [ ] = REG_ALLOC_ORDER ; memcpy ( reg_alloc_order , arm_reg_alloc_order , sizeof ( reg_alloc_order ) ) ; if ( TARGET_THUMB ) memcpy ( reg_alloc_order , thumb_core_reg_alloc_order , sizeof ( thumb_core_reg_alloc_order ) ) ; } </s>

Adjust register allocation order when compiling for Thumb .


<s> bool ix86_function_value_regno_p ( int regno ) { if ( regno == 0 || ( regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387 ) || ( regno == FIRST_SSE_REG && TARGET_SSE ) ) return true ; if ( ! TARGET_64BIT && ( regno == FIRST_MMX_REG && TARGET_MMX ) ) return true ; return false ; } </s>

Return true if N is a possible register number of function value .


<s> uint32_t ARMMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( isThumb2 ( STI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , ARM :: fixup_t2_condbranch , Fixups , STI ) ; return getARMBranchTargetOpValue ( MI , OpIdx , Fixups , STI ) ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> static void ix86_adjust_counter ( rtx countreg , HOST_WIDE_INT value ) { emit_insn ( gen_add2_insn ( countreg , GEN_INT ( - value ) ) ) ; } </s>


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x , cc_reg ; machine_mode mode , r_mode ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; r_mode = mode ; if ( mode == QImode || mode == HImode ) { r_mode = SImode ; rval = gen_reg_rtx ( r_mode ) ; } if ( TARGET_LSE ) { if ( reg_overlap_mentioned_p ( rval , oldval ) ) rval = copy_to_mode_reg ( r_mode , oldval ) ; else emit_move_insn ( rval , gen_lowpart ( r_mode , oldval ) ) ; emit_insn ( gen_aarch64_compare_and_swap_lse ( mode , rval , mem , newval , mod_s ) ) ; cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; } else if ( TARGET_OUTLINE_ATOMICS ) { if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; rtx func = aarch64_atomic_ool_func ( mode , mod_s , & aarch64_ool_cas_names ) ; rval = emit_library_call_value ( func , NULL_RTX , LCT_NORMAL , r_mode , oldval , mode , newval , mode , XEXP ( mem , 0 ) , Pmode ) ; cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; } else { insn_code code = code_for_aarch64_compare_and_swap ( mode ) ; if ( ! insn_data [ code ] . operand [ 2 ] . predicate ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; emit_insn ( GEN_FCN ( code ) ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; cc_reg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; } if ( r_mode != mode ) rval = gen_lowpart ( mode , rval ) ; emit_move_insn ( operands [ 1 ] , rval ) ; x = gen_rtx_EQ ( SImode , cc_reg , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } </s>


<s>
unsigned
SystemZRegisterInfo
::
getFrameRegister
(
MachineFunction
&
MF
)
const
{
assert
(
0
&&
"What is the frame register"
)
;
return
0
;
}
</s>


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> virtual bool isProfitableToUnpredicate ( MachineBasicBlock & TMBB , MachineBasicBlock & FMBB ) const { return false ; } </s>

Return true if it 's profitable to unpredicate one side of a 'diamond ' , i.e .


<s> static bool aarch64_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; if ( sel . ninputs ( ) == 1 || ( op0 && rtx_equal_p ( op0 , op1 ) ) ) d . one_vector_p = true ; else if ( sel . all_from_input_p ( 0 ) ) { d . one_vector_p = true ; op1 = op0 ; } else if ( sel . all_from_input_p ( 1 ) ) { d . one_vector_p = true ; op0 = op1 ; } else d . one_vector_p = false ; d . perm . new_vector ( sel . encoding ( ) , d . one_vector_p ? 1 : 2 , sel . nelts_per_input ( ) ) ; d . vmode = vmode ; d . vec_flags = aarch64_classify_vector_mode ( d . vmode ) ; d . target = target ; d . op0 = op0 ; d . op1 = op1 ; d . testing_p = ! target ; if ( ! d . testing_p ) return aarch64_expand_vec_perm_const_1 ( & d ) ; rtx_insn * last = get_last_insn ( ) ; bool ret = aarch64_expand_vec_perm_const_1 ( & d ) ; gcc_assert ( last == get_last_insn ( ) ) ; return ret ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; X86MachineFunctionInfo * MFI = MF . getInfo < X86MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>

runOnMachineFunction - Emit the function body .


"%qE attribute only applies to functions"

Check `` fast_interrupt '' , `` interrupt '' and `` naked '' attributes .


<s> rtx standard_80387_constant_rtx ( int idx ) { int i ; if ( ! ext_80387_constants_init ) init_ext_80387_constants ( ) ; switch ( idx ) { case 3 : case 4 : case 5 : case 6 : case 7 : i = idx - 3 ; break ; default : gcc_unreachable ( ) ; } return const_double_from_real_value ( ext_80387_constants_table [ i ] , XFmode ) ; } </s>

Return the CONST_DOUBLE representing the 80387 constant that is loaded by the specified special instruction . The argument IDX matches the return value from standard_80387_constant_p .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static int loongarch_binary_cost ( rtx x , int single_cost , int double_cost , bool speed ) { int cost ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * 2 ) cost = double_cost ; else cost = single_cost ; return ( cost + set_src_cost ( XEXP ( x , 0 ) , GET_MODE ( x ) , speed ) + rtx_cost ( XEXP ( x , 1 ) , GET_MODE ( x ) , GET_CODE ( x ) , 1 , speed ) ) ; } </s>

Return the cost of binary operation X , given that the instruction sequence for a word-sized or smaller operation has cost SINGLE_COST and that the sequence of a double-word operation has cost DOUBLE_COST . If SPEED is true , optimize for speed otherwise optimize for size .


<s> uint64_t getReturnSaveOffset ( ) const { return ReturnSaveOffset ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> bool AArch64AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { if ( ! parseAuthExpr ( Res , EndLoc ) ) return false ; return getParser ( ) . parsePrimaryExpr ( Res , EndLoc ) ; } </s>


<s> bool runOnModule ( Module & M ) override { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; if ( skipModule ( M ) ) return false ; bool Changed = false ; PromotionCacheTy PromotionCache ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF , PromotionCache ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static int mips_binary_cost ( rtx x , int single_cost , int double_cost , bool speed ) { int cost ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * 2 ) cost = double_cost ; else cost = single_cost ; return ( cost + set_src_cost ( XEXP ( x , 0 ) , speed ) + rtx_cost ( XEXP ( x , 1 ) , GET_CODE ( x ) , 1 , speed ) ) ; } </s>


<s> static inline bool offset_below_red_zone_p ( HOST_WIDE_INT offset ) { return offset < ( DEFAULT_ABI == ABI_V4 ? 0 : TARGET_32BIT ? - 220 : - 288 ) ; } </s>

Return true if OFFSET from stack pointer can be clobbered by signals . V.4 does n't have any stack cushion , AIX ABIs have 220 or 288 bytes below stack pointer not cloberred by signals .


<s> static int rs6000_psave_function_arg ( machine_mode mode , const_tree type , int align_words , rtx * rvec ) { int k = 0 ; if ( align_words < GP_ARG_NUM_REG ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG || mode == BLKmode || ( TARGET_32BIT && TARGET_POWERPC64 ) ) { machine_mode rmode = TARGET_32BIT ? SImode : DImode ; int i = 0 ; if ( align_words + n_words > GP_ARG_NUM_REG ) { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } do { rtx r = gen_rtx_REG ( rmode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * GET_MODE_SIZE ( rmode ) ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_words != 0 ) ; } else { rtx r = gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , const0_rtx ) ; } } else { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } return k ; } </s>

We have an argument of MODE and TYPE that goes into FPRs or VRs , but must also be copied into the parameter save area starting at offset ALIGN_WORDS . Fill in RVEC with the elements corresponding to the GPRs and/or memory . Return the number of elements used .


<s> static int ia32_multipass_dfa_lookahead ( void ) { switch ( ix86_tune ) { case PROCESSOR_PENTIUM : return 2 ; case PROCESSOR_PENTIUMPRO : case PROCESSOR_K6 : return 1 ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : return 4 ; case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_BONNELL : case PROCESSOR_SILVERMONT : case PROCESSOR_KNL : case PROCESSOR_INTEL : if ( reload_completed ) return ix86_issue_rate ( ) ; return 0 ; default : return 0 ; } } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


"selector must be an integer constant in the range "

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s> int standard_sse_constant_p ( rtx x ) { machine_mode mode = GET_MODE ( x ) ; if ( x == const0_rtx || x == CONST0_RTX ( GET_MODE ( x ) ) ) return 1 ; if ( vector_all_ones_operand ( x , mode ) ) switch ( mode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : if ( TARGET_SSE2 ) return 2 ; case V32QImode : case V16HImode : case V8SImode : case V4DImode : if ( TARGET_AVX2 ) return 2 ; case V64QImode : case V32HImode : case V16SImode : case V8DImode : if ( TARGET_AVX512F ) return 2 ; default : break ; } return 0 ; } </s>

Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s> void aarch64_split_simd_combine ( rtx dst , rtx src1 , rtx src2 ) { machine_mode src_mode = GET_MODE ( src1 ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src1 ) && REG_P ( src2 ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( src_mode ) { case V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case V4HFmode : gen = gen_aarch64_simd_combinev4hf ; break ; case V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case DImode : gen = gen_aarch64_simd_combinedi ; break ; case DFmode : gen = gen_aarch64_simd_combinedf ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src1 , src2 ) ) ; return ; } } </s>


<s>
unsigned
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
else
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .