<s> unsigned PPCFastISel :: fastEmitInst_ri ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill , uint64_t Imm ) { if ( MachineInstOpcode == PPC :: ADDI ) MRI . setRegClass ( Op0 , & PPC :: GPRC_and_GPRC_NOR0RegClass ) ; else if ( MachineInstOpcode == PPC :: ADDI8 ) MRI . setRegClass ( Op0 , & PPC :: G8RC_and_G8RC_NOX0RegClass ) ; const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_ri ( MachineInstOpcode , UseRC , Op0 , Op0IsKill , Imm ) ; } </s>

Emit a MachineInstr with a register operand , an immediate , and a result register in the given register class .


<s> static rtx function_arg_record_value ( const_tree type , machine_mode mode , int slotno , bool named , int regbase ) { const int size = int_size_in_bytes ( type ) ; assign_data_t data ; int nregs ; data . slotno = slotno ; data . regbase = regbase ; data . nregs = 0 ; data . intoffset = 0 ; data . stack = false ; traverse_record_type < assign_data_t , count_registers > ( type , named , & data ) ; if ( compute_int_layout ( size * BITS_PER_UNIT , & data , & nregs ) ) data . nregs += nregs ; nregs = data . nregs ; if ( nregs == 0 ) { if ( size <= 0 ) { return gen_rtx_REG ( mode , regbase ) ; } nregs = CEIL_NWORDS ( size ) ; if ( nregs + slotno > SPARC_INT_ARG_MAX ) nregs = SPARC_INT_ARG_MAX - slotno ; } gcc_assert ( nregs > 0 ) ; data . ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( data . stack + nregs ) ) ; if ( data . stack ) XVECEXP ( data . ret , 0 , 0 ) = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; data . nregs = 0 ; data . intoffset = 0 ; traverse_record_type < assign_data_t , assign_registers > ( type , named , & data ) ; assign_int_registers ( size * BITS_PER_UNIT , & data ) ; gcc_assert ( data . nregs == nregs ) ; return data . ret ; } </s>

Used by function_arg and sparc_function_value_1 to implement the complex conventions of the 64-bit ABI for passing and returning structures . Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . MODE is the argument 's machine mode . SLOTNO is the index number of the argument 's slot in the parameter array . NAMED is true if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . REGBASE is the regno of the base register for the parameter array .


"MIPS DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool MipsAsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { return true ; } </s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static unsigned int arm_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL && target_pure_code ) flags |= SECTION_ARM_PURECODE ; return flags ; } </s>

Implements the TARGET_SECTION_FLAGS hook . If DECL is a function declaration and pure-code is passed as an option then add the SFH_ARM_PURECODE attribute to the section flags . NAME is the section 's name and RELOC indicates whether the declarations initializer may contain runtime relocations .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasQPX ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasISEL ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = "+64bit," + FullFS ; else FullFS = "+64bit" ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = 32 ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void register_tuple_type ( unsigned int num_vectors , vector_type_index type ) { tree tuple_type = lang_hooks . types . make_type ( RECORD_TYPE ) ; tree vector_type = acle_vector_types [ 0 ] [ type ] ; tree array_type = build_array_type_nelts ( vector_type , num_vectors ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( array_type ) ) && TYPE_MODE_RAW ( array_type ) == TYPE_MODE ( array_type ) && TYPE_ALIGN ( array_type ) == 128 ) ; tree field = build_decl ( input_location , FIELD_DECL , get_identifier ( "__val" ) , array_type ) ; DECL_FIELD_CONTEXT ( field ) = tuple_type ; TYPE_FIELDS ( tuple_type ) = field ; add_sve_type_attribute ( tuple_type , num_vectors , 0 , NULL ) ; make_type_sizeless ( tuple_type ) ; layout_type ( tuple_type ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( tuple_type ) ) && TYPE_MODE_RAW ( tuple_type ) == TYPE_MODE ( tuple_type ) && TYPE_ALIGN ( tuple_type ) == 128 ) ; char buffer [ sizeof ( "svbfloat16x4_t" ) ] ; const char * vector_type_name = vector_types [ type ] . acle_name ; snprintf ( buffer , sizeof ( buffer ) , "%.*sx%d_t" , ( int ) strlen ( vector_type_name ) - 2 , vector_type_name , num_vectors ) ; tree decl = build_decl ( input_location , TYPE_DECL , get_identifier ( buffer ) , tuple_type ) ; TYPE_NAME ( tuple_type ) = decl ; TYPE_STUB_DECL ( tuple_type ) = decl ; lang_hooks . decls . pushdecl ( decl ) ; DECL_ORIGINAL_TYPE ( decl ) = NULL_TREE ; acle_vector_types [ num_vectors - 1 ] [ type ] = tuple_type ; } </s>

Register the tuple type that contains NUM_VECTORS vectors of type TYPE .


<s> std :: pair < unsigned , unsigned > DLXInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .