<s>
void
LoongArchMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
}
</s>

Encode the given Inst to bytes and append to CB .

LoongArch
LoongArch
"Unhandled encodeInstruction length!"
4
support::endian
support::little


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
bool
AArch64DAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_Q
:
const
TargetRegisterInfo
*
TRI
=
Subtarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i64
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int i386_pe_reloc_rw_mask ( void ) { return 0 ; } </s>

Local and global relocs can be placed always into readonly memory for memory for PE-COFF targets .


<s> bool MipsSEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> Optional < MCFixupKind > ELFPPCAsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . isPPC64 ( ) ) { if ( Name == "R_PPC64_NONE" ) return FK_NONE ; } else { if ( Name == "R_PPC_NONE" ) return FK_NONE ; } return MCAsmBackend :: getFixupKind ( Name ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { const AArch64Subtarget & ST = C -> MF -> getSubtarget < AArch64Subtarget > ( ) ; ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ; DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; DAG -> addMutation ( createStoreClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ; if ( ST . hasFusion ( ) ) DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static rtvec rs6000_const_vec ( machine_mode mode ) { int i , subparts ; rtvec v ; switch ( mode ) { case E_V1TImode : subparts = 1 ; break ; case E_V2DFmode : case E_V2DImode : subparts = 2 ; break ; case E_V4SFmode : case E_V4SImode : subparts = 4 ; break ; case E_V8HImode : subparts = 8 ; break ; case E_V16QImode : subparts = 16 ; break ; default : gcc_unreachable ( ) ; } v = rtvec_alloc ( subparts ) ; for ( i = 0 ; i < subparts / 2 ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i + subparts / 2 ) ; for ( i = subparts / 2 ; i < subparts ; ++ i ) RTVEC_ELT ( v , i ) = gen_rtx_CONST_INT ( DImode , i - subparts / 2 ) ; return v ; } </s>

Generate a vector of constants to permute MODE for a little-endian storage operation by swapping the two halves of a vector .


<s> void MipsSEDAGToDAGISel :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DominatorTreeWrapperPass > ( ) ; SelectionDAGISel :: getAnalysisUsage ( AU ) ; } </s>


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) || ( VT == MVT :: v16f32 && Subtarget . useAVX512Regs ( ) ) ) { if ( VT == MVT :: f32 && Enabled == ReciprocalEstimate :: Unspecified ) return SDValue ( ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; unsigned Opcode = VT == MVT :: v16f32 ? X86ISD :: RCP14 : X86ISD :: FRCP ; return DAG . getNode ( Opcode , DL , VT , Op ) ; } if ( VT . getScalarType ( ) == MVT :: f16 && isTypeLegal ( VT ) && Subtarget . hasFP16 ( ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 0 ; if ( VT == MVT :: f16 ) { SDValue Zero = DAG . getIntPtrConstant ( 0 , DL ) ; SDValue Undef = DAG . getUNDEF ( MVT :: v8f16 ) ; Op = DAG . getNode ( ISD :: SCALAR_TO_VECTOR , DL , MVT :: v8f16 , Op ) ; Op = DAG . getNode ( X86ISD :: RCP14S , DL , MVT :: v8f16 , Undef , Op ) ; return DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , MVT :: f16 , Op , Zero ) ; } return DAG . getNode ( X86ISD :: RCP14 , DL , VT , Op ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> gimple * fold ( gimple_folder & f ) const OVERRIDE { if ( tree amount = uniform_integer_cst_p ( gimple_call_arg ( f . call , 2 ) ) ) { if ( wi :: to_widest ( amount ) >= 0 ) { function_instance instance ( "svlsl" , functions :: svlsl , shapes :: binary_uint_opt_n , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } int element_bits = f . type_suffix ( 0 ) . element_bits ; if ( wi :: to_widest ( amount ) >= - element_bits ) { amount = wide_int_to_tree ( TREE_TYPE ( amount ) , - wi :: to_wide ( amount ) ) ; function_instance instance ( "svrshr" , functions :: svrshr , shapes :: shift_right_imm , MODE_n , f . type_suffix_ids , f . pred ) ; gcall * call = as_a < gcall * > ( f . redirect_call ( instance ) ) ; gimple_call_set_arg ( call , 2 , amount ) ; return call ; } } return NULL ; } </s>

Try to fold the call . Return the new statement on success and null on failure .


<s> bool MipsConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return false ; } </s>


<s> static machine_mode aarch64_simd_container_mode ( machine_mode mode , unsigned width ) { gcc_assert ( width == 64 || width == 128 ) ; if ( TARGET_SIMD ) { if ( width == 128 ) switch ( mode ) { case DFmode : return V2DFmode ; case SFmode : return V4SFmode ; case HFmode : return V8HFmode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; case DImode : return V2DImode ; default : break ; } else switch ( mode ) { case SFmode : return V2SFmode ; case HFmode : return V4HFmode ; case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : break ; } } return word_mode ; } </s>

Return appropriate SIMD container for MODE within a vector of WIDTH bits .


<s> static void arm_encode_section_info ( tree decl , rtx rtl , int first ) { if ( optimize > 0 && TREE_CONSTANT ( decl ) ) SYMBOL_REF_FLAG ( XEXP ( rtl , 0 ) ) = 1 ; if ( first && DECL_P ( decl ) ) { if ( TREE_CODE ( decl ) == FUNCTION_DECL && DECL_WEAK ( decl ) ) arm_encode_call_attribute ( decl , LONG_CALL_FLAG_CHAR ) ; else if ( ! TREE_PUBLIC ( decl ) ) arm_encode_call_attribute ( decl , SHORT_CALL_FLAG_CHAR ) ; } default_encode_section_info ( decl , rtl , first ) ; } </s>

Symbols in the text segment can be accessed without indirecting via the constant pool ; it may take an extra binary operation , but this is still faster than indirecting via memory . Do n't do this when not optimizing , since we wo n't be calculating al of the offsets necessary to do this simplification .


<s>
void
MipsSEInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineMemOperand
*
MMO
=
GetMemOperand
(
MBB
,
FI
,
MachineMemOperand
::
MOStore
)
;
unsigned
Opc
=
0
;
if
(
Mips
::
CPURegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SW_P8
:
Mips
::
SW
;
else
if
(
Mips
::
CPU64RegsRegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SD_P8
:
Mips
::
SD
;
else
if
(
Mips
::
FGR32RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SWC1_P8
:
Mips
::
SWC1
;
else
if
(
Mips
::
AFGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
Mips
::
SDC1
;
else
if
(
Mips
::
FGR64RegClass
.
hasSubClassEq
(
RC
)
)
Opc
=
IsN64
Mips
::
SDC164_P8
:
Mips
::
SDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static rtx find_alignment_op ( rtx_insn * insn , rtx base_reg ) { df_ref base_use ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; rtx and_operation = 0 ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) break ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) break ; rtx_insn * and_insn = DF_REF_INSN ( base_def_link -> ref ) ; and_operation = alignment_mask ( and_insn ) ; if ( and_operation != 0 ) break ; } return and_operation ; } </s>

Given INSN that 's a load or store based at BASE_REG , check if all of its feeding computations align its address on a 16-byte boundary . If so , return true and add all definition insns into AND_INSNS and their corresponding fully-expanded rtxes for the masking operations into AND_OPS .


<s> static rtx aarch64_expand_sve_const_pred ( rtx target , rtx_vector_builder & builder ) { if ( rtx res = aarch64_expand_sve_const_pred_1 ( target , builder , true ) ) return res ; if ( builder . full_nelts ( ) . is_constant ( ) ) if ( rtx mem = force_const_mem ( VNx16BImode , builder . build ( ) ) ) { target = aarch64_target_reg ( target , VNx16BImode ) ; emit_move_insn ( target , mem ) ; return target ; } rtx_vector_builder int_builder ( VNx16QImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; for ( unsigned int i = 0 ; i < builder . encoded_nelts ( ) ; ++ i ) int_builder . quick_push ( INTVAL ( builder . elt ( i ) ) ? constm1_rtx : const0_rtx ) ; return aarch64_convert_sve_data_to_pred ( target , VNx16BImode , int_builder . build ( ) ) ; } </s>

Return an SVE predicate register that contains the VNx16BImode constant in BUILDER , without going through the move expanders . The returned register can have whatever mode seems most natural given the contents of BUILDER . Use TARGET for the result if convenient .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
VE
::
NumTargetFixupKinds
]
=
{
{
"fixup_ve_reflong"
,
0
,
32
,
0
}
,
{
"fixup_ve_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_pc_hi32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ve_pc_lo32"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ve_got_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_got_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_gotoff_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_gotoff_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_plt_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_plt_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tls_gd_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tls_gd_lo32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tpoff_hi32"
,
0
,
32
,
0
}
,
{
"fixup_ve_tpoff_lo32"
,
0
,
32
,
0
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> unsigned AArch64InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: STRWui : case AArch64 :: STRXui : case AArch64 :: STRBui : case AArch64 :: STRHui : case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STR_PXI : case AArch64 :: STR_ZXI : case AArch64 :: STR_ZZXI : case AArch64 :: STR_ZZZXI : case AArch64 :: STR_ZZZZXI : if ( MI -> getOperand ( 0 ) . getSubReg ( ) == 0 && MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> inline void assign_registers ( const_tree field , HOST_WIDE_INT bitpos , bool fp , assign_data_t * data ) { if ( fp ) { assign_int_registers ( bitpos , data ) ; assign_fp_registers ( field , bitpos , data ) ; } else { if ( data -> intoffset < 0 ) data -> intoffset = bitpos ; } } </s>

A subroutine of function_arg_record_value . Assign FIELD and the bits of the structure between PARMS- > intoffset and BITPOS to registers .


<s>
const
char
*
thumb1_output_interwork
(
void
)
{
const
char
*
name
;
FILE
*
f
=
asm_out_file
;
gcc_assert
(
MEM_P
(
DECL_RTL
(
current_function_decl
)
)
)
;
gcc_assert
(
GET_CODE
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
)
==
SYMBOL_REF
)
;
name
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
asm_fprintf
(
f
,
"\torr\t%r, %r, #1\n"
,
IP_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tbx\t%r\n"
,
IP_REGNUM
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
if
(
arm_dllexport_name_p
(
name
)
)
name
=
arm_strip_name_encoding
(
name
)
;
asm_fprintf
(
f
,
"\t.globl %s%U%s\n"
,
STUB_NAME
,
name
)
;
fprintf
(
f
,
"\t.thumb_func\n"
)
;
asm_fprintf
(
f
,
"%s%U%s:\n"
,
STUB_NAME
,
name
)
;
return
""
;
}
</s>

Implementation of insn prologue_thumb1_interwork . This is the first `` instruction '' of a function called in ARM mode . Swap to thumb mode .


"immediate value expected for vector index"

tryParseRegister - parse one register if possible


<s>
bool
SystemZAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
Operands
.
push_back
(
SystemZOperand
::
createToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
Parser
.
eatToEndOfStatement
(
)
;
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

SystemZ
SystemZ
SystemZ
"unexpected token in argument list"


<s> void setPersonality ( const MCSymbol * Per ) { HasPersonality = true ; } </s>


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
;
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARM::tPUSH
ARM::tPOP


<s> SDValue Cpu0TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool FPGATTIImpl :: shouldBuildLookupTables ( ) { return false ; } </s>

Return true if switches should be turned into lookup tables for the target .


<s>
bool
X86TargetLowering
::
isNoopAddrSpaceCast
(
unsigned
SrcAS
,
unsigned
DestAS
)
const
{
assert
(
SrcAS
!=
DestAS
&&
"Expected different address spaces!"
)
;
return
SrcAS
<
256
&&
DestAS
<
256
;
}
</s>

Returns true if a cast between SrcAS and DestAS is a noop .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( ConstantSDNode * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


<s> bool SystemZInstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , BranchProbability Probability ) const { return NumCycles == 1 ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> static bool expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt , bool testing_p ) { machine_mode v2mode ; rtx x ; bool ok ; if ( vselect_insn == NULL_RTX ) init_vselect_insn ( ) ; v2mode = GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) ; x = XEXP ( SET_SRC ( PATTERN ( vselect_insn ) ) , 0 ) ; PUT_MODE ( x , v2mode ) ; XEXP ( x , 0 ) = op0 ; XEXP ( x , 1 ) = op1 ; ok = expand_vselect ( target , x , perm , nelt , testing_p ) ; XEXP ( x , 0 ) = const0_rtx ; XEXP ( x , 1 ) = const0_rtx ; return ok ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s>
static
void
process_cfa_adjust_cfa
(
FILE
*
out_file
,
rtx
pat
,
rtx
insn
,
bool
unwind
,
bool
frame
)
{
rtx
dest
=
SET_DEST
(
pat
)
;
rtx
src
=
SET_SRC
(
pat
)
;
if
(
dest
==
stack_pointer_rtx
)
{
if
(
GET_CODE
(
src
)
==
PLUS
)
{
rtx
op0
=
XEXP
(
src
,
0
)
;
rtx
op1
=
XEXP
(
src
,
1
)
;
gcc_assert
(
op0
==
dest
&&
GET_CODE
(
op1
)
==
CONST_INT
)
;
if
(
INTVAL
(
op1
)
<
0
)
{
gcc_assert
(
!
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.fframe "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
INTVAL
(
op1
)
)
;
}
else
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
}
else
{
gcc_assert
(
src
==
hard_frame_pointer_rtx
)
;
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
}
}
else
if
(
dest
==
hard_frame_pointer_rtx
)
{
gcc_assert
(
src
==
stack_pointer_rtx
)
;
gcc_assert
(
frame_pointer_needed
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.vframe r%d\n"
,
ia64_dbx_register_number
(
REGNO
(
dest
)
)
)
;
}
else
gcc_unreachable
(
)
;
}
</s>

This function processes a SET pattern for REG_CFA_ADJUST_CFA .


<s> inline hashval_t mips_lo_sum_offset_hasher :: hash ( const value_type * entry ) { return mips_hash_base ( entry -> base ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> bool X86TargetLowering :: isTypeDesirableForOp ( unsigned Opc , EVT VT ) const { if ( ! isTypeLegal ( VT ) ) return false ; if ( VT != MVT :: i16 ) return true ; switch ( Opc ) { default : return true ; case ISD :: LOAD : case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: ANY_EXTEND : case ISD :: SHL : case ISD :: SRL : case ISD :: SUB : case ISD :: ADD : case ISD :: MUL : case ISD :: AND : case ISD :: OR : case ISD :: XOR : return false ; } } </s>

Return true if the target has native support for the specified value type and it is 'desirable ' to use the type for the given node type .


<s> static bool is_power9_pairable_vec_type ( enum attr_type type ) { switch ( type ) { case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX : case TYPE_VECDIV : case TYPE_VECCMP : case TYPE_VECPERM : case TYPE_VECFLOAT : case TYPE_VECFDIV : case TYPE_VECDOUBLE : return true ; default : break ; } return false ; } </s>

Return whether TYPE is a Power9 pairable vector instruction type .


<s> static void emit_v9_brxx_insn ( enum rtx_code code , rtx op0 , rtx label ) { emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; } </s>

Emit a conditional jump insn for the v9 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the v9 brxx insns .


<s> static rtx expand_set_or_movmem_constant_prologue ( rtx dst , rtx * srcp , rtx destreg , rtx srcreg , rtx value , rtx vec_value , int desired_align , int align_bytes , bool issetmem ) { rtx src = NULL ; rtx orig_dst = dst ; rtx orig_src = NULL ; int piece_size = 1 ; int copied_bytes = 0 ; if ( ! issetmem ) { gcc_assert ( srcp != NULL ) ; src = * srcp ; orig_src = src ; } for ( piece_size = 1 ; piece_size <= desired_align && copied_bytes < align_bytes ; piece_size <<= 1 ) { if ( align_bytes & piece_size ) { if ( issetmem ) { if ( vec_value && piece_size > GET_MODE_SIZE ( GET_MODE ( value ) ) ) dst = emit_memset ( dst , destreg , vec_value , piece_size ) ; else dst = emit_memset ( dst , destreg , value , piece_size ) ; } else dst = emit_memmov ( dst , & src , destreg , srcreg , piece_size ) ; copied_bytes += piece_size ; } } if ( MEM_ALIGN ( dst ) < ( unsigned int ) desired_align * BITS_PER_UNIT ) set_mem_align ( dst , desired_align * BITS_PER_UNIT ) ; if ( MEM_SIZE_KNOWN_P ( orig_dst ) ) set_mem_size ( dst , MEM_SIZE ( orig_dst ) - align_bytes ) ; if ( ! issetmem ) { int src_align_bytes = get_mem_align_offset ( src , desired_align * BITS_PER_UNIT ) ; if ( src_align_bytes >= 0 ) src_align_bytes = desired_align - src_align_bytes ; if ( src_align_bytes >= 0 ) { unsigned int src_align ; for ( src_align = desired_align ; src_align >= 2 ; src_align >>= 1 ) { if ( ( src_align_bytes & ( src_align - 1 ) ) == ( align_bytes & ( src_align - 1 ) ) ) break ; } if ( src_align > ( unsigned int ) desired_align ) src_align = desired_align ; if ( MEM_ALIGN ( src ) < src_align * BITS_PER_UNIT ) set_mem_align ( src , src_align * BITS_PER_UNIT ) ; } if ( MEM_SIZE_KNOWN_P ( orig_src ) ) set_mem_size ( src , MEM_SIZE ( orig_src ) - align_bytes ) ; * srcp = src ; } return dst ; } </s>

This function is like the previous one , except here we know how many bytes need to be copied . That allows us to update alignment not only of DST , which is returned , but also of SRC , which is passed as a pointer for that reason .


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST_IMM ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! EnableARMTailCalls ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; return ! Subtarget -> isThumb1Only ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


"Unsupported cpu name returned from kernel for "

"Please use an explicit cpu name.  Valid cpu names are: %s"

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> static void arm_option_save ( struct cl_target_option * ptr , struct gcc_options * opts ) { ptr -> x_arm_arch_string = opts -> x_arm_arch_string ; ptr -> x_arm_cpu_string = opts -> x_arm_cpu_string ; ptr -> x_arm_tune_string = opts -> x_arm_tune_string ; } </s>


<s> virtual const LC3bSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> void ix86_expand_vector_convert_uns_vsivsf ( rtx target , rtx val ) { rtx tmp [ 8 ] ; REAL_VALUE_TYPE TWO16r ; machine_mode intmode = GET_MODE ( val ) ; machine_mode fltmode = GET_MODE ( target ) ; rtx ( * cvt ) ( rtx , rtx ) ; if ( intmode == V4SImode ) cvt = gen_floatv4siv4sf2 ; else cvt = gen_floatv8siv8sf2 ; tmp [ 0 ] = ix86_build_const_vector ( intmode , 1 , GEN_INT ( 0xffff ) ) ; tmp [ 0 ] = force_reg ( intmode , tmp [ 0 ] ) ; tmp [ 1 ] = expand_simple_binop ( intmode , AND , val , tmp [ 0 ] , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp [ 2 ] = expand_simple_binop ( intmode , LSHIFTRT , val , GEN_INT ( 16 ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp [ 3 ] = gen_reg_rtx ( fltmode ) ; emit_insn ( cvt ( tmp [ 3 ] , tmp [ 1 ] ) ) ; tmp [ 4 ] = gen_reg_rtx ( fltmode ) ; emit_insn ( cvt ( tmp [ 4 ] , tmp [ 2 ] ) ) ; real_ldexp ( & TWO16r , & dconst1 , 16 ) ; tmp [ 5 ] = const_double_from_real_value ( TWO16r , SFmode ) ; tmp [ 5 ] = force_reg ( fltmode , ix86_build_const_vector ( fltmode , 1 , tmp [ 5 ] ) ) ; if ( TARGET_FMA ) { tmp [ 6 ] = gen_rtx_FMA ( fltmode , tmp [ 4 ] , tmp [ 5 ] , tmp [ 3 ] ) ; emit_move_insn ( target , tmp [ 6 ] ) ; } else { tmp [ 6 ] = expand_simple_binop ( fltmode , MULT , tmp [ 4 ] , tmp [ 5 ] , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp [ 7 ] = expand_simple_binop ( fltmode , PLUS , tmp [ 3 ] , tmp [ 6 ] , target , 1 , OPTAB_DIRECT ) ; if ( tmp [ 7 ] != target ) emit_move_insn ( target , tmp [ 7 ] ) ; } } </s>

floatunsv { 4,8 } siv { 4,8 } sf2 expander . Expand code to convert a vector of unsigned ints VAL to vector of floats TARGET .


<s>
unsigned
getReg
(
)
const
{
assert
(
isRegNumber
(
)
&&
"Invalid access!"
)
;
return
(
unsigned
)
Imm
.
Val
;
}
</s>

Returns the register associated with this edge .


<s> unsigned X86TargetLowering :: getJumpTableEncoding ( ) const { if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget -> isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static void aarch64_sched_fusion_priority ( rtx_insn * insn , int max_pri , int * fusion_pri , int * pri ) { int tmp , off_val ; rtx base , offset ; enum sched_fusion_type fusion ; gcc_assert ( INSN_P ( insn ) ) ; tmp = max_pri - 1 ; fusion = fusion_load_store ( insn , & base , & offset ) ; if ( fusion == SCHED_FUSION_NONE ) { * pri = tmp ; * fusion_pri = tmp ; return ; } * fusion_pri = tmp - fusion * FIRST_PSEUDO_REGISTER - REGNO ( base ) ; tmp /= 2 ; off_val = ( int ) ( INTVAL ( offset ) ) ; if ( off_val >= 0 ) tmp -= ( off_val & 0xfffff ) ; else tmp += ( ( - off_val ) & 0xfffff ) ; * pri = tmp ; return ; } </s>

Implement the TARGET_SCHED_FUSION_PRIORITY hook . Currently we only support to fuse ldr or str instructions , so FUSION_PRI and PRI are only calculated for these instructions . For other instruction , FUSION_PRI and PRI are simply set to MAX_PRI - 1 . In the future , other type instruction fusion can be added by returning different priorities . It 's important that irrelevant instructions get the largest FUSION_PRI .


"***** Machine Function before Domain Reassignment *****\n"

"***** Machine Function after Domain Reassignment *****\n"

runOnMachineFunction - Emit the function body .


"Stack realignment in presence of dynamic allocas is not supported with"

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void PPCIncomingValueHandler :: assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) { markPhysRegUsed ( PhysReg ) ; IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static bool mips_use_debug_exception_return_p ( tree type ) { return lookup_attribute ( "use_debug_exception_return" , TYPE_ATTRIBUTES ( type ) ) != NULL ; } </s>

Check if the attribute to use debug exception return is set for a function .


<s> TargetLowering :: ConstraintWeight MipsTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( Subtarget -> hasMSA ( ) && type -> isVectorTy ( ) && cast < VectorType > ( type ) -> getBitWidth ( ) == 128 ) weight = CW_Register ; else if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; case 'c' : case 'l' : case 'x' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool MipsNaClRewritePass :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const MipsInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; if ( FlagSfiLoad ) Modified |= SandboxLoadsInBlock ( MBB ) ; if ( FlagSfiStore ) Modified |= SandboxStoresInBlock ( MBB ) ; if ( FlagSfiBranch ) Modified |= SandboxBranchesInBlock ( MBB ) ; if ( FlagSfiStack ) Modified |= SandboxStackChangesInBlock ( MBB ) ; } if ( FlagSfiBranch ) AlignAllJumpTargets ( MF ) ; return Modified ; } </s>


<s> static bool aarch64_advsimd_valid_immediate ( unsigned HOST_WIDE_INT val64 , simd_immediate_info * info , enum simd_immediate_check which ) { unsigned int val32 = val64 & 0xffffffff ; unsigned int val16 = val64 & 0xffff ; unsigned int val8 = val64 & 0xff ; if ( val32 == ( val64 >> 32 ) ) { if ( ( which & AARCH64_CHECK_ORR ) != 0 && aarch64_advsimd_valid_immediate_hs ( val32 , info , which , simd_immediate_info :: MOV ) ) return true ; if ( ( which & AARCH64_CHECK_BIC ) != 0 && aarch64_advsimd_valid_immediate_hs ( ~ val32 , info , which , simd_immediate_info :: MVN ) ) return true ; if ( which == AARCH64_CHECK_MOV && val16 == ( val32 >> 16 ) && val8 == ( val16 >> 8 ) ) { if ( info ) * info = simd_immediate_info ( QImode , val8 ) ; return true ; } } if ( which == AARCH64_CHECK_MOV ) { unsigned int i ; for ( i = 0 ; i < 64 ; i += 8 ) { unsigned char byte = ( val64 >> i ) & 0xff ; if ( byte != 0 && byte != 0xff ) break ; } if ( i == 64 ) { if ( info ) * info = simd_immediate_info ( DImode , val64 ) ; return true ; } } return false ; } </s>

Return true if replicating VAL64 is a valid immediate for the Advanced SIMD operation described by WHICH . If INFO is nonnull , use it to describe valid immediates .


<s> static HOST_WIDE_INT rs6000_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return 0 ; return RS6000_STARTING_FRAME_OFFSET ; } </s>


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ; } </s>

Get the source location of the point where the field was defined .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( ) ) ; if ( PACStack :: doAArch64IRPass ( ) ) addPass ( PACStack :: createPACStackOptCallPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> const TOYRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"We have a different number of location and args?!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool isAndroid ( ) const { return IsAndroid ; } </s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool xscale_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { if ( REG_NOTE_KIND ( link ) == 0 && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { int shift_opnum = get_attr_shift ( insn ) ; enum attr_type attr_type = get_attr_type ( dep ) ; if ( shift_opnum != 0 && ( attr_type == TYPE_ALU_SHIFT_IMM || attr_type == TYPE_ALUS_SHIFT_IMM || attr_type == TYPE_LOGIC_SHIFT_IMM || attr_type == TYPE_LOGICS_SHIFT_IMM || attr_type == TYPE_ALU_SHIFT_REG || attr_type == TYPE_ALUS_SHIFT_REG || attr_type == TYPE_LOGIC_SHIFT_REG || attr_type == TYPE_LOGICS_SHIFT_REG || attr_type == TYPE_MOV_SHIFT || attr_type == TYPE_MVN_SHIFT || attr_type == TYPE_MOV_SHIFT_REG || attr_type == TYPE_MVN_SHIFT_REG ) ) { rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( dep ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) { * cost = 2 ; return false ; } } } } return true ; } </s>


<s> const PPCMCExpr * PPCMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> static tree rs6000_builtin_vectorized_libmass ( combined_fn fn , tree type_out , tree type_in ) { char name [ 32 ] ; const char * suffix = NULL ; tree fntype , new_fndecl , bdecl = NULL_TREE ; int n_args = 1 ; const char * bname ; machine_mode el_mode , in_mode ; int n , in_n ; if ( ! flag_unsafe_math_optimizations || ! TARGET_VSX ) return NULL_TREE ; el_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; if ( el_mode != in_mode || n != in_n ) return NULL_TREE ; switch ( fn ) { CASE_CFN_ATAN2 : CASE_CFN_HYPOT : CASE_CFN_POW : n_args = 2 ; CASE_CFN_ACOS : CASE_CFN_ACOSH : CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == 2 ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = "d2" ; } else if ( el_mode == SFmode && n == 4 ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = "4" ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( "__builtin_" ) - 1 ) ; strcat ( name , suffix ) ; if ( n_args == 1 ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == 2 ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = 1 ; DECL_EXTERNAL ( new_fndecl ) = 1 ; DECL_IS_NOVOPS ( new_fndecl ) = 1 ; TREE_READONLY ( new_fndecl ) = 1 ; return new_fndecl ; } </s>

Handler for the Mathematical Acceleration Subsystem ( mass ) interface to a library with vectorized intrinsics .


<s>
void
X86ATTInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
EvaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


This function tries to implement an atomic exchange operation using a compare_and_swap loop . VAL is written to * MEM . The previous contents of * MEM are returned , using TARGET if possible . No memory model is required since a compare_and_swap loop is seq-cst .


<s> static void pru_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { int regi = pru_function_arg_regi ( cum_v , arg . mode , arg . type , arg . named ) ; if ( regi >= 0 ) pru_function_arg_regi_mark_slot ( regi , cum_v , arg . mode , arg . type , arg . named ) ; } </s>

Update the data in CUM to advance over argument ARG .


<s> int nds32_can_use_return_insn ( void ) { int sp_adjust ; if ( ! reload_completed ) return 0 ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return 1 ; return ( cfun -> machine -> naked_p && ( cfun -> machine -> va_args_size == 0 ) ) ; } </s>

Return nonzero if this function is known to have a null epilogue . This allows the optimizer to omit jumps to jumps if no stack was created .


<s> type_suffix_index function_resolver :: infer_vector_type ( unsigned int argno ) { return infer_vector_or_tuple_type ( argno , 1 ) ; } </s>

Require argument ARGNO to have some form of vector type . Return the associated type suffix on success , using TYPE_SUFFIX_b for predicates . Report an error and return NUM_TYPE_SUFFIXES on failure .


<s> int csky_get_movedouble_length ( rtx operands [ ] ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 1 ] ; if ( REG_P ( dst ) ) { if ( REG_P ( src ) ) { int dstreg = REGNO ( dst ) ; int srcreg = REGNO ( src ) ; if ( CSKY_VREG_P ( srcreg ) && CSKY_VREG_P ( dstreg ) ) return 4 ; else return 8 ; } else if ( GET_CODE ( src ) == MEM ) { rtx memexp = XEXP ( src , 0 ) ; int dstreg = REGNO ( dst ) ; struct csky_address op0 ; decompose_csky_address ( XEXP ( src , 0 ) , & op0 ) ; if ( GET_CODE ( memexp ) == LABEL_REF ) return 8 ; if ( CSKY_VREG_P ( dstreg ) ) return 4 ; return 8 ; } else if ( GET_CODE ( src ) == CONST_INT || GET_CODE ( src ) == CONST_DOUBLE ) { split_double ( src , operands + 2 , operands + 3 ) ; if ( CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ 2 ] ) + 1 ) && CSKY_CONST_OK_FOR_N ( INTVAL ( operands [ 3 ] ) + 1 ) && REGNO ( operands [ 0 ] ) < 6 ) return 4 ; else return 8 ; } } else if ( GET_CODE ( dst ) == MEM && GET_CODE ( src ) == REG ) { rtx memexp = XEXP ( dst , 0 ) ; int srcreg = REGNO ( src ) ; int offset = - 1 ; if ( CSKY_VREG_P ( srcreg ) ) return 4 ; if ( GET_CODE ( memexp ) == REG ) offset = 0 ; else if ( GET_CODE ( memexp ) == PLUS ) { if ( GET_CODE ( XEXP ( memexp , 0 ) ) == REG ) offset = INTVAL ( XEXP ( memexp , 1 ) ) ; else if ( GET_CODE ( XEXP ( memexp , 1 ) ) == REG ) offset = INTVAL ( XEXP ( memexp , 0 ) ) ; else gcc_unreachable ( ) ; } else gcc_unreachable ( ) ; if ( srcreg <= 6 && offset <= 1020 ) return 4 ; else if ( ( srcreg == 7 && offset <= 1024 ) || ( srcreg <= 7 && offset == 1024 ) ) return 6 ; else return 8 ; } else gcc_unreachable ( ) ; return 0 ; } </s>

Calculate the instruction 's length for moving double-word data .


<s> unsigned int nds32_data_alignment ( tree data , unsigned int basic_align ) { if ( ( basic_align < BITS_PER_WORD ) && ( TREE_CODE ( data ) == ARRAY_TYPE || TREE_CODE ( data ) == UNION_TYPE || TREE_CODE ( data ) == RECORD_TYPE ) ) return BITS_PER_WORD ; else return basic_align ; } </s>


<s> static void sparc_init_pic_reg ( void ) { edge entry_edge ; rtx_insn * seq ; if ( ! flag_pic || ( ! crtl -> uses_pic_offset_table && ! optimize ) ) return ; start_sequence ( ) ; load_got_register ( ) ; if ( ! TARGET_VXWORKS_RTP ) emit_move_insn ( pic_offset_table_rtx , got_register_rtx ) ; seq = get_insns ( ) ; end_sequence ( ) ; entry_edge = single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ; insert_insn_on_edge ( seq , entry_edge ) ; commit_one_edge_insertion ( entry_edge ) ; } </s>


<s>
const
RegisterBank
&
AArch64RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
,
LLT
)
const
{
switch
(
RC
.
getID
(
)
)
{
case
AArch64
::
FPR8RegClassID
:
case
AArch64
::
FPR16RegClassID
:
case
AArch64
::
FPR16_loRegClassID
:
case
AArch64
::
FPR32_with_hsub_in_FPR16_loRegClassID
:
case
AArch64
::
FPR32RegClassID
:
case
AArch64
::
FPR64RegClassID
:
case
AArch64
::
FPR64_loRegClassID
:
case
AArch64
::
FPR128RegClassID
:
case
AArch64
::
FPR128_loRegClassID
:
case
AArch64
::
DDRegClassID
:
case
AArch64
::
DDDRegClassID
:
case
AArch64
::
DDDDRegClassID
:
case
AArch64
::
QQRegClassID
:
case
AArch64
::
QQQRegClassID
:
case
AArch64
::
QQQQRegClassID
:
return
getRegBank
(
AArch64
::
FPRRegBankID
)
;
case
AArch64
::
GPR32commonRegClassID
:
case
AArch64
::
GPR32RegClassID
:
case
AArch64
::
GPR32spRegClassID
:
case
AArch64
::
GPR32sponlyRegClassID
:
case
AArch64
::
GPR32argRegClassID
:
case
AArch64
::
GPR32allRegClassID
:
case
AArch64
::
GPR64commonRegClassID
:
case
AArch64
::
GPR64RegClassID
:
case
AArch64
::
GPR64spRegClassID
:
case
AArch64
::
GPR64sponlyRegClassID
:
case
AArch64
::
GPR64argRegClassID
:
case
AArch64
::
GPR64allRegClassID
:
case
AArch64
::
GPR64noipRegClassID
:
case
AArch64
::
GPR64common_and_GPR64noipRegClassID
:
case
AArch64
::
GPR64noip_and_tcGPR64RegClassID
:
case
AArch64
::
tcGPR64RegClassID
:
case
AArch64
::
rtcGPR64RegClassID
:
case
AArch64
::
WSeqPairsClassRegClassID
:
case
AArch64
::
XSeqPairsClassRegClassID
:
return
getRegBank
(
AArch64
::
GPRRegBankID
)
;
case
AArch64
::
CCRRegClassID
:
return
getRegBank
(
AArch64
::
CCRegBankID
)
;
default
:
llvm_unreachable
(
"Register class not supported"
)
;
}
}
</s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AZPR Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"EFLAGS are not live-out from a patchpoint."

Prior to adding the live-out mask to a stackmap or patchpoint instruction , provide the target the opportunity to adjust it ( mainly to remove pseudo-registers that should be ignored ) .


<s> TargetLowering :: ConstraintWeight ARM64TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'x' : case 'w' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ 2 ] , & Constraint [ Size - 1 ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= 0 && RegNo <= 31 ) { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , 0 , IsZExt ) ) return false ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> const char * PPCTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case PPCISD :: FSEL : return "PPCISD::FSEL" ; case PPCISD :: FCFID : return "PPCISD::FCFID" ; case PPCISD :: FCTIDZ : return "PPCISD::FCTIDZ" ; case PPCISD :: FCTIWZ : return "PPCISD::FCTIWZ" ; case PPCISD :: STFIWX : return "PPCISD::STFIWX" ; case PPCISD :: VMADDFP : return "PPCISD::VMADDFP" ; case PPCISD :: VNMSUBFP : return "PPCISD::VNMSUBFP" ; case PPCISD :: VPERM : return "PPCISD::VPERM" ; case PPCISD :: Hi : return "PPCISD::Hi" ; case PPCISD :: Lo : return "PPCISD::Lo" ; case PPCISD :: TOC_ENTRY : return "PPCISD::TOC_ENTRY" ; case PPCISD :: TOC_RESTORE : return "PPCISD::TOC_RESTORE" ; case PPCISD :: LOAD : return "PPCISD::LOAD" ; case PPCISD :: LOAD_TOC : return "PPCISD::LOAD_TOC" ; case PPCISD :: DYNALLOC : return "PPCISD::DYNALLOC" ; case PPCISD :: GlobalBaseReg : return "PPCISD::GlobalBaseReg" ; case PPCISD :: SRL : return "PPCISD::SRL" ; case PPCISD :: SRA : return "PPCISD::SRA" ; case PPCISD :: SHL : return "PPCISD::SHL" ; case PPCISD :: EXTSW_32 : return "PPCISD::EXTSW_32" ; case PPCISD :: STD_32 : return "PPCISD::STD_32" ; case PPCISD :: CALL_SVR4 : return "PPCISD::CALL_SVR4" ; case PPCISD :: CALL_NOP_SVR4 : return "PPCISD::CALL_NOP_SVR4" ; case PPCISD :: CALL_Darwin : return "PPCISD::CALL_Darwin" ; case PPCISD :: NOP : return "PPCISD::NOP" ; case PPCISD :: MTCTR : return "PPCISD::MTCTR" ; case PPCISD :: BCTRL_Darwin : return "PPCISD::BCTRL_Darwin" ; case PPCISD :: BCTRL_SVR4 : return "PPCISD::BCTRL_SVR4" ; case PPCISD :: RET_FLAG : return "PPCISD::RET_FLAG" ; case PPCISD :: MFCR : return "PPCISD::MFCR" ; case PPCISD :: VCMP : return "PPCISD::VCMP" ; case PPCISD :: VCMPo : return "PPCISD::VCMPo" ; case PPCISD :: LBRX : return "PPCISD::LBRX" ; case PPCISD :: STBRX : return "PPCISD::STBRX" ; case PPCISD :: LARX : return "PPCISD::LARX" ; case PPCISD :: STCX : return "PPCISD::STCX" ; case PPCISD :: COND_BRANCH : return "PPCISD::COND_BRANCH" ; case PPCISD :: MFFS : return "PPCISD::MFFS" ; case PPCISD :: MTFSB0 : return "PPCISD::MTFSB0" ; case PPCISD :: MTFSB1 : return "PPCISD::MTFSB1" ; case PPCISD :: FADDRTZ : return "PPCISD::FADDRTZ" ; case PPCISD :: MTFSF : return "PPCISD::MTFSF" ; case PPCISD :: TC_RETURN : return "PPCISD::TC_RETURN" ; case PPCISD :: CR6SET : return "PPCISD::CR6SET" ; case PPCISD :: CR6UNSET : return "PPCISD::CR6UNSET" ; case PPCISD :: ADDIS_TOC_HA : return "PPCISD::ADDIS_TOC_HA" ; case PPCISD :: LD_TOC_L : return "PPCISD::LD_TOC_L" ; case PPCISD :: ADDI_TOC_L : return "PPCISD::ADDI_TOC_L" ; case PPCISD :: ADDIS_GOT_TPREL_HA : return "PPCISD::ADDIS_GOT_TPREL_HA" ; case PPCISD :: LD_GOT_TPREL_L : return "PPCISD::LD_GOT_TPREL_L" ; case PPCISD :: ADD_TLS : return "PPCISD::ADD_TLS" ; case PPCISD :: ADDIS_TLSGD_HA : return "PPCISD::ADDIS_TLSGD_HA" ; case PPCISD :: ADDI_TLSGD_L : return "PPCISD::ADDI_TLSGD_L" ; case PPCISD :: GET_TLS_ADDR : return "PPCISD::GET_TLS_ADDR" ; case PPCISD :: ADDIS_TLSLD_HA : return "PPCISD::ADDIS_TLSLD_HA" ; case PPCISD :: ADDI_TLSLD_L : return "PPCISD::ADDI_TLSLD_L" ; case PPCISD :: GET_TLSLD_ADDR : return "PPCISD::GET_TLSLD_ADDR" ; case PPCISD :: ADDIS_DTPREL_HA : return "PPCISD::ADDIS_DTPREL_HA" ; case PPCISD :: ADDI_DTPREL_L : return "PPCISD::ADDI_DTPREL_L" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s>
SDValue
LanaiTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
IsVarArg
,
Ins
,
DL
,
DAG
,
InVals
)
;
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

Lanai
Lanai
ISD::InputArg
"Unsupported calling convention"


<s>
int
SparcRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
assert
(
0
&&
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == 8 ; return createELFObjectWriter ( new PPCELFObjectWriter ( is64 , OSType , is64 ? ELF :: EM_PPC64 : ELF :: EM_PPC , true , false ) , OS , false ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> const MCExpr * getSubExpr ( ) const { return Expr ; } </s>

getSubExpr - Get the child of this expression .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
STI
.
getFramePointerReg
(
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasD32
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
markSuperRegs
(
Reserved
,
ARM
::
ZR
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
int
AArch64InstrInfo
::
getMemScale
(
unsigned
Opc
)
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
LDURBBi
:
case
AArch64
::
LDRSBWui
:
case
AArch64
::
LDURSBWi
:
case
AArch64
::
STRBBui
:
case
AArch64
::
STURBBi
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
LDURHHi
:
case
AArch64
::
LDRSHWui
:
case
AArch64
::
LDURSHWi
:
case
AArch64
::
STRHHui
:
case
AArch64
::
STURHHi
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
case
AArch64
::
STGOffset
:
case
AArch64
::
STZGOffset
:
case
AArch64
::
ST2GOffset
:
case
AArch64
::
STZ2GOffset
:
case
AArch64
::
STGPi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


<s>
static
void
arm_option_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
int
flags
=
ptr
->
x_target_flags
;
const
char
*
fpu_name
;
fpu_name
=
(
ptr
->
x_arm_fpu_index
==
TARGET_FPU_auto
"auto"
:
all_fpus
[
ptr
->
x_arm_fpu_index
]
.
name
)
;
fprintf
(
file
,
"%*sselected arch %s\n"
,
indent
,
""
,
TARGET_THUMB2_P
(
flags
)
"thumb2"
:
TARGET_THUMB_P
(
flags
)
"thumb1"
:
"arm"
)
;
fprintf
(
file
,
"%*sselected fpu %s\n"
,
indent
,
""
,
fpu_name
)
;
}
</s>

arm
"auto"
"%*sselected arch %s\n"
""
"thumb2"
"thumb1"
"arm"
"%*sselected fpu %s\n"
""


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> DecodeStatus PPCDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = 4 ; if ( Bytes . size ( ) < 4 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ 0 ] << 24 ) | ( Bytes [ 1 ] << 16 ) | ( Bytes [ 2 ] << 8 ) | ( Bytes [ 3 ] << 0 ) ; if ( ( STI . getFeatureBits ( ) & PPC :: FeatureQPX ) != 0 ) { DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) return result ; MI . clear ( ) ; } return decodeInstruction ( DecoderTable32 , MI , Inst , Address , this , STI ) ; } </s>

Returns the disassembly of a single instruction .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
char
*
output_e500_flip_gt_bit
(
rtx
dst
,
rtx
src
)
{
static
char
string
[
64
]
;
int
a
,
b
;
gcc_assert
(
GET_CODE
(
dst
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
dst
)
)
&&
GET_CODE
(
src
)
==
REG
&&
CR_REGNO_P
(
REGNO
(
src
)
)
)
;
a
=
4
*
(
REGNO
(
dst
)
CR0_REGNO
)
+
1
;
b
=
4
*
(
REGNO
(
src
)
CR0_REGNO
)
+
1
;
sprintf
(
string
,
"crnot %d,%d"
,
a
,
b
)
;
return
string
;
}
</s>

Return the string to flip the GT bit on a CR .


<s>
static
int
rs6000_arg_partial_bytes
(
cumulative_args_t
cum_v
,
machine_mode
mode
,
tree
type
,
bool
named
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
cum_v
)
;
bool
passed_in_gprs
=
true
;
int
ret
=
0
;
int
align_words
;
machine_mode
elt_mode
;
int
n_elts
;
rs6000_discover_homogeneous_aggregate
(
mode
,
type
,
&
elt_mode
,
&
n_elts
)
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
elt_mode
,
named
)
)
{
if
(
TARGET_64BIT
&&
!
cum
->
prototype
&&
(
!
cum
->
libcall
||
!
FLOAT128_VECTOR_P
(
elt_mode
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
vregno
+
n_elts
>
ALTIVEC_ARG_MAX_REG
+
1
)
ret
=
(
ALTIVEC_ARG_MAX_REG
+
1
cum
->
vregno
)
*
16
;
}
if
(
TARGET_MACHO
&&
rs6000_darwin64_struct_check_p
(
mode
,
type
)
)
return
0
;
align_words
=
rs6000_parm_start
(
mode
,
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
elt_mode
)
&&
!
(
TARGET_AIX
&&
!
TARGET_ELF
&&
type
!=
&&
AGGREGATE_TYPE_P
(
type
)
)
)
{
unsigned
long
n_fpreg
=
(
GET_MODE_SIZE
(
elt_mode
)
+
7
)
>>
3
;
if
(
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
fregno
+
n_elts
*
n_fpreg
>
FP_ARG_MAX_REG
+
1
)
{
int
fpr
=
(
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
MIN
(
8
,
GET_MODE_SIZE
(
elt_mode
)
)
)
;
int
fpr_words
=
fpr
/
(
TARGET_32BIT
4
:
8
)
;
if
(
align_words
+
fpr_words
<
GP_ARG_NUM_REG
)
passed_in_gprs
=
true
;
else
ret
=
fpr
;
}
}
if
(
passed_in_gprs
&&
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
mode
,
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s> static rtx ix86_load_returned_bounds ( rtx slot ) { rtx res ; gcc_assert ( REG_P ( slot ) ) ; res = gen_reg_rtx ( BNDmode ) ; emit_move_insn ( res , slot ) ; return res ; } </s>

Load and return bounds returned by function in SLOT .


<s> static bool mips_refers_to_kernel_reg_p ( const_rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) if ( REG_P ( * iter ) && KERNEL_REG_P ( REGNO ( * iter ) ) ) return true ; return false ; } </s>

Return true if X contains a kernel register .


<s> static inline hashval_t hash ( tree_map * m ) { return m -> hash ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> bool rs6000_is_valid_mask ( rtx mask , int * b , int * e , machine_mode mode ) { unsigned HOST_WIDE_INT val = INTVAL ( mask ) ; unsigned HOST_WIDE_INT bit ; int nb , ne ; int n = GET_MODE_PRECISION ( mode ) ; if ( mode != DImode && mode != SImode ) return false ; if ( INTVAL ( mask ) >= 0 ) { bit = val & - val ; ne = exact_log2 ( bit ) ; nb = exact_log2 ( val + bit ) ; } else if ( val + 1 == 0 ) { nb = n ; ne = 0 ; } else if ( val & 1 ) { val = ~ val ; bit = val & - val ; nb = exact_log2 ( bit ) ; ne = exact_log2 ( val + bit ) ; } else { bit = val & - val ; ne = exact_log2 ( bit ) ; if ( val + bit == 0 ) nb = n ; else nb = 0 ; } nb -- ; if ( nb < 0 || ne < 0 || nb >= n || ne >= n ) return false ; if ( b ) * b = nb ; if ( e ) * e = ne ; return true ; } </s>

Return whether MASK ( a CONST_INT ) is a valid mask for any rlwinm , rldicl , rldicr , or rldic instruction in mode MODE . If so , if E is not zero , store there the bit offset ( counted from the right ) where the single stretch of 1 bits begins ; and similarly for B , the bit offset where it ends .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; unsigned SlotSize = STI . is64Bit ( ) ? 8 : 4 ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned CalleeFrameSize = 0 ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>


<s> bool X86FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return X86SelectLoad ( I ) ; case Instruction :: Store : return X86SelectStore ( I ) ; case Instruction :: Ret : return X86SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return X86SelectCmp ( I ) ; case Instruction :: ZExt : return X86SelectZExt ( I ) ; case Instruction :: Br : return X86SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return X86SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return X86SelectDivRem ( I ) ; case Instruction :: Select : return X86SelectSelect ( I ) ; case Instruction :: Trunc : return X86SelectTrunc ( I ) ; case Instruction :: FPExt : return X86SelectFPExt ( I ) ; case Instruction :: FPTrunc : return X86SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return X86SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return X86SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return X86SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } case Instruction :: BitCast : { if ( ! Subtarget -> hasSSE2 ( ) ) return false ; EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( 0 ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( ! SrcVT . isSimple ( ) || ! DstVT . isSimple ( ) ) return false ; if ( ! SrcVT . is128BitVector ( ) && ! ( Subtarget -> hasAVX ( ) && SrcVT . is256BitVector ( ) ) ) return false ; unsigned Reg = getRegForValue ( I -> getOperand ( 0 ) ) ; if ( Reg == 0 ) return false ; updateValueMap ( I , Reg ) ; return true ; } } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s>
unsigned
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
SelectionDAG
&
DAG
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .

ARM
ARM
"sp"
ARM::SP
0
"Invalid register name \""
"\"."


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; int Offset = 0 ; for ( int i = FFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - FFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = FFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( FFI -> isDeadObjectIndex ( i ) ) continue ; Offset += FFI -> getObjectSize ( i ) ; unsigned Align = FFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; } return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s> bool ix86_fp_jump_nontrivial_p ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_CMOVE ) return true ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ; return bypass_code != UNKNOWN || second_code != UNKNOWN ; } </s>

Return true if the CODE will result in nontrivial jump sequence .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to have vector type TYPE , in cases where this requirement holds for all uses of the function . Return true if the argument has the right form , otherwise report an appropriate error .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
,
MipsTargetMachine
*
_TM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMips16HardFloat
(
Mips16HardFloat
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
AllowMixed16_32
(
Mixed16_32
|
Mips_Os16
)
,
Os16
(
Mips_Os16
)
,
HasMSA
(
false
)
,
RM
(
_RM
)
,
OverrideMode
(
NoOverride
)
,
TM
(
_TM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
PreviousInMips16Mode
=
InMips16Mode
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
if
(
inMips16Mode
(
)
)
HasBitCount
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"
Mips


<s> bool ARMBaseInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) ) return true ; MachineBasicBlock :: const_iterator I = MI ; while ( ++ I != MBB -> end ( ) && I -> isDebugValue ( ) ) ; if ( I != MBB -> end ( ) && I -> getOpcode ( ) == ARM :: t2IT ) return true ; if ( MI -> definesRegister ( ARM :: SP ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s>
DEBUG_FUNCTION
void
debug_ready_dispatch
(
void
)
{
int
i
;
int
no_ready
=
number_in_ready
(
)
;
fprintf
(
stdout
,
"Number of ready: %d\n"
,
no_ready
)
;
for
(
i
=
0
;
i
<
no_ready
;
i
++
)
debug_insn_dispatch_info_file
(
stdout
,
get_ready_element
(
i
)
)
;
}
</s>

Print to STDERR the status of the ready list with respect to dispatch windows .


<s> static void aarch64_add_offset_1 ( scalar_int_mode mode , rtx dest , rtx src , HOST_WIDE_INT offset , rtx temp1 , bool frame_related_p , bool emit_move_imm ) { gcc_assert ( emit_move_imm || temp1 != NULL_RTX ) ; gcc_assert ( temp1 == NULL_RTX || ! reg_overlap_mentioned_p ( temp1 , src ) ) ; unsigned HOST_WIDE_INT moffset = absu_hwi ( offset ) ; rtx_insn * insn ; if ( ! moffset ) { if ( ! rtx_equal_p ( dest , src ) ) { insn = emit_insn ( gen_rtx_SET ( dest , src ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; } return ; } if ( aarch64_uimm12_shift ( moffset ) ) { insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( moffset < 0x1000000 && ( ( ! temp1 && ! can_create_pseudo_p ( ) ) || ! aarch64_move_imm ( moffset , mode ) ) ) { HOST_WIDE_INT low_off = moffset & 0xfff ; low_off = offset < 0 ? - low_off : low_off ; insn = emit_insn ( gen_add3_insn ( dest , src , GEN_INT ( low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; insn = emit_insn ( gen_add2_insn ( dest , GEN_INT ( offset - low_off ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; return ; } if ( emit_move_imm ) { gcc_assert ( temp1 != NULL_RTX || can_create_pseudo_p ( ) ) ; temp1 = aarch64_force_temporary ( mode , temp1 , gen_int_mode ( moffset , mode ) ) ; } insn = emit_insn ( offset < 0 ? gen_sub3_insn ( dest , src , temp1 ) : gen_add3_insn ( dest , src , temp1 ) ) ; if ( frame_related_p ) { RTX_FRAME_RELATED_P ( insn ) = frame_related_p ; rtx adj = plus_constant ( mode , src , offset ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( dest , adj ) ) ; } } </s>

A subroutine of aarch64_add_offset . Set DEST to SRC + OFFSET for a non-polynomial OFFSET . MODE is the mode of the addition . FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should be set and CFA adjustments added to the generated instructions . TEMP1 , if nonnull , is a register of mode MODE that can be used as a temporary if register allocation is already complete . This temporary register may overlap DEST but must not overlap SRC . If TEMP1 is known to hold abs ( OFFSET ) , EMIT_MOVE_IMM can be set to false to avoid emitting the immediate again . Since this function may be used to adjust the stack pointer , we must ensure that it can not cause transient stack deallocation ( for example by first incrementing SP and then decrementing when adjusting by a large immediate ) .


<s> int ix86_frame_pointer_required ( void ) { if ( cfun -> machine -> accesses_prev_frame ) return 1 ; if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return 1 ; if ( TARGET_OMIT_LEAF_FRAME_POINTER && ( ! current_function_is_leaf ) ) return 1 ; if ( current_function_profile ) return 1 ; return 0 ; } </s>

Value should be nonzero if functions must have frame pointers . Zero means the frame pointer need not be set up ( and parms may be accessed via the stack pointer ) in functions that seem suitable .


<s> void CSKYAsmPrinter :: emitEndOfAsmFile ( Module & M ) { CSKYTargetStreamer & CTS = static_cast < CSKYTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) CTS . finishAttributeSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


Return an array that contains the bitmask target flag values and their names .

ARM ARM ARM "arm-got" "arm-sbrel" "arm-dllimport" "arm-secrel" "arm-nonlazy"


<s>
bool
ARMAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
&&
MO
.
getReg
(
)
!=
ARM
::
CPSR
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
GetSymbolRef
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
GetSymbolRef
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
APFloat
Val
=
MO
.
getFPImm
(
)
->
getValueAPF
(
)
;
bool
ignored
;
Val
.
convert
(
APFloat
::
IEEEdouble
,
APFloat
::
rmTowardZero
,
&
ignored
)
;
MCOp
=
MCOperand
::
CreateFPImm
(
Val
.
convertToDouble
(
)
)
;
break
;
}
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

ARM
ARM
"unknown operand type"
ARM::CPSR
"Subregs should be eliminated!"


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static unsigned ix86_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = 0 ; tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( TARGET_BONNELL && kind == vector_stmt && vectype && GET_MODE_INNER ( TYPE_MODE ( vectype ) ) == DFmode ) stmt_cost *= 5 ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; if ( ( TARGET_SILVERMONT || TARGET_INTEL ) && stmt_info && stmt_info -> stmt ) { tree lhs_op = gimple_get_lhs ( stmt_info -> stmt ) ; if ( lhs_op && TREE_CODE ( TREE_TYPE ( lhs_op ) ) == INTEGER_TYPE ) retval = ( retval * 17 ) / 10 ; } cost [ where ] += retval ; return retval ; } </s>


"stack limit expression is not supported"

Emit the correct code for allocating stack space , as insns . If COPY_R12 , make sure a copy of the old frame is left in r12 . The generated code may use hard register 0 as a temporary .


<s>
StringRef
getPassName
(
)
const
override
{
return
"DLX Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> TargetLowering :: AtomicExpansionKind ARMTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { unsigned Size = AI -> getOperand ( 1 ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; bool HasAtomicCmpXchg ; if ( Subtarget -> isMClass ( ) ) HasAtomicCmpXchg = Subtarget -> hasV8MBaselineOps ( ) ; else if ( Subtarget -> isThumb ( ) ) HasAtomicCmpXchg = Subtarget -> hasV7Ops ( ) ; else HasAtomicCmpXchg = Subtarget -> hasV6Ops ( ) ; if ( getTargetMachine ( ) . getOptLevel ( ) != 0 && HasAtomicCmpXchg && Size <= ( Subtarget -> isMClass ( ) ? 32U : 64U ) ) return AtomicExpansionKind :: LLSC ; return AtomicExpansionKind :: None ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( unsigned I = 0 ; I < 4 ; ++ I ) { Buffer [ I ] = uint8_t ( Inst ) ; Inst >>= 8 ; } EmitA64MappingSymbol ( ) ; MCELFStreamer :: emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> bool PPCTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return ( EnableQuadPrecision && Subtarget . hasP9Vector ( ) ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> const char * ARMTargetLowering :: LowerXConstraint ( EVT ConstraintVT ) const { if ( ! Subtarget -> hasVFP2 ( ) ) return "r" ; if ( ConstraintVT . isFloatingPoint ( ) ) return "w" ; if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == 64 || ConstraintVT . getSizeInBits ( ) == 128 ) ) return "w" ; return "r" ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


"Stack realignment in presence of dynamic allocas is not supported with"

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"%<target_clones%> attribute needs GLIBC (2.23 and newer) that "

"multiversioning needs %<ifunc%> which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> static unsigned int aarch64_sve_rev_unspec ( machine_mode mode ) { switch ( GET_MODE_UNIT_SIZE ( mode ) ) { case 1 : return UNSPEC_REVB ; case 2 : return UNSPEC_REVH ; case 4 : return UNSPEC_REVW ; } gcc_unreachable ( ) ; } </s>

Return the SVE REV [ BHW ] unspec for reversing quantites of mode MODE stored in wider integer containers .


<s> static inline SlotWithTag getEmptyKey ( ) { return { - 2 , - 2 ; } </s>

Empty key : no key should be generated that has no DILocalVariable .


<s> static MipsOperand * CreateMem ( MipsOperand * Base , const MCExpr * Off , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { MipsOperand * Op = new MipsOperand ( k_Memory , Parser ) ; Op -> Mem . Base = Base ; Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>


<s> SMLoc getStartLoc ( ) const { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


"missing value in %<target()%> pragma or attribute"

"invalid value (\"%s\") in %<target()%> pragma or attribute"

Parse an architecture extensions target attribute string specified in STR . For example `` +fp+nosimd '' . Show any errors if needed . Return TRUE if successful . Update aarch64_isa_flags to reflect the ISA features modified . PRAGMA_OR_ATTR is used in potential error messages .


<s> const uint32_t * SparcRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> virtual const OR1KRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( "disable-tail-calls" ) ; if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == "true" ) return false ; return ! Subtarget -> isThumb1Only ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> int const_ok_for_op ( HOST_WIDE_INT i , enum rtx_code code ) { if ( const_ok_for_arm ( i ) ) return 1 ; switch ( code ) { case SET : if ( TARGET_HAVE_MOVT && ( i & 0xffff0000 ) == 0 ) return 1 ; else return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; case PLUS : if ( TARGET_THUMB2 && ( ( i & 0xfffff000 ) == 0 || ( ( - i ) & 0xfffff000 ) == 0 ) ) return 1 ; case COMPARE : case EQ : case NE : case GT : case LE : case LT : case GE : case GEU : case LTU : case GTU : case LEU : case UNORDERED : case ORDERED : case UNEQ : case UNGE : case UNLT : case UNGT : case UNLE : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : return 0 ; case IOR : if ( TARGET_THUMB2 ) return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; return 0 ; case AND : return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if I is a valid constant for the operation CODE .


<s> static rtx pseudo_reg_set ( rtx_insn * insn ) { rtx set = single_set ( insn ) ; if ( ! set ) return NULL ; machine_mode mode = TARGET_64BIT ? TImode : DImode ; if ( REG_P ( SET_SRC ( set ) ) && ! HARD_REGISTER_P ( SET_SRC ( set ) ) && push_operand ( SET_DEST ( set ) , mode ) ) return set ; df_ref ref ; FOR_EACH_INSN_DEF ( ref , insn ) if ( HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) && ! DF_REF_FLAGS_IS_SET ( ref , DF_REF_MUST_CLOBBER ) && DF_REF_REGNO ( ref ) != FLAGS_REG ) return NULL ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) ) return NULL ; return set ; } </s>

Return the SET expression if INSN does n't reference hard register . Return NULL if INSN uses or defines a hard register , excluding pseudo register pushes , hard register uses in a memory address , clobbers and flags definitions .


<s> static unsigned long get_csky_current_func_type ( void ) { if ( CSKY_FUNCTION_TYPE ( cfun -> machine -> func_type ) == CSKY_FT_UNKNOWN ) { unsigned long type = CSKY_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( "naked" , attr ) ; if ( a != NULL_TREE ) type |= CSKY_FT_NAKED ; a = lookup_attribute ( "isr" , attr ) ; if ( a == NULL_TREE ) a = lookup_attribute ( "interrupt" , attr ) ; if ( a == NULL_TREE ) type |= CSKY_FT_NORMAL ; else type |= get_csky_isr_type ( TREE_VALUE ( a ) ) ; cfun -> machine -> func_type = type ; } return cfun -> machine -> func_type ; } </s>

Classify cfun as a normal function or some sort of interrupt handler , and set the corresponding bits in cfun- > machine- > func_type .


<s>
bool
ARMDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
char
ConstraintCode
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
assert
(
ConstraintCode
==
'm'
&&
"unexpected asm memory constraint"
)
;
OutOps
.
push_back
(
Op
)
;
return
false
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .

ARM
ARM
"unexpected asm memory constraint"


<s> virtual unsigned int execute ( function * ) { return aarch64_do_track_speculation ( ) ; } </s>


<s> static rtx arm_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target , int do_load ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( do_load ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; else { if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; } pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of arm_expand_builtin to take care of unop insns .


<s> static void abort_with_insn ( rtx insn , const char * reason ) { error ( reason ) ; debug_rtx ( insn ) ; fancy_abort ( __FILE__ , __LINE__ , __FUNCTION__ ) ; } </s>

Abort after printing out a specific insn .


<s> void Note ( SMLoc L , const Twine & Msg , SMRange Range = None ) { return getParser ( ) . Note ( L , Msg , Range ) ; } </s>

Emit a note at the location L , with the message Msg .


<s> static char * construct_fntype_id ( prototype * protoptr ) { int len = protoptr -> nargs ? ( protoptr -> nargs + 1 ) * 9 + 6 : 17 ; char * buf = ( char * ) malloc ( len ) ; int bufi = 0 ; if ( protoptr -> rettype . ispointer ) buf [ bufi ++ ] = 'p' ; if ( protoptr -> rettype . isvoid ) buf [ bufi ++ ] = 'v' ; else { if ( protoptr -> rettype . isunsigned ) buf [ bufi ++ ] = 'u' ; if ( protoptr -> rettype . isvector ) complete_vector_type ( & protoptr -> rettype , buf , & bufi ) ; else complete_base_type ( & protoptr -> rettype , buf , & bufi ) ; } memcpy ( & buf [ bufi ] , "_ftype" , 6 ) ; bufi += 6 ; if ( ! protoptr -> nargs ) { memcpy ( & buf [ bufi ] , "_v" , 2 ) ; bufi += 2 ; } else { typelist * argptr = protoptr -> args ; for ( int i = 0 ; i < protoptr -> nargs ; i ++ , argptr = argptr -> next ) { assert ( argptr ) ; buf [ bufi ++ ] = '_' ; if ( argptr -> info . isconst && argptr -> info . base == BT_INT && ! argptr -> info . ispointer ) { buf [ bufi ++ ] = 'c' ; buf [ bufi ++ ] = 'i' ; continue ; } if ( argptr -> info . ispointer ) { if ( argptr -> info . isvoid ) { if ( argptr -> info . isconst ) { memcpy ( & buf [ bufi ] , "pcvoid" , 6 ) ; bufi += 6 ; continue ; } else { buf [ bufi ++ ] = 'p' ; buf [ bufi ++ ] = 'v' ; continue ; } } else buf [ bufi ++ ] = 'p' ; } if ( argptr -> info . isunsigned ) buf [ bufi ++ ] = 'u' ; if ( argptr -> info . isvector ) complete_vector_type ( & argptr -> info , buf , & bufi ) ; else complete_base_type ( & argptr -> info , buf , & bufi ) ; } assert ( ! argptr ) ; } buf [ bufi ] = '\0' ; rbt_insert ( & fntype_rbt , buf ) ; return buf ; } </s>

Build a function type descriptor identifier from the return type and argument types described by PROTOPTR , and store it if it does not already exist . Return the identifier .


<s> static unsigned getReg ( const void * D , unsigned RC , unsigned RegNo ) { const AArch64Disassembler * Dis = static_cast < const AArch64Disassembler * > ( D ) ; const MCRegisterInfo * RegInfo = Dis -> getContext ( ) . getRegisterInfo ( ) ; return RegInfo -> getRegClass ( RC ) . getRegister ( RegNo ) ; } </s>

Returns the register associated with this edge .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { const PPCSubtarget & ST = C -> MF -> getSubtarget < PPCSubtarget > ( ) ; if ( ST . usePPCPreRASchedStrategy ( ) ) return createPPCMachineScheduler ( C ) ; return nullptr ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasV4TOps ( false ) , HasV5TOps ( false ) , HasV5TEOps ( false ) , HasV6Ops ( false ) , HasV6T2Ops ( false ) , HasV7Ops ( false ) , HasVFPv2 ( false ) , HasVFPv3 ( false ) , HasVFPv4 ( false ) , HasNEON ( false ) , HasNEONVFPv4 ( false ) , UseNEONForSinglePrecisionFP ( false ) , SlowFPVMLx ( false ) , HasVMLxForwarding ( false ) , SlowFPBrcc ( false ) , InThumbMode ( false ) , HasThumb2 ( false ) , IsMClass ( false ) , NoARM ( false ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( false ) , SupportsTailCall ( false ) , HasFP16 ( false ) , HasD16 ( false ) , HasHardwareDivide ( false ) , HasT2ExtractPack ( false ) , HasDataBarrier ( false ) , Pref32BitThumb ( false ) , AvoidCPSRPartialUpdate ( false ) , HasMPExtension ( false ) , FPOnlySP ( false ) , AllowsUnalignedMem ( false ) , Thumb2DSP ( false ) , stackAlignment ( 4 ) , CPUString ( CPU ) , TargetTriple ( TT ) , TargetABI ( ARM_ABI_APCS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; std :: string ArchFS = ARM_MC :: ParseARMTriple ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + "," + FS ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; if ( ! HasV6T2Ops && hasThumb2 ( ) ) HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; computeIssueWidth ( ) ; if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( ! isTargetIOS ( ) ) UseMovt = hasV6T2Ops ( ) ; else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; UseMovt = DarwinUseMOVT && hasV6T2Ops ( ) ; const Triple & T = getTargetTriple ( ) ; SupportsTailCall = ! T . isOSVersionLT ( 5 , 0 ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; if ( ! StrictAlign && hasV6Ops ( ) && isTargetDarwin ( ) ) AllowsUnalignedMem = true ; } </s>

This constructor initializes the data members to match that of the specified triple .

ARM ARM ARM ARM ARM ARM 4 ARM "generic" ARM ARM "," "eabi" ARM 8 5 0


<s> static const MCAsmInfo * createMCAsmInfo ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; switch ( TheTriple . getOS ( ) ) { case Triple :: Darwin : return new X86MCAsmInfoDarwin ( TheTriple ) ; case Triple :: MinGW32 : case Triple :: MinGW64 : case Triple :: Cygwin : case Triple :: Win32 : return new X86MCAsmInfoCOFF ( TheTriple ) ; default : return new X86ELFMCAsmInfo ( TheTriple ) ; } } </s>

createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple .


<s> SDNode * SparcDAGToDAGISel :: getGlobalBaseReg ( ) { MachineFunction * MF = BB -> getParent ( ) ; unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static bool split_stack_arg_pointer_used_p ( void ) { if ( cfun -> machine -> split_stack_arg_pointer != NULL_RTX && ( ! REG_P ( cfun -> machine -> split_stack_arg_pointer ) || HARD_REGISTER_P ( cfun -> machine -> split_stack_arg_pointer ) ) ) return true ; rtx_insn * insn ; basic_block bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; FOR_BB_INSNS ( bb , insn ) if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) return false ; df_ref use ; FOR_EACH_INSN_USE ( use , insn ) { rtx x = DF_REF_REG ( use ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return true ; } df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) { rtx x = DF_REF_REG ( def ) ; if ( REG_P ( x ) && REGNO ( x ) == 12 ) return false ; } } return bitmap_bit_p ( DF_LR_OUT ( bb ) , 12 ) ; } </s>

Return whether the split-stack arg pointer ( r12 ) is used .


<s>
const
char
*
nds32_output_casesi
(
rtx
*
operands
)
{
output_asm_insn
(
"la\t$ta, %l1"
,
operands
)
;
output_asm_insn
(
"lw\t%2, [$ta + %0 << 2]"
,
operands
)
;
if
(
TARGET_16_BIT
)
return
"jr5\t%2"
;
else
return
"jr\t%2"
;
}
</s>

Function to generate normal jump table .


<s> bool SparcTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createSparcISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


Targets may add passes immediately before machine code is emitted in this callback .