<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; REAL_VALUE_TYPE rval ; REAL_VALUE_FROM_CONST_DOUBLE ( rval , elt ) ; assemble_real ( rval , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


Relax the instruction in the given fragment to the next wider instruction .


<s> bool X86TTIImpl :: isLegalMaskedGather ( Type * DataTy ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( isa < VectorType > ( DataTy ) ) { unsigned NumElts = DataTy -> getVectorNumElements ( ) ; if ( NumElts == 1 || ! isPowerOf2_32 ( NumElts ) ) return false ; } Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ; return IntWidth == 32 || IntWidth == 64 ; } </s>

Return true if the target supports masked gather .


<s> static void rs6000_elf_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( first && TREE_CODE ( decl ) == FUNCTION_DECL && ! TARGET_AIX && DEFAULT_ABI == ABI_AIX ) { rtx sym_ref = XEXP ( rtl , 0 ) ; size_t len = strlen ( XSTR ( sym_ref , 0 ) ) ; char * str = XALLOCAVEC ( char , len + 2 ) ; str [ 0 ] = '.' ; memcpy ( str + 1 , XSTR ( sym_ref , 0 ) , len + 1 ) ; XSTR ( sym_ref , 0 ) = ggc_alloc_string ( str , len + 1 ) ; } } </s>

For a SYMBOL_REF , set generic flags and then perform some target-specific processing . When the AIX ABI is requested on a non-AIX system , replace the function name with the real name ( with a leading . ) rather than the function descriptor name . This saves a lot of overriding code to read the prefixes .


<s> static rtx mips_call_tls_get_addr ( rtx sym , enum mips_symbol_type type , rtx v0 ) { rtx insn , loc , a0 ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! mips_tls_symbol ) mips_tls_symbol = init_one_libfunc ( "__tls_get_addr" ) ; loc = mips_unspec_address ( sym , type ) ; start_sequence ( ) ; emit_insn ( gen_rtx_SET ( Pmode , a0 , gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , loc ) ) ) ; insn = mips_expand_call ( MIPS_CALL_NORMAL , v0 , mips_tls_symbol , const0_rtx , NULL_RTX , false ) ; RTL_CONST_CALL_P ( insn ) = 1 ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ; insn = get_insns ( ) ; end_sequence ( ) ; return insn ; } </s>

Return an instruction sequence that calls __tls_get_addr . SYM is the TLS symbol we are referencing and TYPE is the symbol type to use ( either global dynamic or local dynamic ) . V0 is an RTX for the return value location .


<s>
static
void
split_words
(
const
std
::
string
&
val
,
std
::
set
<
std
::
string
>
&
result
)
{
size_t
cur
,
prev
=
0
;
std
::
string
word
;
while
(
(
cur
=
val
.
find_first_of
(
" \n"
,
prev
)
)
!=
std
::
string
::
npos
)
{
word
=
val
.
substr
(
prev
,
cur
prev
)
;
if
(
!
word
.
empty
(
)
)
result
.
insert
(
word
)
;
prev
=
cur
+
1
;
}
if
(
prev
!=
cur
)
result
.
insert
(
val
.
substr
(
prev
)
)
;
}
</s>

Splits and returns a string based on whitespace and return it as part of a set . Empty strings are ignored .


<s> static int ia32_multipass_dfa_lookahead ( void ) { if ( ix86_tune == PROCESSOR_PENTIUM ) return 2 ; if ( ix86_tune == PROCESSOR_PENTIUMPRO || ix86_tune == PROCESSOR_K6 ) return 1 ; else return 0 ; } </s>

How many alternative schedules to try . This should be as wide as the scheduling freedom in the DFA , but no wider . Making this value too large results extra work for the scheduler .


<s> static bool aarch64_advsimd_valid_immediate_hs ( unsigned int val32 , simd_immediate_info * info , enum simd_immediate_check which , simd_immediate_info :: insn_type insn ) { for ( unsigned int shift = 0 ; shift < 32 ; shift += 8 ) if ( ( val32 & ( 0xff << shift ) ) == val32 ) { if ( info ) * info = simd_immediate_info ( SImode , val32 >> shift , insn , simd_immediate_info :: LSL , shift ) ; return true ; } unsigned int imm16 = val32 & 0xffff ; if ( imm16 == ( val32 >> 16 ) ) for ( unsigned int shift = 0 ; shift < 16 ; shift += 8 ) if ( ( imm16 & ( 0xff << shift ) ) == imm16 ) { if ( info ) * info = simd_immediate_info ( HImode , imm16 >> shift , insn , simd_immediate_info :: LSL , shift ) ; return true ; } if ( which == AARCH64_CHECK_MOV ) for ( unsigned int shift = 8 ; shift < 24 ; shift += 8 ) { unsigned int low = ( 1 << shift ) - 1 ; if ( ( ( val32 & ( 0xff << shift ) ) | low ) == val32 ) { if ( info ) * info = simd_immediate_info ( SImode , val32 >> shift , insn , simd_immediate_info :: MSL , shift ) ; return true ; } } return false ; } </s>

Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate for the Advanced SIMD operation described by WHICH and INSN . If INFO is nonnull , use it to describe valid immediates .


<s> static void output_addr_reloc ( FILE * stream , rtx x , HOST_WIDE_INT add , const char * reloc ) { if ( * reloc ) { fputs ( reloc , stream ) ; fputc ( '(' , stream ) ; } output_addr_const ( stream , x ) ; if ( add ) { if ( add > 0 ) fputc ( '+' , stream ) ; fprintf ( stream , HOST_WIDE_INT_PRINT_DEC , add ) ; } if ( * reloc ) fputc ( ')' , stream ) ; } </s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s>
void
X86TargetLowering
::
emitBitTestAtomicRMWIntrinsic
(
AtomicRMWInst
*
AI
)
const
{
IRBuilder
<
>
Builder
(
AI
)
;
Intrinsic
::
ID
IID
=
Intrinsic
::
not_intrinsic
;
switch
(
AI
->
getOperation
(
)
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Or
:
IID
=
Intrinsic
::
x86_atomic_bts
;
break
;
case
AtomicRMWInst
::
Xor
:
IID
=
Intrinsic
::
x86_atomic_btc
;
break
;
case
AtomicRMWInst
::
And
:
IID
=
Intrinsic
::
x86_atomic_btr
;
break
;
}
Instruction
*
I
=
AI
->
user_back
(
)
;
LLVMContext
&
Ctx
=
AI
->
getContext
(
)
;
unsigned
Imm
=
countTrailingZeros
(
cast
<
ConstantInt
>
(
I
->
getOperand
(
1
)
)
->
getZExtValue
(
)
)
;
Function
*
BitTest
=
Intrinsic
::
getDeclaration
(
AI
->
getModule
(
)
,
IID
,
AI
->
getType
(
)
)
;
Value
*
Addr
=
Builder
.
CreatePointerCast
(
AI
->
getPointerOperand
(
)
,
Type
::
getInt8PtrTy
(
Ctx
)
)
;
Value
*
Result
=
Builder
.
CreateCall
(
BitTest
,
{
Addr
,
Builder
.
getInt8
(
Imm
)
}
)
;
I
->
replaceAllUsesWith
(
Result
)
;
I
->
eraseFromParent
(
)
;
AI
->
eraseFromParent
(
)
;
}
</s>

Perform a bit test atomicrmw using a target-specific intrinsic .


<s> rtx arm_return_addr ( int count , rtx frame ATTRIBUTE_UNUSED ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; } </s>

Return an RTX indicating where the return address to the calling function can be found .


<s> static rtx sparc_builtin_saveregs ( void ) { int first_reg = crtl -> args . info . words ; rtx address ; int regno ; for ( regno = first_reg ; regno < SPARC_INT_ARG_MAX ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , SPARC_INCOMING_INT_ARG_FIRST + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + UNITS_PER_WORD * first_reg ) ) ; return address ; } </s>

Do what is necessary for ` va_start ' . We look at the current function to determine if stdarg or varargs is used and return the address of the first unnamed parameter .


<s>
bool
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
override
{
switch
(
ConstraintID
)
{
default
:
errs
(
)
<<
"ConstraintID: "
<<
ConstraintID
<<
"\n"
;
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_es
:
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
case
InlineAsm
::
Constraint_Q
:
case
InlineAsm
::
Constraint_Z
:
case
InlineAsm
::
Constraint_Zy
:
const
TargetRegisterInfo
*
TRI
=
PPCSubTarget
->
getRegisterInfo
(
)
;
const
TargetRegisterClass
*
TRC
=
TRI
->
getPointerRegClass
(
*
MF
,
1
)
;
SDLoc
dl
(
Op
)
;
SDValue
RC
=
CurDAG
->
getTargetConstant
(
TRC
->
getID
(
)
,
dl
,
MVT
::
i32
)
;
SDValue
NewOp
=
SDValue
(
CurDAG
->
getMachineNode
(
TargetOpcode
::
COPY_TO_REGCLASS
,
dl
,
Op
.
getValueType
(
)
,
Op
,
RC
)
,
0
)
;
OutOps
.
push_back
(
NewOp
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> int const_ok_for_arm ( HOST_WIDE_INT i ) { int lowbit ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != 0 && ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != ( ( ~ ( unsigned HOST_WIDE_INT ) 0 ) & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) ) ) return FALSE ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xff ) == 0 ) return TRUE ; lowbit = ffs ( ( int ) i ) - 1 ; if ( TARGET_ARM ) lowbit &= ~ 1 ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) 0xff ) << lowbit ) ) == 0 ) return TRUE ; if ( TARGET_ARM ) { if ( lowbit <= 4 && ( ( i & ~ 0xc000003f ) == 0 || ( i & ~ 0xf000000f ) == 0 || ( i & ~ 0xfc000003 ) == 0 ) ) return TRUE ; } else if ( TARGET_THUMB2 ) { HOST_WIDE_INT v ; v = i & 0xff ; v |= v << 16 ; if ( i == v || i == ( v | ( v << 8 ) ) ) return TRUE ; v = i & 0xff00 ; v |= v << 16 ; if ( i == v ) return TRUE ; } else if ( TARGET_HAVE_MOVT ) { if ( i > 0xffff ) return FALSE ; else return TRUE ; } return FALSE ; } </s>

Return TRUE if int I is a valid immediate ARM constant .


"\nRelevant insns with their flag settings\n\n"


<s> bool aarch64_madd_needs_nop ( rtx_insn * insn ) { enum attr_type attr_type ; rtx_insn * prev ; rtx body ; if ( ! aarch64_fix_a53_err835769 ) return false ; if ( recog_memoized ( insn ) < 0 ) return false ; attr_type = get_attr_type ( insn ) ; if ( ! is_madd_op ( attr_type ) ) return false ; prev = aarch64_prev_real_insn ( insn ) ; extract_constrain_insn_cached ( insn ) ; if ( ! prev || ! has_memory_op ( prev ) ) return false ; body = single_set ( prev ) ; if ( GET_MODE ( recog_data . operand [ 0 ] ) == DImode && ( ! body || ! dep_between_memop_and_curr ( body ) ) ) return true ; return false ; } </s>

When working around the Cortex-A53 erratum 835769 , given rtx_insn INSN , return true if it is a 64-bit multiply-accumulate instruction and has a preceding memory instruction such that a NOP should be inserted between them .


<s> unsigned getCSRFirstUseCost ( const MachineFunction & MF ) const override { return 5 ; } </s>

Allow the target to override the cost of using a callee-saved register for the first time .


<s> HOST_WIDE_INT csky_initial_elimination_offset ( int from , int to ) { int offset ; csky_layout_stack_frame ( ) ; switch ( from ) { case FRAME_POINTER_REGNUM : case HARD_FRAME_POINTER_REGNUM : offset = cfun -> machine -> reg_offset ; break ; case ARG_POINTER_REGNUM : offset = cfun -> machine -> arg_offset ; break ; default : gcc_unreachable ( ) ; } if ( to == FRAME_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM ) offset -= cfun -> machine -> reg_offset ; return offset ; } </s>

Worker function for INITIAL_ELIMINATION_OFFSET macro . Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> bool ARMTTIImpl :: isLegalMaskedLoad ( Type * DataTy , MaybeAlign Alignment ) { if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( auto * VecTy = dyn_cast < VectorType > ( DataTy ) ) { if ( VecTy -> getNumElements ( ) == 2 ) return false ; unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != 128 && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == 32 && ( ! Alignment || Alignment >= 4 ) ) || ( EltWidth == 16 && ( ! Alignment || Alignment >= 2 ) ) || ( EltWidth == 8 ) ; } </s>

Return true if the target supports masked load .


<s> void validate_condition_mode ( enum rtx_code code , machine_mode mode ) { gcc_assert ( ( GET_RTX_CLASS ( code ) == RTX_COMPARE || GET_RTX_CLASS ( code ) == RTX_COMM_COMPARE ) && GET_MODE_CLASS ( mode ) == MODE_CC ) ; gcc_assert ( ( code != GT && code != LT && code != GE && code != LE ) || mode != CCUNSmode ) ; gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT && code != UNGT && code != UNLT ) ) ; gcc_assert ( mode != CCEQmode || code == EQ || code == NE ) ; } </s>

A validation routine : say whether CODE , a condition code , and MODE match . The other alternatives either do n't make sense or should never be generated .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> static int ix86_fp_comparison_cost ( enum rtx_code code ) { int fcomi_cost , sahf_cost , arithmetics_cost = 1024 ; int min ; fcomi_cost = ix86_fp_comparison_fcomi_cost ( code ) ; sahf_cost = ix86_fp_comparison_sahf_cost ( code ) ; min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost ( code ) ; if ( min > sahf_cost ) min = sahf_cost ; if ( min > fcomi_cost ) min = fcomi_cost ; return min ; } </s>

Compute cost of the comparison done using any method . See ix86_fp_comparison_arithmetics_cost for the metrics .


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getDataLayout
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> static void ix86_set_current_function ( tree fndecl ) { if ( fndecl == ix86_previous_fndecl ) return ; tree old_tree ; if ( ix86_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; if ( TARGET_64BIT && ( call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) ) reinit_regs ( ) ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> bool AArch64TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { CCAssignFn * RetCC = CCAssignFnForReturn ( CallConv ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> bool FalkorMarkStridedAccesses :: run ( ) { bool MadeChange = false ; for ( Loop * L : LI ) for ( auto LIt = df_begin ( L ) , LE = df_end ( L ) ; LIt != LE ; ++ LIt ) MadeChange |= runOnLoop ( * * LIt ) ; return MadeChange ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> rtx extract_shift_reg ( rtx alu_shift_rtx ) { alu_shift_rtx = extract_pattern_from_insn ( alu_shift_rtx ) ; rtx alu_rtx = SET_SRC ( alu_shift_rtx ) ; rtx shift_rtx ; if ( REG_P ( XEXP ( alu_rtx , 0 ) ) ) shift_rtx = XEXP ( alu_rtx , 1 ) ; else shift_rtx = XEXP ( alu_rtx , 0 ) ; return XEXP ( shift_rtx , 0 ) ; } </s>

Extract the register of the shift operand from an ALU_SHIFT rtx .


<s> static bool arm_cookie_has_size ( void ) { return TARGET_AAPCS_BASED ; } </s>

The EABI says that array cookies should also contain the element size .


<s> static rtx ix86_gen_TWO52 ( machine_mode mode ) { const struct real_format * fmt ; REAL_VALUE_TYPE TWO52r ; rtx TWO52 ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & TWO52r , fmt -> p - 1 , mode ) ; TWO52 = const_double_from_real_value ( TWO52r , mode ) ; TWO52 = force_reg ( mode , TWO52 ) ; return TWO52 ; } </s>

Generate and return a rtx of mode MODE for 2 * * n where n is the number of bits of the mantissa of MODE , which must be one of DFmode or SFmode .


<s> static unsigned int aarch64_sve_adjust_stmt_cost ( class vec_info * vinfo , vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , unsigned int stmt_cost ) { if ( kind == vector_stmt && aarch64_extending_load_p ( vinfo , stmt_info ) ) stmt_cost = 0 ; if ( kind == vector_stmt && aarch64_integer_truncation_p ( stmt_info ) ) stmt_cost = 0 ; if ( STMT_VINFO_GROUPED_ACCESS ( stmt_info ) ) { stmt_vec_info first = DR_GROUP_FIRST_ELEMENT ( stmt_info ) ; unsigned int count = DR_GROUP_SIZE ( first ) - DR_GROUP_GAP ( first ) ; unsigned int elt_bits = GET_MODE_UNIT_BITSIZE ( TYPE_MODE ( vectype ) ) ; if ( multiple_p ( count * elt_bits , 256 ) && aarch64_advsimd_ldp_stp_p ( kind , stmt_info ) ) stmt_cost *= 2 ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Adjust the cost as necessary for SVE targets .


<s> static rtx gen_load_pcrel_sym ( rtx op0 , rtx op1 , rtx op2 ) { int orig_flag_pic = flag_pic ; rtx insn ; flag_pic = 0 ; if ( TARGET_ARCH64 ) insn = gen_load_pcrel_symdi ( op0 , op1 , op2 , GEN_INT ( REGNO ( op0 ) ) ) ; else insn = gen_load_pcrel_symsi ( op0 , op1 , op2 , GEN_INT ( REGNO ( op0 ) ) ) ; flag_pic = orig_flag_pic ; return insn ; } </s>

Wrapper around the load_pcrel_sym { si , di } patterns .


<s> static unsigned int insn_is_load_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( GET_CODE ( SET_SRC ( body ) ) == MEM ) return 1 ; if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) == MEM ) return 1 ; return 0 ; } if ( GET_CODE ( body ) != PARALLEL ) return 0 ; rtx set = XVECEXP ( body , 0 , 0 ) ; if ( GET_CODE ( set ) == SET && GET_CODE ( SET_SRC ( set ) ) == MEM ) return 1 ; return 0 ; } </s>

Return 1 iff INSN is a load insn , including permuting loads that represent an lvxd2x instruction ; else return 0 .


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> bool X86InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; bool is64Bit = TM . getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ; unsigned Opc = is64Bit ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; BuildMI ( MBB , MI , DL , get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"Instructions set to be inserted is empty!"

Fix up the placeholder we may add in genAlternativeCodeSequence ( ) .


"Removing insn %d from candidates list\n"

For a given bitmap of insn UIDs scans all instructions and remove insn from CANDIDATES in case it has both convertible and not convertible definitions . All insns in a bitmap are conversion candidates according to scalar_to_vector_candidate_p . Currently it implies all insns are single_set .


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; return ; } BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Subtarget . getReturnOpcode ( ) ) ) . add ( predOps ( ARMCC :: AL ) ) ; } </s>

Insert a custom frame for outlined functions .

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL ARMCC::AL


<s> unsigned PPCDispatchGroupSBHazardRecognizer :: PreEmitNoops ( SUnit * SU ) { if ( isLoadAfterStore ( SU ) && CurSlots < 6 ) { unsigned Directive = DAG -> TM . getSubtarget < PPCSubtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == PPC :: DIR_PWR6 || Directive == PPC :: DIR_PWR7 ) return 1 ; return 5 - CurSlots ; } return ScoreboardHazardRecognizer :: PreEmitNoops ( SU ) ; } </s>

PreEmitNoops - This callback is invoked prior to emitting an instruction .


<s> static struct machine_function * mmix_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>


<s> static rtx_insn * thumb1_emit_multi_reg_push ( unsigned long mask , unsigned long real_regs ) { unsigned long regno ; rtx par [ 10 ] , tmp , reg ; rtx_insn * insn ; int i , j ; for ( i = 0 ; mask ; ++ i , mask &= mask - 1 ) { regno = ctz_hwi ( mask ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( i == 0 ) tmp = gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ; else tmp = gen_rtx_USE ( VOIDmode , reg ) ; par [ i ] = tmp ; } tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; tmp = gen_frame_mem ( BLKmode , tmp ) ; tmp = gen_rtx_SET ( tmp , par [ 0 ] ) ; par [ 0 ] = tmp ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( i , par ) ) ; insn = emit_insn ( tmp ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , tmp ) ; par [ 0 ] = tmp ; for ( j = 0 ; real_regs ; ++ j , real_regs &= real_regs - 1 ) { regno = ctz_hwi ( real_regs ) ; reg = gen_rtx_REG ( SImode , regno ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , j * 4 ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; par [ j + 1 ] = tmp ; } if ( j == 0 ) tmp = par [ 0 ] ; else { RTX_FRAME_RELATED_P ( par [ 0 ] ) = 1 ; tmp = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec_v ( j + 1 , par ) ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , tmp ) ; return insn ; } </s>

Like emit_multi_reg_push , but allowing for a different set of registers to be described as saved . MASK is the set of registers to be saved ; REAL_REGS is the set of registers to be described as saved . If REAL_REGS is 0 , only describe the stack adjustment .


<s>
void
ARMOperand
::
dump
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
CondCode
:
OS
<<
"<ARMCC::"
<<
ARMCondCodeToString
(
getCondCode
(
)
)
<<
">"
;
break
;
case
CCOut
:
OS
<<
"<ccout "
<<
getReg
(
)
<<
">"
;
break
;
case
CoprocNum
:
OS
<<
"<coprocessor number: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
CoprocReg
:
OS
<<
"<coprocessor register: "
<<
getCoproc
(
)
<<
">"
;
break
;
case
MSRMask
:
OS
<<
"<mask: "
<<
getMSRMask
(
)
<<
">"
;
break
;
case
Immediate
:
getImm
(
)
->
print
(
OS
)
;
break
;
case
MemBarrierOpt
:
OS
<<
"<ARM_MB::"
<<
MemBOptToString
(
getMemBarrierOpt
(
)
)
<<
">"
;
break
;
case
Memory
:
OS
<<
"<memory "
<<
"base:"
<<
getMemBaseRegNum
(
)
;
if
(
getMemOffsetIsReg
(
)
)
{
OS
<<
" offset:<register "
<<
getMemOffsetRegNum
(
)
;
if
(
getMemOffsetRegShifted
(
)
)
{
OS
<<
" offset-shift-type:"
<<
getMemShiftType
(
)
;
OS
<<
" offset-shift-amount:"
<<
*
getMemShiftAmount
(
)
;
}
}
else
{
OS
<<
" offset:"
<<
*
getMemOffset
(
)
;
}
if
(
getMemOffsetIsReg
(
)
)
OS
<<
" (offset-is-reg)"
;
if
(
getMemPreindexed
(
)
)
OS
<<
" (pre-indexed)"
;
if
(
getMemPostindexed
(
)
)
OS
<<
" (post-indexed)"
;
if
(
getMemNegative
(
)
)
OS
<<
" (negative)"
;
if
(
getMemWriteback
(
)
)
OS
<<
" (writeback)"
;
OS
<<
">"
;
break
;
case
ProcIFlags
:
{
OS
<<
"<ARM_PROC::"
;
unsigned
IFlags
=
getProcIFlags
(
)
;
for
(
int
i
=
2
;
i
>=
0
;
i
)
if
(
IFlags
&
(
1
<<
i
)
)
OS
<<
ARM_PROC
::
IFlagsToString
(
1
<<
i
)
;
OS
<<
">"
;
break
;
}
case
Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
break
;
case
RegisterList
:
case
DPRRegisterList
:
case
SPRRegisterList
:
{
OS
<<
"<register_list "
;
const
SmallVectorImpl
<
unsigned
>
&
RegList
=
getRegList
(
)
;
for
(
SmallVectorImpl
<
unsigned
>
::
const_iterator
I
=
RegList
.
begin
(
)
,
E
=
RegList
.
end
(
)
;
I
!=
E
;
)
{
OS
<<
*
I
;
if
(
++
I
<
E
)
OS
<<
", "
;
}
OS
<<
">"
;
break
;
}
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .

ARM
ARM
"<ARMCC::"
ARM
">"
"<ccout "
">"
"<coprocessor number: "
">"
"<coprocessor register: "
">"
"<mask: "
">"
"<ARM_MB::"
">"
"<memory "
"base:"
" offset:<register "
" offset-shift-type:"
" offset-shift-amount:"
" offset:"
" (offset-is-reg)"
" (pre-indexed)"
" (post-indexed)"
" (negative)"
" (writeback)"
">"
"<ARM_PROC::"
2
0
1
ARM_PROC::IFlagsToString
1
">"
"<register "
">"
"<register_list "
", "
">"
"'"
"'"


<s> bool isLegalMaskedStore ( Type * DataType , MaybeAlign Alignment ) { return isLegalMaskedLoadStore ( DataType , Alignment ) ; } </s>

Return true if the target supports masked store .


Expand cpymem , as if from a __builtin_memcpy . Return true if we succeed , otherwise return false .


<s> rtx rs6000_libcall_value ( machine_mode mode ) { unsigned int regno ; if ( TARGET_32BIT && TARGET_POWERPC64 && mode == DImode ) return rs6000_parallel_return ( mode , 2 , SImode , GP_ARG_RETURN , 1 ) ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS && ( ( TARGET_SINGLE_FLOAT && mode == SFmode ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI ) regno = ALTIVEC_ARG_RETURN ; else if ( COMPLEX_MODE_P ( mode ) && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && ( mode == DFmode || mode == DCmode || FLOAT128_IBM_P ( mode ) || mode == TCmode ) ) return spe_build_register_parallel ( mode , GP_ARG_RETURN ) ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> static rtx pa_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , PA_STRUCT_VALUE_REGNUM ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> unsigned getNumFixupKinds ( ) const override { return AArch64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! getARMSubtarget ( ) . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( getARMSubtarget ( ) . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( IfConverterID ) ; } if ( getARMSubtarget ( ) . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM ARM ARM ARM ARM ARM::DPRRegClass ARM ARM ARM


<s> void aarch64_swap_ldrstr_operands ( rtx * operands , bool load ) { rtx mem_1 , mem_2 , base_1 , base_2 , offset_1 , offset_2 ; HOST_WIDE_INT offval_1 , offval_2 ; if ( load ) { mem_1 = operands [ 1 ] ; mem_2 = operands [ 3 ] ; } else { mem_1 = operands [ 0 ] ; mem_2 = operands [ 2 ] ; } extract_base_offset_in_addr ( mem_1 , & base_1 , & offset_1 ) ; extract_base_offset_in_addr ( mem_2 , & base_2 , & offset_2 ) ; offval_1 = INTVAL ( offset_1 ) ; offval_2 = INTVAL ( offset_2 ) ; if ( offval_1 > offval_2 ) { std :: swap ( operands [ 0 ] , operands [ 2 ] ) ; std :: swap ( operands [ 1 ] , operands [ 3 ] ) ; } } </s>

Given OPERANDS of consecutive load/store that can be merged , swap them if they are not in ascending order .


<s> bool X86FastTileConfig :: runOnMachineFunction ( MachineFunction & MFunc ) { MF = & MFunc ; MRI = & MFunc . getRegInfo ( ) ; ST = & MFunc . getSubtarget < X86Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = MFunc . getSubtarget ( ) . getInstrInfo ( ) ; X86FI = MFunc . getInfo < X86MachineFunctionInfo > ( ) ; return fastTileConfig ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool AArch64TargetLowering :: needsFixedCatchObjects ( ) const { return false ; } </s>


<s> bool X86TargetLowering :: getSafeStackPointerLocation ( unsigned & AddressSpace , unsigned & Offset ) const { if ( ! Subtarget -> isTargetAndroid ( ) ) return false ; if ( Subtarget -> is64Bit ( ) ) { Offset = 0x48 ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = 256 ; else AddressSpace = 257 ; } else { Offset = 0x24 ; AddressSpace = 256 ; } return true ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( HasSoftFloat ) HasVector = false ; if ( ! HasVector ) { HasVectorEnhancements1 = false ; HasVectorEnhancements2 = false ; HasVectorPackedDecimal = false ; HasVectorPackedDecimalEnhancement = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass || RC == ARM :: tGPRRegisterClass ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool const_load_sequence_p ( swap_web_entry * insn_entry , rtx insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; const_rtx tocrel_base ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || ! ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) || ! MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; if ( ! REG_P ( base_reg ) ) return false ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( MEM_P ( tocrel_expr ) ) tocrel_expr = XEXP ( tocrel_expr , 0 ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false , & tocrel_base , NULL ) ) return false ; split_const ( XVECEXP ( tocrel_base , 0 , 0 ) , & base , & offset ) ; if ( ! SYMBOL_REF_P ( base ) || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; else { rtx const_vector = get_pool_constant ( base ) ; if ( SYMBOL_REF_P ( const_vector ) && CONSTANT_POOL_ADDRESS_P ( const_vector ) ) const_vector = get_pool_constant ( const_vector ) ; if ( GET_CODE ( const_vector ) != CONST_VECTOR ) return false ; } } } return true ; } </s>

Return TRUE if insn is a swap fed by a load from the constant pool .


<s> static bool indirectable_constant_address_p ( rtx x , bool indirect ATTRIBUTE_UNUSED ) { return CONSTANT_ADDRESS_P ( x ) ; } </s>

Re-definition of CONSTANT_ADDRESS_P , which is true only when there are no SYMBOL_REFs for external symbols present .


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeLegal ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; unsigned DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; CLI . Call = MIB ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s> static bool ia64_vectorize_vec_perm_const_ok ( machine_mode vmode , const unsigned char * sel ) { struct expand_vec_perm_d d ; unsigned int i , nelt , which ; bool ret ; d . vmode = vmode ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = true ; memcpy ( d . perm , sel , nelt ) ; for ( i = which = 0 ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < 2 * nelt ) ; which |= ( e < nelt ? 1 : 2 ) ; } if ( which == 2 ) for ( i = 0 ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_operand_p = ( which != 3 ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 1 ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 2 ) ; if ( ! d . one_operand_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + 3 ) ; start_sequence ( ) ; ret = ia64_expand_vec_perm_const_1 ( & d ) ; end_sequence ( ) ; return ret ; } </s>


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) override { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; return MIRBuilder . buildFrameIndex ( LLT :: pointer ( 0 , DL . getPointerSizeInBits ( 0 ) ) , FI ) . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"LEG DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> void SystemZMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ; } </s>


<s> int mips_adjust_insn_length ( rtx_insn * insn , int length ) { if ( length == MAX_PIC_BRANCH_LENGTH && JUMP_P ( insn ) && INSN_CODE ( insn ) >= 0 && get_attr_type ( insn ) == TYPE_BRANCH ) { length = simplejump_p ( insn ) ? 0 : 8 ; length += BASE_INSN_LENGTH * mips_load_label_num_insns ( ) ; length += TARGET_COMPRESSION ? 2 : 4 ; } if ( CALL_P ( insn ) || ( TARGET_MIPS16 ? simplejump_p ( insn ) : JUMP_P ( insn ) ) ) length += TARGET_MIPS16 ? 2 : 4 ; if ( ! cfun -> machine -> ignore_hazard_length_p && INSN_P ( insn ) && INSN_CODE ( insn ) >= 0 ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_DELAY : case HAZARD_FORBIDDEN_SLOT : length += NOP_INSN_LENGTH ; break ; case HAZARD_HILO : length += NOP_INSN_LENGTH * 2 ; break ; } return length ; } </s>

Return the length of INSN . LENGTH is the initial length computed by attributes in the machine-description file .


<s> static unsigned rs6000_hash_constant ( rtx k ) { enum rtx_code code = GET_CODE ( k ) ; machine_mode mode = GET_MODE ( k ) ; unsigned result = ( code << 3 ) ^ mode ; const char * format ; int flen , fidx ; format = GET_RTX_FORMAT ( code ) ; flen = strlen ( format ) ; fidx = 0 ; switch ( code ) { case LABEL_REF : return result * 1231 + ( unsigned ) INSN_UID ( XEXP ( k , 0 ) ) ; case CONST_WIDE_INT : { int i ; flen = CONST_WIDE_INT_NUNITS ( k ) ; for ( i = 0 ; i < flen ; i ++ ) result = result * 613 + CONST_WIDE_INT_ELT ( k , i ) ; return result ; } case CONST_DOUBLE : if ( mode != VOIDmode ) return real_hash ( CONST_DOUBLE_REAL_VALUE ( k ) ) * result ; flen = 2 ; break ; case CODE_LABEL : fidx = 3 ; break ; default : break ; } for ( ; fidx < flen ; fidx ++ ) switch ( format [ fidx ] ) { case 's' : { unsigned i , len ; const char * str = XSTR ( k , fidx ) ; len = strlen ( str ) ; result = result * 613 + len ; for ( i = 0 ; i < len ; i ++ ) result = result * 613 + ( unsigned ) str [ i ] ; break ; } case 'u' : case 'e' : result = result * 1231 + rs6000_hash_constant ( XEXP ( k , fidx ) ) ; break ; case 'i' : case 'n' : result = result * 613 + ( unsigned ) XINT ( k , fidx ) ; break ; case 'w' : if ( sizeof ( unsigned ) >= sizeof ( HOST_WIDE_INT ) ) result = result * 613 + ( unsigned ) XWINT ( k , fidx ) ; else { size_t i ; for ( i = 0 ; i < sizeof ( HOST_WIDE_INT ) / sizeof ( unsigned ) ; i ++ ) result = result * 613 + ( unsigned ) ( XWINT ( k , fidx ) >> CHAR_BIT * i ) ; } break ; case '0' : break ; default : gcc_unreachable ( ) ; } return result ; } </s>


<s> static tree ix86_builtin_decl ( unsigned code , bool ) { if ( code >= IX86_BUILTIN_MAX ) return error_mark_node ; return ix86_builtins [ code ] ; } </s>


<s> bool ix86_memtag_can_tag_addresses ( ) { return ix86_lam_type != lam_none && TARGET_LP64 ; } </s>


"There must be a free register after frame setup"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips6432 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } Result = decodeInstruction ( DecoderTableMips32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> void handle_arm_neon_h ( void ) { aarch64_simd_switcher simd ; for ( unsigned int i = 0 ; i < ARM_NEON_H_TYPES_LAST ; i ++ ) for ( unsigned int count = 2 ; count <= 4 ; ++ count ) if ( ! aarch64_scalar_builtin_type_p ( aarch64_simd_types [ i ] . type ) ) register_tuple_type ( count , i ) ; aarch64_init_simd_builtin_functions ( true ) ; aarch64_init_simd_intrinsics ( ) ; } </s>

Implement # pragma GCC aarch64 `` arm_neon.h '' . The types and functions defined here need to be available internally during LTO as well .


<s> rtx function_value ( tree type , enum machine_mode mode , int incoming_p ) { int regbase = ( incoming_p ? SPARC_OUTGOING_INT_ARG_FIRST : SPARC_INCOMING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , TYPE_MODE ( TREE_TYPE ( type ) ) , SPARC_FP_ARG_FIRST ) ; else mclass = MODE_FLOAT ; } else if ( type && TARGET_ARCH64 ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { gcc_assert ( int_size_in_bytes ( type ) <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT bytes = int_size_in_bytes ( type ) ; gcc_assert ( bytes <= 32 ) ; mode = mode_for_size ( bytes * BITS_PER_UNIT , MODE_INT , 0 ) ; if ( mode == BLKmode ) return function_arg_union_value ( bytes , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle FUNCTION_VALUE , FUNCTION_OUTGOING_VALUE , and LIBCALL_VALUE macros . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> const unsigned * IA64RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { IA64 :: r5 , 0 } ; return CalleeSavedRegs ; } </s>


Returns the description of caches on AIX .


<s> static rtx_insn * emit_frame_save ( rtx frame_reg , machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT frame_reg_to_sp ) { rtx reg ; gcc_checking_assert ( ! ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX , NULL_RTX ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < ProfileSummaryInfoWrapperPass > ( ) ; AU . addRequired < LazyMachineBlockFrequencyInfoPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int ix86_nsaved_regs ( void ) { int nregs = 0 ; int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) nregs ++ ; return nregs ; } </s>

Return number of registers to be saved on the stack .


<s>
static
void
ix86_avoid_jump_misspredicts
(
void
)
{
rtx
insn
,
start
=
get_insns
(
)
;
int
nbytes
=
0
,
njumps
=
0
;
int
isjump
=
0
;
for
(
insn
=
get_insns
(
)
;
insn
;
insn
=
NEXT_INSN
(
insn
)
)
{
nbytes
+=
min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Insn %i estimated to %i bytes\n"
,
INSN_UID
(
insn
)
,
min_insn_size
(
insn
)
)
;
if
(
(
GET_CODE
(
insn
)
==
JUMP_INSN
&&
GET_CODE
(
PATTERN
(
insn
)
)
!=
ADDR_VEC
&&
GET_CODE
(
PATTERN
(
insn
)
)
!=
ADDR_DIFF_VEC
)
||
GET_CODE
(
insn
)
==
CALL_INSN
)
njumps
++
;
else
continue
;
while
(
njumps
>
3
)
{
start
=
NEXT_INSN
(
start
)
;
if
(
(
GET_CODE
(
start
)
==
JUMP_INSN
&&
GET_CODE
(
PATTERN
(
start
)
)
!=
ADDR_VEC
&&
GET_CODE
(
PATTERN
(
start
)
)
!=
ADDR_DIFF_VEC
)
||
GET_CODE
(
start
)
==
CALL_INSN
)
njumps
,
isjump
=
1
;
else
isjump
=
0
;
nbytes
-=
min_insn_size
(
start
)
;
}
gcc_assert
(
njumps
>=
0
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Interval %i to %i has %i bytes\n"
,
INSN_UID
(
start
)
,
INSN_UID
(
insn
)
,
nbytes
)
;
if
(
njumps
==
3
&&
isjump
&&
nbytes
<
16
)
{
int
padsize
=
15
nbytes
+
min_insn_size
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Padding insn %i by %i bytes!\n"
,
INSN_UID
(
insn
)
,
padsize
)
;
emit_insn_before
(
gen_align
(
GEN_INT
(
padsize
)
)
,
insn
)
;
}
}
}
</s>

AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte window .


<s> unsigned MipsRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? Mips :: FP : Mips :: SP ; } </s>


<s>
unsigned
VEMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
MO
.
getImm
(
)
;
assert
(
MO
.
isExpr
(
)
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
if
(
const
VEMCExpr
*
SExpr
=
dyn_cast
<
VEMCExpr
>
(
Expr
)
)
{
MCFixupKind
Kind
=
(
MCFixupKind
)
SExpr
->
getFixupKind
(
)
;
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
Expr
,
Kind
)
)
;
return
0
;
}
int64_t
Res
;
if
(
Expr
->
evaluateAsAbsolute
(
Res
)
)
return
Res
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) rs6000_density_test ( cost_data ) ; if ( cost_data -> loop_info ) { loop_vec_info vec_info = loop_vec_info_for_loop ( cost_data -> loop_info ) ; if ( ! rs6000_vect_nonmem && LOOP_VINFO_VECT_FACTOR ( vec_info ) == 2 && LOOP_REQUIRES_VERSIONING ( vec_info ) ) cost_data -> cost [ vect_body ] += 10000 ; } * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasISEL ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = "+64bit," + FullFS ; else FullFS = "+64bit" ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool AArch64InstrInfo :: useMachineCombiner ( ) const { return true ; } </s>

Return true when a target supports MachineCombiner .


<s> static rtx r10k_simplify_address ( rtx x , rtx_insn * insn ) { rtx newx , op0 , op1 , set , note ; rtx_insn * def_insn ; df_ref use , def ; struct df_link * defs ; newx = NULL_RTX ; if ( UNARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , 0 ) , insn ) ; if ( op0 != XEXP ( x , 0 ) ) newx = simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , GET_MODE ( XEXP ( x , 0 ) ) ) ; } else if ( BINARY_P ( x ) ) { op0 = r10k_simplify_address ( XEXP ( x , 0 ) , insn ) ; op1 = r10k_simplify_address ( XEXP ( x , 1 ) , insn ) ; if ( op0 != XEXP ( x , 0 ) || op1 != XEXP ( x , 1 ) ) newx = simplify_gen_binary ( GET_CODE ( x ) , GET_MODE ( x ) , op0 , op1 ) ; } else if ( GET_CODE ( x ) == LO_SUM ) { op0 = r10k_simplify_address ( XEXP ( x , 0 ) , insn ) ; if ( GET_CODE ( op0 ) == HIGH ) newx = XEXP ( x , 1 ) ; } else if ( REG_P ( x ) ) { use = df_find_use ( insn , regno_reg_rtx [ REGNO ( x ) ] ) ; gcc_assert ( use ) ; defs = DF_REF_CHAIN ( use ) ; if ( defs && defs -> next == NULL ) { def = defs -> ref ; if ( DF_REF_IS_ARTIFICIAL ( def ) ) { if ( x == stack_pointer_rtx && DF_REF_BB ( def ) == ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) newx = virtual_incoming_args_rtx ; } else if ( dominated_by_p ( CDI_DOMINATORS , DF_REF_BB ( use ) , DF_REF_BB ( def ) ) ) { def_insn = DF_REF_INSN ( def ) ; if ( NONJUMP_INSN_P ( def_insn ) ) { set = single_set ( def_insn ) ; if ( set && rtx_equal_p ( SET_DEST ( set ) , x ) ) { note = find_reg_equal_equiv_note ( def_insn ) ; if ( note ) newx = XEXP ( note , 0 ) ; else newx = SET_SRC ( set ) ; newx = r10k_simplify_address ( newx , def_insn ) ; } } } } } if ( newx && r10k_simplified_address_p ( newx ) ) return newx ; return x ; } </s>

X is an expression that appears in INSN . Try to use the UD chains to simplify it , returning the simplified form on success and the original form otherwise . Replace the incoming value of $ sp with virtual_incoming_args_rtx ( which should never occur in X otherwise ) .


<s> const uint32_t * SystemZRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const SystemZSubtarget & Subtarget = MF . getSubtarget < SystemZSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) return Subtarget . hasVector ( ) ? CSR_SystemZ_AllRegs_Vector_RegMask : CSR_SystemZ_AllRegs_RegMask ; if ( MF . getSubtarget ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_SystemZ_SwiftError_RegMask ; return CSR_SystemZ_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> BaseKind getKind ( ) const { return Kind ; } </s>


<s> static bool aarch64_evpc_rev_local ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT diff ; unsigned int i , size , unspec ; machine_mode pred_mode ; if ( d -> vec_flags == VEC_SVE_PRED || ! d -> one_vector_p || ! d -> perm [ 0 ] . is_constant ( & diff ) ) return false ; size = ( diff + 1 ) * GET_MODE_UNIT_SIZE ( d -> vmode ) ; if ( size == 8 ) { unspec = UNSPEC_REV64 ; pred_mode = VNx2BImode ; } else if ( size == 4 ) { unspec = UNSPEC_REV32 ; pred_mode = VNx4BImode ; } else if ( size == 2 ) { unspec = UNSPEC_REV16 ; pred_mode = VNx8BImode ; } else return false ; unsigned int step = diff + 1 ; for ( i = 0 ; i < step ; ++ i ) if ( ! d -> perm . series_p ( i , step , diff - i , step ) ) return false ; if ( d -> testing_p ) return true ; if ( d -> vec_flags == VEC_SVE_DATA ) { machine_mode int_mode = aarch64_sve_int_mode ( pred_mode ) ; rtx target = gen_reg_rtx ( int_mode ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_aarch64_sve_reinterpret ( int_mode , target , d -> op0 ) ) ; else { int unspec = aarch64_sve_rev_unspec ( d -> vmode ) ; rtx pred = aarch64_ptrue_reg ( pred_mode ) ; emit_insn ( gen_aarch64_pred ( unspec , int_mode , target , pred , gen_lowpart ( int_mode , d -> op0 ) ) ) ; } emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , target ) ) ; return true ; } rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( 1 , d -> op0 ) , unspec ) ; emit_set_insn ( d -> target , src ) ; return true ; } </s>

Recognize patterns for the REV { 64,32,16 } insns , which reverse elements within each 64-bit , 32-bit or 16-bit granule .


<s> bool AArch64PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install an IR translator pass , which converts from LLVM code to machine instructions with possibly generic opcodes .


<s> static bool mips_mode_ok_for_mov_fmt_p ( machine_mode mode ) { switch ( mode ) { case E_CCFmode : case E_SFmode : return TARGET_HARD_FLOAT ; case E_DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; case E_V2SFmode : return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT ; default : return MSA_SUPPORTED_MODE_P ( mode ) ; } } </s>

Return true if moves in mode MODE can use the FPU 's mov.fmt instruction .


<s> bool X86PassConfig :: addPreEmitPass ( ) { bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && getX86Subtarget ( ) . hasSSE2 ( ) ) { PM -> add ( createExecutionDependencyFixPass ( & X86 :: VR128RegClass ) ) ; ShouldPrint = true ; } if ( getX86Subtarget ( ) . hasAVX ( ) && UseVZeroUpper ) { PM -> add ( createX86IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } return ShouldPrint ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( SoftFloat ) FS += FS . empty ( ) ? "-hard-float" : ",-hard-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "-hard-float" ",-hard-float" PPC


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == 0 ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static unsigned getBit ( InsnType insn , int pos ) { return getBits ( insn , pos , 1 ) ; } </s>

Get the Init value of the specified bit .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( ! MFI -> hasVarSizedObjects ( ) ) return true ; if ( ! EnableBasePointer ) return false ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> bool gen_ldm_seq ( rtx * operands , int nops , bool sort_regs ) { int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == 0 ) return false ; if ( sort_regs ) for ( i = 0 ; i < nops - 1 ; i ++ ) for ( j = i + 1 ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( peep2_reg_dead_p ( nops , base_reg_rtx ) ) ; gcc_assert ( ldm_case == 1 || ldm_case == 5 ) ; write_back = TRUE ; } if ( ldm_case == 5 ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ 0 ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; if ( ! TARGET_THUMB1 ) base_reg_rtx = newbase ; } for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of loads into an LDM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate loads we are trying to combine . SORT_REGS is true if we can reorder the registers because they are used commutatively subsequently . Returns true iff we could generate a new instruction .


<s> rtx ix86_memtag_extract_tag ( rtx tagged_pointer , rtx target ) { rtx tag = expand_simple_binop ( Pmode , LSHIFTRT , tagged_pointer , GEN_INT ( IX86_HWASAN_SHIFT ) , target , 0 , OPTAB_DIRECT ) ; rtx ret = gen_reg_rtx ( QImode ) ; if ( ix86_lam_type == lam_u57 ) { unsigned HOST_WIDE_INT and_imm = ( HOST_WIDE_INT_1U << IX86_HWASAN_TAG_SIZE ) - 1 ; emit_insn ( gen_andqi3 ( ret , gen_lowpart ( QImode , tag ) , gen_int_mode ( and_imm , QImode ) ) ) ; } else emit_move_insn ( ret , gen_lowpart ( QImode , tag ) ) ; return ret ; } </s>


<s> static void do_load_mask_compare ( const machine_mode load_mode , rtx diff , rtx cmp_rem , rtx dcond , rtx src1_addr , rtx src2_addr , rtx orig_src1 , rtx orig_src2 ) { HOST_WIDE_INT load_mode_size = GET_MODE_SIZE ( load_mode ) ; rtx shift_amount = gen_reg_rtx ( word_mode ) ; rtx d1 = gen_reg_rtx ( word_mode ) ; rtx d2 = gen_reg_rtx ( word_mode ) ; do_load_for_compare_from_addr ( load_mode , d1 , src1_addr , orig_src1 ) ; do_load_for_compare_from_addr ( load_mode , d2 , src2_addr , orig_src2 ) ; do_sub3 ( shift_amount , GEN_INT ( load_mode_size ) , cmp_rem ) ; if ( word_mode == DImode ) { emit_insn ( gen_ashldi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrdi3 ( d1 , d1 , gen_lowpart ( SImode , shift_amount ) ) ) ; emit_insn ( gen_lshrdi3 ( d2 , d2 , gen_lowpart ( SImode , shift_amount ) ) ) ; } else { emit_insn ( gen_ashlsi3 ( shift_amount , shift_amount , GEN_INT ( LOG2_BITS_PER_UNIT ) ) ) ; emit_insn ( gen_lshrsi3 ( d1 , d1 , shift_amount ) ) ; emit_insn ( gen_lshrsi3 ( d2 , d2 , shift_amount ) ) ; } if ( TARGET_P9_MISC ) { rtx cmp = gen_rtx_COMPARE ( CCUNSmode , d1 , d2 ) ; emit_insn ( gen_rtx_SET ( dcond , cmp ) ) ; } else { if ( word_mode == DImode ) emit_insn ( gen_subfdi3_carry ( diff , d2 , d1 ) ) ; else emit_insn ( gen_subfsi3_carry ( diff , d2 , d1 ) ) ; } } </s>

Generate rtl for a load , shift , and compare of less than a full word . LOAD_MODE is the machine mode for the loads . DIFF is the reg for the difference . CMP_REM is the reg containing the remaining bytes to compare . DCOND is the CCUNS reg for the compare if we are doing P9 code with setb . SRC1_ADDR is the first source address . SRC2_ADDR is the second source address . ORIG_SRC1 is the original first source block 's address rtx . ORIG_SRC2 is the original second source block 's address rtx .


<s> bool AArch64PassConfig :: addInstSelector ( ) { addPass ( createAArch64ISelDag ( getAArch64TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getTargetTriple ( ) . isOSBinFormatELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64CleanupLocalDynamicTLSPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"no low registers available for popping high registers"

The bits which are n't usefully expanded as rtl .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2LDRDi8 ) ) ; AddDReg ( MIB , DestReg , ARM :: gsub_0 , RegState :: DefineNoRead , TRI ) ; AddDReg ( MIB , DestReg , ARM :: gsub_1 , RegState :: DefineNoRead , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC , TRI ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
unsigned
AArch64MCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
{
assert
(
MO
.
isImm
(
)
&&
"did not expect relocated expression"
)
;
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
0
&&
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> const CallLowering * MipsSubtarget :: getCallLowering ( ) const { return CallLoweringInfo . get ( ) ; } </s>


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; const SystemZSubtarget * Subtarget = & MF . getSubtarget < SystemZSubtarget > ( ) ; SystemZCallingConventionRegisters * Regs = Subtarget -> getSpecialRegisters ( ) ; if ( TFI -> hasFP ( MF ) ) for ( MCRegAliasIterator AI ( Regs -> getFramePointerRegister ( ) , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( Regs -> getStackPointerRegister ( ) , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; Reserved . set ( SystemZ :: A0 ) ; Reserved . set ( SystemZ :: A1 ) ; Reserved . set ( SystemZ :: FPC ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ::A0 SystemZ::A1 SystemZ::FPC


<s> const char * LanaiTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case LanaiISD :: ADJDYNALLOC : return "LanaiISD::ADJDYNALLOC" ; case LanaiISD :: RET_FLAG : return "LanaiISD::RET_FLAG" ; case LanaiISD :: CALL : return "LanaiISD::CALL" ; case LanaiISD :: SELECT_CC : return "LanaiISD::SELECT_CC" ; case LanaiISD :: SETCC : return "LanaiISD::SETCC" ; case LanaiISD :: SUBBF : return "LanaiISD::SUBBF" ; case LanaiISD :: SET_FLAG : return "LanaiISD::SET_FLAG" ; case LanaiISD :: BR_CC : return "LanaiISD::BR_CC" ; case LanaiISD :: Wrapper : return "LanaiISD::Wrapper" ; case LanaiISD :: HI : return "LanaiISD::HI" ; case LanaiISD :: LO : return "LanaiISD::LO" ; case LanaiISD :: SMALL : return "LanaiISD::SMALL" ; default : return nullptr ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Lanai Lanai LanaiISD::ADJDYNALLOC "LanaiISD::ADJDYNALLOC" LanaiISD::RET_FLAG "LanaiISD::RET_FLAG" LanaiISD::CALL "LanaiISD::CALL" LanaiISD::SELECT_CC "LanaiISD::SELECT_CC" LanaiISD::SETCC "LanaiISD::SETCC" LanaiISD::SUBBF "LanaiISD::SUBBF" LanaiISD::SET_FLAG "LanaiISD::SET_FLAG" LanaiISD::BR_CC "LanaiISD::BR_CC" LanaiISD::Wrapper "LanaiISD::Wrapper" LanaiISD::HI "LanaiISD::HI" LanaiISD::LO "LanaiISD::LO" LanaiISD::SMALL "LanaiISD::SMALL"


<s>
const
RegisterBank
&
X86RegisterBankInfo
::
getRegBankFromRegClass
(
const
TargetRegisterClass
&
RC
)
const
{
if
(
X86
::
GR8RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR16RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR32RegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
GR64RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
GPRRegBankID
)
;
if
(
X86
::
FR32XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
FR64XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR128XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR256XRegClass
.
hasSubClassEq
(
&
RC
)
||
X86
::
VR512RegClass
.
hasSubClassEq
(
&
RC
)
)
return
getRegBank
(
X86
::
VECRRegBankID
)
;
llvm_unreachable
(
"Unsupported register kind yet."
)
;
}
</s>


<s> unsigned int execute ( function * ) { return nds32_relax_opt ( ) ; } </s>


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroName = ( V && V -> isNullValue ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s> int arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == HImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return FALSE ; if ( TARGET_THUMB2 ) return TRUE ; return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return FALSE ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
symbol_name
,
*
lazy_ptr_name
;
char
*
local_label_0
;
static
int
label
=
0
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
alloca
(
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
lazy_ptr_name
=
alloca
(
length
+
32
)
;
GEN_LAZY_PTR_NAME_FOR_SYMBOL
(
lazy_ptr_name
,
symb
,
length
)
;
if
(
flag_pic
==
2
)
machopic_picsymbol_stub1_section
(
)
;
else
machopic_symbol_stub1_section
(
)
;
if
(
flag_pic
==
2
)
{
fprintf
(
file
,
"\t.align 5\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
label
++
;
local_label_0
=
alloca
(
sizeof
(
"\"L00000000000$spb\""
)
)
;
sprintf
(
local_label_0
,
"\"L%011d$spb\""
,
label
)
;
fprintf
(
file
,
"\tmflr r0\n"
)
;
fprintf
(
file
,
"\tbcl 20,31,%s\n"
,
local_label_0
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
fprintf
(
file
,
"\taddis r11,r11,ha16(%s-%s)\n"
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtlr r0\n"
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s-%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
else
{
fprintf
(
file
,
"\t.align 4\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\tlis r11,ha16(%s)\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
machopic_lazy_symbol_ptr_section
(
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"%sdyld_stub_binding_helper\n"
,
(
TARGET_64BIT
DOUBLE_INT_ASM_OP
:
"\t.long\t"
)
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { enum machine_mode mode = GET_MODE ( op ) ; enum machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits = GET_MODE_NUNITS ( mode ) ; unsigned bitsize = GET_MODE_BITSIZE ( inner ) ; unsigned mask = GET_MODE_MASK ( inner ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - 1 ) ; HOST_WIDE_INT val = INTVAL ( last ) ; HOST_WIDE_INT splat_val = val ; HOST_WIDE_INT msb_val = val > 0 ? 0 : - 1 ; for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else return false ; for ( i = 0 ; i < nunits - 1 ; ++ i ) { HOST_WIDE_INT desired_val ; if ( ( ( i + 1 ) & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != INTVAL ( CONST_VECTOR_ELT ( op , i ) ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


<s>
void
ARMConstantIslands
::
verify
(
)
{
BBInfoVector
&
BBInfo
=
BBUtils
->
getBBInfo
(
)
;
assert
(
is_sorted
(
*
MF
,
[
&
BBInfo
]
(
const
MachineBasicBlock
&
LHS
,
const
MachineBasicBlock
&
RHS
)
{
return
BBInfo
[
LHS
.
getNumber
(
)
]
.
postOffset
(
)
<
BBInfo
[
RHS
.
getNumber
(
)
]
.
postOffset
(
)
;
}
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Verifying "
<<
CPUsers
.
size
(
)
<<
" CP users.\n"
)
;
for
(
CPUser
&
U
:
CPUsers
)
{
unsigned
UserOffset
=
getUserOffset
(
U
)
;
if
(
isCPEntryInRange
(
U
.
MI
,
UserOffset
,
U
.
CPEMI
,
U
.
getMaxDisp
(
)
+
2
,
U
.
NegOk
,
true
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"OK\n"
)
;
continue
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Out of range.\n"
)
;
dumpBBs
(
)
;
LLVM_DEBUG
(
MF
->
dump
(
)
)
;
llvm_unreachable
(
"Constant pool entry out of range!"
)
;
}
}
</s>

ARM
ARM
"Verifying "
" CP users.\n"
2
"OK\n"
"Out of range.\n"
"Constant pool entry out of range!"


<s>
const
LegalizerInfo
*
ARMSubtarget
::
getLegalizerInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getLegalizerInfo
(
)
;
}
</s>

Expose LegalizerInfo so the clients can re-use .

ARM
ARM
"Access to GlobalISel APIs not set"


<s> const Cpu0InstrInfo * getInstrInfo ( ) const override { return InstrInfo . get ( ) ; } </s>


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & AArch64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: NumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ArgGPRs [ I ] ) ; if ( ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame -> hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! EnableCheri128FailHard ) return false ; InstrInfo = MF . getSubtarget < MipsSubtarget > ( ) . getInstrInfo ( ) ; SmallVector < MachineInstr * , 16 > instrs ; std :: set < MachineBasicBlock * > bbs ; for ( auto & MBB : MF ) for ( auto & MI : MBB ) if ( ( MI . getOpcode ( ) == Mips :: CIncOffset ) || ( MI . getOpcode ( ) == Mips :: CSetOffset ) ) { instrs . push_back ( & MI ) ; bbs . insert ( & MBB ) ; } if ( instrs . empty ( ) ) return false ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; for ( auto * MI : instrs ) { Register tag_before = RI . createVirtualRegister ( & Mips :: GPR64RegClass ) ; Register tag_after = RI . createVirtualRegister ( & Mips :: GPR64RegClass ) ; auto & MBB = * MI -> getParent ( ) ; BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: CGetTag ) ) . addDef ( tag_before ) . addUse ( MI -> getOperand ( 1 ) . getReg ( ) ) ; MachineBasicBlock :: iterator after = BuildMI ( * MI -> getParent ( ) , ++ MachineBasicBlock :: iterator ( MI ) , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: CGetTag ) ) . addDef ( tag_after ) . addUse ( MI -> getOperand ( 0 ) . getReg ( ) ) . getInstr ( ) ; auto Sink = MF . CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF . insert ( ++ MachineFunction :: iterator ( MBB ) , Sink ) ; Sink -> splice ( Sink -> begin ( ) , & MBB , std :: next ( after ) , MBB . end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( Sink ) ; assert ( Sink -> getParent ( ) == & MF ) ; after = BuildMI ( MBB , ++ after , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: BEQ64 ) ) . addUse ( tag_after , RegState :: Kill ) . addUse ( tag_before , RegState :: Kill ) . addMBB ( Sink ) ; BuildMI ( MBB , ++ after , MI -> getDebugLoc ( ) , InstrInfo -> get ( Mips :: TRAP ) ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void SystemZConstantPoolValue :: print ( raw_ostream & O ) const { O << GV << "@" << int ( Modifier ) ; } </s>

print - Print a debug representation of the operand to the given stream .


<s>
static
void
seh_emit_save
(
FILE
*
f
,
struct
seh_frame_state
*
seh
,
rtx
reg
,
HOST_WIDE_INT
cfa_offset
)
{
unsigned
int
regno
=
REGNO
(
reg
)
;
HOST_WIDE_INT
offset
;
gcc_assert
(
seh
->
sp_offset
>=
cfa_offset
)
;
offset
=
seh
->
sp_offset
cfa_offset
;
fputs
(
(
SSE_REGNO_P
(
regno
)
"\t.seh_savexmm\t"
:
GENERAL_REGNO_P
(
regno
)
"\t.seh_savereg\t"
:
(
gcc_unreachable
(
)
,
""
)
)
,
f
)
;
print_reg
(
reg
,
0
,
f
)
;
fprintf
(
f
,
", "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
offset
)
;
}
</s>

Emit an assembler directive to save REG at CFA - CFA_OFFSET .


<s> bool allowPositionIndependentMovt ( ) const { return isROPI ( ) || ! isTargetELF ( ) ; } </s>

Allow movt+movw for PIC global address calculation .


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SDC1 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
const
char
*
getPassName
(
)
const
{
return
"Merge internal globals"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool ix86_ifunc_ref_local_ok ( void ) { return ! flag_pic || ( TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC ) ; } </s>

Implement TARGET_IFUNC_REF_LOCAL_OK . If this hook returns true , the PLT entry will be used as the function address for local IFUNC functions . When the PIC register is needed for PLT call , indirect call via the PLT entry will fail since the PIC register may not be set up properly for indirect call . In this case , we should return false .


<s> int sparc_check_64 ( rtx x , rtx_insn * insn ) { int set_once = 0 ; rtx y = x ; gcc_assert ( GET_CODE ( x ) == REG ) ; if ( GET_MODE ( x ) == DImode ) y = gen_rtx_REG ( SImode , REGNO ( x ) + WORDS_BIG_ENDIAN ) ; if ( flag_expensive_optimizations && df && DF_REG_DEF_COUNT ( REGNO ( y ) ) == 1 ) set_once = 1 ; if ( insn == 0 ) { if ( set_once ) insn = get_last_insn_anywhere ( ) ; else return 0 ; } while ( ( insn = PREV_INSN ( insn ) ) ) { switch ( GET_CODE ( insn ) ) { case JUMP_INSN : case NOTE : break ; case CODE_LABEL : case CALL_INSN : default : if ( ! set_once ) return 0 ; break ; case INSN : { rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) != SET ) return 0 ; if ( rtx_equal_p ( x , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( y && rtx_equal_p ( y , SET_DEST ( pat ) ) ) return set_extends ( insn ) ; if ( reg_overlap_mentioned_p ( SET_DEST ( pat ) , y ) ) return 0 ; } } } return 0 ; } </s>

Return 0 if the high 32 bits of X ( the low word of X , if DImode ) are unknown . Return 1 if the high bits are zero , -1 if the register is sign extended .


<s> void llvm :: emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc dl , const TargetInstrInfo & TII , unsigned ScratchReg , int64_t NumBytes , MachineInstr :: MIFlag MIFlags ) { emitRegUpdate ( MBB , MI , dl , TII , AArch64 :: XSP , AArch64 :: XSP , AArch64 :: X16 , NumBytes , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s> void SystemZTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { unsigned BitWidth = Known . getBitWidth ( ) ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { case SystemZISD :: SELECT_CCMASK : { KnownBits TrueKnown ( BitWidth ) , FalseKnown ( BitWidth ) ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , TrueKnown , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 1 ) , FalseKnown , Depth + 1 ) ; Known . Zero = TrueKnown . Zero & FalseKnown . Zero ; Known . One = TrueKnown . One & FalseKnown . One ; break ; } default : break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool isTarget64BitILP32 ( ) const { return Is64Bit && ( TargetTriple . isX32 ( ) || TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case X86 :: MOV8mr : case X86 :: MOV16mr : case X86 :: MOV16_mr : case X86 :: MOV32mr : case X86 :: MOV32_mr : case X86 :: MOV64mr : case X86 :: ST_FpP64m : case X86 :: MOVSSmr : case X86 :: MOVSDmr : case X86 :: MOVAPSmr : case X86 :: MOVAPDmr : case X86 :: MOVDQAmr : case X86 :: MMX_MOVD64mr : case X86 :: MMX_MOVQ64mr : case X86 :: MMX_MOVNTQmr : if ( MI -> getOperand ( 0 ) . isFI ( ) && MI -> getOperand ( 1 ) . isImm ( ) && MI -> getOperand ( 2 ) . isReg ( ) && MI -> getOperand ( 3 ) . isImm ( ) && MI -> getOperand ( 1 ) . getImm ( ) == 1 && MI -> getOperand ( 2 ) . getReg ( ) == 0 && MI -> getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 4 ) . getReg ( ) ; } break ; } return 0 ; } </s>


<s> bool isPPC64 ( ) const { return IsPPC64 ; } </s>

Tests whether the target is 64-bit PowerPC ( little and big endian ) .


<s> static rtx ix86_delegitimize_address ( rtx orig_x ) { rtx x = orig_x , y ; if ( GET_CODE ( x ) == MEM ) x = XEXP ( x , 0 ) ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST || GET_CODE ( XEXP ( x , 0 ) ) != UNSPEC || XINT ( XEXP ( x , 0 ) , 1 ) != UNSPEC_GOTPCREL || GET_CODE ( orig_x ) != MEM ) return orig_x ; return XVECEXP ( XEXP ( x , 0 ) , 0 , 0 ) ; } if ( GET_CODE ( x ) != PLUS || GET_CODE ( XEXP ( x , 1 ) ) != CONST ) return orig_x ; if ( GET_CODE ( XEXP ( x , 0 ) ) == REG && REGNO ( XEXP ( x , 0 ) ) == PIC_OFFSET_TABLE_REGNUM ) y = NULL ; else if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS ) { y = XEXP ( x , 0 ) ; if ( GET_CODE ( XEXP ( y , 0 ) ) == REG && REGNO ( XEXP ( y , 0 ) ) == PIC_OFFSET_TABLE_REGNUM ) y = XEXP ( y , 1 ) ; else if ( GET_CODE ( XEXP ( y , 1 ) ) == REG && REGNO ( XEXP ( y , 1 ) ) == PIC_OFFSET_TABLE_REGNUM ) y = XEXP ( y , 0 ) ; else return orig_x ; if ( GET_CODE ( y ) != REG && GET_CODE ( y ) != MULT && GET_CODE ( y ) != ASHIFT ) return orig_x ; } else return orig_x ; x = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( x ) == UNSPEC && ( ( XINT ( x , 1 ) == UNSPEC_GOT && GET_CODE ( orig_x ) == MEM ) || ( XINT ( x , 1 ) == UNSPEC_GOTOFF && GET_CODE ( orig_x ) != MEM ) ) ) { if ( y ) return gen_rtx_PLUS ( Pmode , y , XVECEXP ( x , 0 , 0 ) ) ; return XVECEXP ( x , 0 , 0 ) ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( ( XINT ( XEXP ( x , 0 ) , 1 ) == UNSPEC_GOT && GET_CODE ( orig_x ) == MEM ) || ( XINT ( XEXP ( x , 0 ) , 1 ) == UNSPEC_GOTOFF && GET_CODE ( orig_x ) != MEM ) ) ) { x = gen_rtx_PLUS ( VOIDmode , XVECEXP ( XEXP ( x , 0 ) , 0 , 0 ) , XEXP ( x , 1 ) ) ; if ( y ) return gen_rtx_PLUS ( Pmode , y , x ) ; return x ; } return orig_x ; } </s>

In the name of slightly smaller debug output , and to cater to general assembler lossage , recognize PIC+GOTOFF and turn it back into a direct symbol reference . On Darwin , this is necessary to avoid a crash , because Darwin has a different PIC label for each routine but the DWARF debugging information is not associated with any particular routine , so it 's necessary to remove references to the PIC label from RTL stored by the DWARF output code .


<s>
static
void
ia64_output_function_prologue
(
FILE
*
file
)
{
int
mask
,
grsave
,
grsave_prev
;
if
(
current_frame_info
.
need_regstk
)
fprintf
(
file
,
"\t.regstk %d, %d, %d, %d\n"
,
current_frame_info
.
n_input_regs
,
current_frame_info
.
n_local_regs
,
current_frame_info
.
n_output_regs
,
current_frame_info
.
n_rotate_regs
)
;
if
(
ia64_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
mask
=
0
;
grsave
=
grsave_prev
=
0
;
if
(
current_frame_info
.
r
[
reg_save_b0
]
!=
0
)
{
mask
|=
8
;
grsave
=
grsave_prev
=
current_frame_info
.
r
[
reg_save_b0
]
;
}
if
(
current_frame_info
.
r
[
reg_save_ar_pfs
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_ar_pfs
]
==
grsave_prev
+
1
)
)
{
mask
|=
4
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
grsave_prev
=
current_frame_info
.
r
[
reg_save_ar_pfs
]
;
}
if
(
current_frame_info
.
r
[
reg_fp
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_fp
]
==
grsave_prev
+
1
)
)
{
mask
|=
2
;
if
(
grsave_prev
==
0
)
grsave
=
HARD_FRAME_POINTER_REGNUM
;
grsave_prev
=
current_frame_info
.
r
[
reg_fp
]
;
}
if
(
current_frame_info
.
r
[
reg_save_pr
]
!=
0
&&
(
grsave_prev
==
0
||
current_frame_info
.
r
[
reg_save_pr
]
==
grsave_prev
+
1
)
)
{
mask
|=
1
;
if
(
grsave_prev
==
0
)
grsave
=
current_frame_info
.
r
[
reg_save_pr
]
;
}
if
(
mask
&&
TARGET_GNU_AS
)
fprintf
(
file
,
"\t.prologue %d, %d\n"
,
mask
,
ia64_dbx_register_number
(
grsave
)
)
;
else
fputs
(
"\t.prologue\n"
,
file
)
;
if
(
current_frame_info
.
spill_cfa_off
!=
16
)
fprintf
(
file
,
"\t.spill %ld\n"
,
(
long
)
(
current_frame_info
.
spill_cfa_off
+
current_frame_info
.
spill_size
)
)
;
}
</s>


"ShadowCallStack attribute not supported on Darwin."

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static rtx altivec_expand_vec_init_builtin ( tree type , tree exp , rtx target ) { machine_mode tmode = TYPE_MODE ( type ) ; machine_mode inner_mode = GET_MODE_INNER ( tmode ) ; int i , n_elt = GET_MODE_NUNITS ( tmode ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; gcc_assert ( n_elt == call_expr_nargs ( exp ) ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( n_elt == 1 && GET_MODE_SIZE ( tmode ) == GET_MODE_SIZE ( inner_mode ) ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , 0 ) ) ; emit_move_insn ( target , gen_lowpart ( tmode , x ) ) ; } else { rtvec v = rtvec_alloc ( n_elt ) ; for ( i = 0 ; i < n_elt ; ++ i ) { rtx x = expand_normal ( CALL_EXPR_ARG ( exp , i ) ) ; RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } rs6000_expand_vector_init ( target , gen_rtx_PARALLEL ( tmode , v ) ) ; } return target ; } </s>


<s>
static
X86Operand
*
CreateMem
(
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
bool
NeedSizeDir
=
false
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
X86Operand
*
Res
=
new
X86Operand
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
NeedSizeDir
=
NeedSizeDir
;
return
Res
;
}
</s>


<s> static bool ix86_legitimate_combined_insn ( rtx_insn * insn ) { if ( ( INSN_CODE ( insn ) = recog ( PATTERN ( insn ) , insn , 0 ) ) >= 0 ) { int i ; extract_insn ( insn ) ; preprocess_constraints ( insn ) ; int n_operands = recog_data . n_operands ; int n_alternatives = recog_data . n_alternatives ; for ( i = 0 ; i < n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; machine_mode mode = GET_MODE ( op ) ; const operand_alternative * op_alt ; int offset = 0 ; bool win ; int j ; if ( ! TARGET_AVX && VECTOR_MODE_P ( mode ) && misaligned_operand ( op , mode ) ) { unsigned int min_align = get_attr_ssememalign ( insn ) ; if ( min_align == 0 || MEM_ALIGN ( op ) < min_align ) return false ; } if ( UNARY_P ( op ) ) op = XEXP ( op , 0 ) ; if ( SUBREG_P ( op ) ) { if ( REG_P ( SUBREG_REG ( op ) ) && REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) offset = subreg_regno_offset ( REGNO ( SUBREG_REG ( op ) ) , GET_MODE ( SUBREG_REG ( op ) ) , SUBREG_BYTE ( op ) , GET_MODE ( op ) ) ; op = SUBREG_REG ( op ) ; } if ( ! ( REG_P ( op ) && HARD_REGISTER_P ( op ) ) ) continue ; op_alt = recog_op_alt ; win = ! n_alternatives ; alternative_mask preferred = get_preferred_alternatives ( insn ) ; for ( j = 0 ; j < n_alternatives ; j ++ , op_alt += n_operands ) { if ( ! TEST_BIT ( preferred , j ) ) continue ; if ( op_alt [ i ] . anything_ok || ( op_alt [ i ] . matches != - 1 && operands_match_p ( recog_data . operand [ i ] , recog_data . operand [ op_alt [ i ] . matches ] ) ) || reg_fits_class_p ( op , op_alt [ i ] . cl , offset , mode ) ) { win = true ; break ; } } if ( ! win ) return false ; } } return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .