<s>
bool
LanaiInstrInfo
::
areMemAccessesTriviallyDisjoint
(
MachineInstr
&
MIa
,
MachineInstr
&
MIb
,
AliasAnalysis
*
AA
)
const
{
assert
(
MIa
.
mayLoadOrStore
(
)
&&
"MIa must be a load or store."
)
;
assert
(
MIb
.
mayLoadOrStore
(
)
&&
"MIb must be a load or store."
)
;
if
(
MIa
.
hasUnmodeledSideEffects
(
)
||
MIb
.
hasUnmodeledSideEffects
(
)
||
MIa
.
hasOrderedMemoryRef
(
)
||
MIb
.
hasOrderedMemoryRef
(
)
)
return
false
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
unsigned
BaseRegA
=
0
,
BaseRegB
=
0
;
int64_t
OffsetA
=
0
,
OffsetB
=
0
;
unsigned
int
WidthA
=
0
,
WidthB
=
0
;
if
(
getMemOpBaseRegImmOfsWidth
(
MIa
,
BaseRegA
,
OffsetA
,
WidthA
,
TRI
)
&&
getMemOpBaseRegImmOfsWidth
(
MIb
,
BaseRegB
,
OffsetB
,
WidthB
,
TRI
)
)
{
if
(
BaseRegA
==
BaseRegB
)
{
int
LowOffset
=
std
::
min
(
OffsetA
,
OffsetB
)
;
int
HighOffset
=
std
::
max
(
OffsetA
,
OffsetB
)
;
int
LowWidth
=
(
LowOffset
==
OffsetA
)
WidthA
:
WidthB
;
if
(
LowOffset
+
LowWidth
<=
HighOffset
)
return
true
;
}
}
return
false
;
}
</s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function & F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F . hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F . optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F . optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) { OutStreamer -> EmitLabel ( TIP . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( TIP . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> static unsigned getLinkageSize ( bool isPPC64 , bool isDarwinABI , bool isELFv2ABI ) { if ( isDarwinABI || isPPC64 ) return ( isELFv2ABI ? 4 : 6 ) * ( isPPC64 ? 8 : 4 ) ; return 8 ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s> StringRef AArch64NamedImmMapper :: toString ( uint32_t Value , bool & Valid ) const { for ( unsigned i = 0 ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value == Value ) { Valid = true ; return Pairs [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> FastISel * X86TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo ) const { return X86 :: createFastISel ( funcInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> SDNode * X86DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; auto & DL = MF -> getDataLayout ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( DL ) ) . getNode ( ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { if ( isa < VectorType > ( DataTy ) && DataTy -> getVectorNumElements ( ) == 1 ) return false ; Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( ( DataWidth == 32 || DataWidth == 64 ) && ST -> hasAVX ( ) ) || ( ( DataWidth == 8 || DataWidth == 16 ) && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
unsigned
DefaultBaseReg
=
X86
::
NoRegister
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
,
unsigned
FrontendSize
=
0
,
bool
UseUpRegs
=
false
,
bool
MaybeDirectBranchDest
=
true
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
||
DefaultBaseReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
std
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
DefaultBaseReg
=
DefaultBaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
Mem
.
FrontendSize
=
FrontendSize
;
Res
->
Mem
.
MaybeDirectBranchDest
=
MaybeDirectBranchDest
;
Res
->
UseUpRegs
=
UseUpRegs
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> static int rid_int128 ( void ) { int i ; for ( i = 0 ; i < NUM_INT_N_ENTS ; i ++ ) if ( int_n_enabled_p [ i ] && int_n_data [ i ] . bitsize == 128 ) return RID_INT_N_0 + i ; return RID_MAX + 1 ; } </s>

Helper function to find out which RID_INT_N_ * code is the one for __int128 , if any . Returns RID_MAX+1 if none apply , which is safe ( for our purposes , since we always expect to have __int128 ) to compare against .


<s> rtx return_addr_rtx ( int count , rtx frameaddr ) { rtx label ; rtx rp ; rtx saved_rp ; rtx ins ; if ( count != 0 ) return NULL_RTX ; rp = get_hard_reg_initial_val ( Pmode , 2 ) ; if ( TARGET_64BIT || TARGET_NO_SPACE_REGS ) return rp ; saved_rp = gen_reg_rtx ( Pmode ) ; emit_move_insn ( saved_rp , rp ) ; ins = copy_to_reg ( gen_rtx_AND ( Pmode , rp , MASK_RETURN_ADDR ) ) ; label = gen_label_rtx ( ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , ins ) , GEN_INT ( 0x4bc23fd1 ) , NE , NULL_RTX , SImode , 1 ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , plus_constant ( ins , 4 ) ) , GEN_INT ( 0x004010a1 ) , NE , NULL_RTX , SImode , 1 ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , plus_constant ( ins , 8 ) ) , GEN_INT ( 0x00011820 ) , NE , NULL_RTX , SImode , 1 ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_cmp_insn ( gen_rtx_MEM ( SImode , plus_constant ( ins , 12 ) ) , GEN_INT ( 0xe0400002 ) , NE , NULL_RTX , SImode , 1 ) ; emit_jump_insn ( gen_bne ( label ) ) ; emit_move_insn ( saved_rp , gen_rtx_MEM ( Pmode , memory_address ( Pmode , plus_constant ( frameaddr , - 24 ) ) ) ) ; emit_label ( label ) ; return saved_rp ; } </s>

Fetch the return address for the frame COUNT steps up from the current frame , after the prologue . FRAMEADDR is the frame pointer of the COUNT frame . We want to ignore any export stub remnants here . To handle this , we examine the code at the return address , and if it is an export stub , we return a memory rtx for the stub return address stored at frame-24 . The value returned is used in two different ways : 1 . To find a function 's caller . 2 . To change the return address for a function . This function handles most instances of case 1 ; however , it will fail if there are two levels of stubs to execute on the return path . The only way I believe that can happen is if the return value needs a parameter relocation , which never happens for C code . This function handles most instances of case 2 ; however , it will fail if we did not originally have stub code on the return path but will need stub code on the new return path . This can happen if the caller & callee are both in the main program , but the new return location is in a shared library .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void ix86_add_new_builtins ( HOST_WIDE_INT isa ) { if ( ( isa & deferred_isa_values ) == 0 ) return ; deferred_isa_values &= ~ isa ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; if ( ix86_builtins_isa [ i ] . leaf_p ) DECL_ATTRIBUTES ( decl ) = build_tree_list ( get_identifier ( "leaf" ) , NULL_TREE ) ; if ( ix86_builtins_isa [ i ] . nothrow_p ) TREE_NOTHROW ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s> static void mep_rewrite_mult ( rtx_insn * insn , rtx pattern ) { rtx hi_clobber ; hi_clobber = XVECEXP ( pattern , 0 , XVECLEN ( pattern , 0 ) - 1 ) ; XEXP ( hi_clobber , 0 ) = gen_rtx_REG ( SImode , HI_REGNO ) ; PATTERN ( insn ) = pattern ; INSN_CODE ( insn ) = - 1 ; } </s>

Replace INSN 's pattern with PATTERN , a multiplication PARALLEL . Change the last element of PATTERN from ( clobber ( scratch : SI ) ) to ( clobber ( reg : SI HI_REGNO ) ) .


<s> MCELFStreamer & SparcTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static void aarch64_emit_load_exclusive ( machine_mode mode , rtx rval , rtx mem , rtx model_rtx ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( mode ) { case QImode : gen = gen_aarch64_load_exclusiveqi ; break ; case HImode : gen = gen_aarch64_load_exclusivehi ; break ; case SImode : gen = gen_aarch64_load_exclusivesi ; break ; case DImode : gen = gen_aarch64_load_exclusivedi ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , model_rtx ) ) ; } </s>


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case SystemZISD :: RET_FLAG : return "SystemZISD::RET_FLAG" ; case SystemZISD :: CALL : return "SystemZISD::CALL" ; case SystemZISD :: BRCOND : return "SystemZISD::BRCOND" ; case SystemZISD :: CMP : return "SystemZISD::CMP" ; case SystemZISD :: UCMP : return "SystemZISD::UCMP" ; case SystemZISD :: SELECT : return "SystemZISD::SELECT" ; case SystemZISD :: PCRelativeWrapper : return "SystemZISD::PCRelativeWrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

SystemZ SystemZ SystemZISD::RET_FLAG "SystemZISD::RET_FLAG" SystemZISD::CALL "SystemZISD::CALL" SystemZISD::BRCOND "SystemZISD::BRCOND" SystemZISD::CMP "SystemZISD::CMP" SystemZISD::UCMP "SystemZISD::UCMP" SystemZISD::SELECT "SystemZISD::SELECT" SystemZISD::PCRelativeWrapper "SystemZISD::PCRelativeWrapper"


<s> static bool note_invalid_constants ( rtx insn , HOST_WIDE_INT address , int do_pushes ) { bool result = false ; int opno ; extract_insn ( insn ) ; if ( ! constrain_operands ( 1 ) ) fatal_insn_not_found ( insn ) ; if ( recog_data . n_alternatives == 0 ) return false ; preprocess_constraints ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( recog_op_alt [ opno ] [ which_alternative ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; result = true ; } else if ( GET_CODE ( op ) == MEM && GET_CODE ( XEXP ( op , 0 ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( op , 0 ) ) ) { if ( do_pushes ) { rtx cop = avoid_constant_pool_reference ( op ) ; if ( op == cop ) cop = get_pool_constant ( XEXP ( op , 0 ) ) ; push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , cop ) ; } result = true ; } } } return result ; } </s>

Scan INSN and note any of its operands that need fixing . If DO_PUSHES is false we do not actually push any of the fixups needed . The function returns TRUE if any fixups were needed/pushed . This is used by arm_memory_load_p ( ) which needs to know about loads of constants that will be converted into minipool loads .


<s> bool X86TargetLowering :: hasInlineStackProbe ( MachineFunction & MF ) const { if ( Subtarget . isOSWindows ( ) || MF . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) return false ; if ( MF . getFunction ( ) . hasFnAttribute ( "probe-stack" ) ) return MF . getFunction ( ) . getFnAttribute ( "probe-stack" ) . getValueAsString ( ) == "inline-asm" ; return false ; } </s>

Returns true if stack probing through inline assembly is requested .

X86 X86 "no-stack-arg-probe" "probe-stack" "probe-stack" "inline-asm"


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
.
bitcastToAPInt
(
)
.
getZExtValue
(
)
;
if
(
!
getFPImmIsExact
(
)
)
OS
<<
" (inexact)"
;
OS
<<
">"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_BTIHint
:
OS
<<
getBTIHintName
(
)
;
break
;
case
k_MatrixRegister
:
OS
<<
"<matrix "
<<
getMatrixReg
(
)
<<
">"
;
break
;
case
k_MatrixTileList
:
{
OS
<<
"<matrixlist "
;
unsigned
RegMask
=
getMatrixTileListRegMask
(
)
;
unsigned
MaxBits
=
8
;
for
(
unsigned
I
=
MaxBits
;
I
>
0
;
I
)
OS
<<
(
(
RegMask
&
(
1
<<
(
I
1
)
)
)
>>
(
I
1
)
)
;
OS
<<
'>'
;
break
;
}
case
k_SVCR
:
{
OS
<<
getSVCR
(
)
;
break
;
}
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
" (inexact)"
">"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<matrix "
">"
"<matrixlist "
8
0
1
1
1
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s> static tree arm_convert_to_type ( tree type , tree expr ) { tree fromtype = TREE_TYPE ( expr ) ; if ( ! SCALAR_FLOAT_TYPE_P ( fromtype ) || ! SCALAR_FLOAT_TYPE_P ( type ) ) return NULL_TREE ; if ( ( TYPE_PRECISION ( fromtype ) == 16 && TYPE_PRECISION ( type ) > 32 ) || ( TYPE_PRECISION ( type ) == 16 && TYPE_PRECISION ( fromtype ) > 32 ) ) return convert ( type , convert ( float_type_node , expr ) ) ; return NULL_TREE ; } </s>

Implement TARGET_CONVERT_TO_TYPE . Specifically , this hook implements the peculiarity of the ARM half-precision floating-point C semantics that requires conversions between __fp16 to or from double to do an intermediate conversion to float .


<s> void Reset ( ) { Ops . clear ( ) ; OpBegins . clear ( ) ; OpBegins . push_back ( 0 ) ; HasPersonality = 0 ; } </s>


<s> static void rs6000_init_sched_context ( void * _sc , bool clean_p ) { rs6000_sched_context_t sc = ( rs6000_sched_context_t ) _sc ; if ( clean_p ) { sc -> cached_can_issue_more = 0 ; sc -> last_scheduled_insn = NULL ; sc -> load_store_pendulum = 0 ; sc -> divide_cnt = 0 ; sc -> vec_pairing = 0 ; } else { sc -> cached_can_issue_more = cached_can_issue_more ; sc -> last_scheduled_insn = last_scheduled_insn ; sc -> load_store_pendulum = load_store_pendulum ; sc -> divide_cnt = divide_cnt ; sc -> vec_pairing = vec_pairing ; } } </s>

If CLEAN_P is true then initializes _SC with clean data , and from the global context otherwise .


<s>
void
SystemZMCAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
BitSize
=
getFixupKindInfo
(
Kind
)
.
TargetSize
;
unsigned
Size
=
(
BitSize
+
7
)
/
8
;
assert
(
Offset
+
Size
<=
DataSize
&&
"Invalid fixup offset!"
)
;
Value
=
extractBitsForFixup
(
Kind
,
Value
)
;
if
(
BitSize
<
64
)
Value
&=
(
(
uint64_t
)
1
<<
BitSize
)
1
;
unsigned
ShiftValue
=
(
Size
*
8
)
8
;
for
(
unsigned
I
=
0
;
I
!=
Size
;
++
I
)
{
Data
[
Offset
+
I
]
|=
uint8_t
(
Value
>>
ShiftValue
)
;
ShiftValue
-=
8
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool rs6000_is_valid_2insn_and ( rtx c , machine_mode mode ) { if ( rs6000_is_valid_mask ( c , NULL , NULL , mode ) ) return true ; unsigned HOST_WIDE_INT val = INTVAL ( c ) ; unsigned HOST_WIDE_INT bit1 = val & - val ; unsigned HOST_WIDE_INT bit2 = ( val + bit1 ) & ~ val ; unsigned HOST_WIDE_INT val1 = ( val + bit1 ) & val ; unsigned HOST_WIDE_INT bit3 = val1 & - val1 ; return rs6000_is_valid_and_mask ( GEN_INT ( val + bit3 - bit2 ) , mode ) ; } </s>

Return whether an AND with C ( a CONST_INT ) in mode MODE can be done using two machine instructions .


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; SDLoc dl ( N ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; DAG . computeKnownBits ( SDValue ( N , 0 ) , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s> unsigned MipsTargetLowering :: getJumpTableEncoding ( ) const { if ( ABI . IsN64 ( ) ) return MachineJumpTableInfo :: EK_GPRel64BlockAddress ; return TargetLowering :: getJumpTableEncoding ( ) ; } </s>

Return the entry encoding for a jump table in the current function .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AArch64FI = MF . getInfo < AArch64FunctionInfo > ( ) ; STI = & MF . getSubtarget < AArch64Subtarget > ( ) ; SetupMachineFunction ( MF ) ; if ( STI -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> emitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


"-m64 requires PowerPC64 architecture, enabling"

The Darwin version of SUBTARGET_OVERRIDE_OPTIONS .


<s> static int vfp_emit_fstmd ( int base_reg , int count ) { rtx par ; rtx dwarf ; rtx tmp , reg ; int i ; if ( count == 2 && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - 3 ) base_reg -= 2 ; count ++ ; } if ( count > 16 ) { int saved ; saved = vfp_emit_fstmd ( base_reg + 32 , count - 16 ) ; saved += vfp_emit_fstmd ( base_reg , 16 ) ; return saved ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; tmp = gen_rtx_SET ( gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 1 ) = tmp ; for ( i = 1 ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , i * 8 ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , i + 1 ) = tmp ; } par = emit_insn ( par ) ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; return count * 8 ; } </s>

Emit RTL to save block of VFP register pairs to the stack . Returns the number of bytes pushed .


<s> void SystemZTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { if ( Constraint . length ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 8 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'J' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isUInt < 12 > ( C -> getZExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'K' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 16 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'L' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( isInt < 20 > ( C -> getSExtValue ( ) ) ) Ops . push_back ( DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ) ; return ; case 'M' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) if ( C -> getZExtValue ( ) == 0x7fffffff ) Ops . push_back ( DAG . getTargetConstant ( C -> getZExtValue ( ) , Op . getValueType ( ) ) ) ; return ; } } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( ! MF . getTarget ( ) . Options . RealignStack ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: None ) { const Function & F = MF . getFunction ( ) ; if ( Subtarget . hasQPX ( ) && Size >= 32 && ( ! IsMemset || Size >= 64 ) && ( ! SrcAlign || SrcAlign >= 32 ) && ( ! DstAlign || DstAlign >= 32 ) && ! F . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { return MVT :: v4f64 ; } if ( Subtarget . hasAltivec ( ) && Size >= 16 && ( ( ( ! SrcAlign || SrcAlign >= 16 ) && ( ! DstAlign || DstAlign >= 16 ) ) || ( ( IsMemset && Subtarget . hasVSX ( ) ) || Subtarget . hasP8Vector ( ) ) ) ) return MVT :: v4i32 ; } if ( Subtarget . isPPC64 ( ) ) { return MVT :: i64 ; } return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> void advance ( ) { assert ( Current != - 1 ) ; Current = Set . V . find_next ( Current ) ; } </s>

Advance across the current instruction .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> enum reg_class mmix_preferred_output_reload_class ( rtx x ATTRIBUTE_UNUSED , enum reg_class class ) { return GET_CODE ( x ) == MOD && GET_MODE ( x ) == DImode ? REMAINDER_REG : class ; } </s>

PREFERRED_OUTPUT_RELOAD_CLASS . We need to extend the reload class of REMAINDER_REG and HIMULT_REG .


<s> void FixupLEAPass :: processInstruction ( MachineBasicBlock :: iterator & I , MachineFunction :: iterator MFI ) { MachineInstr & MI = * I ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int AddrOffset = X86II :: getMemoryOperandNo ( Desc . TSFlags ) ; if ( AddrOffset >= 0 ) { AddrOffset += X86II :: getOperandBias ( Desc ) ; MachineOperand & p = MI . getOperand ( AddrOffset + X86 :: AddrBaseReg ) ; if ( p . isReg ( ) && p . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI . getOperand ( AddrOffset + X86 :: AddrIndexReg ) ; if ( q . isReg ( ) && q . getReg ( ) != X86 :: ESP ) { seekLEAFixup ( q , I , MFI ) ; } } } </s>

Process a single instruction and collect debug info anchors .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsSubtarget & STI ) { if ( STI . inMips16Mode ( ) ) return llvm :: createMips16InstrInfo ( STI ) ; return llvm :: createMipsSEInstrInfo ( STI ) ; } </s>


<s> static rtx ia64_struct_value_rtx ( tree fntype , int incoming ATTRIBUTE_UNUSED ) { if ( TARGET_ABI_OPEN_VMS || ( fntype && ia64_struct_retval_addr_is_first_parm_p ( fntype ) ) ) return NULL_RTX ; return gen_rtx_REG ( Pmode , GR_REG ( 8 ) ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> bool sh2a_function_vector_p ( tree func ) { if ( TREE_CODE ( func ) != FUNCTION_DECL ) return false ; for ( tree list = SH_ATTRIBUTES ( func ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( "function_vector" , get_attribute_name ( list ) ) ) return true ; return false ; } </s>

Returns true if FUNC has been assigned the attribute `` function_vector '' .


<s> bool nds32_n7_load_to_ii_p ( rtx_insn * producer , rtx_insn * consumer ) { if ( post_update_insn_p ( producer ) ) return false ; rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return n7_consumed_by_ii_dep_p ( consumer , def_reg ) ; } </s>


<s> void func_fma_steering :: analyze ( ) { int i , n_blocks , * bb_dfs_preorder ; basic_block bb ; rtx_insn * insn ; bb_dfs_preorder = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n_blocks = pre_and_rev_post_order_compute ( bb_dfs_preorder , NULL , false ) ; for ( i = 0 ; i < n_blocks ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , bb_dfs_preorder [ i ] ) ; FOR_BB_INSNS ( bb , insn ) { operand_rr_info * dest_op_info ; struct du_chain * chain ; unsigned dest_regno ; fma_forest * forest ; du_head_p head ; int i ; if ( ! is_fmul_fmac_insn ( insn , true ) ) continue ; dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = 0 ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; forest = NULL ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * * fma_slot ; if ( ! is_fmul_fmac_insn ( chain -> insn , true ) ) continue ; if ( chain -> loc != & SET_DEST ( PATTERN ( chain -> insn ) ) ) continue ; if ( chain -> insn == insn ) break ; fma_slot = this -> m_insn_fma_head_map -> get ( chain -> insn ) ; if ( fma_slot && ( * fma_slot ) -> get_children ( ) ) forest = ( * fma_slot ) -> get_forest ( ) ; } if ( chain ) break ; } gcc_assert ( i < dest_op_info -> n_chains ) ; this -> analyze_fma_fmul_insn ( forest , chain , head ) ; } } free ( bb_dfs_preorder ) ; if ( dump_file ) this -> dfs ( dump_forest_info , dump_tree_root_info , dump_tree_node_info , false ) ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s> const char * VETargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case VEISD :: NAME : \ return "VEISD::" # NAME ; switch ( ( VEISD :: NodeType ) Opcode ) { case VEISD :: FIRST_NUMBER : break ; TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

VE VE VEISD::NAME "VEISD::" VEISD::NodeType VEISD::FIRST_NUMBER


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; AArch64BranchTargetAligner BTA ; unsigned Opcode = Inst . getOpcode ( ) ; if ( BTA . needsSpecialAlignment ( STI . getCPU ( ) , Opcode ) ) { unsigned BA = BTA . getBranchTargetAlignment ( Inst ) ; if ( BA ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitCodeAlignment ( BA ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned X86TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { if ( classifyEHPersonality ( PersonalityFn ) == EHPersonality :: CoreCLR ) return Subtarget -> isTarget64BitLP64 ( ) ? X86 :: RDX : X86 :: EDX ; return Subtarget -> isTarget64BitLP64 ( ) ? X86 :: RAX : X86 :: EAX ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


"  rs6000_builtin_decls[RS6000_BIF_NONE] = NULL_TREE;\n"

"  rs6000_builtin_decls[RS6000_BIF_MAX] = NULL_TREE;\n"

"  rs6000_builtin_decls[RS6000_OVLD_NONE] = NULL_TREE;\n\n"

Write everything to the initialization file ( rs6000-builtins.cc ) . Return 1 if successful , 0 otherwise .


<s> static bool dimode_scalar_to_vector_candidate_p ( rtx_insn * insn ) { rtx def_set = single_set ( insn ) ; if ( ! def_set ) return false ; if ( has_non_address_hard_reg ( insn ) ) return false ; rtx src = SET_SRC ( def_set ) ; rtx dst = SET_DEST ( def_set ) ; if ( GET_CODE ( src ) == COMPARE ) return convertible_comparison_p ( insn ) ; if ( ( GET_MODE ( src ) != DImode && ! CONST_INT_P ( src ) ) || GET_MODE ( dst ) != DImode ) return false ; if ( ! REG_P ( dst ) && ! MEM_P ( dst ) ) return false ; switch ( GET_CODE ( src ) ) { case ASHIFTRT : if ( ! TARGET_AVX512VL ) return false ; case ASHIFT : case LSHIFTRT : if ( ! REG_P ( XEXP ( src , 1 ) ) && ( ! SUBREG_P ( XEXP ( src , 1 ) ) || SUBREG_BYTE ( XEXP ( src , 1 ) ) != 0 || ! REG_P ( SUBREG_REG ( XEXP ( src , 1 ) ) ) ) && ( ! CONST_INT_P ( XEXP ( src , 1 ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , 1 ) ) , 0 , 63 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != QImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , 1 ) ) && ! MEM_P ( XEXP ( src , 1 ) ) && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 1 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 1 ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , 0 ) ) && ! MEM_P ( XEXP ( src , 0 ) ) && ! CONST_INT_P ( XEXP ( src , 0 ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , 0 ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , 0 ) , 0 ) ) ) ) return false ; if ( GET_MODE ( XEXP ( src , 0 ) ) != DImode && ! CONST_INT_P ( XEXP ( src , 0 ) ) ) return false ; return true ; } </s>

The DImode version of scalar_to_vector_candidate_p .


<s> static bool nds32_legitimate_index_p ( machine_mode outer_mode , rtx index , bool strict ) { int regno ; rtx op0 ; rtx op1 ; switch ( GET_CODE ( index ) ) { case REG : regno = REGNO ( index ) ; if ( strict ) return REGNO_OK_FOR_INDEX_P ( regno ) ; else return true ; case CONST_INT : if ( GET_MODE_SIZE ( outer_mode ) == 1 ) { if ( ! satisfies_constraint_Is15 ( index ) ) return false ; return true ; } if ( GET_MODE_SIZE ( outer_mode ) == 2 && NDS32_HALF_WORD_ALIGN_P ( INTVAL ( index ) ) ) { if ( ! satisfies_constraint_Is16 ( index ) ) return false ; return true ; } if ( GET_MODE_SIZE ( outer_mode ) == 4 && NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) { if ( ! satisfies_constraint_Is17 ( index ) ) return false ; return true ; } if ( GET_MODE_SIZE ( outer_mode ) == 8 && NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( index ) ) ) { if ( ! satisfies_constraint_Is17 ( gen_int_mode ( INTVAL ( index ) + 4 , SImode ) ) ) return false ; return true ; } return false ; case MULT : op0 = XEXP ( index , 0 ) ; op1 = XEXP ( index , 1 ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { int multiplier ; multiplier = INTVAL ( op1 ) ; if ( multiplier != 1 && multiplier != 2 && multiplier != 4 ) return false ; regno = REGNO ( op0 ) ; if ( strict ) return REGNO_OK_FOR_INDEX_P ( regno ) ; else return true ; } return false ; case ASHIFT : op0 = XEXP ( index , 0 ) ; op1 = XEXP ( index , 1 ) ; if ( REG_P ( op0 ) && CONST_INT_P ( op1 ) ) { int sv ; sv = INTVAL ( op1 ) ; if ( sv != 0 && sv != 1 && sv != 2 ) return false ; regno = REGNO ( op0 ) ; if ( strict ) return REGNO_OK_FOR_INDEX_P ( regno ) ; else return true ; } return false ; default : return false ; } } </s>

Function that check if 'INDEX ' is valid to be a index rtx for address . OUTER_MODE : Machine mode of outer address rtx . INDEX : Check if this rtx is valid to be a index for address . STRICT : If it is true , we are in reload pass or after reload pass .


<s> static const struct mips_cpu_info * mips_default_arch ( void ) { unsigned int i ; for ( i = 0 ; i < ARRAY_SIZE ( mips_cpu_info_table ) ; i ++ ) if ( strcmp ( mips_cpu_info_table [ i ] . name , MIPS_CPU_STRING_DEFAULT ) == 0 ) return mips_cpu_info_table + i ; gcc_unreachable ( ) ; return mips_cpu_info_from_isa ( MIPS_ISA_DEFAULT ) ; return mips_cpu_info_from_opt ( MIPS_ARCH_OPTION_FROM_ABI ) ; } </s>

Return a default mips_cpu_info entry , given that no -march= option was explicitly specified .


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s>
char
*
xstormy16_output_cbranch_si
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx
insn
)
{
static
char
string
[
64
]
;
int
need_longbranch
=
get_attr_length
(
insn
)
>=
8
;
int
really_reversed
=
reversed
^
need_longbranch
;
const
char
*
ccode
;
const
char
*
template
;
char
prevop
[
16
]
;
enum
rtx_code
code
;
code
=
GET_CODE
(
op
)
;
if
(
really_reversed
)
code
=
reverse_condition
(
code
)
;
switch
(
code
)
{
case
EQ
:
ccode
=
"z"
;
break
;
case
NE
:
ccode
=
"nz"
;
break
;
case
GE
:
ccode
=
"ge"
;
break
;
case
LT
:
ccode
=
"lt"
;
break
;
case
GEU
:
ccode
=
"nc"
;
break
;
case
LTU
:
ccode
=
"c"
;
break
;
default
:
gcc_unreachable
(
)
;
}
switch
(
code
)
{
case
EQ
:
case
NE
:
{
int
regnum
;
gcc_assert
(
GET_CODE
(
XEXP
(
op
,
0
)
)
==
REG
)
;
regnum
=
REGNO
(
XEXP
(
op
,
0
)
)
;
sprintf
(
prevop
,
"or %s,%s"
,
reg_names
[
regnum
]
,
reg_names
[
regnum
+
1
]
)
;
}
break
;
case
GE
:
case
LT
:
case
GEU
:
case
LTU
:
strcpy
(
prevop
,
"sbc %2,%3"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
need_longbranch
)
template
=
"%s | b%s .+6 | jmpf %s"
;
else
template
=
"%s | b%s %s"
;
sprintf
(
string
,
template
,
prevop
,
ccode
,
label
)
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , which is the operand number of the label , but suitable for the tail of a SImode branch . OP is the conditional expression ( OP is never NULL_RTX ) . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the insn .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s>
LLVM_DUMP_METHOD
void
dump
(
const
MachineRegisterInfo
*
MRI
)
const
{
dbgs
(
)
<<
"Registers: "
;
bool
First
=
true
;
for
(
unsigned
Reg
:
Edges
)
{
if
(
!
First
)
dbgs
(
)
<<
", "
;
First
=
false
;
dbgs
(
)
<<
printReg
(
Reg
,
MRI
->
getTargetRegisterInfo
(
)
)
;
}
dbgs
(
)
<<
"\n"
<<
"Instructions:"
;
for
(
MachineInstr
*
MI
:
Instrs
)
{
dbgs
(
)
<<
"\n  "
;
MI
->
print
(
dbgs
(
)
)
;
}
dbgs
(
)
<<
"\n"
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"Registers: "
", "
"\n"
"Instructions:"
"\n  "
"\n"


<s> bool X86TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; CallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! IsTailCallConvention ( CalleeCC ) && ! IsCCallConvention ( CalleeCC ) ) return false ; return true ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s>
bool
AArch64InstrInfo
::
isCandidateToMergeOrPair
(
MachineInstr
*
MI
)
const
{
if
(
MI
->
hasOrderedMemoryRef
(
)
)
return
false
;
assert
(
MI
->
getOperand
(
1
)
.
isReg
(
)
&&
"Expected a reg operand."
)
;
if
(
!
MI
->
getOperand
(
2
)
.
isImm
(
)
)
return
false
;
unsigned
BaseReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
if
(
MI
->
modifiesRegister
(
BaseReg
,
TRI
)
)
return
false
;
if
(
isLdStPairSuppressed
(
MI
)
)
return
false
;
if
(
Subtarget
.
avoidQuadLdStPairs
(
)
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDURQi
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDRQui
:
case
AArch64
::
STRQui
:
return
false
;
}
}
return
true
;
}
</s>

Return true if this is a load/store that can be potentially paired/merged .


<s> static tree ix86_stack_protect_guard ( void ) { if ( TARGET_SSP_TLS_GUARD ) return NULL_TREE ; return default_stack_protect_guard ( ) ; } </s>

If using TLS guards , do n't waste time creating and expanding __stack_chk_guard decl and MEM as we are going to ignore it .


"\nrs6000_mode_dependent_address: ret = %s\n"

Debug version of rs6000_mode_dependent_address .


<s> std :: pair < unsigned , const TargetRegisterClass * > SystemZTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'r' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: GR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: GR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: GR32BitRegClass ) ; case 'a' : if ( VT == MVT :: i64 ) return std :: make_pair ( 0U , & SystemZ :: ADDR64BitRegClass ) ; else if ( VT == MVT :: i128 ) return std :: make_pair ( 0U , & SystemZ :: ADDR128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: ADDR32BitRegClass ) ; case 'f' : if ( VT == MVT :: f64 ) return std :: make_pair ( 0U , & SystemZ :: FP64BitRegClass ) ; else if ( VT == MVT :: f128 ) return std :: make_pair ( 0U , & SystemZ :: FP128BitRegClass ) ; return std :: make_pair ( 0U , & SystemZ :: FP32BitRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIdx
)
>=
TRI
->
getSpillSize
(
*
RC
)
&&
"Stack slot too small for store"
)
;
if
(
RC
->
getID
(
)
==
X86
::
TILERegClassID
)
{
unsigned
Opc
=
X86
::
TILESTORED
;
MachineRegisterInfo
&
RegInfo
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
Register
VirtReg
=
RegInfo
.
createVirtualRegister
(
&
X86
::
GR64_NOSPRegClass
)
;
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
X86
::
MOV64ri
)
,
VirtReg
)
.
addImm
(
64
)
;
MachineInstr
*
NewMI
=
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
MachineOperand
&
MO
=
NewMI
->
getOperand
(
2
)
;
MO
.
setReg
(
VirtReg
)
;
MO
.
setIsKill
(
true
)
;
}
else
if
(
RC
->
getID
(
)
==
X86
::
TILECFGRegClassID
)
{
unsigned
Opc
=
X86
::
PSTTILECFG
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
else
{
unsigned
Alignment
=
std
::
max
<
uint32_t
>
(
TRI
->
getSpillSize
(
*
RC
)
,
16
)
;
bool
isAligned
=
(
Subtarget
.
getFrameLowering
(
)
->
getStackAlign
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
Subtarget
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DebugLoc
(
)
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void union_uses ( swap_web_entry * insn_entry , rtx insn , df_ref def ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_out = 1 ; if ( DF_REF_INSN_INFO ( link -> ref ) ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; if ( NONDEBUG_INSN_P ( use_insn ) ) unionfind_union ( insn_entry + INSN_UID ( insn ) , insn_entry + INSN_UID ( use_insn ) ) ; } link = link -> next ; } } </s>

Union INSN with all insns containing uses reached from DEF . Detect whether DEF is live-out from the current function .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool X86InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; switch ( MI -> getOpcode ( ) ) { case X86 :: V_SET0 : return Expand2AddrUndef ( MI , get ( HasAVX ? X86 :: VPXORrr : X86 :: PXORrr ) ) ; case X86 :: TEST8ri_NOREX : MI -> setDesc ( get ( X86 :: TEST8ri ) ) ; return true ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Kudeyar Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> MCLOHType getKind ( ) const { return Kind ; } </s>


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const AArch64Subtarget & ST = C -> MF -> getSubtarget < AArch64Subtarget > ( ) ; if ( ST . hasFuseAES ( ) || ST . hasFuseLiterals ( ) ) { ScheduleDAGMI * DAG = createGenericSchedPostRA ( C ) ; DAG -> addMutation ( createAArch64MacroFusionDAGMutation ( ) ) ; return DAG ; } return nullptr ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static void emit_cbcond_insn ( enum rtx_code code , rtx op0 , rtx op1 , rtx label ) { rtx if_then_else ; if_then_else = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , if_then_else ) ) ; } </s>

Emit a conditional jump insn for the UA2011 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the UA2011 Compare and Branch insns .


"Only FP0 could be passed as an argument"

runOnMachineFunction - Emit the function body .


<s> MachineInstr * PPCInstrInfo :: findLoopInstr ( MachineBasicBlock & PreHeader ) const { unsigned LOOPi = ( Subtarget . isPPC64 ( ) ? PPC :: MTCTR8loop : PPC :: MTCTRloop ) ; for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( ) == LOOPi ) return & I ; return nullptr ; } </s>

Find the hardware loop instruction used to set-up the specified loop .

PowerPC PPC PPC PPC::MTCTR8loop PPC::MTCTRloop


<s>
static
void
ia64_asm_unwind_emit
(
FILE
*
out_file
,
rtx_insn
*
insn
)
{
bool
unwind
=
ia64_except_unwind_info
(
&
global_options
)
==
UI_TARGET
;
bool
frame
=
dwarf2out_do_frame
(
)
;
rtx
note
,
pat
;
bool
handled_one
;
if
(
!
unwind
&&
!
frame
)
return
;
if
(
NOTE_INSN_BASIC_BLOCK_P
(
insn
)
)
{
last_block
=
NOTE_BASIC_BLOCK
(
insn
)
->
next_bb
==
EXIT_BLOCK_PTR_FOR_FN
(
cfun
)
;
if
(
need_copy_state
)
{
if
(
unwind
)
{
fprintf
(
out_file
,
"\t.body\n"
)
;
fprintf
(
out_file
,
"\t.copy_state %d\n"
,
cfun
->
machine
->
state_num
)
;
}
need_copy_state
=
false
;
}
}
if
(
NOTE_P
(
insn
)
||
!
RTX_FRAME_RELATED_P
(
insn
)
)
return
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_alloc
)
{
rtx
dest
=
SET_DEST
(
XVECEXP
(
PATTERN
(
insn
)
,
0
,
0
)
)
;
int
dest_regno
=
REGNO
(
dest
)
;
if
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_pfs
]
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.pfs, r%d\n"
,
ia64_dbx_register_number
(
dest_regno
)
)
;
}
else
{
if
(
current_frame_info
.
total_size
==
0
&&
!
frame_pointer_needed
)
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.prologue\n"
)
;
}
return
;
}
handled_one
=
false
;
for
(
note
=
REG_NOTES
(
insn
)
;
note
;
note
=
XEXP
(
note
,
1
)
)
switch
(
REG_NOTE_KIND
(
note
)
)
{
case
REG_CFA_ADJUST_CFA
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_adjust_cfa
(
out_file
,
pat
,
insn
,
unwind
,
frame
)
;
handled_one
=
true
;
break
;
case
REG_CFA_OFFSET
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_offset
(
out_file
,
pat
,
unwind
)
;
handled_one
=
true
;
break
;
case
REG_CFA_REGISTER
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_register
(
out_file
,
pat
,
unwind
)
;
handled_one
=
true
;
break
;
case
REG_FRAME_RELATED_EXPR
:
case
REG_CFA_DEF_CFA
:
case
REG_CFA_EXPRESSION
:
case
REG_CFA_RESTORE
:
case
REG_CFA_SET_VDRAP
:
gcc_unreachable
(
)
;
default
:
break
;
}
gcc_assert
(
handled_one
)
;
}
</s>

This function looks at a single insn and emits any directives required to unwind this insn .


<s> static void arm_emit_ldrd_pop ( unsigned long saved_regs_mask ) { int j = 0 ; int offset = 0 ; rtx par = NULL_RTX ; rtx dwarf = NULL_RTX ; rtx tmp , mem ; gcc_assert ( ! ( ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ) ) ; j = 0 ; while ( j <= LAST_ARM_REGNUM ) if ( saved_regs_mask & ( 1 << j ) ) { if ( ( j % 2 ) == 0 && ( saved_regs_mask & ( 1 << ( j + 1 ) ) ) && ( j + 1 ) != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( DImode , gen_rtx_REG ( DImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j + 1 ) , dwarf ) ; REG_NOTES ( tmp ) = dwarf ; offset += 8 ; j += 2 ; } else if ( j != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; offset += 4 ; j += 1 ; } else j ++ ; } else j ++ ; if ( offset > 0 ) { tmp = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = emit_insn ( tmp ) ; arm_add_cfa_adjust_cfa_note ( tmp , offset , stack_pointer_rtx , stack_pointer_rtx ) ; offset = 0 ; } if ( saved_regs_mask & ( 1 << PC_REGNUM ) ) { par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; tmp = gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , PC_REGNUM ) , gen_frame_mem ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 1 ) = tmp ; par = emit_jump_insn ( par ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , PC_REGNUM ) , NULL_RTX ) ; REG_NOTES ( par ) = dwarf ; arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD , stack_pointer_rtx , stack_pointer_rtx ) ; } } </s>

LDRD in ARM mode needs consecutive registers as operands . This function emits LDRD whenever possible , otherwise it emits single-word loads . It uses offset addressing and then generates one separate stack udpate . This provides more scheduling freedom , compared to writeback on every load . However , if the function returns using load into PC directly ( i.e. , if PC is in SAVED_REGS_MASK ) , the stack needs to be updated before the last load . TODO : Add a peephole optimization to recognize the new epilogue sequence as an LDM instruction whenever possible . TODO : Add peephole optimization to merge the load at stack-offset zero with the stack update instruction using load with writeback in post-index addressing mode .


<s>
DEBUG_FUNCTION
char
*
rs6000_debug_addr_mask
(
addr_mask_type
mask
,
bool
keep_spaces
)
{
static
char
ret
[
8
]
;
char
*
p
=
ret
;
if
(
(
mask
&
RELOAD_REG_VALID
)
!=
0
)
*
p
++
=
'v'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_MULTIPLE
)
!=
0
)
*
p
++
=
'm'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_INDEXED
)
!=
0
)
*
p
++
=
'i'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_QUAD_OFFSET
)
!=
0
)
*
p
++
=
'O'
;
else
if
(
(
mask
&
RELOAD_REG_OFFSET
)
!=
0
)
*
p
++
=
'o'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_INCDEC
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_PRE_MODIFY
)
!=
0
)
*
p
++
=
'+'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
if
(
(
mask
&
RELOAD_REG_AND_M16
)
!=
0
)
*
p
++
=
'&'
;
else
if
(
keep_spaces
)
*
p
++
=
' '
;
*
p
=
'\0'
;
return
ret
;
}
</s>

Inner function printing just the address mask for a particular reload register class .


<s>
unsigned
MipsCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
getMipsRegisterNumbering
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
getRelocation
(
MI
,
MO
)
,
true
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isCPI
(
)
)
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
getRelocation
(
MI
,
MO
)
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

Mips
Mips
Mips
"Unable to encode MachineOperand!"
0


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( shouldAssumeDSOLocal ( RM , TargetTriple , M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( RM != Reloc :: PIC_ ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
void
SystemZOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
break
;
case
KindToken
:
OS
<<
"Token:"
<<
getToken
(
)
;
break
;
case
KindReg
:
OS
<<
"Reg:"
<<
SystemZInstPrinter
::
getRegisterName
(
getReg
(
)
)
;
break
;
case
KindImm
:
OS
<<
"Imm:"
;
printMCExpr
(
getImm
(
)
,
OS
)
;
break
;
case
KindImmTLS
:
OS
<<
"ImmTLS:"
;
printMCExpr
(
getImmTLS
(
)
.
Imm
,
OS
)
;
if
(
getImmTLS
(
)
.
Sym
)
{
OS
<<
", "
;
printMCExpr
(
getImmTLS
(
)
.
Sym
,
OS
)
;
}
break
;
case
KindMem
:
{
const
MemOp
&
Op
=
getMem
(
)
;
OS
<<
"Mem:"
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Disp
)
;
if
(
Op
.
Base
)
{
OS
<<
"("
;
if
(
Op
.
MemKind
==
BDLMem
)
OS
<<
*
cast
<
MCConstantExpr
>
(
Op
.
Length
.
Imm
)
<<
","
;
else
if
(
Op
.
MemKind
==
BDRMem
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Length
.
Reg
)
<<
","
;
if
(
Op
.
Index
)
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Index
)
<<
","
;
OS
<<
SystemZInstPrinter
::
getRegisterName
(
Op
.
Base
)
;
OS
<<
")"
;
}
break
;
}
case
KindInvalid
:
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

SystemZ
SystemZ
"Token:"
"Reg:"
SystemZ
"Imm:"
"ImmTLS:"
", "
"Mem:"
"("
","
SystemZ
","
SystemZ
","
SystemZ
")"


<s> void OR1KRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
bool
SystemZInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
2
&&
"Invalid condition"
)
;
Cond
[
1
]
.
setImm
(
Cond
[
1
]
.
getImm
(
)
^
Cond
[
0
]
.
getImm
(
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> bool addrSinkUsingGEPs ( ) const override { return useAA ( ) || isTargetILP32 ( ) ; } </s>

Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic .


<s> static void rs6000_darwin64_record_arg_flush ( CUMULATIVE_ARGS * cum , HOST_WIDE_INT bitpos , rtx rvec [ ] , int * k ) { machine_mode mode ; unsigned int regno ; unsigned int startbit , endbit ; int this_regno , intregs , intoffset ; rtx reg ; if ( cum -> intoffset == - 1 ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - 1 ; if ( intoffset % BITS_PER_WORD != 0 ) { unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD ; if ( ! int_mode_for_size ( bits , 0 ) . exists ( & mode ) ) { intoffset = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; mode = word_mode ; } } else mode = word_mode ; startbit = ROUND_DOWN ( intoffset , BITS_PER_WORD ) ; endbit = ROUND_UP ( bitpos , BITS_PER_WORD ) ; intregs = ( endbit - startbit ) / BITS_PER_WORD ; this_regno = cum -> words + intoffset / BITS_PER_WORD ; if ( intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno ) cum -> use_stack = 1 ; intregs = MIN ( intregs , GP_ARG_NUM_REG - this_regno ) ; if ( intregs <= 0 ) return ; intoffset /= BITS_PER_UNIT ; do { regno = GP_ARG_MIN_REG + this_regno ; reg = gen_rtx_REG ( mode , regno ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; this_regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; mode = word_mode ; intregs -= 1 ; } while ( intregs > 0 ) ; } </s>

A subroutine of rs6000_darwin64_record_arg . Assign the bits of the structure between cum- > intoffset and bitpos to integer registers .


"********** ARM MVE VPT Optimisations **********\n"


<s>
BitVector
ARMBaseRegisterInfo
::
getReservedRegs
(
const
MachineFunction
&
MF
)
const
{
const
ARMSubtarget
&
STI
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
const
ARMFrameLowering
*
TFI
=
getFrameLowering
(
MF
)
;
BitVector
Reserved
(
getNumRegs
(
)
)
;
markSuperRegs
(
Reserved
,
ARM
::
SP
)
;
markSuperRegs
(
Reserved
,
ARM
::
PC
)
;
markSuperRegs
(
Reserved
,
ARM
::
FPSCR
)
;
markSuperRegs
(
Reserved
,
ARM
::
APSR_NZCV
)
;
if
(
TFI
->
hasFP
(
MF
)
)
markSuperRegs
(
Reserved
,
getFramePointerReg
(
STI
)
)
;
if
(
hasBasePointer
(
MF
)
)
markSuperRegs
(
Reserved
,
BasePtr
)
;
if
(
STI
.
isR9Reserved
(
)
)
markSuperRegs
(
Reserved
,
ARM
::
R9
)
;
const
Function
&
F
=
MF
.
getFunction
(
)
;
if
(
F
.
getCallingConv
(
)
==
CallingConv
::
Mono
)
markSuperRegs
(
Reserved
,
ARM
::
R8
)
;
if
(
!
STI
.
hasVFP3
(
)
||
STI
.
hasD16
(
)
)
{
static_assert
(
ARM
::
D31
==
ARM
::
D16
+
15
,
"Register list not consecutive!"
)
;
for
(
unsigned
R
=
0
;
R
<
16
;
++
R
)
markSuperRegs
(
Reserved
,
ARM
::
D16
+
R
)
;
}
const
TargetRegisterClass
&
RC
=
ARM
::
GPRPairRegClass
;
for
(
unsigned
Reg
:
RC
)
for
(
MCSubRegIterator
SI
(
Reg
,
this
)
;
SI
.
isValid
(
)
;
++
SI
)
if
(
Reserved
.
test
(
*
SI
)
)
markSuperRegs
(
Reserved
,
Reg
)
;
assert
(
checkAllSuperRegsMarked
(
Reserved
)
)
;
return
Reserved
;
}
</s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool Thumb1FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; bool isVarArg = AFI -> getArgRegsSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , TII . get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; if ( STI . hasV4TOps ( ) && ! STI . hasV5TOps ( ) ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( TII . get ( ARM :: tPOP_RET ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void validate_condition_mode ( enum rtx_code code , enum machine_mode mode ) { gcc_assert ( ( GET_RTX_CLASS ( code ) == RTX_COMPARE || GET_RTX_CLASS ( code ) == RTX_COMM_COMPARE ) && GET_MODE_CLASS ( mode ) == MODE_CC ) ; gcc_assert ( ( code != GT && code != LT && code != GE && code != LE ) || mode != CCUNSmode ) ; gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT && code != UNGT && code != UNLT ) ) ; gcc_assert ( mode != CCEQmode || code == EQ || code == NE ) ; } </s>

A validation routine : say whether CODE , a condition code , and MODE match . The other alternatives either do n't make sense or should never be generated .


<s> void arm_emit_call_insn ( rtx pat , rtx addr , bool sibcall ) { rtx insn ; insn = emit_call_insn ( pat ) ; if ( TARGET_VXWORKS_RTP && flag_pic && ! sibcall && GET_CODE ( addr ) == SYMBOL_REF && ( SYMBOL_REF_DECL ( addr ) ? ! targetm . binds_local_p ( SYMBOL_REF_DECL ( addr ) ) : ! SYMBOL_REF_LOCAL_P ( addr ) ) ) { require_pic_register ( NULL_RTX , false ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , cfun -> machine -> pic_reg ) ; } if ( TARGET_AAPCS_BASED ) { rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ; clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP_REGNUM ) ) ; } } </s>

Emit a call instruction with pattern PAT . ADDR is the address of the call target .


<s> static MipsOperand * CreateReg ( unsigned Index , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , MipsAsmParser & Parser ) { MipsOperand * Op = new MipsOperand ( k_RegisterIndex , Parser ) ; Op -> RegIdx . Index = Index ; Op -> RegIdx . RegInfo = RegInfo ; Op -> RegIdx . Kind = RegKind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


"  Mark r%d def in insn %d as requiring both modes in chain #%d\n"

For DImode conversion , mark register defined by DEF as requiring conversion .


<s> bool ARMAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( STI ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write ( OS , nopEncoding , Endian ) ; if ( Count & 1 ) OS << '\0' ; return true ; } const uint32_t nopEncoding = hasNOP ( STI ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) support :: endian :: write ( OS , nopEncoding , Endian ) ; switch ( Count % 4 ) { default : break ; case 1 : OS << '\0' ; break ; case 2 : OS . write ( "\0\0" , 2 ) ; break ; case 3 : OS . write ( "\0\0\xa0" , 3 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> rtx ix86_find_base_term ( rtx x ) { rtx term ; if ( TARGET_64BIT ) { if ( GET_CODE ( x ) != CONST ) return x ; term = XEXP ( x , 0 ) ; if ( GET_CODE ( term ) == PLUS && CONST_INT_P ( XEXP ( term , 1 ) ) ) term = XEXP ( term , 0 ) ; if ( GET_CODE ( term ) != UNSPEC || ( XINT ( term , 1 ) != UNSPEC_GOTPCREL && XINT ( term , 1 ) != UNSPEC_PCREL ) ) return x ; return XVECEXP ( term , 0 , 0 ) ; } return ix86_delegitimize_address ( x ) ; } </s>

If X is a machine specific address ( i.e . a symbol or label being referenced as a displacement from the GOT implemented using an UNSPEC ) , then return the base term . Otherwise return X .


<s>
unsigned
ARMCodeEmitter
::
getMachineOpValue
(
const
MachineInstr
&
MI
,
const
MachineOperand
&
MO
)
const
{
if
(
MO
.
isReg
(
)
)
return
II
->
getRegisterInfo
(
)
.
getEncodingValue
(
MO
.
getReg
(
)
)
;
else
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
else
if
(
MO
.
isGlobal
(
)
)
emitGlobalAddress
(
MO
.
getGlobal
(
)
,
ARM
::
reloc_arm_branch
,
true
,
false
)
;
else
if
(
MO
.
isSymbol
(
)
)
emitExternalSymbolAddress
(
MO
.
getSymbolName
(
)
,
ARM
::
reloc_arm_branch
)
;
else
if
(
MO
.
isCPI
(
)
)
{
const
MCInstrDesc
&
MCID
=
MI
.
getDesc
(
)
;
unsigned
Reloc
=
(
(
MCID
.
TSFlags
&
ARMII
::
FormMask
)
==
ARMII
::
VFPLdStFrm
)
ARM
::
reloc_arm_vfp_cp_entry
:
ARM
::
reloc_arm_cp_entry
;
emitConstPoolAddress
(
MO
.
getIndex
(
)
,
Reloc
)
;
}
else
if
(
MO
.
isJTI
(
)
)
emitJumpTableAddress
(
MO
.
getIndex
(
)
,
ARM
::
reloc_arm_relative
)
;
else
if
(
MO
.
isMBB
(
)
)
emitMachineBasicBlock
(
MO
.
getMBB
(
)
,
ARM
::
reloc_arm_branch
)
;
else
llvm_unreachable
(
"Unable to encode MachineOperand!"
)
;
return
0
;
}
</s>


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> bool PPCInstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ; if ( getFMAPatterns ( Root , Patterns , DoRegPressureReduce ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns , DoRegPressureReduce ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s>
void
TeeRISCInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
TeeRISC
::
IntRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
TeeRISC
::
OR
)
,
DestReg
)
.
addReg
(
TeeRISC
::
ZERO
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>

TeeRISC
TeeRISC
TeeRISC::IntRegsRegClass
TeeRISC::OR
TeeRISC::ZERO
"Impossible reg-to-reg copy"


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static bool aarch64_emit_cfi_for_reg_p ( unsigned int regno ) { return ( GP_REGNUM_P ( regno ) || ! default_function_abi . clobbers_full_reg_p ( regno ) ) ; } </s>

Return true if we should emit CFI for register REGNO .


<s> void altivec_expand_stvex_be ( rtx op0 , rtx op1 , machine_mode mode , unsigned unspec ) { machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx tmp = gen_reg_rtx ( mode ) ; rtx stvx = gen_rtx_UNSPEC ( inner_mode , gen_rtvec ( 1 , tmp ) , unspec ) ; rtx sel = swap_selector_for_mode ( mode ) ; rtx vperm ; gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( 3 , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , stvx ) ) ; } </s>

Generate code for a `` stve * x '' built-in for a little endian target with -maltivec=be specified . Issue the store preceded by an element-reversing permute .


<s> static void rs6000_set_handled_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> gpr_is_wrapped_separately [ i ] = true ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) if ( bitmap_bit_p ( components , i ) ) cfun -> machine -> fpr_is_wrapped_separately [ i - 32 ] = true ; if ( bitmap_bit_p ( components , 0 ) ) cfun -> machine -> lr_is_wrapped_separately = true ; if ( bitmap_bit_p ( components , 2 ) ) cfun -> machine -> toc_is_wrapped_separately = true ; } </s>


<s> static void mips_insert_insn_pseudos ( void ) { bool insn_pseudo_needed = TRUE ; rtx_insn * insn ; for ( insn = get_last_insn ( ) ; insn != NULL_RTX ; insn = PREV_INSN ( insn ) ) switch ( GET_CODE ( insn ) ) { case INSN : if ( GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPEC_CONSTTABLE ) { insn_pseudo_needed = TRUE ; break ; } case JUMP_INSN : case CALL_INSN : case JUMP_TABLE_DATA : insn_pseudo_needed = FALSE ; break ; case CODE_LABEL : if ( insn_pseudo_needed ) { emit_insn_after ( gen_insn_pseudo ( ) , insn ) ; insn_pseudo_needed = FALSE ; } break ; default : break ; } } </s>

Insert a ` .insn ' assembly pseudo-op after any labels followed by a MIPS16 constant pool or no insn at all . This is needed so that targets that have been optimized away are still marked as code and therefore branches that remained and point to them are known to retain the ISA mode and as such can be successfully assembled .


<s>
void
MipsCodeEmitter
::
emitInstruction
(
const
MachineInstr
&
MI
)
{
DEBUG
(
errs
(
)
<<
"JIT: "
<<
(
void
*
)
MCE
.
getCurrentPCValue
(
)
<<
":\t"
<<
MI
)
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
true
)
;
if
(
(
MI
.
getDesc
(
)
.
TSFlags
&
MipsII
::
FormMask
)
==
MipsII
::
Pseudo
)
return
;
emitWordLE
(
getBinaryCodeForInstr
(
MI
)
)
;
++
NumEmitted
;
MCE
.
processDebugLoc
(
MI
.
getDebugLoc
(
)
,
false
)
;
}
</s>

Targets should implement this to emit instructions .

Mips
Mips
"JIT: "
":\t"
MipsII::FormMask
MipsII::Pseudo


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11W ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15W ) ; Reserved . set ( SystemZ :: R14Q ) ; return Reserved ; } </s>


<s> virtual unsigned int execute ( function * ) { return rest_of_insert_bti ( ) ; } </s>


"Thumb2 instruction size reduction pass"

getPassName - Return a nice clean name for a pass .


<s> bool nds32_n13_load_to_e1_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer ) == TYPE_LOAD ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; return n13_consumed_by_e1_dep_p ( consumer , def_reg ) ; } </s>

Check dependencies from Load-Store Unit ( E3 ) to E1 .


<s> static int pa_issue_rate ( void ) { switch ( pa_cpu ) { case PROCESSOR_700 : return 1 ; case PROCESSOR_7100 : return 2 ; case PROCESSOR_7100LC : return 2 ; case PROCESSOR_7200 : return 2 ; case PROCESSOR_7300 : return 2 ; case PROCESSOR_8000 : return 4 ; default : gcc_unreachable ( ) ; } } </s>

The 700 can only issue a single insn at a time . The 7XXX processors can issue two insns at a time . The 8000 can issue 4 insns at a time .


<s> virtual void initializePass ( ) { pushTTIStack ( this ) ; } </s>

initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require .


<s> static bool ix86_nopic_noplt_attribute_p ( rtx call_op ) { if ( flag_pic || ix86_cmodel == CM_LARGE || ! ( TARGET_64BIT || HAVE_AS_IX86_GOT32X ) || TARGET_MACHO || TARGET_SEH || TARGET_PECOFF || SYMBOL_REF_LOCAL_P ( call_op ) ) return false ; tree symbol_decl = SYMBOL_REF_DECL ( call_op ) ; if ( ! flag_plt || ( symbol_decl != NULL_TREE && lookup_attribute ( "noplt" , DECL_ATTRIBUTES ( symbol_decl ) ) ) ) return true ; return false ; } </s>

Return true if the function being called was marked with attribute `` noplt '' or using -fno-plt and we are compiling for non-PIC and x86_64 . We need to handle the non-PIC case in the backend because there is no easy interface for the front-end to force non-PLT calls to use the GOT . This is currently used only with 64-bit ELF targets to call the function marked `` noplt '' indirectly .


<s> int ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static tree ix86_stack_protect_fail ( void ) { return TARGET_64BIT ? default_external_stack_protect_fail ( ) : default_hidden_stack_protect_fail ( ) ; } </s>

For 32-bit code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . 64-bit code does n't need to setup any PIC register , so it is better to call __stack_chk_fail directly .


<s> void MipsTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; this -> TM = & static_cast < const MipsTargetMachine & > ( TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> static void sh_emit_storesi ( rtx addr , HOST_WIDE_INT offset , rtx value ) { gcc_assert ( ( offset & 3 ) == 0 ) ; emit_move_insn ( offset == 0 ? change_address ( addr , SImode , NULL_RTX ) : adjust_address ( addr , SImode , offset ) , value ) ; } </s>

Emit insns to store a value at memory address + offset .


<s> StringRef getType ( ) { return CurType . Name ; } </s>

Overload to return most specific vector type .


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s> static enum loongarch_symbol_type loongarch_classify_symbol ( const_rtx x ) { enum loongarch_symbol_type pcrel = TARGET_CMODEL_EXTREME ? SYMBOL_PCREL64 : SYMBOL_PCREL ; if ( ! SYMBOL_REF_P ( x ) ) return pcrel ; if ( SYMBOL_REF_TLS_MODEL ( x ) ) return SYMBOL_TLS ; if ( ! loongarch_symbol_binds_local_p ( x ) ) return SYMBOL_GOT_DISP ; tree t = SYMBOL_REF_DECL ( x ) ; if ( ! t ) return pcrel ; t = lookup_attribute ( "model" , DECL_ATTRIBUTES ( t ) ) ; if ( ! t ) return pcrel ; t = TREE_VALUE ( TREE_VALUE ( t ) ) ; gcc_assert ( TREE_CODE ( t ) == STRING_CST ) ; const char * model = TREE_STRING_POINTER ( t ) ; if ( strcmp ( model , "normal" ) == 0 ) return SYMBOL_PCREL ; if ( strcmp ( model , "extreme" ) == 0 ) return SYMBOL_PCREL64 ; gcc_unreachable ( ) ; } </s>

Return the method that should be used to access SYMBOL_REF or LABEL_REF X .

loongarch "model" "normal" 0 "extreme" 0


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < TargetPassConfig > ( ) ; AU . addPreserved < StackProtector > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


"%qs attribute only applies to functions"

"attribute interrupt_handler is not compatible with -m5-compact"

Handle an `` interrupt_handler '' attribute ; arguments as in struct attribute_spec.handler .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> OR1KSubtarget & OR1KSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> const char * SHUXITargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SHUXIISD :: NodeType ) Opcode ) { case SHUXIISD :: FIRST_NUMBER : break ; case SHUXIISD :: CMP : return "SHUXIISD::CMP" ; case SHUXIISD :: RET_FLAG : return "SHUXIISD::RET_FLAG" ; case SHUXIISD :: BR_CC : return "SHUXIISD::BR_CC" ; case SHUXIISD :: SELECT_CC : return "SHUXIISD::SELECT_CC" ; case SHUXIISD :: Wrapper : return "SHUXIISD::Wrapper" ; case SHUXIISD :: CALL : return "SHUXIISD::CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; rtx r12 = NULL_RTX ; rtx func_addr = func_desc ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( INTVAL ( cookie ) & CALL_LONG && SYMBOL_REF_P ( func_desc ) ) { gcc_assert ( rs6000_pcrel_p ( ) ) ; func_desc = rs6000_longcall_ref ( func_desc , tlsarg ) ; } else gcc_assert ( INTVAL ( cookie ) == 0 ) ; if ( GET_CODE ( func_desc ) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2 ) { r12 = gen_rtx_REG ( Pmode , 12 ) ; emit_move_insn ( r12 , func_desc ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , r12 ) ; } call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; if ( ! rs6000_pcrel_p ( ) ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; if ( r12 ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , r12 ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s>
void
SparcFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
SparcMachineFunctionInfo
*
FuncInfo
=
MF
.
getInfo
<
SparcMachineFunctionInfo
>
(
)
;
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
const
SparcInstrInfo
&
TII
=
*
static_cast
<
const
SparcInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
int
NumBytes
=
(
int
)
MFI
->
getStackSize
(
)
;
unsigned
SAVEri
=
SP
::
SAVEri
;
unsigned
SAVErr
=
SP
::
SAVErr
;
if
(
FuncInfo
->
isLeafProc
(
)
)
{
if
(
NumBytes
==
0
)
return
;
SAVEri
=
SP
::
ADDri
;
SAVErr
=
SP
::
ADDrr
;
}
NumBytes
=
MF
.
getSubtarget
<
SparcSubtarget
>
(
)
.
getAdjustedFrameSize
(
NumBytes
)
;
emitSPAdjustment
(
MF
,
MBB
,
MBBI
,
NumBytes
,
SAVErr
,
SAVEri
)
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
unsigned
regFP
=
MRI
->
getDwarfRegNum
(
SP
::
I6
,
true
)
;
unsigned
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaRegister
(
nullptr
,
regFP
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createWindowSave
(
nullptr
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
unsigned
regInRA
=
MRI
->
getDwarfRegNum
(
SP
::
I7
,
true
)
;
unsigned
regOutRA
=
MRI
->
getDwarfRegNum
(
SP
::
O7
,
true
)
;
CFIIndex
=
MMI
.
addFrameInst
(
MCCFIInstruction
::
createRegister
(
nullptr
,
regOutRA
,
regInRA
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .

Sparc
Sparc
Sparc
Sparc
"Shrink-wrapping not yet supported"
Sparc
Sparc
SP::SAVEri
SP::SAVErr
0
SP::ADDri
SP::ADDrr
Sparc
SP
SP::I6
SP::I7
SP::O7


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i16 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> static tree gen_stdcall_or_fastcall_suffix ( tree decl , tree id , bool fastcall ) { HOST_WIDE_INT total = 0 ; const char * old_str = IDENTIFIER_POINTER ( id != NULL_TREE ? id : DECL_NAME ( decl ) ) ; char * new_str , * p ; tree type = TREE_TYPE ( DECL_ORIGIN ( decl ) ) ; tree arg ; function_args_iterator args_iter ; gcc_assert ( TREE_CODE ( decl ) == FUNCTION_DECL ) ; if ( prototype_p ( type ) ) { if ( stdarg_p ( type ) ) return NULL_TREE ; FOREACH_FUNCTION_ARGS ( type , arg , args_iter ) { HOST_WIDE_INT parm_size ; HOST_WIDE_INT parm_boundary_bytes = PARM_BOUNDARY / BITS_PER_UNIT ; if ( ! COMPLETE_TYPE_P ( arg ) ) break ; parm_size = int_size_in_bytes ( arg ) ; if ( parm_size < 0 ) break ; parm_size = ( ( parm_size + parm_boundary_bytes - 1 ) / parm_boundary_bytes * parm_boundary_bytes ) ; total += parm_size ; } } p = new_str = XALLOCAVEC ( char , 1 + strlen ( old_str ) + 1 + 8 + 1 ) ; if ( fastcall ) * p ++ = FASTCALL_PREFIX ; sprintf ( p , "%s@" HOST_WIDE_INT_PRINT_DEC , old_str , total ) ; return get_identifier ( new_str ) ; } </s>

Return string which is the former assembler name modified with a suffix consisting of an atsign ( @ ) followed by the number of bytes of arguments . If FASTCALL is true , also add the FASTCALL_PREFIX .


<s> static bool isAssociativeAndCommutative ( unsigned Opcode ) { switch ( Opcode ) { case X86 :: ADDSDrr : case X86 :: ADDSSrr : case X86 :: VADDSDrr : case X86 :: VADDSSrr : case X86 :: MULSDrr : case X86 :: MULSSrr : case X86 :: VMULSDrr : case X86 :: VMULSSrr : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s>
void
Cpu0SEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Cpu0
::
ADDu
,
ZeroReg
=
Cpu0
::
ZERO
;
else
if
(
SrcReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MFHI
,
SrcReg
=
0
;
else
if
(
SrcReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MFLO
,
SrcReg
=
0
;
}
else
if
(
Cpu0
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
Cpu0
::
HI
)
Opc
=
Cpu0
::
MTHI
,
DestReg
=
0
;
else
if
(
DestReg
==
Cpu0
::
LO
)
Opc
=
Cpu0
::
MTLO
,
DestReg
=
0
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { GlobalBaseReg = 0 ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget . isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MipsAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; if ( const BasicBlock * bb = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( bb -> getTerminator ( ) ) ) return false ; if ( MBB -> isLandingPad ( ) || MBB -> pred_empty ( ) ) return false ; MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> getDesc ( ) . isTerminator ( ) ) ; return ! I -> getDesc ( ) . isBarrier ( ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> const char * ix86_output_indirect_jmp ( rtx call_op ) { if ( cfun -> machine -> indirect_branch_type != indirect_branch_keep ) { if ( ix86_red_zone_used ) gcc_unreachable ( ) ; ix86_output_indirect_branch ( call_op , "%0" , true ) ; } else output_asm_insn ( "%!jmp\t%A0" , & call_op ) ; return ( ix86_harden_sls & harden_sls_indirect_jmp ) ? "int3" : "" ; } </s>

Output indirect jump . CALL_OP is the jump target .


Create constant where bits outside of lowest bit set to highest bit set are set to 1 .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( this -> TRI -> hasBasePointer ( MF ) ) { if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % Align ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s>
SICSubtarget
&
SICSubtarget
::
initializeSubtargetDependencies
(
StringRef
CPU
,
StringRef
FS
,
const
TargetMachine
&
TM
)
{
if
(
TargetTriple
.
getArch
(
)
==
Triple
::
sic
)
{
if
(
CPU
.
empty
(
)
||
CPU
==
"generic"
)
{
CPU
=
"sicxe"
;
}
else
if
(
CPU
==
"help"
)
{
CPU
=
""
;
return
*
this
;
}
else
if
(
CPU
!=
"sicse"
&&
CPU
!=
"sicxe"
)
{
CPU
=
"sicxe"
;
}
}
else
{
errs
(
)
<<
"!!!Error, TargetTriple.getArch() = "
<<
TargetTriple
.
getArch
(
)
<<
"CPU = "
<<
CPU
<<
"\n"
;
exit
(
0
)
;
}
if
(
CPU
==
"sicse"
)
SICArchVersion
=
SICSE
;
else
if
(
CPU
==
"sicxe"
)
SICArchVersion
=
SICXE
;
ParseSubtargetFeatures
(
CPU
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPU
)
;
return
*
this
;
}
</s>

SIC
SIC
SIC
"generic"
"sicxe"
"help"
""
"sicse"
"sicxe"
"sicxe"
"!!!Error, TargetTriple.getArch() = "
"CPU = "
"\n"
0
"sicse"
SIC
SIC
"sicxe"
SIC
SIC


<s> align_flags rs6000_loop_align ( rtx label ) { basic_block bb ; int ninsns ; if ( ! can_override_loop_align ) return align_loops ; bb = BLOCK_FOR_INSN ( label ) ; ninsns = num_loop_insns ( bb -> loop_father ) ; if ( ninsns > 4 && ninsns <= 8 && ( rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5 || rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 ) ) return align_flags ( 5 ) ; else return align_loops ; } </s>


<s> static void xstormy16_print_operand_address ( FILE * file , rtx address ) { HOST_WIDE_INT offset ; int pre_dec , post_inc ; if ( CONST_INT_P ( address ) ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( address ) & 0xFFFF ) ; return ; } if ( CONSTANT_P ( address ) || LABEL_P ( address ) ) { output_addr_const ( file , address ) ; return ; } if ( GET_CODE ( address ) == PLUS ) { gcc_assert ( CONST_INT_P ( XEXP ( address , 1 ) ) ) ; offset = INTVAL ( XEXP ( address , 1 ) ) ; address = XEXP ( address , 0 ) ; } else offset = 0 ; pre_dec = ( GET_CODE ( address ) == PRE_DEC ) ; post_inc = ( GET_CODE ( address ) == POST_INC ) ; if ( pre_dec || post_inc ) address = XEXP ( address , 0 ) ; gcc_assert ( REG_P ( address ) ) ; fputc ( '(' , file ) ; if ( pre_dec ) fputs ( "--" , file ) ; fputs ( reg_names [ REGNO ( address ) ] , file ) ; if ( post_inc ) fputs ( "++" , file ) ; if ( offset != 0 ) fprintf ( file , "," HOST_WIDE_INT_PRINT_DEC , offset ) ; fputc ( ')' , file ) ; } </s>

Print a memory address as an operand to reference that memory location .


<s> static void * rs6000_init_cost ( struct loop * loop_info ) { rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = 0 ; data -> cost [ vect_body ] = 0 ; data -> cost [ vect_epilogue ] = 0 ; rs6000_vect_nonmem = false ; return data ; } </s>


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = FloatABI :: Soft ; } </s>


<s> int AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { int Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1