open Base

module type Rtl = sig
  module Language : sig
    type t =
      | Verilog
      | Vhdl
    [@@deriving sexp_of]

    val file_extension : t -> string
    val legalize_identifier : t -> string -> string
  end

  (** RTL generation options. *)
  module Output_mode : sig
    type t =
      | In_directory of string
* Write each circuit into a file in the given directory .   The file name consists 
           of the circuit name and the approriate file extension ( [ .v ] for Verilog and 
           [ .vhd ] for  ) .
          of the circuit name and the approriate file extension ([.v] for Verilog and
          [.vhd] for VHDL). *)
* Write all circuits into one buffer .
* Write all circuits to one out channel .
* Write all circuits into one file .
    [@@deriving sexp_of]
  end

* Control blackbox generation . [ None ] implies blackboxes are not used . [ Top ] means the 
       circuit will be turned into a blackbox . [ Instantiations ] means that the top level 
       circuit will be written as normal , but submodules will be written as blackboxes .
      circuit will be turned into a blackbox. [Instantiations] means that the top level
      circuit will be written as normal, but submodules will be written as blackboxes. *)
  module Blackbox : sig
    type t =
      | None
      | Top
      | Instantiations
    [@@deriving sexp_of]
  end

  module Uid_with_index : sig
    type t = Signal.Uid.t * int [@@deriving compare, sexp_of]

    include Comparator.S with type t := t
  end

  type signals_name_map_t = string Map.M(Uid_with_index).t

* Write circuit to [ Verilog ] or [ Vhdl ] .   Instantiations are ( recursively ) looked up in 
       [ database ] and if a circuit exists it is also written .   The [ output_mode ] specifies 
       how the circuit should be written - either to a single file ( or buffer , or channel ) 
       or to a directory with one file for each for the top level circuit and any 
       instantiated circuits contained in the database .
      [database] and if a circuit exists it is also written.  The [output_mode] specifies
      how the circuit should be written - either to a single file (or buffer, or channel)
      or to a directory with one file for each for the top level circuit and any
      instantiated circuits contained in the database. *)
  val output
    :  ?output_mode:Output_mode.t (** default is [To_file (Circuit.name circuit)]. *)
    -> ?database:Circuit_database.t (** default is an empty database  *)
    -> ?blackbox:Blackbox.t (** Default is [None] *)
    -> Language.t
    -> Circuit.t
    -> unit

  (** [print] is [output ~output_mode:(To_channel stdout)] *)
  val print
    :  ?database:Circuit_database.t
    -> ?blackbox:Blackbox.t (** Default is [None] *)
    -> Language.t
    -> Circuit.t
    -> unit

  module Digest : sig
    type t [@@deriving sexp_of]

    val create
      :  ?database:Circuit_database.t
      -> ?blackbox:Blackbox.t
      -> Language.t
      -> Circuit.t
      -> t

    val to_string : t -> String.t
  end

  module Expert : sig
    val output_with_name_map
      :  ?output_mode:Output_mode.t (** default is [To_file (Circuit.name circuit)]. *)
      -> ?database:Circuit_database.t (** default is an empty database  *)
      -> ?blackbox:Blackbox.t (** Default is [None] *)
      -> Language.t
      -> Circuit.t
      -> signals_name_map_t
  end
end

* RTL generation options. 
* default is [To_file (Circuit.name circuit)]. 
* default is an empty database  
* Default is [None] 
* [print] is [output ~output_mode:(To_channel stdout)] 
* Default is [None] 
* default is [To_file (Circuit.name circuit)]. 
* default is an empty database  
* Default is [None] 
open Base

module type Rtl = sig
  module Language : sig
    type t =
      | Verilog
      | Vhdl
    [@@deriving sexp_of]

    val file_extension : t -> string
    val legalize_identifier : t -> string -> string
  end

  module Output_mode : sig
    type t =
      | In_directory of string
* Write each circuit into a file in the given directory .   The file name consists 
           of the circuit name and the approriate file extension ( [ .v ] for Verilog and 
           [ .vhd ] for  ) .
          of the circuit name and the approriate file extension ([.v] for Verilog and
          [.vhd] for VHDL). *)
* Write all circuits into one buffer .
* Write all circuits to one out channel .
* Write all circuits into one file .
    [@@deriving sexp_of]
  end

* Control blackbox generation . [ None ] implies blackboxes are not used . [ Top ] means the 
       circuit will be turned into a blackbox . [ Instantiations ] means that the top level 
       circuit will be written as normal , but submodules will be written as blackboxes .
      circuit will be turned into a blackbox. [Instantiations] means that the top level
      circuit will be written as normal, but submodules will be written as blackboxes. *)
  module Blackbox : sig
    type t =
      | None
      | Top
      | Instantiations
    [@@deriving sexp_of]
  end

  module Uid_with_index : sig
    type t = Signal.Uid.t * int [@@deriving compare, sexp_of]

    include Comparator.S with type t := t
  end

  type signals_name_map_t = string Map.M(Uid_with_index).t

* Write circuit to [ Verilog ] or [ Vhdl ] .   Instantiations are ( recursively ) looked up in 
       [ database ] and if a circuit exists it is also written .   The [ output_mode ] specifies 
       how the circuit should be written - either to a single file ( or buffer , or channel ) 
       or to a directory with one file for each for the top level circuit and any 
       instantiated circuits contained in the database .
      [database] and if a circuit exists it is also written.  The [output_mode] specifies
      how the circuit should be written - either to a single file (or buffer, or channel)
      or to a directory with one file for each for the top level circuit and any
      instantiated circuits contained in the database. *)
  val output
    -> Language.t
    -> Circuit.t
    -> unit

  val print
    :  ?database:Circuit_database.t
    -> Language.t
    -> Circuit.t
    -> unit

  module Digest : sig
    type t [@@deriving sexp_of]

    val create
      :  ?database:Circuit_database.t
      -> ?blackbox:Blackbox.t
      -> Language.t
      -> Circuit.t
      -> t

    val to_string : t -> String.t
  end

  module Expert : sig
    val output_with_name_map
      -> Language.t
      -> Circuit.t
      -> signals_name_map_t
  end
end
