▁that ▁most ▁designs ▁that ▁will ▁fit ▁in ▁terms ▁of ▁lookup ▁tables ▁( L UT s ) ▁and ▁I / Os ▁can ▁be ▁rout ed . ▁This ▁is ▁determined ▁by ▁estimates ▁such ▁as ▁those ▁derived ▁from ▁R ent ' s ▁rule ▁or ▁by ▁experiments ▁with ▁existing ▁designs . ▁, ▁network - on - ch ip ▁architect ures ▁for ▁routing ▁and ▁inter connection ▁are ▁being ▁developed . ▁ ▁In ▁general , ▁a ▁logic ▁block ▁consists ▁of ▁a ▁few ▁logical ▁cells ▁( called ▁AL M , ▁LE , ▁slice ▁etc .). ▁A ▁typical ▁cell ▁consists ▁of ▁a ▁ 4 - input ▁L UT , ▁a ▁full ▁ad der ▁( FA ) ▁and ▁a ▁D - type ▁f lip - f lop , ▁as ▁shown ▁above . ▁The ▁L UT s ▁are ▁in ▁this ▁figure ▁split ▁into ▁two ▁ 3 - input ▁L UT s . ▁In ▁normal ▁mode ▁those ▁are ▁combined ▁into ▁a ▁ 4 - input ▁L UT ▁through ▁the ▁left ▁multiple x er ▁( m ux ). ▁In ▁arithmetic ▁mode , ▁their ▁outputs ▁are ▁fed ▁to ▁the ▁ad der . ▁The ▁selection ▁of ▁mode ▁is ▁program med ▁into ▁the ▁middle ▁M U X . ▁The ▁output ▁can ▁be ▁either ▁synchron ous ▁or ▁asynchronous , ▁depending ▁on ▁the ▁programming ▁of ▁the ▁m ux ▁to ▁the ▁right , ▁in ▁the ▁figure ▁example . ▁In ▁practice , ▁entire ▁or ▁parts ▁of ▁the ▁ad der ▁are ▁stored ▁as ▁functions ▁into ▁the ▁L UT s ▁in ▁order ▁to ▁save ▁space . ▁ ▁Hard ▁blocks ▁ ▁Modern ▁F P GA