es , ▁it ▁becomes ▁a ▁challenge ▁to ▁verify ▁correct ▁timing ▁of ▁valid ▁data ▁within ▁setup ▁time ▁and ▁hold ▁time . ▁ ▁F loor ▁planning ▁enables ▁resource ▁allocation ▁within ▁F PG As ▁to ▁meet ▁these ▁time ▁constraints . ▁F PG As ▁can ▁be ▁used ▁to ▁implement ▁any ▁logical ▁function ▁that ▁an ▁AS IC ▁can ▁perform . ▁The ▁ability ▁to ▁update ▁the ▁functionality ▁after ▁sh ipping , ▁partial ▁re - configuration ▁of ▁a ▁portion ▁of ▁the ▁design ▁and ▁the ▁low ▁non - rec urr ing ▁engineering ▁costs ▁relative ▁to ▁an ▁AS IC ▁design ▁( not with standing ▁the ▁generally ▁higher ▁unit ▁cost ), ▁offer ▁advantages ▁for ▁many ▁applications . ▁ ▁Some ▁F PG As ▁have ▁analog ▁features ▁in ▁addition ▁to ▁digital ▁functions . ▁The ▁most ▁common ▁analog ▁feature ▁is ▁a ▁program m able ▁sle w ▁rate ▁on ▁each ▁output ▁pin , ▁allowing ▁the ▁engineer ▁to ▁set ▁low ▁rates ▁on ▁light ly ▁loaded ▁p ins ▁that ▁would ▁otherwise ▁ring ▁or ▁couple ▁un accept ably , ▁and ▁to ▁set ▁higher ▁rates ▁on ▁heavily ▁loaded ▁p ins ▁on ▁high - speed ▁channels ▁that ▁would ▁otherwise ▁run ▁too ▁slowly . ▁Also ▁common ▁are ▁quart z - c ry stal ▁oscill ators , ▁on - ch ip ▁resistance - cap ac it ance ▁oscill ators , ▁and ▁phase - locked ▁loops ▁with ▁embedded ▁voltage - control led ▁oscill ators ▁used ▁for ▁clock ▁generation ▁and ▁management ▁and ▁for ▁high - speed ▁serial izer - des er ial izer ▁( SER DE S ) ▁transmit ▁clock s ▁and ▁receiver ▁clock ▁recovery .