. ▁This ▁reference ▁frame ▁results ▁in ▁an ▁instant aneous ▁E IB ▁band width ▁figure ▁of ▁ 3 8 4   GB / s ▁and ▁an ▁arbitr ation - limited ▁band width ▁figure ▁of ▁ 2 5 6   GB / s . ▁ ▁All ▁things ▁considered ▁the ▁the or etic ▁ 2 0 4 . 8   GB / s ▁number ▁most ▁often ▁c ited ▁is ▁the ▁best ▁one ▁to ▁bear ▁in ▁mind . ▁The ▁IBM ▁Systems ▁Performance ▁group ▁has ▁demonstrated ▁S PU - cent ric ▁data ▁flows ▁ach ieving ▁ 1 9 7   GB / s ▁on ▁a ▁Cell ▁processor ▁running ▁at ▁ 3 . 2   G Hz ▁so ▁this ▁number ▁is ▁a ▁fair ▁reflection ▁on ▁practice ▁as ▁well . ▁ ▁Memory ▁and ▁I / O ▁controllers ▁Cell ▁contains ▁a ▁dual ▁channel ▁R amb us ▁X IO ▁macro ▁which ▁interfaces ▁to ▁R amb us ▁X DR ▁memory . ▁The ▁memory ▁interface ▁controller ▁( M IC ) ▁is ▁separate ▁from ▁the ▁X IO ▁macro ▁and ▁is ▁designed ▁by ▁IBM . ▁The ▁X IO - X DR ▁link ▁runs ▁at ▁ 3 . 2   G bit / s ▁per ▁pin . ▁Two ▁ 3 2 - bit ▁channels ▁can ▁provide ▁a ▁theoretical ▁maximum ▁of ▁ 2 5 . 6   GB / s . ▁ ▁The ▁I / O ▁interface , ▁also ▁a ▁R amb us ▁design , ▁is ▁known ▁as ▁F lex IO . ▁The ▁F lex IO ▁interface ▁is ▁organized ▁into ▁ 1 2 ▁lan es , ▁each ▁l