▁interrupt ▁controller ), ▁and ▁a ▁ 1 6 - bit ▁data ▁word ▁to ▁identify ▁it . ▁The ▁interrupt ▁number ▁is ▁added ▁to ▁the ▁data ▁word ▁to ▁identify ▁the ▁interrupt . ▁Some ▁platforms ▁such ▁as ▁Windows ▁do ▁not ▁use ▁all ▁ 3 2 ▁interrupt s ▁but ▁only ▁use ▁up ▁to ▁ 1 6 ▁interrupt s . ▁ ▁M SI - X ▁ ▁M SI - X ▁( first ▁defined ▁in ▁P CI ▁ 3 . 0 ) ▁perm its ▁a ▁device ▁to ▁allocate ▁up ▁to ▁ 2 0 4 8 ▁interrupt s . ▁The ▁single ▁address ▁used ▁by ▁original ▁M SI ▁was ▁found ▁to ▁be ▁restrict ive ▁for ▁some ▁architect ures . ▁In ▁particular , ▁it ▁made ▁it ▁difficult ▁to ▁target ▁individual ▁interrupt s ▁to ▁different ▁process ors , ▁which ▁is ▁helpful ▁in ▁some ▁high - speed ▁networking ▁applications . ▁M SI - X ▁allows ▁a ▁larger ▁number ▁of ▁interrupt s ▁and ▁gives ▁each ▁one ▁a ▁separate ▁target ▁address ▁and ▁data ▁word . ▁Dev ices ▁with ▁M SI - X ▁do ▁not ▁necessarily ▁support ▁ 2 0 4 8 ▁interrupt s . ▁ ▁Optional ▁features ▁in ▁M SI ▁( 6 4 - bit ▁address ing ▁and ▁interrupt ▁mask ing ) ▁are ▁also ▁mand atory ▁with ▁M SI - X . ▁ ▁x 8 6 ▁systems ▁ ▁On ▁Intel ▁systems , ▁the ▁L API C ▁must ▁be ▁enabled ▁for ▁the ▁P CI ▁( and ▁P CI ▁Express ) ▁M SI / MS I - X ▁to ▁work , ▁even ▁on ▁un ip ro cess or