▁the ▁CPU ▁Si S ▁created ▁a ▁multimedia ▁ch ips et ▁for ▁the ▁X box ▁ 3 6 0 . ▁ ▁South bridge ▁ch ips ▁ ▁Pa ired ▁with ▁later ▁Si S ▁ch ips ets , ▁such ▁as ▁the ▁ 6 6 1 G X / 7 6 1 G X , ▁which ▁adopt ▁a ▁standard ▁two - ch ip ▁ch ips et ▁design ▁( inst ead ▁of ▁single - ch ip , ▁like ▁the ▁older ▁Si S ▁ 6 3 0 / 7 3 0 ▁series ▁ch ips ets ). ▁Si S ▁south brid ges ▁handle ▁IDE , ▁L AN ▁( with ▁MAC ▁chip ), ▁audio ▁( with ▁CO DE C ▁chip ), ▁and ▁other ▁I / O ▁connect ivity . ▁Si S ' ▁propriet ary ▁Mu TI OL ▁inter connect ▁connect s ▁the ▁south bridge ▁chip ▁to ▁the ▁north bridge , ▁which ▁contains ▁the ▁RAM ▁controller ▁( for ▁ch ips ets ▁target ed ▁at ▁Intel ▁platforms ) ▁and ▁interfaces ▁with ▁the ▁CPU . ▁ ▁Graphics ▁ch ips ets ▁ ▁Si S ▁ 6 2 0 1 ▁ ▁Si S ▁ 6 2 0 2 ▁ ▁Si S ▁ 6 2 0 5 ▁ ▁Si S ▁ 6 2 1 5 ▁ ▁Si S ▁ 6 2 2 5 ▁ ▁Si S ▁ 6 3 0 6 ▁ ▁Si S ▁ 6 3 2 6 ▁ ▁Si S ▁ 3 0 0 ▁ ▁Si S ▁ 3 0 1 ▁ ▁Si S ▁ 3 0 5 ▁ ▁Si S ▁ 3 1 5