▁formats . ▁System ▁memory ▁addresses ▁for ▁both ▁the ▁P PE ▁and ▁S PE ▁are ▁expressed ▁as ▁ 6 4 - bit ▁values ▁for ▁a ▁the or etic ▁address ▁range ▁of ▁ 2 6 4 ▁bytes ▁( 1 6 ▁ex aby tes ▁or ▁ 1 6 , 7 7 7 , 2 1 6 ▁ter aby tes ). ▁In ▁practice , ▁not ▁all ▁of ▁these ▁bits ▁are ▁implemented ▁in ▁hardware . ▁Local ▁store ▁addresses ▁internal ▁to ▁the ▁S PU ▁( Syn erg istic ▁Process or ▁Unit ) ▁processor ▁are ▁expressed ▁as ▁a ▁ 3 2 - bit ▁word . ▁In ▁documentation ▁rel ating ▁to ▁Cell ▁a ▁word ▁is ▁always ▁taken ▁to ▁mean ▁ 3 2 ▁bits , ▁a ▁double word ▁means ▁ 6 4 ▁bits , ▁and ▁a ▁quad word ▁means ▁ 1 2 8 ▁bits . ▁ ▁Power X Cell ▁ 8 i ▁In ▁ 2 0 0 8 , ▁IBM ▁announced ▁a ▁re vised ▁variant ▁of ▁the ▁Cell ▁called ▁the ▁Power X Cell ▁ 8 i , ▁which ▁is ▁available ▁in ▁Q S 2 2 ▁Bla de ▁Ser vers ▁from ▁IBM . ▁The ▁Power X Cell ▁is ▁manufact ured ▁on ▁a ▁ 6 5   nm ▁process , ▁and ▁adds ▁support ▁for ▁up ▁to ▁ 3 2   GB ▁of ▁sl otted ▁DDR 2 ▁memory , ▁as ▁well ▁as ▁dram atically ▁impro ving ▁double - prec ision ▁floating - point ▁performance ▁on ▁the ▁S PE s ▁from ▁a ▁peak ▁of ▁about ▁ 1 2 . 8   G F LO PS ▁to