▁Element ▁Inter connect ▁Bus ▁( E IB ) ▁The ▁E IB ▁is ▁a ▁communication ▁bus ▁internal ▁to ▁the ▁Cell ▁processor ▁which ▁connect s ▁the ▁various ▁on - ch ip ▁system ▁elements : ▁the ▁P PE ▁processor , ▁the ▁memory ▁controller ▁( M IC ), ▁the ▁eight ▁S PE ▁cop ro cess ors , ▁and ▁two ▁off - ch ip ▁I / O ▁interfaces , ▁for ▁a ▁total ▁of ▁ 1 2 ▁participants ▁in ▁the ▁PS 3 ▁( the ▁number ▁of ▁S PU ▁can ▁vary ▁in ▁industrial ▁applications ). ▁The ▁E IB ▁also ▁includes ▁an ▁arbitr ation ▁unit ▁which ▁functions ▁as ▁a ▁set ▁of ▁traffic ▁lights . ▁In ▁some ▁documents ▁IBM ▁refers ▁to ▁E IB ▁participants ▁as ▁' un its '. ▁ ▁The ▁E IB ▁is ▁presently ▁implemented ▁as ▁a ▁circular ▁ring ▁consisting ▁of ▁four ▁ 1 6 ▁bytes ▁wide ▁un id irection al ▁channels ▁which ▁counter - rotate ▁in ▁pairs . ▁When ▁traffic ▁patterns ▁permit , ▁each ▁channel ▁can ▁convey ▁up ▁to ▁three ▁transactions ▁concurrent ly . ▁As ▁the ▁E IB ▁runs ▁at ▁half ▁the ▁system ▁clock ▁rate ▁the ▁effective ▁channel ▁rate ▁is ▁ 1 6 ▁bytes ▁every ▁two ▁system ▁clock s . ▁At ▁maximum ▁conc urrency , ▁with ▁three ▁active ▁transactions ▁on ▁each ▁of ▁the ▁four ▁rings , ▁the ▁peak ▁instant aneous ▁E IB ▁band width ▁is ▁ 9 6 ▁bytes ▁per ▁clock ▁( 1 2 ▁concurrent ▁transactions ▁* ▁ 1 6 ▁bytes ▁wide ▁/ ▁ 2 ▁system ▁clock s ▁per ▁transfer ). ▁While ▁this ▁figure ▁is ▁often ▁quoted ▁in ▁IBM ▁literature