; ▁or ▁eight ▁single ▁precision ▁operations ▁per ▁clock ▁cycle ▁with ▁a ▁vector ▁f used - multip ly - add ▁instruction , ▁which ▁transl ates ▁to ▁ 2 5 . 6   G F LO PS ▁at ▁ 3 . 2   G Hz . ▁ ▁X en on ▁in ▁X box ▁ 3 6 0 ▁The ▁P PE ▁was ▁designed ▁specifically ▁for ▁the ▁Cell ▁processor ▁but ▁during ▁development , ▁Microsoft ▁approached ▁IBM ▁wanting ▁a ▁high ▁performance ▁processor ▁core ▁for ▁its ▁X box ▁ 3 6 0 . ▁IBM ▁comp lied ▁and ▁made ▁the ▁tri - core ▁X en on ▁processor , ▁based ▁on ▁a ▁slightly ▁modified ▁version ▁of ▁the ▁P PE ▁with ▁added ▁VM X 1 2 8 ▁extensions . ▁ ▁Syn erg istic ▁Process ing ▁Element s ▁( S PE ) ▁Each ▁S PE ▁is ▁a ▁dual ▁issue ▁in ▁order ▁processor ▁composed ▁of ▁a ▁" Syn erg istic ▁Process ing ▁Unit ", ▁S PU , ▁and ▁a ▁" Memory ▁Flow ▁Controller ", ▁M FC ▁( D MA , ▁MM U , ▁and ▁bus ▁interface ). ▁S PE s ▁don ' t ▁have ▁any ▁branch ▁prediction ▁hardware ▁( h ence ▁there ▁is ▁a ▁heavy ▁bur den ▁on ▁the ▁compiler ). ▁Each ▁S PE ▁has ▁ 6 ▁execution ▁units ▁divided ▁among ▁odd ▁and ▁even ▁pip elines ▁on ▁each ▁S PE ▁: ▁The ▁S PU ▁runs ▁a ▁spe cially ▁developed ▁instruction ▁set ▁( IS A ) ▁with ▁ 1 2 8 - bit ▁SI MD ▁organization ▁for ▁single ▁and ▁double ▁precision ▁instructions . ▁With ▁the