▁could ▁race ▁with ▁a ▁posted ▁write ▁to ▁memory . ▁That ▁is , ▁the ▁P CI ▁device ▁would ▁write ▁data ▁to ▁memory ▁and ▁then ▁send ▁an ▁interrupt ▁to ▁indicate ▁the ▁D MA ▁write ▁was ▁complete . ▁However , ▁a ▁P CI ▁bridge ▁or ▁memory ▁controller ▁might ▁buffer ▁the ▁write ▁in ▁order ▁to ▁not ▁inter f ere ▁with ▁some ▁other ▁memory ▁use . ▁The ▁interrupt ▁could ▁arrive ▁before ▁the ▁D MA ▁write ▁was ▁complete , ▁and ▁the ▁processor ▁could ▁read ▁st ale ▁data ▁from ▁memory . ▁To ▁prevent ▁this ▁race , ▁interrupt ▁handlers ▁were ▁required ▁to ▁read ▁from ▁the ▁device ▁to ▁ensure ▁that ▁the ▁D MA ▁write ▁had ▁finished . ▁This ▁read ▁had ▁a ▁moder ate ▁performance ▁penalty . ▁An ▁M SI ▁write ▁cannot ▁pass ▁a ▁D MA ▁write , ▁so ▁the ▁race ▁is ▁elimin ated . ▁ ▁M SI ▁types ▁ ▁P CI ▁defines ▁two ▁optional ▁extensions ▁to ▁support ▁Message ▁Sign alled ▁Inter rupt s , ▁M SI ▁and ▁M SI - X . ▁ ▁While ▁P CI ▁Express ▁is ▁compatible ▁with ▁legacy ▁interrupt s ▁on ▁the ▁software ▁level , ▁it ▁requires ▁M SI ▁or ▁M SI - X . ▁ ▁M SI ▁ ▁M SI ▁( first ▁defined ▁in ▁P CI ▁ 2 . 2 ) ▁perm its ▁a ▁device ▁to ▁allocate ▁ 1 , ▁ 2 , ▁ 4 , ▁ 8 , ▁ 1 6 ▁or ▁ 3 2 ▁interrupt s . ▁The ▁device ▁is ▁program med ▁with ▁an ▁address ▁to ▁write ▁to ▁( gener ally ▁a ▁control ▁register ▁in ▁an