ches ▁to ▁simulate ▁the ▁system ▁and ▁observe ▁results . ▁Then , ▁after ▁the ▁synth esis ▁engine ▁has ▁mapped ▁the ▁design ▁to ▁a ▁net list , ▁the ▁net list ▁is ▁translated ▁to ▁a ▁gate - level ▁description ▁where ▁simulation ▁is ▁repeated ▁to ▁confirm ▁the ▁synth esis ▁proceeded ▁without ▁errors . ▁Finally ▁the ▁design ▁is ▁laid ▁out ▁in ▁the ▁F P GA ▁at ▁which ▁point ▁propag ation ▁del ays ▁can ▁be ▁added ▁and ▁the ▁simulation ▁run ▁again ▁with ▁these ▁values ▁back - annot ated ▁onto ▁the ▁net list . ▁ ▁More ▁recently , ▁Open CL ▁( Open ▁Comput ing ▁Language ) ▁is ▁being ▁used ▁by ▁program mers ▁to ▁take ▁advantage ▁of ▁the ▁performance ▁and ▁power ▁effic ien cies ▁that ▁F PG As ▁provide . ▁Open CL ▁allows ▁program mers ▁to ▁develop ▁code ▁in ▁the ▁C ▁programming ▁language ▁and ▁target ▁F P GA ▁functions ▁as ▁Open CL ▁k ern els ▁using ▁Open CL ▁construct s . ▁For ▁further ▁information , ▁see ▁high - level ▁synth esis ▁and ▁C ▁to ▁HD L . ▁ ▁Basic ▁process ▁technology ▁types ▁ ▁S RAM ▁– ▁based ▁on ▁static ▁memory ▁technology . ▁In - system ▁program m able ▁and ▁re - program m able . ▁Re qu ires ▁external ▁boot ▁devices . ▁C M OS . ▁Currently ▁in ▁use . ▁Not ably , ▁flash ▁memory ▁or ▁E EP ROM ▁devices ▁may ▁often ▁load ▁contents ▁into ▁internal ▁S RAM ▁that ▁controls ▁routing ▁and ▁logic . ▁ ▁F use ▁– ▁One - time ▁program m able . ▁B ip olar . ▁Ob sole