▁restrict ive ▁structure ▁consisting ▁of ▁one ▁or ▁more ▁program m able ▁sum - of - products ▁logic ▁arrays ▁feed ing ▁a ▁relatively ▁small ▁number ▁of ▁clock ed ▁registers . ▁As ▁a ▁result , ▁C PL D s ▁are ▁less ▁flexible , ▁but ▁have ▁the ▁advantage ▁of ▁more ▁predict able ▁timing ▁del ays ▁and ▁ ▁F P GA ▁architect ures , ▁on ▁the ▁other ▁hand , ▁are ▁domin ated ▁by ▁inter connect . ▁This ▁makes ▁them ▁far ▁more ▁flexible ▁( in ▁terms ▁of ▁the ▁range ▁of ▁designs ▁that ▁are ▁practical ▁for ▁implementation ▁on ▁them ) ▁but ▁also ▁far ▁more ▁complex ▁to ▁design ▁for , ▁or ▁at ▁least ▁requiring ▁more ▁complex ▁electronic ▁design ▁autom ation ▁( ED A ) ▁software . ▁ ▁In ▁practice , ▁the ▁distinction ▁between ▁F PG As ▁and ▁C PL D s ▁is ▁often ▁one ▁of ▁size ▁as ▁F PG As ▁are ▁usually ▁much ▁larger ▁in ▁terms ▁of ▁resources ▁than ▁C PL D s . ▁Typ ically ▁only ▁F PG As ▁contain ▁more ▁complex ▁embedded ▁functions ▁such ▁as ▁add ers , ▁multip liers , ▁memory , ▁and ▁serial izer / des er ial izers . ▁Another ▁common ▁distinction ▁is ▁that ▁C PL D s ▁contain ▁embedded ▁flash ▁memory ▁to ▁store ▁their ▁configuration ▁while ▁F PG As ▁usually ▁require ▁external ▁non - vol atile ▁memory ▁( but ▁not ▁always ). ▁ ▁When ▁a ▁design ▁requires ▁simple ▁instant - on ▁( logic ▁is ▁already ▁configured ▁at ▁power - up ) ▁C PL D s ▁are ▁generally ▁preferred . ▁For ▁most ▁other ▁applications ▁F