". ▁This ▁number ▁reflect s ▁the ▁peak ▁instant aneous ▁E IB ▁band width ▁scale d ▁by ▁processor ▁frequency . ▁ ▁However , ▁other ▁technical ▁restrictions ▁are ▁involved ▁in ▁the ▁arbitr ation ▁mechanism ▁for ▁packets ▁accepted ▁onto ▁the ▁bus . ▁The ▁IBM ▁Systems ▁Performance ▁group ▁explained : ▁ ▁This ▁quote ▁apparently ▁represents ▁the ▁full ▁extent ▁of ▁IBM ' s ▁public ▁dis closure ▁of ▁this ▁mechanism ▁and ▁its ▁impact . ▁The ▁E IB ▁arbitr ation ▁unit , ▁the ▁s no op ing ▁mechanism , ▁and ▁interrupt ▁generation ▁on ▁segment ▁or ▁page ▁translation ▁fault s ▁are ▁not ▁well ▁described ▁in ▁the ▁documentation ▁set ▁as ▁yet ▁made ▁public ▁by ▁IBM . ▁ ▁In ▁practice ▁effective ▁E IB ▁band width ▁can ▁also ▁be ▁limited ▁by ▁the ▁ring ▁participants ▁involved . ▁While ▁each ▁of ▁the ▁nine ▁processing ▁cores ▁can ▁sust ain ▁ 2 5 . 6   GB / s ▁read ▁and ▁write ▁concurrent ly , ▁the ▁memory ▁interface ▁controller ▁( M IC ) ▁is ▁tied ▁to ▁a ▁pair ▁of ▁X DR ▁memory ▁channels ▁perm itting ▁a ▁maximum ▁flow ▁of ▁ 2 5 . 6   GB / s ▁for ▁reads ▁and ▁writes ▁combined ▁and ▁the ▁two ▁IO ▁controllers ▁are ▁documented ▁as ▁supporting ▁a ▁peak ▁combined ▁input ▁speed ▁of ▁ 2 5 . 6   GB / s ▁and ▁a ▁peak ▁combined ▁output ▁speed ▁of ▁ 3 5   GB / s . ▁ ▁To ▁add ▁further ▁to ▁the ▁confusion , ▁some ▁older ▁publications ▁c ite ▁E IB ▁band width ▁assuming ▁a ▁ 4   G Hz ▁system ▁clock