▁prime ▁them ▁before ▁they ▁can ▁do ▁any ▁useful ▁work . ▁As ▁most ▁of ▁the ▁" hor se power " ▁of ▁the ▁system ▁comes ▁from ▁the ▁syn erg istic ▁processing ▁elements , ▁the ▁use ▁of ▁D MA ▁as ▁a ▁method ▁of ▁data ▁transfer ▁and ▁the ▁limited ▁local ▁memory ▁foot print ▁of ▁each ▁S PE ▁pose ▁a ▁major ▁challenge ▁to ▁software ▁developers ▁who ▁wish ▁to ▁make ▁the ▁most ▁of ▁this ▁horse power , ▁demand ing ▁careful ▁hand - t uning ▁of ▁programs ▁to ▁extract ▁maximal ▁performance ▁from ▁this ▁CPU . ▁ ▁The ▁P PE ▁and ▁bus ▁architecture ▁includes ▁various ▁modes ▁of ▁operation ▁giving ▁different ▁levels ▁of ▁memory ▁protection , ▁allowing ▁areas ▁of ▁memory ▁to ▁be ▁protected ▁from ▁access ▁by ▁specific ▁processes ▁running ▁on ▁the ▁S PE s ▁or ▁the ▁P PE . ▁ ▁Both ▁the ▁P PE ▁and ▁S PE ▁are ▁R IS C ▁architect ures ▁with ▁a ▁fixed - width ▁ 3 2 - bit ▁instruction ▁format . ▁The ▁P PE ▁contains ▁a ▁ 6 4 - bit ▁general ▁purpose ▁register ▁set ▁( G PR ), ▁a ▁ 6 4 - bit ▁floating ▁point ▁register ▁set ▁( F PR ), ▁and ▁a ▁ 1 2 8 - bit ▁Alt ive c ▁register ▁set . ▁The ▁S PE ▁contains ▁ 1 2 8 - bit ▁registers ▁only . ▁These ▁can ▁be ▁used ▁for ▁scalar ▁data ▁types ▁r anging ▁from ▁ 8 - bits ▁to ▁ 6 4 - bits ▁in ▁size ▁or ▁for ▁SI MD ▁comput ations ▁on ▁a ▁variety ▁of ▁integer ▁and ▁floating ▁point