, ▁so ▁High - level ▁ver ification ▁today ▁has ▁two ▁important ▁areas ▁under ▁development ▁ ▁to ▁validate ▁H LS ▁is ▁correct ▁in ▁the ▁translation ▁process , ▁i . e . ▁to ▁validate ▁the ▁design ▁before ▁and ▁after ▁H LS ▁are ▁equivalent , ▁typically ▁through ▁formal ▁methods ▁ ▁to ▁verify ▁a ▁design ▁in ▁A NS I ▁C / C ++ / System C ▁code ▁is ▁conform ing ▁to ▁a ▁specification , ▁typically ▁through ▁logic ▁simulation . ▁ ▁Term in ology ▁ ▁History ▁ ▁Product ▁areas ▁▁ ▁F ormal ▁Solution : ▁Ver ify ▁high ▁level ▁models ▁against ▁R TL ▁designs ▁ ▁Sim ulation ▁Solution : ▁Int ellig ent ▁stim ulus ▁generation , ▁code ▁and ▁functional ▁coverage , ▁temporal ▁assertion ▁check er ▁ ▁See ▁also ▁▁ ▁Acc ell era ▁ ▁Electron ic ▁system - level ▁( ES L ) ▁ ▁F ormal ▁ver ification ▁ ▁Property ▁Spec ification ▁Language ▁( PS L ) ▁ ▁System C ▁ ▁System Ver ilog ▁ ▁Trans action - level ▁model ing ▁( TL M ) ▁ ▁References ▁▁▁▁ ▁Acc ell era ▁PS L ▁v 1 . 1 ▁L R M , ▁Acc ell era ▁ ▁" Native ▁System C ▁Assert ion ▁for ▁O CP ▁property ▁checking " ▁ ▁www . n asc ug . org ▁ ▁" Check ing ▁for ▁T LM 2 . 0 ▁Comp liance , ▁Why ▁bother ?" ▁ ▁www . n asc ug . org ▁ ▁External ▁links ▁▁ ▁Acc ell era ▁( former ly ▁OS CI ; ▁Open ▁System C ▁In iti ative ) ▁