▁high ▁abstra ction ▁level , ▁i . e ., ▁it ▁is ▁the ▁task ▁to ▁verify ▁a ▁model ▁that ▁represents ▁hardware ▁above ▁register - trans fer ▁level ▁( RT L ) ▁abstract ▁level . ▁For ▁high - level ▁synth esis ▁( H LS ▁or ▁C ▁synth esis ), ▁H L V ▁is ▁to ▁H LS ▁as ▁functional ▁ver ification ▁is ▁to ▁logic ▁synth esis . ▁ ▁Electron ic ▁digital ▁hardware ▁design ▁has ▁evol ved ▁from ▁low ▁level ▁abstra ction ▁at ▁gate ▁level ▁to ▁register ▁transfer ▁level ▁( RT L ), ▁the ▁abstra ction ▁level ▁above ▁R TL ▁is ▁commonly ▁called ▁high - level , ▁E SL , ▁or ▁behavior al / algorithm ic ▁level . ▁ ▁In ▁high - level ▁synth esis , ▁behavior al / algorithm ic ▁designs ▁in ▁A NS I ▁C / C ++ / System C ▁code ▁is ▁synth es ized ▁to ▁R TL , ▁which ▁is ▁then ▁synth es ized ▁into ▁gate ▁level ▁through ▁logic ▁synth esis . ▁Function al ▁ver ification ▁is ▁the ▁task ▁to ▁make ▁sure ▁a ▁design ▁at ▁R TL ▁or ▁gate ▁level ▁con forms ▁to ▁a ▁specification . ▁As ▁logic ▁synth esis ▁m atures , ▁most ▁functional ▁ver ification ▁is ▁done ▁at ▁the ▁higher ▁abstra ction , ▁i . e . ▁at ▁R TL ▁level , ▁the ▁correct ness ▁of ▁logic ▁synth esis ▁tool ▁in ▁the ▁transl ating ▁process ▁from ▁R TL ▁description ▁to ▁gate ▁net list ▁is ▁of ▁less ▁concern ▁today . ▁ ▁High - level ▁synth esis ▁is ▁still ▁an ▁emer ging ▁technology