▁Level ▁ 2 ▁cache . ▁The ▁size ▁of ▁a ▁cache ▁line ▁is ▁ 1 2 8 ▁bytes . ▁Additionally , ▁IBM ▁has ▁included ▁an ▁Al ti Vec ( VM X ) ▁unit ▁which ▁is ▁fully ▁pip el ined ▁for ▁single ▁precision ▁floating ▁point ▁( Alt ive c ▁ 1 ▁does ▁not ▁support ▁double ▁precision ▁floating - point ▁vectors .), ▁ 3 2 - bit ▁F ixed ▁Point ▁Unit ▁( FX U ) ▁with ▁ 6 4 - bit ▁register ▁file ▁per ▁thread , ▁Load ▁and ▁Store ▁Unit ▁( LS U ), ▁ 6 4 - bit ▁Flo ating - Point ▁Unit ▁( F PU ) ▁, ▁Branch ▁Unit ▁( BR U ) ▁and ▁Branch ▁Exec ution ▁Unit ( B X U ). ▁P PE ▁consists ▁of ▁three ▁main ▁units : ▁Inst ruction ▁Unit ▁( I U ), ▁Exec ution ▁Unit ▁( X U ) ▁and ▁vector / scal ar ▁execution ▁unit ▁( V SU ). ▁IU ▁contains ▁L 1 ▁instruction ▁cache , ▁branch ▁prediction ▁hardware , ▁instruction ▁buff ers ▁and ▁dependency ▁checking ▁login . ▁X U ▁contains ▁integer ▁execution ▁units ▁( FX U ) ▁and ▁load - store ▁unit ▁( LS U ). ▁VS U ▁contains ▁all ▁of ▁the ▁execution ▁resources ▁for ▁F PU ▁and ▁VM X . ▁Each ▁P PE ▁can ▁complete ▁two ▁double ▁precision ▁operations ▁per ▁clock ▁cycle ▁using ▁a ▁scalar ▁f used - multip ly - add ▁instruction , ▁which ▁transl ates ▁to ▁ 6 . 4   G F LO PS ▁at ▁ 3 . 2   G Hz