▁Cell ▁chip ▁can ▁have ▁a ▁number ▁of ▁different ▁configurations , ▁the ▁basic ▁configuration ▁is ▁a ▁multi - core ▁chip ▁composed ▁of ▁one ▁" Power ▁Process or ▁Element " ▁(" P PE ") ▁( s ometimes ▁called ▁" Process ing ▁Element ", ▁or ▁" PE "), ▁and ▁multiple ▁" Syn erg istic ▁Process ing ▁Element s " ▁(" S PE "). ▁The ▁P PE ▁and ▁S PE s ▁are ▁linked ▁together ▁by ▁an ▁internal ▁high ▁speed ▁bus ▁dub bed ▁" Element ▁Inter connect ▁Bus " ▁(" E IB "). ▁ ▁Power ▁Process or ▁Element ▁( P PE ) ▁ ▁The ▁P PE ▁is ▁the ▁Power PC ▁based , ▁dual - issue ▁in - order ▁two - way ▁simultane ous - mult ith read ed ▁core ▁with ▁a ▁ 2 3 - stage ▁pipeline ▁acting ▁as ▁the ▁controller ▁for ▁the ▁eight ▁S PE s , ▁which ▁handle ▁most ▁of ▁the ▁computational ▁work load . ▁P PE ▁has ▁limited ▁out ▁of ▁order ▁execution ▁capabilities ; ▁it ▁can ▁perform ▁loads ▁out ▁of ▁order ▁and ▁has ▁delayed ▁execution ▁pip elines . ▁The ▁P PE ▁will ▁work ▁with ▁conventional ▁operating ▁systems ▁due ▁to ▁its ▁similarity ▁to ▁other ▁ 6 4 - bit ▁Power PC ▁process ors , ▁while ▁the ▁S PE s ▁are ▁designed ▁for ▁vector ized ▁floating ▁point ▁code ▁execution . ▁The ▁P PE ▁contains ▁a ▁ 6 4 ▁Ki B ▁level ▁ 1 ▁cache ▁( 3 2 ▁Ki B ▁instruction ▁and ▁a ▁ 3 2 ▁Ki B ▁data ) ▁and ▁a ▁ 5 1 2 ▁Ki B