▁current ▁generation ▁of ▁the ▁Cell , ▁each ▁S PE ▁contains ▁a ▁ 2 5 6   K i B ▁embedded ▁S RAM ▁for ▁instruction ▁and ▁data , ▁called ▁" Local ▁Storage " ▁( not ▁to ▁be ▁mistaken ▁for ▁" Local ▁Memory " ▁in ▁Sony ' s ▁documents ▁that ▁refer ▁to ▁the ▁V RAM ) ▁which ▁is ▁visible ▁to ▁the ▁P PE ▁and ▁can ▁be ▁addressed ▁directly ▁by ▁software . ▁Each ▁S PE ▁can ▁support ▁up ▁to ▁ 4 ▁Gi B ▁of ▁local ▁store ▁memory . ▁The ▁local ▁store ▁does ▁not ▁operate ▁like ▁a ▁conventional ▁CPU ▁cache ▁since ▁it ▁is ▁neither ▁transparent ▁to ▁software ▁nor ▁does ▁it ▁contain ▁hardware ▁structures ▁that ▁predict ▁which ▁data ▁to ▁load . ▁The ▁S PE s ▁contain ▁a ▁ 1 2 8 - bit , ▁ 1 2 8 - entry ▁register ▁file ▁and ▁measures ▁ 1 4 . 5   mm 2 ▁on ▁a ▁ 9 0   nm ▁process . ▁An ▁S PE ▁can ▁operate ▁on ▁six teen ▁ 8 - bit ▁integers , ▁eight ▁ 1 6 - bit ▁integers , ▁four ▁ 3 2 - bit ▁integers , ▁or ▁four ▁single - prec ision ▁floating - point ▁numbers ▁in ▁a ▁single ▁clock ▁cycle , ▁as ▁well ▁as ▁a ▁memory ▁operation . ▁Note ▁that ▁the ▁S PU ▁cannot ▁directly ▁access ▁system ▁memory ; ▁the ▁ 6 4 - bit ▁virtual ▁memory ▁addresses ▁formed ▁by ▁the ▁S PU ▁must ▁be ▁passed ▁from ▁the ▁S PU ▁to ▁the ▁S PE ▁memory ▁flow ▁controller ▁( M FC ) ▁to