▁was ▁unique ▁from ▁future ▁modules ▁in ▁many ▁ways . ▁ ▁It ▁had ▁a ▁unique ▁" edge ▁card " ▁conne ctor . ▁ ▁This ▁was ▁a ▁" cost ▁sav ings " ▁over ▁the ▁E EC ▁I / II / II ▁" pin ▁and ▁socket " ▁connect ors ▁but ▁was ▁quickly ▁abandoned ▁due ▁to ▁reli ability ▁concerns . ▁ ▁It ▁util ized ▁a ▁ 4 0 ▁pin ▁" DI P " ▁IC ▁package ▁which ▁limited ▁the ▁number ▁of ▁inputs / output s . ▁ ▁It ▁also ▁used ▁only ▁ 1 ▁memory ▁ch ips ▁which ▁contained ▁ 8 K ▁bytes ▁of ▁M ROM ▁instructions / data ▁and ▁ 1 2 8 ▁addition ▁bytes ▁of ▁RAM . ▁ ▁All ▁future ▁E EC - IV ▁modules ▁used ▁a ▁unique ▁" through ▁hole " ▁IC ▁package ▁with ▁st agger ed ▁p ins ▁on ▁all ▁ 4 ▁edges . ▁ ▁This ▁allowed ▁all ▁available ▁I / O ▁to ▁be ▁util ized . ▁ ▁Memory ▁quickly ▁grew ▁to ▁ 2 ▁- ▁ 8 k / 1 2 8 ▁M ROM / RAM ▁ch ips ▁and ▁then ▁a ▁separate ▁ 3 2 K ▁M ROM ▁and ▁ 1 K ▁RAM . ▁ ▁Bus ▁loading ▁limited ▁the ▁design ▁to ▁ 2 ▁external ▁memory ▁devices . ▁ ▁Intel ▁only ▁manufact ured ▁ch ips , ▁not ▁modules . ▁ ▁Event ually ▁there ▁was ▁a ▁unique ▁MB US ▁U VE P ROM ▁designed ▁and ▁manufact ured ▁by ▁Intel . ▁ ▁Motor ola ▁and ▁Ford ▁Electron ics ▁Division ▁( prec ursor ▁to ▁V iste on ) ▁designed