▁sch ematic ▁design . ▁The ▁HD L ▁form ▁is ▁more ▁su ited ▁to ▁work ▁with ▁large ▁structures ▁because ▁it ' s ▁possible ▁to ▁specify ▁high - level ▁functional ▁behavior ▁rather ▁than ▁drawing ▁every ▁piece ▁by ▁hand . ▁However , ▁sch ematic ▁entry ▁can ▁allow ▁for ▁easier ▁visual ization ▁of ▁a ▁design ▁and ▁its ▁component ▁modules . ▁ ▁Using ▁an ▁electronic ▁design ▁autom ation ▁tool , ▁a ▁technology - ma pped ▁net list ▁is ▁generated . ▁The ▁net list ▁can ▁then ▁be ▁fit ▁to ▁the ▁actual ▁F P GA ▁architecture ▁using ▁a ▁process ▁called ▁place - and - route , ▁usually ▁performed ▁by ▁the ▁F P GA ▁company ' s ▁propriet ary ▁place - and - route ▁software . ▁The ▁user ▁will ▁validate ▁the ▁map , ▁place ▁and ▁route ▁results ▁via ▁timing ▁analysis , ▁simulation , ▁and ▁other ▁ver ification ▁and ▁validation ▁method ologies . ▁Once ▁the ▁design ▁and ▁validation ▁process ▁is ▁complete , ▁the ▁binary ▁file ▁generated , ▁typically ▁using ▁the ▁F P GA ▁vendor ' s ▁propriet ary ▁software , ▁is ▁used ▁to ▁( re -) configure ▁the ▁F P GA . ▁This ▁file ▁is ▁transferred ▁to ▁the ▁F P GA / CP LD ▁via ▁a ▁serial ▁interface ▁( J TAG ) ▁or ▁to ▁an ▁external ▁memory ▁device ▁like ▁an ▁E EP ROM . ▁ ▁The ▁most ▁common ▁HD L s ▁are ▁V H DL ▁and ▁Ver ilog ▁as ▁well ▁as ▁extensions ▁such ▁as ▁System Ver ilog . ▁However , ▁in ▁an ▁attempt ▁to ▁reduce ▁the ▁complexity ▁of ▁design ing ▁in ▁HD