▁the ▁state ▁of ▁each ▁activity ▁which ▁may ▁be ▁changed ▁by ▁gate ▁and ▁interrupt ▁trans itions . ▁ ▁Prote ction ▁Mechan isms ▁▁ ▁The ▁ 2 2 0 0 ▁Series ▁protection ▁architecture ▁uses ▁three ▁pieces ▁of ▁activity ▁state ▁that ▁are ▁reflected ▁in ▁the ▁hardware ▁state . ▁ ▁They ▁are ▁Process or ▁Priv ile ge ▁( PP ), ▁Ring , ▁and ▁Domain . ▁ ▁Process or ▁Priv ile ge ▁controls ▁the ▁ability ▁to ▁execute ▁privile ged ▁instructions ▁and ▁access ▁protected ▁registers ▁and ▁other ▁state . ▁ ▁P P = 0 ▁is ▁used ▁by ▁the ▁Exec ▁and ▁gives ▁full ▁access ▁to ▁all ▁instructions ▁and ▁privile ged ▁state . ▁ ▁Exec ▁activities ▁and ▁user ▁activities ▁that ▁have ▁used ▁a ▁gate ▁to ▁access ▁an ▁Exec ▁API ▁run ▁at ▁P P = 0 . ▁ ▁P P = 1 ▁restrict s ▁most ▁privile ged ▁instructions ▁but ▁does ▁allow ▁reading ▁of ▁the ▁day ▁clock s ▁and ▁reading ▁the ▁contents ▁of ▁some ▁of ▁the ▁privile ged ▁registers . ▁ ▁None ▁of ▁the ▁privile ged ▁registers ▁contain ▁any ▁truly ▁sensitive ▁information , ▁but ▁allowing ▁general ▁read ▁access ▁could ▁easily ▁lead ▁to ▁und et ected ▁errors ▁in ▁user ▁programs . ▁ ▁Basically ▁at ▁P P = 1 , ▁instructions ▁that ▁can ▁change ▁the ▁address ing ▁environment , ▁change ▁the ▁clock s , ▁change ▁instrument ation ▁state , ▁or ▁perform ▁I / O ▁are ▁all ▁restricted . ▁ ▁P P = 1 ▁is ▁rarely ▁used . ▁ ▁P P = 2 ▁is ▁the ▁normal ▁user ▁mode ▁and ▁is ▁state ▁in ▁which ▁all ▁other ▁code