▁interrupt s ▁with ▁a ▁lower ▁priority ▁to ▁be ▁put ▁into ▁a ▁pending ▁state , ▁until ▁the ▁CPU ▁releases ▁control ▁back ▁to ▁the ▁interrupt ▁controller . ▁If ▁a ▁signal ▁comes ▁in ▁at ▁a ▁higher ▁priority , ▁then ▁the ▁current ▁interrupt ▁will ▁be ▁put ▁into ▁a ▁pending ▁state ; ▁the ▁CPU ▁sets ▁the ▁interrupt ▁mask ▁to ▁the ▁priority ▁and ▁places ▁any ▁interrupt s ▁with ▁a ▁lower ▁priority ▁into ▁a ▁pending ▁state ▁until ▁the ▁CPU ▁finish es ▁handling ▁the ▁new , ▁higher ▁priority ▁interrupt . ▁ ▁Windows ▁maps ▁not ▁only ▁hardware ▁interrupt ▁levels ▁to ▁its ▁internal ▁interrupt ▁table ▁but ▁also ▁maps ▁software ▁interrupt s . ▁The ▁ma ppings ▁in ▁this ▁table ▁are ▁called ▁Inter rupt ▁Request ▁Level s , ▁or ▁IR QL s , ▁and ▁a ▁separate ▁IR QL ▁is ▁kept ▁for ▁each ▁processor ▁in ▁a ▁multip ro cess or ▁system . ▁The ▁IR QL ▁values ▁are ▁specific ▁to ▁the ▁x 8 6 , ▁I A 6 4 ▁and ▁A MD 6 4 ▁processor ▁architect ures ▁that ▁Windows ▁can ▁run ▁on , ▁though ▁theoret ically ▁they ▁can ▁support ▁other ▁CPU s ▁that ▁use ▁a ▁similar ▁interrupt ▁scheme ▁( such ▁as ▁the ▁DE C ▁Al pha ▁and ▁M IP S , ▁which ▁were ▁supported ▁briefly ▁on ▁early ▁versions ▁of ▁Windows ). ▁What ▁this ▁essentially ▁means ▁is ▁that ▁A PC s ▁( as ynchronous ▁procedure ▁calls ), ▁user ▁threads ▁and ▁kernel ▁mode ▁operations ▁can ▁be ▁interrupted , ▁and ▁the ▁system ▁must ▁run ▁them ▁at ▁an ▁IR QL ▁lower ▁than ▁the ▁thread ▁sch eduler ▁( or ▁" dispatch er