m ▁process ▁( sh r unk ▁to ▁ 6 5 ▁n m ▁in ▁ 2 0 0 8 ▁and ▁to ▁ 4 0 ▁n m ▁in ▁ 2 0 1 0 ), ▁ 3 0 0 + ▁million ▁trans ist ors ▁ ▁Based ▁on ▁N V 4 7 ▁( N vidia ▁Ge For ce ▁ 7 8 0 0 ▁architecture ) ▁ ▁Little ▁End ian ▁ ▁Multi - way ▁program m able ▁parallel ▁floating - point ▁sh ader ▁pip elines , ▁independent ▁pixel / ver tex ▁sh ader ▁architecture ▁▁ 2 4 ▁parallel ▁pixel - sh ader ▁AL U ▁pip elines ▁clock ed ▁at ▁ 5 5 0 ▁M Hz ▁▁ 5 ▁AL U ▁operations ▁per ▁pipeline , ▁per ▁cycle ▁( 2 ▁vector 4 , ▁ 2 ▁scalar / du al / co - issue ▁and ▁fog ▁AL U , ▁ 1 ▁texture ▁AL U ) ▁▁ 2 7 ▁floating - point ▁operations ▁per ▁pipeline , ▁per ▁cycle ▁ ▁Flo ating ▁Point ▁Oper ations ▁per ▁a ▁second ▁: ▁ 1 9 2 ▁G F LO P s ▁▁▁ 8 ▁parallel ▁vertex ▁pip elines ▁▁ 2 ▁AL U ▁operations ▁per ▁pipeline , ▁per ▁cycle ▁( 1 ▁vector 4 ▁and ▁ 1 ▁scalar , ▁dual ▁issue ) ▁▁ 1 0 ▁F LO PS ▁per ▁pipeline , ▁per ▁cycle ▁▁ 2 4 ▁texture ▁filtering ▁units ▁( TF ) ▁and ▁ 8 ▁vertex ▁texture ▁address ing ▁units ▁( TA ) ▁▁ 2 4 ▁filtered ▁samples ▁per ▁clock ▁ ▁Max imum ▁Tex el ▁fill rate : ▁ 1