▁composed ▁of ▁ 4 ▁stages , ▁number ed ▁ 1 ▁to ▁ 4 , ▁and ▁an ▁additional ▁leading ▁R source ▁and ▁trailing ▁R load . ▁ ▁Each ▁stage ▁i ▁has ▁a ▁designed ▁input - to - output ▁voltage ▁at ten u ation ▁ratio i ▁as : ▁ ▁For ▁log arith mic ▁scale d ▁at ten u ators , ▁it ▁is ▁common ▁practice ▁to ▁express ▁their ▁at ten u ation ▁in ▁de ci b els : ▁ ▁for ▁ ▁and ▁▁ ▁This ▁reve als ▁a ▁basic ▁property : ▁▁ ▁To ▁show ▁that ▁this ▁ ▁satisfies ▁the ▁overall ▁intention : ▁ ▁for ▁ ▁and ▁▁ ▁The ▁different ▁stages ▁ 1 ▁.. ▁N ▁should ▁function ▁independently ▁of ▁each ▁other , ▁as ▁to ▁obtain ▁ 2 N ▁different ▁states ▁with ▁a ▁compos able ▁behavior . ▁To ▁achieve ▁an ▁at ten u ation ▁of ▁each ▁stage ▁that ▁is ▁independent ▁of ▁its ▁surrounding ▁stages , ▁either ▁one ▁of ▁two ▁design ▁choices ▁is ▁to ▁be ▁implemented : ▁constant ▁input ▁resistance ▁or ▁constant ▁output ▁resistance . ▁ ▁Constant ▁input ▁resistance ▁ ▁The ▁input ▁resistance ▁of ▁any ▁stage ▁shall ▁be ▁independent ▁of ▁its ▁on / off ▁switch ▁position , ▁and ▁must ▁be ▁equal ▁to ▁R load . ▁ ▁This ▁leads ▁to : ▁ ▁With ▁these ▁equations , ▁all ▁res istor ▁values ▁of ▁the ▁circuit ▁diagram ▁follow ▁easily ▁after ▁choosing ▁values ▁for ▁N , ▁ ▁and ▁R load . ▁( The ▁value ▁of ▁R source ▁does ▁not ▁influence ▁the ▁log arith mic ▁behavior ) ▁ ▁Constant ▁output ▁resistance ▁ ▁The ▁output ▁resistance ▁of