) ▁or ▁fall ▁through ▁to ▁the ▁next ▁instruction ( T SS ). ▁ ▁On ▁a ▁T S ▁interrupt ▁the ▁OS ▁takes ▁one ▁of ▁several ▁actions ▁depending ▁on ▁the ▁instruction ▁sequence ▁and ▁activity ▁priority . ▁ ▁Real ▁time ▁and ▁Exec ▁activities ▁simply ▁get ▁control ▁back ▁to ▁allow ▁re try ▁unless ▁there ▁is ▁an ▁even ▁higher - p riority ▁activity ▁waiting . ▁ ▁The ▁pres umption ▁is ▁that ▁the ▁lock ▁is ▁set ▁on ▁another ▁processor ▁and ▁will ▁soon ▁be ▁cleared . ▁ ▁If ▁it ▁is ▁a ▁user ▁activity ▁not ▁running ▁at ▁real ▁time ▁priority , ▁it ▁may ▁have ▁its ▁priority ▁tempor arily ▁reduced ▁and ▁be ▁placed ▁back ▁in ▁the ▁dispatch ing ▁que ues . ▁ ▁Alternatively , ▁the ▁code ▁sequence ▁may ▁indicate ▁that ▁Test ▁& ▁Set ▁Que uing ▁is ▁being ▁used . ▁ ▁In ▁this ▁case , ▁the ▁OS ▁places ▁the ▁activity ▁in ▁a ▁wait ▁state ▁and ▁ch ains ▁it ▁to ▁the ▁end ▁of ▁the ▁list ▁of ▁activities ▁waiting ▁for ▁that ▁particular ▁lock . ▁ ▁Activ ities ▁clear ing ▁such ▁a ▁lock ▁check ▁to ▁see ▁if ▁any ▁are ▁waiting ▁and ▁if ▁so ▁notify ▁the ▁OS ▁to ▁allow ▁one ▁of ▁more ▁to ▁try ▁again . ▁ ▁Test ▁& ▁Set ▁Que uing ▁is ▁typically ▁used ▁for ▁synchron ization ▁within ▁sub system s ▁such ▁as ▁the ▁database ▁manager ▁where ▁activities ▁from ▁many ▁programs ▁may ▁be ▁executing . ▁ ▁The ▁result ▁of ▁these ▁mechan isms ▁is ▁very ▁efficient , ▁low ▁overhead , ▁synchron ization ▁among ▁activities . ▁ ▁The ▁que uing ▁architecture ▁is ▁another ▁interesting ▁special ▁case . ▁