▁not ▁over la pping ▁with ▁AV X , ▁parts ▁that ▁over la pped ▁with ▁AV X ▁were ▁removed ▁or ▁moved ▁to ▁separate ▁standards ▁such ▁as ▁ ▁F MA 4 ▁( f lo ating - point ▁vector ▁multiply – acc um ulate ) ▁ ▁and ▁ ▁CV T 1 6 ▁( H alf - prec ision ▁floating - point ▁conversion ▁implemented ▁as ▁F 1 6 C ▁by ▁Intel ). ▁ ▁All ▁S SE 5 ▁instructions ▁that ▁were ▁equivalent ▁or ▁similar ▁to ▁instructions ▁in ▁the ▁AV X ▁and ▁F MA 4 ▁instruction ▁sets ▁announced ▁by ▁Intel ▁have ▁been ▁changed ▁to ▁use ▁the ▁coding ▁proposed ▁by ▁Intel . ▁Integer ▁instructions ▁without ▁equival ents ▁in ▁AV X ▁were ▁class ified ▁as ▁the ▁X OP ▁extension . ▁The ▁X OP ▁instructions ▁have ▁an ▁op code ▁byte ▁ 8 F ▁( hex ade c imal ), ▁but ▁otherwise ▁almost ▁identical ▁coding ▁scheme ▁as ▁AV X ▁with ▁the ▁ 3 - byte ▁V EX ▁prefix . ▁ ▁Comment ators ▁have ▁seen ▁this ▁as ▁evidence ▁that ▁Intel ▁has ▁not ▁allowed ▁A MD ▁to ▁use ▁any ▁part ▁of ▁the ▁large ▁V EX ▁coding ▁space . ▁A MD ▁has ▁been ▁forced ▁to ▁use ▁different ▁codes ▁in ▁order ▁to ▁avoid ▁using ▁any ▁code ▁combination ▁that ▁Intel ▁might ▁possibly ▁be ▁using ▁in ▁its ▁development ▁pipeline ▁for ▁something ▁else . ▁The ▁X OP ▁coding ▁scheme ▁is ▁as ▁close ▁to ▁the ▁V EX ▁scheme ▁as ▁techn ically ▁possible ▁without ▁risk ing ▁that ▁the ▁A MD ▁codes ▁overlap ▁with ▁future ▁Intel ▁codes . ▁This ▁inference ▁is ▁spec ulative