▁memory , ▁main ▁X DR ▁memory ▁can ▁be ▁accessed ▁by ▁R S X ▁too , ▁which ▁is ▁limited ▁to ▁either : ▁▁ 0 MB ▁- ▁ 2 5 6 MB ▁( 0 x 0 0 0 0 0 0 0 0 ▁- ▁ 0 x 0 FFFF FF F ) ▁- or - ▁▁ 0 MB ▁- ▁ 5 1 2 MB ▁( 0 x 0 0 0 0 0 0 0 0 ▁- ▁ 0 x 1 FFFF FF F ) ▁ ▁Speed , ▁band width ▁and ▁laten cy ▁ ▁System ▁band width ▁( the oret ical ▁maximum ): ▁Cell ▁to / from ▁ 2 5 6 MB ▁X DR ▁: ▁ 2 5 . 6 ▁GB / s ▁Cell ▁to ▁R S X ▁( IO I FO ): ▁ 2 0 GB / s ▁( p ract ical ▁: ▁ 1 5 . 8 GB / s ▁@ ▁packets ize ▁ 1 2 8 B ) ▁Cell ▁from ▁R S X ▁( IO I FI ) ▁: ▁ 1 5 GB / s ▁( p ract ical ▁: ▁ 1 1 . 9 GB / s ▁@ ▁packets ize ▁ 1 2 8 B ) ▁R S X ▁to / from ▁ 2 5 6 MB ▁G DD R 3 ▁: ▁ 2 0 . 8 GB / s ▁(@ ▁ 6 5 0   M Hz ) ▁ ▁Because ▁of ▁the ▁a for ement ioned ▁layout ▁of ▁the ▁communication ▁path ▁between ▁the ▁different ▁ch ips , ▁and ▁the ▁laten cy