▁and ▁band width ▁differences ▁between ▁the ▁various ▁components , ▁there ▁are ▁different ▁access ▁spe eds ▁depending ▁on ▁the ▁direction ▁of ▁the ▁access ▁in ▁relation ▁to ▁the ▁source ▁and ▁destination . ▁The ▁following ▁is ▁a ▁chart ▁showing ▁the ▁speed ▁of ▁reads ▁and ▁writes ▁to ▁the ▁G DD R 3 ▁and ▁X DR ▁memory ▁from ▁the ▁view point ▁of ▁the ▁Cell ▁and ▁R S X . ▁Note ▁that ▁these ▁are ▁measured ▁spe eds ▁( r ather ▁than ▁calculated ▁spe eds ) ▁and ▁they ▁should ▁be ▁worse ▁if ▁R S X ▁and ▁G DD R 3 ▁access ▁are ▁involved ▁because ▁these ▁figures ▁were ▁measured ▁when ▁the ▁R S X ▁was ▁clock ed ▁at ▁ 5 5 0 M h z ▁and ▁the ▁G DD R 3 ▁memory ▁was ▁clock ed ▁at ▁ 7 0 0 M h z . ▁The ▁sh ipped ▁PS 3 ▁has ▁the ▁R S X ▁clock ed ▁in ▁at ▁ 5 0 0 M h z ▁( front ▁and ▁back ▁end , ▁although ▁the ▁pixel ▁sh aders ▁run ▁separately ▁inside ▁at ▁ 5 5 0 M h z ). ▁In ▁addition , ▁the ▁G DD R 3 ▁memory ▁was ▁also ▁clock ed ▁lower ▁at ▁ 6 5 0 M h z . ▁ ▁Speed ▁table ▁▁ ▁Because ▁of ▁the ▁very ▁slow ▁Cell ▁Read ▁speed ▁from ▁the ▁ 2 5 6 MB ▁G DD R 3 ▁memory , ▁it ▁is ▁more ▁efficient ▁for ▁the ▁Cell ▁to ▁work ▁in ▁X DR ▁and ▁then ▁have ▁the ▁R S X ▁pull ▁data ▁from ▁X DR ▁and