Open Verification Library

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages (HDLs). OVL is currently maintained by Accellera.
Applications.
OVL works by placing modules or components checking specific properties of the circuit alongside regular modules or components. Those special modules are called checkers and are tied to circuit signals via ports. Some aspects of the checker functionality can be modified by adjusting checker parameters. Typical properties verified by OVL checkers include:
Depending on the selected parameters, OVL checkers can work as assertion, assumption or coverage point checkers.
Main source of OVL popularity is the fact that it allows introducing high-level verification concepts to the existing or new designs without requiring new language, e.g. a designer having access to Verilog tools does not need a new language to start using property checking with OVL. 
Supported Languages.
While first versions of OVL supported Verilog and VHDL, most recent versions support (in alphabetical order):
Depending on the demand, support for two more languages may be added: "PSL - VHDL" flavour and "SystemC".