Blackbox

In Unix computing, Blackbox is a free and open-source stacking window manager for the X Window System.
Blackbox has specific design goals, and some functionality is provided only through other applications. One example is the bbkeys hotkey application.
Blackbox is written in C++ and contains completely original code. It was created by Bradley T. Hughes and is available under the MIT License. Blackbox has compliance with the Extended Window Manager Hints specification.
The original author seems to have ceased updating the repository with the exception of a minor fix of compilation problems in 2015, leaving the last original version at 0.70.1. However an actively maintained fork by Brian Bidulock has been picked up by several Linux distributions in its place, and it is featured in pkgsrc. Despite that, some other Linux distributions still use the original source code, as does FreeBSD.
Features.
Features of the Blackbox window manager include:
Related projects.
There are a number of other window manager forks of Blackbox:
Windows shell replacements.
Although they do not share the same codebase, these projects are also inspired by Blackbox.


MC68340

The MC68340 is a high-performance 32-bit microprocessor with direct memory access (DMA).
Family.
The MC68340 is one of a series of components in Motorola's M68300 Family. Other members of the family
include the MC68302, MC68330, MC68331, MC68332, and MC68F333.


Time Stamp Counter

The Time Stamp Counter (TSC) is a 64-bit register present on all x86 processors since the Pentium. It counts the number of CPU cycles since its reset. The instruction codice_1 returns the TSC in EDX:EAX. In x86-64 mode, codice_1 also clears the higher 32 bits of RAX and lower 32 bits of RDX, so that OR'ing them together provides the 64 bit value. Its opcode is codice_3. Pentium competitors such as the Cyrix 6x86 did not always have a TSC and may consider codice_1 an illegal instruction. Cyrix included a Time Stamp Counter in their MII.
Use.
The Time Stamp Counter was once an excellent high-resolution, low-overhead way for a program to get CPU timing information. With the advent of multi-core/hyper-threaded CPUs, systems with multiple CPUs, and hibernating operating systems, the TSC cannot be relied upon to provide accurate results — unless great care is taken to correct the possible flaws: rate of tick and whether all cores (processors) have identical values in their time-keeping registers. There is no promise that the timestamp counters of multiple CPUs on a single motherboard will be synchronized. Therefore, a program can get reliable results only by limiting itself to run on one specific CPU. Even then, the CPU speed may change because of power-saving measures taken by the OS or BIOS, or the system may be hibernated and later resumed, resetting the TSC. In those latter cases, to stay relevant, the program must re-calibrate the counter periodically.
Relying on the TSC also reduces portability, as other processors may not have a similar feature. Recent Intel processors include a constant rate TSC (identified by the kern.timecounter.invariant_tsc sysctl on FreeBSD or by the "codice_5" flag in Linux's codice_6). With these processors, the TSC ticks at the processor's nominal frequency, regardless of the actual CPU clock frequency due to turbo or power saving states. Hence TSC ticks are counting the passage of time, not the number of CPU clock cycles elapsed.
On Windows platforms, Microsoft strongly discourages using the TSC for high-resolution timing for exactly these reasons, providing instead the Windows APIs codice_7 and codice_8. On POSIX systems, a program can get similar function by reading the value of codice_9 clock using the codice_10 function.
Starting with the Pentium Pro, Intel processors have practiced out-of-order execution, where instructions are not necessarily performed in the order they appear in the program. This can cause the processor to execute codice_1 earlier than a simple program expects, producing a misleading cycle count. The programmer can solve this problem by inserting a serializing instruction, such as CPUID, to force every preceding instruction to complete before allowing the program to continue. The codice_12 instruction is a variant of codice_1 that features partial serialization of the instruction stream, but should not be considered as serializing.
Implementation in various processors.
Intel processor families increment the time-stamp counter differently:
The specific processor configuration determines the behavior. Constant TSC behavior ensures that the duration of each clock tick is uniform and makes it possible to use of the TSC as a wall clock timer even if the processor core changes frequency. This is the architectural behavior for all later Intel processors.
AMD processors up to the K8 core always incremented the time-stamp counter every clock cycle. Thus, power management features were able to change the number of increments per second, and the values could get out of sync between different cores or processors in the same system. For Windows, AMD provides a utility to periodically synchronize the counters on multiple core CPUs.
Since the family 10h (Barcelona/Phenom), AMD chips feature a constant TSC, which can be driven either by the HyperTransport speed or the highest P state. A CPUID bit (codice_14) advertises this; Intel-CPUs also report their invariant TSC on that bit.
Operating system use.
An operating system may provide methods that both use and don't use the codice_1 instruction for time keeping, under administrator control. For example, on some versions of the Linux kernel, seccomp sandboxing mode disables codice_1. It can also be disabled using the codice_17 argument to the codice_18 system call.
Use in exploiting cache side-channel attacks.
The time stamp counter can be used to time instructions accurately which can be exploited in the Meltdown and Spectre security vulnerabilities. However if this is not available other counters or timers can be used, as is the case with the ARM processors vulnerable to this type of attack.
Other architectures.
Other processors also have registers which count CPU clock cycles, but with different names. For instance, on the AVR32, it is called the Performance Clock Counter (PCCNT) register. SPARC V9 provides the codice_19 register. PowerPC provides the 64-bit codice_20 register.
ARMv7 and ARMv8 architectures provide a generic counter which counts at a constant frequency. ARMv7 provides the Cycle Counter Register (CCNT instruction) to read and write the counter, but the instruction is privileged.


Turbo Touch 360

The Turbo Touch 360 is a series of aftermarket third-party controllers made by Triax for the Nintendo Entertainment System, Super Nintendo Entertainment System, and Sega Genesis (the latter version also being compatible with Atari and Commodore systems).
Whereas most controllers used a D-pad with mechanical switches, the Turbo Touch had an octagonal plate with eight capacitive touch sensors arranged in the cardinal directions; contrary to the "360" name, the controller only provided digital input along the cardinal directions. The idea was that the controller could be operated with less physical force, reducing thumb injuries and "numb thumb", thereby improving player comfort and health. The controller was endorsed by Dr. Robert Grossman, an orthopaedic surgeon specialising in sports injuries.
Other than the touchpad, the controllers have a standard set of features typical for controllers of the time, with turbo support.
Reception.
The controller was ranked the ninth worst video game controller by "IGN" editor Craig Harris.


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New Nintendo 2DS XL

The New Nintendo 2DS XL (branded as New Nintendo 2DS LL in Japan) is a handheld game console produced by Nintendo. It is the sixth and final system in the Nintendo 3DS family of handheld consoles, and was released in Australia and New Zealand on 15 June 2017, in Japan and South Korea on 13 July 2017, and in North America and Europe on 28 July 2017.
Serving as a companion to the Nintendo 2DS, the New Nintendo 2DS XL uses the same clamshell form factor of other 3DS models. It carries over hardware improvements from the New Nintendo 3DS (including its updated processor, additional controls, near-field communications support for Amiibo and support for additional titles leveraging its hardware improvements), but with no autostereoscopic 3D display, a thinner form factor, the microphone and camera moved to the hinge, and speakers moved to the lower half of the device.
The New 2DS XL received positive reviews, with critics noting that it combined traits of the 2DS and New Nintendo 3DS XL into a more ergonomic and aesthetically-pleasing device over the slate-shaped 2DS, but noting slight regressions in display and speaker quality.
As of 17 September 2020, New 2DS XL models have ended production worldwide, thereby ending production of the entire Nintendo 3DS family of systems.
History.
Nintendo has presented versions of the console in black with blue accents for the North American market, and white with orange-gold accents for the Japanese, South Korean and PAL region market, as well as a Japan-exclusive "Dragon Quest XI" limited edition. Later, the White + Orange variant came to North America, as well as Lavender + White, Black + Green (both Japan-exclusive) as well as Poké Ball and Pikachu variants to coincide with the launch of "Pokémon Ultra Sun" and "Ultra Moon" (the former also coming to that region).
In July 2018, a "Hylian Shield" variant was released as a GameStop exclusive in North America, bundled with a pre-installed copy of '. This came alongside an ' variant for Europe and Japan, and red/black "Mario Kart 7" and "Minecraft" Creeper styles exclusive to Japan.
A month later, in August, Nintendo announced a new version of the console in purple with silver accents, which would release in September 2018. Additionally, Nintendo confirmed that all future shipments of the Black + Blue, White + Orange and Purple + Silver models would come with a pre-installed copy of "Mario Kart 7".
On 17 September 2020, Nintendo officially discontinued the New 2DS XL, thereby ending production of all systems in the family. The 3DS was subsequently removed from Nintendo's homepage following this announcement.
Software and services.
The system software of the New Nintendo 2DS XL is otherwise identical to that of the New Nintendo 3DS, remaining compatible with all games released for the 3DS (in two-dimensional mode only), DSi (including games with 3DS enhancements), DS (excluding those requiring the Game Boy Advance cartridge slot), and New Nintendo 3DS (such as "Xenoblade Chronicles 3D" and "Fire Emblem Warriors"), and offering online features such as Nintendo Network for multiplayer and online gaming, Nintendo eShop for downloading and purchasing games, and SpotPass and StreetPass.
Reception.
IGN considered the New 2DS XL to be an improvement over the "ugly doorstop-like" 2DS, praising its incorporation of features from the New 3DS XL into a device with a thinner and more "comfortable" form factor. Other changes were noted, such as using flaps to protect the game and SD card slots (the latter also removing the need to use tools to access it), and better-feeling shoulder buttons than the New 3DS XL. Regressions were also noted, however, such as its screens having a "washed out" appearance and lacking contrast, the top screen having a mirror-like coat that diminished viewing angles, the speakers sounding "muffled", and the short length of the included stylus. The New 2DS XL was recommended for users who did not need 3D but still wanted to play the platform's exclusives.
"TechRadar" was similarly positive, but also noting that the hinge now protruded from the back of the device (thus making it look less streamlined when closed), its battery life was "underwhelming", and the timing of its launch was at odds with the release of Nintendo Switch.


Thread control block

Thread Control Block (TCB) is a data structure in the operating system kernel which contains thread-specific information needed to manage it. The TCB is "the manifestation of a thread in an operating system."
An example of information contained within a TCB is:
The Thread Control Block acts as a library of information about the threads in a system. Specific information is stored in the thread control block highlighting important information about each process.


GeForce 700 series

The GeForce 700 series (stylized as GEFORCE GTX 700 SERIES) is a series of graphics processing units developed by Nvidia. While mainly a refresh of the Kepler microarchitecture (GK-codenamed chips), some cards use Fermi (GF) and later cards use Maxwell (GM). GeForce 700 series cards were first released in 2013, starting with the release of the GeForce GTX Titan on February 19, 2013, followed by the GeForce GTX 780 on May 23, 2013. The first mobile GeForce 700 series chips were released in April 2013.
Overview.
GK110 was designed and marketed with computational performance in mind. It contains 7.1 billion transistors. This model also attempts to maximise energy efficiency through the execution of as many tasks as possible in parallel according to the capabilities of its streaming processors.
With GK110, increases in memory space and bandwidth for both the register file and the L2 cache over previous models, are seen. At the SMX level, GK110's register file space has increased to 256KB composed of 64K 32bit registers, as compared to Fermi's 32K 32bit registers totaling 128 KB. As for the L2 cache, GK110 L2 cache space increased by up to 1.5MB, 2x as big as GF110. Both the L2 cache and register file bandwidth have also doubled.
Performance in register-starved scenarios is also improved as there are more registers available to each thread. This goes in hand with an increase of total number of registers each thread can address, moving from 63 registers per thread to 255 registers per thread with GK110.
With GK110, Nvidia also reworked the GPU texture cache to be used for compute. With 48KB in size, in compute the texture cache becomes a read-only cache, specializing in unaligned memory access workloads. Furthermore, error detection capabilities have been added to make it safer for use with workloads that rely on ECC.
This series support DirectX 12 on Windows 10.
Dynamic Super Resolution (DSR) was added to Kepler GPUs with the latest Nvidia drivers.
Architecture.
The GeForce 700 Series contains features from both GK104 and GK110. Kepler based members of the 700 series add the following standard features to the GeForce family.
Derived from GK104 :
New Features from GK110 :
Compute focus SMX improvement.
With GK110, Nvidia opted to increase compute performance. The single biggest change from GK104 is that rather than 8 dedicated FP64 CUDA cores, GK110 has up to 64, giving it 8x the FP64 throughput of a GK104 SMX. The SMX also sees an increase in space for register file. Register file space has increased to 256KB compared to Fermi. The texture cache are also improved. With a 48KB space, the texture cache can become a read-only cache for compute workloads.
New shuffle Instructions.
At a low level, GK110 sees additional instructions and operations to further improve performance. New shuffle instructions allow for threads within a warp to share data without going back to memory, making the process much quicker than the previous load/share/store method. Atomic operations are also overhauled, speeding up the execution speed of atomic operations and adding some FP64 operations that were previously only available for FP32 data.
Hyper-Q.
Hyper-Q expands GK110 hardware work queues from 1 to 32. The significance of this being that having a single work queue meant that Fermi could be under occupied at times as there wasn't enough work in that queue to fill every SM. By having 32 work queues, GK110 can in many scenarios, achieve higher utilization by being able to put different task streams on what would otherwise be an idle SMX. The simple nature of Hyper-Q is further reinforced by the fact that it's easily map to MPI, a common message passing interface frequently used in HPC. As legacy MPI-based algorithms that were originally designed for multi-CPU systems that became bottlenecked by false dependencies now have a solution. By increasing the number of MPI jobs, it's possible to utilize Hyper-Q on these algorithms to improve the efficiency all without changing the code itself.
Microsoft DirectX support.
NVIDIA Kepler GPUs of the GeForce 700 series fully support DirectX 11.0.
NVIDIA supports the DX12 API on all the DX11-class GPUs it has shipped; these belong to the Fermi, Kepler and Maxwell architectural families.
Dynamic parallelism.
Dynamic Parallelism ability is for kernels to be able to dispatch other kernels. With Fermi, only the CPU could dispatch a kernel, which incurs a certain amount of overhead by having to communicate back to the CPU. By giving kernels the ability to dispatch their own child kernels, GK110 can both save time by not having to go back to the CPU, and in the process free up the CPU to work on other tasks.
Products.
GeForce 700 (7xx) series.
The GeForce 700 series for desktop architecture. Cheaper and lower performing products were expected to be released over time. Kepler supports 11.1 features with 11_0 feature level through the DirectX 11.1 API, however Nvidia did not enable four non-gaming features in Hardware in Kepler (for 11_1).
GeForce 700M (7xxM) series.
Some implementations may use different specifications.
Discontinued support.
Nvidia announced that after Release 390.x drivers, it will no longer release 32-bit drivers for 32-bit operating systems.
Nvidia announced that Kepler notebook GPUs will transition to legacy support from April 2019 onwards and be supported until April 2020. All notebook GPUs from the 7xxM family are affected by this change.
In Windows the last driver to fully support CUDA with 64-Bit Compute Capability 3.5 for Kepler in Windows 7 & Windows 8.1 64-bit is 388.71,
tested with latest CUDA-Z and GPU-Z, after that driver, the 64-Bit CUDA support becomes broken for GeForce 700 series GK110 with Kepler architecture.
The last driver where monitor type detection is working properly on Windows XP is 352.86.


Robert M. Graham

Robert M. Graham (1929 in Michigan, U.S. – January 2, 2020) was a cybersecurity researcher computer scientist and Professor Emeritus of Computer Science at the University of Massachusetts Amherst. He was born to a Scottish emigrant.
He received his undergraduate and graduate degrees from the University of Michigan. While working at the UofM's Computing Center he co-authored two compilers, GAT for the IBM 650 and MAD for the IBM 704/709/7090.
In 1963 he moved to MIT to participate in the development of Multics, one of the first virtual memory time-sharing computer operating systems. He had responsibility for protection, dynamic linking, and other key system kernel areas.
Later worked at University of California, Berkeley, City College of New York, and the University of Massachusetts Amherst. Officially retired in 1996, but continued to teach until the end of 2003.
In 1996 he was inducted as a Fellow of the Association for Computing Machinery.
He is the author of numerous books and professional articles.


DJ Delorie


Custom Robo V2

 is a sci-fi action role playing game developed by Noise and published by Nintendo. It was released for the Nintendo 64 in Japan on November 10, 2000. Later, on February 19, 2008, it was released for the Virtual Console in Japan. It is the second title of the "Custom Robo series", as well as the last of the series for the Nintendo 64. It is also the first title of the series to allow up to four players to play, instead of two players.
Gameplay.
The battle system in "Custom Robo V2" is very similar to the first game in the series, except it features tag-teaming, which was never used in later 3D "Custom Robo" titles except for "" for the Nintendo GameCube.
The gameplay of "Custom Robo V2" is divided into two main parts: the over world and Robo battles. During the over world, parts of the game play like any other RPG, meaning that the player can control a character in a free roaming world where other characters follow. The main object of the game is to finish its plot by collecting every Robo, battle part, and other items, while winning every battle that moves the character from one part of the storyline to the next.
In Custom Robo battles, the object is to reduce the opponent's hit points from 1000 to 0 by using different Custom Robos, guns, bombs, pods, and dash attacks. Battles begin with both robos being launched out of a Robocannon which is controlled with the control stick. There are six ways your robo can land once shot out of the Robocannon. Custom Robos are arranged in groups that are similar to their abilities. An endurance bar is located above the hit points. Once it runs out the robo gets "downed" which means that it stays fallen for a couple seconds. After it gets up, it goes into "rebirth", where it stays invincible for about 3 seconds.
Reception.
"Custom Robo V2" sold 62,558 copies during its first week of sale in Japan.


Cars Race-O-Rama

Cars Race-O-Rama is a racing video game based on the "Cars" franchise that was released on October 12, 2009. It is the sequel to "Cars Mater-National Championship", which was released on October 29, 2007.
Gameplay.
"Cars Race-O-Rama" is a racing adventure game in which the player controls "Cars" protagonist and Piston Cup racer Lightning McQueen. The game features five nonlinear open worlds, including Radiator Springs. In each area McQueen can participate in multiple race types, including circuit races, relay, and point-to-point. Some events allow the player to control other characters, such as the forklift Guido in events known as Guido Kart. During these events the player participates in combat racing similar to that found in the "Mario Kart" series.
Throughout the single-player campaign players will have the opportunity to visually upgrade McQueen. In his starting configuration the player can change McQueen's front bumper, hood, side skirts and spoiler. Additionally his wheels and paint livery can be changed via unlocks from the gameplay world collectables.
Development.
"Cars Race-O-Rama" debuted at E3 2009. The primary version was developed by Incinerator Studios, and this version was released on PlayStation 3, Wii, Xbox 360, and PlayStation 2. It was powered by Rainbow Studios' engine, which had been the technology behind the previous two "Cars" installments. The PSP and DS versions of the game were created by Tantalus Media in Melbourne and Brisbane, Australia. A toy line for the release was released in early 2009, as the name "Race O Rama" was used for the 3rd series of Mattel Die-Cast Disney Cars. This is the last Disney/Pixar video game published by THQ as well as the last game to be published by any other company except Disney Interactive Studios until 2017 when "" was published by Warner Bros. Interactive. It is also the final "Cars" game to be released on the PlayStation 2.
Reception.
"Cars Race-O-Rama" received mixed reviews, according to Metacritic.


IBM PS/55 Note

The IBM Personal System/55 Note (stylized as PS/55 note) is a series of notebooks manufactured by the IBM subsidiary IBM Japan as part of the IBM Personal System/55 series.
The international IBM PS/2 Note series was based on the PS/55 Note series.
History.
IBM started selling the PS/55 Note series in Japan in April 1991.
Western Digital has supplied video and logic chips for the PS/55 Note.
Models.
The prices for the PS/55 Note varies between $1,680 and $2,550.
Reception.
The PS/55 Note was a rapid succes in Japan.


VFAT


PlayStation Link Cable

The PlayStation Link Cable (SCPH-1040) is a peripheral cable for the PlayStation console. Utilizing the serial I/O port found on the back of most PlayStation models, it allows for two consoles to be connected in order to play compatible multiplayer games on separate consoles. It was released during the 1995 Christmas shopping season.
The cable is a 12-pin inline serial cable that plugs directly into the back of the PlayStation console and was a fully supported Sony accessory for the market life of the console. Because it was only designed for original PlayStation models, it's not compatible with the redesigned PS one, nor with succeeding PlayStation consoles such as the PlayStation 2.
The main advantage to using the cable was that a split-screen wouldn't be necessary for multiplayer, increasing each player's screen size and potentially increasing game performance (as only one view has to be rendered per console). However, the use of this cable requires two televisions, two PlayStations (with appropriate cables), and two copies of the game being played (with the exception of ', ' and "", which require only one copy as the games come with two discs). This expense was impractical for most consumers, and by the end of 1997 most retailers were no longer carrying the PlayStation Link Cable.


MSDOS.COM


SpeedStart


Intel DX4

IntelDX4 is a clock-tripled i486 microprocessor with 16-kB Level 1 cache. Intel named it DX4 (rather than "DX3") as a consequence of litigation with AMD over trademarks. The product was officially named IntelDX4, but OEMs continued using the i486 naming convention.
Intel produced IntelDX4s with two clock speed steppings: A 75-MHz version (3× 25 MHz multiplier), and a 100-MHz version (3× 33.3 MHz). Both chips were released in March 1994. A version of IntelDX4 featuring write-back cache was released in October 1994. The original write-through versions of the chip are marked with a laser-embossed “&E,” while the write-back-enabled versions are marked “&EW.” i486 OverDrive editions of IntelDX4 had locked multipliers, and therefore can only run at 3× the external clock speed. The 100-MHz model of the processor had an iCOMP rating of 435, while the 75-MHz processor had a rating of 319. IntelDX4 was an OEM-only product, but the DX4 Overdrive could be purchased at a retail store.
The IntelDX4 microprocessor is mostly pin-compatible with the 80486, but requires a lower 3.3-V supply. Normal 80486 and DX2 processors use a 5-V supply; plugging a DX4 into an unmodified socket will destroy the processor. Motherboards lacking support for the 3.3-V CPUs can sometimes make use of them using a voltage regulator (VRM) that fits between the socket and the CPU.


Hybrid kernel

A hybrid kernel is an operating system kernel architecture that attempts to combine aspects and benefits of microkernel and monolithic kernel architectures used in computer operating systems.
Overview.
The traditional kernel categories are monolithic kernels and microkernels (with nanokernels and exokernels seen as more extreme versions of microkernels). The "hybrid" category is controversial, due to the similarity of hybrid kernels and ordinary monolithic kernels; the term has been dismissed by Linus Torvalds as simple marketing.
The idea behind a hybrid kernel is to have a kernel structure similar to that of a microkernel, but to implement that structure in the manner of a monolithic kernel. In contrast to a microkernel, all (or nearly all) operating system services in a hybrid kernel are still in kernel space. There are none of the reliability benefits of having services in user space, as with a microkernel. However, just as with an ordinary monolithic kernel, there is none of the performance overhead for message passing and context switching between kernel and user mode that normally comes with a microkernel.
Examples.
NT kernel.
One prominent example of a hybrid kernel is the Microsoft Windows NT kernel that powers all operating systems in the Windows NT family, up to and including Windows 10 and Windows Server 2019, and powers Windows Phone 8, Windows Phone 8.1, and Xbox One.
Windows NT was the first Windows operating system based on a hybrid kernel. The hybrid kernel was designed as a modified microkernel, influenced by the Mach microkernel developed by Richard Rashid at Carnegie Mellon University, but without meeting all of the criteria of a pure microkernel. NT-based Windows is classified as a hybrid kernel (or a macrokernel) rather than a monolithic kernel because the emulation subsystems run in user-mode server processes, rather than in kernel mode as on a monolithic kernel, and further because of the large number of design goals which resemble design goals of Mach (in particular the separation of OS personalities from a general kernel design). Conversely, the reason NT is not a microkernel system is because most of the system components run in the same address space as the kernel, as would be the case with a monolithic design (in a traditional monolithic design, there would not be a microkernel per se, but the kernel would implement broadly similar functionality to NT's microkernel and kernel-mode subsystems).
The primary operating system personality on Windows is the Windows API, which is always present. The emulation subsystem which implements the Windows personality is called the Client/Server Runtime Subsystem (csrss.exe). On versions of NT prior to 4.0, this subsystem process also contained the window manager, graphics device interface and graphics device drivers. For performance reasons, however, in version 4.0 and later, these modules (which are often implemented in user mode even on monolithic systems, especially those designed without internal graphics support) run as a kernel-mode subsystem.
Applications that run on NT are written to one of the OS personalities (usually the Windows API), and not to the native NT API for which documentation is not publicly available (with the exception of routines used in device driver development). An OS personality is implemented via a set of user-mode DLLs (see Dynamic-link library), which are mapped into application processes' address spaces as required, together with an emulation subsystem server process (as described previously). Applications access system services by calling into the OS personality DLLs mapped into their address spaces, which in turn call into the NT run-time library (ntdll.dll), also mapped into the process address space. The NT run-time library services these requests by trapping into kernel mode to either call kernel-mode Executive routines or make Local Procedure Calls (LPCs) to the appropriate user-mode subsystem server processes, which in turn use the NT API to communicate with application processes, the kernel-mode subsystems and each other.
XNU kernel.
XNU is the kernel that Apple Inc. acquired and developed for use in the macOS, iOS, watchOS, and tvOS operating systems and released as free and open source software as part of the Darwin operating system. "XNU" is an acronym for "X is Not Unix".
Originally developed by NeXT for the NeXTSTEP operating system, XNU was a hybrid kernel combining version 2.5 of the Mach kernel with components from 4.3BSD and an object-oriented API for writing drivers called Driver Kit.
After Apple acquired NeXT, the Mach component was upgraded to OSFMK 7.3, which is a microkernel. Apple uses a heavily modified OSFMK 7.3 functioning as a hybrid kernel with parts of FreeBSD included. (OSFMK 7.3 includes applicable code from the University of Utah Mach 4 kernel and applicable code from the many Mach 3.0 variants that sprouted off from the original Carnegie Mellon University Mach 3.0 kernel.) The BSD components were upgraded with code from the FreeBSD project and the Driver Kit was replaced with a C++ API for writing drivers called I/O Kit.
Description.
Like some other modern kernels, XNU is a hybrid, containing features of both monolithic and microkernels, attempting to make the best use of both technologies, such as the message passing capability of microkernels enabling greater modularity and larger portions of the OS to benefit from protected memory, as well as retaining the speed of monolithic kernels for certain critical tasks.


Scoreloop

Scoreloop, a subsidiary of BlackBerry, was a cross-platform social gaming network for the operating systems including BlackBerry (Tablet OS and BlackBerry 10), Android, Bada, iOS and Windows Phone 7.
History.
The company, based in Munich, Germany, raised US$2.8 million to help create the service that they founded in 2008. Early Investors included Earlybird Venture Capital and Target Partners. In March 2010, Scoreloop gave developers that used its service the ability to monetize their apps using the company's services. The network was among the first to add support for Android apps.
During August 2010, Scoreloop revealed that its user base was growing by over 100,000 new users per day.
On June 7, 2011, Scoreloop was acquired by BlackBerry for US$71 million.
On July 8, 2014, BlackBerry announced that the Scoreloop service is to be discontinued starting December 1, 2014 and encouraged all developers to remove all Scoreloop features and integrations from their developed games.


Athlon 64

The Athlon 64 is an eighth-generation, AMD64-architecture microprocessor produced by AMD, released on September 23, 2003. It is the third processor to bear the name "Athlon", and the immediate successor to the Athlon XP. The second processor (after the Opteron) to implement the AMD64 architecture and the first 64-bit processor targeted at the average consumer, it was AMD's primary consumer microprocessor, and primarily competed with Intel's Pentium 4, especially the "Prescott" and "Cedar Mill" core revisions. It is AMD's first K8, eighth-generation processor core for desktop and mobile computers. Despite being natively 64-bit, the AMD64 architecture is backward-compatible with 32-bit x86 instructions. Athlon 64s have been produced for Socket 754, Socket 939, Socket 940 and Socket AM2. The line was succeeded by the dual-core Athlon 64 X2 and Athlon X2 lines.
Background.
The Athlon 64 was originally codenamed "ClawHammer" by AMD, and was referred to as such internally and in press releases. The first Athlon 64 FX was based on the first Opteron core, "SledgeHammer". Both cores, produced on a 130 nanometer process, were first introduced on September 23, 2003. The models first available were the FX-51, fitting Socket 940, and the 3200+, fitting Socket 754. Like the Opteron, on which it was based, the Athlon FX-51 required buffered RAM, increasing the final cost of an upgrade. The week of the Athlon 64's launch, Intel released the Pentium 4 Extreme Edition, a CPU designed to compete with the Athlon 64 FX. The Extreme Edition was widely considered a marketing ploy to draw publicity away from AMD, and was quickly nicknamed among some circles the "Emergency Edition". Despite a very strong demand for the chip, AMD experienced early manufacturing difficulties that made it difficult to deliver Athlon 64s in quantity. In the early months of the Athlon 64 lifespan, AMD could only produce 100,000 chips per month. However, it was very competitive in terms of performance to the Pentium 4, with magazine PC World calling it the "fastest yet". "Newcastle" was released soon after ClawHammer, with half the Level 2 cache.
Single-core Athlon 64.
All the 64-bit processors sold by AMD so far have their genesis in the "K8" or "Hammer" project. On June 1, 2004, AMD released new versions of both the ClawHammer and Newcastle core revisions for the newly introduced Socket 939, an altered Socket 940 without the need for buffered memory. Socket 939 offered two main improvements over Socket 754: the memory controller was altered with dual-channel architecture, doubling peak memory bandwidth, and the HyperTransport bus was increased in speed from 800 MHz to 1000 MHz. Socket 939 also was introduced in the FX series in the form of the FX-55. At the same time, AMD also began to ship the "Winchester" core, based on a 90 nanometer process.
Core revisions "Venice" and "San Diego" succeeded all previous revisions on April 15, 2005. Venice, the lower-end part, was produced for both Sockets 754 and 939, and included 512 KB of L2 cache. San Diego, the higher-end chip, was produced only for Socket 939 and doubled Venice's L2 cache to 1 MB. Both were produced on the 90 nm fabrication process. Both also included support for the SSE3 instruction set, a new feature that had been included in the rival Pentium 4 since the release of the Prescott core in February 2004. In addition, AMD overhauled the memory controller for this revision, resulting in performance improvements as well as support for newer DDR RAM.
Dual-core Athlon 64.
On April 21, 2005, less than a week after the release of Venice and San Diego, AMD announced its next addition to the Athlon 64 line, the Athlon 64 X2. Released on May 31, 2005, it also initially had two different core revisions available to the public, Manchester and Toledo, the only appreciable difference between them being the amount of L2 cache. Both were released only for Socket 939. The Athlon 64 X2 was received very well by reviewers and the general public, with a general consensus emerging that AMD's implementation of multi-core was superior to that of the competing Pentium D. Some felt initially that the X2 would cause market confusion with regard to price points since the new processor was targeted at the same "enthusiast," US$350 and above market already occupied by AMD's existing socket 939 Athlon 64s. AMD's official breakdown of the chips placed the Athlon X2 aimed at a segment they called the "prosumer", along with digital media fans. The Athlon 64 was targeted at the mainstream consumer, and the Athlon FX at gamers. The Sempron budget processor was targeted at value-conscious consumers. Following the launch of the Athlon 64 X2, AMD surpassed Intel in US retail sales for a period of time, although Intel retained overall market leadership because of its exclusive relationships with direct sellers such as Dell.
DDR2.
The Athlon 64 had been maligned by some critics for some time because of its lack of support for DDR2 SDRAM, an emerging technology that had been adopted much earlier by Intel. AMD's official position was that the CAS latency on DDR2 had not progressed to a point where it would be advantageous for the consumer to adopt it. AMD finally remedied this gap with the "Orleans" core revision, the first Athlon 64 to fit Socket AM2, released on May 23, 2006. "Windsor", an Athlon 64 X2 revision for Socket AM2, was released concurrently. Both Orleans and Windsor have either 512 KB or 1 MB of L2 cache per core. The Athlon 64 FX-62 was also released concurrently on the Socket AM2 platform. Socket AM2 also consumes less power than previous platforms, and supports AMD-V.
The memory controller used in all DDR2 SDRAM capable processors (Socket AM2), has extended column address range of 11 columns instead of conventional 10 columns, and the support of 16 KB page size, with at most 2048 individual entries supported. An OCZ unbuffered DDR2 kit, optimized for 64-bit operating systems, was released to exploit the functionality provided by the memory controller in socket AM2 processors, allowing the memory controller to stay longer on the same page, thus benefitting graphics intensive applications.
Moving to the subnotebook space.
The Athlon architecture was further extended with the release of Athlon Neo processors on January 9, 2009. Based on the same architecture as the other Athlon 64 variants, the new processor features a small package footprint targeting Ultra-portable notebook market.
Features.
There are four variants: "Athlon 64", "Athlon 64 FX", "Mobile Athlon 64" (later renamed "Turion 64") and the dual-core "Athlon 64 X2". Common among the Athlon 64 line are a variety of instruction sets including MMX, 3DNow!, SSE, SSE2, and SSE3. All Athlon 64s also support the NX bit, a security feature named "Enhanced Virus Protection" by AMD. And as implementations of the AMD64 architecture, all Athlon 64 variants are able to run 16 bit, 32 bit x86, and AMD64 code, through two different modes the processor can run in: "Legacy mode" and "long mode". Legacy mode runs 16-bit and 32-bit programs natively, and long mode runs 64-bit programs natively, but also allows for 32-bit programs running inside a 64-bit operating system. All Athlon 64 processors feature 128 Kilobytes of level 1 cache, and at least 512 KB of level 2 cache.
On-die memory controller.
The Athlon 64 features an on-die memory controller, a feature previously seen on only the Transmeta Crusoe. This means the controller runs at the same clock rate as the CPU and that the electrical signals have a shorter physical distance to travel compared to the old northbridge interfaces. The result is a significant reduction in latency (response time) for access requests to main memory. The lower latency was often cited as one of the advantages of the Athlon 64's architecture over those of its competitors at the time.
Memory and HT Northbridge buses.
As the memory controller is integrated onto the CPU die, there is no FSB for the system memory to base its speed upon. Instead, system memory speed is obtained by using the following formula (using the ceiling function):
In simpler terms, the memory is always running at a set fraction of the CPU speed, with the divisor being a whole number. A 'FSB' figure is still used to determine the CPU speed, but the RAM speed is no longer directly related to this 'FSB' figure (known otherwise as the LDT).
A second bus, the northbridge, connected the CPU to the chipset and device attachment bus (PCIe, AGP, PCI). This was implemented using a new high-performance standard, HyperTransport. AMD attempted, with some success, to make this an industry standard. It was also useful in building multi-processor systems without additional glue chips.
Translation Lookaside Buffers.
Translation Lookaside Buffers (TLBs) have also been enlarged (40 4k/2M/4M entries in L1 cache, 512 4k entries), with reduced latencies and improved branch prediction, with four times the number of bimodal counters in the global history counter. This and other architectural enhancements, especially as regards SSE implementation, improve instruction per cycle (IPC) performance over the previous Athlon XP generation. To make this easier for consumers to understand, AMD has chosen to market the Athlon 64 using a PR (Performance Rating) system, where the numbers roughly map to Pentium 4 performance equivalents, rather than actual clock speed.
Cool'n'Quiet.
Athlon 64 also features CPU speed throttling technology branded "Cool'n'Quiet", a feature similar to Intel's "SpeedStep" that can throttle the processor's clock speed back to facilitate lower power consumption and heat production. When the user is running undemanding applications and the load on the processor is light, the processor's clock speed and voltage are reduced. This in turn reduces its peak power consumption (max TDP set at 89 W by AMD) to as low as 32 W (stepping C0, clock speed reduced to 800 MHz) or 22W (stepping CG, clock speed reduced to 1 GHz). The Athlon 64 also has an Integrated Heat Spreader (IHS) which prevents the CPU die from accidentally being damaged when mounting and unmounting heat sinks. With prior AMD CPUs a CPU shim could be used by people worried about damaging the die.
NX bit.
The No Execute bit (NX bit) supported by Windows XP Service Pack 2 and future versions of Windows, Linux 2.6.8 and higher and FreeBSD 5.3 and higher is also included, for improved protection from malicious buffer overflow security threats. Hardware-set permission levels make it much more difficult for malicious code to take control of the system. It is intended to make 64-bit computing a more secure environment.
Semiconductor Technology.
The Athlon 64 CPUs have been produced with 130 nm and 90 nm SOI process technologies. All of the latest chips (Winchester, Venice and San Diego models) are on 90 nm. The Venice and San Diego models also incorporate dual stress liner technology (an amalgam of strained silicon and 'squeezed silicon', the latter of which is not actually a technology) co-developed with IBM.
Processor cores.
Athlon 64 FX.
The Athlon 64 FX is positioned as a hardware enthusiast product, marketed by AMD especially toward gamers. Unlike the standard Athlon 64, all of the Athlon 64 FX processors have their multipliers completely unlocked. Starting with the FX-60, the FX line became dual-core. The FX always has the highest clock speed of all Athlons at its release. From FX-70 onwards, the line of processors will also support dual-processor setup with NUMA, named AMD Quad FX platform.
Athlon 64 X2.
The Athlon 64 X2 is the first dual-core desktop CPU manufactured by AMD.
In 2007, AMD released two final Athlon 64 X2 versions: the AMD Athlon 64 X2 6400+ and 5000+ Black Editions. Both processors feature an unlocked multiplier, which allows for a large range of overclocked settings. The 6400+ is based on a 90 nm Windsor core (3.2 GHz, 2x1MB L2, 125W TDP) while the 5000+ is based on a 65 nm Brisbane core (2.6 GHz, 2x512KB L2, 65W TDP). These Black Edition processors are available at retail, but AMD does not include heatsinks in the retail package.
Turion 64 (formerly Mobile Athlon 64).
Previously introduced as "Mobile Athlon 64", Turion 64 is now the brand name AMD applies to its 64-bit low-power consumption ("mobile") processors. The Turion 64 and Turion 64 X2 processors compete with Intel's mobile processors, initially the "Pentium M" and later the Intel Core and Intel Core 2 processors.
Earlier Turion 64 processors are compatible with AMD's Socket 754. The newer "Richmond" models are designed for AMD's Socket S1. They are equipped with 512 or 1024 KB of L2 cache, a 64-bit single channel on-die memory controller, and an 800 MHz HyperTransport bus. Battery saving features, like "PowerNow!", are central to the marketing and usefulness of these CPUs.
Model naming methodology.
The model naming scheme does not make it obvious how to compare one Turion with another, or even an Athlon 64. The model name is two letters, a dash, and a two digit number (for example, ML-34). The two letters together designate a processor class, while the number represents a PR rating. The first letter is M for single core processors and T for dual core Turion 64 X2 processors. The later in the alphabet that the second letter appears, the more the model has been designed for mobility (frugal power consumption). Take for instance, an MT-30 and an ML-34. Since the T in the MT-30 is later in the alphabet than the L in ML-34, the MT-30 consumes less power than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30.
Athlon Neo.
With 27 mm × 27 mm in size and 2.5 mm in thickness, the Athlon Neo processors utilize a new package called "ASB1", essentially a BGA package, for smaller footprint to allow smaller designs for notebooks and lowering the cost. The clock of the processors is significantly lower than desktop and other mobile counterparts to reach a low TDP, at 15W maximum for a single core x86-64 CPU at 1.6 GHz. The Athlon Neo processors are equipped with 512 KB of L2 cache and HyperTransport 1.0 running at 800 MHz frequency.
Sockets.
At the introduction of Athlon 64 in September 2003, only Socket 754 and Socket 940 (Opteron) were ready and available. The onboard memory controller was not capable of running unbuffered (non-registered) memory in dual-channel mode at the time of release; as a stopgap measure, they introduced the Athlon 64 on Socket 754, and brought out a non-multiprocessor version of the Opteron called the Athlon 64 FX, as a multiplier unlocked enthusiast part for Socket 940, comparable to Intel's Pentium 4 Extreme Edition for the high end market.
In June 2004, AMD released Socket 939 as the mainstream Athlon 64 with dual-channel memory interface, leaving Socket 940 solely for the server market (Opterons), and relegating Socket 754 as a value/budget line, for Semprons and slower versions of the Athlon 64. Eventually Socket 754 replaced Socket A for Semprons.
In May 2006, AMD released Socket AM2, which provided support for the DDR2 memory interface. Also, this marked the release of AMD-V.
In August 2006, AMD released Socket F for Opteron server CPU which uses the LGA chip form factor.
In November 2006, AMD released a specialized version of Socket F, called 1207 FX, for dual-socket, dual-core Athlon FX processors on the Quad FX platform. While Socket F Opterons already allowed for four processor cores, Quad FX allowed unbuffered RAM and expanded CPU/chipset configuration in the BIOS. Consequentially, Socket F and F 1207 FX are incompatible and require different processors, chipsets, and motherboards.
Athlon 64 FX models.
Toledo (90 nm SOI).
Dual-core CPU
Windsor (90 nm SOI).
Dual-core CPU
Windsor (90 nm SOI) - Quad FX platform.
Dual-core, dual CPUs (four cores total)
Athlon 64 models.
Newcastle (130 nm SOI).
Also possible: ClawHammer-512 (Clawhammer with partially disabled L2-Cache)
Successors.
The Athlon 64 was succeeded by the K10 architecture in 2007, including but not limited to the Phenom and Phenom II processors. These successors feature higher core counts per CPU, and implement Hypertransport 3.0 and Socket AM2+/AM3.
As of February 2012, Athlon64 X2 processors were still available for sale.


Radeon Software


POWER4

The POWER4 is a microprocessor developed by International Business Machines (IBM) that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, and was used in RS/6000 and AS/400 computers, ending a separate development of PowerPC microprocessors for the AS/400. The POWER4 was a multicore microprocessor, with two cores on a single die, the first non-embedded microprocessor to do so. POWER4 Chip was first commercially available multiprocessor chip. The original POWER4 had a clock speed of 1.1 and 1.3 GHz, while an enhanced version, the POWER4+, reached a clock speed of 1.9 GHz. The PowerPC 970 is a derivative of the POWER4.
Functional layout.
The POWER4 has a unified L2 cache, divided into three equal parts. Each has its own independent L2 controller which can feed 32 bytes of data per cycle. The Core Interface Unit (CIU) connects each L2 controller to either the data cache or instruction cache in either of the two processors. The Non-Cacheable (NC) Unit is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topology. There is an L3 cache controller, but the actual memory is off-chip. The GX bus controller controls I/O device communications, and there are two 4-byte wide GX buses, one incoming and the other outgoing. The Fabric Controller is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4 chips {4-way, 8-way, 16-way, 32-way} and POWER4 MCM's. Trace-and-Debug, used for First Failure Data Capture, is provided. There is also a Built In Self Test function (BIST) and Performance Monitoring Unit (PMU). Power-on reset (POR) is supported.
Execution units.
The POWER4 implements a superscalar microarchitecture through high-frequency speculative out-of-order execution using eight independent execution units. They are: two floating-point units (FP1-2), two load-store units (LD1-2), two fixed-point units (FX1-2), a branch unit (BR), and a conditional-register unit (CR). These execution units can complete up to eight operations per clock (not including the BR and CR units):
The pipeline stages are:
Multi-chip configuration.
The POWER4 also came in a configuration using a multi-chip module (MCM) containing four POWER4 dies in a single package, with up to 128 MB of shared L3 ECC cache per MCM.
POWER4+.
The POWER4+, released in 2003, was an improved version of the POWER4 that ran at up to 1.9 GHz. It contained 184 million transistors, measured 267 mm2, and was fabricated in a 0.13 µm SOI CMOS process with eight layers of copper interconnect.


GeForce 3 series

The GeForce 3 series (NV20) is the third generation of Nvidia's GeForce graphics processing units (GPUs). Introduced in February 2001, it advanced the GeForce architecture by adding programmable pixel and vertex shaders, multisample anti-aliasing and improved the overall efficiency of the rendering process.
The GeForce 3 was unveiled during the 2001 Macworld Conference & Expo/Tokyo 2001 in Makuhari Messe and powered realtime demos of Pixar's Junior Lamp and id Software's Doom 3. Apple would later announce launch rights for its new line of computers.
The GeForce 3 family comprises 3 consumer models: the GeForce 3, the GeForce 3 Ti200, and the GeForce 3 Ti500. A separate professional version, with a feature-set tailored for computer aided design, was sold as the Quadro DCC. A derivative of the GeForce 3, known as the NV2A, is used in the Microsoft Xbox game console.
Architecture.
Introduced three months after NVIDIA acquired 3dfx and marketed as the "nFinite FX Engine", the GeForce 3 was the first Microsoft Direct3D 8.0 compliant 3D-card. Its programmable shader architecture enabled applications to execute custom visual effects programs in Microsoft Shader language 1.1. It is believed that the fixed-function T&L hardware from GeForce 2 was still included on the chip for use with Direct3D 7.0 applications, as the single vertex shader was not fast enough to emulate it yet. With respect to pure pixel and texel throughput, the GeForce 3 has four pixel pipelines which each can sample two textures per clock. This is the same configuration as GeForce 2, excluding the slower GeForce 2 MX line.
To take better advantage of available memory performance, the GeForce 3 has a memory subsystem dubbed "Lightspeed Memory Architecture" (LMA). This is composed of several mechanisms that reduce overdraw, conserve memory bandwidth by compressing the z-buffer (depth buffer) and better manage interaction with the DRAM.
Other architectural changes include EMBM support (first introduced by Matrox in 1999) and improvements to anti-aliasing functionality. Previous GeForce chips could perform only super-sampled anti-aliasing (SSAA), a demanding process that renders the image at a large size internally and then scales it down to the end output resolution. GeForce 3 adds multi-sampling anti-aliasing (MSAA) and Quincunx anti-aliasing methods, both of which perform significantly better than super-sampling anti-aliasing at the expense of quality. With multi-sampling, the render output units super-sample only the Z buffers and stencil buffers, and using that information get greater geometry detail needed to determine if a pixel covers more than one polygonal object. This saves the pixel/fragment shader from having to render multiple fragments for pixels where the same object covers all of the same sub-pixels in a pixel. This method fails with texture maps which have varying transparency (e.g. a texture map that represents a chain link fence). Quincunx anti-aliasing is a blur filter that shifts the rendered image a half-pixel up and a half-pixel left in order to create sub-pixels which are then averaged together in a diagonal cross pattern, destroying both jagged edges but also some overall image detail. Finally, the GeForce 3's texture sampling units were upgraded to support 8-tap anisotropic filtering, compared to the previous limit of 2-tap with GeForce 2. With 8-tap anisotropic filtering enabled, distant textures can be noticeably sharper.
Performance.
The GeForce 3 GPU (NV20) has the same theoretical pixel and texel throughput per clock as the GeForce 2 (NV15). GeForce 2 Ultra is clocked 25% faster than the original GeForce 3 and 43% faster than the Ti200; this means that in select instances, like Direct3D 7 T&L benchmarks, the GeForce 2 Ultra and sometimes even GTS can outperform the GeForce 3 and Ti200, because the newer GPUs use the same fixed-function T&L unit, but are clocked lower. The GeForce 2 Ultra also has considerable raw memory bandwidth available to it, only matched by the GeForce 3 Ti500. However, when comparing anti-aliasing performance the GeForce 3 is clearly superior because of its MSAA support and memory bandwidth/fillrate management efficiency.
When comparing the shading capabilities to the Radeon 8500, reviewers noted superior precision with the ATi card.
Product positioning.
NVIDIA refreshed the lineup in October 2001 with the release of the GeForce 3 Ti200 and Ti500. This coincided with ATI's releases of the Radeon 8500 and Radeon 7500. The Ti500 has higher core and memory clocks (240 MHz core/250 MHz RAM) than the original GeForce 3 (200 MHz/230 MHz), and generally matches the Radeon 8500. The Ti200 was the slowest, and lowest-priced GeForce3 release. It is clocked lower (175 MHz/200 MHz) yet it surpasses the Radeon 7500 in speed and feature set besides dual-monitor implementation.
The original GeForce3 was only released in 64 MiB configurations, while the Ti200 and Ti500 were also released as 128 MiB versions.
Discontinued support.
Nvidia has ceased driver support for GeForce 3 series.
Final drivers include.
Windows 95/98/Me Driver Archive
Windows XP/2000 Driver Archive
Successor.
The GeForce 4 Series (Non-MX), introduced in April 2002, was a revision of the GeForce 3 architecture. The budget variant, dubbed the GeForce 4 MX, was closer in terms of design to the GeForce 2.


EVEX prefix

The EVEX prefix (Enhanced vector extension) and corresponding coding scheme is an extension to the 32-bit x86 (IA-32) and 64-bit x86-64 (AMD64) instruction set architecture. EVEX is based on, but should not be confused with the MVEX prefix used by the Knights Corner processor.
The EVEX scheme is a 4-byte extension to the VEX scheme which supports the AVX-512 instruction set and allows addressing new 512-bit ZMM registers and new 64-bit operand mask registers.
Features.
EVEX coding can address 8 operand mask registers, 16 general-purpose registers and 32 vector registers in 64-bit mode (otherwise, 8 general-purpose and 8 vector), and can support up to 4 operands.
Like the VEX coding scheme, the EVEX prefix unifies existing opcode prefixes and escape codes, memory addressing and operand length modifiers of the x86 instruction set .
The following features are carried over from the VEX scheme:
EVEX also extends VEX with additional capabilities:
For example, the EVEX encoding scheme allows conditional vector addition in the form of
 VADDPS zmm1 {k1}{z}, zmm2, zmm3
where {k1} modifier next to the destination operand encodes the use of opmask register k1 for conditional processing and updates to destination, and {z} modifier (encoded by EVEX.z) provides the two types of masking (merging and zeroing), with merging as default when no modifier is attached.
Technical description.
The EVEX coding scheme uses a code prefix consisting of 4 bytes; the first byte is always 62h and derives from an unused opcode of the 32-bit BOUND instruction, which is not supported in 64-bit mode.
The ModR/M byte specifies one operand (always a register) with "reg" field, and the second operand is encoded with "mod" and "r/m" fields, specifying either a register or a location in memory. Base-plus-index and scale-plus-index addressing require the SIB byte, which encodes 2-bit "scale" factor as well as 3-bit "index" and 3-bit "base" registers. Depending on the addressing mode, Disp8/Disp16/Disp32 field may follow with displacement that needs to be added to the address.
The EVEX prefix retains fields introduced in the VEX prefix:
New functions of the existing fields:
There are several new bit fields:
The encoding of the EVEX prefix is as follows:
The following table lists possible register addressing combinations (bit 4 is always zero when encoding the 16 general purpose registers):
A few VEX-encoded AVX blending instructions have 4 operands. To accommodate this, VEX has IS4 addressing mode, which encodes 4th operand (a vector register) in bits Imm8[7:4] of the immediate constant. Similar EVEX-encoded blend instructions have their 4th operand in a mask register. No EVEX-encoded instruction uses IS4 addressing mode encoding.


Microsoft SQ2


Namco Arcade Stick

The is a joystick video game controller released by Namco in 1996 for the PlayStation.
Overview.
The Arcade Stick functions similar towards the layout of a generic arcade stick found on an arcade game machine. It also features very similar components, manufactured by Hori. It is compatible with the original PlayStation control pad protocol, therefore it can be used with many games for PlayStation and PlayStation 2. Namco PlayStation games such as "Tekken", "Soul Edge" and "Namco Museum Encore" are labelled as compatible with the peripheral. It is also compatible with the PlayStation 3 upon use of a PS2 to PC USB adapter. Functionality was expanded on the PlayStation 3 upon the 2.0 firmware update. It is fully compatible with PlayStation 3 fighting games such as "Ultimate Marvel vs. Capcom 3", "Tekken Tag Tournament 2", and "Super Street Fighter IV".


Pentium M

The Pentium M is a family of mobile 32-bit single-core x86 microprocessors (with the modified Intel P6 microarchitecture) introduced in March 2003 and forming a part of the Intel Carmel notebook platform under the then new Centrino brand. The "Pentium M" processors had a maximum thermal design power (TDP) of 5–27 W depending on the model, and were intended for use in laptops (thus the "M" suffix standing for "mobile"). They evolved from the core of the last Pentium III–branded CPU by adding the front-side bus (FSB) interface of Pentium 4, an improved instruction decoding and issuing front end, improved branch prediction, SSE2 support, and a much larger cache. The first Pentium M–branded CPU, code-named Banias, was followed by Dothan. The Pentium M-branded processors were succeeded by the Core-branded dual-core mobile Yonah CPU with a modified microarchitecture.
Overview.
The Pentium M represented a new and radical departure for Intel, as it was not a low-power version of the desktop-oriented Pentium 4, but instead a heavily modified version of the Pentium III Tualatin design (itself based on the Pentium II core design, which in turn had been a heavily improved evolution of the Pentium Pro). It is optimized for power efficiency, a vital characteristic for extending notebook computer battery life. Running with very low average power consumption and much lower heat output than desktop processors, the Pentium M runs at a lower clock speed than the laptop version of the Pentium 4 (The Pentium 4-Mobile, or P4-M), but with similar performance - a 1.6 GHz Pentium M can typically attain or even surpass the performance of a 2.4 GHz Pentium 4-M. The Pentium M 740 has been tested to perform up to approximately 7,400 MIPS and 3.9 GFLOPS (using SSE2).
The Pentium M coupled the execution core of the Pentium III with a Pentium 4 compatible bus interface, an improved instruction decoding/issuing front end, improved branch prediction, SSE2 support, and a much larger cache. The usually power-hungry secondary cache uses an access method which only switches on the portion being accessed. The main intention behind the large cache was to keep a decent-sized portion of it still available to the processor even when most of the L2 cache was switched off, but its size led to a welcome improvement in performance.
Other power saving methods include dynamically variable clock frequency and core voltage, allowing the Pentium M to throttle clock speed when the system is idle in order to conserve energy, using the SpeedStep 3 technology (which has more sleep stages than previous versions of SpeedStep). With this technology, a 1.6 GHz Pentium M can effectively throttle to clock speeds of 600 MHz, 800 MHz, 1000 MHz, 1200 MHz, 1400 MHz and 1600 MHz; these intermediate clock states allow the CPU to better throttle clock speed to suit conditions. The power requirements of the Pentium M varies from 5 watts when idle to 27 watts at full load. This is useful to notebook manufacturers as it allows them to include the Pentium M into smaller notebooks.
Although Intel marketed the Pentium M exclusively as a mobile product, motherboard manufacturers such as AOpen, DFI and MSI shipped Pentium M compatible boards designed to non-mobile enthusiasts, HTPC, workstation and server applications. An adapter, the CT-479, was developed by ASUS to allow the use of Pentium M processors in selected ASUS motherboards designed for Socket 478 Pentium 4 processors. Shuttle Inc. offered packaged Pentium M desktops, marketed for low energy consumption and minimal cooling system noise. Pentium M processors are also of interest to embedded systems' manufacturers because the low power consumption of the Pentium M allows the design of fanless and miniaturized embedded PCs. The Pentium M also responds very well to undervolting, which can be done with the program Notebook Hardware Control or RMClock.
Banias.
As the M line was originally designed in Israel, the first Pentium M was identified by the codename Banias, named after an ancient site in the Golan Heights. The Intel Haifa team had previously been working on the memory controller for Timna, which was based on earlier P6 memory controller designs giving them detailed knowledge of P6 architecture which they used when Intel gave them a crash project to create a backup mobile CPU. Given the product code 80535, it initially had no model number suffix, but was later identified as the Pentium M 705. It was manufactured on a 130 nm process, was released at frequencies from 900 MHz to 1.7 GHz using a 400 MT/s FSB, and had 1 megabyte (MB) of Level 2 cache. The core average TDP (Thermal Design Power) is 24.5 watts.
The Banias family processors internally support Physical Address Extension (PAE) but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support is required in their kernels. Using the 'forcepae' Linux boot option will allow Linux to boot using PAE in these cases.
Windows 8 and later won't boot on these CPUs for the same reason, emitting an error with code 0xc0000260 when attempting to load ntoskrnl.exe early on in the boot process.
Dothan.
On September 17, 2003, Intel unveiled plans for releasing its then next-generation of Pentium M processors, codenamed "Dothan" by them. It was named after another ancient town in Israel, and it launched formally on May 10, 2004. Dothan Pentium M processors (product code 80536, CPUID 0x6DX) are among the first Intel processors to be identified using a "processor number" rather than a clockspeed rating; the initial Dothan versions with the 400Mhz Front-Side-Bus (FSB) are known as Pentium M 710 (1.4 GHz), 715 (1.5 GHz), 725 (1.6 GHz), 735 (1.7 GHz), 745 (1.8 GHz), 755 (2.0 GHz), and 765 (2.1 GHz). These initial Dothan models all have a TDP of 21 W and a 2 MB L2 cache.
These 700 series Dothan Pentium M processors retain the same basic design as the original Banias Pentium M, but are manufactured on a 90 nm process, with twice the secondary cache. Die size, at 87 mm2, remains in the same neighborhood as the original Pentium M, even though the 1000 series contains approximately 140 million transistors, most of which make up the 2 MB cache. TDP is also down to 21 watts with the 400 MT/s FSB (from 24.5 watts in Banias), though power use at lower clockspeeds has increased highly
However, tests conducted by third party hardware review sites show that Banias and Dothan equipped notebooks have roughly equivalent battery life.
Additionally third party hardware review sites have benchmarked the Dothan at approx 10-20% better performance than the Banias in most situations.
Revisions of the Dothan core were released in the first quarter of 2005 with the Sonoma chipsets and supported a 533 MT/s FSB and XD (Intel's name for the NX bit); and the PAE support flag in the CPUID was enabled, unlike earlier Pentium Ms that showed PAE unavailable. These revised Dothan processors include the 730 (1.6 GHz), 740 (1.73 GHz), 750 (1.86 GHz), 760 (2.0 GHz), 770 (2.13 GHz) and 780 (2.26 GHz) and have a TDP of 27 W and a 2 MB L2 cache.
In July 2005, Intel released the 780 (2.26 GHz) and the low-voltage 778 (1.60 GHz).
The processor line had models running at clock speeds from 1.0 GHz to 2.26 GHz . The models with lower frequencies were either low voltage or ultra-low voltage CPUs designed for improved battery life and reduced heat output. The 718 (1.3 GHz), 738 (1.4 GHz), and 758 (1.5 GHz) models are low-voltage (1.116 V) with a TDP of 10 W, while the 723 (1.0 GHz), 733 (1.1 GHz), and 753 (1.2 GHz) models are ultra-low voltage (0.940 V) with a TDP of 5 W.
Intel A100 Series.
An ultra low-power microprocessor based on the Dothan built on a 90 nm process with 512 KB L2 cache and 400 MT/s front side bus (FSB).
Core Solo and Core Duo.
The next generation of processors, codenamed Yonah, were based on the Enhanced Pentium M architecture, and released under the Intel Core brand, as Core Duo and Core Solo.


Intel Cluster Ready

The Intel Cluster Ready certification is a marketing program from Intel. It is aimed at hardware and software vendors in the low-end and mid-range cluster market. To get certified, systems have to fulfill a minimum set of cluster-specific requirements. This way, vendors of parallel software can build their applications on a basic cluster platform, trusting certain components to be present. Other drivers, libraries and tools will have to be provided by the software vendor or its partners, or by a system integrator.
Description.
The program was announced in June 2007.
The nodes of an Intel Cluster Ready compliant cluster are based on Xeon server processors and PC hardware, interconnected through Ethernet or InfiniBand. The operating system is a Linux distribution conforming to a specific file system layout. Also included are Intel's closed source but publicly available parallel libraries: the Message Passing Interface, Threading Building Blocks, and Math Kernel Library.
Intel only specifies the requirements a cluster has to fulfill to get certified. The specific implementation is the responsibility of the platform vendor. Intel's Cluster Checker checks the system's compliance. It is not only deployed by the vendor, the integrator and the end user to verify the system, it can also be used to troubleshoot an operational cluster.
While cluster hardware gets certified, software can be registered as well. Intel provides a minimal cluster infrastructure where software vendors can run their package, test scripts and test data. After successful completion, the application gets registered as being Intel Cluster Ready compliant. The Cluster Ready program is free for both hardware and software vendors.
The Intel Cluster Ready program does not primarily include the high-end clusters used for scientific calculations at universities and research institutes. It aims to commoditize the parallel systems used for industrial and commercial applications. According to IDC, more than half of the servers currently sold for technical applications is deployed as part of a cluster. For example, these systems are used for industrial computations, financial analyses, and modelling in engineering. IDC expects clustered systems to responsible for more than three-quarters of the high-performance technical computing market.
AMD-based clusters.
Although the Cluster Ready program is aimed at systems built on Intel's Xeon processors, the Cluster Checker can also be used to verify an Advanced Micro Devices-based system. Intel's parallel libraries run on AMD hardware with the same performance and are fully supported by Intel. According to Werner Krotz-Vogel, Technical Marketing Engineer at Intel's Cluster Ready team, the Math Kernel Library (MKL) runs even faster than the open source library Automatically Tuned Linear Algebra Software (ATLAS) on an AMD Opteron system.


PA-RISC

PA-RISC is an instruction set architecture (ISA) developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer (RISC) architecture, where the PA stands for Precision Architecture. The design is also referred to as HP/PA for Hewlett Packard Precision Architecture.
The architecture was introduced on 26 February 1986, when the HP 3000 Series 930 and HP 9000 Model 840 computers were launched featuring the first implementation, the TS1.
PA-RISC has been succeeded by the Itanium (originally IA-64) ISA, jointly developed by HP and Intel. HP stopped selling PA-RISC-based HP 9000 systems at the end of 2008 but supported servers running PA-RISC chips until 2013.
History.
In the late 1980s, HP was building four series of computers, all based on CISC CPUs. One line was the IBM PC compatible Intel i286-based Vectra Series, started in 1986. All others were non-Intel systems. One of them was the HP Series 300 of Motorola 68000-based workstations, another Series 200 line of technical workstations based on a custom silicon on sapphire (SOS) chip design, the SOS based 16-bit HP 3000 classic series, and finally the HP 9000 Series 500 minicomputers, based on their own (16 and 32-bit) FOCUS microprocessor.
The Precision Architecture is the result of what was known inside Hewlett-Packard as the Spectrum program. HP planned to use Spectrum to move all of their non-PC compatible machines to a single RISC CPU family.
Work began on the Precision Architecture at HP Laboratories in early 1982 defining the instruction set and virtual memory system, and the first TTL implementation began in April 1983, with simulation of the processor occurring in 1983, and with a complete processor delivered to software developers in July 1984. Systems prototyping followed, with "lab prototypes" being produced in 1985 and product prototypes in 1986.
The first processors were introduced in products during 1986. It had thirty-two 32-bit integer registers and sixteen 64-bit floating-point registers. The number of floating-point registers was doubled in the 1.1 version to 32 once it became apparent that 16 were inadequate and restricted performance. The architects included Allen Baum, Hans Jeans, Michael J. Mahon, Ruby Bei-Loh Lee, Russel Kao, Steve Muchnick, Terrence C. Miller, David Fotland, and William S. Worley.
The first implementation was the TS1, a central processing unit built from discrete transistor–transistor logic (74F TTL) devices. Later implementations were multi-chip VLSI designs fabricated in NMOS processes (NS1 and NS2) and CMOS (CS1 and PCX).
They were first used in a new series of HP 3000 machines in the late 1980s – the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs. These machines ran MPE-XL. The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX.
Other operating systems ported to the PA-RISC architecture include Linux, OpenBSD, NetBSD and NeXTSTEP.
An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache. Instead large Level 1 caches are used, formerly as separate chips connected by a bus, and now integrated on-chip. Only the PA-7100LC and PA-7300LC had L2 caches. Another innovation of the PA-RISC was the addition of vectorized instructions (SIMD) in the form of MAX, which were first introduced on the PA-7100LC.
Precision RISC Organization, an industry group led by HP, was founded in 1992, to promote the PA-RISC architecture. Members included Convex, Hitachi, Hughes Aircraft, Mitsubishi, NEC, OKI, Prime, Stratus, Yokogawa, Red Brick Software, and Allegro Consultants, Inc..
The ISA was extended in 1996 to 64 bits, with this revision named PA-RISC 2.0. PA-RISC 2.0 also added fused multiply–add instructions, which help certain floating-point intensive algorithms, and the MAX-2 SIMD extension, which provides instructions for accelerating multimedia applications. The first PA-RISC 2.0 implementation was the PA-8000, which was introduced in January 1996.


System 573

The System 573 is a series of arcade system boards by Konami based on the original PlayStation. The hardware was used primarily for Konami's Bemani series of music video game arcades, most commonly the "Dance Dance Revolution" series introduced in 1998. The System 573 is available in two variants with analog and digital I/O boards, dubbed the Bemani System 573 Analog and Bemani System 573 Digital respectively, along with a third variant called the System 573 Satellite Terminal which allows for up to 8 cabinets to be networked to a central one.
The name of the board is rooted in Japanese wordplay; each number in Japanese can be read with a number of different names, with Konami's name being one of many possible readings for "five-seven-three."


Bust-A-Move 3 DX


CID The Dummy

CID The Dummy is an adventure video game released for the PlayStation 2, Wii, Microsoft Windows and PlayStation Portable on April 17, 2009 in Europe and July 7, 2009 in North America.
Reception.
"CID The Dummy" received negative reviews upon its release. On Metacritic, the game holds scores of 41/100 for the PlayStation Portable version based on 6 reviews, and 31/100 for the Wii version based on 7 reviews. On GameRankings, the game holds scores of 36.00% for the PlayStation 2 version based on 2 reviews, 35.60% for the PlayStation Portable version based on 5 reviews, and 33.43% for the Wii version based on 7 reviews. The game was panned by both gamers and critics for its lackluster gameplay, sluggish controls, poor graphics and awful voice acting.


Richard Soley

Richard Mark Soley (born c. 1960, in Baltimore, Maryland) is an American computer scientist and businessman, and Chairman and CEO of the Object Management Group, Inc. (OMG). He is also Executive Director of the Cloud Standards Customer Council, and Executive Director of the Industrial Internet Consortium, managed by the OMG.
Life and work.
Soley studied Computer Science and Engineering at the Massachusetts Institute of Technology, where he obtained his B.A. in 1982, his M.A. in 1985 and his Ph.D. in 1989. He began his professional life at Honeywell, working on the Multics operating system.
Soley joined OMG as Technical Director in 1989, leading the development of OMG's standardization process and the original CORBA specification.
In 1996, he led the effort to move into vertical market standards (starting with healthcare, finance, telecommunications and manufacturing) and modeling. Those efforts made OMG a major early adopter of Unified Modeling Language (UML) and model-driven architecture (MDA).
Soley was co-founder and former Chairman and CEO of A.I. Architects, Inc., a firm which manufactured hardware and software for personal computers and workstations. He has also served as a consultant on matters relating to software investment opportunities for several corporations including IBM, Motorola, and Texas Instruments.


Wait state

A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond.
Computer microprocessors generally run much faster than the computer's other subsystems, which hold the data the CPU reads and writes. Even memory, the fastest of these, cannot supply data as fast as the CPU could process it. In an example from 2011, typical PC processors like the Intel Core 2 and the AMD Athlon 64 X2 run with a clock of several GHz, which means that one clock cycle is less than 1 nanosecond (typically about 0.3 ns to 0.5 ns on modern desktop CPUs), while main memory has a latency of about 15–30 ns. Some second-level CPU caches run slower than the processor core.
When the processor needs to access external memory, it starts placing the address of the requested information on the address bus. It then must wait for the answer, that may come back tens if not hundreds of cycles later. Each of the cycles spent waiting is called a wait state.
Wait states are a pure waste of a processor's performance. Modern designs try to eliminate or hide them using a variety of techniques: CPU caches, instruction pipelines, instruction prefetch, branch prediction, simultaneous multithreading and others. No single technique is 100% successful, but together can significantly reduce the problem.
Energy conservation.
Wait states can be used to reduce the energy consumption of a processor, by allowing the main processor clock to either slow down or temporarily pause during the wait state if the CPU has no other work to do. Rather than spinning uselessly in a tight loop waiting for data, sporadically reducing the clock speed in this manner helps to keep the processor core cool and to extend battery life in portable computing devices.
Alternative meaning on IBM mainframes.
On IBM mainframes, the term "wait state" is used with a different meaning. A wait state refers to a CPU being halted, possibly due to some kind of serious error condition (such as an unrecoverable error during operating system to IPL). A wait state is indicated by bit 14 of the PSW being set to 1, with other bits of the PSW providing a wait state code giving a reason for the wait. In z/Architecture mode, the wait state code is found in bits 116-127.


MRCI (interface)


NEC V30


3rd Super Robot Wars

 was the third game in a series, the second in the "classic" canon, and the first on the Super Famicom, published on July 23, 1993. Along with "2nd" and "EX", "3rd Super Robot Wars" was released on the Sony PlayStation on June 10, 1999, as part of "Super Robot Wars Complete Box" and June 22, 1999, as a stand-alone port.
Story.
The game take place after the "2nd Super Robot Wars", the Divine Crusaders reformed under the leadership of the Zabi family, led by Gihren Zabi, who plans to use the DC to create a dictatorship. However, as the Federation tries to deal with the resurgence of the DC, a new foe appears, the aliens which Bian Zoldark warned of.


Bit Test

The codice_1 x86 assembly language instruction stands for Bit Test and was added to the x86 instruction set with the 80386 processor. codice_1 copies a bit from a given register to the carry flag.
Example: copy the third least significant bit from EAX to the carry flag
BT EAX, 2
codice_3 (Bit Test and Set) operates the same, but also sets the bit in the register, while codice_4 (Bit Test and Reset) resets it, and codice_5 (Bit Test and Complement) flips it.
Logical Explanation BT
 BT SRC, POSITION
 SRC
 Represent as bits array
 POSITION
 Represent as numeric position
 From Right to Left
 Start at 0
 CF
 Carry Flag
 Result
 CF = SRC[POSITION]
Logical Explanation BTC
 BTC SRC, POSITION
 SRC
 Represent as bits array for CF Result
 Represent as hex for SRC Result
 POSITION
 Represent as numeric position
 From Right to Left
 Start at 0
 CF
 Carry Flag
 Result
 CF = SRC[POSITION]
 XOR SRC, POW(2,POSITION)


Radeon X700 series

The Radeon X700 (RV410) series replaced the X600 in September 2004. X700 Pro is clocked at 425 MHz core, and produced on a 0.11 micrometre process. RV410 used a layout consisting of 8 pixel pipelines connected to 4 ROPs (similar to GeForce 6600) while maintaining the 6 vertex shaders of X800. The 110 nm process was a cost-cutting process, designed not for high clock speeds but for reducing die size while maintaining high yields. An X700 XT was planned for production, and reviewed by various hardware web sites, but was never released. It was believed that X700 XT set too high of a clock ceiling for ATI to profitably produce. X700 XT was also not adequately competitive with nVidia's impressive GeForce 6600GT. ATI would go on produce a card in the X800 series to compete instead.


VIEWMAX.APP


NXP ColdFire

The NXP ColdFire is a microprocessor that derives from the Motorola 68000 family architecture, manufactured for embedded systems development by NXP Semiconductors. It was formerly manufactured by Freescale Semiconductor (formerly the semiconductor division of Motorola) which merged with NXP in 2015.
Instruction set.
The ColdFire instruction set is "assembly source" compatible (by means of translation software available from the vendor) and not entirely object code compatible with the 68000. When compared to classic 68k hardware, the instruction set differs mainly in that it no longer has support for the binary-coded decimal (BCD) packed data format; it removes a number of other, less used instructions; and most instructions that are kept support fewer addressing modes. Also, floating point intermediates are 64 bits and not 80 bits as in the 68881 and 68882 coprocessors. The instructions are only 16, 32, or 48 bits long, a simplification compared to the 68000 series.
Models.
In February 1999, the μClinux project's Linux kernel was ported to two ColdFire processors (MCF5206 and MCF5307). In 2006, the Debian project was looking into making its m68k port compatible with the ColdFires, as there are ColdFire models that can be clocked as high as 300 MHz. This is much faster than the 68060, which can officially reach 75 MHz and can be overclocked to 110 MHz. Stallion Technologies ePipe, Secure Computing SnapGear security appliances, and Arcturus Networks's System on Module products are based on ColdFire processors. There are ColdFire Linux-based single-board computers (SBC) with Ethernet and CompactFlash as small as 23×55 mm or 45×45 mm or based on CompactFlash (37×43 mm) itself. ColdFire based products have even been deployed to the International Space Station as an electronic nose project.
There are five generations or versions of the ColdFire available from Freescale:
There is also the Fido 1100, a microcontroller launched in 2007 aimed at predictable embedded control systems such as Industrial Ethernet applications using the 68k/CPU32 instruction set. However, Fido has its own unique architecture and shares the instruction set with 68k only.
In November 2006, Freescale announced that ColdFire microprocessor cores were available for license as semiconductor Intellectual Property through their IP licensing and support partner IPextreme Inc. ColdFire v1 core is now available under Free license (and no per use royalty) for Altera Cyclone-III FPGA's.
In September 2007, Freescale launched the 32-bit Flexis microcontroller family with a ColdFire CPU core.
In June 2010, Freescale announced the ColdFire+ line, which is a ColdFire V1 core using a 90 nm TFS technology.
In 2010, Freescale also launched Kinetis, an ARM-based product line, leading some industry observers to speculate about the future of the ColdFire range, given that Freescale would have several competing CPU ranges.


List of PS one Classics (PAL region)

This is a list of PS one Classics that are available in the PAL region on PlayStation 3, PlayStation Portable and PlayStation Vita.


Accent kernel

Accent was an operating system kernel developed at Carnegie Mellon University (CMU). Accent was developed as a follow-on to the Aleph kernel developed at the University of Rochester, fixing several of its problems and re-targeting its hardware support for networks of workstation machines (specifically, the Three Rivers PERQ) instead of minicomputers. Accent was part of the SPICE Project at CMU which ran from 1981 to 1985. Development of Accent led directly to the famous Mach kernel.
The original Aleph project used data copying to allow programs to communicate. Applications could open "ports", which would allow them to receive data sent to them by other programs. The idea was to write a number of "servers" that would control resources on the machine, passing data along until it reached an end user. In this respect it was similar in concept to Unix, although the implementation was much different, using messages instead of memory. This turned out to have a number of problems, notably that copying memory on their Data General Eclipse was very expensive.
In 1979 one of the Aleph engineers, Richard Rashid, left for CMU and started work on a new version of Aleph that avoided its problems. In particular, Accent targeted workstation machines featuring a MMU, using the MMU to "copy" large blocks of memory via "mapping", making the memory appear to be in two different places. Only data that was changed by one program or another would have to be physically copied, using the copy-on-write algorithm.
To understand the difference, consider two interacting programs, one feeding a file to another. Under Aleph the data from the provider would have to be copied 2kB at a time (due to features of the Eclipse) into the user process. Under Accent the data simply "appeared" in the user process for the cost of a few instructions sent to the MMU. Only if the user process changed the data would anything need to be copied, and even then, only the portions of the data that actually changed.
Another problem in Aleph was that its ports were identified by unique ID's that were assigned sequentially. It was simple for a program to "guess" them, thereby gaining access to resources on the computer that it had not been granted. This made the Aleph system rather insecure.
To address this, Accent made the port ID's internal to the kernel only. Instances of a program opening ports were handed back different IDs, stored in a mapping in the kernel. Whenever a message was sent to the kernel for delivery, it would first check that the program had access to the port in question by comparing with the mapping table for that program. Guessing port numbers no longer worked, the program's port IDs gave no clue of the "real" IDs in the kernel, and any attempt to talk on one not explicitly handed out by the kernel was an error. Thus Accent's ports represented "capabilities", granting rights to use resources as the result of being handed a valid port ID. This kind of capability system, using subject-specific identifiers for capabilities, is called a C-list system.
After a few years the Accent project started looking less and less interesting. In the early 1980s many felt that future gains in performance would be made by adding more CPUs to machines, something the Accent kernel was not really equipped to handle. Adding to the problem was that a new generation of more powerful workstations were appearing, meaning that Accent would likely have to be ported to them anyway. Likewise Unix had grown into "the" operating system of choice for experimental work, both on operating system design, as well as a development platform for user applications.
In order to address these changes, it was decided to end work on Accent and start again. The new system would use Accent's ports system within a Unix kernel, creating the famed Mach kernel.
Some features of Accent:


Cutie Suzuki no Ringside Angel

 is a 1990 Japan-exclusive Sega Mega Drive video game about female professional wrestling. It features the famous female Japanese wrestler Cutie Suzuki.
As the first video game based on women's professional wrestling for the Sega Mega Drive, it played a pivotal role in establishing women as protagonists in 16-bit video games, predating Alisia Dragoon by two years.
Plot.
Many girls in Japan have dreamt of fighting in a professional wrestling federation. All their training effort has helped them become glamorous professional wrestlers who dream of glory. Only nine girls have the "burning spirit" to fight for the five major titles of women's professional wrestling.
Gameplay.
Punching is allowed in addition to traditional wrestling moves like the piledriver and the suplex. There is even a spectator mode that allows players to preview each fighter's moves.
Damage is displayed for each fighter by the facial expressions of the character. Players can continue to lose matches without the threat of a game over screen. Each wrestler recovers stamina at a different rate. They also have different ways of expressing physical pain and they have different types of screams when they are in anguish.


Nemesis (operating system)

Nemesis was an operating system that was designed by the University of Cambridge, the University of Glasgow, the Swedish Institute of Computer Science and Citrix Systems.
Nemesis was conceived with multimedia uses in mind. In a microkernel environment, an application is typically implemented by a number of processes, most of which are servers performing work on behalf of more than one client. This leads to enormous difficulty in accounting for resource usage. In a Monolithic kernel based system, multimedia applications spend most of their time in the kernel, leading to similar problems.
The guiding principle in the design of Nemesis was to structure the operating system in such a way that the majority of code could execute in the application process itself. Nemesis therefore had an extremely small lightweight kernel and performed most operating system functions in shared libraries, which executed in the user’s process.
The ISAs that Nemesis supports include x86 (Intel i486, Pentium, Pentium Pro, and Pentium II), Alpha and ARM (StrongARM SA–110). Nemesis also runs on evaluation boards (21064 and 21164).


Boot disk

A boot disk is a removable digital data storage medium from which a computer can load and run (boot) an operating system or utility program. The computer must have a built-in program which will load and execute a program from a boot disk meeting certain standards.
While almost all modern computers can boot from a hard drive containing the operating system and other software, they would not normally be called boot disks (because they are not removable media). CD-ROMs are the most common forms of media used, but other media, such as magnetic or paper tape drives, ZIP drives, and more recently USB flash drives can be used. The computer's BIOS must support booting from the device in question.
One can make one's own "boot disk" (typically done to prepare for when the system won't start properly).
Uses.
Boot disks are used for:
Process.
The term "boot" comes from the idea of lifting oneself by one's own bootstraps: the computer contains a tiny program (bootstrap loader) which will load and run a program found on a boot device. This program may itself be a small program designed to load a larger and more capable program, i.e., the full operating system. To enable booting without the requirement either for a mass storage device or to write to the boot medium, it is usual for the boot program to use some system RAM as a RAM disk for temporary file storage.
As an example, any computer compatible with the IBM PC is able with built-in software to load the contents of the first 512 bytes of a floppy and to execute it if it is a viable program; boot floppies have a very simple loader program in these bytes. The process is vulnerable to abuse; data floppies could have a virus written to their first sector which silently infects the host computer if switched on with the disk in the drive.
Media.
Bootable floppy disks ("boot floppies") for PCs usually contain DOS or miniature versions of Linux. The most commonly available floppy disk can hold only 1.4 MB of data in its standard format, making it impractical for loading large operating systems. The use of boot floppies is in decline, due to the availability of other higher-capacity options, such as CD-ROMs or USB flash drives.
Device selection.
A modern PC is configured to attempt to boot from various devices in a certain order. If a computer is not booting from the device desired, such as the floppy drive, the user may have to enter the BIOS Setup function by pressing a special key when the computer is first turned on (such as , , , or ), and then changing the boot order. More recent BIOSes permit the interruption of the final stage of the boot process and invoke the Boot Menu by pressing a function key (usually or ). This results in a list of bootable devices being presented, from which a selection may be made.
Modern Apple Macs will display the Boot Menu if user presses the or while the machine is starting.
Requirements.
Different operating systems use different boot disk contents. All boot disks must be compatible with the computer they are designed for.
All files must be for the same version of the operating system. Complete boot disks can be prepared in one operation by an installed operating system; details vary.


Radeon X800 series

Radeon X800 is a series of graphics cards designed by ATI Technologies Inc. introduced at the end of 2004.
History of Radeon X800.
The Radeon X800 series was designed to take the position X700 XT failed to secure, with 12 pipelines and a 256-bit RAM bus. The card surpassed the 6600GT with performance similar to that of the GeForce 6800. The new X800 XL, a similar product, was positioned to dethrone NVIDIA's GeForce 6800 GT with higher memory speeds and a full 16 pipelines to boost performance. R430 was unable to reach high clock speeds, having been designed to reduce the cost per GPU, creating a need for new top-of-the-line core. The new high-end R4x0-generation arrived with the X850 series, equipped with various core tweaks for slightly higher performance than the "R420"-based X800 series. The "R480"-based X850 line was available in 3 forms: the X850 Pro, the X850 XT, and the X850 XT Platinum Edition, and was built on the reliable high-performance 130 nanometer Low-K process.


Indy Racing 2000

Indy Racing 2000 is a racing game for the Nintendo 64 that was released in 2000. The game is based on the 1999 Indy Racing League and races a 20-car field. The game's modes of play include single race, Championship, Two player and Gold Cup. There are 9 tracks and 11 races. The Gold Cup mode lets the player race Midget cars, sprint cars, Formula cars, and Indy cars on fictional tracks (All but 1 are road courses).
Reception.
The game received "average" reviews according to the review aggregation website GameRankings.


SSSE3

Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History.
SSSE3 was first introduced with Intel processors based on the Core microarchitecture on June 26, 2006 with the "Woodcrest" Xeons.
SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it.
Functionality.
SSSE3 contains 16 new discrete instructions. Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. They include:
New instructions.
In the table below, satsw(X) (read as 'saturate to signed word') takes a signed integer X, and converts it to −32768 if it is less than −32768, to +32767 if it is greater than 32767, and leaves it unchanged otherwise. As normal for the Intel architecture, bytes are 8 bits, words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMM vector register.