Ouya

The Ouya ( ), stylized as OUYA, is an Android-based microconsole developed by Ouya Inc. Julie Uhrman founded the project in 2012, bringing in designer Yves Béhar to collaborate on its design and Muffi Ghadiali as VP of Product Management to put together the engineering team. Development was funded via Kickstarter, raising 8.5 million, becoming one of the website's highest earning projects in its history.
Units started to ship to Kickstarter backers in March 2013 and were released to the general public in June 2013. It features an exclusive Ouya store for applications and games designed specifically for the Ouya platform, of which the majority are casual games targeted at or used by a mass audience of casual gamers. Out of the box, Ouya supports media apps such as Twitch and the Kodi media center. It runs a modified version of Android Jelly Bean, with rooting being officially encouraged. The console's hardware design allows it to be easily opened up, requiring only a standard screwdriver for easy modding and possible hardware add-ons.
All systems can be used as development kits, allowing any Ouya owner to also be a developer, without the need for licensing fees. All games were initially required to have some kind of free-to-play aspect, whether that be completely free, has a free trial, or has purchasable upgrades, levels, or other in-game items. This requirement was later removed.
Despite the successful Kickstarter campaign, sales were lackluster, causing financial problems for Ouya Inc. and forcing the company to wind down the business. Its software assets were sold to Razer Inc., who announced the discontinuation of the console in July 2015. Razer continued to provide software support for existing Ouya units until June 2019, when it shut down Ouya storefront, services and accounts, making most apps on the console unusable. The Ouya has since been considered a commercial failure.
History.
Ouya was announced on July 3, 2012 as a new home video game console, led by Julie Uhrman, the chief executive officer of Santa Monica, California-based Boxer8, Inc. (later rebranded Ouya, Inc. on August 13, 2012). On July 10, Ouya started a campaign to gauge how many people were interested in the project. Boxer8 confirmed having a working prototype with in-progress software and user interface. It features an Nvidia Tegra 3 chip and a price tag of $99 ($95 for 1000 "early birds" backers of the Kickstarter campaign).
The Kickstarter fundraising goal was $950,000, with a month to reach that goal; within 8 hours it surpassed $1 million. Funding continued to increase as more models were made available at various funding levels. According to Kickstarter, in reaching its goal, Ouya holds the record for best first-day performance of any project hosted to date. Within the first 24 hours, the project attracted one backer every 5.59 seconds. Ouya became the eighth project in Kickstarter history to raise more than a million dollars and was the quickest project ever to do so. The Kickstarter campaign finished on August 9 with $8,596,475 at 904% of their goal. This made the Ouya Kickstarter the fifth-highest earning in the website's history at the time.
Ouya units for Kickstarter funders started to ship on March 28, 2013. On June 25, 2013, the Ouya was released to the public for $99.
Ouya announced the "Free the Games Fund" in July 2013 with the goal to support developers making games exclusively for their system with Ouya matching a Kickstarter campaign's pledge dollar-for-dollar if a minimum of $50,000 is raised, but only if the game will be an Ouya exclusive for six months.
In October 2013, Uhrman stated that the company planned on releasing a new iteration of the Ouya console sometime in 2014, with an improved controller, double the storage space, and better Wi-Fi. On November 23, 2013, a limited edition white Ouya with double the storage of the original and a new controller design was available for pre-order at $129.
As of January 1, 2014, the limited edition white Ouya went off sale and cannot be found on the official store, nor from any official resellers. On January 31, 2014, a new black version of the Ouya was released with double storage and new controller design.
In January 2015, Ouya received an investment of US$10 million from Alibaba with the possibility of incorporating some of Ouya technologies into Alibaba's set-top box.
In April 2015, it was revealed that Ouya was trying to sell the company because it failed to renegotiate its debt. On July 27, 2015, it was announced that Razer Inc. had acquired Ouya's employees and content library and that Ouya hardware was now discontinued. The deal does not include Ouya's hardware assets. Owners were encouraged to migrate to Razer's own Forge microconsole; Ouya's content library will be integrated into the Forge ecosystem, and "[the] Ouya brand name will live on as a standalone gaming publisher for Android TV and Android-based TV consoles." On the same day Uhrman stepped down as Ouya's CEO.
The technical team and developer relations personnel behind Ouya joined the software team of Razer, which developed its own game platform called the Forge TV. The Forge TV was discontinued in 2016.
On May 21, 2019, Razer released a statement which announced that online accounts and services would be discontinued on June 25, 2019. According to Razer, most apps will become unusable on the platform, many relying on the user accounts to work. Razer suggests that users may be able to transfer purchases to other storefront platforms like Google Play, if developers and publishers agree to such.
Hardware.
The Ouya is a cube designed to be used with a TV as the display via an HDMI connection. It ships with a single wireless controller, but it can also support multiple controllers. Games are available via digital distribution or can be side-loaded.
Specifications.
Notes:
Controller.
The Ouya controller is a typical gamepad with dual analog sticks, a directional pad, 4 face buttons (labeled O, U, Y, and A) and pairs of back bumpers and triggers. It also includes a single-touch touchpad in the center of the controller. The Ouya controller also has magnetically attached faceplates which enclose the 2 AA batteries, one on each side of the removable plates.
Alternate controllers may be used with the console (including those from the Xbox 360, PlayStation 3 and Wii) but only for compatible games.
Reception.
Pre-release.
While initial reception of the Ouya was positive, raising $3.7 million on Kickstarter in the first two days, there were a number of vocal critics who were skeptical of the ability of the fledgling company to deliver a product at all. On July 12, 2012, "PC Magazine"s Sascha Segan ran an op-ed entitled "Why Kickstarter's Ouya Looks Like a Scam" which was critical not only of the Ouya but of all Kickstarter-funded hardware projects. "Unreality Magazine" defended the Ouya, stating "A scam implies some sort of intentionally illegal deceit. [...] Tapping multiple investors from multiple sources isn't a scam, it's not even illegal, it's business."
"Engadget" reviewed the Kickstarter pre-release version of the Ouya on April 3, 2013. While praising the low cost and ease of hacking the console, it reported issues with controller buttons becoming stuck beneath the controller plating and the right analog stick snagging on the plating. It also reported a slight lag between the controller and the console and went on to say the controller was "usable, but it's far from great."
"The Verge" reported similar issues with the controller and questioned its construction quality. While they praised the hacking and openness of the console, calling it "a device with lots of potential and few true limitations", the review was mostly negative and was critical of the interface and game launch choice and stated that "Ouya isn't a viable gaming platform, or a good console, or even a nice TV interface."
Retail reception.
"Tom's Hardware" summarized early media reviews of the Ouya as "lukewarm".
"Engadget" reviewed the retail version of the Ouya, and noted a largely improved experience as compared to what they found with their pre-release unit. Improvements to the gamepad were "huge", and they found "that the UI has been cleaned up and sped up". Engadget concluded that their "latest experience with the Android-based gaming device [left them] feeling optimistic" and that the company was "taking customer feedback seriously".
"Digital Trends" called the final retail console "a device with a lot of potential built with love", and called the design a "sleek and cool-looking cube filled with gamingy goodness". The mostly positive review cited a lot of potential for the future, but was tempered by noting deficiencies in performance ("as powerful as many current smartphones"), and pointing out that the Ouya won't be able to compete with the "big three" console makers on performance, but must rely on carving out a niche in the market.
"ExtremeTech" found that Ouya "has a number of serious faults". They mentioned the sub-par controller, the connectivity issues, and games which worked flawlessly on smartphones but stuttered on the console. Also, they remarked that "there just aren’t enough worthwhile games to play".
Sales.
Market analyst NPD Group described Ouya sales in its first month as "relatively light", while several outlets noted low sales of games on the service in initial reports from developers. In April 2014, developer Maddy Thorson stated that their title "TowerFall", the Ouya's most popular game at the time, had only sold 7,000 copies for the console. The Ouya in total sold around 200,000 units.
Free the Games Fund.
In July 2013, Ouya announced the "Free the Games Fund", a scheme to help fund developers, where Ouya would match any Kickstarter campaign if a minimum target of $50,000 was reached, and provided the game remained Ouya exclusive for six months. Suspicions were raised concerning the first two games to reach the target. Commentators noticed the small number of backers each pledging a high value amount, the large number of those who had never backed a project before, as well as the use of duplicate names and avatars that included those of celebrities. This led some to suggest that the projects were artificially inflating their project's backing in order to receive extra money from Ouya. In addition, one project had a backer whose identity appeared to be taken from that of a missing person's case.
Nevertheless, Ouya rejected any suspicion regarding the backing of the projects, and planned to continue with providing funding. In September 2013, funding for one of the games that had reached its target ("Elementary, My Dear Holmes") was later suspended by Kickstarter. The developers of the other funded game, "Gridiron Thunder", threatened litigation against a commenter on the Kickstarter page, and further dismissed concerns that they would have no rights to official NFL branding, a license currently held by Electronic Arts. In the same month, another project, "Dungeons the Eye of Draconus", caused controversy by openly stating that a relative of one developer had provided substantial additional backing in order to have the project qualify for money from the Free the Games fund. The project was removed by Ouya from the Free the Games fund, resulting in the developers removing the project from Kickstarter.
Many developers criticized the fund's rules. Sophie Houlden removed her game, "Rose and Time", from the Ouya marketplace in protest. Matt Gilgenbach, who was trying to finance his game "Neverending Nightmares" with help from the fund, said, "It would kill me if due to other projects abusing the Free the Games Fund, people lost confidence in our project and what we are trying to do...While I believe in the idea of the Free the Games Fund, I think it definitely could use some reform in light of the potential avenues for abuse." Eventually, Uhrman accepted this criticism. "Developers were telling us over and over, 'You're being too idealistic, and you're being too naive.' That was the part that personally took me a while to understand." Ouya changed the fund rules, including adding a dollar-per-backer limit. Houlden put her game back on the store, and "Neverending Nightmares" qualified for funding under the new rules.
On September 18, 2013, Ouya modified the exclusivity clause of the fund. Developers would still not be able to release their software on mobile devices, video game consoles, and set-top boxes during the six-month exclusivity period, but they would be allowed to release on other personal computer systems, such as Windows, Mac OS X, and Linux, during that time.


DEL (command)


The Con (video game)

The Con, released as Gamble Con Fight in Japan, and The Con: Gamble Fight in South Korea, is a fighting video game that was developed by Japanese studio Think and Feel and published by Sony Computer Entertainment for the PlayStation Portable in 2005. The story follows the life of a con artist who fights for money.
Gameplay.
"The Con" is an innovative 3D fighting game based on an underworld where illegal fighting tournaments exist and high-stakes gambling takes center stage. During gameplay, players can train their fighter to fight solo or in a team of three in Story Mode where their ability to build up a team and implementing match-up strategy plays a huge role. Throughout gameplay, players can learn re-programmable fighting combinations based on five different brawling disciplines—Boxing, Wrestling, Kick Boxing, Tae Kwon Do and Jeet Kune Do. These five brawling disciplines are always on default character, but your custom character can choose any brawling disciplines. All brawling disciplines have moves combinations that can be acted as combo, which can be updated depending of the moves you put in a combo.
Quick Play.
There are three modes: arcade, time-attack and survival.
In this mode, there are eleven stages. The first nine are random, and the final two are always the same: Hardcase, a supposedly disgraced man as he wears a cloth which covers his mouth and has scars on his body; and Mask, a man whose fighting style is dependent on the player; if the player is a street boxer, he is a street boxer too, etc.
Plot.
A Con artist is introduced to underground fighting by Reina. He/she wins twice and then the protagonist is taught how to make money, and he/she has to do the following: Fight to win, Pull off a comeback con, start like a loser and make a comeback, and take a dive, start like a winner and then lose.
Then the protagonist confronts Reina and tells her they are done. Reina says she owns him/her. Reina is killed by the protagonist who claims no one owns him. The protagonist then recruits two other fighters and form a team. Team (name) fight to get invited to the Big Time, where the winners of the tournament get 10 million dollars. They defeat Boneyard and his team Phantom of rank D (24-2), Smoke and his team Extreme of rank C (26-2),Shaman and his team Demoish of team B (36-2), Cinder and her team Crimson of rank A (52-6) and optionally, Cornfed and his team Triumph (57-0) (it is not required to defeat team Triumph to go to the Big Time Tournament.) But when that team jumps to rank A, Smoke, whom they fought at rank C, will want to join his/her team. If the protagonist wants him, he/she is going to have to choose which fighting style Smoke is going to fight as. Yes, Smoke masters every style in the game. But at the cost of another team member. One is going home, while Smoke joins the team. If he/she says no, he leaves immediately and there is no other chance. After some fights, the old team member comes back to take his/her old place. The protagonist can choose to keep Smoke or kick Smoke out.
Once they get to the Big Time tournament, the gang talk about the protagonist, but Kuro remains confident that Shades will take care of that team. te that team fights to the finals, in the semi-finals defeating Shades and his team Collosus. But something strange happens during the finals. If the player accepted Smoke's offer, it is revealed he was infiltrating as he was never on the protagonist's side to begin with, alongside Cornfed and Kuro (they may have fought Cornfed at rank S already.) If he/she did not accept the offer, or Smoke eventually got kicked out to get the old team member back, one of the team members is killed by Smoke. Either way, that team is going to have to fight team Menace with two members against the three.
But still, they defeat team Menace and bring home that prize money, and Kuro is arrested.
Reception.
"The Con" received "mixed" reviews according to video game review aggregator Metacritic. In Japan, "Famitsu" gave it a score of two sevens and two sixes, for a total of 26 out of 40.


Dead Head Fred

 is a horror comedy action-adventure video game for the PlayStation Portable, developed by Vicious Cycle Software and published by D3 Publisher. It was released in North America on August 28, 2007 and is powered by Vicious Cycle's proprietary Vicious Engine. It features a premise that is a combination of 1940s-style noir and contemporary horror, dubbed "twisted noir" by the design team.
The game is a single-player experience whose title character, Fred Neuman, is a private investigator with the ability to switch heads. Fred has recently been murdered and decapitated, and has few memories of the events leading to his death. The plot follows Fred as he pieces together the clues of his murder and tries to get revenge on the man who killed him. Unlike many action game heroes, Fred has no conventional weapons—he relies solely on the powers available to him from the severed heads of fallen enemies.
The game received generally positive reviews, with reviewers mentioning its dark humor and noir-inspired motif as high points. It received criticism for its controls and lack of combat depth. In 2008, it won the Writers Guild of America's first-ever award for video game writing.
Dead Head Fred was later made available on PlayStation Vita.
Gameplay.
"Dead Head Fred" is a third-person action-adventure game that incorporates a variety of gameplay styles, including combat, platforming, and puzzles. The core gameplay of "Dead Head Fred" revolves around Fred's missing head and his ability to "switch" heads by defeating certain enemies, decapitating them, and collecting their heads (referred to as "headhunting"). As Fred explores the city of Hope Falls, he can collect an assortment of heads, each of which has unique abilities. Examples include the Stone Idol head, which Fred can use as a battering ram, and the Corpse head, which can be used to suck up and spit out water, gasoline, and other materials. Fred uses these heads to navigate the city of Hope Falls, and certain parts of the city are not accessible until certain heads are found. The high level of radiation in Hope Falls has led to a proliferation of grossly mutated worms, which the player can collect and use to upgrade Fred's heads and temporarily increase his fighting abilities, among other benefits. Also collectible are money and special items, which can be earned by defeating enemies or completing various side-missions. There are several minigames unrelated to the plot, such as pinball and fishing, scattered around the city.
In combat, players have several attacks at their disposal, depending on the head Fred is equipped with. These attacks include combos, head-specific counterattacks, and ranged attacks. During a counterattack, the player can complete a Quick Time Event to instantly kill an enemy by removing its head, which gives Fred "Rage" points. Rage energy builds up over time, and the player can use it to unleash powerful attacks on multiple foes. Dealing a large amount of damage to an opponent will stun them, during which time Fred can remove their head. Collected heads can be traded at "Head Shops" for a usable version.
There are several types of environmental puzzles that the player has to solve in order to progress through the game. Each one requires a specific head—the Bone head gives Fred sharp claws which allow him to climb on the sides of buildings, while the Shrunken head decreases his size dramatically and lets him navigate platforming levels, such as a saw mill. There is also a mannequin head that Fred must use to socialize with the residents of Hope Falls, because they are terrified of his other heads. There are nine available heads, seven of which are suitable for combat.
Plot.
Setting.
"Dead Head Fred" takes place in Hope Falls, New Jersey, a once-prosperous area based on American cities in the 1940s. The city has steadily fallen from grace since a business mogul named Ulysses Pitt began accumulating power. Pitt has a background of petty crime, and there are allegations that he was somehow responsible for the disappearance of Vinni Rossini, an influential Hope Falls businessman. Pitt's new "Nukular Plant" has recently finished construction and has caused a high level of radiation in the city, leading to strange phenomena like mutated wildlife and undead monsters.
Hope Falls is composed of several areas. The first that Fred has access to is Dr. Steiner's castle, the ancestral home of the Steiner family where Fred has been resurrected. Outside of the castle is a large cemetery that borders the forested area of Creepy Hollow. In Hope Falls proper are the urban areas of Downtown, Uptown, Old Hope Falls and Zombietown. Downtown is the home of Pitt's headquarters, and Fred's office is found in Old Hope Falls. Zombietown, as its name suggests, is overrun with zombies and most of its residents have fled the neighborhood or barricaded themselves in their homes. Two other rural areas border the city: Freak Farms, where Fred owns a small cabin, and the Boonies, a highly irradiated area where the Nukular Reactor has been built. Each area contains several teleporters in the form of sewer manholes, which Fred can use to quickly move from one area of Hope Falls to another.
Characters.
The protagonist of "Dead Head Fred" is Fred Neuman (voiced by John C. McGinley), a private detective. Fred is the only playable character, but since each head gives him a different set of animations, he could be considered nine separate characters. As he does not have a proper face, Fred's mood is portrayed by the tone of his voice and by face-like expressions formed by his eyes and frontal lobes. Fred has a wisecracking, sarcastic personality and occasionally breaks the fourth wall, such as heckling the player when he dies. Ulysses Pitt (Jon Polito), the game's primary antagonist, is a small-time hoodlum turned racketeer. Pitt employs many henchmen throughout Hope Falls, the most prominent of which is his lieutenant Lefty, whose right leg has been amputated and replaced with a tommygun. Fred makes several allies throughout the game, including Dr. Steiner, who resurrected him, his girlfriend Jeanne Rossini (Kari Wahlgren), and his former partner Benny Salazar. Fred's enemies are generally employees of Pitt, like the skeletal "bone thugs", or creatures created by Hope Falls' radiation, like zombies and animated scarecrows.
Story.
The game begins with Fred waking up in the castle of a Dr. Freidrich Steiner, an employee of Ulysses Pitt. Fred soon learns that he has been murdered and subsequently resurrected, and his head is missing. In its place is a liquid-filled jar that contains his brain and eyes. Steiner explains that Fred is a private detective who had been investigating Pitt, but Pitt had discovered that Fred was on to him and had him murdered. Many of Fred's memories are missing as a result of the trauma to his brain, and before Steiner can explain further, Pitt and several of his henchmen arrive. As Fred hides in Steiner's lab, Pitt's thugs apprehend Steiner and announce that he is to be taken to the Horseman, a minion of Pitt's who resides in Creepy Hollow.
Fred leaves Steiner's castle and meets a blue-skinned hunchback in the cemetery outside. The hunchback introduces himself as Sam Spade, a gravedigger and "head merchant" who can help Fred by providing him with quality interchangeable heads. Fred continues to Creepy Hollow, where he defeats the Horseman and rescues Dr. Steiner. Steiner, however, has little information regarding Fred's investigation and suggests that he question the residents of Hope Falls to learn more about his demise. Fred begins exploring Hope Falls, meeting many strange personalities along the way. He reconnects with his old girlfriend Jeanne, who is the daughter of a prominent Hope Falls citizen, Vinni Rossini. Fred learns that Mr. Rossini had been reported missing by Jeanne, and Jeanne had subsequently hired Fred to find him. Fred had eventually followed the trail to Pitt, who had bribed Fred's partner, Benny Salazar, into betraying him. Fred was promptly caught by Pitt's henchmen and shot to death by his right-hand man, Lefty.
Armed with the knowledge of his death and the events leading up to it, Fred continues his investigation and recovers a videotape of Vinni Rossini's murder that incriminates Pitt. Pitt learns that Fred is still "alive" and kidnaps Jeanne to use as leverage against him. Fred confronts the mobster at his headquarters after shutting down the centerpiece of his criminal enterprise, the Pitt Nukular Plant, and defeating Lefty. Lefty, however, was exposed to nuclear waste during the fight and subsequently mutated into a huge beast who comes to Pitt's aid in the game's final battle. Fred ultimately defeats both Pitt and Lefty atop the Pitt Building. Pitt is killed during the battle, but Lefty manages to escape and retreats to the remains of the Nukular Plant. After the battle, Fred's head, which, along with Jeanne, had been held hostage by Pitt, is shown tumbling into an open manhole near the Pitt Building, unbeknownst to Fred. The final scene of the game shows Fred and Jeanne having dinner at a restaurant to celebrate, with Fred lamenting the loss of his head.
Development.
Geo.
"Dead Head Fred" uses the Vicious Engine, a game engine created and maintained by game design company Vicious Cycle Software. Considered "middleware" in the video game industry, the engine was designed as a simple set of creation tools that could be used across multiple consoles. The game was originally conceived as a platform game based on the character "Geo." Vicious Cycle's president, Eric Peterson, and some of his staff developed a conceptual world called "Prime" where Geo lived. Geo had the ability to switch his head between several different shapes (a cube, sphere, cylinder, and pyramid) that would help him solve puzzles, fight, and move around Prime in his quest to stop the evil King Rhombus, who was trying to destroy Prime. Each of Geo's shaped heads had unique properties that gave him different abilities—the sphere head allowed him to roll around very quickly, for example.
The Geo concept was described by the development team as similar to other platform games like "Rayman" or "Spyro", and skewed towards a younger audience. When the concept was complete, the development team presented it to several publishers, who stated that they liked the idea but its geometry-based core too strongly resembled "edutainment", and that they were interested in developing a more edgy, adult premise. The Nintendo GameCube had been an early choice for hosting the game before the PSP was chosen.
Noir setting.
Vicious Cycle went back to the drawing board and produced a new concept that they felt was darker and better suited to an older audience. The "head-switching" game mechanic had been praised by the potential publishers and was kept, but this time the cartoonish, childlike Geo was replaced by an angry, vengeful private detective named Fred Neuman. The world of Prime was replaced with the bleak, film noir-esque city of Hope Falls, where Fred would seek revenge against those who had wronged him. Vicious Cycle presented the new project to Sony, who promptly approved the game for the PSP, despite it not having secured a publisher. Shortly afterwards, the project was picked up by D3Publisher.
Vicious Cycle then submitted the concept to art company Massive Black Studios to develop initial character sketches. Massive Black's artists were allowed to use their imagination while developing Fred, but the one stipulation Vicious Cycle made from the beginning was Fred's head—the developers wanted it to be a liquid-filled jar with the detective's brain and eyes floating around inside. Massive Black came up with several different versions of Fred, including some with guns, which lead designer Adam Cogan had already decided the game would not include. After receiving the sketches, Vicious Cycle chose several that portrayed Fred with a squat, childlike appearance that retained some of the youthful focus of the scrapped Geo project. The publisher, D3, decided to present all of the concept art to a test group. To the developers' surprise, the test group was much more interested in a darker, more intimidating portrayal of Fred than the cartoonish, playful look they had chosen. The developers decided to flesh out the concept and took the chosen sketches back to Massive Black. This time the art came back darker, with similarities to "Dirty Harry" and "The Matrix" and "The Evil Dead", and a Norman Rockwell-inspired look that would influence the game's art style towards a more violent theme.
Further testing.
D3 provided the development team with more focus groups, and as a result, the game slowly incorporated more combat and less platforming and puzzles. Fred's combat capabilities were revamped to give him more attacks, counterattacks and combinations. D3 also gave Vicious Cycle more time to develop the game, with the hope of receiving better reviews and potentially turning "Dead Head Fred" into a franchise. The delay pushed back the game's release from January to August 2007. D3Publisher bought Vicious Cycle two months before the game's release, but the company's headquarters remained in North Carolina and the staff was retained.
Audio.
Soundtrack.
The music of "Dead Head Fred" was composed by Rod Abernethy and Jason Graves and recorded at Abernethy's studio, Rednote Audio. Abernethy and Graves had worked on previous games by Vicious Cycle, like "Curious George". The composers were interested in developing a sound for "Dead Head Fred" that was retro-futuristic, and borrowed from other death-themed pieces like "Stubbs the Zombie" and "Beetlejuice". The development team did not have any substantial ideas for the game's music beyond the theme and mood of Hope Falls, giving the composers free rein on the soundtrack's direction.
Voice work.
A crucial area of development was the formation of the game's mood, theme, and story to give it a dark, yet humorous quality. Hiring a Hollywood screenwriter to create the script was proposed, but ultimately Vicious Cycle designer Dave Ellis was given the task of writing the game's cutscenes and voiceover script, while Cogan focused on the in-game dialog. Ellis referred to several noir films for inspiration, especially "Miller's Crossing" and "Who Framed Roger Rabbit" During this time, Eric Peterson cast several voice actors, including John C. McGinley from the TV show "Scrubs" and Jon Polito from the aforementioned "Miller's Crossing". McGinley was cast as Fred because of his "Scrubs" character's sarcasm and wit, while Polito was cast in the role of mob boss Ulysses Pitt, which was very similar to his role of Johnny Caspar in "Miller's Crossing".
The development team then set about recording the game's dialog, which proved to be challenging because of Vicious Cycle's location on the East Coast. All of the recordings were done over the phone at a studio in Hollywood. Despite this, and the fact that Fred alone had over 1000 lines of in-game dialog, the recording went smoothly, with the exception of one unidentified actor who walked out in the middle of a session. The original script had only one instance of the word "fuck", but several recording sessions with McGinley resulted in a great deal of colorful improvisation. The design team liked the recordings and the script was modified to permit McGinley and other actors to curse more. McGinley focused on portraying Fred as "pissed off" and "having a chip on his shoulder" because his head was missing.
Promotion and release.
"Dead Head Fred" was first announced at the Electronics Entertainment Expo (E3) video game convention in May 2006, where a trailer was shown to the public. Following this, little was heard about the game until Cogan started a developer diary on Vicious Cycle's website in March 2007. Three diary entries were written by Cogan and Ellis, which provided details about the game's pre-production conceptualization and voice work. In May 2007, D3 announced that John C. McGinley would be voicing Fred, and the next month the company issued a press release stating that the game was finished and ready for mass production. However, the game was delayed, allowing D3 Publisher to show it at E3 2007. It was eventually released on August 28, 2007 in North America after nearly two years of development. It was released on October 26 in Europe, November 2 in Australia, and March 19, 2008 in Japan. In December 2007, D3 reduced the price of the game, and in October 2008 it was made available for download on Sony's PlayStation Network. The soundtrack was released on iTunes by Lakeshore Records on September 18, 2007.
Future.
"Dead Head Fred" was designed specifically for the PSP, and Vicious Cycle intended it to be their "flagship" title for the system. However, the game's designers hinted that the game could potentially be ported to the PlayStation Network or Xbox Live Arcade with a few months' work. As of March 2009, D3Publisher announced a sequel, but the designers stated that subsequent titles were discussed during the game's development. John C. McGinley has expressed interest in reprising Fred. Namco Bandai Games (the parent of D3) were impressed with the game and wanted to publish the sequel because they "wanted" to test out Vicious Cycle's gameplay on the PSP.
Unfortunately, Vicious Cycle was shut down in 2016 and its publisher D3 Publisher of America has shifted its focus to mobile gaming a year before (changing its name to D3 GO!), making the future of the game unknown.
Reception.
"Dead Head Fred" received generally favorable reviews from critics. The game's writing and dialogue were considered the main strengths of the game, with GameSpy's reviewer stating that "In the vast sea of PSP titles, "Dead Head Fred" stands 'head and shoulders' above the rest." IGN said "The tale of revenge in a dark world is twisted [and] unapologetically humorous". Other publications were not as impressed, however, with one reviewer stating "...the overused profanity just makes it feel like it's been designed by teenagers desperately trying to be edgy." The game's supernatural themes elicited comparisons to "The Darkness" and "Grim Fandango". GamesRadar included it in their list of the 100 most overlooked games of its generation. Editor Jason Fanelli felt that PSP games often lacked creativity and that "Dead Head Fred" was the exception.
Many reviewers were pleased with the game's premise and setting, variously describing it as "weird", "wacky" and "silly". Hope Falls, especially the area of Creepy Hollow, was compared to the work of Tim Burton. "Dead Head Fred's" graphics were warmly received, with GameSpy noting "The game looks simply phenomenal on the PSP screen." "Pocket Gamer" UK said "graphically the game won't blow your head off but it is undeniably stylish." "Pocket Gamer" also felt that the game's level design, with its emphasis on changing heads to solve environmental puzzles, made up for the "mediocre combat system". The character design was praised; GameSpy said "Fred is one of the most interesting and entertaining characters to ever hit gaming," and GameZone said "Fred’s freakish form is like looking at a car crash … you really don’t want to stare but you just can’t help it."
The voice acting, in particular John C. McGinley's portrayal of Fred, was widely praised, as was the rest of the game's audio. GameZone's Natalie Romano said "There’s also some great music in the game and the sound effects are...wonderfully detailed".
The focal point of reviewers' criticism was "Dead Head Fred's" gameplay, specifically the combat. It was generally considered tedious and repetitive. Australia's PAL Gaming Network described the combat as "one of the poorest elements of the game", and "Game Informer" called the combat mechanics "awful". The performance of the camera was also criticized, with IGN noting "Considering that the camera will sometimes choose some horrible angles for you in battle or during puzzles, it's annoying to have to fight it as well as mutants that want you dead." GameZone said "I just wish the camera wouldn’t be such a hindrance sometimes." Reviewers were also unhappy with "Dead Head Fred's" loading times; Eurogamer considered them "excessively high", and IGN said "The only downside that crops up when it comes to the visuals are the continual loading times on just about every single area."
Awards.
"Dead Head Fred" was nominated for several awards, including the Writers Guild of America's first award for video game writing, which it won. During E3 2007, the game was nominated for the Best of E3 2007: Best Handheld Game award by the Game Critics Awards, a group of prominent media journalists. "Dead Head Fred" lost to ' for the Nintendo DS, but was notable for being the only new intellectual property nominated in the handheld category. The audio was nominated for two awards at the Game Audio Network Guild's 6th annual ceremony, Best Soundtrack of the Year and Best Handheld Audio. "Dead Head Fred" lost to "BioShock" and ', respectively.


Epson Equity

The Epson Equity series of IBM Compatible Personal Computers was manufactured from 1985 until the early '90s by Epson Inc. Epson was well known for its dot matrix printers at the time and the Equity series represents their entry into the growing PC compatible market. The Equity I was the first system introduced, equipped with an Intel 8088 CPU and one or two 5.25" floppy disk drives.
The original Equity was a no-frills offering. It ran at the PC's standard 4.77 MHz clock rate, came with 256 KB RAM, expansion above 512 KB required an expansion board, displayed CGA video, had few available expansion slots, only two half-height drive bays, and lacked a socket for an 8087 math chip. Subsequent versions, the Equity I+ and Apex 100, upped the clock rate to 10 Mhz, the standard RAM to 640 KB, supported 3.5 inch floppy drives and hard disks, sported an 8087 socket, and had display circuitry for the monochrome Hercules Graphics Adapter. Epson bundled some utility programs that offered decent turnkey functionality for novice users. The Equity was a reliable and compatible design for half the price of a similarly-configured IBM PC. Epson often promoted sales by bundling one of their printers with it at cost. The Equity I sold well enough to warrant the furtherance of the Equity line with the follow-on Equity II, Equity III, and others based on the i386SX.


Peripheral Component Interconnect

Peripheral Component Interconnect (PCI) is a local computer bus for attaching hardware devices in a computer and is part of the PCI Local Bus standard. The PCI bus supports the functions found on a processor bus but in a standardized format that is independent of any given processor's native bus. Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in the processor's address space. It is a parallel bus, synchronous to a single bus clock.
Attached devices can take either the form of an integrated circuit fitted onto the motherboard (called a "planar device" in the PCI specification) or an expansion card that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatibles, where it displaced the combination of several slow Industry Standard Architecture (ISA) slots and one fast VESA Local Bus (VLB) slot as the bus configuration. It has subsequently been adopted for other computer types. Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as Universal Serial Bus (USB) or serial, TV tuner cards and hard disk drive host adapters. PCI video cards replaced ISA and VLB cards until rising bandwidth needs outgrew the abilities of PCI. The preferred interface for video cards then became Accelerated Graphics Port (AGP), a superset of PCI, before giving way to PCI Express.
The first version of PCI found in retail desktop computers was a 32-bit bus using a 33 MHz bus clock and 5 V signalling, although the PCI 1.0 standard provided for a 64-bit variant as well. These have one locating notch in the card. Version 2.0 of the PCI standard introduced 3.3 V slots, physically distinguished by a flipped physical connector to prevent accidental insertion of 5 V cards. Universal cards, which can operate on either voltage, have two notches. Version 2.1 of the PCI standard introduced optional 66 MHz operation. A server-oriented variant of PCI, PCI Extended (PCI-X) operated at frequencies up to 133 MHz for PCI-X 1.0 and up to 533 MHz for PCI-X 2.0. An internal connector for laptop cards, called Mini PCI, was introduced in version 2.2 of the PCI specification. The PCI bus was also adopted for an external laptop connector standard the CardBus. The first PCI specification was developed by Intel, but subsequent development of the standard became the responsibility of the "PCI Special Interest Group" (PCI-SIG).
PCI and PCI-X sometimes are referred to as either "Parallel PCI" or "Conventional PCI" to distinguish them technologically from their more recent successor PCI Express, which adopted a serial, lane-based architecture. PCI's heyday in the desktop computer market was approximately 1995 to 2005. PCI and PCI-X have become obsolete for most purposes; however in 2020 they are still common on modern desktops for the purposes of backward compatibility and the low relative cost to produce. Another common modern application of parallel PCI is in industrial PCs, where many specialized expansion cards, used here, never transitioned to PCI Express, just as with some ISA cards. Many kinds of devices formerly available on PCI expansion cards are now commonly integrated onto motherboards or available in USB and PCI Express versions.
History.
Work on PCI began at the Intel Architecture Labs (IAL, also Architecture Development Lab) . A team of primarily IAL engineers defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations.
PCI was immediately put to use in servers, replacing Micro Channel architecture (MCA) and Extended Industry Standard Architecture (EISA) as the server expansion bus of choice. In mainstream PCs, PCI was slower to replace VLB, and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996, VLB was all but extinct, and manufacturers had adopted PCI even for Intel 80486 (486) computers. EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus) in mid-1995, and the consumer Performa product line (replacing LC Processor Direct Slot (PDS)) in mid-1996.
Outside the server market, the 64-bit version of plain PCI remained rare in practice though, although it was used for example by all (post-iMac) G3 and G4 Power Macintosh computers.
Later revisions of PCI added new features and performance improvements, including a 66 MHz 3.3 V standard and 133 MHz PCI-X, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards. These revisions were used on server hardware but consumer PC hardware remained nearly all 32-bit, 33 MHz and 5 volt.
The PCI-SIG introduced the serial PCI Express in . Since then, motherboard manufacturers have included progressively fewer PCI slots in favor of the new standard. Many new motherboards do not provide PCI slots at all, as of late 2013.
Auto configuration.
PCI provides separate memory and memory-mapped I/O port address spaces for the x86 processor family, 64 and 32 bits, respectively. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or input/output (I/O) port space via its configuration space registers.
In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is.
The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.
Devices may have an on-board read-only memory (ROM) containing executable code for x86 or PA-RISC processors, an Open Firmware driver, or an Option ROM. These are typically needed for devices used during system startup, before device drivers are loaded by the operating system.
In addition, there are "PCI Latency Timers" that are a mechanism for "PCI Bus-Mastering" devices to share the PCI bus fairly. "Fair" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done. Note, this does not apply to PCI Express.
Interrupts.
Devices are required to follow a protocol so that the interrupt lines can be shared. The PCI bus includes four interrupt lines, all of which are available to each device. However, they are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that. Single-function devices use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts.
The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent. Platform-specific Basic Input/Output System (BIOS) code is meant to know this, and set the "interrupt line" field in each device's configuration space indicating which IRQ it is connected to.
PCI interrupt lines are level-triggered. This was chosen over edge-triggering to gain an advantage when servicing a shared interrupt line, and for robustness: edge triggered interrupts are easy to miss.
Later revisions of the PCI specification add support for message-signaled interrupts. In this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band, it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines.
PCI Express does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively.
Conventional hardware specifications.
These specifications represent the most common version of PCI used in normal PCs:
The PCI specification also provides options for 3.3 V signaling, 64-bit bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.
The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.
Card voltage and keying.
Typical PCI cards have either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.47 mm from the backplate. This allows cards to be fitted only into slots with a voltage they support. "Universal cards" accepting either voltage have both key notches.
Connector pinout.
The PCI connector is defined as having 62 contacts on each side of the edge connector, but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side. Side A refers to the 'solder side' and side B refers to the 'component side': if the card is held with the connector pointing down, a view of side A will have the backplate on the right, whereas a view of side B will have the backplate on the left. The pinout of B and A sides are as follows, looking down into the motherboard connector (pins A1 and B1 are closest to backplate).
64-bit PCI extends this by an additional 32 contacts on each side which provide AD[63:32], C/BE[7:4]#, the PAR64 parity signal, and a number of power and ground pins.
Most lines are connected to each slot in parallel. The exceptions are:
Notes:
Mixing of 32-bit and 64-bit PCI cards in different width slots.
Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus clock rate will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology. For example, when a PCI 2.3, 66-MHz peripheral is installed into a PCI-X bus capable of 133 MHz, the entire bus backplane will be limited to 66 MHz. To get around this limitation, many motherboards have two or more PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals.
Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of performance. An example of this is the Adaptec 29160 64-bit SCSI interface card. However, some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.
Installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging. This requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector.
Physical dimensions.
PCI brackets heights:
PCI Card lengths (Standard Bracket & 3.3 V):
PCI Card lengths (Low Profile Bracket & 3.3 V):
Mini PCI.
Mini PCI was added to PCI version 2.2 for use in laptops; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for bus mastering and DMA. The standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts. There is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors. This limits the kinds of functions a Mini PCI card can perform.
Many Mini PCI devices were developed such as Wi-Fi, Fast Ethernet, Bluetooth, modems (often Winmodems), sound cards, cryptographic accelerators, SCSI, IDE–ATA, SATA controllers and combination cards. Mini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI "converters". Mini PCI has been superseded by the much narrower PCI Express Mini Card
Technical details of Mini PCI.
Mini PCI cards have a 2 W maximum power consumption, which limits the functionality that can be implemented in this form factor. They also are required to support the CLKRUN# PCI signal used to start and stop the PCI clock for power management purposes.
There are three card form factors: Type I, Type II, and Type III cards. The card connector used for each type include: Type I and II use a 100-pin stacking connector, while Type III uses a 124-pin edge connector, i.e. the connector for Types I and II differs from that for Type III, where the connector is on the edge of a card, like with a SO-DIMM. The additional 24 pins provide the extra signals required to route I/O back through the system connector (audio, AC-Link, LAN, phone-line interface). Type II cards have RJ11 and RJ45 mounted connectors. These cards must be located at the edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access.
Mini PCI is distinct from 144-pin Micro PCI.
PCI bus transactions.
PCI bus traffic consists of a series of PCI bus transactions. Each transaction consists of an "address phase" followed by one or more "data phases". The direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction. Either party may pause or halt the data phases at any point. (One common example is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)
Any PCI device may initiate a transaction. First, it must request permission from a PCI bus arbiter on the motherboard. The arbiter grants permission to one of the requesting devices. The initiator begins the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for a target to respond. All other devices examine this address and one of them responds a few cycles later.
64-bit addressing is done using a two-stage address phase. The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code. Devices which do not support 64-bit addressing can simply not respond to that command code. The next cycle, the initiator transmits the high 32 address bits, plus the real command code. The transaction operates identically from that point on. To ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.
While the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which 8-bit bytes are to be considered significant. In particular, a write must affect only the enabled bytes in the target PCI device. They are of little importance for memory reads, but I/O reads might have side effects. The PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.
PCI address spaces.
PCI has three address spaces: memory, I/O address, and configuration.
Memory addresses are 32 bits (optionally 64 bits) in size, support caching and can be burst transactions.
I/O addresses are for compatibility with the Intel x86 architecture's I/O port address space. Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.
Finally, PCI configuration space provides access to 256 bytes of special configuration registers per PCI device. Each PCI slot gets its own configuration space address range. The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators. When a computer is first turned on, all PCI devices respond only to their configuration space accesses. The computer's BIOS scans for devices and assigns Memory and I/O address ranges to them.
If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation. In case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case. PCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.
PCI command codes.
There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target). PCI targets must examine the command code as well as the address and not respond to address phases which specify an unsupported command code.
The commands that refer to cache lines depend on the PCI configuration space cache line size register being set up properly; they may not be used until that has been done.
PCI bus latency.
Soon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause buffer underrun or overrun in other devices. Recommendations on the timing of individual phases in Revision 2.0 were made mandatory in revision 2.1:
Additionally, as of revision 2.1, all initiators capable of bursting more than two data phases must implement a programmable latency timer. The timer starts counting clock cycles when a transaction starts (initiator asserts FRAME#). If the timer has expired "and" the arbiter has removed GNT#, then the initiator must terminate the transaction at the next legal opportunity. This is usually the next data phase, but Memory Write and Invalidate transactions must continue to the end of the cache line.
Delayed transactions.
Devices unable to meet those timing restrictions must use a combination of posted writes (for memory writes) and delayed transactions (for other writes and all reads). In a delayed transaction, the target records the transaction (including the write data) internally and aborts (asserts STOP# rather than TRDY#) the first data phase. The initiator "must" retry exactly the same transaction later. In the interim, the target internally performs the transaction, and waits for the retried transaction. When the retried transaction is seen, the buffered result is delivered.
A device may be the target of other transactions while completing one delayed transaction; it must remember the transaction type, address, byte selects and (if a write) data value, and only complete the correct transaction.
If the target has a limit on the number of delayed transactions that it can record internally (simple targets may impose a limit of 1), it will force those transactions to retry without recording them. They will be dealt with when the current delayed transaction is completed. If two initiators attempt the same transaction, a delayed transaction begun by one may have its result delivered to the other; this is harmless.
A target abandons a delayed transaction when a retry succeeds in delivering the buffered result, the bus is reset, or when 215=32768 clock cycles (approximately 1 ms) elapse without seeing a retry. The latter should never happen in normal operation, but it prevents a deadlock of the whole bus if one initiator is reset or malfunctions.
PCI bus bridges.
The PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required. Although PCI tends not to use many bus bridges, PCI Express systems use many PCI-to-PCI bridge called "PCI Express Root Port"; each PCI Express slot appears to be a separate bus, connected by a bridge to the others. The PCI host bridge (usually northbridge in x86 platforms) interconnect between CPU, main memory and PCI bus.
Posted writes.
Generally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready. One notable exception occurs in the case of memory writes. Here, the bridge may record the write data internally (if it has room) and signal completion of the write before the forwarded write has completed. Or, indeed, before it has begun. Such "sent but not yet arrived" writes are referred to as "posted writes", by analogy with a postal mail message. Although they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.
Combining, merging, and collapsing.
The PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations. This can improve the efficiency of the PCI bus.
PCI bus signals.
PCI bus transactions are controlled by five main control signals, two driven by the initiator of a transaction (FRAME# and IRDY#), and three driven by the target (DEVSEL#, TRDY#, and STOP#). There are two additional arbitration signals (REQ# and GNT#) which are used to obtain permission to initiate a transaction. All are active-low, meaning that the active or "asserted" state is a low voltage. Pull-up resistors on the motherboard ensure they will remain high (inactive or "deasserted") if not driven by any device, but the PCI bus does not depend on the resistors to "change" the signal level; all devices drive the signals high for one cycle before ceasing to drive the signals.
Signal timing.
All PCI bus signals are sampled on the rising edge of the clock. Signals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.
The PCI bus requires that every time the device driving a PCI bus signal changes, one "turnaround cycle" must elapse between the time the one device stops driving the signal and the other device starts. Without this, there might be a period when both devices were driving the signal, which would interfere with bus operation.
The combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners. The PCI bus protocol is designed so this is rarely a limitation; only in a few special cases (notably fast back-to-back transactions) is it necessary to insert additional delay to meet this requirement.
Arbitration.
Any device on a PCI bus that is capable of acting as a bus master may initiate a transaction with any other device. To ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT#, from an arbiter located on the motherboard. Each device has a separate request line REQ# that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no current requests.
The arbiter may remove GNT# at any time. A device which loses GNT# may complete its current transaction, but may not start one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it begins.
The arbiter may also provide GNT# at any time, including during another master's transaction. During a transaction, either FRAME# or IRDY# or both are asserted; when both are deasserted, the bus is idle. A device may initiate a transaction at any time that GNT# is asserted and the bus is idle.
Address phase.
A PCI bus transaction begins with an "address phase". The initiator, seeing that it has GNT# and the bus is idle, drives the target address onto the AD[31:0] lines, the associated command (e.g. memory read, or I/O write) on the C/BE[3:0]# lines, and pulls FRAME# low.
Each other device examines the address and command and decides whether to respond as the target by asserting DEVSEL#. A device must respond by asserting DEVSEL# within 3 cycles. Devices which promise to respond within 1 or 2 cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively. (Actually, the time to respond is 2.5 cycles, since PCI devices must transmit all signals half a cycle early so that they can be received three cycles later.)
Note that a device must latch the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL# response. The additional time is available only for interpreting the address and command after it is captured.
On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is allowed for some address ranges. This is commonly used by an ISA bus bridge for addresses within its range (24 bits for memory and 16 bits for I/O).
On the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME#. This is known as "master abort termination" and it is customary for PCI bus bridges to return all-ones data (0xFFFFFFFF) in this case. PCI devices therefore are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.
Address phase timing.
On the rising edge of clock 0, the initiator observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the rising edge of clock 1. Targets latch the address and begin decoding it. They may respond with DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow). Subtractive decode devices, seeing no other response by clock 4, may respond on clock 5. If the master does not see a response by clock 5, it will terminate the transaction and remove FRAME# on clock 6.
TRDY# and STOP# are deasserted (high) during the address phase. The initiator may assert IRDY# as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.
Dual-cycle address.
To allow 64-bit addressing, a master will present the address over two consecutive cycles. First, it sends the low-order address bits with a special "dual-cycle address" command on the C/BE[3:0]#. On the following cycle, it sends the high-order address bits and the actual command. Dual-address cycles are forbidden if the high-order address bits are zero, so devices which do not support 64-bit addressing can simply not respond to dual cycle commands.
Configuration access.
Addresses for PCI configuration space access are decoded specially. For these, the low-order address lines specify the offset of the desired PCI configuration register, and the high-order address lines are ignored. Instead, an additional address signal, the IDSEL input, must be high before a device may assert DEVSEL#. Each slot connects a different high-order address line to the IDSEL pin, and is selected using one-hot encoding on the upper address lines.
Data phases.
After the address phase (specifically, beginning with the cycle that DEVSEL# goes low) comes a burst of one or more "data phases". In all cases, the initiator drives active-low byte select signals on the C/BE[3:0]# lines, but the data on the AD[31:0] may be driven by the initiator (in case of writes) or target (in case of reads).
During data phases, the C/BE[3:0]# lines are interpreted as active-low "byte enables". In case of a write, the asserted signals indicate which of the four bytes on the AD bus are to be written to the addressed location. In the case of a read, they indicate which bytes the initiator is interested in. For reads, it is always legal to ignore the byte enable signals and simply return all 32 bits; cacheable memory resources are required to always return 32 valid bits. The byte enables are mainly useful for I/O space accesses where reads have side effects.
A data phase with all four C/BE# lines deasserted is explicitly permitted by the PCI standard, and must have no effect on the target other than to advance the address in the burst access in progress.
The data phase continues until both parties are ready to complete the transfer and continue to the next data phase. The initiator asserts IRDY# ("initiator ready") when it no longer needs to wait, while the target asserts TRDY# ("target ready"). Whichever side is providing the data must drive it on the AD bus before asserting its ready signal.
Once one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase. The data recipient must latch the AD bus each cycle until it sees both IRDY# and TRDY# asserted, which marks the end of the current data phase and indicates that the just-latched data is the word to be transferred.
To maintain full burst speed, the data sender then has half a clock cycle after seeing both IRDY# and TRDY# asserted to drive the next word onto the AD bus.
This continues the address cycle illustrated above, assuming a single address cycle with medium DEVSEL, so the target responds in time for clock 3.
However, at that time, neither side is ready to transfer data. For clock 4, the initiator is ready, but the target is not. On clock 5, both are ready, and a data transfer takes place (as indicated by the vertical lines). For clock 6, the target is ready to transfer, but the initiator is not. On clock 7, the initiator becomes ready, and data is transferred. For clocks 8 and 9, both sides remain ready to transfer data, and data is transferred at the maximum possible rate (32 bits per clock cycle).
In case of a read, clock 2 is reserved for turning around the AD bus, so the target is not permitted to drive data on the bus even if it is capable of fast DEVSEL.
Fast DEVSEL# on reads.
A target that supports fast DEVSEL could in theory begin responding to a read the cycle after the address is presented. This cycle is, however, reserved for AD bus turnaround. Thus, a target may not drive the AD bus (and thus may not assert TRDY#) on the second cycle of a transaction. Note that most targets will not be this fast and will not need any special logic to enforce this condition.
Ending transactions.
Either side may request that a burst end after the current data phase. Simple PCI devices that do not support multi-word bursts will always request this immediately. Even devices that do support bursts will have some limit on the maximum length they can support, such as the end of their addressable memory.
Initiator burst termination.
The initiator can mark any data phase as the final one in a transaction by deasserting FRAME# at the same time as it asserts IRDY#. The cycle after the target asserts TRDY#, the final data transfer is complete, both sides deassert their respective RDY# signals, and the bus is idle again. The master may not deassert FRAME# before asserting IRDY#, nor may it deassert FRAME# while waiting, with IRDY# asserted, for the target to assert TRDY#.
The only minor exception is a "master abort termination", when no target responds with DEVSEL#. Obviously, it is pointless to wait for TRDY# in such a case. However, even in this case, the master must assert IRDY# for at least one cycle after deasserting FRAME#. (Commonly, a master will assert IRDY# before receiving DEVSEL#, so it must simply hold IRDY# asserted for one cycle longer.) This is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.
Target burst termination.
The target requests the initiator end a burst by asserting STOP#. The initiator will then end the transaction by deasserting FRAME# at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction. There are several ways for the target to do this:
There will always be at least one more cycle after a target-initiated disconnection, to allow the master to deassert FRAME#. There are two sub-cases, which take the same amount of time, but one requires an additional data phase:
If the initiator ends the burst at the same time as the target requests disconnection, there is no additional bus cycle.
Burst addressing.
For memory space accesses, the words in a burst may be accessed in several orders. The unnecessary low-order address bits AD[1:0] are used to convey the initiator's requested order. A target which does not support a particular order must terminate the burst after the first word. Some of these orders depend on the cache line size, which is configurable on all PCI devices.
If the starting offset within the cache line is zero, all of these modes reduce to the same order.
Cache line toggle and cache line wrap modes are two forms of critical-word-first cache line fetching. Toggle mode XORs the supplied address with an incrementing counter. This is the native order for Intel 486 and Pentium processors. It has the advantage that it is not necessary to know the cache line size to implement it.
PCI version 2.1 obsoleted toggle mode and added the cache line wrap mode, where fetching proceeds linearly, wrapping around at the end of each cache line. When one cache line is completely fetched, fetching jumps to the starting offset in the next cache line.
Note that most PCI devices only support a limited range of typical cache line sizes; if the cache line size is programmed to an unexpected value, they force single-word access.
PCI also supports burst access to I/O and configuration space, but only linear mode is supported. (This is rarely used, and may be buggy in some devices; they may not support it, but not properly force single-word access either.)
Transaction examples.
This is the highest-possible speed four-word write burst, terminated by the master:
On clock edge 1, the initiator starts a transaction by driving an address, command, and asserting FRAME# The other signals are idle (indicated by ^^^), pulled high by the motherboard's pull-up resistors. That might be their turnaround cycle. On cycle 2, the target asserts both DEVSEL# and TRDY#. As the initiator is also ready, a data transfer occurs. This repeats for three more cycles, but before the last one (clock edge 5), the master deasserts FRAME#, indicating that this is the end. On clock edge 6, the AD bus and FRAME# are undriven (turnaround cycle) and the other control lines are driven high for 1 cycle. On clock edge 7, another initiator can start a different transaction. This is also the turnaround cycle for the other control lines.
The equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY#:
A high-speed burst terminated by the target will have an extra cycle at the end:
On clock edge 6, the target indicates that it wants to stop (with data), but the initiator is already holding IRDY# low, so there is a fifth data phase (clock edge 7), during which no data is transferred.
Parity.
The PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication. Due to this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later. During a data phase, whichever device is driving the AD[31:0] lines computes even parity over them and the C/BE[3:0]# lines, and sends that out the PAR line one cycle later. All access rules and turnaround cycles for the AD bus apply to the PAR line, just one cycle later. The device listening on the AD bus checks the received parity and asserts the PERR# (parity error) line one cycle after that. This generally generates a processor interrupt, and the processor can search the PCI bus for the device which detected the error.
The PERR# line is only used during data phases, once a target has been selected. If a parity error is detected during an address phase (or the data phase of a Special Cycle), the devices which observe it assert the SERR# (System error) line.
Even when some bytes are masked by the C/BE# lines and not in use, they must still have "some" defined value, and this value must be used to compute the parity.
Fast back-to-back transactions.
Due to the need for a turnaround cycle between different devices driving PCI bus signals, in general it is necessary to have an idle cycle between PCI bus transactions. However, in some circumstances it is permitted to skip this idle cycle, going directly from the final cycle of one transfer (IRDY# asserted, FRAME# deasserted) to the first cycle of the next (FRAME# asserted, IRDY# deasserted).
An initiator may only perform back-to-back transactions when:
Additional timing constraints may come from the need to turn around are the target control lines, particularly DEVSEL#. The target deasserts DEVSEL#, driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase. The second cycle of the address phase is then reserved for DEVSEL# turnaround, so if the target is different from the prior one, it must not assert DEVSEL# until the third cycle (medium DEVSEL speed).
One case where this problem cannot arise is if the initiator knows somehow (presumably because the addresses share sufficient high-order bits) that the second transfer is addressed to the same target as the prior one. In that case, it may perform back-to-back transactions. All PCI targets must support this.
It is also possible for the target keeps track of the requirements. If it never does fast DEVSEL, they are met trivially. If it does, it must wait until medium DEVSEL time unless:
Targets which have this ability indicate it by a special bit in a PCI configuration register, and if all targets on a bus have it, all initiators may use back-to-back transfers freely.
A subtractive decoding bus bridge must know to expect this extra delay in the event of back-to-back cycles, to advertise back-to-back support.
64-bit PCI.
Starting from revision 2.1, the PCI specification includes optional 64-bit support. This is provided via an extended connector which provides the 64-bit bus extensions AD[63:32], C/BE[7:4]#, and PAR64, and a number of additional power and ground pins. The 64-bit PCI connector can be distinguished from a 32-bit connector by the additional 64-bit segment.
Memory transactions between 64-bit devices may use all 64 bits to double the data transfer rate. Non-memory transactions (including configuration and I/O space accesses) may not use the 64-bit extension. During a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the address is incremented twice per data phase. The starting address must be 64-bit aligned; i.e. AD2 must be 0. The data corresponding to the intervening addresses (with AD2 = 1) is carried on the upper half of the AD bus.
To initiate a 64-bit transaction, the initiator drives the starting address on the AD bus and asserts REQ64# at the same time as FRAME#. If the selected target can support a 64-bit transfer for this transaction, it replies by asserting ACK64# at the same time as DEVSEL#. Note that a target may decide on a per-transaction basis whether to allow a 64-bit transfer.
If REQ64# is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus. If the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the address and the final command code during both address phase cycles; this allows a 64-bit target to see the entire address and begin responding earlier.
If the initiator sees DEVSEL# asserted without ACK64#, it performs 32-bit data phases. The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase. Typically, the initiator drives all 64 bits of data before seeing DEVSEL#. If ACK64# is missing, it may cease driving the upper half of the data bus.
The REQ64# and ACK64# lines are held asserted for the entire transaction save the last data phase, and deasserted at the same time as FRAME# and DEVSEL#, respectively.
The PAR64 line operates just like the PAR line, but provides even parity over AD[63:32] and C/BE[7:4]#. It is only valid for address phases if REQ64# is asserted. PAR64 is only valid for data phases if both REQ64# and ACK64# are asserted.
Cache snooping (obsolete).
PCI originally included optional support for write-back cache coherence. This required support by cacheable memory targets, which would listen to two pins from the cache on the bus, SDONE (snoop done) and SBO# (snoop backoff).
Because this was rarely implemented in practice, it was deleted from revision 2.2 of the PCI specification, and the pins re-used for SMBus access in revision 2.3.
The cache would watch all memory accesses, without asserting DEVSEL#. If it noticed an access that might be cached, it would drive SDONE low (snoop not done). A coherence-supporting target would avoid completing a data phase (asserting TRDY#) until it observed SDONE high.
In the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy, and would assert SDONE as soon as this was established. However, if the cache contained dirty data, the cache would have to write it back before the access could proceed. so it would assert SBO# when raising SDONE. This would signal the active target to assert STOP# rather than TRDY#, causing the initiator to disconnect and retry the operation later. In the meantime, the cache would arbitrate for the bus and write its data back to memory.
Targets supporting cache coherency are also required to terminate bursts before they cross cache lines.
Development tools.
When developing and/or troubleshooting the PCI bus, examination of hardware signals can be very important. Logic analyzers and bus analyzers are tools which collect, analyze, and decode signals for users to view in useful ways.


List of PlayStation 4 games

This is a list of games for the PlayStation 4. The PlayStation 4 supports both physical and digital games. Physical games are sold on Blu-ray Disc and digital games can be purchased through the PlayStation Store. See "Arcade Archives" and "Arcade Game Series" for a list of emulated arcade games that have been released on the PlayStation 4, and List of PlayStation 2 games for PlayStation 4 for PlayStation 2 games running on PlayStation 4 with an emulator. See List of PlayStation VR games for a larger range of dedicated PlayStation VR games.
There are currently games on this list.


UNIX/32V

UNIX/32V was an early version of the Unix operating system from Bell Laboratories, released in June 1979. 32V was a direct port of the Seventh Edition Unix to the DEC VAX architecture.
Overview.
Before 32V, Unix had primarily run on DEC PDP-11 computers. The Bell Labs group that developed the operating system was dissatisfied with DEC, so its members refused DEC's offer to buy a VAX when the machine was announced in 1977. They had already begun a Unix port to the Interdata 8/32 instead. DEC then approached a different Bell Labs group in Holmdel, New Jersey, which accepted the offer and started work on what was to become 32V.
Performed by Tom London and John F. Reiser, porting Unix was made possible due to work done between the Sixth and Seventh Editions of the operating system to decouple it from its "native" PDP-11 environment. The 32V team first ported the C compiler (Johnson's pcc), adapting an assembler and loader written for the Interdata 8/32 version of Unix to the VAX. They then ported the April 15, 1978 version of Unix, finding in the process that "[t]he (Bourne) shell [...] required by far the largest conversion effort of any supposedly portable program, for the simple reason that it is not portable."
UNIX/32V was released without paging virtual memory, retaining only the swapping architecture of Seventh Edition. A virtual memory system was added at Berkeley by Bill Joy and Özalp Babaoğlu in order to support Franz Lisp; this was released to other Unix licensees as the Third Berkeley Software Distribution (3BSD) in 1979. Thanks to the popularity of the two systems' successors, 4BSD and UNIX System V, UNIX/32V is an antecedent of nearly all modern Unix systems.


Swap Magic

Swap Magic is a specialized PlayStation 2 game disc used for tricking the console into reading non-retail or burned game discs, homebrew software, or games outside the console's region. The software has existed since at least mid-2003, with several different versions of the disc having been developed.
Swap Magic and its related mods, such as the Magic Switch and Swap Tool, which are used to allow the user to swap discs without the system being aware, are notable over other methods (such as a modchip) due to the fact that they do not void the PS2's warranty.
Features.
The Swap Magic disc allows the user to boot into software which allows the system to read discs that it would normally refuse because of the lack of a burst cutting area on discs that have been burned with an ordinary DVD drive, as opposed to regular retail discs which are stamped or pressed en masse. The user then removes the disc (after installing small modifications to prevent the system from detecting the drive being opened) and replaces it with another disc which can then be started. The software also allows other homebrew software to be run from a memory card or USB flash drive.
Swap Magic and most other non-Sony-made PlayStation 2 bootable discs use a method of "growing" and "splicing" stampers from original PlayStation 2 discs, a method of growing a stamper from an original game disc and joining a new stamper with the program data on to it; in essence, the resulting discs contain a portion of an original disc.
Datel, the first company outside Sony to make a bootable PlayStation 2 disc, researched the protection and produced their own discs with protection in their on-site mastering facility.
IFPI.
The IFPI on a DVD can be found on the inner ring on the underside (data side) of the disc, before the start of data in the mirror part of the disc's hub. Most contain text specified at the time of mastering; this usually consists of the string "IFPI" followed by a code describing the mastering system used, then followed by a text product description, and finally a bar code.
Development.
Swap Magic v1 was released and is compatible with the v12 slim PS2. Swap Magic v2 was released after Sony had slightly changed the design of their console in the v13-15 models of the slim PS2, and Swap Magic v1 did not work with those models. Version 2 was widely criticized as it required the user to open the console and, therefore, voided the warranty. The company responded to this criticism by releasing Swap Magic v3, which did not require any opening of the console.
CODER.
Swap Magic v3.8 (also known as CODER) was released, which adds the ability of loading Action Replay cheats into the booted game, as well as the ability to load an ELF file from usb or memory card. However, some users have complained that CODER has some compatibility issues as well as known bugs. For example, some games that work on v3.6 do not work with CODER. Consequently, v3.6 remains the most popular version of Swap Magic, though the ability to boot an ELF file allows for soft modding of the PS2.


Vayu (computer cluster)

The Vayu computer cluster, was the predecessor of Raijin, the Current Peak System of the Australian National Computational Infrastructure, located at the Australian National University in Canberra, Australian Capital Territory. It was based on a Sun Microsystems Sun Constellation System. The Vayu system was taken from Sun's code name for the compute blade within the system. Vayu is a [Hindu] god], the name meaning "wind".
The cluster was officially launched on 2009-11-16 by the Government of Australia's Minister for Innovation, Industry, Science and Research, Senator Kim Carr,[2] after provisional acceptance on 2009-09-18.[3]
Performance.
Vayu was first operated in September 2009 with one eighth of the final computing power, with the full system commissioned in March 2010.
Vayu has the following performance characteristics:
Physical system.
The system comprises:
Power consumption of the full 11936 CPU system will be approx 605 kW, but all the power used will be from green energy sources.
Software.
System software for the Vayu cluster includes:
Funding.
The national government has provided around A$26m to enable the building of the centre and installation of Vayu. Other participating organisations included the Australian Bureau of Meteorology, Australian National University, and the Commonwealth Scientific and Industrial Research Organisation, cooperating using an integrated computational environment for the earth systems sciences, including investigating aspects of operational weather forecasting through to climate modelling and prediction. The ANU and CSIRO each subscribed about A$3m, thereby getting about a quarter of the machine.
The ANU and CSIRO, with the support of the Australian Government have already made plans for funding Vayu's replacement, in about 2011-2012, with a machine about 12 times more powerful.


Xbiff

xbiff is a small utility for the X Window System that shows a mailbox with its flag raised whenever the user has new e-mail. It is included in almost every X Window System.


Microreboot

Microrebooting is a technique used to recover from failures in crash-only software systems. Instead of rebooting the whole system, only subsets of fine-grain components are restarted. The granularity of components is typically finer than the process level (e.g., EJB-level in Java EE systems).
The goal of confining the reboot to fine-grain components is threefold: to reduce the amount of time it takes for the system to return to service, to minimize the failure's disruption to the system and its users, and to preserve as much in-memory application data as possible.
The concept was proposed in 2001 by George Candea and Armando Fox, while the former was a graduate student at Stanford University. It was initially reduced to practice in systems such as a satellite ground station control system and a Java EE application server; later on it formed the basis of the design of commercial systems like Aster Data Systems nCluster.


Nvidia GRID

Nvidia GRID is a family of graphics processing units (GPUs) made by Nvidia, introduced in 2008, that is targeted specifically towards cloud gaming. The Nvidia GRID includes both graphics processing and video encoding into a single device which is able to decrease the input to display latency of cloud based video game streaming. Nvidia offer their own game streaming service that makes use of the Nvidia Grid that supports full 1080p at 60 frames per second over the Internet.
While many of Nvidia’s cards are known for gaming, there has been a recent growth of business applications that are GPU-accelerated. The Nvidia GRID K1 and K2 are being integrated with Supermicro server clusters for use with 3D-intensive applications such as graphics and computer aided design (CAD). In 2015, Microsoft began including Nvidia GRID as part of its Azure Enterprise cloud platform targeted towards professionals such as engineers, designers and researchers.


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PlayStation Broadband Navigator

PlayStation Broadband Navigator (also referred to as BB Navigator and PSBBN) is software for Japanese PlayStation 2 consoles that formats a hard disk drive for use with those consoles and provides an interface for manipulating data on that hard disk drive. It only works with official PlayStation 2 HDD units.
The PlayStation Broadband Navigator installation disc is reported to have a more strict region lock on it than normal PlayStation 2 software, as the software will only boot on NTSC-J systems with a model number ending in 0, meaning they are sold in Japan, making the software unusable on Korean and Asian NTSC-J PlayStation 2 consoles.
Online services pertaining to the software closed on March 31, 2016.
Features.
PlayStation Broadband Navigator offers many features that are not available with the original HDD Utility Disc software. Some Japanese releases take advantage of the features, and may even require a specific version (or higher) of the software.
Non-Japanese Release.
Sony Computer Entertainment America released the HDD on March 23, 2004 with HDD Utility Disc 1.01 and bundled with Final Fantasy XI. Consumers that knew about PlayStation Broadband Navigator were confused as to why it wasn't included with the HDD Utility Disc. SCEA's response was always that PlayStation Broadband Navigator would be released in North America "at a later date." This date now appears to be never in light that SCEA has switched to only manufacturing the slim, HDD-incompatible PlayStation 2 models and stopping manufacture of HDD units for their region.
Sony Computer Entertainment Europe and Sony Computer Entertainment Australia never released the HDD outside of the Linux Kit before switching to only manufacturing the slim PlayStation 2 model, so it appears that neither HDD Utility Disc or PlayStation Broadband Navigator will be released in those regions.
Broadband Navigator can later be used on any PS2 by using a modified disc.
Compatible Software.
A few games require PlayStation Broadband Navigator either for certain features to work, or for the game to work at all.


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