The Death and Return of Superman

The Death and Return of Superman is a side-scrolling beat 'em up video game released by Sunsoft for the Super NES and Genesis in 1994. It is based on "The Death of Superman" comic book storyline by DC Comics and features many characters from the comics, including Superman himself, Superboy, Steel, Cyborg Superman, the Eradicator, and Doomsday. All of the five Supermen are playable characters at some point.
Gameplay.
The Death and Return of Superman has standard "beat 'em up" gameplay, in which the player controls a character that can move in all directions. A set number of foes will enter the screen and only after they are defeated can the character continue on the quest. Although different in appearance, each character has the same basic abilities: standard melee attacks (punches), grappling attacks (get close enough to character and attack), throws (holding the forward key and attacking), grab and throw upward (holding the “up” key and attacking), grab and throw backward (holding the “back” key and attacking), or grab and pummel (hold the “down” key and attack), a projectile attack, and an “ultimate” attack that destroys all standard enemies on the screen. Their attacks only slightly vary, mostly in range and appearance.
Each Superman has the ability to fly and can thereby avoid certain characters or obstacles using this ability. There are also characters that have the ability to fly and are thereby easier to defeat if confronted in the air. There are also certain areas and levels where flying is mandatory. Also, many obstacles can be passed only by flying. However, certain screens in which the character is on an elevated platform the flying ability is almost completely negated.
With the exceptions of Superman and to a point the Man of Steel, each character has two standard types of level: melee combat and flying in which only projectile moves can be used. The standard melee levels consist of the character fighting through “common” enemies and ending the level with a fight with a “boss” character. When playing the flying levels, the player can move the character anywhere in the screen while firing the character's projectile move at greatly weakened enemies. No boss characters appear in these levels. Strangely, Superman never has a flying level and instead plays through three standard melee levels. Steel has a unique flying level that plays more like a combat level as he doesn't use his projectile attacks and relies on his melee attack. Also, Steel has a “boss” character he must defeat in order for the game to progress.
Choice of characters isn't allowed during the game and the player must play through the game as a pre-determined character for each level.
During the start of the game enemies are usually armed with guns, bombs, or chainsaws if they are armed at all. Superman's invulnerability seems to have been removed, as these items are capable of hurting him. Later characters are armed with more powerful energy type weapons and pure melee characters are now robots. Most characters appear time and time again and more powerful enemies use the same game sprite but with a different color.
Plot.
The game starts when Clawster and his army and Underworlders initiate a power failure in the city of Metropolis in an attempt to take over the city. Superman intervenes and defeats the horde of Underdwellers, Clawster included. Not long after the power is restored, a news report bulletin states a monster of unknown origin (Doomsday) is leading a path of destruction towards Metropolis, and the Justice League were unable to stop the creature. The titanic struggle between Superman and Doomsday reached a conclusion when the two delivered each other the killing blow. Superman succumbs to his injuries as he dies, as well as Doomsday.
Three months later, four Supermen emerge in an effort to replace the original Superman, whilst the other claiming he is indeed the original Superman. The game shifts to Cyborg Superman (the "Man of Tomorrow") as he attacks a Project Cadmus base to locate a comatose Doomsday. Fearing he would be a threat once again if he wakes up, the Cyborg exiles Doomsday in deep space. Next, the player controls the Eradicator (the "Last Son of Krypton") as he patrols the streets of Metropolis. However, he is forced into battle with another Superman, Steel, as the armored hero fights to prevent the Last Son of Krypton from killing enemies. After the two Supermen fought to a standstill, the Eradicator reconsiders his brutal approach to fighting crime after Steel tells him it takes humanity and compassion to be considered a Superman.
However, a bigger threat comes, as a mysterious spacecraft arrives and obliterates Coast City (the hometown of Hal Jordan). The Eradicator investigates the situation, only to run in with the mastermind, the Cyborg. The Eradicator is critically injured at the Cyborg's hands, and rushes to the Fortress of Solitude. The game shifts its focus on Superboy (the "Metropolis Kid") as he attempts to handle the current situation in Metropolis. After successfully doing so, Superboy flies off to Coast City, doing battle with the Cyborg as he arrives. The Cyborg knocks out and imprisons Superboy in the spacecraft. There, the rogue Superman reveals his plan: to destroy the world and reconstruct it in his image, starting with Coast City and Metropolis. While this is going on, a being flies among the skies above the Fortress of Solitude, albeit weakly. Back in Coast City, Superboy escapes imprisonment to go back to Metropolis, where he and Steel encounter the real Superman. Not wanting to wait, Superboy convinces the two to go with him to Coast City to stop the Cyborg once and for all.
The player now controls Steel (the "Man of Steel") as he, Superman, and Superboy launch an assault on Engine City. However, the Cyborg launches a missile set to destroy Metropolis. Superboy elects to stop the missile, and, with player controlling Superboy, he successfully destroys the missile. At Engine City, the player shifts back to Steel, as he enters the Engine's core to shut it down. Meanwhile, a regenerated Eradicator bursts out of the Fortress and arrives at Engine City to help a weakened Superman, who is at the Cyborg's mercy. The Cyborg shoots Kryptonite fuel at Superman but the Eradicator arrives and shields Superman from the blast. The BMI of the Eradicator alters the deadly effects of the Kryptonite fuel and restores Superman to full strength as the Eradicator dies. Now controlling Superman, the player defeats and destroys the Cyborg Superman. The game ends with Steel and Superboy congratulating Superman for his success and accepting him as the real Superman.
Reception.
"Next Generation" reviewed the Genesis version of the game, rating it two stars out of five, and stated that "If you must catch a glimpse of your favorite superhero, buy the comic book, not the game."
IGN placed the SNES version 81st in their Top 100 SNES Games of All Time.


Gilad Bracha

Gilad Bracha is the creator of the Newspeak programming language, a software engineer at Tensyr, and a former software engineer at Google where he worked on the Dart programming language team. He is a co-author of the second and third editions of the Java Language Specification, and a major contributor to the second edition of the Java Virtual Machine Specification.
Between 1994 and 1997, he worked on the Smalltalk system developed by Animorphic Systems, a company that was bought by Sun in 1997. From 1997 to 2006, he worked at Sun Microsystems as "Computational Theologist" and, as of 2005, "Distinguished Engineer", on various aspects of the specification and implementation of Java. Following that, he was "Distinguished Engineer" at Cadence Design Systems from 2006 to 2009, where he led a team of developers designing and implementing Newspeak.
Bracha received his B.Sc in Mathematics and Computer Science from Ben Gurion University in Israel and his Ph.D. in Computer Science from the University of Utah.
Bracha won the Senior Dahl–Nygaard Prize in 2017.
BGGA closures.
In 2006, Gilad Bracha together with Neal Gafter, James Gosling, and Peter von der Ahé (collectively BGGA) drafted a specification for adding closures to the Java programming language version 6. The proposal has been criticized by Joshua Bloch on terms of being needlessly complex (adding function types and non-local returns) while providing little benefit for the average Java programmer over other simpler proposals. Closures were added to Java 8, but based on a different proposal than the BGGA one.
Pluggable type systems.
It has been proposed by Bracha that choice of type system be made independent of choice of language; that a type system should be a module that can be "plugged" into a language as required. He believes this is advantageous, because what he calls mandatory type systems make languages less expressive and code more fragile. The requirement that types do not affect the semantics of the language is challenging to fulfill; for example, constructs like type-based overloading are disallowed.
In practice, pluggable type systems are variously called optional typing, type hinting, type annotations or gradual type checking. They tend to be constructed by adding a static type system to an existing dynamically typed language without changing its semantics and usually keeping the syntax unchanged as well. Examples include Smalltalk, Python 3, Ruby, Clojure, and PHP 5. For most of the languages there is only one implementation of the type system. The exception is Python 3 where the type system is truly pluggable, because there are several implementations and the programmer can use the one that is the best fit. The only language designed with pluggable type system in mind from the beginning is Newspeak. Java 8 provides the ability to extend the type system but does not allow flexibility in the basics of the type system, such as choosing between static and dynamic typing.
Generic Java.
A 1998 paper authored by Bracha claims that "casts inserted by the [generics] translation are guaranteed to not fail." Although initially true, wildcards were added and made the type system unsound.


Debugfs

debugfs is a special file system available in the Linux kernel since version 2.6.10-rc3. It was written by Greg Kroah-Hartman.
debugfs is a simple-to-use RAM-based file system specially designed for debugging purposes. It exists as a simple way for kernel developers to make information available to user space. Unlike , which is only meant for information about a process, or sysfs, which has strict one-value-per-file rules, debugfs has no rules at all. Developers can put any information they want there.
Use.
To compile a Linux kernel with the debugfs facility, the option must be set to yes. It is typically mounted at with a command such as:
mount -t debugfs none /sys/kernel/debug
It can be manipulated using several calls from the C header file , which include:


Brian Aker

Brian Aker, born August 4, 1972 in Lexington, Kentucky, US is an open-source hacker who has worked on various Apache modules, the Slash system, and numerous storage engines for the MySQL database. Aker was Director of Architecture at MySQL AB until it was acquired by Sun Microsystems. He led Sun's web scaling research group, where he worked on the Drizzle database project. He later became a Distinguished Engineer for Sun Microsystems. After leaving Sun when Oracle acquired it, he became the CTO of Data Differential and provided support to open source projects such as libmemcached, Gearman and the Drizzle database project. Aker is currently a Fellow and VP at Hewlett Packard Enterprise.
After graduating with triple majors in environmental science, computing and mathematics, from Antioch College, Aker contributed to his first open source project, the 386BSD operating system. He then moved to work on Slashdot, where his initial task was to rewrite the database back-end to use Oracle. However, he extended the system to ensure it allowed multiple database back-ends, and became a published author along the way, writing "Running Weblogs with Slash" () with chromatic and Dave Krieger. From 2001 to 2007 he posted stories on Slashdot under the Author name of "Krow".
Aker first involved himself with the MySQL project in 1998. In 2001 he released an early prototype of MySQL with Perl-based functions and later went from VA Linux Systems to MySQL to lead development of the 4.1 and 5.0 versions of the MySQL Database Server. He has presented projects integrating MySQL with a number of technologies, including a working version of MySQL with Java-based functions with Eric Herman in 2004
Aker has been known to offer a Perl Certification Course at the University of Washington. He has also worked on the Virtual Hospital project, providing the Internet's first medical website, while at the University of Iowa Hospital and Clinics.
While not traveling and presenting at about six open source related conferences a year, he resides in Seattle, Washington. Some of the conferences Aker has presented at are OSCON, LinuxFest Northwest, Southern California Linux Expo, and the MySQL Users Conference & Expo. He is also the maintainer of the C client library for the Memcached server. He also maintains the current version of Gearman.
He is a commentator on the prolific creation of NoSQL databases giving Ignite talks on its evolution.
A list of MySQL projects Brian Aker has created:


PlayStation controller

The PlayStation controller is the first gamepad released by Sony Computer Entertainment for its PlayStation home video game console. The original version (model SCPH-1010) was released alongside the PlayStation on December 3, 1994.
Design.
Based on the basic button configuration established with Nintendo's Super NES Controller, the PlayStation controller added a second pair of shoulder buttons for the middle fingers. Intended to update the gamepad for navigating 3D environments such as the ones PlayStation was designed to generate, the concept behind featuring shoulder buttons for both the index and middle fingers was to implement two-way directional depth controls using the two sets of buttons. To compensate for the less stable grip from shifting the middle fingers' placement to the shoulders, grip handles were added to the controller.
Using the simple geometric shapes of a green triangle, a red circle, a blue cross, and a pink square (, , , ) to label its action buttons rather than traditionally used letters or numbers, the PlayStation controller established a trademark which would be incorporated heavily into the PlayStation brand. In an interview with Teiyu Goto, designer of the original PlayStation controller, he explained what the symbols mean: the circle and cross represent "yes" and "no," respectively (which explains their common use as "confirm" and "cancel" in games; this layout is reversed in Western games); the triangle symbolizes a point of view and the square is equated to a sheet of paper there to be used to access menus.
The PlayStation 2 console is backward-compatible with the original PlayStation controller, with limited function due to a lack of analog sticks and pressure sensitive buttons.
History.
Ken Kutaragi recounted the designing of the controller:
Both Goto and Kutaragi recalled that Sony president Norio Ohga showed a special interest in the development of the controller, and strongly supported the final version.
On April 2, 1996, Sony released a revised version of the PlayStation controller (model SCPH-1080), which is 10% larger than the launch model and features a longer cord with a ferrite bead. This model was bundled with all subsequent PlayStation consoles including North American launch models.
After briefly selling the Dual Analog Controller in 1997, Sony began phasing out the PlayStation controller later that year with the introduction of the DualShock controller, which would become the new standard controller for the PlayStation, although the first game to require its use, "Ape Escape", would only be released two years later.


Intel Quark

Intel Quark is a line of 32-bit x86 SoCs and microcontrollers by Intel, designed for small size and low power consumption, and targeted at new markets including wearable devices. The line was introduced at Intel Developer Forum in 2013. Quark processors, while slower than Atom processors, are much smaller and consume less power. They lack support for SIMD instruction sets (such as MMX and SSE) and only support embedded operating systems. Quark powers the (now discontinued) Intel Galileo developer microcontroller board. However, in 2016 Arduino released the Arduino 101 board that includes an Intel Quark SoC. The CPU instruction set is the same as a Pentium (P54C/i586) CPU.
The first product in the Quark line is the single-core 32 nm X1000 SoC with a clock rate of up to 400 MHz. The system includes several interfaces, including PCI Express, serial UART, I²C, Fast Ethernet, USB 2.0, SDIO, power management controller, and GPIO. There are 16 kB of on-chip embedded SRAM and an integrated DDR3 memory controller.
A second Intel product that includes Quark core, the Intel Edison microcomputer, was presented in January 2014. It has a form factor close to the size of an SD card, and is capable of wireless networking using Wi-Fi or Bluetooth.
In January 2015, Intel announced the sub-miniature Intel Curie module for wearable applications, based on a "Quark SE" core with 80 kB SRAM and 384 kB flash. At the size of a button, it also features a 6-axis accelerometer, a DSP sensor hub, a Bluetooth LE unit and a battery charge controller.
Intel announced the end-of-life of its Quark products in January 2019, with orders accepted until July 2019 and final shipments set for July 2022.
List of Intel Quark processors.
"Lakemont" (32 nm).
The name "Lakemont" has been used in reference to the processor core in multiple Quark-series processors.
Segfault bug.
Intel Quark SoC X1000 contains a bug #71538 that "under specific circumstances" results in a type of crash known as a segfault. The workaround implemented by Intel is to omit LOCK prefixes (not required on single-threaded processors) in the compiled code. While source-based embedded systems like those built using the Yocto Project can incorporate this workaround at compile time, general purpose Linux distributions such as Debian are deeply affected by the bug. Such a workaround is not easy to implement in binaries meant to support multithreading too as they require LOCK prefixes to function properly.


Xbox Wireless Controller

The Xbox Wireless Controller is the primary game controller for the Xbox One and Xbox Series X/S home video game consoles, also commercialized for its use in Windows-based PCs, and compatible with other operating systems such as macOS, Linux, iOS and Android. The controller maintains the overall layout found in the Xbox 360 controller, but with various tweaks to its design, such as a revised shape, redesigned analog sticks, shoulder buttons, and triggers, along with new rumble motors within the triggers to allow for directional haptic feedback.
It has had three revisions with several changes to the controller's design and functionality. Microsoft also markets the Elite Wireless Controller, a premium version geared towards professional gamers, including interchangeable parts and programmability features. In turn, each of the aforementioned variations has been offered in various color schemes, some featuring special designs tying into specific games. The Xbox Series X and Series S introduced an updated version of the controller, with further refinements to its shape and ergonomics.
Layout.
The Xbox One controller retains roughly the same layout as the Xbox 360 controller, including four main face buttons, two shoulder bumpers, two analog triggers, two analog sticks and a digital D-pad. The "Start" and "Back" buttons are replaced by "Menu" and "View" buttons, while the Guide button now consists of a white backlit Xbox logo, and does not feature the "ring of light" that served as an indicator for the controller's assigned number (1 to 4).
Design.
Microsoft invested over $100 million into refining the controller design for the Xbox One; internal designers had created prototypes with various tweaks and refinements to the design over the Xbox 360 controller, along with those including unorthodox features such as embedded screens and speakers (which were rejected due to their effects on battery life, and redundancy to the main display and sound system), and the ability to emit odors.
The Xbox One controller maintains the overall layout found in the Xbox 360 controller's design, but with enhancements such as redesigned grips, a smoother build, and the removal of the protruding battery compartment. The controller also contains light emitters that allow it to be tracked and paired using Kinect sensor, and to detect when it is not being held to automatically enter a low-power state. The controller contains a micro USB port, enabling wired use of the controller with the console or on computers running Windows 7 or later with drivers, and firmware updates. For communication, the controller uses a new proprietary protocol with a greater bandwidth than the wireless protocol used by the Xbox 360 controller, reducing latency and allowing for higher quality headset audio.
The analog sticks feature a new textured rim, while the D-pad was changed to use a more traditional 4-way design rather than the circular 8-way design of the 360 controller. This change was made partially due to criticism by players of fighting games who, despite the use of "sweeps" across the D-pad in these games being part of the motivation for the 8-way design, felt that the Xbox 360's D-pad performed poorly in that type of game. The updated 4-way design is also better suited for use as individual keys in games that use them for item selection. The design of the face buttons was revised to improve their legibility, using a three-layer design consisting of a black background, colored letter, and a clear covering intended to make the letter appear to "hover" inside it. The buttons themselves are also spaced slightly closer together.
The bumpers and trigger buttons were overhauled with a new curved shape to improve their ergonomics, as the user's fingers now naturally lie at an angle upon them unlike the straighter design on Xbox 360 controllers. The bumpers were also made flush with the triggers. The triggers themselves now have a smoother feel, and were made more accurate. Each trigger features independent rumble motors called "Impulse Triggers", which allows developers to program directional vibration. One trigger can be made to vibrate when firing a gun, or both can work together to create feedback that indicates the direction of an incoming hit.
Models.
Xbox One launch model.
The original controller launched with the Xbox One console in November 2013 was black, with colored face buttons. A commemorative white variant was issued to Microsoft employees at launch, but was not available to the public until almost a year later, initially bundled with a matching white console and "Sunset Overdrive".
2015 (first) revision.
On June 9, 2015, Microsoft unveiled a revised version of the standard controller, with model 1697. Its shoulder buttons were redesigned for improved responsiveness, a 3.5 mm headphone jack was added near the controller's expansion port, and support for wireless firmware updates was added.
Externally, few changes were made; the main distinguishing feature of the 2015 revision (Model 1697) compared with the original (Model 1537) is the presence of the headphone jack on the bottom of the controller.
2016 (second) revision.
A third revision of the controller, model 1708, was introduced alongside the Xbox One S, an updated model of the Xbox One console unveiled in June 2016. It features textured grips, and additionally supports Bluetooth for use with compatible PCs and mobile devices. Users can also custom-order this controller revision via the "Xbox Design Lab" service, with their choice of colors, and an optional inscription of their Xbox Live screen name for an additional fee.
The second revision can be distinguished from prior revisions by the color and texture of the plastic surrounding the lighted Xbox/guide button. Prior controller models (1537 and 1697) have a separate piece of black glossy plastic, with the Model 1698 "Elite" also having a separate piece in black, dark red, or white. In the second revision (Model 1708) the front shell of the controller is a single piece, and the part surrounding the Xbox button now matches the texture and color of the controller. It has been made available in white, black, red, and blue colors, as well as other limited edition colors.
Xbox Series X/S launch model.
A fourth revision of the controller was released in November 2020, which is bundled with Xbox Series X and Series S, and backwards compatible with existing Xbox One consoles. It has a refined build with a slightly smaller body, a "Share" button on the center of the controller below the "View" and "Menu" buttons, a circular dished D-pad similar to the Elite Controller, and a USB-C connector instead of USB Micro-B. The controller also supports Bluetooth Low Energy.
Summary.
All of the controllers in this table are fully compatible with any Xbox One consoles, up to X|S Series.
Colors and styles.
Besides standard colors, "special" and "limited edition" Xbox Wireless Controllers have also been sold by Microsoft with special color and design schemes, sometimes tying into specific games.
Elite controller.
On June 15, 2015, during its E3 2015 press conference, Microsoft unveiled the Xbox One Elite Wireless Controller, a new controller which Xbox division head Phil Spencer described as being "an elite controller for the elite gamer". It features a steel construction with a soft-touch plastic exterior, along with interchangeable rear paddle buttons (with either short or long forms), analog stick tops (original Xbox one stick, a convex dome, and an extended version for increased accuracy ), and directional pad designs (either the traditional four-way design, or a concave disc-like design), and "hair trigger locks" for the triggers that allow users to reduce the amount of distance required to register a press. Through software, users can customize button and paddle mappings and adjust the sensitivity of the triggers and analog sticks. Two button profiles can be assigned to a switch on the controller for quick access. The Elite Controller was released on October 27, 2015.
Cosmetic variants.
A special "Gears of War 4"-themed limited edition variant of the Elite controller was unveiled during Microsoft's E3 2016 press conference. It features a rustic, dark red color scheme with a blood splatter effect and the series emblem on the rear of the controller, and a D-pad disc with weapon symbols corresponding to the in-game weapons bound to these controls.
A White Special Edition of the controller was announced on August 29, 2018. Although a revised Elite controller was leaked early in 2018 incorporating functional changes, the White Special Edition was another cosmetic variant of the original Elite.
Series 2.
Plans for a revised version of the Elite controller were leaked in January 2018, with a number of new features, including USB-C connector, and other hardware improvements such as three-level Hair Trigger Locks, adjustable tension for the thumbsticks, revised rubber grips, three user-defined profile settings, and Bluetooth connectivity, which had been introduced with the revised Xbox One S controller in 2016.
At E3 2019, Microsoft announced they would begin taking pre-orders for the Xbox Elite Wireless Controller Series 2; the controller would be available starting on November 4, 2019 at a suggested retail price of .
Support on other platforms.
Drivers were released in June 2014 to allow Xbox One controllers to be used over a USB connection on PCs running Windows 7 or later. The Xbox One Wireless Adapter for Windows is a USB dongle that allows up to eight controllers to be used at once wirelessly. Upon its release in October 2015, it was supported only by Windows 10. Drivers for Windows 7 and 8.1 were released in December 2015. An updated version of the adapter, with a smaller form factor, was released in August 2017.
Per a partnership between Microsoft and Oculus VR, the Oculus Rift CV1 virtual reality headset initially included an Xbox One controller, up until the launch of the Oculus Touch motion controllers.
On Windows 10, support for the controller is built-in, including support for wireless audio when using the wireless dongle or USB cable (it is not supported over Bluetooth). The controller is also manageable via the Xbox Accessories app, whose features include button remapping (for both the regular and Elite controller), input tests, and firmware update. On Windows 7 or 8.1, drivers are required, and the aforementioned features are not available.
Microsoft also supports Bluetooth-enabled Xbox One controllers on Android, specifically listing support for "Minecraft: Gear VR Edition" on certain Samsung Galaxy devices.
On Linux, Xbox One controllers are supported by the xpad USB driver. There also exists an alternative xpadneo driver, which supports some controller revisions that are not supported by the xpad driver, as well as additional features. Some of these additional features, such as driver support for the trigger rumble motors, aren't even supported on Windows 10.
In June 2019, Apple announced support for Bluetooth-enabled Xbox One controllers in iOS 13, macOS Catalina and tvOS 13, which became available in the fall of 2019.
Accessories.
Stereo headset adapter.
The Xbox One Stereo Headset Adapter allows the use of headsets with 3.5 millimeter headphone jacks with the original Xbox One controller, which does not include a 3.5 mm jack. An adapter for 2.5 mm headphone jacks is also included.
Chatpad.
A keyboard chatpad attachment, similar to the Xbox 360 Messenger Kit, was unveiled at Gamescom on August 4, 2015.
Play and Charge Kit.
Similarly to the Xbox 360 version, the Play and Charge kit is the official rechargeable battery pack for Xbox One controllers.


TMP.EXE


Explicit data graph execution

Explicit data graph execution, or EDGE, is a type of instruction set architecture (ISA) which intends to improve computing performance compared to common processors like the Intel x86 line. EDGE combines many individual instructions into a larger group known as a "hyperblock". Hyperblocks are designed to be able to easily run in parallel.
Parallelism of modern CPU designs generally starts to plateau at about eight internal units and from one to four "cores", EDGE designs intend to support hundreds of internal units and offer processing speeds hundreds of times greater than existing designs. Major development of the EDGE concept had been led by the University of Texas at Austin under DARPA's Polymorphous Computing Architectures program, with the stated goal of producing a single-chip CPU design with 1 TFLOPS performance by 2012, which has yet to be realized as of 2018.
Traditional designs.
Almost all computer programs consist of a series of instructions that convert data from one form to another. Most instructions require several internal steps to complete an operation. Over time, the relative performance and cost of the different steps have changed dramatically, resulting in several major shifts in ISA design.
CISC to RISC.
In the 1960s memory was relatively expensive, and CPU designers produced instruction sets that densely encoded instructions and data in order to better utilize this resource. For instance, the codice_1 instruction would be provided in many different forms that would gather A and B from different places; main memory, indexes, or registers. Providing these different instructions allowed the programmer to select the instruction that took up the least possible room in memory, reducing the program's needs and leaving more room for data.
Actually making these instructions work required circuity in the CPU, which was a significant limitation in early designs and required designers to select just those instructions that were really needed. In 1964, IBM introduced its System/360 series which used microcode to allow a single expansive instruction set architecture (ISA) to run across a wide variety of machines by implementing more or less instructions in hardware depending on the need. This allowed the ISA to be expansive, and this became the paragon of computer design in the 1960s and 70s, the so-called "orthogonal" design. This style of memory access with wide variety of modes led to instruction sets with hundreds of different instructions, a style known today as CISC (Complex Instruction Set Computing).
In 1975 IBM started a project to develop a telephone switch that required performance about three times that of their fastest contemporary computers. To reach this goal, the development team began to study the massive amount of performance data IBM had collected over the last decade. This study demonstrated that the complex ISA was in fact a significant problem; because only the most basic instructions were guaranteed to be implemented in hardware, compilers ignored the more complex ones that only ran in hardware on certain machines. As a result, the vast majority of a program's time was being spent in only five instructions. Further, even when the program called one of those five instructions, the microcode required a finite time to decode it, even if it was just to call the internal hardware. On faster machines, this overhead was considerable.
Their work, known at the time as the IBM 801, eventually led to the RISC (Reduced Instruction Set Computing) concept. Microcode was removed, and only the most basic versions of any given instruction were put into the CPU. Any more complex code was left to the compiler. The removal of so much circuitry, about of the transistors in the Motorola 68000 for instance, allowed the CPU to include more registers, which had a direct impact on performance. By the mid-1980s, further developed versions of these basic concepts were delivering performance as much as 10 times that of the fastest CISC designs, in spite of using less-developed fabrication.
Internal parallelism.
In the 1990s the chip design and fabrication process grew to the point where it was possible to build a commodity processor with every potential feature built into it. To improve performance, CPU designs started adding internal parallelism, becoming "superscalar". In any program there are instructions that work on unrelated data, so by adding more functional units these instructions can be run at the same time. A new portion of the CPU, the "scheduler", looks for these independent instructions and feeds them into the units, taking their outputs and re-ordering them so externally it appears they ran in succession.
The amount of parallelism that can be extracted in superscalar designs is limited by the number of instructions that the scheduler can examine for interdependencies. Examining a greater number of instructions can improve the chance of finding an instruction that can be run in parallel, but only at the cost of increasing the complexity of the scheduler itself. Despite massive efforts, CPU designs using classic RISC or CISC ISA's have plateaued at about three or four functional units .
Additional performance can be wrung from systems by examining the instructions to find ones that operate on different "types" of data and adding units dedicated to that sort of data; this has led to the introduction of floating point units and, more recently, single instruction, multiple data (SIMD) units. The drawback to this approach is that it makes the CPU less generic; feeding the CPU with a program that uses almost all floating point instructions, for instance, will bog the FPUs while the other units sit idle.
A more recent problem in modern CPU designs is the delay talking to the registers. In general terms the size of the CPU die has remained largely the same over time, while the size of the units within the CPU has grown much smaller as more and more units were added. That means that the "relative" distance between any one function unit and the global register file has grown over time. Once introduced in order to avoid delays in talking to main memory, the global register file has itself become a delay that is worth avoiding.
A new ISA?
Just as the delays talking to memory while its price fell suggested a radical change in ISA (Instruction Set Architecture) from CISC to RISC, designers are considering whether the problems scaling in parallelism and the increasing delays talking to registers demands another switch in basic ISA.
Among the ways to introduce a new ISA are the very long instruction word (VLIW) architectures, typified by the Itanium. VLIW moves the scheduler logic out of the CPU and into the compiler, where it has much more memory and longer timelines to examine the instruction stream. This "static placement, static issue" execution model works well when all delays are known, but in the presence of cache latencies, filling instruction words has proven to be a difficult challenge for the compiler. An instruction that might take five cycles if the data is in the cache could take hundreds if it is not, but the compiler has no way to know whether that data will be in the cache at runtime that's determined by overall system load and other factors that have nothing to do with the program being compiled.
The key performance bottleneck in traditional designs is that the data and the instructions that operate on them are theoretically scattered about memory. Memory performance dominates overall performance, and classic "dynamic placement, dynamic issue" designs seem to have reached the limit of their performance capabilities. VLIW uses a "static placement, static issue" model, but has proven difficult to master because the runtime behavior of programs is difficult to predict and properly schedule in advance.
EDGE.
Theory.
EDGE architectures are a new class of ISA's based on a "static placement, dynamic issue" design. EDGE systems compile source code into a form consisting of statically-allocated "hyperblocks" containing many individual instructions, hundreds or thousands. These hyperblocks are then scheduled dynamically by the CPU. EDGE thus combines the advantages of the VLIW concept of looking for independent data at compile time, with the superscalar RISC concept of executing the instructions when the data for them becomes available.
In the vast majority of real-world programs, the linkage of data and instructions is both obvious and explicit. Programs are divided into small blocks referred to as subroutines, procedures or methods (depending on the era and the programming language being used) which generally have well-defined entrance and exit points where data is passed in or out. This information is lost as the high level language is converted into the processor's much simpler ISA. But this information is so useful that modern compilers have generalized the concept as the "basic block", attempting to identify them within programs while they optimize memory access through the registers. A block of instructions does not have control statements but can have predicated instructions. The dataflow graph is encoded using these blocks, by specifying the flow of data from one block of instructions to another, or to some storage area.
The basic idea of EDGE is to directly support and operate on these blocks at the ISA level. Since basic blocks access memory in well-defined ways, the processor can load up related blocks and schedule them so that the output of one block feeds directly into the one that will consume its data. This eliminates the need for a global register file, and simplifies the compiler's task in scheduling access to the registers by the program as a whole instead, each basic block is given its own local registers and the compiler optimizes access within the block, a much simpler task.
EDGE systems bear a strong resemblance to dataflow languages from the 1960s–1970s, and again in the 1990s. Dataflow computers execute programs according to the "dataflow firing rule", which stipulates that an instruction may execute at any time after its operands are available. Due to the isolation of data, similar to EDGE, dataflow languages are inherently parallel, and interest in them followed the more general interest in massive parallelism as a solution to general computing problems. Studies based on existing CPU technology at the time demonstrated that it would be difficult for a dataflow machine to keep enough data near the CPU to be widely parallel, and it is precisely this bottleneck that modern fabrication techniques can solve by placing hundreds of CPU's and their memory on a single die.
Another reason that dataflow systems never became popular is that compilers of the era found it difficult to work with common imperative languages like C++. Instead, most dataflow systems used dedicated languages like Prograph, which limited their commercial interest. A decade of compiler research has eliminated many of these problems, and a key difference between dataflow and EDGE approaches is that EDGE designs intend to work with commonly used languages.
CPUs.
An EDGE-based CPU would consist of one or more small block engines with their own local registers; realistic designs might have hundreds of these units. The units are interconnected to each other using dedicated inter-block communication links. Due to the information encoded into the block by the compiler, the scheduler can examine an entire block to see if its inputs are available and send it into an engine for execution there is no need to examine the individual instructions within.
With a small increase in complexity, the scheduler can examine multiple blocks to see if the outputs of one are fed in as the inputs of another, and place these blocks on units that reduce their inter-unit communications delays. If a modern CPU examines a thousand instructions for potential parallelism, the same complexity in EDGE allows it to examine a thousand hyperblocks, each one consisting of hundreds of instructions. This gives the scheduler considerably better scope for no additional cost. It is this pattern of operation that gives the concept its name; the "graph" is the string of blocks connected by the data flowing between them.
Another advantage of the EDGE concept is that it is massively scalable. A low-end design could consist of a single block engine with a stub scheduler that simply sends in blocks as they are called by the program. An EDGE processor intended for desktop use would instead include hundreds of block engines. Critically, all that changes between these designs is the physical layout of the chip and private information that is known only by the scheduler; a program written for the single-unit machine would run without any changes on the desktop version, albeit thousands of times faster. Power scaling is likewise dramatically improved and simplified; block engines can be turned on or off as required with a linear effect on power consumption.
Perhaps the greatest advantage to the EDGE concept is that it is suitable for running any sort of data load. Unlike modern CPU designs where different portions of the CPU are dedicated to different sorts of data, an EDGE CPU would normally consist of a single type of ALU-like unit. A desktop user running several different programs at the same time would get just as much parallelism as a scientific user feeding in a single program using floating point only; in both cases the scheduler would simply load every block it could into the units. At a low level the performance of the individual block engines would not match that of a dedicated FPU, for instance, but it would attempt to overwhelm any such advantage through massive parallelism.
Implementations.
TRIPS.
The University of Texas at Austin was developing an EDGE ISA known as TRIPS. In order to simplify the microarchitecture of a CPU designed to run it, the TRIPS ISA imposes several well-defined constraints on each TRIPS hyperblock, they:
The TRIPS compiler statically bundles instructions into hyperblocks, but also statically compiles these blocks to run on particular ALUs. This means that TRIPS programs have some dependency on the precise implementation they are compiled for.
In 2003 they produced a sample TRIPS prototype with sixteen block engines in a 4 by 4 grid, along with a megabyte of local cache and transfer memory. A single chip version of TRIPS, fabbed by IBM in Canada using a 130 nm process, contains two such "grid engines" along with shared level-2 cache and various support systems. Four such chips and a gigabyte of RAM are placed together on a daughter-card for experimentation.
The TRIPS team had set an ultimate goal of producing a single-chip implementation capable of running at a sustained performance of 1 TFLOPS, about 50 times the performance of high-end commodity CPUs available in 2008 (the dual-core Xeon 5160 provides about 17 GFLOPS).
CASH.
CMU's CASH is a compiler that produces an intermediate code called "Pegasus". CASH and TRIPS are very similar in concept, but CASH is not targeted to produce output for a specific architecture, and therefore has no hard limits on the block layout.
WaveScalar.
The University of Washington's WaveScalar architecture is substantially similar to EDGE, but does not statically place instructions within its "waves". Instead, special instructions ("phi", and "rho") mark the boundaries of the waves and allow scheduling.


Bootsplash

A bootsplash, also known as a bootscreen, is a graphical representation of the boot process of the operating system.
A bootsplash can be a simple visualization of the scrolling boot messages in the console, but it can also present graphics or some combinations of both.
Unlike splash screens, bootsplash is not necessarily designed for marketing purposes, but can be to enhance the experience of the user as eye candy, or provide the user with messages (with an added advantage of color-coding facility) to diagnose the state of the system.
Microsoft Windows.
All versions of Microsoft Windows feature a boot screen, which is loaded during the startup process. With extra, third-party utilities, it is possible to replace the default Windows boot screen with custom images, text, and/or animations.
Windows Vista.
In Windows Vista, the default boot screen is represented by a green indeterminate progress indicator. The boot screen can be changed so that it displays a static image of an aurora with the text, "Starting Windows Vista" by enabling the "No GUI boot" option within the Windows System Configuration Utility (msconfig.exe). Microsoft would update the aurora image throughout the lifecycle of the operating system, starting with the first service pack, where it was altered to match the image displayed during the operating system's hibernation screen.
Windows 7.
In Windows 7, the change of the boot screen, although possible through third-party utilities, is extremely risky and may cause the system to be unable to boot. Also, the hidden "Aurora" boot screen was removed.
Windows 8, 8.1, 10.
If the system is UEFI boot (not Legacy boot) and the ACPI BGRT table is present, Windows 8 and later will display the OEM logo during startup.


GeForce 6 series

The GeForce 6 series (codename NV40) is Nvidia's sixth generation of GeForce graphic processing units. Launched on April 14, 2004, the GeForce 6 family introduced PureVideo post-processing for video, "SLI" technology, and "Shader Model 3.0" support (compliant with Microsoft DirectX 9.0c specification and OpenGL 2.0).
GeForce 6 Series features.
SLI.
The Scalable Link Interface (SLI) allows two GeForce 6 cards of the same type to be connected in tandem. The driver software balances the workload between the cards. SLI-capability is limited to select members of the GeForce 6 family; 6500 and above. SLI is only available for cards utilizing the PCI-Express bus.
Nvidia PureVideo Technology.
Nvidia PureVideo technology is the combination of a dedicated video processing core and software which decodes H.264, VC-1, WMV, and MPEG-2 videos with reduced CPU utilization.
Shader Model 3.0.
Nvidia was the first to deliver Shader Model 3.0 (SM3) capability in its GPUs. SM3 extends SM2 in a number of ways: standard FP32 (32-bit floating-point) precision, dynamic branching, increased efficiency and longer shader lengths are the main additions. Shader Model 3.0 was quickly adopted by game developers because it was quite simple to convert existing shaders coded with SM 2.0/2.0A/2.0B to version 3.0, and it offered noticeable performance improvements across the entire GeForce 6 line.
Caveats.
PureVideo functionality varies by model, with some models lacking WMV9 and/or H.264 acceleration.
In addition, motherboards with some VIA and SIS chipsets and an AMD Athlon XP processor seemingly have compatibility problems with the GeForce 6600 and 6800 GPUs. Problems that have been known to arise are freezing, artifacts, reboots, and other issues that make gaming and use of 3D applications almost impossible. These problems seem to happen only on Direct3D based applications and do not affect OpenGL.
Geforce 6 Series comparison.
Here is how the released versions of the "GeForce 6" series family compare to Nvidia's previous flagship GPU, the GeForce FX 5950 Ultra, in addition to the comparable units of ATI's newly released for the time Radeon X800 and X850 Series:
(*) GeForce FX series has an Array-based Vertex Shader.
(**) AGP 6600 GT variant.
GeForce 6800 Series.
The first family in the GeForce 6 product-line, the 6800 series catered to the high-performance gaming market. As the very first GeForce 6 model, the 16 pixel pipeline GeForce 6800 Ultra (NV40) was 2 to 2.5 times faster than Nvidia's previous top-line product (the GeForce FX 5950 Ultra), packed four times the number of pixel pipelines, twice the number of texture units and added a much improved pixel-shader architecture. Yet, the 6800 Ultra was fabricated on the same (IBM) 130 nanometer process node as the FX 5950, and it consumed slightly less power.
Like all of Nvidia's GPUs up until 2004, initial 6800 members were designed for the AGP bus. Nvidia added support for the PCI Express (PCIe) bus in later GeForce 6 products, usually by use of an AGP-PCIe bridge chip. In the case of the 6800 GT and 6800 Ultra, Nvidia developed a variant of the NV40 chip called the NV45. The NV45 shares the same die core as the NV40, but embeds an AGP-PCIe bridge on the chip's package. (Internally, the NV45 is an AGP NV40 with added bus-translation logic, to permit interfacing with a PCIe motherboard. Externally, the NV45 is a single package with two separate silicon dies clearly visible on the top.) NV48 is a version of NV45 which supports 512MB RAM.
The use of an AGP-PCIe bridge chip initially led to fears that natively-AGP GPUs would not be able to take advantage of the additional bandwidth offered by PCIe and would therefore be at a disadvantage relative to native PCIe chips. However, benchmarking reveals that even AGP 4x is fast enough that most contemporary games do not improve significantly in performance when switched to AGP 8x, rendering the further bandwidth increase provided by PCIe largely superfluous. Additionally, Nvidia's on-board implementations of AGP are clocked at AGP 12x or 16x, providing bandwidth comparable to PCIe for the rare situations when this bandwidth is actually necessary.
The use of a bridge chip allowed Nvidia to release a full complement of PCIe graphics cards without having to redesign them for the PCIe interface. Later, when Nvidia's GPUs were designed to use PCIe natively, the bidirectional bridge chip allowed them to be used in AGP cards.
ATI, initially a critic of the bridge chip, eventually designed a similar mechanism for their own cards.
Nvidia's professional "Quadro" line contains members drawn from the 6800 series: Quadro FX 4000 (AGP) and the Quadro FX 3400, 4400 and 4400g (both PCI Express). The 6800 series was also incorporated into laptops with the GeForce Go 6800 and Go 6800 Ultra GPUs.
PureVideo and the AGP GeForce 6800.
PureVideo expanded the level of multimedia-video support from decoding of MPEG-2 video to decoding of more advanced codecs (MPEG-4, WMV9), enhanced post-processing (advanced de-interlacing), and limited acceleration for encoding. But perhaps ironically, the first GeForce product(s) to offer PureVideo, the AGP GeForce 6800/GT/Ultra, failed to support all of PureVideo's advertised features.
Media player software (WMP9) with support for WMV-acceleration did not become available until several months after the 6800's introduction. User and web reports showed little if any difference between PureVideo enabled GeForces and non-Purevideo cards. The prolonged public silence of Nvidia, after promising updated drivers, and test benchmarks gathered by users led the user community to conclude that the WMV9 decoder component of the AGP 6800's PureVideo unit is either non-functional or intentionally disabled.
In late 2005, an update to Nvidia's website finally confirmed what had long been suspected by the user community: WMV-acceleration is not available on the AGP 6800. Of course, today's standard computers are fast enough to play WMV9 video and other sophisticated codecs like MPEG-4, H.264 or VP8 without hardware acceleration.
GeForce 6600 Series.
The GeForce 6600 (NV43) was officially launched on August 12, 2004, several months after the launch of the 6800 Ultra. With half the pixel pipelines and vertex shaders of the 6800 GT, and a smaller 128-bit memory bus, the lower-performance and lower-cost 6600 is the mainstream product of the GeForce 6 series. The 6600 series retains the core rendering features of the 6800 series, including SLI. Equipped with fewer rendering units, the 6600 series processes pixel data at a slower rate than the more powerful 6800 series. However, the reduction in hardware resources, and migration to TSMC's 110 nm manufacturing process (versus the 6800's 130 nm process), make the 6600 both less expensive for Nvidia to manufacture and less expensive for customers to purchase.
Their 6600 series currently has three variants: the GeForce 6600LE, the 6600, and the 6600GT (in order from slowest to fastest.) The 6600 GT performs quite a bit better than the GeForce FX 5950 Ultra or Radeon 9800 XT, with the 6600 GT scoring around 8000 in 3DMark03, while the GeForce FX 5950 Ultra scored around 6000, and it is also much cheaper. Notably, the 6600 GT offered identical performance to ATI's high-end X800 PRO graphics card with drivers previous December 2004, when running the popular game "Doom 3". It was also about as fast as the higher-end GeForce 6800 when running games without anti-aliasing in most scenarios.
At introduction, the 6600 family was only available in PCI Express form. AGP models became available roughly a month later, through the use of Nvidia's AGP-PCIe bridge chip. A majority of the AGP GeForce 6600GTs have their memory clocked at 900 MHz, which is 100 MHz slower than the PCI-E cards, on which the memory operates at 1000 MHz. This can contribute to a performance decline when playing certain games. However, it was often possible to "overclock" the memory to its nominal frequency of 1000 MHz and there are AGP cards (for example from XFX) that use 1000 MHz by default.
6600 chipset table.
Other data for PCI Express based cards:
Other data for AGP based cards:
GeForce 6500.
The GeForce 6500 was released in October 2005 and is based on the same NV44 core as the value/budget (low-end or entry level) GeForce 6200TC, but with a higher GPU clock speed and more memory. The GeForce 6500 also supports SLI.
GeForce 6200.
With just 4 pixel pipelines, the 6200 series forms Nvidia's value/budget (low-end or entry level) product. The 6200 omits memory compression and SLI support, but otherwise offers similar rendering features as the 6600s. The later 6200 boards were based on the NV44 core (s), which is the final production silicon for the 6200 series.
However, at introduction, production silicon was not yet ready. Nvidia fulfilled 6200 orders by shipping binned/rejected 6600 series cores (NV43V). The rejects were factory-modified to disable four pixel pipelines, thereby converting the native 6600 product into a 6200 product. Some users were able to "unlock" early 6200 boards through a software utility (effectively converting the 6200 back into a 6600 with the complete set of eight pixel pipelines total) if they owned boards with an NV43 A2 or earlier revision of the core. Thus, not all NV43-based 6200 boards could successfully be unlocked (specifically, those with a core revision of A4 or higher), and as soon as NV44 production silicon became available, Nvidia discontinued shipments of downgraded NV43V cores.
GeForce 6200 TurboCache / AGP.
The GeForce 6200 TurboCache / AGP (NV44/NV44a) is a natively four-pipeline version of the NV43. GeForce 6200 TurboCache cards only have a very small (by modern standards) amount of memory, but attempt to make up for this by using system memory accessed through the PCI-Express bus.
GeForce 6200 TurboCache / AGP chip specifications.
GeForce 6200 PCI (NV44) without TurboCache.
BFG Technologies originally introduced a unique PCI variant of the GeForce 6200 via its namesake B.F.G. and 3D Fuzion product lines. Subsequently, PNY (GeForce 6200 256 MB PCI), SPARKLE Computer (GeForce 6200 128 MB PCI and GeForce 6200 256 MB PCI), and eVGA (e-GeForce 6200 256 MB PCI) released their own PCI versions of the Geforce 6200 featuring higher memory clocks and resultant memory bandwidth.
Until the release of the ATI X1300 PCI, these were the only PCI DirectX 9 capable cards not based on previous generation GeForce5 FX technology or discontinued XGI Technology Volari V3XT chipsets.
Excluding SPARKLE's GeForce 8400 and 8500 series, Zotac GT 610 cards and Club 3D HD 5450, in late 2012 the enhanced 512 MB Geforce 6200 PCI variants remain among the most powerful PCI based systems available, making these cards desired by users lacking the option of upgrading to an AGP or PCI Express based discrete video card.
GeForce 6100 and 6150 series.
In late 2005 Nvidia introduced a new member to the GeForce family, the 6100 series, also known as C51. The term GeForce 6100/6150 actually refers to an nForce4-based motherboard with an integrated NV44 core, as opposed to a standalone graphics card. Nvidia released this product both to follow up its immensely popular GeForce4 MX based nForce and nForce2 boards and to compete with ATI's RS480/482 and Intel's GMA 900/950 in the integrated graphics space. The 6100 series is very competitive, usually tying with or just edging out the ATI products in most benchmarks.
The motherboards use two different types of southbridges - the nForce 410 and the nForce 430. They are fairly similar in features to the nForce4 Ultra motherboards that were on the market before them. Both feature PCI Express and PCI support, eight USB 2.0 ports, integrated sound, two Parallel ATA ports, and Serial ATA 3.0 Gbit/s with Native Command Queuing (NCQ) – two SATA ports in the case of the 410, four in the 430. The 430 southbridge also supports Gigabit Ethernet with Nvidia's ActiveArmor hardware firewall, while the 410 supports standard 10/100 Ethernet only.
GeForce 6100 and 6150 series chip specifications.
Both the 6100 and 6150 support Shader Model 3.0 and DirectX 9.0c. The 6150 also features support for High-Definition video decoding of H.264/VC1/MPEG2, PureVideo Processing, DVI, and video-out. The 6100 only supports SD decoding of MPEG2/WMV9. Maximum supported resolution is 1920 x 1440 pixels (@75 Hz) for RGB display and 1600 x 1200 pixels (@65 Hz) for DVI-D display
GeForce 61XX abnormally high failure rate in notebook computers.
In 2008, Nvidia took a $150 to 250M charge against revenue because the GPUs were failing at "higher than normal rates." HP provided an extension to their warranty of up to 24 months for notebooks affected by this issue. A class action suit was filed against HP and Nvidia by Whatley Drake & Kallas LLC.
GeForce 6150LE.
The GeForce 6150LE was primarily featured in the 2006 lineup of the Nvidia Business Platform. The chip is used by Fujitsu-Siemens in its Esprimo green desktop, HP in its Pavilion Media Center a1547c Desktop PC and Compaq Presario SR1915 Desktop, and Dell in its Dimension C521 and E521 desktop PCs.
GeForce 6150SE.
GeForce 6150SE (MCP61, also known as C61) is an updated, single-chip version of the Nvidia GeForce 6100. The MCP61 uses less power than the original C51 2-chip version of 6100. Its onboard video outperforms the 6150 in many 3D benchmarks despite its lower core frequency (425 MHz), because of added hardware Z-culling.
MCP61 introduced a bug in the SATA NCQ implementation. As a result, Nvidia employees have contributed code to disable NCQ operations under Linux.
IntelliSample 4.0 and the GeForce 6 GPUs.
Upon launch of the GeForce 7 family of graphics processing units, IntelliSample 4.0 was considered to be an exclusive feature of the GeForce 7 series of GPUs. However, version 91.47 (and subsequent versions) of the Nvidia ForceWare drivers enable the features of IntelliSample 4.0 on the GeForce 6 GPUs. IntelliSample 4.0 introduces two new antialiasing modes, known as Transparency Supersampling Antialiasing and Transparency Multisampling Antialiasing. These new antialiasing modes enhance the image quality of thin-lined objects such as fences, trees, vegetation and grass in various games.
One possible reason for the enabling of IntelliSample 4.0 for GeForce 6 GPUs might be the fact that the GeForce 7100 GS GPUs are based on NV44 chips, the same as the GeForce 6200 models. Because of this, Nvidia had to backport IntelliSample 4.0 features to the NV4x GPUs, and as a result, the entire GeForce 6 family is able to enjoy the benefits of Transparency Antialiasing.
It was already well known across various communities that Transparency Antialiasing could be used on GeForce 6 GPUs by using some third party tweak tools. As of Nvidia ForceWare drivers 175.16, GeForce 6 IntelliSample 4.0 support has been removed.
Discontinued support.
NVIDIA has ceased driver support for GeForce 6 series.


Rex C. Conn


RealMagic

RealMagic (or "ReelMagic"), from Sigma Designs, was one of the first fully compliant MPEG playback boards on the market in the mid-1990s.
RealMagic is a hardware-accelerated MPEG decoder that mixes its video stream into a computer video card's output through the video card's feature connector. It is also a SoundBlaster-compatible sound card.
Successors.
Sigma design's Realmagic superseded by
Several software companies in 1993 promised to support the card, including Access, Interplay, and Sierra. Software written for RealMagic includes:
Note: the above titles were on a REELMAGIC demo CD that came with the hardware. The CD also contained corporate promotion videos, training videos, news footage of JFK and the Apollo moon mission. Also included in the bundle, was a complete version of The Horde - published by Crystal Dynamics (1994)
Other software includes:


MIPS-3D

MIPS-3D is an extension to the MIPS V instruction set architecture (ISA) that added 13 new instructions for improving the performance of 3D graphics applications. The instructions improved performance by reducing the number of instructions required to implement four common 3D graphics operations: vertex transformation, clipping, transformation and lighting.
For vertex transformation:
For clipping:
For perspective division and normalization:


Mac OS nanokernel

The Mac OS nanokernel is an operating system kernel serving as the basis of most PowerPC based system software versions 7 through 9 of the classic Mac OS, predating Mac OS X.
The initial revision of this software is a single tasking system which delegates most tasks to an emulator running the Motorola 68000 series (68K) version of the operating system. The second major revision supports multitasking, multiprocessing, and message passing, and would be more properly called a microkernel. Unlike the 68K-derived Mac OS kernel running within it, the PowerPC kernel exists in a protected memory space and executes device drivers in user mode.
The nanokernel is very different from the Copland OS microkernel, although they were created in succession with similar goals.
System 7.1.2 – Mac OS 8.5.1.
The original nanokernel, and the tightly integrated Mac 68k emulator, were written by emulation consultant Gary Davidian. Its main purpose is to allow the existing Motorola 68K version of the operating system to run on new hardware. As such, the normal state of the system is to be running 68K code. The operating system does little until activated by an interrupt, which is quickly mapped to its 68K equivalent within the virtual machine.
Other tasks may include switching back to PowerPC mode, if necessary, upon completion of the interrupt handler, and mapping the Macintosh virtual memory system to the PowerPC hardware. However, as the software is little documented, these might instead be handled by the emulator running in user mode.
This nanokernel is stored on the Mac OS ROM chip integrated into Old World ROM computers, or inside the Mac OS ROM file on disk on the New World ROM computers, rather than being installed in the familiar sense.
Interim development.
Progress after 1994 demanded additional functionality. A forward-looking architecture was introduced for PCI card drivers in anticipation of the Copland microkernel called NuKernel, which supports memory protection. The Open Transport networking architecture introduced standardized PowerPC synchronization primitives. The DayStar Digital Genesis MP Macintosh clone requires kernel extensions to support multiprocessing. This evolution would later affect the overhaul to the nanokernel in Mac OS 8.6.
Mac OS 8.6 and later.
Mac OS 8.6's nanokernel was rewritten by René A. Vega to add Multiprocessing Services 2.0 support. PowerMacInfo, distributed in the Multiprocessing SDK, is an application that displays statistics about the nanokernel's operation.


HELP (command)


OpenBGPD

OpenBGPD, also known as OpenBSD Border Gateway Protocol Daemon, is a server software program that allows general purpose computers to be used as routers. It is a Unix system daemon that provides a free, open-source implementation of the Border Gateway Protocol version 4. This allows a machine to exchange routes with other systems that speak BGP.
OpenBSD Border Gateway Protocol Daemon is developed by Henning Brauer, Peter Hessler, and Claudio Jeker as part of the OpenBSD project. OpenOSPFD, developed by Esben Nørby, is a companion daemon of OpenBGPD that implements the Open Shortest Path First protocol. The suite was developed as an alternative to packages such as Quagga, a Linux-focused routing suite which is licensed under the GPL and does not meet the project's requirements and quality standards.
Goals.
The design goals of OpenBSD Border Gateway Protocol Daemon include being secure (non-exploitable), reliable, and lean enough for most users, both in size and memory usage. The configuration language should be both powerful and easy to use. It must also be able to quickly handle hundreds of thousands of table entries in a memory-efficient way.
Design.
OpenBGPD consists of a parent process, and two child processes: the Route Decision Engine (RDE), and the Session Engine (SE). The parent process is the only part that doesn't drop privileges; the others do, in the interest of non-exploitability. The parent process cannot drop privileges, because it needs to update the routing table and it has to run on a root port.


List of AMD mobile microprocessors

Initial platform (2003).
Launched in 2003, the initial platform for mobile AMD processors consists of:
Mobile Sempron.
"Dublin" (Socket 754, CG, 130 nm, Desktop replacement).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit"
"Dublin" (Socket 754, CG, 130 nm, Low power).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit"
"Georgetown" (Socket 754, D0, 90 nm, Desktop replacement).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit"
"Sonora" (Socket 754, D0, 90 nm, Low power).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit"
"Albany" (Socket 754, E6, 90 nm, Desktop replacement).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit"
"Roma" (Socket 754, E6, 90 nm, Low power).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit"
Mobile Athlon 64.
"ClawHammer" (C0 & CG, 130 nm, Desktop replacement).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
"ClawHammer" (C0 & CG, 130 nm, 62 W TDP).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
"ClawHammer" (CG, 130 nm, 35 W TDP).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
"Odessa" (CG, 130 nm, Desktop replacement).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
"Odessa" (CG, 130 nm, 35 W TDP).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
"Oakville" (D0, 90 nm, 35 W TDP Low Power).
"MMX, SSE, SSE2, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
"Newark" (E5, 90 nm, 62 W TDP).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
Turion 64.
"Lancaster" (90 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!"
Kite platform (2006).
Introduced in 2006, the "Kite" platform consists of:
Mobile Sempron.
"Keene" (Socket S1, F2, 90 nm, Low power).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!"
Turion 64.
"Richmond" (90 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Turion 64 X2.
"Taylor" (90 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
"Trinidad" (90 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Kite Refresh platform (2007).
AMD used Kite Refresh as the codenamed for the second-generation AMD mobile platform introduced in February 2007.
Mobile Sempron.
"Sherman" (Socket S1, G1 & G2, 65 nm, Low power).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64"
Athlon 64 X2.
"Tyler" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Turion 64 X2.
"Tyler" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Puma platform (2008).
The "Puma" platform introduced in 2008 with June 2008 availability for the third-generation AMD mobile platform consists of:
Mobile Sempron.
"Sable" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!"
Athlon X2.
"Lion" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Turion X2.
"Lion" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Turion X2 Ultra.
"Lion" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Yukon platform (2009).
The "Yukon" platform was introduced on January 8, 2009 with expected April availability for the first AMD Ultrathin Platform targeting the ultra-portable notebook market.
Athlon Neo.
"Huron" (65 nm, 15 W TDP).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!, AMD-V"
"Sherman" (65 nm, 15 W TDP).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
"Congo" (65 nm, 13 W TDP).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
Turion.
"Congo" (65 nm, 20 W TDP).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64 (AMD's x86-64 implementation), PowerNow!"
Congo platform (2009).
The "Congo" platform was introduced in September 2009, as the second AMD Ultrathin Platform targeting the ultra-portable notebook market.
Athlon Neo X2.
"Conesus" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, AMD-V"
Turion Neo X2.
"Conesus" (65 nm).
"MMX, SSE, SSE2, SSE3, Enhanced 3DNow!, NX bit, AMD64, AMD-V, PowerNow!"
Tigris platform (2009).
The "Tigris" platform introduced in September 2009 for the AMD Mainstream Notebook Platform consists of:
Sempron.
"Caspian" (45 nm).
Single-core mobile processor
"MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Athlon II.
"Caspian" (45 nm).
Dual-core mobile processor
"MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Turion II.
"Caspian" (45 nm).
Dual-core mobile processor
"MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Turion II (Ultra).
"Caspian" (45 nm).
Dual-core mobile processor
"MMX, SSE, SSE2, SSE3, SSE4a, ABM, Enhanced 3DNow!, NX bit, AMD64, PowerNow!, AMD-V"
Nile platform (2010).
The "Nile" platform introduced on May 12, 2010 for the third AMD Ultrathin Platform consists of:
V series.
"Geneva" (45 nm).
Single-core mobile processor
Athlon II Neo.
"Geneva" (45 nm).
Single-core mobile processor
Single-core mobile processor
Dual-core mobile processor
Turion II Neo.
"Geneva" (45 nm).
Dual-core mobile processor
Danube platform (2010).
The "Danube" platform introduced on May 12, 2010 for the AMD Mainstream Notebook Platform consists of:
V series.
Champlain (45 nm).
Single-core mobile processor
Athlon II.
Champlain (45 nm).
Dual-core mobile processor
Turion II.
Champlain (45 nm).
Dual-core mobile processor
Phenom II.
Champlain (45 nm).
Dual-core mobile processor
 Triple-core mobile processors
 Quad-core mobile processors
Brazos platform (2011).
AMD Ultrathin Platform introduced on January 5, 2011, as the fourth AMD mobile platform targeting the ultra-portable notebook market. It features the 40 nm AMD Ontario (a 9-watt APU for netbooks and small form factor desktops and devices) and Zacate (an 18-watt TDP APU for ultrathin, mainstream, and value notebooks as well as desktops and all-in-ones) APUs.
Both low-power APU versions feature two Bobcat x86 cores and fully support DirectX11, DirectCompute (Microsoft programming interface for GPU computing) and OpenCL (cross-platform programming interface standard for multi-core x86 and accelerated GPU computing). Both also include UVD dedicated hardware acceleration for HD video including 1080p resolutions. This platform consists of:
Sabine (Fusion) platform (2011).
The "Sabine" platform introduced on June 30, 2011 for the AMD Mainstream Notebook Platform consists of:
""Llano" (32 nm).
1 Unified shaders : Texture mapping units : Render output units
Brazos 2.0 platform (2012).
AMD Ultrathin Platform introduced on June 6, 2012, as the fourth AMD mobile platform targeting the ultra-portable notebook market. It will feature the 40 nm Zacate (an 18-watt TDP APU for ultrathin, mainstream, and value notebooks as well as desktops and all-in-ones) APUs.
This platform consists of:
Comal (Fusion) platform (2012).
The "Comal" platform introduced on May 15, 2012 for the AMD Mainstream Notebook Platform consists of:
"Trinity" (2012, 32 nm).
1 Config GPU are Unified shaders : Texture mapping units : Render output units
"Richland"" (2013, 32 nm).
1 Config GPU are Unified shaders : Texture mapping units : Render output units
Jaguar (2013).
"Temash" (2013, 28 nm).
Elite Mobility APU:
1 Unified shaders : Texture mapping units : Render output units
"Kabini" (2013, 28 nm).
Mainstream APU:
1 Unified shaders : Texture mapping units : Render output units


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