Portable Executable

The Portable Executable (PE) format is a file format for executables, object code, DLLs and others used in 32-bit and 64-bit versions of Windows operating systems. The PE format is a data structure that encapsulates the information necessary for the Windows OS loader to manage the wrapped executable code. This includes dynamic library references for linking, API export and import tables, resource management data and thread-local storage (TLS) data. On NT operating systems, the PE format is used for EXE, DLL, SYS (device driver), MUI and other file types. The Unified Extensible Firmware Interface (UEFI) specification states that PE is the standard executable format in EFI environments.
On Windows NT operating systems, PE currently supports the x86-32, x86-64 (AMD64/Intel 64), IA-64, ARM and ARM64 instruction set architectures (ISAs). Prior to Windows 2000, Windows NT (and thus PE) supported the MIPS, Alpha, and PowerPC ISAs. Because PE is used on Windows CE, it continues to support several variants of the MIPS, ARM (including Thumb), and SuperH ISAs.
Analogous formats to PE are ELF (used in Linux and most other versions of Unix) and Mach-O (used in macOS and iOS).
History.
Microsoft migrated to the PE format from the 16-bit NE formats with the introduction of the Windows NT 3.1 operating system. All later versions of Windows, including Windows 95/98/ME and the Win32s addition to Windows 3.1x, support the file structure. The format has retained limited legacy support to bridge the gap between DOS-based and NT systems. For example, PE/COFF headers still include a DOS executable program, which is by default a DOS stub that displays a message like "This program cannot be run in DOS mode" (or similar), though it can be a full-fledged DOS version of the program (a later notable case being the Windows 98 SE installer). This constitutes a form of fat binary. PE also continues to serve the changing Windows platform. Some extensions include the .NET PE format (see below), a 64-bit version called PE32+ (sometimes PE+), and a specification for Windows CE.
Technical details.
Layout.
A PE file consists of a number of headers and sections that tell the dynamic linker how to map the file into memory. An executable image consists of several different regions, each of which require different memory protection; so the start of each section must be aligned to a page boundary. For instance, typically the ".text" section (which holds program code) is mapped as execute/readonly, and the ".data" section (holding global variables) is mapped as no-execute/readwrite. However, to avoid wasting space, the different sections are not page aligned on disk. Part of the job of the dynamic linker is to map each section to memory individually and assign the correct permissions to the resulting regions, according to the instructions found in the headers.
Import table.
One section of note is the "import address table" (IAT), which is used as a lookup table when the application is calling a function in a different module. It can be in the form of both import by ordinal and import by name. Because a compiled program cannot know the memory location of the libraries it depends upon, an indirect jump is required whenever an API call is made. As the dynamic linker loads modules and joins them together, it writes actual addresses into the IAT slots, so that they point to the memory locations of the corresponding library functions. Though this adds an extra jump over the cost of an intra-module call resulting in a performance penalty, it provides a key benefit: The number of memory pages that need to be copy-on-write changed by the loader is minimized, saving memory and disk I/O time. If the compiler knows ahead of time that a call will be inter-module (via a dllimport attribute) it can produce more optimized code that simply results in an indirect call opcode.
Relocations.
PE files normally do not contain position-independent code. Instead they are compiled to a preferred "base address", and all addresses emitted by the compiler/linker are fixed ahead of time. If a PE file cannot be loaded at its preferred address (because it's already taken by something else), the operating system will "rebase" it. This involves recalculating every absolute address and modifying the code to use the new values. The loader does this by comparing the preferred and actual load addresses, and calculating a delta value. This is then added to the preferred address to come up with the new address of the memory location. Base relocations are stored in a list and added, as needed, to an existing memory location. The resulting code is now private to the process and no longer shareable, so many of the memory saving benefits of DLLs are lost in this scenario. It also slows down loading of the module significantly. For this reason rebasing is to be avoided wherever possible, and the DLLs shipped by Microsoft have base addresses pre-computed so as not to overlap. In the no rebase case PE therefore has the advantage of very efficient code, but in the presence of rebasing the memory usage hit can be expensive. This contrasts with ELF which uses fully position-independent code and a global offset table, which trades off execution time in favor of lower memory usage.
.NET, metadata, and the PE format.
In a .NET executable, the PE code section contains a stub that invokes the CLR virtual machine startup entry, _CorExeMain or _CorDllMain in mscoree.dll, much like it was in Visual Basic executables. The virtual machine then makes use of .NET metadata present, the root of which, IMAGE_COR20_HEADER (also called "CLR header") is pointed to by codice_1 entry in the PE header's data directory. IMAGE_COR20_HEADER strongly resembles PE's optional header, essentially playing its role for the CLR loader.
The CLR-related data, including the root structure itself, is typically contained in the common code section, .text. It is composed of a few directories: metadata, embedded resources, strong names and a few for native-code interoperability. Metadata directory is a set of tables that list all the distinct .NET entities in the assembly, including types, methods, fields, constants, events, as well as references between them and to other assemblies.
Use on other operating systems.
The PE format is also used by ReactOS, as ReactOS is intended to be binary-compatible with Windows. It has also historically been used by a number of other operating systems, including SkyOS and BeOS R3. However, both SkyOS and BeOS eventually moved to ELF.
As the Mono development platform intends to be binary compatible with the Microsoft .NET Framework, it uses the same PE format as the Microsoft implementation. The same goes for Microsoft's own cross-platform .NET Core.
On x86(-64) Unix-like operating systems, Windows binaries (in PE format) can be executed with Wine. The HX DOS Extender also uses the PE format for native DOS 32-bit binaries, plus it can, to some degree, execute existing Windows binaries in DOS, thus acting like an equivalent of Wine for DOS.
On IA-32 and x86-64 Linux one can also run Windows' DLLs under loadlibrary.
Mac OS X 10.5 has the ability to load and parse PE files, but is not binary compatible with Windows.
UEFI and EFI firmware use Portable Executable files as well as the Windows ABI x64 calling convention for applications.


RDCPM.COM


List of Nintendo 64 games

<onlyinclude>The list of Nintendo 64 games includes licensed releases spanning from the platform's launch in 1996 to the final release in 2002. The Nintendo 64 home video game console's library of games were primarily released in a plastic ROM cartridge called the Game Pak. This strategic choice of high-performance but lower-capacity medium was met with some controversy compared to CD-ROM. Two small indentations on the back of each cartridge allows it to connect or pass through the system's cartridge dustcover flaps. All regions have the same connectors, and region-locked cartridges will fit into the other regions' systems by using a cartridge converter or by simply removing the cartridge's casing. However, the systems are also equipped with lockout chips that will only allow them to play their appropriate games. Both Japanese and North American systems have the same NTSC lockout, and Europe has a PAL lockout. A bypass device such as the N64 Passport or the Datel Action Replay can be used to play import games, but a few require an additional boot code.
The Nintendo 64 was first launched in Japan on June 23, 1996 with "Super Mario 64", "Pilotwings 64", and "Saikyō Habu Shōgi"; in North America with "Super Mario 64" and "Pilotwings 64"; and in Europe with "Super Mario 64", "Pilotwings 64", ', and '. The final licensed game to be published for the system is the North American-locked "Tony Hawk's Pro Skater 3" on August 20, 2002. The final first-party games are "Dr. Mario 64" on April 8, 2001 in North America, and "Dōbutsu no Mori" six days later in Japan. The best-selling game is "Super Mario 64" with 11 million units . The total unit sales of Nintendo 64 software has exceeded the total unit sales of GameCube software, but it has the lowest software sales per console sold among all Nintendo consoles. The Nintendo 64 library is to date the smallest for a Nintendo home console.
This list is initially organized by either the game's English language title, or the hepburn romanization of Japan-only releases. All English titles are listed first, followed by alternate titles, and there are no unofficial translations. Games for the 64DD peripheral and the Aleck 64 arcade system are not included in this list.
Nintendo 64 games.
There are currently games on this list.


Chrome shell


GUID Partition Table

The GUID Partition Table (GPT) is a standard for the layout of partition tables of a physical computer storage device, such as a hard disk drive or solid-state drive, using universally unique identifiers, which are also known as globally unique identifiers (GUIDs). Forming a part of the Unified Extensible Firmware Interface (UEFI) standard (Unified EFI Forum-proposed replacement for the PC BIOS), it is nevertheless also used for some BIOS systems, because of the limitations of master boot record (MBR) partition tables, which use 32 bits for logical block addressing (LBA) of traditional 512-byte disk sectors.
All modern personal computer operating systems support GPT. Some, including macOS and Microsoft Windows on the x86 architecture, support booting from GPT partitions only on systems with EFI firmware, but FreeBSD and most Linux distributions can boot from GPT partitions on systems with either the BIOS or the EFI firmware interface.
History.
The Master Boot Record (MBR) partitioning scheme, widely used since the early 1980s, imposed limitations for use of modern hardware. The available size for block addresses and related information is limited to 32 bits. For hard disks with 512byte sectors, the MBR partition table entries allow a maximum size of 2 TiB (2³² × 512bytes) or 2.20 TB (2.20 × 10¹² bytes).
In the late 1990s, Intel developed a new partition table format as part of what eventually became the Unified Extensible Firmware Interface (UEFI). The GUID Partition Table is specified in chapter 5 of the UEFI 2.8 specification. GPT uses 64 bits for logical block addresses, allowing a maximum disk size of 264 sectors. For disks with 512byte sectors, the maximum size is 8 ZiB (264 × 512bytes) or 9.44 ZB (9.44 × 10²¹ bytes). For disks with 4,096byte sectors the maximum size is 64 ZiB (264 × 4,096bytes) or 75.6 ZB (75.6 × 10²¹ bytes).
In 2010, hard-disk manufacturers introduced drives with 4,096byte sectors (Advanced Format). For compatibility with legacy hardware and software, those drives include an emulation technology (512e) that presents 512byte sectors to the entity accessing the hard drive, despite their underlying 4,096byte physical sectors.
Features.
Like MBR, GPTs use logical block addressing (LBA) in place of the historical cylinder-head-sector (CHS) addressing. The protective MBR is stored at LBA 0, the GPT header is in LBA 1. The GPT header has a pointer to the partition table ("Partition Entry Array"), which is typically at LBA 2. Each entry on the partition table has a size of 128 bytes.
The UEFI specification stipulates that a minimum of 16,384 bytes, regardless of sector size, are allocated for the Partition Entry Array. Thus, on a disk with 512-byte sectors, at least 32 sectors are used for the Partition Entry Array, and the first usable block is LBA 34 or higher. While on a 4,096-byte sectors disk, at least 4 sectors are used for the Partition Entry Array, and the first usable block is LBA 6 or higher.
MBR variants.
Protective MBR (LBA 0).
For limited backward compatibility, the space of the legacy MBR is still reserved in the GPT specification, but it is now used in a way that prevents MBR-based disk utilities from misrecognizing and possibly overwriting GPT disks. This is referred to as a "protective MBR".
A single codice_1 of , encompassing the entire GPT drive (where "entire" actually means as much of the drive as can be represented in an MBR), is indicated and identifies it as GPT. Operating systems and tools which cannot read GPT disks will generally recognize the disk as containing one partition of unknown type and no empty space, and will typically refuse to modify the disk unless the user explicitly requests and confirms the deletion of this partition. This minimizes accidental erasures. Furthermore, GPT-aware OSes may check the protective MBR and if the enclosed partition type is not of type or if there are multiple partitions defined on the target device, the OS may refuse to manipulate the partition table.
If the actual size of the disk exceeds the maximum partition size representable using the legacy 32-bit LBA entries in the MBR partition table, the recorded size of this partition is clipped at the maximum, thereby ignoring the rest of the disk. This amounts to a maximum reported size of 2 TiB, assuming a disk with 512 bytes per sector (see 512e). It would result in 16 TiB with 4 KiB sectors (4Kn), but since many older operating systems and tools are hard coded for a sector size of 512 bytes or are limited to 32-bit calculations, exceeding the 2 TiB limit could cause compatibility problems.
Hybrid MBR (LBA 0 + GPT).
In operating systems that support GPT-based boot through BIOS services rather than EFI, the first sector may also still be used to store the first stage of the bootloader code, but modified to recognize GPT partitions. The bootloader in the MBR must not assume a sector size of 512 bytes.
Partition table header (LBA 1).
The partition table header defines the usable blocks on the disk. It also defines the number and size of the partition entries that make up the partition table (offsets 80 and 84 in the table).
Partition entries (LBA 2–33).
After the header, the Partition Entry Array describes partitions, using a minimum size of 128 bytes for each entry block. The starting location of the array on disk, and the size of each entry, are given in the GPT header. The first 16 bytes of each entry designate the partition type's globally unique identifier (GUID). For example, the GUID for an EFI system partition is . The second 16 bytes are a GUID unique to the partition. Then follow the starting and ending 64 bit LBAs, partition attributes, and the 36 character (max.) Unicode partition name. As is the nature and purpose of GUIDs and as per RFC 4122, no central registry is needed to ensure the uniqueness of the GUID partition type designators.
The 64-bit partition table attributes are shared between 48-bit common attributes for all partition types, and 16-bit type-specific attributes:
Microsoft defines the type-specific attributes for basic data partition as:
Google defines the type-specific attributes for Chrome OS kernel as:
Operating-system support.
Windows: 32-bit versions.
Windows 7 and earlier do not support UEFI on 32-bit platforms, and therefore do not allow booting from GPT partitions.
Windows: 64-bit versions.
Limited to 128 partitions per disk.
Partition type GUIDs.
Each partition has a "partition type GUID" that identifies the type of the partition and therefore partitions of the same type will all have the same "partition type GUID". Each partition also has a "partition unique GUID" as a separate entry, which as the name implies is a unique id for each partition.


SPARC64 IXfx


AntiX

antiX () is a Linux distribution built directly on Debian Stable. It is comparatively lightweight and suitable for older computers, while also providing cutting edge kernel and applications, as well as updates and additions via the apt-get package system and Debian-compatible repositories. Since version 19 it comes in two init system flavours: sysVinit and runit.
Versions.
antiX is available for IA-32 and x86-64 architectures, and comes in 3 versions:
These three versions were joined by antiX MX in 2014, developed in cooperation with the MEPIS Community. It uses Xfce as the default desktop environment, is based directly on Debian Stable, is highly stable and gives solid performance from a medium-sized footprint. As of November 2016, MX Linux is now listed as a separate distro on DistroWatch.
Release history.
antiX is a Linux distribution, originally based on MEPIS, which itself is based on the Debian stable distribution. It initially replaced the MEPIS KDE desktop environment with the Fluxbox and IceWM window managers, making it suitable for older, less powerful x86-based systems. Unlike Debian, antiX is systemd-free.


Gulftown

Gulftown or Westmere-EP is the codename of an up to six-core hyperthreaded Intel processor able to run up to 12 threads in parallel. It is based on Westmere microarchitecture, the 32 nm shrink of Nehalem. Originally rumored to be called the Intel Core i9, it is sold as an Intel Core i7. The first release was the Core i7 980X in the first quarter of 2010, along with its server counterpart, the Xeon 3600 and the dual-socket Xeon 5600 (Westmere-EP) series using identical chips.
Processor.
First figures indicate that at equivalent clock rates, depending on the software, it has up to 50% higher performance than the identically clocked quad-core Bloomfield Core i7-975. Despite having 50% more transistors, the CPU strongly benefits from the 32-nm process, drawing the same or even less power (depending on the operating system) than its Bloomfield predecessors with merely four cores. The thermal design power (TDP) of all planned models is stated to be 130 watts.
Westmere-EP is the first six-core dual-socket processor from Intel, following the quad-core Bloomfield and Gainestown (also known as Nehalem-EP) processors using the same LGA 1366 package, while the earlier Dunnington six-core processor is a Socket 604 based multi-socket processor. The CPUID extended model number is 44 (2Ch) and two product codes are used, 80613 for the UP desktop/server models and 80614 for the Xeon 5600-series DP server models. In some models, only four of the six cores are enabled.
Since 2014, Xeon 3600 and 5600 series Westmere-EP processors became somewhat sought-after as an upgrade route for older X58 motherboards. In some cases, motherboard BIOS revisions have allowed the installation of these six core processors onto boards originally targeted for two or four core processors. In fully threaded workloads, total system performance will increase by a value equal to the number of cores added (i.e. moving from a four core 2.6 GHz to a six core 2.6 GHz system would deliver 50% more multithreaded performance). With proper BIOS support and the correct supporting components, many users have reported substantial overclocking potential, often as high as 4.4 GHz while staying within Intel's maximum allowed voltages (no higher than 1.35v for the core or the uncore)


Nanolinux

NanoLinux
is an open source, free and very lightweight Linux distribution that requires only 14 MB of disk space including tiny versions of the most common desktop applications and several games. It is based on the Core version of the Tiny Core Linux
distribution and uses Busybox, Nano-X instead of X.Org, FLTK 1.3.x as the default GUI toolkit, and SLWM (super-lightweight window manager). The included applications are mainly based on FLTK.
Applications included in the distribution.
Nanolinux includes several lightweight applications, including:
The distribution also includes several games, such as Tuxchess, Checkers, NXeyes, Mastermind, Sudoku and Blocks.
Support for TrueType fonts and UTF-8 is also provided. Nanolinux is distributed as Live CD ISO images, installation on flash disk
and hard disk
is documented on its Wiki pages.
System requirements.
Minimal configuration:
The Live CD version without swapfile requires 64 MB of RAM and 14 MB of disk space.


Conroe (microprocessor)

Conroe is the code name for many Intel processors sold as Core 2 Duo, Xeon, Pentium Dual-Core and Celeron. It was the first desktop processor to be based on the Core microarchitecture, replacing the NetBurst microarchitecture based Cedar Mill processor. It has product code 80557, which is shared with "Allendale" and "Conroe-L" that are very similar but have a smaller L2 cache. Conroe-L has only one processor core and a new CPUID model. The mobile version of Conroe is Merom, the dual-socket server version is Woodcrest, and the quad-core desktop version is Kentsfield.
Conroe was replaced by the 45 nm Wolfdale processor.
Variants.
Conroe.
The first Intel Core 2 Duo branded processor cores, code-named Conroe, were launched on July 27, 2006, at Fragapalooza, a yearly gaming event in Edmonton, Alberta, Canada. These processors were fabricated on 300 mm wafers using a 65 nm manufacturing process, and intended for desktop computers, as a replacement for the Pentium 4 and Pentium D branded CPUs. Intel has claimed that Conroe provides 40% more performance at 40% less power compared to the Pentium D; the E6300, lowest end of the initial Conroe lineup, is able to match or even exceed the former flagship Pentium Extreme Edition 965 in performance despite a massive 50% clock frequency deficit. All Conroe processors are manufactured with 4 MB L2 cache; however, due to manufacturing defects or possibly for marketing purposes, the E6300 and E6400 versions based on this core have half their cache disabled, leaving them with only 2 MB of usable L2 cache. These Conroe-based E6300 and E6400 CPUs have the B2 stepping.
The lower end E6300 (1.86 GHz) and E6400 (2.13 GHz), both with a 1066 MHz FSB (64-bits wide), were released on July 27, 2006. Traditionally, CPUs of the same family with less cache simply have the unavailable cache disabled, since this allows parts that fail quality control to be sold at a lower rating. When yields improve, they may be replaced with versions that only have the cache amount needed on the die, to bring down manufacturing cost. At launch time, Intel's prices for the Core 2 Duo E6300 and E6400 processors were US$183 and US$224 each in quantities of 1000. Conroe CPUs have improved capabilities over previous models with similar processor clock rates. According to reviews, the larger 4 MB L2 cache vs. the smaller 2 MB L2 cache at the same frequency and FSB can provide a 0–9% performance gain with certain applications and 0–16% performance gain with certain games.
The higher end Conroe processors are the E6600 (2.4 GHz) and E6700 (2.67 GHz) Core 2 Duo models. The family has a 1066 MHz front side bus, 4 MB shared L2 cache, and 65 watts TDP. These processors have been tested against AMD's then-current top performing processors (Athlon 64 FX Series), which were, until this latest Intel release, the highest performance X86 CPUs available. Conroe chips also produce less heat than their predecessors — a benefit of the new 65 nm technology and the more efficient microarchitecture. At launch time,
Intel's prices for the Core 2 Duo E6600 and E6700 processors were US$316 and US$530, respectively, each in quantities of 1000.
E6320 and E6420 Conroe CPUs at 1.86 and 2.13 GHz respectively were launched on April 22, 2007 featuring a full 4 MB of cache and are considered Conroes.
Intel released four additional Core 2 Duo Processors on July 22, 2007. The release coincided with that of the Intel Bearlake (x3x) chipsets. The new processors are named Core 2 Duo E6540, E6550, E6750, and E6850. Processors with a number ending in "50" have a 1333 MHz FSB. The processors all have 4 MB of L2 cache. Their clock frequency is similar to that of the already released processors with the same first two digits (E6600, E6700, X6800). An additional model, the E6540, was launched with specifications similar to the E6550 but lacking Intel Trusted Execution Technology and vPro support. These processors are stated to compete with AMD's Phenom processor line and are therefore priced below corresponding processors with a 1066 MHz FSB.
All remaining Conroe Core 2 processors have been phased out in March 2009.
Conroe XE.
The Core 2 Extreme was officially released on July 29, 2006. However, some retailers appeared to have released it on July 13, 2006, though at a higher premium. Currently, the Core 2 Extreme X6800 is the only dual core Core 2 Extreme processor available. The less powerful E6x00 models of Core 2 Duo were scheduled for simultaneous release with the X6800, which are both available at this time. It uses the Conroe XE core and replaces the dual-core Pentium Extreme Edition processors. The Core 2 Extreme X6800 has a clock rate of 2.93 GHz and a 1066 MHz FSB, although it was initially expected to be released with a 3.33 GHz clock rate and a 1333 MHz FSB. The TDP for the X6800 is 75–watts, higher than the TDPs of regular Core 2 Duo CPUs, which have a 65 watt TDP. With SpeedStep enabled, the average temperature of the CPU when idle is essentially that of the ambient atmosphere with its fan running at 1500 RPM.
At launch time, Intel's price for the Core 2 Extreme X6800 was US$999 each in quantities of 1000. Like the desktop Core 2 Duo, it has 4 MB of shared L2 cache available. This means that the only major difference between the regular Core 2 Duo and Core 2 Extreme is the higher clock rate and unlocked multiplier, the usual advantages of the "Extreme Edition." The fully unlocked multiplier is of use to enthusiasts as it allows the user to set the clock rate higher than shipping frequency without modifying the FSB frequency unlike mainstream Core 2 Duo models whose multipliers are downward unlocked only.
Allendale.
Allendale was originally the name for the E4000 processors, which use a low-cost version of the "Conroe" core. They feature a lower front side bus frequency of 800 MHz instead of 1066 MHz and only half the L2 cache (2 MB, similar to the Core 2 Duo E6300 and E6400), offering a smaller die size and therefore greater yields. Most media have subsequently applied the name "Allendale" to all LGA 775 processors with steppings L2 and M0, while Intel refers to all of these as "Conroe".
The Core 2 Duo E4300 uses an "Allendale" core, released on January 21, 2007. "Allendale" processors are produced in the LGA 775 form factor, on the 65 nm process node.
Initial list price per processor in quantities of one thousand for the E4300 was US$163. A standard OEM price was US$175, or US$189 for a retail package. The price was cut on April 22, 2007, when the E4400 was released at $133 and the E4300 dropped to $113. A new E2000 series of Allendale processors with half their L2 cache disabled was released in mid-June 2007 under the Pentium Dual-Core brand name. The working cache memory was reduced by half again when the Allendale core was released under Intel's Celeron brand; the Celeron E1000 processors have a 512k L2 cache shared between its two cores.
Subsequent E4000 "Allendale" processors were introduced as E4500 and E4600. The final E4700 processor was using the G0 stepping instead of M0, which makes it a "Conroe" core. The E4000 processors were discontinued on March 6, 2009.
E6300 and E6400 CPUs, as well as their Xeon 3040 and 3050 counterparts, have been made using the original 4 MB "B2" stepping with half their L2 cache disabled prior to Q1 2007, but using the 2 MB "L2" stepping later. This caused contention regarding whether or not the previously available versions were specimens of the "Allendale" core. Only the newer cores are now commonly referred to as "Allendale".
Quoted from The Tech Report:
You'll find plenty of sources that will tell you the code name for these 2 MB Core 2 Duo processors is "Allendale," but Intel says otherwise. These CPUs are still code-named "Conroe," which makes sense since they're the same physical chips with half of their L2 cache disabled. Intel may well be cooking up a chip code-named Allendale with 2 MB of L2 cache natively, but this is not that chip.
Conroe-L.
The Conroe-L Celeron is a single-core processor built on the Core microarchitecture and is clocked much lower than the Cedar Mill Celerons, but still outperforms them. It is based on the 65 nm Conroe-L core, and uses a 400-series model number sequence. The FSB was increased from 533 MHz to 800 MHz in this generation, and the TDP was decreased from 65 W to 35 W. Traditionally with Celerons, it does not have Intel VT-x support or SpeedStep. All Conroe-L models are single-core processors for the value segment of the market, much like the AMD K8-based Sempron. The product line was launched on June 5, 2007.
On October 21, 2007, Intel presented a new processor for its Intel Essential Series. The full name of the processor is a Celeron 220 and is soldered on the D201GLY2 motherboard. With 1.2 GHz and a 512 KB second level cache it has a TDP of 19 Watt and can be cooled passively. The Celeron 220 is the successor of the Celeron 215 which is based on a Yonah core and used on the D201GLY motherboard. This processor is exclusively used on the mini-ITX boards targeted to the sub-value market segment.
Conroe-CL.
Conroe-CL is a version of Conroe with the LGA 771 Socket otherwise used in Woodcrest. Unlike real Woodcrest, they are only usable in single-CPU configurations. The three Conroe-CL processors that are known are sold as Core 2 Duo E6305, E6405 and Celeron 445. These processors will not work in regular LGA 775 mainboards but are typically used in blade servers that also use Woodcrest or other DP server processors.


Zeiss Otus 1.4/55

The Zeiss Otus 1.4/55 is a manual focus standard prime lens for Canon Inc. and Nikon DSLR bodies. It was announced by Zeiss on October 7, 2013.
It is noted for producing a sharp image, with good correction for chromatic and spherical aberration as well as distortion. It produces pleasant bokeh, but vignettes strongly on full frame bodies at its maximum aperture.


ThinkCentre A series

The A Series desktops are part of Lenovo’s ThinkCentre product line. Formerly an IBM brand, Lenovo acquired the ThinkCentre desktop brand following its purchase of IBM’s Personal Computing Division (PCD) in 2005. The first desktop in the A Series was the ThinkCentre A50p. Lenovo has released A Series desktops in multiple form factors, ranging from traditional tower, to small form factor, and all-in-ones (AIOs).
2010.
A70.
The A70 was released by Lenovo in 2010 with the following specifications:
A70z.
The ThinkCentre A70z was an all-in-one (AIO) desktop released by Lenovo in 2010. The AIO offered the following specifications:
Engadget reported that the A70z was easy to set up and offered a 35-second boot time, in-line with Lenovo's claims. The A70z was capable of handling high-definition video and running Adobe Photoshop with ease, making it suitable for everyday business use. However, the presence of the integrated graphics card prevented 3D gaming on the desktop.
The ThinkCentre A70z received positive reviews from "Inc.", "Desktop Review", and "Hardware Central". "Inc." ranked the ThinkCentre A70z third on its list of ‘Best New Business Desktops’. Desktop Review listed the A70z desktop on its list of ‘Top 10 Desktops for Back to School’. Hardware Central awarded the desktop 12 out of 15 stars, with 4 of 5 stars for features, performance, and value respectively.
A58.
Announced in March 2010, the ThinkCentre A58 desktop was equipped with the Intel Pentium Dual-Core E5200 processor with a speed of 2.5 GHz,
up to a Core 2 quad q9x50. 3GB 800 MHz DDR2 SDRAM, a 250GB 7200 RPM SATA hard disk drive up to 1TB 7200 rpm and an 160gb 10.000rpm drive, Integrated HD audio with a built-in mono speaker, Intel GMA 4500 integrated graphics, Microsoft Windows Vista Business, 6 USB2.0 ports, 2 PS/2 inputs, and 2 headphone and microphone audio jacks with line out. Desktop Review listed the pros of the desktop as being the build quality, legacy ports, and power saving software. The cons were listed as wasted internal space, the absence of card readers, and the limited port selection.
2007.
A55.
PC World indicated that the ThinkCentre A55 small form factor desktop, announced in January 2007, was a “pure business PC.". The desktop incorporated a mid-range processor, the Intel E6300 Core 2 Duo with a speed of 1.83 GHz, and offered a maximum of 4GB of DDR2 667 MHz RAM on 2 DIMM slots. PC World noted that the desktop scored 89 on its World Bench 5 test, indicating that it could run most software packages available at the time with ease.
A61e.
The ThinkCentre A61e desktop was announced in September 2007 and was called “the company's smallest, quietest and most energy-efficient desktop yet”. The A61e was equipped with an AMD Athlon X2 BE-2350 processor with a speed of 2.1 GHz, 2GB RAM, a 180GB hard disk drive, the ATI Radeon X1200 graphics card, and Microsoft Windows Vista Business.
PC Mag listed the pros of the desktop as its compact size, energy efficiency, processor, quiet operation, affordable price, ThinkVantage utilities, case design, and light weight. The cons were listed as being the slightly reduced performance compared to other business systems, the lack of internal expansion for PCI/PCIe slots, notebook-class RAM, and external power supply.
2006.
A60.
The ThinkCentre A60 desktop was announced in August 2006 by Lenovo following the company’s acquisition of IBM’s Personal Computing Division in 2005.
It was categorized a mid-range desktop by PCMag. The desktop was praised for its useful utilities, a toolless chassis designed for upgrades, Athlon X2 dual core processor, spacious hard disk drive and the fact that it still had a floppy disk drive. The cons were that the desktop had shared video memory despite the use of Windows Vista and that it was slower than desktops with Intel Core 2 Duo processors.
A53.
The ThinkCentre A53 and A55 desktops were announced in September 2006 by Lenovo. The A53 desktop featured an Intel Pentium D 945 3.4 GHz dual core processor, SiS662 chipset, up to 2GB DDR2 Non-ECC SDRAM, an 80GB SATA-300 7200RPM hard disk drive, an integrated High Definition Audio sound card, and built in speakers.
A55.
The ThinkCentre A55 desktop was equipped with an Intel Pentium 4 541 Processor, 512MB PC2-4200 DDR2 Memory, an 80GB 7200rpm SATA Hard Drive, 48x CD-RW/DVD Combo Drive, Intel GMA 3000 Integrated Graphics with 128MB Shared Memory, Integrated AC'97 Audio, and six USB 2.0 Ports. Both processor and storage were criticized by About.com, with software bundle being complimented.
Launch in 2003.
A50p.
The first ThinkCentre A Series desktop was the A50p. It was designed as a business machine, as observed in a review by About.com. This was because of the storage space on the desktop, which was limited to 40GB – sufficient for business documents and applications, but not for images and video. The A50p had an Intel Pentium 4 2.8 GHz Processor, 256MB PC2700 DDR Memory, 40GB 7,200rpm Hard Drive, 48x CD-ROM Optical Drive, SoundMAX Cadenza (AC'97) Audio, Intel Extreme 2 Integrated Graphics with 64MB of Shared Memory, a 10/100 Ethernet Port, and six USB 2.0 Ports.
The A50p was called a "high-end consumer PC" by "PC Magazine". The machine was indicated to be a capable home-office machine to which multimedia applications could be added. The specifications of the A50p desktop were: Intel Pentium 4 processor, 1GB RAM, 120GB hard disk drive, and a 17 inch LCD screen.


Celeron

Celeron is a brand name given by Intel to a number of different low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers.
Celeron processors are compatible with IA-32 computer programs, but their performance is typically significantly lower when compared to similar CPUs of higher-priced Intel CPU brands. The Celeron brand often has less cache memory or intentionally disabled advanced features. These missing features can have a variable impact on performance, but it is often very substantial. While a few of the Celeron designs have achieved surprising performance, most of the Celeron line has exhibited noticeably degraded performance. This has been the primary justification for the higher cost of other Intel CPU brands versus the Celeron range.
Introduced in April 1998, the first Celeron-branded CPU was based on the Pentium II. Subsequent Celeron-branded CPUs were based on the Pentium III, Pentium 4, Pentium M, and Intel Core.
Background.
As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to the Cyrix 6x86, the AMD K6, and the IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance-competitive at 233 MHz. Although a faster Pentium MMX would have been a lower-risk strategy, the industry-standard Socket 7 platform hosted a market of competitor CPUs that could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was to be pin-compatible with their high-end Pentium II product, using the Pentium II's proprietary Slot 1 interface.
The Celeron also effectively killed off the nine-year-old 80486 chip, which had been the low-end processor brand for laptops until 1998.
Intel hired marketing firm Lexicon Branding, which had originally come up with the name "Pentium", to devise a name for the new product as well. The "San Jose Mercury News" described Lexicon's reasoning behind the name they chose: ""Celer" is Latin for swift. As in 'accelerate'. And 'on'. As in 'turned on'. Celeron is seven letters and three syllables, like Pentium. The 'Cel' of Celeron rhymes with 'tel' of Intel."
Desktop Celerons.
P6-based Celerons.
Covington.
Launched in April 1998, the first "Covington" Celeron was essentially a 266 MHz Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (frequencies 33 or 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons had trouble outcompeting the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance, and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless, the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in Slot 1 SEPP format.
Mendocino.
The "Mendocino" Celeron, launched August 24, 1998, was the first retail CPU to use on-die L2 cache. Whereas Covington had no secondary cache at all, Mendocino included 128 KB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron "300A". Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an "A" appended, some people call all Mendocino processors "Celeron-A" regardless of clock rate.
The new Mendocino-core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as "too" successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, many Celeron 300A CPUs could run reliably at 450 MHz. This was achieved by simply increasing the front-side bus (FSB) clock rate from the stock 66 MHz to the 100 MHz clock of the Pentium II, helped by several facts: the 440BX chipset with nominal support for 100 MHz and correspondent memory had already been on the market, and the internal L2 cache was more tolerant to overclocking than external cache chips, which already had to run at half-CPU speed by design. At this frequency, the budget Mendocino Celeron rivaled the fastest x86 processors available. Some motherboards were designed to prevent this modification, by restricting the Celeron's front side bus to 66 MHz. However, overclockers soon found that putting tape over pin B21 of the Celeron's interface slot circumvented this, allowing a 100 MHz bus.
At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KB or 1 MB), but they carried the performance penalty of slower cache performance, typically running at FSB frequency of 60 to 100 MHz. The Pentium II's 512 KB of L2 cache was implemented with a pair of relatively high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's clock rate and communicating with the CPU through a special back-side bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.
Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The Mendocino Celeron CPU came only designed for a 66 MHz front-side bus, but this would not be a serious performance bottleneck until clock rates reached higher levels.
The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant; beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is they supported symmetric multiprocessing (SMP), and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.
The Mendocino also came in a mobile variant, with clock rates of 266, 300, 333, 366, 400, 433 and 466 MHz.
In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related "Dixon" Mobile Pentium II variant.
Coppermine-128.
The next generation Celeron was the " 'Coppermine-128' " (sometimes known as the "Celeron II"). These were a derivative of Intel's "Coppermine" Pentium III and were released on March 29, 2000. This Celeron used a Coppermine core with half of its L2 cache switched off, resulting in 128 KB of 4-way associative on-chip L2 cache as on the Mendocino, and was initially likewise restricted to a 66 MHz Front Side Bus speed. Despite the halved associativity on the L2 cache, which reduced hit rates compared to the full Coppermine design, it kept the 256-bit wide L2 cache bus, which meant an advantage compared to Mendocino and older Katmai/Pentium II designs, which all had a 64-bit datapath to their L2 caches. SSE instructions were also enabled.
All Coppermine-128s were produced in the same FCPGA Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533 MHz and continued through 566, 600, 633, 667, 700, 733, and 766 MHz. Because of the limitations of the 66 MHz bus, there were diminishing returns on performance as clock rates increased. On January 3, 2001, Intel switched to a 100 MHz bus with the launch of the 800 MHz Celeron, resulting in a significant performance-per-clock improvement. All Coppermine-128 CPUs from 800 MHz and higher use the 100 MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100 MHz.
In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526.
Tualatin-256.
These Celeron processors, released initially at 1.2 GHz on October 2, 2001, were based on the Pentium III 'Tualatin' core and made with a 0.13 micrometer process for the FCPGA 2 Socket 370. They were nicknamed "Tualeron" by some enthusiasts — a portmanteau of the words Tualatin and Celeron. Some software and users refer to the chips as "Celeron-S", referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1 GHz and 1.1 GHz parts (which were given the extension "A" to their name to differentiate them from the Coppermine-128 of the same clock rate they replaced). A 1.3 GHz chip, launched January 4, 2002, and finally a 1.4 GHz chip, launched May 15, 2002 (the same day as the 1.7 GHz Willamette-based Celeron launch), marked the end of the Tualatin-256 line.
The most significant differences compared to the Pentium III Tualatin are a lower 100 MHz bus and fixed 256 KB of L2 cache (whereas the Pentium III was offered with either 256 KB or 512 KB L2 cache); cache associativity stayed at 8-way, although the newly introduced data prefetching appears to have been disabled. Furthermore, the Tualatin-256's L2 cache has a higher latency which boosted manufacturing yields for this budget CPU. On the other hand, this improved stability when overclocking and most of them had no problem working at 133 MHz FSB for a substantial performance increase.
Despite offering much improved performance over the Coppermine Celeron it superseded, the Tualatin Celeron still suffered stiff competition from AMD's Duron budget processor. Intel later responded by releasing the Netburst Willamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with the Pentium 4-based Celerons that replaced them.
In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530.
NetBurst-based Celerons.
Willamette-128.
These Celerons were for socket 478 and were based on the "Willamette" Pentium 4 core, being a completely different design compared to the previous Tualatin Celeron. These are often known as the "Celeron 4". Their L2 cache (128 KB) is half that of the "Willamette"-based Pentium 4's 256 KB of L2 cache, but otherwise the two are very similar. With the transition to the Pentium 4 core the Celeron now featured SSE2 instructions. The ability to share the same socket as the Pentium 4 meant that the Celeron now had the option to use RDRAM, DDR SDRAM, or traditional SDRAM. Willamette Celerons were launched May 15, 2002, initially at 1.7 GHz, and offered a noticeable performance improvement over the older 1.3 GHz "Tualatin"-based Celeron part, being able to finally outperform a 1.3 GHz AMD Duron, which at the time was AMD's top competing budget processor. On June 12, 2002, Intel launched the last Willamette Celeron, a 1.8 GHz model. It contains 42 million transistors and has a die area of 217 mm2.
In Intel's "Family/Model/Stepping" scheme, Willamette Celerons and Pentium 4s are family 15, model 1, and their Intel product code is 80531.
Northwood-128.
These socket 478 Celerons are based on the "Northwood" Pentium 4 core, and also have 128 KB of L2 cache. The only difference between the "Northwood-128"-based and the "Willamette-128"-based Celeron is the fact that it was built on the new 130 nm process which shrank the die size, increased the transistor count, and lowered the core voltage from 1.7 V on the "Willamette-128" to 1.52 V for the "Northwood-128". Despite these differences, they are functionally the same as the Willamette-128 Celeron, and perform largely the same clock-for-clock. The "Northwood-128" family of processors were initially released as a 2 GHz core (a 1.9 GHz model was announced earlier, but never launched) on September 18, 2002. Since that time Intel has released at total of 10 different clock speeds ranging from 1.8 GHz to 2.8 GHz, before being surpassed by the Celeron D. Although the "Northwood"-based Celerons suffer considerably from their small L2 cache, some clock rates have been favored in the enthusiast market because, like the old 300A, they can run well above their specified clock rate.
In Intel's "Family/Model/Stepping" scheme, Northwood Celerons and Pentium 4s are family 15, model 2, and their Intel product code is 80532.
Prescott-256.
Prescott-256 Celeron D processors, initially launched June 25, 2004, featuring double the L1 cache (16 KB) and L2 cache (256 KB) as compared to the previous Willamette and Northwood desktop Celerons, by virtue of being based on the "Prescott" Pentium 4 core.
It also features a 533 MT/s bus and SSE3, and a 3xx model number (compared to 5xx for Pentium 4s and 7xx for Pentium Ms). The Prescott-256 Celeron D was manufactured for Socket 478 and LGA 775, with 3x0 and 3x5 designations from 310 through to 355 at clock speeds of 2.13 GHz to 3.33 GHz.
The Intel Celeron D processor works with the Intel 845 and 865 chipset families. The "D" suffix actually has no official designation, and does not indicate that these models are dual-core. It is used simply to distinguish this line of Celeron from the previous, lower performing Northwood and Willamette series, and also from the mobile series, the Celeron M (which also uses 3xx model numbers). Unlike the Pentium D, the Celeron D is "not" a dual core processor.
The Celeron D was a major performance improvement over previous NetBurst-based Celerons. A test using a variety of applications, run by Derek Wilson at Anandtech.com, showed that the new Celeron D architecture alone offered up performance improvements on average of >10% over a Northwood Celeron when both CPUs were run at the same bus and clock rate. This CPU also had the addition of SSE3 instructions and the higher FSB which only contributed to this already impressive gain.
Despite its many improvements, the "Prescott" core of the Celeron D had at least one major drawback heat. Unlike the fairly cool-running Northwood Celeron, the Prescott-256 had a class-rated TDP of 73 W, which prompted Intel to include a more intricate copper core/aluminum finned cooler to help handle the additional heat.
In mid-2005, Intel refreshed the Celeron D with Intel 64 and XD Bit (eXecute Disable) enabled. Model numbers increase by 1 over the previous generation (e.g., 330 became 331). This only applied to LGA 775 Celeron Ds. There are no Socket 478 CPUs with XD Bit capabilities.
In Intel's "Family/Model/Stepping" scheme, Prescott Celeron Ds and Pentium 4s are family 15, model 3 (up to stepping E0) or 4 (stepping E0 onwards), and their Intel product code is 80546 or 80547, depending on socket type.
Cedar Mill-512.
Based on the "Cedar Mill" Pentium 4 core, this version of the Celeron D was launched May 28, 2006, and continued the 3xx naming scheme with the Celeron D 347 (3.06 GHz), 352 (3.2 GHz), 356 (3.33 GHz), 360 (3.46 GHz), and 365 (3.6 GHz). The Cedar Mill Celeron D is largely the same as the Prescott-256, except with double the L2 cache (512 KB) and based on a 65 nm manufacturing process. The Cedar Mill-512 Celeron D is LGA 775 exclusive. The main benefits of the Cedar Mill Celerons over the Prescott Celerons are the slightly increased performance due to the larger L2 cache, higher clock rates, and less heat dissipation, with several models having a TDP lowered to 65 W from Prescott's lowest offering of 73 W.
In Intel's "Family/Model/Stepping" scheme, Cedar Mill Celeron Ds and Pentium 4s are family 15, model 6, and their Intel product code is 80552.
Core-based Celerons.
Conroe-L.
The Conroe-L Celeron is a single-core processor built on the Core microarchitecture and is thus clocked much lower than the Cedar Mill Celerons, but still outperforms them. It is based on the 65 nm Conroe-L core, and uses a 400-series model number sequence. The FSB was increased to 800 MT/s from 533 MT/s in this generation, and the TDP was decreased from 65 W to 35 W. As is traditional with Celerons, it does not have Intel VT-x instruction support or SpeedStep (although Enhanced Halt State is enabled, allowing the Celerons to lower the multiplier to 6× and decrease core voltage while idle). All Conroe-L models are single-core processors for the value segment of the market, much like the AMD K8-based Sempron. The product line was launched on June 5, 2007.
On October 21, 2007, Intel presented a new processor for its Intel Essential Series. The full name of the processor is Celeron 220 and is soldered on the D201GLY2 motherboard. With 1.2 GHz and a 512 KB L2 cache it has a TDP of 19 W and can be cooled passively. The Celeron 220 is the successor of the Celeron 215 which is based on a Yonah core and used on the D201GLY motherboard. This processor is exclusively used on the mini-ITX boards targeted to the sub-value market segment.
Allendale.
Intel launched the dual core Celeron E1xxx processor line on January 20, 2008, based on the Allendale core. The CPU has 800 MT/s FSB, 65 W TDP and uses 512 KB of the chip's 2 MB L2 cache, significantly limiting performance for uses such as gaming. New features to the Celeron family included full enhanced halt state and enhanced Intel SpeedStep technology. Clock rates range from 1.6 GHz to 2.4 GHz. It is compatible with other Allendale-based CPUs such as the Core 2 Duo E4xxx and Pentium Dual-Core E2xxx.
Wolfdale-3M.
The Celeron E3000 series, starting with E3200 and E3300, was released in August 2009, featuring the Wolfdale-3M core used in Pentium Dual-Core E5000, Pentium E6000 and Core 2 Duo E7000 series. The main difference to Allendale-based Celeron processors is the support for Intel VT-x and increased performance due to the double L2 Cache of 1 MB.
Nehalem-based Celerons.
Clarkdale.
With the introduction of the Desktop Core i3 and Core i5 processor code named "Clarkdale" in January 2010, Intel also added a new Celeron line, starting with the Celeron G1101. This is the first Celeron to come with on-chip PCI Express and integrated graphics. Despite using the same Clarkdale chip as the Core i5-6xx line, it does not support Turbo Boost, HyperThreading, VT-d, SMT, Trusted Execution Technology or AES new instructions, and it comes with only 2 MB of third-level cache enabled.
Jasper Forest.
The Celeron P1053 is an embedded processor for Socket 1366 from the "Jasper Forest" family. All other members of this family are known as Xeon C35xx or C55xx. The Jasper Forest chip is closely related to Lynnfield and contains four cores, 8 MB of L3 cache and a QPI interface, but most of these are disabled in the Celeron version, leaving a single core with 2 MB of L3 cache.
Sandy Bridge-based desktop Celerons.
The Sandy Bridge-based Celeron processors were released in 2011. They are LGA 1155 processors (available in single- and dual-core versions) with integrated Intel HD Graphics GPU and containing up to 2 MB of L3 cache. Turbo-Boost, AVX and AES-NI have been disabled. Hyper-Threading is available on some single-core models, namely G460, G465 and G470.
Ivy Bridge-based desktop Celerons.
All Celerons of this generation belong in the G16xx series. They give some boost in performance over Sandy Bridge-based Celerons due to a 22 nm die shrink, as well as some other minor improvements.
Skylake-based desktop Celerons.
All Celerons of this generation added AES-NI and RDRAND instruction set.
Mobile Celerons.
P6-based mobile Celerons.
Mendocino (mobile).
Similar to the Mendocino (Celeron-A): 0.25 μm, 32 KB L1 cache and 128 KB L2 cache, but uses a lower voltage (1.5–1.9 V) and two power-saving modes: Quick Start, and Deep Sleep. Packaged in the small, 615-pin BGA2 or Micro-PGA2 package.
Tualatin-256 (mobile).
These were the first Mobile Celerons based on the Tualatin core. They differed from their desktop counterparts in that the Mobile series were offered in both 100 MHz and 133 MHz FSB. Like the desktop Tualatins, these chips had 256 KB of L2 cache.
NetBurst-based mobile Celerons.
Northwood-256.
These are the Mobile Celeron range used in laptops. Also based on the Northwood core, they feature a 256 KB L2 cache. These Celeron processors were a good deal higher performing than the desktop counterparts because of their larger L2 cache sizes. They were eventually replaced by the Celeron M brand which is built around the Pentium M processor design.
Pentium M-based mobile Celerons.
Banias-512.
This Celeron (sold under the Celeron M brand) is based on the "Banias" Pentium M, and differs from its parent in that it has half the L2 cache, and does not support the clock-varying SpeedStep technology. It performs reasonably well compared to the Pentium M, but battery life is noticeably shorter on a Celeron M–based notebook than it is on a comparable Pentium M notebook.
A system based on the Celeron M processor may not use the Centrino brand name, regardless of what chipset and Wi-Fi components are used.
In Intel's "Family/Model/Stepping" scheme, Banias Celeron Ms and Pentium Ms are family 6, model 9 and their Intel product code is 80535.
Shelton.
The "Shelton" core is a Banias core without "any" L2 cache and SpeedStep. It is used in Intel's small form factor D845GVSH motherboard, intended for Asian and South American markets. The processor identifies itself as a "Intel Celeron 1.0B GHz", to differentiate it from the previous Coppermine-128 and Tualatin 1.0 GHz processors.
The Shelton'08 is a basic platform for a low cost notebook released by Intel at January 2008. The platform uses Intel's single-core Diamondville CPU with a clock frequency of 1.6 GHz and a 533 MT/s FSB and power consumption of 3.5 W. The platform's total power consumption is around 8 W, translating to battery usage time of between 3–4 hours. The platform consists of a 945GSE chipset, which includes built-in DirectX 9 graphics and supports single channel DDR2 memory. An 802.11g Wi-Fi module, USB/PATA port SSD (solid state drive), and a 7- or 8-inch panel will typically round out the platform.
Dothan-1024.
A 90 nm Celeron M with half of the L2 cache of the 90 nm "Dothan" Pentium Ms (twice the L2 cache of the 130 nm Celeron Ms, though), and, like its predecessor, lacking SpeedStep. The first Celeron Ms that supports the XD bit was released in January 2005, in general any Celeron M released after that supports the XD bit. There is also a 512 KB low voltage version that was used in the early ASUS Eee PC models.
In Intel's "Family/Model/Stepping" scheme, Dothan Celeron Ms and Pentium Ms are family 6, model 13 and their Intel product code is 80536.
Yonah.
The Celeron M 400-series is a 65 nm Celeron M based on the single-core Yonah chip, like the Core Solo. Like its predecessors in the Celeron M series, this Celeron M has half of the L2 cache (1 MB) of Core Solo and lacks SpeedStep. This core also brings new features to Celeron M including a higher front side bus (533 MT/s), SSE3 instructions. September 2006 and January 4, 2008, mark a discontinuation of many "Celeron M" branded CPUs.
Core-based mobile Celerons.
Merom-L.
The Celeron M 523 (933 MHz ULV), M 520 (1.6 GHz), M 530 (1.73 GHz), 530 (1.73 GHz), 540 (1.86 GHz), 550 (2.0 GHz), 560 (2.13 GHz), 570 (2.26 GHz) are single-core 65 nm CPUs based on the "Merom" Core 2 architecture. They feature a 533 MT/s FSB, 1 MB of L2 cache (half that of the low end Core 2 Duo's 2 MB cache), XD-bit support, and Intel 64 technology, but lack SpeedStep and Virtualization Technology. Two different processor models are used with identical part numbers with the same part numbers, single-core Merom-L with 1 MB cache and dual-core Merom with 4 MB L2 cache that have the extra cache and core disabled. Celeron M 523, M 520 and M 530 are Socket M-based, while Celeron 530 through 570 (without the M) are for Socket P. January 4, 2008, marked the discontinuation of Merom CPUs.
Merom-2M.
The Celeron 573 (1 GHz, ULV), 575 (2 GHz) and 585 (2.16 GHz) are based on the Merom-2M core with only one core and 1 MB L2 cache enabled. They are similar to the Merom and Merom-L based Celerons but have a faster 667 MT/s FSB.
The Celeron T1xxx processors are also based on the Merom-2M chips but have both cores enabled. The earlier T1400 (1.73 GHz) and T1500 (1.86 GHz) versions have a 533 MT/s FSB and 512 B L2 cache, while the more recent T1600 (1.66 GHz) and T1700 (1.83 GHz) versions have 667 MT/s and 1 MB L2 cache enabled but come with a lower clock frequency.
Penryn-3M.
At the same time as the dual-core Merom-2M, Intel introduced the first 45 nm Celeron processor based on the Penryn-3M core with 800 MT/s FSB, 1 MB L2 cache and one core enabled. This includes the Celeron M 7xx Consumer Ultra-Low Voltage (CULV) series starting at 1.2 GHz and the later Celeron 900 (2.2 GHz).
The initial 45 nm dual-core Celeron processor was released in June 2009 and is also based on Penryn-3M. The Celeron T3000 (1.8 GHz) and T3100 (1.9 GHz) again come with 1 MB of L2 cache enabled and an 800 MT/s FSB. In September 2009, Intel also started the dual-core CULV Celeron SU2000 series, again with 1 MB L2 cache. Despite the similar name, they are very different from Pentium SU2000 (with 2 MB L2 cache and one active core) and Pentium T3000 (based on the 65 nm Merom processor).
Nehalem-based mobile Celerons.
Arrandale.
The Arrandale-based Celeron P4xxx and U3xxx lines are low-end versions of the Pentium P6xxx and U5xxx lines, originally released as the mobile dual-core lines of Core i3/i5/i7. Like the Clarkdale-based Celeron G1xxx, they use 2 MB of L3 cache, which is the amount that the earlier "Penryn" based CPUs used in the Pentium brand as their L2 cache. Like all Arrandale processors, the Celeron P4xxx and U3xxx use an integrated graphics core.
Sandy Bridge-based mobile Celerons.
The Celeron B8xx processors released in 2011 follow the Arrandale line. They are Dual-Core processors with integrated graphics and use the same chips as the Pentium B9xx and Core i3/i5/i7-2xxx mobile processors, but with Turbo-Boost, Hyper-Threading, VT-d, TXT and AES-NI disabled and the L3 cache reduced to 2MB.
Dual-processor support.
As a budget processor, the Celeron does not support a dual-processor configuration using multiple CPU sockets, however it has been discovered that multiprocessing could be enabled on Slot 1 Celeron processors by connecting a pin on the CPU core to a contact on the processor card's connector. In addition, Mendocino Socket 370 processors can use multiprocessing when used on specific dual Slot 1 motherboards by using a slot adapter.
The unofficial SMP support was removed in the Coppermine Celerons, and dual-socket support is now limited to higher-end Xeon server-class processors. Conroe/Allendale based Celeron processors and later support multiprocessing using multi-core chips, but are still limited to one socket.
The ABIT BP6 motherboard also allows two Mendocino Socket 370 Celeron processors to operate in a symmetric multiprocessing (SMP) configuration without any modification to the CPUs or the motherboard.


Super NES Classic Edition

The Super Nintendo Entertainment System: Super NES Classic Edition, known as the Nintendo Classic Mini: Super Nintendo Entertainment System in Europe and Australia and the in Japan, and also colloquially as the SNES Mini or SNES Classic, is a dedicated home video game console released by Nintendo, which emulates the Super Nintendo Entertainment System. The console, a successor to the NES Classic Edition, comes with twenty-one Super NES titles pre-installed, including the first official release of "Star Fox 2". It was released in North America and Europe on September 29, 2017.
Hardware.
The console is distributed in three variations, featuring the unique design of the original systems released in Japan, North America, and Europe respectively. While the North American release features an appearance based on the straight-angled grey-and-purple design of the Super NES, the Japan and PAL region releases are modelled after the rounded edge Super Famicom/PAL Super NES design as originally released in these regions.
Internally, the console uses an Allwinner R16 system on a chip with four ARM Cortex-A7 central processing units, an ARM Mali 400 MP2 graphics processing unit, and 512 MB of flash storage and 256 MB of DDR3 memory. The same hardware was used in the previous NES Classic Edition product.
The system features 720p/60 Hz HDMI display output and two controller ports; two wired SNES controllers are bundled with the system. The controller ports are hidden behind a faux front flap which is designed to appear like the original Super NES controller ports. Similarly to the predecessor's controllers, the Super NES Classic Edition controllers have connectors that can be inserted into the Wii Remote, and be used to play Super NES games on the Wii and Wii U Virtual Console. The Wii's Classic Controller is also compatible with the Super NES Classic Edition. While the NES Classic Edition controller is technically functional with the Super NES Classic Edition, gameplay is impractical in most games due to the absence of the X and Y face buttons and the shoulder buttons.
The console uses the Linux operating system and runs a set of emulators developed by Nintendo's European Research & Development (NERD). These emulators provide the basic compatibility with the Super NES system, and for specific games, chipsets that were included on the cartridges, such as the Super FX chip used for "Star Fox".
The Super NES Classic Edition includes two controllers with cables, addressing complaints about the short ones used for the NES Classic.
Hacking.
An anonymous user who previously discovered a means to hack the NES Classic Edition discovered a similar hacking ability to install additional SNES games onto the unit. Not all SNES games can work due to missing emulation of custom cartridge chipsets.
Games.
The microconsole contains 21 built-in games. These include "Star Fox 2", a sequel to "Star Fox" that had been cancelled near the very end of its development in 1996; while Nintendo had given no official word to the cancellation, developer Dylan Cuthbert said that Nintendo feared how "Star Fox 2" would look compared to similar games on the more advanced PlayStation and Sega Saturn consoles. Players can unlock "Star Fox 2" on the SNES Classic upon clearing the first level of "Star Fox".
Despite the fact that the hardware shells are different, both western editions of the microconsole feature identical software, and all included games are based on their American localizations, running at 60 Hz, similarly to the NES Classic Edition. Consequently, games that originally had different titles in the PAL regions now use their respective American monikers, such as "Contra III: The Alien Wars" (originally "Super Probotector: Alien Rebels"), "Star Fox" (originally "Starwing") and "Kirby Super Star" (originally "Kirby's Fun Pak").
From the 21 included titles, 16 are common between all regions, while the five remaining ones are exclusive to either Japan or North America/PAL region respectively.
Release.
The Super NES Classic Edition was revealed on June 26, 2017, as the successor to the widely-popular NES Classic. Nintendo announced that the system would come with 21 Super Nintendo games, including the unreleased "Star Fox 2". It was released in North America on September 29, 2017 with a price of $79.99.
Criticism of availability.
With the release of the NES Classic Edition, Nintendo was strongly criticized for the system's lack of availability for the console, which reached levels of popularity that they had not been fully prepared for. On July 21, 2017, the console was mistakenly made available for pre-order at Walmart in the United States due to a "technical glitch", and all pre-orders were cancelled on July 26, leading to widespread criticism among the gaming press. "PC Magazine" called the situation "badly handled by Walmart" and said that the future availability of the console was "not looking good". "USGamer" called attempting to obtain a Super NES Classic Edition a "waking nightmare" and stated the availability would likely be as low as the NES Classic, saying the situation was "because we can't have nice things". "GameSpot" stated that there was "frustratingly little word" from Nintendo as to when pre-orders would be made available. Nintendo gave no comment about the situation.
On August 22, 2017, pre-orders officially opened at several major retailers, causing many of their sites to crash before customers could buy the system, as well as at physical GameStop locations in limited amounts, which also sold out quickly on a first-come, first-served basis. The Target website became "glitched out", removing the items from users' carts, and pre-orders from Walmart were sold out in less than a minute. This led to Nintendo of America being criticized as "inept or underhanded", and that they contributed to a "chaotic" situation.
"Polygon" also confirmed that the Tai Ding internet bot was being used to quickly pre-order systems before humans could get the chance to order them, which was proving successful due to a lack of CAPTCHAs on store websites. Scalpers soon flooded eBay with pre-order listings, some at markups of over 300%.
Nintendo of America CEO Reggie Fils-Aimé stated in September 2017 that people should not buy SNES Classic pre-orders from scalpers, and suggested SNES Classics would be readily available. He also stated that the company was not trying to create artificial scarcity, saying that the issues with pre-orders were "outside our control". Nintendo has also stated that there would be more SNES Classics available on launch day than the entire amount of NES Classics that were shipped in 2016, and that shipments would continue into 2018 unlike originally planned due to high demand.
With the Super NES Classic Edition, Nintendo originally said that although they were prepared to produce significantly more Super NES Classics than NES Classics, they would be halting production at the end of 2017. Due to overwhelming demand, Nintendo changed their plans, with Reggie Fils-Aimé confirming the continued production of the system throughout 2018 alongside announcing the return of the NES Classic in 2018, which many people were unable to get after scalpers bought masses of them and resold them for much more than their MSRP. Fils-Aimé also discouraged consumers from buying from these scalpers and said there would be plenty stock of both NES and SNES. In May 2018, Nintendo of America announced via Twitter that both consoles would be in stock throughout the second half of 2018, with the NES Classic returning to stores on June 29.
On December 13, 2018, Reggie Fils-Aimé affirmed that both the NES and SNES Classic Editions will not be restocked after the 2018 holiday season, nor does Nintendo anticipate producing any similar mini-console version of its other home consoles in the future.
Reception.
Despite slightly criticizing its library of titles and issues carried over from the NES Classic, "IGN"'s Jonathon Dornbush praised the Super NES Classic's features and enjoyability. "Eurogamer" praised the games library, the selection of border arts, the improved scaling over the NES Classic Mini, and the support of 60 Hz as well as the fact that there are now two controllers with longer cables in the scope of delivery in contrast to the NES Classic Mini. "Eurogamer" also claimed that the emulation of the SNES Classic Mini is superior to that of the Virtual Console. "IGN" rated the SNES Classic Mini 8.5 out of 10 points, praising the included games, the image quality, the longer cables and the rewind feature.
Sales.
The SNES Mini sold 368,913 units within its first four days on sale in Japan. By the end of October 2017, it had sold more than 2 million units worldwide. By its fiscal year 2017 report, ending March 31, 2018, the SNES Classic had sold more than 5 million units. Combined sales of the NES and SNES Classic editions by September 30, 2018 exceeded 10 million units.
Future.
According to Nintendo, there are currently no plans for a Nintendo 64 Classic Mini. Doug Bowser, current President of Nintendo of America, said that "Our focus right now is absolutely on our dedicated platforms such as Nintendo Switch Lite and our flagship Nintendo Switch." Reggie Fils-Aimé said "For us, these were limited time opportunities that were a way for us as a business to bridge from the conclusion of Wii U as a hardware system to the launch of Nintendo Switch. That was the very strategic reason we launched the NES Classic system."
There are rumors that Nintendo will release a Game Boy Classic Mini.


Bootloader

A bootloader is software that is responsible for booting a computer.
When a computer is turned off, its softwareincluding operating systems, application code, and dataremains stored on non-volatile memory. When the computer is powered on, it typically does not have an operating system or its loader in random-access memory (RAM). The computer first executes a relatively small program stored in read-only memory (ROM) along with a small amount of needed data, to access the nonvolatile device or devices from which the operating system programs and data can be loaded into RAM.
The small program that starts this sequence is known as a bootstrap loader, bootstrap or boot loader. This small program's only job is to load other data and programs which are then executed from RAM. Often, multiple-stage boot loaders are used, during which several programs of increasing complexity load one after the other in a process of chain loading.
Some computer systems, upon receiving a boot signal from a human operator or a peripheral device, may load a very small number of fixed instructions into memory at a specific location, initialize at least one CPU, and then point the CPU to the instructions and start their execution. These instructions typically start an input operation from some peripheral device (which may be switch-selectable by the operator). Other systems may send hardware commands directly to peripheral devices or I/O controllers that cause an extremely simple input operation (such as "read sector zero of the system device into memory starting at location 1000") to be carried out, effectively loading a small number of boot loader instructions into memory; a completion signal from the I/O device may then be used to start execution of the instructions by the CPU.
Smaller computers often use less flexible but more automatic boot loader mechanisms to ensure that the computer starts quickly and with a predetermined software configuration. In many desktop computers, for example, the bootstrapping process begins with the CPU executing software contained in ROM (for example, the BIOS of an IBM PC or an IBM PC compatible) at a predefined address (some CPUs, including the Intel x86 series are designed to execute this software after reset without outside help). This software contains rudimentary functionality to search for devices eligible to participate in booting, and load a small program from a special section (most commonly the boot sector) of the most promising device, typically starting at a fixed entry point such as the start of the sector.
First-stage boot loader.
Boot loaders may face peculiar constraints, especially in size; for instance, on the IBM PC and compatibles, a boot sector should typically work in only 32 KB (later relaxed to 64 KB) of system memory and only use instructions supported by the original 8088/8086 processors. The first stage of PC boot loaders (FSBL, first-stage boot loader) located on fixed disks and removable drives must fit into the first 446 bytes of the Master Boot Record in order to leave room for the default 64-byte partition table with four partition entries and the two-byte boot signature, which the BIOS requires for a proper boot loader — or even less, when additional features like more than four partition entries (up to 16 with 16 bytes each), a disk signature (6 bytes), a disk timestamp (6 bytes), an Advanced Active Partition (18 bytes) or special multi-boot loaders have to be supported as well in some environments. In floppy and superfloppy Volume Boot Records, up to 59 bytes are occupied for the Extended BIOS Parameter Block on FAT12 and FAT16 volumes since DOS 4.0, whereas the FAT32 EBPB introduced with DOS 7.1 requires even 87 bytes, leaving only 423 bytes for the boot loader when assuming a sector size of 512 bytes. Microsoft boot sectors therefore traditionally imposed certain restrictions on the boot process, for example, the boot file had to be located at a fixed position in the root directory of the file system and stored as consecutive sectors, conditions taken care of by the codice_1 command and slightly relaxed in later versions of DOS. The boot loader was then able to load the first three sectors of the file into memory, which happened to contain another embedded boot loader able to load the remainder of the file into memory. When Microsoft added LBA and FAT32 support, they even switched to a boot loader reaching over "two" physical sectors and using 386 instructions for size reasons. At the same time other vendors managed to squeeze much more functionality into a single boot sector without relaxing the original constraints on only minimal available memory (32 KB) and processor support (8088/8086). For example, DR-DOS boot sectors are able to locate the boot file in the FAT12, FAT16 and FAT32 file system, and load it into memory as a whole via CHS or LBA, even if the file is not stored in a fixed location and in consecutive sectors.
BIOS (in x86 systems) and UEFI not only load the operating system from a non-volatile device, they also initialize system hardware for operating system.
Examples of first-stage bootloaders include BIOS, coreboot, Libreboot and Das U-Boot.
Second-stage boot loader.
Second-stage boot loaders, such as GNU GRUB, rEFInd, BOOTMGR, Syslinux, NTLDR or BootX, are not themselves operating systems, but are able to load an operating system properly and transfer execution to it; the operating system subsequently initializes itself and may load extra device drivers. The second-stage boot loader does not need drivers for its own operation, but may instead use generic storage access methods provided by system firmware such as the BIOS or Open Firmware, though typically with restricted hardware functionality and lower performance.
Many boot loaders (like GNU GRUB, rEFInd, Windows's BOOTMGR, Syslinux, and Windows NT/2000/XP's NTLDR) can be configured to give the user multiple booting choices. These choices can include different operating systems (for dual or multi-booting from different partitions or drives), different versions of the same operating system (in case a new version has unexpected problems), different operating system loading options (e.g., booting into a rescue or safe mode), and some standalone programs that can function without an operating system, such as memory testers (e.g., memtest86+), a basic shell (as in GNU GRUB), or even games (see List of PC Booter games). Some boot loaders can also load other boot loaders; for example, GRUB loads BOOTMGR instead of loading Windows directly. Usually, a default choice is preselected with a time delay during which a user can press a key to change the choice; after this delay, the default choice is automatically run so normal booting can occur without interaction.
The boot process can be considered complete when the computer is ready to interact with the user, or the operating system is capable of running system programs or application programs.
Many embedded systems must boot immediately. For example, waiting a minute for a digital television or a GPS navigation device to start is generally unacceptable. Therefore, such devices have software systems in ROM or flash memory so the device can begin functioning immediately; little or no loading is necessary, because the loading can be precomputed and stored on the ROM when the device is made.
Large and complex systems may have boot procedures that proceed in multiple phases until finally the operating system and other programs are loaded and ready to execute. Because operating systems are designed as if they never start or stop, a boot loader might load the operating system, configure itself as a mere process within that system, and then irrevocably transfer control to the operating system. The boot loader then terminates normally as any other process would.
Network booting.
Most computers are also capable of booting over a computer network. In this scenario, the operating system is stored on the disk of a server, and certain parts of it are transferred to the client using a simple protocol such as the Trivial File Transfer Protocol (TFTP). After these parts have been transferred, the operating system takes over the control of the booting process.
As with the second-stage boot loader, network booting begins by using generic network access methods provided by the network interface's boot ROM, which typically contains a Preboot Execution Environment (PXE) image. No drivers are required, but the system functionality is limited until the operating system kernel and drivers are transferred and started. As a result, once the ROM-based booting has completed it is entirely possible to network boot into an operating system that itself does not have the ability to use the network interface.


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List of television programs broadcast by Xbox Live

This is a list of programs currently and soon to be broadcast by Xbox Live; most are viewed via IPTV or video on demand applications (such as sporting events via the ESPN application), while others, such as "Majors Minute", are streamed by Xbox Live. However, most events are not available in all regions.
Sports.
Tennis.
Other.
Xbox Live simulcasts the ATP Masters 1000 tournaments in Indian Wells, Miami, Toronto/Montreal and Cincinnati.
Former programs.
On May 2, 2012, it was announced that Inside Xbox would be discontinued to focus more on its entertainment features.


Grayscale

In digital photography, computer-generated imagery, and colourimetry, a greyscale or image is one in which the value of each pixel is a single sample representing only an "amount" of light; that is, it carries only intensity information. Greyscale images, a kind of black-and-white or grey monochrome, are composed exclusively of shades of grey. The contrast ranges from black at the weakest intensity to white at the strongest.
Greyscale images are distinct from one-bit bi-tonal black-and-white images, which, in the context of computer imaging, are images with only two colours: black and white (also called "bilevel" or "binary images"). Greyscale images have many shades of grey in between.
Greyscale images can be the result of measuring the intensity of light at each pixel according to a particular weighted combination of frequencies (or wavelengths), and in such cases they are monochromatic proper when only a single frequency (in practice, a narrow band of frequencies) is captured. The frequencies can in principle be from anywhere in the electromagnetic spectrum (e.g. infrared, visible light, ultraviolet, etc.).
A colourimetric (or more specifically photometric) greyscale image is an image that has a defined greyscale colourspace, which maps the stored numeric sample values to the achromatic channel of a standard colourspace, which itself is based on measured properties of human vision.
If the original colour image has no defined colourspace, or if the greyscale image is not intended to have the same human-perceived achromatic intensity as the colour image, then there is no unique mapping from such a colour image to a greyscale image.
Numerical representations.
The intensity of a pixel is expressed within a given range between a minimum and a maximum, inclusive. This range is represented in an abstract way as a range from 0 (or 0%) (total absence, black) and 1 (or 100%) (total presence, white), with any fractional values in between. This notation is used in academic papers, but this does not define what "black" or "white" is in terms of colourimetry. Sometimes the scale is reversed, as in printing where the numeric intensity denotes how much ink is employed in halftoning, with 0% representing the paper white (no ink) and 100% being a solid black (full ink).
In computing, although the greyscale can be computed through rational numbers, image pixels are usually quantized to store them as unsigned integers, to reduce the required storage and computation. Some early greyscale monitors can only display up to sixteen different shades, which would be stored in binary form using 4 bits. But today greyscale images (such as photographs) intended for visual display (both on screen and printed) are commonly stored with 8 bits per sampled pixel. This pixel depth allows 256 different intensities (i.e., shades of grey) to be recorded, and also simplifies computation as each pixel sample can be accessed individually as one full byte. However, if these intensities were spaced equally in proportion to the amount of physical light they represent at that pixel (called a linear encoding or scale), the differences between adjacent dark shades could be quite noticeable as banding artifacts, while many of the lighter shades would be "wasted" by encoding a lot of perceptually-indistinguishable increments. Therefore, the shades are instead typically spread out evenly on a gamma-compressed nonlinear scale, which better approximates uniform perceptual increments for both dark and light shades, usually making these 256 shades enough (just barely) to avoid noticeable increments.
Technical uses (e.g. in medical imaging or remote sensing applications) often require more levels, to make full use of the sensor accuracy (typically 10 or 12 bits per sample) and to reduce rounding errors in computations. Sixteen bits per sample (65,536 levels) is often a convenient choice for such uses, as computers manage 16-bit words efficiently. The TIFF and PNG (among other) image file formats support 16-bit greyscale natively, although browsers and many imaging programs tend to ignore the low order 8 bits of each pixel. Internally for computation and working storage, image processing software typically uses integer or floating-point numbers of size 16 or 32 bits.
Converting colour to greyscale.
Conversion of an arbitrary colour image to greyscale is not unique in general; different weighting of the colour channels effectively represent the effect of shooting black-and-white film with different-coloured photographic filters on the cameras.
Colourimetric (perceptual luminance-preserving) conversion to greyscale.
A common strategy is to use the principles of photometry or, more broadly, colourimetry to calculate the greyscale values (in the target greyscale colourspace) so as to have the same luminance (technically relative luminance) as the original colour image (according to its colourspace). In addition to the same (relative) luminance, this method also ensures that both images will have the same absolute luminance when displayed, as can be measured by instruments in its SI units of candelas per square meter, in any given area of the image, given equal whitepoints. Luminance itself is defined using a standard model of human vision, so preserving the luminance in the greyscale image also preserves other perceptual lightness measures, such as (as in the 1976 CIE "L"ab colour space) which is determined by the linear luminance itself (as in the CIE 1931 "XYZ" colour space) which we will refer to here as to avoid any ambiguity.
To convert a colour from a colourspace based on a typical gamma-compressed (nonlinear) RGB colourmodel to a greyscale representation of its luminance, the gamma compression function must first be removed via gamma expansion (linearization) to transform the image to a linear RGB colourspace, so that the appropriate weighted sum can be applied to the linear colour components (formula_1) to calculate the linear luminance , which can then be gamma-compressed back again if the greyscale result is also to be encoded and stored in a typical nonlinear colourspace.
For the common sRGB colour space, gamma expansion is defined as
where represents any of the three gamma-compressed sRGB primaries (, , and , each in range [0,1]) and is the corresponding linear-intensity value (, , and , also in range [0,1]). Then, linear luminance is calculated as a weighted sum of the three linear-intensity values. The sRGB colour space is defined in terms of the CIE 1931 linear luminance , which is given by
These three particular coefficients represent the intensity (luminance) perception of typical trichromat humans to light of the precise Rec. 709 additive primary colours (chromaticities) that are used in the definition of sRGB. Human vision is most sensitive to green, so this has the greatest coefficient value (0.7152), and least sensitive to blue, so this has the smallest coefficient (0.0722). To encode greyscale intensity in linear RGB, each of the three colour components can be set to equal the calculated linear luminance formula_4 (replacing formula_1 by the values formula_6 to get this linear greyscale), which then typically needs to be gamma compressed to get back to a conventional non-linear representation. For sRGB, each of its three primaries is then set to the same gamma-compressed given by the inverse of the gamma expansion above as
Because the three sRGB components are then equal, indicating that it is actually a grey image (not colour), it is only necessary to store these values once, and we call this the resulting greyscale image. This is how it will normally be stored in sRGB-compatible image formats that support a single-channel greyscale representation, such as JPEG or PNG. Web browsers and other software that recognizes sRGB images should produce the same rendering for such a greyscale image as it would for a "colour" sRGB image having the same values in all three colour channels.
Luma coding in video systems.
For images in colour spaces such as Y'UV and its relatives, which are used in standard colour TV and video systems such as PAL, SECAM, and NTSC, a nonlinear luma component is calculated directly from gamma-compressed primary intensities as a weighted sum, which, although not a perfect representation of the colourimetric luminance, can be calculated more quickly without the gamma expansion and compression used in photometric/colourimetric calculations. In the Y'UV and Y'IQ models used by PAL and NTSC, the rec601 luma component is computed as
where we use the prime to distinguish these nonlinear values from the sRGB nonlinear values (discussed above) which use a somewhat different gamma compression formula, and from the linear RGB components. The ITU-R BT.709 standard used for HDTV developed by the ATSC uses different colour coefficients, computing the luma component as
Although these are numerically the same coefficients used in sRGB above, the effect is different because here they are being applied directly to gamma-compressed values rather than to the linearized values. The ITU-R BT.2100 standard for HDR television uses yet different coefficients, computing the luma component as
Normally these colourspaces are transformed back to nonlinear R'G'B' before rendering for viewing. To the extent that enough precision remains, they can then be rendered accurately.
But if the luma component Y' itself is instead used directly as a greyscale representation of the colour image, luminance is not preserved: two colours can have the same luma but different CIE linear luminance (and thus different nonlinear as defined above) and therefore appear darker or lighter to a typical human than the original colour. Similarly, two colours having the same luminance (and thus the same ) will in general have different luma by either of the luma definitions above.
Greyscale as single channels of multichannel colour images.
Colour images are often built of several stacked colour channels, each of them representing value levels of the given channel. For example, RGB images are composed of three independent channels for red, green and blue primary colour components; CMYK images have four channels for cyan, magenta, yellow and black ink plates, etc.
Here is an example of colour channel splitting of a full RGB colour image. The column at left shows the isolated colour channels in natural colours, while at right there are their greyscale equivalences:
The reverse is also possible: to build a full colour image from their separate greyscale channels. By mangling channels, using offsets, rotating and other manipulations, artistic effects can be achieved instead of accurately reproducing the original image.
Greyscale modes.
Some operating systems offer a greyscale mode. It may be bound to a hotkey or this could be programmable.
It is also possible to install a greyscale mode extension in some browsers.