Cars (video game)

Cars (also known as Cars: The Video Game) is an open world racing video game, based on the 2006 Pixar film of the same name. Developed by Rainbow Studios, it was released for the GameCube, PlayStation 2, Xbox, Microsoft Windows, Game Boy Advance, Nintendo DS, and PSP in June 2006, with versions for the Xbox 360 and Wii released later that year. The Wii version includes functionality geared towards its Wii Remote controller, and was a launch game for the system.
Taking place after the events of the film, the player controls protagonist Lightning McQueen as he participates in the new racing season with the end goal of winning the Piston Cup for the first time in his career, while also racing and training with the local community of Radiator Springs. In the PSP version, the player controls Lightning McQueen. After meeting and almost colliding with the Delinquent Road Hazards gang, he challenges them to a race to which they agree. The consoles versions feature the full the voice-over cast from the film, including the likes of Owen Wilson, Michael Keaton, Paul Newman, and Larry the Cable Guy. However in the PSP and DS versions, Lightning McQueen is instead voiced by Keith Ferguson.
The home console and PC versions received generally positive reviews from critics, though the GBA version saw negative reception. The game was followed by two sequels; "Cars Mater-National Championship" (2007) and "Cars Race-O-Rama" (2009).
Gameplay.
The console versions of the game are set in the fictional town of Radiator Springs, where it takes place after the movie. The player must compete in 19 road races, 8 mini-games, and 5 piston cup races to help Lightning McQueen win his first Piston Cup. In the PSP version, the game presumably takes place between the events of the movie and the events of the other versions, or on an alternate timeline. The player must compete in 13 races, as well as 5 boss races, to help Lightning McQueen kick Chick Hicks' crew out of Radiator Springs. The game takes place in a sand box environment in the vein of "Need for Speed", "Grand Theft Auto" and "Midnight Club" and features ten playable characters from the film, all voiced by the original voice talent. The game also features a number of minigames and items for the player to collect.
Reception.
"Cars" received generally positive reviews. "GameSpot" gave 7.0 out of 10 for Xbox 360 and Wii versions, 7.6 out of 10 for the GameCube and Xbox versions, and 7.4 out of 10 for the PSP version. Metacritic gave 65 out of 100 for the Wii version, 54 out of 100 for the DS version, 73 out of 100 for the PC version, 71 out of 100 for the PlayStation 2 version, and 70 out of 100 for the PSP version.
The PlayStation 2 and Nintendo DS releases of "Cars" each received a "Platinum" sales award from the Entertainment and Leisure Software Publishers Association (ELSPA), indicating sales of at least 300,000 copies per version in the United Kingdom. In total, the game sold more than 8 million copies as of May 2007.
The GBA version was criticized as being "the worst version of the game" because of its incredibly short length, zoomed in camera, a lack of a multiplayer mode, and a lack of any depth.


Intel 80486SL

The Intel's i486SL is the power-saving variant of the i486DX microprocessor. The SL was designed for use in mobile computers. It was produced between November 1992 and June 1993. Clock speeds available were 20, 25 and 33 MHz. The i486SL contained all features of the i486DX.
In addition, the System Management Mode (SMM) (the same mode introduced with i386SL) was included with this processor. The system management mode makes it possible to shut down the processor without losing data. To achieve this, the processor state is saved in an area of static RAM (SMRAM).
In mid-1993, Intel incorporated the SMM feature in all its new 80486 processors and discontinued the SL series.
Refer to the respective section of the list of Intel microprocessors for technical details.


Intel Capital

Intel Capital is a division of Intel Corporation, set up to manage corporate venture capital, global investment, mergers and acquisitions. Intel Capital makes equity investments in a range of technology startups and companies offering hardware, software, and services targeting artificial intelligence, autonomous technology, data center and cloud, 5G, next-generation compute, semiconductor manufacturing and other technologies.
History.
Intel Capital was set up in 1991 by Les Vadasz, and Avram Miller. It was originally called Corporate Business Development (CBD). At that time, Intel mainly invested in American companies, and in 1998 95% of investment was in the USA. Over time, investment in non-US companies increased, and by 2012 international investments accounted for about 57%. Intel Capital has invested more than US$12.5 billion in over 1,550 companies in 57 countries. In that timeframe, over 200 portfolio companies have gone public on various exchanges around the world, and more than 325 were acquired or participated in a merger.
In 2014, Intel Capital has 26 offices, including in Belgium, Brazil, China, India, Germany, Ireland, Japan, Israel, Nigeria, Poland, Russia, Singapore, South Korea, Taiwan, Turkey, UK, USA
Investments.
Intel Capital investments include Actions Semiconductor, AlterGeo, AppyStore, AVG, Bellrock Media, Box, Broadcom, Cloudera, CNET, Citrix Systems, Elpida Memory, Gaikai, Gigya, IndiaInfoline.com, Inktomi, Insyde Software, Integrant Technologies, July Systems, Kingsoft, LogMeIn, Mall.cz, Marvell, Mellanox, Mirantis, MongoDB, MySQL, NIIT, Ondot Systems, PCCW, Red Hat, Rediff.com, Research in Motion (Blackberry), Saffron Technology, Sasken, Smart Technologies, Snapdeal, Sonda, Sohu.com, Stratoscale, TechFaith, Trigence, VMware, Volocopter and WebMD. In 2014 Intel Capital has made $62 Mn investment in 16 tech startups, In September 2017, According to the reports, Intel Capital invested $1 billion into AI startups including Mighty AI, Data Robot, Lumiata and many more. In 2020 Intel Capital invested in Jio Platforms.


INIT.COM


All-in-Wonder

The All-in-Wonder (also abbreviated to AIW) was a combination graphics card/TV tuner card designed by ATI Technologies. It was introduced on November 11, 1996. ATI had previously used the "Wonder" trademark on other graphics cards, however, they were not full TV/graphics combo cards (EGA Wonder, VGA Wonder, Graphics Wonder). ATI also made other TV oriented cards that use the word "Wonder" (TV Wonder, HDTV Wonder, DV Wonder), and remote control (Remote Wonder). The All-in-Wonder line debuted with the Rage chipset series. The cards were available in two forms, built by third-party manufacturers (marked as "Powered by ATI") as well as by ATI itself ("Built by ATI").
Each of the "All-in-Wonder Radeon" cards is based on a Radeon chipset with extra features incorporated onto the board. AIW cards run at lower clock speeds (two exceptions are the AIW 9600XT/AIW X800XT faster/same speed) than their conventional counterparts to reduce heat and power consumption. In June 2008, AMD revived the product line with an HD model.
Accessories.
The cards use a variety of specialised ports along the side to provide output to televisions, with the retail version equipped with composite ports and the ability to output to component. Later products also comes with a Remote Wonder remote control and a USB RF receiver to receive radio frequency signals from the remote. Some variants of the All-in-Wonder included FM radio tuning as well. Some analog tuners were bundled with Gemstar's Guide Plus+ electronic program guide for TV listings, while digital tuners used TitanTV instead.
Drivers.
The AIW card drivers are based on ATI's Catalyst drivers with additional T200 unified stream drivers. Currently, the only operating systems fully supporting TV capture with these cards are Microsoft Windows XP, 2000, 98, and 95. Display drivers work on Linux, and TV capture is supported on some cards with the GATOS project.


SpotPass and StreetPass

SpotPass and StreetPass are communication systems first introduced in the Nintendo 3DS. SpotPass was later incorporated into the Nintendo 2DS, models of the New 3DS and New 2DS, and Wii U game consoles. SpotPass delivers content from the Internet to the consoles, and StreetPass uses local Wi-Fi functionality to exchange data between 3DS, 2DS, and Wii U systems.
SpotPass.
SpotPass is a Nintendo 3DS and Wii U "always on" online background connectivity system, similarly to how predecessor WiiConnect24 originally functioned with Wii, which can automatically seek and connect to wireless network nodes such as Wi-Fi hotspots, sending and downloading information in the background while in sleep mode or while playing a game or running an application. It can be customized to fit the user's preferences, including opting out of it altogether for selected software. One application is being considered to use this functionality to "automatically acquire magazine and newspaper articles", similar to networked e-book reader applications.
Nintendo 3DS.
While full WiFi connectivity requires the Nintendo 3DS to be properly connected to a Wi-Fi connection via its settings, SpotPass can be obtained through most wireless connections. When new data is received from SpotPass and the system is in sleep mode, the notification LED of the system will turn blue and will remain blue until the system is taken out of sleep mode; when SpotPass data is received while the system is not in sleep mode, the notification LED will blink blue a few times before returning to being off. During the 2011 Game Developers Conference, Nintendo of America president Reggie Fils-Aimé announced that Nintendo has partnered with AT&T to provide access to AT&T hotspots via the Nintendo 3DS. Users are able to connect to these hotspots automatically and free of charge. SpotPass also makes uses of certified hotspots to access an application called "Nintendo Zone". In the Nintendo Zone application, users can view game trailers, game screenshots, and information about current and upcoming Nintendo 3DS titles. After leaving the hotspot, although the app remains on their Nintendo 3DS system, the player becomes unable to access it.
Wii U.
Similar to Nintendo 3DS's more distinctly mobile SpotPass functionality, the SpotPass feature on Wii U allows the system to automatically download available content via the Internet in the background, while the system is in use or in sleep mode. When the system is transmitting while in sleep mode, the system light will turn orange. Content that can be downloaded via SpotPass includes full game and application downloads, firmware updates, patches, and specific in-game content. Content currently being downloaded can be viewed in the Download Manager, accessed via the Wii U's Home Menu.
StreetPass.
StreetPass is Nintendo 3DS functionality which allows passive communication between Nintendo 3DS systems held by users in close proximity, an example being the sharing of Mii avatars in the "StreetPass Mii Plaza" application, and other game data. Similar with SpotPass in the Nintendo 3DS, when new data is received from StreetPass and the system is in sleep mode, the notification LED of the system will turn green and will remain green until the system is taken out of sleep mode; when StreetPass data is received while the system is not in sleep mode, the notification LED will blink green a few times before returning to being off.
StreetPass allows users to exchange software content from select games played on their system, regardless of what software is currently in the console. StreetPass functionality must be activated for each piece of compatible software and can be disabled by parental controls. Currently shared content is stored in one of twelve "data slots" in the console. Using this data slot, Nintendo 3DS users can readily share and exchange content for multiple games at the same time, whenever they are connected. Using the console's background connectivity, a Nintendo 3DS in "Sleep Mode" can automatically discover other Nintendo 3DS systems within range, establish a connection, and exchange content for mutually played games, all transparently and without requiring any user input. For example, in "Rhythm Heaven Megamix", if the user passes by someone with the same software, they will take on a figure fighting duel challenge. Each game can only hold a certain number of StreetPass exchanges, requiring the player to check their game software before additional exchanges can be made (for example, "StreetPass Plaza" can only hold ten visitors at a time).
Trademarks suggested that this functionality would be named "CrossPass", but on September 29, 2010, during the Nintendo World conference, the name of the Tag Mode service was confirmed to be StreetPass.
StreetPass Mii Plaza.
"StreetPass Mii Plaza" is a built-in application included with every Nintendo 3DS family device, and the primary application for StreetPass interactivity. Here, players can set up their Mii to appear on other 3DS devices that it encounters via StreetPass. Up to ten Miis can be brought into the plaza at a time and taken into various mini-games. Two mini-games, "Puzzle Swap" and "Find Mii / StreetPass Quest", are included as standard, whilst eleven additional games; "Mii Force / StreetPass Squad", "Flower Town / StreetPass Garden", "Warrior's Way / StreetPass Battle", "Monster Manor / StreetPass Mansion", "Ultimate Angler", "Battleground Z", "Slot Car Rivals", "Market Crashers", "Feed Mii", "Ninja Launcher", and "Mii Trek" can be purchased separately. All games allow players to use Play Coins in place of StreetPass Miis.
StreetPass Relay.
"StreetPass Relay" was announced during an analyst briefing at E3 2013, where Nintendo announced that it was creating thousands of new StreetPass Relay stations across the United States and Europe. Nintendo planned to turn over 29,000 Wi-Fi access points into relays in the US, while Europe would see approximately 30,000. With this network, Nintendo aimed to vastly improve the functionality of the 3DS and enable players to find more Miis in their "StreetPass Mii Plaza". It was powered by Hbase, Puppet, fluentd, and Amazon Web Services cloud technologies.
StreetPass Relay points were located at Nintendo Zones all across the country. When a Nintendo 3DS user got near a StreetPass Relay point, it automatically forwarded his or her StreetPass data to Nintendo's servers which stored it temporarily to pass it on to the next Nintendo 3DS user to pass by the same relay point. The Nintendo servers kept track of each relay point by the MAC address of the node. StreetPass Relay points supported StreetPass data for various games each time a Nintendo 3DS user passes by. This meant the user could get StreetPass data for several games at once.
On March 28 2018, StreetPass Relays worldwide were shut down, with the exception of the Nintendo store in New York City and Best Buy locations In Canada.


Linux Router Project

The Linux Router Project (LRP) is a now defunct networking-centric micro Linux distribution. The released versions of LRP were small enough to fit on a single 1.44MB floppy disk, and made building and maintaining routers, access servers, thin servers, thin clients, network appliances, and typically embedded systems next to trivial.
History.
LRP was conceived and primarily developed by Dave Cinege from 1997 until 2002. It began originally as a 'router on a floppy' and evolved into a streamlined general purpose network operating system.
As LRP is the oldest embedded Linux distribution, it formed (in whole or in part) the basis of many other embedded system distributions and commercial products which followed it. Several parts developed or specifically enhanced for LRP are still found in common usage today such as POSIXness and BusyBox.
Unreleased Work.
Dave Cinege worked on a version 4.0 rewrite of LRP from late 2000 into January 2001. He then began testing some ideas he had with proof of concept code, which he claimed was a radical departure from the status quo. To his surprise, this new direction seemed ideal, prompting him to abandon all work done on LRP 4.0 and begin from scratch on a new OS named LRP 5.0.
LRP 5.0 development was headed towards a complete rewrite and reimplementation of Linux userland with a new standard design outside of the POSIX specification. The stated purpose of this was to provide a modern standard base operating system suitable for any application including embedded systems, appliances, servers, and desktop computers.
Cinege however stopped work several months later due to financial reasons. He refused to release any further work, or even the name of this OS, due to animosity towards the computer industry and what he perceived as the plundering of open source authors' work by large corporations.
On May 6, 2003 Cinege updated the LRP website to reflect that the project was being abandoned.


Arena Football (2006 video game)

Arena Football is an Arena Football League video game developed by Electronic Arts (under their EA Sports brand) for the PlayStation 2 and Xbox. It was released on February 7, 2006. The cover features quarterback John Dutton of the Colorado Crush, the champions of ArenaBowl XIX. The game is similar to EA's other simulation football games ("NCAA Football" and "Madden NFL"), but adopts a style of play that is similar to the faster and more frantic paced Arena game. The game includes all the rules, rosters, and teams for the 2006 AFL season. A sequel, "" was made the following year for the PS2 only.
Teams.
2006 AFL teams.
All of the teams that competed in the 2006 season are included. The New Orleans VooDoo have been excluded because they have temporarily halted operations due to Hurricane Katrina. However, their logo is available for use in the game's create-a-team feature as well as their stadium, the New Orleans Arena if, in the create a team option, the player creates a team called the New Orleans VooDoo. The VooDoo resumed operations in 2007. The Kansas City Brigade franchise and its colors have been included, but the official name and logo didn't make it in because they were unveiled after the game had gone into production so the team was known as the Kansas City KC in the video game.
Historic teams.
EA included a number of historic teams in "Arena Football". They are awarded to the player upon meeting certain statistical goals in a game.
Reception.
The game received positive reviews. IGN gave the game an 8.3, stating, "While the season mode is shallow, online play and solid multiplayer action will keep you bouncing off the walls for some time." GameSpot gave the game a lower score of 6.9, and like IGN, criticized Season Mode. While GameSpot praised the Telemetry system, they also commented that the game cannot "decide whether it wants to be arcade- or simulation-oriented."


Mkdosfs

mkdosfs is one of the applications that are included in the dosfstools package, and it is used to create a FAT file system under Linux on a data storage device (usually a disk partition).
Usage.
 mkdosfs [options] device
You may specify the number of blocks on the device or allow mkdosfs to guess
Known issues.
mkdosfs does not support creating boot-able partitions.


Quantum Effect Devices

Quantum Effect Devices (QED) was a microprocessor design company incorporated in 1991 as Quantum Effect Design. It was based in Palo Alto, California.
History.
The three founders, Tom Riordan, Earl Killian and Ray Kunita, were senior managers at MIPS Computer Systems Inc.. They left MIPS at a time when the company was having a difficult time selling entire computer systems (MIPS Magnum) instead of concentrating on building microprocessor chips which was MIPS' original mission. Soon after, SGI purchased MIPS. IDT was a major funder and customer for the initial QED design.
Business.
The original product plan for QED was to build a MIPS microprocessor for a laptop computer. This was during the ACE initiative from Microsoft to support multiple RISC architectures for their new Windows NT operating system. System companies like DeskStation Technology and board companies like ShaBLAMM! Computer were building products in the hope that RISC-based personal computers would become mainstream. While that market never materialized, the first product, the R4600 "Orion" microprocessor, proved to be successful in several embedded markets such as networking routers and arcade games. Subsequent projects were designed for companies such as Toshiba and IDT (R4700), IDT & NKK (R4650), SGI and NEC (R5000).
The PowerPC 603q was a PowerPC microprocessor designed for Motorola, meant for Apple Computer's home PC and game machine designs. Neither of these designs were productized, so the PowerPC 603q never reached full production.
Several years later, in an attempt to increase product revenue, the company transformed itself to a product company selling its own line of MIPS microprocessors. At that time, the company changed its name to Quantum Effect Devices. After successful products introductions like the RM5200 and the RM7000, under its own "RISCMark" label, the company had its IPO on 1 February 2000. The initial stock price of $16 jumped to $56.50 on the first day of trading. The company was acquired by PMC-Sierra on October 2000; at the time, Quantum Effect Devices was valued in a stock swap worth $2.3 billion according to one estimate. The company became the Microprocessor Products Division of PMC. The acquisition was done by stock exchange and was valued at $2.3 billion. The team completed the RM9x00 product line while at PMC, but that product line was not successful in the marketplace. Most of the microprocessor core development team derived from QED was laid off as a group by PMC-Sierra in June 2005; the last few were laid off in January 2006.
The company name was attributed to Tom Riordan. He believed that the company would survive to the age when semiconductor geometry dimensions would become so small that quantum effects would dominate circuit behavior.
Devices.
The first QED microprocessor was the R4600. The founders of QED, who were previously involved with the R4000, felt that the large device was too complicated and that a simpler implementation would give a better price/performance ratio. For that reason, the R4600 is a re-implementation of the 5-stage Classic RISC pipeline with large (for the time) caches. For a while, this small and low cost device was one of the highest performance microprocessors on the market. While the initial target market of a MIPS laptop computer never materialized, this device found success in several markets. It was the first RISC processor used within a Cisco Systems network router. It was used in several Atari/Midway arcade games such as the well-known original Mortal Kombat game. The R4600 was licensed by IDT and Toshiba who manufactured and sold the devices.
The R4700 was targeted at SGI, who wanted a little more floating point performance. The R4700 improved on the repeat rate of floating point multiply instructions. This device was used inside the SGI Indy low-end workstation. The R4700 was licensed by IDT and Toshiba who manufactured and sold the devices.
The R4650 was commissioned by NKK, who desired a cheaper implementation for a video console game machine. The R4650 achieved a smaller die area by cutting the caches in half, only implementing single precision floating-point. This device was the first QED device that implemented the multiply–accumulate instructions, which enabled software functions such as softmodem. This device was used in the original Microsoft WebTV device. The R4650 was licensed by IDT and NKK who manufactured and sold the devices. The R4640 was the same chip but with the system bus restricted to 32-bits instead of 64-bits.
The R5000 was commissioned by SGI. This device doubled the instruction and data caches to 32 KB. It implemented a high-performance, fully pipelined floating point unit with multiply–accumulate capability and a SRT divider. The device had a limited implementation of superscalar instruction issue in which one integer instruction and one floating-point instruction could be issued in one cycle. This device was used in the SGI O2 and SGI Indy low-end workstations. The design was owned by SGI, which licensed the design to IDT and NEC and eventually to Toshiba.
The PowerPC 603q was commissioned by Motorola and the target market was Apple Computer's low-cost accounts including a home computer for students and a home video console game named "Pippen". The 603q was basically the R4600 pipeline re-targeted for the PowerPC instruction set. Since the PowerPC 603 was then the most power-efficient chip from the AIM alliance, the name of this device was chosen to reflect its low-cost and low-power characteristics. Once those Apple projects were cancelled, Motorola stopped the development of the 603q even though QED had received first silicon samples and they were functional.
The RM52XX series was the first product line sold directly by QED. The first of the series was a cost-reduced version of the R5000 with smaller caches and a different pin-out. The earlier RM52X0 devices had only 16 KB caches while the later RM52X1 devices had 32 KB caches. The RM523X devices had 32-bit system buses while RM526X had 64-bit system buses. This product line was very successful in the laser printer market, winning many accounts at printer companies such as Hewlett-Packard, Lexmark, Ricoh, Samsung.
The RM70XX series was the second product line sold directly by QED. It implemented a large 256 KB on-chip level 2 cache. The RM7000 was one of the first microprocessors to do so, especially within the embedded microprocessor market segment. It also implemented symmetric superscalar instruction issue with two integer execution units. The RM7061 device was a pin-compatible upgrade for the RM526X series. This product line was a very successful follow-on to the RM52XX products.
The RM9x00 family was the first SOC implemented by QED. The Apollo microprocessor core that was part of the RM9x00 had its pipeline lengthened to 7 stages to enable higher operating frequencies. Dynamic branch prediction was added to ameliorate the longer branch latencies. Within the RM9x00, two Apollo cores were used to implement a dual-core device. These processor cores successfully achieved their operating frequency target of 1 GHz. The SOC system interconnect was an in-house design with centralized storage for the transactions flowing through the SOC. Peripherals included a DDR memory controller, a SysAD bus controller, a boot bus controller, a DMA controller and a Hypertransport controller. A second generation device added a Gigabit ethernet controller, a PCI controller and cache coherency. This product family was not successful due to being late to the market. The company was financially conservative during the time leading up to and after the company's initial public offering and would not fully staff the SOC project. One of the reasons for selling the company to PMC-Sierra was to fund these SOC projects. By that time, competitors like SiByte had already entered the market with equivalent devices.


SGI Origin 2000

The SGI Origin 2000 is a family of mid-range and high-end server computers developed and manufactured by Silicon Graphics (SGI). They were introduced in 1996 to succeed the SGI Challenge and POWER Challenge. At the time of introduction, these ran the IRIX operating system, originally version 6.4 and later, 6.5. A variant of the Origin 2000 with graphics capability is known as the Onyx2. An entry-level variant based on the same architecture but with a different hardware implementation is known as the Origin 200. The Origin 2000 was succeeded by the Origin 3000 in July 2000, and was discontinued on June 30, 2002.
Models.
The family was announced on October 7, 1996.
The project was code named "Lego", and also known as SN0, to indicate the first in a series of scalable node architectures, contrasting with previous symmetric multiprocessor architectures in the SGI Challenge series.
The highest CPU count that SGI marketed for the Origin 2000 is 128 CPUs; above 64 CPUs the product was originally branded "CRAY Origin 2000" since Cray Research has just been merged with SGI. Three Origin 2000 models are capable of using 512 CPUs and 512 GB of memory but these were never marketed as a system to customers. One of the 512-CPU Origin 2000 series was installed at SGI's facility in Eagan, Minnesota for test purposes and the other two were sold to NASA Ames Research Center in Mountain View, California for specialized scientific computing. The 512-CPU Origin 2800s cost roughly $40 million each and the delivery of the Origin 3000 systems, scalable up to 512 or 1024 CPUs at a lower price per performance, made the 512-CPU Origin 2800 obsolete.
Several customers also bought 256-CPU Origin 2000 series systems, although they were never marketed as a product by SGI either.
The largest installation of SGI Origin 2000 series was Accelerated Strategic Computing Initiative (ASCI) Blue Mountain at Los Alamos National Labs. It included 48 Origin 2000 series 128-CPU systems all connected via High Performance Parallel Interface (HIPPI) for a total of 6144 processors. At the time it was tested, it placed second on the TOP500 list of fastest computers in the world. That test was completed with only 40 nodes of 128 CPUs each and recorded a sustained 1.6 teraflops. With all nodes connected, it was able to sustain 2.1 teraflops and peak of over 2.5 teraflops.
Los Alamos National Laboratory also had another 12 Origin 128-CPU system (for a total of 1536 CPUs) as part of the same testing.
The climate simulation laboratory at the National Center for Atmospheric Research (NCAR) had an Origin 2000 system named "Ute" with 128 CPUs. It was delivered on May 18, 1998, and decommissioned on July 15, 2002.
A smaller system at NCAR was named dataproc, delivered on March 29, with 16 CPUs.
The systems at NASA Ames included the one named for Harvard Lomax with 512 CPUs, one named for Joseph Steger with 128 CPUs, one named for Grace Hopper with 64CPUs, and one named for Alan Turing with 24 CPUs.
Hardware.
Each Origin 2000 module is based on nodes that are plugged into a backplane. Each module can contain up to four node boards, two router boards and twelve XIO options. The modules are then mounted inside a deskside enclosure or a rack. Deskside enclosures can only contain one module, while racks can contain two. In configurations with more than two modules, multiple racks are used.
The Origin 200 uses some of the architectural components, but in a very different physical realization that is not scalable.
Architecture.
An Origin 2000 system is composed of nodes linked together by an interconnection network. It uses the distributed shared memory sometimes called Scalable Shared-Memory Multiprocessing (S2MP) architecture. The Origin 2000 uses NUMAlink (originally named CrayLink) for its system interconnect. The nodes are connected to router boards, which use NUMAlink cables to connect to other nodes through their routers. The Origin 2000's network topology is a bristled fat hypercube. In configurations with more than 64 processors, a hierarchical fat hypercube network topology is used instead. Additional NUMAlink cables, called Xpress links can be installed between unused Standard Router ports to reduce latency and increase bandwidth. Xpress links can only be used in systems that have 16 or 32 processors, as these are the only configurations with a network topology that enables unused ports to be used in such a way.
The architecture has its roots in the DASH project at Stanford University, led by John L. Hennessy, which included two of the Origin designers.
Router boards.
There are four different router boards used by the Origin 2000. Each successive router board allows a larger amount of nodes to be connected.
Null Router.
The Null Router connects two nodes in the same module. A system using the Null Router cannot be expanded as there are no external connectors.
Star Router.
The Star Router can connect up to four nodes. It is always used in conjunction with a Standard Router to function correctly.
Standard Router (Rack Router).
The Standard Router can connect up to 32 nodes. It contains an application specific integrated circuit (ASIC) known as the scalable pipelined interconnect for distributed endpoint routing (SPIDER), which serves as a router for the NUMAlink network. The SPIDER ASIC has six ports, each with a pair of unidirectional links, connected to a crossbar which enables the ports to communicate with one another.
Meta Router (Cray Router).
The Meta Router is used in conjunction with Standard Routers to connect more than 32 nodes. It can connect up to 64 nodes.
Nodes.
Each Origin 2000 node fits on a single 16" by 11" printed circuit board that contains one or two processors, the main memory, the directory memory and the Hub ASIC. The node board plugs into the backplane through a 300-pad CPOP (Compression Pad-on-Pad) connector. The connector actually combines two connections, one to the NUMAlink router network and another to the XIO I/O subsystem.
Processor.
Each processor and their secondary cache is contained on a HIMM (Horizontal Inline Memory Module) daughter card that plugs into the node board. At the time of introduction, the Origin 2000 used the IP27 board, featuring one or two R10000 processors clocked at 180 MHz with 1 MB secondary cache(s). A high-end model with two 195 MHz R10000 processors with 4 MB secondary caches was also available. In February 1998, the IP31 board was introduced with two 250 MHz R10000 processors with 4 MB secondary caches. Later, the IP31 board was upgraded to support two 300, 350 or 400 MHz R12000 processors. The 300 and 400 MHz models had 8 MB L2 caches, while the 350 MHz model had 4 MB L2 caches. Near the end of its life, a variant of the IP31 board that could utilize the 500 MHz R14000 with 8 MB L2 caches was made available.
Main memory and directory memory.
Each node board can support a maximum of 4 GB of memory through 16 DIMM slots by using proprietary ECC memory SDRAM DIMMs with capacities of 16, 32, 64 and 256 MB. Because the memory bus is 144 bits wide (128 bits for data and 16 bits for ECC), memory modules are inserted in pairs. To support the Origin 2000 distributed shared memory model, the memory modules are proprietary and include directory memory, which contains information on the contents of remote caches for maintaining cache coherency, supporting up to 32 processors. Additional directory memory is required in configurations with more than 32 processors. The additional directory memory is contained on proprietary DIMMs that are inserted into eight DIMM slots set aside for its use.
Hub ASIC.
The Hub ASIC interfaces the processors, memory and XIO to the NUMAlink 2 system interconnect. The ASIC contains five major sections: the crossbar (referred to as the "XB"), the I/O interface (referred to as the "II"), the network interface (referred to as the "NI"), the processor interface (referred to as the "PI") and the memory and directory interface (referred to as the "DM"), which also serves as the memory controller. The interfaces communicate with each other via FIFO buffers that are connected to the crossbar. When two processors are connected to the Hub ASIC, the node does not behave in a SMP fashion. Instead, the two processors operate separately and their buses are multiplexed over the single processor interface. This was done to save pins on the Hub ASIC. The Hub ASIC is clocked at 100 MHz and contains 900,000 gates fabricated in a five-layer metal process.
I/O subsystem.
The I/O subsystem is based around the Crossbow (Xbow) ASIC, which shares many similarities with the SPIDER ASIC. Since the Xbow ASIC is intended for use with the simpler XIO protocol, its hardware is also simpler, allowing the ASIC to feature eight ports, compared with the SPIDER ASIC's six ports. Two of the ports connect to the node boards, and the remaining six to XIO cards. While the I/O subsystem's native bus is XIO, PCI-X and VME64 buses can also be used, provided by XIO bridges.
An IO6 base I/O board is present in every system. It is a XIO card that provides:
The IO6G (G for Graphics) had 2 additional serial ports and keyboard/mouse ports plus the above ports. The IO6G was required on systems with the Onyx Graphics pipes(cards) to connect keyboard/mouse.


Virtual File Allocation Table


Chili Con Carnage

Chili Con Carnage is an action/adventure third-person shooter video game. It was developed by Deadline Games and published by Sci Entertainment in Europe and by Eidos in North America. Its predecessor "Total Overdose" was released September 27, 2005. Many reviews of the game classify it as both a sequel and a remake.
Story.
The player character is Ramiro "Ram" Cruz, an athletic wisecracker. Ramiro, after witnessing his father Ernesto being murdered (along with some kittens, which were Ram's birthday present to his father) in a freak combine harvester accident, wants revenge on the culprits responsible. The player fights with drug lords, corrupt bandits, femme fatales, crooked mercenaries, and ritualistic zombies. In between missions the player can choose to play mini games, in each of which the player is dropped right into the middle of a situation and must complete a number of moves (Fly on the Wall, Burrito Blast, Etc.) with a limited number of enemies, or beat a set score in a limited amount of time. There is no free-roaming option in the game.
Reception.
The game received average reviews, a bit more favorable than "Total Overdose", according to the review aggregation website Metacritic.


Bubble and Squeak (video game)

Bubble and Squeak is a platform game published for the Amiga in 1994 by Audiogenic Software. It was developed by Fox Williams under the name "Barney & Clyde", and they ported it to the Sega Genesis for which it was published by Sunsoft under license from Audiogenic. The game is a childlike sci-fi fantasy platform game in which players control a little human boy named Bubble along with recent alien acquaintance Squeak. The platform levels are separated by brief underwater scrolling shooter bonus segments.
Plot.
The story takes place on the planet Grool, a planet inhabited by mostly short, anthropomorphous felines. The idyllic and mundane lifestyle of the feline aliens is interrupted when an alien invader known as Kat of Nine Tails kidnaps Grool's sentient populace, inadvertently leaving one of them, Squeak, behind. Shortly after, Squeak encounters a human boy known only as Bubble who agrees to rescue Squeak's captured populace.
Gameplay.
Players controlled Bubble and at any time during gameplay could command Squeak to either 'follow' or 'wait' for him. Squeak, who was invulnerable to enemies and enemy fire, had his own AI and would help collect items or give Bubble a boost via piggy-back, letting Squeak toss him up to tall heights or by simply standing on top of Squeak's head. Collectable items included gems, coins, and a submersible icon which was necessary to play the shooter stages; some items could be picked up and carried to other locations such as springs, but the only items the player could pick up in the shooter stages were extra lives and Speed-ups. In both modes of gameplay (collecting and shooting), Bubble was equipped with unlimited ammunition, either stars or torpedoes.
Reception.
"Electronic Gaming Monthly" gave the Genesis version a 6.6 out of 10, praising the use of teamwork and strategy and the impressive graphics.


Intel Core 2

Intel Core 2 is the processor family encompassing a range of Intel's consumer 64-bit x86-64 single-, dual-, and quad-core microprocessors based on the Core microarchitecture. The single- and dual-core models are single-die, whereas the quad-core models comprise two dies, each containing two cores, packaged in a multi-chip module. The Core 2 range was the last flagship range of Intel desktop processors to use a front-side bus.
The introduction of Core 2 relegated the Pentium brand to the mid-range market, and reunified laptop and desktop CPU lines for marketing purposes under the same product name, which were formerly divided into the Pentium 4, Pentium D, and Pentium M brands.
The "Core 2" processor line was introduced on July 27, 2006, comprising the "Duo" (dual-core) and "Extreme" (dual- or quad-core CPUs for enthusiasts), and in 2007, the "Quad" (quad-core) and "Solo" (single-core) sub-brands. Intel Core 2 processors with vPro technology (designed for businesses) include the dual-core and quad-core branches.
Although Woodcrest processors are also based on the Core architecture, they are available under the Xeon brand. From December 2006, all Core 2 Duo processors were manufactured from 300 millimeter plates at Fab 12 factory in Arizona and at Fab 24-2 in County Kildare, Ireland.
Virtual machine or virtualization abilities.
"Core 2" and other LGA 775 processors can support virtualization, when the virtual machine (VM) software supports those processors, e.g., the processor supports 'VT-x with EPT'.
Newer versions of VM software do not support processors older than Nehalem (Core 2 and older) because the older processors lack support for Intel "VT-x" with "Extended Page Table" ("EPT"), also termed "second-level address translation" ("SLAT"). Intel's "VT-x with EPT" was introduced on the newer, Nehalem microarchitecture released in 2008.
Models.
The "Core 2"-branded CPUs include: "Conroe"/"Allendale" (dual-core for desktops), "Merom" (dual-core for laptops), "Merom-L" (single-core for laptops), "Kentsfield" (quad-core for desktops), and the updated variants named "Wolfdale" (dual-core for desktops), "Penryn" (dual-core for laptops), and "Yorkfield" (quad-core for desktops).
The Core 2 branded processors feature Virtualization Technology without EPT (with some exceptions), Execute Disable Bit, and SSE3. Their Core microarchitecture introduced SSSE3, Trusted Execution Technology, Enhanced SpeedStep, and Active Management Technology (iAMT2). With a maximum thermal design power (TDP) of 65W, the Core 2 Duo Conroe dissipates half the power of the less capable contemporary Pentium D-branded desktop chips that have a max TDP of 130 W.
Known marks.
With the release of the Core 2 processor, the abbreviation "C2" has come into common use, with its variants "C2D" (the present Core 2 Duo), and "C2Q", "C2E" to refer to the Core 2 Quad and Core 2 Extreme processors respectively. "C2QX" stands for the Extreme-Editions of the Quad (QX6700, QX6800, QX6850).
The successors to the "Core 2" brand are a set of Nehalem microarchitecture based processors called "Core i3, i5, and i7". 'Core i7' was officially launched on November 17, 2008 as a family of three quad-core processor desktop models, further models started appearing throughout 2009. The last processor of the family to be released was the Core 2 Quad Q9500 in January 2010. The Core 2 processor line was removed from the official price lists in July 2011, and the last processors were discontinued in June 2012.
External links.
1st public demonstration:Anandtech discovers Core 2 Duo performance under the supervision of Francois Piednoel


IBM 3270 AT


Crimson Gem Saga

Crimson Gem Saga is a role-playing video game developed for the PlayStation Portable and iOS. It was developed by South Korean studio IRONNOS and published in Korea by SK Telecom as Astonishia Story 2. It was released in North America on May 26, 2009 by Atlus under the title "Crimson Gem Saga", and was released in Japan under the title Garnet Chronicle by Sega.
The game is set in the world of Latein, where, unbeknownst to the public, an artifact formerly known as the Crimson Gem is being sought. One of the parties caught up in the whirlwind is Killian von Rohcoff, a recent graduate of the Green Hill Chevalier Academy, the game's protagonist. The game is a sequel in story to "Astonishia Story", but since much of the game's mechanics were changed, the title in all regions was also changed.
Gameplay.
Combat in Crimson Gem Saga is similar to many turn-based RPGs. The most noticeable quirk is the ambush system. If contact between the player's icon and a generic monster icon occur on a field map, a battle will occur. If the player touches the monster icon while the monster is facing away from the player, the player will gain an immediate preliminary attack with the combined force of all party members. If the monster has a "!" symbol appear above their head, and contacts the player after that symbol disappears, the enemy may begin battle with a preemptive attack on the player with the combined force of all the enemy party members.
The game also features a weapon and skill customization system, as well as combination attacks that include anywhere from 2 to 4 party members.
Story.
The story of the game revolves around the protagonist Killian von Rohcoff, who seems to always be on the wrong end of fate. He somehow gets caught up with the search for a powerful ancient artifact.
Characters.
Killian von Rohcoff: Killian is the protagonist of this game. When the game begins we find him attempting to shake off the effects of last night's partying in order to make it in time to attend his own graduation.
Herbert von Guterrian: Herbert is Killian's rival, and they've been enemies since the day they first met at Green Hill Academy. He constantly annoys Killian with his arrogance, his unique laugh, and the way that he always beats Killian at everything.
Spinel: Spinel is an elf, and a self-described "treasure hunter extraordinaire". She meets up with Killian at the beginning of the game and only further complicates his life.
Jeffrey: Jeffrey also meets up with Killian at the beginning of the game, and is probably the only character who has even worse luck than Killian. He first runs into Killian while in the middle of a dispute with Spinel.
Henson: Henson's a mysterious, wise-cracking mage who is both quick with a burning insult and a burning fireball. Not much is known about his past.
Gelts: Gelts is a former priest who has renounced his old ways. Now his hobbies include boozing and womanizing. He wields a giant hammer in battle.
Lahduk: Lahduk is even more mysterious than Henson, and likely even more powerful.
Acelora: Acelora is one of the Radiant Crusaders that serve the Order of Light. She's quickly rising through the ranks, and thinks of nothing other than aiding the Order.
Reception.
The game was met with positive to average reception. GameRankings and Metacritic gave it a score of 79.02% and 78 out of 100 for the PSP version, and 69.75% and 70 out of 100 for the iOS version.
Most reviewers noted that the game doesn't do anything particularly innovative or new, but it follows the formula so well that they can forgive that. Many of the early reviews have also favorably commented on both the quality of the writing, and the quality of the voice acting. GameSpot has been the most critical so far, with their reviewer noting that they felt the game was simple and uninspired.
iOS release.
On August 3, 2010 "Crimson Gem Saga" was released on Apple's App Store for iOS. It was featured on the App Store's "New and Noteworthy" category for Role Playing iOS Games specifically and for all iOS Games, "Top Grossing Role Playing Game" and "What's Hot" categories. It has not been updated for years, and no longer functions on the current iOS.


Pentium 4

Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. The production of Netburst processors was active from 2000 until May 21, 2010.
All Pentium 4 CPUs are based on the NetBurst microarchitecture. The Pentium 4 "Willamette" (180 nm) introduced SSE2, while the "Prescott" (90 nm) introduced SSE3. Later versions introduced Hyper-Threading Technology (HTT).
The first Pentium 4-branded processor to implement 64-bit was the "Prescott" (90 nm) (February 2004), but this feature was not enabled. Intel subsequently began selling 64-bit Pentium 4s using the ""E0" revision" of the Prescotts, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit) to Intel 64. Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M.
Intel also marketed a version of their low-end Celeron processors based on the NetBurst microarchitecture (often referred to as "Celeron 4"), and a high-end derivative, Xeon, intended for multi-socket servers and workstations. In 2005, the Pentium 4 was complemented by the dual-core-brands Pentium D and Pentium Extreme Edition.
Microarchitecture.
In benchmark evaluations, the advantages of the NetBurst microarchitecture were unclear. With carefully optimized application code, the first Pentium 4s outperformed Intel's fastest Pentium III (clocked at 1.13 GHz at the time), as expected. But in legacy applications with many branching or x87 floating-point instructions, the Pentium 4 would merely match or run slower than its predecessor. Its main downfall was a shared unidirectional bus. The NetBurst microarchitecture consumed more power and emitted more heat than any previous Intel or AMD microarchitectures.
As a result, the Pentium 4's introduction was met with mixed reviews: Developers disliked the Pentium 4, as it posed a new set of code optimization rules. For example, in mathematical applications, AMD's lower-clocked Athlon (the fastest-clocked model was clocked at 1.2 GHz at the time) easily outperformed the Pentium 4, which would only catch up if software was re-compiled with SSE2 support. Tom Yager of "Infoworld" magazine called it "the fastest CPU - for programs that fit entirely in cache". Computer-savvy buyers avoided Pentium 4 PCs due to their price premium, questionable benefit, and initial restriction to Rambus' RDRAM. In terms of product marketing, the Pentium 4's singular emphasis on clock frequency (above all else) made it a marketer's dream. The result of this was that the NetBurst micro architecture was often referred to as a marchitecture by various computing websites and publications during the life of the Pentium 4. It was also called "NetBust," a term popular with reviewers who reflected negatively upon the processor's performance.
The two classical metrics of CPU performance are IPC (instructions per cycle) and clock speed. While IPC is difficult to quantify due to dependence on the benchmark application's instruction mix, clock speed is a simple measurement yielding a single absolute number. Unsophisticated buyers would simply consider the processor with the highest clock speed to be the best product, and the Pentium 4 had the fastest clock speed. Because AMD's processors had slower clock speeds, it countered Intel's marketing advantage with the "megahertz myth" campaign. AMD product marketing used a "PR-rating" system, which assigned a merit value based on relative performance to a baseline machine.
At the launch of the Pentium 4, Intel stated that NetBurst-based processors were expected to scale to 10 GHz after several fabrication process generations. However, the clock speed of processors using the NetBurst micro architecture reached a maximum of 3.8 GHz. Intel had not anticipated a rapid upward scaling of transistor power leakage that began to occur as the die reached the 90 nm lithography and smaller. This new power leakage phenomenon, along with the standard thermal output, created cooling and clock scaling problems as clock speeds increased. Reacting to these unexpected obstacles, Intel attempted several core redesigns ("Prescott" most notably) and explored new manufacturing technologies, such as using multiple cores, increasing FSB speeds, increasing the cache size, and using a longer instruction pipeline along with higher clock speeds. These solutions failed, and from 2003 to 2005, Intel shifted development away from NetBurst to focus on the cooler-running Pentium M microarchitecture. On January 5, 2006, Intel launched the Core processors, which put greater emphasis on energy efficiency and performance per clock cycle. The final NetBurst-derived products were released in 2007, with all subsequent product families switching exclusively to the Core microarchitecture.
Testing and validation.
According to Bob Bentley, presenting on behalf of Intel at the 38th annual Design Automation Conference, "The microarchitecture of the Pentium® 4 processor is significantly more complex than any previous IA-32 microprocessor, so the challenge of validating the logical correctness of the design in a timely fashion was indeed a daunting one." He hired a team of 60 recent graduates to help with testing and validation.
Processor cores.
Pentium 4 processors have an integrated heat spreader (IHS) that prevents the die from accidentally being damaged when mounting and unmounting cooling solutions. Prior to the IHS, a CPU shim was sometimes used by people worried about damaging the core. Overclockers sometimes removed the IHS from Socket 423 and Socket 478 chips to allow for more direct heat transfer. On Socket 478 Prescott processors and processors using the Socket LGA 775 (Socket T) interface, the IHS is directly soldered to the die or dies, making it difficult to remove.
Willamette.
Willamette, the project codename for the first NetBurst microarchitecture implementation, experienced long delays in the completion of its design process. The project was started in 1998, when Intel saw the Pentium II as their permanent line. At that time, the Willamette core was expected to operate at frequencies up to about 1 GHz. However, the Pentium III was released while Willamette was still being finished. Due to the radical differences between the P6 and NetBurst microarchitectures, Intel could not market Willamette as a Pentium III, so it was marketed as the Pentium 4.
On November 20, 2000, Intel released the Willamette-based Pentium 4 clocked at 1.4 and 1.5 GHz. Most industry experts regarded the initial release as a stopgap product, introduced before it was truly ready. According to these experts, the Pentium 4 was released because the competing Thunderbird-based AMD Athlon was outperforming the aging Pentium III, and further improvements to the Pentium III were not yet possible. This Pentium 4 was produced using a 180 nm process and initially used Socket 423 (also called socket W, for "Willamette"), with later revisions moving to Socket 478 (socket N, for "Northwood"). These variants were identified by the Intel product codes 80528 and 80531 respectively.
On the test bench, the Willamette was somewhat disappointing to analysts in that not only was it unable to outperform the Athlon and the highest-clocked Pentium IIIs in all testing situations, but it was not superior to the budget segment's AMD Duron. Although introduced at prices of $644 (1.4 GHz) and $819 (1.5 GHz) for 1000 quantities to OEM PC manufacturers (prices for models for the consumer market varied by retailer), it sold at a modest but respectable rate, handicapped somewhat by the requirement for relatively fast yet expensive Rambus Dynamic RAM (RDRAM). The Pentium III remained Intel's top selling processor line, with the Athlon also selling slightly better than the Pentium 4. While Intel bundled two RDRAM modules with each boxed Pentium 4, it did not facilitate Pentium 4 sales and was not considered a true solution by many.
In January 2001, a still slower 1.3 GHz model was added to the range, but over the next twelve months, Intel gradually started reducing AMD's leadership in performance. In April 2001 a 1.7 GHz Pentium 4 was launched, the first model to provide performance clearly superior to the old Pentium III. July saw 1.6 and 1.8 GHz models and in August 2001, Intel released 1.9 and 2 GHz Pentium 4s. In the same month, they released the 845 chipset that supported much cheaper PC133 SDRAM instead of RDRAM. The fact that SDRAM was so much cheaper caused the Pentium 4's sales to grow considerably. The new chipset allowed the Pentium 4 to quickly replace the Pentium III, becoming the top-selling mainstream processor on the market.
The Willamette code name is derived from the Willamette Valley region of Oregon, where a large number of Intel's manufacturing facilities are located.
Northwood.
In January 2002, Intel released Pentium 4s with a new core code named "Northwood" at speeds of 1.6 GHz, 1.8 GHz, 2 GHz and 2.2 GHz. "Northwood" (product code 80532) combined an increase in the L2 cache size from 256 KB to 512 KB (increasing the transistor count from 42 million to 55 million) with a transition to a new 130 nm fabrication process. Making the processor out of smaller transistors means that it can run at higher clock speeds and produce less heat. In the same month boards utilizing the 845 chipset were released with enabled support for DDR SDRAM which provided double the bandwidth of PC133 SDRAM, and alleviated the associated high costs of using Rambus RDRAM for maximal performance with Pentium 4.
A 2.4 GHz Pentium 4 was released on April 2, 2002, and the bus speed increased from 400 MT/s to 533 MT/s (133 MHz physical clock) for the 2.26 GHz, 2.4 GHz, and 2.53 GHz models in May, 2.66 GHz and 2.8 GHz models in August, and 3.06 GHz model in November. With Northwood, the Pentium 4 came of age. The battle for performance leadership remained competitive (as AMD introduced faster versions of the Athlon XP) but most observers agreed that the fastest-clocked Northwood-based Pentium 4 was usually ahead of its rival. This was particularly so in mid-2002, when AMD's changeover to its 130 nm production process did not help the initial "Thoroughbred A" revision Athlon XP CPUs to clock high enough to overcome the advantages of Northwood in the 2.4 to 2.8 GHz range.
The 3.06 GHz Pentium 4 enabled Hyper-Threading Technology that was first supported in Foster-based Xeons. This began the convention of virtual processors (or virtual cores) under x86 by enabling multiple threads to be run at the same time on the same physical processor. By shuffling two (ideally differing) program instructions to simultaneously execute through a single physical processor core, the goal is to best utilize processor resources that would have otherwise been unused from the traditional approach of having these single instructions wait for each other to execute singularly through the core. This initial 3.06 GHz 533FSB Pentium 4 Hyper-Threading enabled processor was known as Pentium 4 HT and was introduced to mass market by Gateway in November 2002.
On April 14, 2003, Intel officially launched the new Pentium 4 HT processor. This processor used an 800 MT/s FSB (200 MHz physical clock), was clocked at 3 GHz, and had Hyper-Threading technology. This was meant to help the Pentium 4 better compete with AMD's Opteron line of processors. The server-oriented Opteron initially did not share a common socket with AMD's desktop processor line (Socket A). Because of this, motherboard manufacturers did not initially build motherboards with AGP for Opterons. As AGP was the primary graphics expansion port for desktop use, this oversight prevented the Opteron from encroaching from the server market and threatening the Pentium 4 desktop market. Meanwhile, with the launch of the Athlon XP 3200+ in AMD's desktop line, AMD increased the Athlon XP's FSB speed from 333 MT/s to 400 MT/s, but it was not enough to hold off the new 3 GHz Pentium 4 HT. The Pentium 4 HT's increase to a 200 MHz quad-pumped bus (200x4=800Mhz effective) greatly helped to satisfy the bandwidth requirements the Netburst architecture desired for reaching optimal performance. While the Athlon XP architecture was less dependent on bandwidth, the bandwidth numbers reached by Intel were well out of range for the Athlon's EV6 bus. Hypothetically, EV6 could have achieved the same bandwidth numbers, but only at speeds unreachable at the time. Intel's higher bandwidth proved useful in benchmarks for streaming operations, and Intel marketing wisely capitalized on this as a tangible improvement over AMD's desktop processors. Northwood 2.4 GHz, 2.6 GHz and 2.8 GHz variants were released on May 21, 2003. A 3.2 GHz variant was launched on June 23, 2003 and the final 3.4 GHz version arrived on February 2, 2004.
Overclocking early stepping Northwood cores yielded a startling phenomenon. While core voltage approaching 1.7 V and above would often allow substantial additional gains in overclocking headroom, the processor would slowly (over several months or even weeks) become more unstable over time with a degradation in maximum stable clock speed before dying and becoming totally unusable. This became known as "Sudden Northwood Death Syndrome" (SNDS), which was caused by electromigration.
Pentium 4-M.
Also based on the Northwood core, the "Mobile Intel Pentium 4 Processor - M" was released on April 23, 2002 and included Intel's SpeedStep and Deeper Sleep technologies. Intel's naming conventions made it difficult at the time of the processor's release to identify the processor model. There was the Pentium III mobile chip, the Mobile Pentium 4-M, the Mobile Pentium 4, and then just the Pentium M which itself was based on the Pentium III and significantly faster than the former three. Its TDP is about 35 watts in most applications. This lowered power consumption was due to lowered core voltage, and other features mentioned previously.
Unlike the desktop Pentium 4, the Pentium 4-M did not feature an integrated heat spreader (IHS), and it operates at a lower voltage. The lower voltage means lower power consumption, and in turn less heat. However, according to Intel specifications, the Pentium 4-M had a maximum thermal junction temperature rating of 100 degrees C, approximately 40 degrees higher than the desktop Pentium 4.
Mobile Pentium 4.
The "Mobile Intel Pentium 4 Processor" was released to address the problem of putting a full desktop Pentium 4 processor into a laptop, which some manufacturers were doing. The Mobile Pentium 4 used a 533 MT/s FSB, following the desktop Pentium 4's evolution. Oddly, increasing the bus speed by 133 MT/s (33 MHz) caused a massive increase in TDPs, as mobile Pentium 4 processors emitted 59.8–70 W of heat, with the Hyper-Threading variants emitting 66.1–88 W. This allowed the mobile Pentium 4 to bridge the gap between the desktop Pentium 4 (up to 115 W TDP), and the Pentium 4-M (up to 35 W TDP).
Northwood (Extreme Edition).
In September 2003, at the Intel Developer Forum, the Pentium 4 Extreme Edition (P4EE) was announced, just over a week before the launch of Athlon 64 and Athlon 64 FX. The design was mostly identical to Pentium 4 (to the extent that it would run in the same motherboards), but differed by an added 2 MB of level 3 cache. It shared the same Gallatin core as the Xeon MP, though in a Socket 478 form factor (as opposed to Socket 603 for the Xeon MP) and with an 800 MT/s bus, twice as fast as that of the Xeon MP.
While Intel maintained that the Extreme Edition was aimed at gamers, critics viewed it as an attempt to steal the Athlon 64's launch thunder, nicknaming it the "Emergency Edition". With a price tag of $999, it was also referred to as the "Expensive Edition" and "Extremely Expensive".
The added cache generally resulted in a noticeable performance increase in most processor intensive applications. Multimedia encoding and certain games benefited the most, with the Extreme Edition outperforming the Pentium 4, and even the two Athlon 64 variants, although the lower price and more balanced performance of the Athlon 64 (particularly the non-FX version) led to it usually being seen as the better value proposition. Nonetheless, the Extreme Edition did achieve Intel's apparent aim, which was to prevent AMD from being the performance champion with the new Athlon 64, which was winning every single major benchmark over the existing Pentium 4s.
In January 2004 a 3.4 GHz version was released for Socket 478, and in Summer 2004 the CPU was released using the new Socket 775. A slight performance increase was achieved in late 2004 by increasing the bus speed from 800 MT/s to 1066 MT/s, resulting in a 3.46 GHz Pentium 4 Extreme Edition. By most metrics, this was on a per-clock basis the fastest single-core NetBurst processor that was ever produced, even outperforming many of its successor chips (not counting the dual-core Pentium D). Afterwards, the Pentium 4 Extreme Edition was migrated to the Prescott core. The new 3.73 GHz Extreme Edition had the same features as a 6x0-sequence Prescott 2M, but with a 1066 MT/s bus. In practice however, the 3.73 GHz Pentium 4 Extreme Edition almost always proved to be slower than the 3.46 GHz Pentium 4 Extreme Edition, which is most likely due to the lack of an L3 cache and the longer instruction pipeline. The only advantage the 3.73 GHz Pentium 4 Extreme Edition had over the 3.46 GHz Pentium 4 Extreme Edition was the ability to run 64-bit applications since all Gallatin-based Pentium 4 Extreme Edition processors lacked the Intel 64 instruction set.
Although never a particularly good seller, especially since it was released in a time when AMD was asserting near total dominance in the processor performance race, the Pentium 4 Extreme Edition established a new position within Intel's product line, that of an enthusiast oriented chip with the highest-end specifications offered by Intel chips, along with unlocked multipliers to allow for easier overclocking. In this role it has since been succeeded by the Pentium Extreme Edition (The Extreme version of the dual-core Pentium D), the Core 2 Extreme, the Core i7 and most recently, the Core i9. Contrary to popular belief however, the Pentium 4 Extreme Edition for Socket 478 has a locked multiplier. Only the Pentium Extreme Edition and Engineering Sample CPUs are unlocked.
Prescott.
On February 1, 2004, Intel introduced a new core codenamed "Prescott". The core used the 90 nm process for the first time, which one analyst described as "a major reworking of the Pentium 4's microarchitecture." Despite this overhaul, the performance gains were inconsistent. Some programs benefited from Prescott's doubled cache and SSE3 instructions, whereas others were harmed by its longer pipeline. The Prescott's microarchitecture allowed slightly higher clock speeds, but not nearly as high as Intel had anticipated. The fastest mass-produced Prescott-based Pentium 4s were clocked at 3.8 GHz. While Northwood ultimately achieved clock speeds 70% higher than Willamette, Prescott only scaled 12% beyond Northwood. Prescott's inability to achieve greater clock speeds was attributed to the very high power consumption and heat output of the processor. This led to the processor receiving the nickname "PresHot" on forums. In fact, Prescott's power and heat characteristics were only slightly higher than those of Northwood of the same speed and nearly equal to the Gallatin-based Extreme Editions, but since those processors had already been operating near the limits of what was considered thermally acceptable, this still posed a major issue.
The "Prescott" Pentium 4 contains 125 million transistors and has a die area of 112 mm2. It was fabricated in a 90 nm process with seven levels of copper interconnect. The process has features such as strained silicon transistors and Low-κ carbon-doped silicon oxide (CDO) dielectric, which is also known as organosilicate glass (OSG). The Prescott was first fabricated at the D1C development fab and was later moved to F11X production fab.
Originally, Intel released two Prescott lines: the E-series, with an 800 MT/s FSB and Hyper-Threading support, and the low-end A-series, with a 533 MT/s FSB and Hyper-Threading disabled. Intel eventually added XD bit (eXecute Disable) and Intel 64 functionality to Prescott.
LGA 775 Prescott uses a rating system, labeling them as the 5xx series (Celeron Ds are the 3xx series, while Pentium Ms are the 7xx series). The LGA 775 version of the E-series uses model numbers 5x0 (520–560), and the LGA 775 version of the A-series uses model numbers 5x5 and 5x9 (505–519). The fastest, the 570J and 571, is clocked at 3.8 GHz. Plans to mass-produce a 4 GHz Pentium 4 were cancelled by Intel in favor of dual core processors, although some European retailers claimed to be selling a Pentium 4 580, clocked at 4 GHz.
The 5x0J series (and its low-end equivalent, the 5x5J and 5x9J series) introduced the XD bit to Intel's line of processors. This technology, introduced to the x86 line by AMD and called NX (No eXecute), can help prevent certain types of malicious code from exploiting a buffer overflow to get executed. Intel also released a series of Prescott supporting Intel 64, Intel's implementation of the AMD-developed x86-64 64-bit extensions to the x86 architecture. These were originally released as the F-series, and only sold to OEMs, but they were later renamed to the 5x1 series and sold to the general public. Two low-end Intel 64-enabled Prescotts, based on the 5x5/5x9 series, were also released with model numbers 506 and 516. 5x0, 5x0J, and 5x1 series Prescott incorporates Hyper-Threading in order to speed up some processes that use multithreaded software, such as video editing. The 5x1 series also supports 64 bit computing.
Prescott 2M (Extreme Edition).
Intel, by the first quarter of 2005, released a new Prescott core with 6x0 numbering, codenamed ""Prescott 2M". "Prescott 2M" is also sometimes known by the name of its Xeon derivative, "Irwindale"". It features Intel 64, the XD bit, EIST (Enhanced Intel SpeedStep Technology), Tm2 (for processors at 3.6 GHz and above), and 2 MB of L2 cache. However, higher cache latency and the double word size, if using Intel 64 mode, negated any advantage that added cache introduced. Rather than being a targeted speed boost the double size cache was intended to provide the same space and hence performance for 64-bit mode operations.
6xx series Prescott 2Ms have incorporated Hyper-Threading in order to speed up some processes that use multithreaded software, such as video editing.
On November 14, 2005, Intel released Prescott 2M processors with VT (Virtualization Technology, codenamed "Vanderpool") enabled. Intel only released two models of this Prescott 2M category: 662 and 672, running at 3.6 GHz and 3.8 GHz, respectively.
Cedar Mill.
The final revision of the Pentium 4 was "Cedar Mill", released on January 5, 2006. This was a die shrink of the Prescott-based 600 series core to 65 nm, with no real feature additions but significantly reduced power consumption. Cedar Mill had a lower heat output than Prescott, with a TDP of 86 W. The Core Stepping of D0 in late 2006 reduced this to 65 watts. It has a 65 nm core and features the same 31-stage pipeline as Prescott, 800 MT/s FSB, Intel 64, Hyper-Threading, but no Virtualization Technology. As with Prescott 2M, Cedar Mill also has a 2 MB L2 cache. It was released as Pentium 6x1 and 6x3 (product code 80552) at frequencies from 3 GHz up to 3.6 GHz. Overclockers managed to exceed 8 GHz with these processors using liquid nitrogen cooling.
To distinguish Cedar Mill cores from Prescott cores with the same features, Intel added 1 to their model numbers. Thus, Pentium 4 631, 641, 651 and 661 are 65 nm Cedar Mill microprocessors, while Pentium 630, 640, 650 and 660 respectively are their 90 nm Prescott equivalents.
The name "Cedar Mill" refers to Cedar Mill, Oregon, an unincorporated community near Intel's Hillsboro, Oregon facilities.
Successor.
The original successor to the Pentium 4 was (codenamed) Tejas, which was scheduled for an early-mid-2005 release. However, it was cancelled a few months after the release of Prescott due to extremely high TDPs (a 2.8 GHz Tejas emitted 150 W of heat, compared to around 80 W for a Northwood of the same speed, and 100 W for a comparably clocked Prescott) and development on the NetBurst microarchitecture as a whole ceased, with the exception of the dual-core Pentium D and Pentium Extreme Edition and the Cedar Mill-based Pentium 4 HT.
Since May 2005, Intel has released dual-core processors under the Pentium D and Pentium Extreme Edition brands. These came under the code names Smithfield and Presler for the 90 nm and 65 nm parts respectively.
The actual successor to the Pentium 4 brand is the Intel Core 2 brand, released on July 27, 2006. The underlying microarchitecture is the Core microarchitecture, and the first chips implementing it (in 65 nm) are called "Conroe". Intel Core 2 processors have been released as single, dual and quad core processors.
Processors implementing the Core microarchitecture were marketed under the "Core 2"-brand, because processors based on the Yonah-microarchitecture had already been marketed under the Core-brand.


Apple A8X

The Apple A8X is a 64-bit ARM-based system on a chip (SoC) designed by Apple Inc. and manufactured by TSMC. It first appeared in the iPad Air 2, which was announced on October 16, 2014. It is a variant of the A8 inside the iPhone 6 family of smartphones and Apple states that it has 40% more CPU performance and 2.5 times the graphics performance of its predecessor, the Apple A7.
Design.
The A8X has three cores clocked at 1.5 GHz, a more powerful GPU compared to the A8 and it contains 3 billion transistors. With an extra 100 MHz and an additional core, the A8X performs around 13% better on single threaded and 55% better on multithreaded operations than the A8 inside the iPhone 6 and iPhone 6 Plus.
Further comparison to the A8 shows that the A8X uses a metal heat spreader, which the A8 does not, and it doesn't use the package on package configuration with included RAM which the A8 does. This is similar to how the older "X" variants, the A5X and A6X, were designed. Instead the A8X in the iPad Air 2 uses an external 2 GB RAM module.
In a first for Apple, the A8X is reported to have a semi-custom GPU. The A8X uses an 8-cluster GPU based on Imagination Technologies PowerVR Series 6XT architecture. Officially, the largest implementation of Rogue is a 6-cluster design, indicating that Apple has made customizations to the design in order to provide higher performance. This GPU is referred to as the GXA6850, with the "A" denoting the Apple customization.
Patent litigation.
The A8X's branch predictor has been claimed to infringe on a 1998 patent. On October 14, 2015, a district judge found Apple guilty of infringing U.S. patent , "Table based data speculation circuit for parallel processing computer", on the Apple A7 and A8 processors. The patent is owned by Wisconsin Alumni Research Foundation (WARF), a firm affiliated with the University of Wisconsin. On July 24, 2017, Apple was ordered to pay WARF $506 million for patent infringement. Apple filed an appellate brief on October 26, 2017 with the U.S. Court of Appeals for the Federal Circuit, that argued that Apple did not infringe on the patent owned by the Wisconsin Alumni Research Foundation. On September 28, 2018, the ruling was overturned on appeal and the award thrown out by the U.S. Federal Circuit Court of Appeals. The patent expired in December 2016.


Intel MPX

Intel MPX (Memory Protection Extensions) is a set of extensions to the x86 instruction set architecture. With compiler, runtime library and operating system support, Intel MPX claimed to enhance security to software by checking pointer references whose normal compile-time intentions are maliciously exploited at runtime due to buffer overflows. In practice, there have been too many flaws discovered in the design for it to be useful, and support has been deprecated or removed from most compilers and operating systems. Intel has listed MPX as a removed in 2019 and onward hardware in section 2.5 of it's Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1.
Extensions.
Intel MPX introduces new bounds registers, and new instruction set extensions that operate on these registers. Additionally, there is a new set of "bound tables" that store bounds beyond what can fit in the bounds registers.
MPX uses four new 128-bit bounds registers, codice_1 to codice_2, each storing a pair of 64-bit lower bound (LB) and upper bound (UB) values of a buffer. The upper bound is stored in ones' complement form, with codice_3 (create bounds) and codice_4 (check upper bound) performing the conversion. The architecture includes two configuration registers codice_5 (codice_6 in user space and codice_7 in kernel mode), and a status register codice_8, which provides a memory address and error code in case of an exception.
Two-level address translation is used for storing bounds in memory. The top layer consists of a Bounds Directory (BD) created on the application startup. Each BD entry is either empty or contains a pointer to a dynamically created Bounds Table (BT), which in turn contains a set of pointer bounds along with the linear addresses of the pointers. The bounds load (codice_9) and store (codice_10) instructions transparently perform the address translation and access bounds in the proper BT entry.
Intel MPX was introduced as part of the Skylake microarchitecture.
Intel Goldmont microarchitecture also supports Intel MPX.
Analysis of Intel MPX.
A study examined a detailed cross-layer dissection of the MPX system stack and comparison with three prominent software-based memory protection mechanisms (AddressSanitizer, SAFECode, and SoftBound) and presents the following conclusions.
In addition, a review concluded MPX was not production ready, and AddressSanitizer was a better option. A review by Kostya Serebryany at Google, AddressSanitizer's developer, had similar findings.
Meltdown.
Another study exploring the scope of Spectre and Meltdown security vulnerabilities discovered that Meltdown can be used to bypass Intel MPX, using the Bound Range Exceeded (#BR) hardware exception. According to their publication, the researchers were able to leak information through a Flush+Reload covert channel from an out-of-bound access on an array safeguarded by the MPX system. Their Proof Of Concept has not been publicly disclosed.


Bimini Run

Bimini Run is a third person shooter/action video game for the Sega Mega Drive/Genesis. It was developed and published by Nuvision Entertainment. Since it was a two-player game, Bimini Run allowed both players to traverse a wide scrolling environment on objective based missions.
Story.
The story begins with the kidnapping of a Kim Ohara, the sister of an expert motorboat driver and secret agent Kenji. The kidnapping is immediately traced to Dr. Orca, who has hired other boat drivers and helicopter pilots to protect his island laboratory/fortress where he plans on unleashing a super weapon on the entire world. Kenji and his partner Luka arm themselves on a power boat and prepare to rescue Kim and save the world.
Gameplay.
The player controls the boat's steering by Kenji and shooting a rapid-fire bazooka by Luka. The gameplay consists of moving around the map (typically, an archipelago), completing objectives and shooting enemies who stand in the way. The player instantly loses a life if hit, so maneuvering to dodge enemy fire and other obstacles is a critical skill to learn. Typical objectives include reaching and destroying certain structures on the islands or following something around the map to their destination. New objectives are received in the form of radio messages notified of by a specific sound effect.
In the pause menu, the player can see the last radio message and the map of the area with current targets marked on it.


LOADER.COM


TUX web server

The TUX web server is an in-kernel web server for Linux licensed under the GNU General Public License (GPL). It was maintained by Ingo Molnár.
It is currently limited to serving static web pages and coordinating between kernelspace modules, userspace modules, and regular userspace web server daemons that provide dynamic content. Regular userspace web servers do not need to be altered in any way for TUX to coordinate with them. However, userspace code has to use a new interface based on the codice_1 system call.
The main differences between TUX and other webservers include:
While only being able to serve static web pages could be seen as a significant disadvantage, TUX has one significant advantage: it is able to serve pages faster than traditional web servers. This is largely due to its place directly within the kernel, where it can improve performance by taking advantage of facilities not available to traditional web servers, which run outside of the kernel. However, this also means that TUX does not generate dynamic content. Because it is running within the kernel, such dynamic content cannot take advantage of functions that the kernel provides to userspace programs, and would create tremendous security issues.
TUX is capable of launching CGI programs to provide dynamic content. However, CGI suffers from significant performance limitations, so a CGI-heavy site would gain no performance advantage from using TUX. TUX can also redirect any request it cannot process to a traditional userspace web server daemon, for example Apache or lighttpd. This allows TUX to handle both dynamic content and errors in a safer, faster, and RFC-correct manner.
TUX has never been an integrated part of the official Linux kernel, although it has been shipped in some distributions, notably Red Hat, SuSE and Fedora. It served as a test bed (and motivator) for many features which were integrated separately. One major component was the Native POSIX Thread Library, which, with the right tuning parameters, allows userspace web servers to serve web pages at a speed very close to that of a kernelspace web server like TUX but without its limitations. Core kernel developers also argued that having an HTTP daemon within the kernel is dangerous. For example, a common bug such as a buffer overflow within TUX could give an attacker superuser control over the machine. Therefore, it is much safer to keep the HTTP daemon entirely within userspace, where a bug does not necessarily give an attacker total control.
Project status.
TUX is completely unnecessary, today--the 2.6 kernel can
provide nearly the same static file serving performance as an the 2.4
kernel did with TUX, and the stability is significantly better. TUX
died because it no longer serves a purpose.
If you want to serve static files very efficiently, and you want to
support large numbers of simultaneous HTTP sessions, then there are
some modern options. Nginx is the current favorite, I think.