Pentium D

The Pentium D brand refers to two series of desktop dual-core 64-bit x86-64 microprocessors with the NetBurst microarchitecture, which is the dual-core variant of Pentium 4 "Prescott" manufactured by Intel. Each CPU comprised two dies, each containing a single core, residing next to each other on a multi-chip module package. The brand's first processor, codenamed Smithfield, was released by Intel on May 25, 2005. Nine months later, Intel introduced its successor, codenamed Presler, but without offering significant upgrades in design, still resulting in relatively high power consumption. By 2004, the NetBurst processors reached a clock speed barrier at 3.8 GHz due to a thermal (and power) limit exemplified by the "Presler's" 130 watt thermal design power (a higher TDP requires additional cooling that can be prohibitively noisy or expensive). The future belonged to more energy efficient and slower clocked dual-core CPUs on a single die instead of two. The final shipment date of the dual die "Presler" chips was August 8, 2008, which marked the end of the Pentium D brand and also the NetBurst microarchitecture.
Pentium D/Extreme Edition.
The dual-core CPU is capable of running multi-threaded applications typical in transcoding of audio and video, compressing, photo and video editing and rendering, and ray-tracing. Single-threaded applications, including most older games, do not benefit much from a second core compared to an equally clocked single-core CPU. Nevertheless, the dual-core CPU is useful to run both the client and server processes of a game without noticeable lag in either thread, as each instance could be running on a different core. Furthermore, multi-threaded games benefit from dual-core CPUs.
In 2008, many business applications were not optimized for multiple cores. They ran at similar speed when not multitasking on the Pentium D or older Pentium 4 branded CPUs at the same clock speed. However, in multitasking environments such as BSD, Linux, Microsoft Windows operating systems, other processes are often running at the same time; if they require significant CPU time, each core of the Pentium D branded processor can handle different programs, improving overall processing speed over its single-core Pentium 4 counterpart.
Smithfield.
In April 2005, Intel's biggest rival, AMD, had x86 dual-core microprocessors intended for workstations and servers on the market, and was poised to launch a comparable product intended for desktop computers. As a response, Intel developed Smithfield, the first x86 dual-core microprocessor intended for desktop computers, beating AMD's Athlon 64 X2 by a few weeks. Intel first launched "Smithfield" on April 16, 2005 in the form of the 3.2 GHz Hyper-threading enabled "Pentium Extreme Edition 840". On May 26, 2005, Intel launched the mainstream Pentium D branded processor lineup with initial clock speeds of 2.8, 3.0, and 3.2 GHz with model numbers of 820, 830, and 840 respectively. In March 2006, Intel launched the last "Smithfield" processor, the entry-level Pentium D 805, clocked at 2.66 GHz with a 533 MT/s bus. The relatively cheap "805" was found to be highly overclockable; 3.5 GHz was often possible with good air cooling. Running it at over 4 GHz was possible with water cooling, and at this speed the "805" outperformed the top-of-the-line processors (May 2006) from both major CPU manufacturers (the AMD "Athlon 64 FX-60" and Intel "Pentium Extreme Edition 965") in many benchmarks including power consumption.
The 805 and 820 models had a 95 watt TDP. All other models were rated at 130 watt.
All "Smithfield" processors were made of two 90 nm Prescott cores, next to each other on a single die with 1 MB of Level 2 (L2) cache per core. Hyper-threading was disabled in all Pentium D 8xx-series "Smithfields" with the exception of the "Pentium Extreme Edition 840". Smithfield did not support Intel VT-x—Intel's x86 virtualization (formerly Vanderpool).
All Pentium D processors supported Intel 64 (formerly EM64T), XD Bit, and were manufactured for the LGA 775 form factor. The only motherboards guaranteed to work with the Pentium D (and Extreme Edition) branded CPUs were those based on the 945-, 955-, 965- and 975-series Intel chipsets, as well as the nForce 4 SLI Intel Edition and ATI Radeon Xpress. The Pentium D 820 did not work with the nForce 4 SLI Intel Edition chipset due to some power design issues, though they were rectified in the X16 version. The 915- and 925-series chipsets did not work at all with the "Smithfields", as they did not support more than one core (to prevent manufacturers making a cheap dual CPU motherboard capable of supporting Xeon CPU's, as had happened with the 875P chipset). The 865- and 875-series chipsets supported multiprocessing. Motherboards with them might be Pentium D compatible with an updated BIOS.
A week after its launch, Intel officially denied a report in "Computerworld Today Australia" that the Pentium D branded CPUs included "secret" digital rights management features in their hardware that could be utilized by Microsoft Windows and other operating systems, but was not publicly disclosed. While Intel admitted that there were some DRM technologies in the 945- and 955-series chipsets, it stated that the extent of the technologies was exaggerated, and that the technologies in question had been present in Intel's chipsets since the 875P.
Smithfield XE.
The Pentium Extreme Edition (PXE) was introduced at the Spring 2005 Intel Developers Forum, not to be confused with the "Pentium 4 Extreme Edition" (an earlier, single-core processor occupying the same niche). The processor was based on the dual-core Pentium D branded "Smithfield", but with Hyper-threading enabled, thus any operating system saw four logical processors. It also had an unlocked multiplier to allow for easier overclocking. It was initially released as Intel Pentium Extreme Edition 840 at 3.20 GHz, in early 2005, at a price point of $999.99 (OEM price) or $1,200 (retail). The only chipsets that worked with the Extreme Edition 840 were Intel's 955X, NVIDIA's nForce4 SLI Intel Edition, and ATi Radeon Xpress 200. Using a Pentium Extreme Edition branded CPU with an Intel 945-series chipset will disable Hyper-threading.
Presler.
The last generation of Pentium D branded processors was Presler released on January 16, 2006, identified by the product code 80553, and made of two 65 nm-process cores found also in Pentium 4 branded Cedar Mill CPUs. "Presler" introduced the 'multi-chip module, or MCM, which consisted of two single-core dies placed next to each other on the same substrate package. This allowed Intel to produce these processors at a reduced production cost as a result of higher yields. "Presler" was supported by the same chipsets as "Smithfield". It was produced using 65 nm technology similar to Yonah. "Presler" communicated with the system using an 800 MT/s FSB, and its two cores communicated also using the FSB, just as in "Smithfield". "Presler" also included Intel VT-x (formerly Vanderpool) – although this was limited to the 9x0 models, and not in the 9x5 models– Intel 64, XD bit, and EIST (Enhanced Intel SpeedStep Technology). "Presler" was released in the first quarter of 2006 with a 2x2 MB Level 2 cache. Its models included 915, 920, 925, 930, 935, 940, 945, 950 and 960 (with a respective 2.8, 2.8, 3.0, 3,0, 3.2, 3.2, 3.4, 3.4, and 3.6 GHz clock frequency).
All steppings of "Presler" models 915, 920, 925, 930, and 935, as well as the C1, D0 steppings of 940, 945 featured a 95 watt TDP. All other models (i.e. certain models with 3.2 GHz or faster clock frequencies) were rated at 130 watt — a 37% increase in power consumption.
[*] The first batch of "Presler" processors (revision B1) had the EIST feature turned off by a microcode update because of stability issues. That affected only its power consumption, when idle, and thermal dissipation. Chips with working EIST started shipping in Q2 2006. They had a different S-Spec number which can be found in Intel errata documentation.
Presler XE.
The Pentium Extreme Edition based on the dual-core Pentium D branded "Presler" was introduced as the 955 model, at 3.46 GHz, and used a 1066 MT/s FSB compared to the 800 MT/s in the non-Extreme edition. A second version, the 965 at 3.73 GHz followed in March 2006. Both CPUs also feature Hyper-Threading Technology and an unlocked multiplier. Overclockers have been able to overclock the core to 4.26 GHz using air cooling simply by raising the unlocked CPU multiplier.
The 'Presler Extreme Edition' was intended to only be combined with the Intel 975X chipset, it could also work with the 955X chipset, though this combination was not supported by Intel. The i975X featured the ICH7R southbridge and supported all LGA 775 (Socket T) Pentium 4, Pentium D, and Pentium Extreme Edition branded processors.
Successor.
The Pentium D brand was succeeded on July 27, 2006, by the Core 2 branded line of microprocessors with the Core microarchitecture released as dual- and quad-core microprocessors branded Duo, Quad, and Extreme.
Implementation.
In a single-processor scenario, the CPU-to-northbridge link is point-to-point and the only real requirement is that it is fast enough to keep the CPU fed with data from memory.
When assessing the Pentium D, it is important to note that it is essentially two CPUs in the same package and that it will face the same bus contention issues as a pair of Xeons prior to the Dual Independent Bus architecture introduced with the Dual-Core Dempsey Xeons. To use a crude analogy one could say that instead of using a single cable between CPU and north bridge, one must use a Y-splitter. Leaving aside advanced issues such as cache coherency, each core can only use half of the 800 MT/s FSB bandwidth when under heavy load.
Comparison to Athlon 64 X2.
The competing Athlon 64 X2, although running at lower clock rates and lacking Hyper-threading, had some significant advantages over the Pentium D, such as an integrated memory controller, a high-speed HyperTransport bus, a shorter pipeline (12 stages compared to the Pentium D's 31), and better floating point performance, more than offsetting the difference in raw clock speed. Also, while the Athlon 64 X2 inherited mature multi-core control logic from the multi-core Opteron, the Pentium D was seemingly rushed to production and essentially consisted of two CPUs in the same package. Indeed, shortly after the launch of the mainstream Pentium D branded processors (26 May 2005) and the Athlon 64 X2 (31 May 2005), a consensus arose that AMD's implementation of multi-core was superior to that of the Pentium D. As a result of this and other factors, AMD surpassed Intel in CPU sales at US retail stores for a period of time, although Intel retained overall market leadership because of its exclusive relationships with direct sellers such as Dell.
Comparison to Pentium Dual-Core.
In 2007, Intel released a new line of desktop processors under the brand Pentium Dual Core, using the Core microarchitecture (which was based upon the Pentium M architecture, which was itself based upon the Pentium III). The newer Pentium Dual-Core processors give off considerably less heat (65 watt max) than the Pentium D (95 or 130 watt max). They also run at lower clock rates, only have up to 2 MB L2 Cache memory while the Pentium D has up to 2×2 MB, and they lack Hyper-threading.
The Pentium Dual-Core has a wider execution unit (four issues wide compared to the Pentium D's three) and its 14 stages-long pipeline is less than half the length of the Pentium D's, allowing it to outperform the Pentium D in most applications despite having lower clock speeds and less L2 cache memory.


SET (command)


SPARC T3

The SPARC T3 microprocessor (previously known as UltraSPARC T3, codenamed "Rainbow Falls", and also known as UltraSPARC KT or "Niagara-3" during development) is a multithreading, multi-core CPU produced by Oracle Corporation (previously Sun Microsystems). Officially launched on 20 September 2010, it is a member of the SPARC family, and the successor to the UltraSPARC T2.
Performance.
Overall single socket and multi-socket throughput increased with the T3 processor in systems, providing superior throughput with half the CPU socket requirements to its predecessor.
The throughput (SPEC CINT2006 rate) increased in single a socket T3-1 platform in comparison to its predecessor T2+ processor in a dual-socket T5240 platform.
Under simulated web serving workloads, dual-socket based SPARC T3 systems benchmarked better performance than quad-socket (previous generation) UltraSPARC T2+ systems (as well as competing dual and quad socket contemporary systems).
History.
Online IT publication "The Register" incorrectly reported in June 2008 that the microprocessor would have 16 cores, each with 16 threads. In September 2009 they published a roadmap that instead showed 8 threads per core. During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads. According to the ISSCC 2010 presentation:
"A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to
maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s
support the required bandwidth. Six clock and four voltage domains, as well as power
management and circuit techniques, optimize performance, power, variability and yield trade-offs
across the 377mm2 die."
Support for the UltraSPARC T3 was confirmed on July 16, 2010 when the ARCBot under Twitter noted unpublished PSARC/2010/274 which revealed a new "-xtarget value for UltraSPARC T3" being included in OpenSolaris.
During Oracle OpenWorld in San Francisco on September 20, 2010, the processor was officially launched as the "SPARC T3" (dropping the "Ultra" prefix in its name), accompanied by new systems and new reported benchmarks claiming world-record performance. Varied real-world application benchmarks were released with full system disclosures. Internationally recognized SPEC benchmarks were also released with full system disclosures.
Oracle disclosed that SPARC T3 was built with a 40 nm process.
Features.
SPARC T3 features include:
Systems.
With the release of the SPARC T3 chip, the new brand of Oracle SPARC T-series servers was introduced to the market, effectively replacing CMT (UltraSPARC T2/T2 Plus) machines from the previous SPARC Enterprise product line. Fewer physical products from the former server line were refreshed with the T3 chip, reducing the total number of servers respectively to four:
Virtualization.
Like the prior T1, T2, and T2+ processors, the T3 supports Hyper-Privileged execution mode. The T3 supports up to 128 Oracle VM Server for SPARC domains (a feature formerly known as "Logical Domains").
Performance improvement versus T2 and T2+.
The SPARC T3 processor is effectively two T2+ processors on a single die. The T3 has:


Class driver

In computing, a class driver is a type of hardware device driver that can operate a large number of different devices of a broadly similar type. Class drivers are very often used with USB based devices, which share the essential USB protocol in common, and devices with similar functionality can easily adopt common protocols.
Instead of having a separate driver for every kind of CD-ROM device, a class driver can operate a wide variety of CD-ROMs from different manufacturers. To accomplish this the manufacturers make their products compatible with a standardized protocol.
In technical terms, a class driver is used as a base or ancestor class for specific drivers which need to have slightly different or extended functionality, but which can take advantage of the majority of the functionality provided by the class driver. This concept is a key aspect of object oriented programming, which when extended to drivers makes it much easier for hardware vendors to provide driver support for their products.


VIA Isaiah


DIR (command)


UNIX System III

UNIX System III (or System 3) is a discontinued version of the Unix operating system released by AT&T's Unix Support Group (USG).
AT&T announced System III in late 1981, and it was first released outside of Bell Labs in 1982. UNIX System III was a mix of various AT&T Unixes: Version 7 Unix, PWB/UNIX 2.0, CB UNIX 3.0, UNIX/RT and UNIX/32V. System III supported the DEC PDP-11 and VAX computers.
The system was apparently called System III because it was considered the outside release of UNIX/TS 3.0.1 and CB UNIX 3 which were internally supported Bell Labs Unices; its manual refers to it as UNIX Release 3.0 and there were no Unix versions called System I or System II. There was no official release of UNIX/TS 4.0 (which would have been "System IV") either, so System III was succeeded by System V, based on UNIX/TS 5.0.
System III introduced new features such as named pipes, the uname system call and command, and the run queue. It also combined various improvements to Version 7 Unix by outside organizations. However, it did not include notable additions made in BSD such as the C shell (csh) and screen editing.
Third-party variants of System III include (early versions of) HP-UX, IRIX, IS/3 and PC/IX, PC-UX, PNX, SINIX, Venix and Xenix.


RMDIR


Intel Architecture Labs

Intel Architecture Labs (IAL) was the personal-computer system research-and-development arm of Intel during the 1990s.
History and formation.
IAL was created by Intel Vice-President Ron Whittier together with Craig Kinnie and Steven McGeady to develop the hardware and software innovations considered to be lacking from PC OEMs and Microsoft in the late 1980s and 1990s. IAL pursued both hardware and software initiatives, both of which were important factors in the evolution of, and the control of, the PC industry.
Rivalry with Microsoft.
Around the same time in the PC industry, Microsoft was emerging as the defacto industry standard in PC Operating Systems and software application for the PC. As IAL's software ambitions began to overlap with Microsoft's, a rivalry broke out between Intel and Microsoft as it related to the amount of influence, control, and the setting of standards in the rapidly growing PC industry. Over time, IAL's work in software projects was gradually de-emphasized after the software efforts collided with similar activities by Microsoft.
Native Signal Processing (NSP).
Native Signal Processing ("NSP") was an example of a significant software effort in IAL. NSP was a software initiative to allow Intel-based PCs to run time-sensitive code independently of the operating system, allowing real-time audio and video processing on the microprocessors of the mid-1990s. Intel, who's microprocessors powered PC hardware designs, invested heavily in improving the performance of its chips. As a result of the increase in performance, Intel saw an opportunity to transfer software workloads from specialized microprocessors over to the central Intel microprocessors. This strategy was fundamental to Intel's vision of a powerful central microprocessor made with its advanced chip building capabilities. NSP was, in that regard, a gold mine of power-hungry software workloads which were previously running on Digital Signal Processor chips. This led to IAL's decision to embark on NSP, a large software initiative to gradually move the algorithms and software implementations from DSPs to the central Intel microprocessor.
IAL's decision to pursue NSP clashed with a similar project that was brewing at Microsoft. NSP's software architecture was designed to be agnostic of the software operating system. This was a common strategic direction with PC chip manufacturers in the 1980s and 1990s because it allowed chips to be used in a multitude of software operating environments, and not just the Microsoft operating systems (OS) such as Microsoft Windows. Microsoft's equivalent project to IAL's NSP was called Direct Show, and at the outset of NSP, this posed a conflict and a challenge for the working relationship between Intel and Microsoft (traditionally very close partners with highly aligned interests). When Intel proposed the NSP software design to Microsoft, it became clear that the two initiatives (NSP & Direct X) were in direct conflict. Microsoft refused to put their support behind a competing standard such as NSP, especially one with the potential to level the OS playing field for PCs. Despite this conflict, IAL continued to work on NSP, showing demonstrations of DSP software running smoothly on the central microprocessor. With every generation of performance and functionality improvements, Microsoft refused to support NSP in its operating systems. Microsoft and Intel, both large and influential companies who worked with the same PC Original Equipment Manufacturers found themselves at odds over the direction of the software and hardware in the PC industry. Microsoft convinced PC makers that the Intel NSP device drivers would render their systems unsupported by the Windows operating system, and in turn this led Intel to pull back from promoting the software, leaving NSP as an orphan project. Although NSP did not achieve commercial success like Direct X, the concepts, prototypes, and implementations of DSP algorithms on native Intel microprocessors was widely recognized as an impressive technological feat at the time, and indirectly supported the overall notion of moving dedicated software workloads to general purpose microprocessors like Intel's.
Internet browser.
IAL also tangled with Microsoft by supporting Netscape and their early browser, and by producing a fast native x86 port of the Java system. Most of these projects were later shelved, and after 1997 IAL tended not to risk competing with Microsoft. The details of IAL's conflicts with Microsoft over software were revealed in Steven McGeady's testimony in the Microsoft antitrust trial.
Not all of IAL's software efforts met bad ends due to Microsoft—IAL developed one of the first software digital video systems, Indeo(tm) - technology that was used in its ProShare videoconferencing product line but suffered later from neglect and was sold to another company in the late 1990s.
Input/output interconnect projects.
However, IAL successes in the hardware world are legendary, and include PCI, USB, AGP, the Northbridge/Southbridge core logic architecture and PCI Express.
Universal Serial Bus (USB).
USB, in particular, was developed in the Oregon offices of IAL, where the architects of PCI and the Plug and Play initiatives assisted in building the first peripheral interconnect that would work with devices without requiring the PC to be dismantled. This vision of a sealed PC that could be extended with external devices was central to Intel's strategy of making the PC more like a consumer device. USB emerged as the lead contender for the interconnect standard interface, and an Intel team of engineers set out to create an industry standard.
Intel's engineering standards were well known as being among the highest in the industry, driven by the company's adherence to careful development of technical specifications before setting out to design or develop a new product. As part of the engineering process, Intel engineers wrote detailed technical specifications during the early phases of design, to ensure the features were well understood and agreed upon. Since Intel's products usually involved complex chip designs, errors or omissions in the design or features could prove costly if done without the appropriate rigor and review that came along with the detailed engineering reviews that accompanied the design process.
In the early 1990s the initial USB specification was spearheaded in IAL, driven by a small team of software and hardware architects & engineers. The engineers were scattered across Intel campuses in Oregon and California. In Oregon, the chief engineers of the USB project in IAL included Brad Hosler, Shelagh Callahan, John Howard, John Garney, and Kosar Jaff, all based in the Hillsboro Oregon Intel site.
While the IAL-based USB team was primarily located in Intel's campus in Hillsboro Oregon, the USB project also included a team of chip designers in the Intel Chipset Group (Peripheral Components Division) located on the Intel campus in Folsom, California. The partnership between the IAL engineers and the chipset engineers was crucial in the development of the original USB specification. Throughout the development of the USB 1.0 specifications, the IAL engineers worked closely with chipset designers (inside and outside Intel). Together, the engineering teams in Oregon and California were tasked with building the world's first USB based computer by designing and manufacturing the USB Host Controller.
USB host controller design.
A critical component of the USB design was the interface between hardware and software, which was the domain of the USB Host Controller, the brains behind the interconnect that all USB devices communicate with. The USB Host Controller was embedded in the South Bridge chip, and was designed to match the USB specification being developed by the IAL engineers. USB was, like PCI, a unique combination of hardware and software definitions, and as a result the project needed a software engineering team from the outset, unlike typical Intel hardware
projects. The USB software device driver "stack" was initially developed on Windows 95 using the Virtual Device Driver (VxD) model of Windows 95. The VxD-based USB driver stack was helpful to Microsoft as they implemented a brand new USB stack using the emerging Windows Driver Model (WDM) largely because of Microsoft's strategic shift towards Windows NT, and away from Windows 95. WDM was uniquely compatible with both operating systems, and the decision to abandon the VxD stack was a win-win for Intel and Microsoft. The collaboration between IAL and Microsoft improved during the development of USB 1.0, largely driven by the software developers that Intel hired into its IAL labs. Software developers at Microsoft were able to speak a familiar technical language with their fellow software developers from IAL, allowing the group to work as a single unit to drive the USB standard into the Windows-based PCs of the 1990s and beyond.
Collaboration with industry partners.
Unlike previous IAL projects which had resulted in considerable conflict and tension with other companies in the PC industry, the USB project stood out as a highlight of the cooperation between IAL's engineers and the rest of the PC industry. The IAL USB team worked closely with Microsoft, sharing their lessons learned, and helping the Microsoft team add support for the USB interconnect in Windows, as well as in Microsoft peripheral devices, such as Microsoft keyboards. The IAL team dedicated a full time engineer to work with Microsoft closely so as to avoid delays and repeating mistakes the Intel team had made during the development of the specification and first hardware and software implementations. The USB team in IAL, while small and focused, developed a reputation for being collaborative, supportive, and focused on educating the industry about the emerging USB standard. The engineers were regular presenters at USB Developer's Conferences and collaborated with dozens of hardware and software companies who were eager to implement the industry's first broadly-adopted interconnect standard to make PCs more user friendly.
Disbanding.
In 2001, after the departure of all of its creators, IAL was disbanded and replaced with the very different Intel Labs under Pat Gelsinger, though most of the creative talent that had been in IAL was by then scattered across the company or had left entirely. In a 2005 re-organization, Intel Labs itself was reorganized with the intent of rebuilding a research function.
Compare Intel's Architecture Development Lab.


List of Debian project leaders

This is a chronological list of Debian project leaders. Debian is a computer operating system composed of software packages released as free and open-source software primarily under the GNU General Public License, developed by a group of individuals known as the Debian project. The Project Leader is a role defined in the "Debian Constitution", and is elected once per year by the Debian developers.
Leaders.
Ian Murdock.
Ian Murdock, the first Debian project leader and the "ian" in "Debian", was an American software engineer. He founded the Debian project in August 1993, naming it after his then-girlfriend and later wife Debra Lynn, and himself (Deb and Ian). He later started Progeny Linux Systems, a commercial Linux company.
He was the Chief Technology Officer of the Free Standards Group and elected chair of the Linux Standard Base workgroup, CTO of the Linux Foundation when the group was formed from the merger of the Free Standards Group and Open Source Development Labs.
He left the Linux Foundation to join Sun Microsystems leading the Project Indiana making OpenSolaris distribution with GNU userland.
From 2011 until 2015 Murdock was Vice President of Platform and Developer Community at Salesforce Marketing Cloud.
From November 2015 until his death Murdock was working for Docker, Inc.
Bruce Perens.
Bruce Perens is an American computer programmer and advocate in the free software movement and author of BusyBox. He created The Open Source Definition and published the first formal announcement and manifesto of open source. He co-founded the Open Source Initiative (OSI) with Eric S. Raymond and Software in the Public Interest.
He represented Open Source at the United Nations World Summit on the Information Society, at the invitation of the United Nations Development Programme in 2005.
He was the Debian project leader from April 1996 to December 1997, replacing Ian Murdock.
Ian Jackson.
Ian Jackson is a long-time free software author and Debian developer. He wrote dpkg, SAUCE (Software Against Unsolicited Commercial Email), userv and debbugs. He used to maintain the Linux FAQ. He was the Debian project leader between 1998 and 1999. Debian GNU/Linux 2.0 (hamm) was released during his term. He was also a vice-president and then president of Software in the Public Interest in 1998 and 1999. He was a member of the Debian Technical Committee until November 2014 when he resigned as a result of controversies around the migration of Debian to systemd.
Wichert Akkerman.
Wichert Akkerman is a Dutch computer programmer who contributed to Debian, dpkg, Plone and strace. He was elected for two terms as the Debian project leader and served from January 1999 to March 2001, and was succeeded by Ben Collins. He has also served as the Secretary to Software in the Public Interest.
Ben Collins.
Ben Collins is an American programmer, Linux developer and system administrator. From April 2001 to April 2002 Collins acted as the Debian project leader. During his tenure he specialised on the UltraSPARC port and advocated for proactive security and testing policies. Collins had stood for Debian project leader two times prior to being elected. When he took up the role he commented that when he joined the project Ian Jackson, who was at the end of his term as Debian project leader, was "very inactive". Jackson was followed by Wichert Akkerman for two terms, and according to Collins "did an excellent job keeping Debian going". Once elected Collins declared his intent to get Debian moving and during his tenure he sought to provide strategic leadership to build the Debian movement. Collins was succeeded as Debian project leader by Bdale Garbee.
Bdale Garbee.
Bdale Garbee is an American computer specialist who works with Linux, particularly Debian. He is also an amateur radio hobbyist, a member of AMSAT, Tucson Amateur Packet Radio (former vice-president)
and the American Radio Relay League and a member of the board of directors of the Linux Foundation and FreedomBox Foundation's board of directors.
He was the Debian project leader for one year between 2002 and 2003.
Martin Michlmayr.
Martin Michlmayr is a free and open-source software advocate and Debian developer. Michlmayr completed a doctorate in technology management at the University of Cambridge in 2007. The focus of this research was on quality improvement in free software and open source projects, and particularly on release management processes and practices. Between 2008 and 2014 served on the board of directors of the Open Source Initiative and is a member of Software Freedom Conservancy's evaluation committee. In the past he acted as an advisor to Software in the Public Interest.
He was elected as Debian project leader in 2003 and re-elected to that position in 2004.
Branden Robinson.
G. Branden Robinson is known for his contributions to the packaging of the X Window System, and his tenure as the Debian project leader from April 2005 to April 2006. He has contributed to Debian since 1998. His most visible contribution is his long-time maintenance of the X Window System packages, which he took over from Mark W. Eichin by uploading the 3.3.2 release of the XFree86 packages on 1998-03-25. Robinson was elected by his fellow developers in 2005, after running for the position five times between 2001 and 2005. He succeeded Martin Michlmayr, who had been elected project leader in 2003 and 2004. During Branden Robinson's term as a leader, the project achieved some incremental successes, such as a stable point release of "stable" by new release managers for that distribution, having AMD64 added to "testing", and the inclusion of modular X in unstable.
Anthony Towns.
Anthony Towns (born 21 June 1978) is a computer programmer who was a long-time Debian release manager, "ftpmaster" team member and later the Debian project leader (from 17 April 2006 until 17 April 2007). He ran for Debian project leader in 2005, but was defeated by Branden Robinson by a margin of 23 effective votes. He ran again in 2006, and was elected as the new Debian project leader on 9 April 2006, beginning his term on 19 April 2006. Towns was elected by the second-narrowest-ever margin and was the first project leader to face a recall vote while in office. Towns was also the first project leader whose support by Debian Developers was reaffirmed through a General Resolution. Since a great deal of Debian work takes place in Europe, Queensland-based Towns created the post of "Debian Second in Charge" (2IC) to lead discussion, support developers, and represent the project in locations which could more easily be reached by the runner-up candidate, Steve McIntyre, than himself.
In September 2006, the "Dunc-tank" project started a fund-raising programme to help Debian release its next distribution, "Etch", on the scheduled date of 4 December 2006. Towns's involvement with Dunc-Tank came under severe criticism, including hitherto-unseen calls to end his Debian project leadership to make clear that the Dunc-Tank project was not officially supported by Debian project members. Some developers slowed down their unpaid work on Debian in response to the programme. Debian "Etch" was not released in December 2006 as hoped; instead its release happened in April 2007. Nonetheless, Towns views the outcome of the Dunc Tank project as positive, highlighting that Dunc-Tank opposition helped to improve quality of Debian Etch.
Sam Hocevar.
Samuel "Sam" Hocevar is a French software and video game developer,
author of the WTFPL version 2, a permissive free software license.
Hocevar was a Wikimedia France board member from 2005 to 2006.
He is known for his contributions to the VideoLAN project and his expertise in reverse engineering and image processing and for authoring the first CAPTCHA decoder framework to defeat multiple CAPTCHAs.
He was the Debian project leader from 17 April 2007 to 16 April 2008.
Steve McIntyre.
Steve McIntyre is a software engineer and a long-time Debian developer, known for his contributions in the field of creating Debian CD/DVD images; he is the "debian-cd" team leader and is responsible for generating the official images. McIntyre ran for the post of Debian project leader in 2006 and 2007 but was defeated. During the 2006 term, he acted as "Second in charge" of the Debian Project. In 2008 he was elected the Debian project leader, and was re-elected in 2009. He chose not to run in the 2010 election; that election was won by Stefano Zacchiroli.
Stefano Zacchiroli.
Stefano Zacchiroli is an Italian-French academic and computer scientist who lives and works in Paris.
He became a Debian Developer in 2001 involved mainly in the OCaml packaging and in the quality assurance team.
He was the Debian project leader between April 2010 and April 2013.
Lucas Nussbaum.
Lucas Nussbaum is a French computer science engineer and assistant professor at University of Lorraine, researcher at LORIA laboratory. Nussbaum was elected leader of the Debian project in April 2013. He has been a Debian Developer since 2007. Since then, he has been active, amongst other things, as a Debian Ruby packager, with the Universal Debian Database or the full rebuilds of the Debian Archive.
During the 2012 election, outgoing leader Stefano Zacchiroli announced that this would be the last term for which he would run; thus, in the 2013 election, the election did not include the incumbent. Nussbaum ran for the first time, opposite Gergely Nagy and Moray Allan.
His term started on April 17, 2013.
He was re-elected on April 14, 2014.
Neil McGovern.
Neil McGovern, an Executive Director at the Gnome Foundation, was elected in April 2015, after running for second time in a row.
Mehdi Dogguy.
Mehdi Dogguy, a Tunisian-French technical manager at Électricité de France, was elected in April 2016, running without opponents.
Chris Lamb.
Chris Lamb, a British freelancer, was elected in April 2017, running against the incumbent leader Mehdi Dogguy. He was re-elected in April 2018.
Sam Hartman.
Sam Hartman served as DPL from April 2019 to April 2020.
Hartman worked as the Chief Technologist at the MIT Kerberos Consortium and as
a Security Area Director of the Internet Engineering Taskforce, and joined Debian in 2000. He was elected running against Joerg Jaspert, Jonathan Carter and Martin Michlmayr and focused his term on resolving conflicts in Debian and facilitating project-wide discussions and decision-making on contentious technical issues.
Jonathan Carter.
Jonathan Carter was elected in April 2020, running against Sruthi Chandran and Brian Gupta.


Volari V3

The Volari V3 is a video card manufactured by XGI Technology.
History.
The V3 was introduced on September 15, 2003. It is a budget option, available with an 8x Accelerated Graphics Port interface from Walton Chaintech Corporation. It is similar in performance to the ATI Radeon 9200 SE, but is generally lower-priced.


DRMDOS.SYS


MB86900

The MB86900 is a microprocessor produced by Fujitsu, which implements the SPARC V7 instruction set architecture developed by Sun Microsystems. It was the first implementation of SPARC, introduced in 1986, and was used in the first SPARC-based workstation, the Sun Microsystems Sun-4, from 1987. Its chipset operated at 16.67 MHz. The chipset consisted of two chips, the MB86900 microprocessor and the MB86910 floating-point unit. The chip set was implemented with two 20,000-gate, 1.2 µm complementary metal–oxide–semiconductor (CMOS) gate-arrays fabricated by Fujitsu Limited.


AUTOEXEC.UI


List of MIPS architecture processors

This is a list of processors that penetrate the MIPS instruction set architecture, sorted by year, process size, frequency, die area, and so on. These processors are designed by Imagination Technologies, MIPS Technologies, and others. It displays an overview of the MIPS processors with performance and functionality versus capabilities for the more recent MIPS Aptiv families.
Imagination Technologies.
MIPS Technologies was acquired 17 December 2012, by Imagination Technologies. Since then, the following processors have been introduced by Imagination Technologies.
Imagination Technologies sold MIPS processor rights to Tallwood MIPS Inc in 2017. MIPS Technologies was acquired by Wave Computing in 2018, where "MIPS operates as an IP licensing business unit".
The Warrior P-Class CPU was announced on .
The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and MIPS64 release 6, and will come in three classes of performance and features:
Other designers.
A number of companies licensed the MIPS architecture and developed their own processors.


Combat Cars

Combat Cars is a vehicular combat racing game released for the Sega Genesis in 1994.
Gameplay.
In "Combat Cars", the player races against other cars and can use various kinds of weapons and gadgets to damage their opponents. Each character has his/her own strengths and weaknesses (speed, car handling, etc.), as well as unique weapons. The characters and their vehicles which are equipped with weapons include a shotgun, glue spots that they can leave to slow other cars, homing missiles, mines, and others. There are 24 different tracks available in the game. The player earns money for winning or placing in races, and this money is used to calculate their score. As the player spends this money on upgrades for their vehicle, their score lowers accordingly.
The player must complete the 24 circuit tracks in multiple laps in linear fashion within a time limit if the player can reach the only checkpoint (which is the start/finish line) in a race to extend the time limit, and should the player run out of time or fail a race, the game is over. The player then must enter their name onto the scoreboard, the background being the type of environment the last race took place. After entering their name, the game resets to the SEGA introduction screen. The game also has a 2-player co-op mode.


Epyc

EPYC is a brand of x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets. Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using Infinity Fabric interchip interconnect.
History.
In March 2017, AMD announced a server platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May. That June, AMD officially launched Epyc by releasing the Epyc 7001 series processors. Two years later, in August 2019, the Epyc 7002 series processors based on the Zen 2 microarchitecture released, bringing much better performance and double the cores compared to their predecessors.
The Zen 3 based Epyc microarchitecture is codenamed "Milan".
Design.
The platform includes one- and two-socket systems. In multi-processor configurations, two Epyc CPUs communicate via AMD's Infinity Fabric. Each server chip supports 8 channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes from each are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration. All first generation Epyc processors are composed of four eight-core Zeppelin dies (the same die as found in Ryzen processors) in a multi-chip module, with the varying product core counts produced by symmetrically disabling cores of each core complex on each Zeppelin die.
Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some unavailable features require additional controller chips to make them available on the system.
The first generation of Epyc microprocessors were manufactured by GlobalFoundries using a 14 nm FinFET process licensed from Samsung Electronics. Epyc 2 will be manufactured by TSMC using a 7 nm FinFET process.
Reception.
Initial reception to Epyc was generally positive. Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.
Products.
Server.
First generation Epyc (Naples).
The following table lists the devices using the first generation design.
A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCI-E lanes from each processor for the communication between processors.
Second generation Epyc (Rome).
In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture. The processors feature up to eight 7nm-based "chiplet" processors with a 14 nm-based IO chip providing 128 PCIe lanes in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket. The 7nm "Rome" is manufactured by TSMC. It was released on August 7, 2019.
Third generation Epyc (Milan).
At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture. Milan chips will use Socket SP3, with up to 64 cores on package, and support eight channel DDR4 SDRAM and 128 PCIe 4.0 lanes. It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.
Milan CPUs were launched by AMD on 15 March 2021.
Embedded.
First generation Epyc (Snowy Owl).
In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.
Chinese variants.
A variant created for the Chinese server market by an AMD–Chinese joint venture is the "Hygon Dhyana" system on a chip. It is noted to be a variant of the AMD EPYC, and is so similar that "there is little to no differentiation between the chips". It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market". Later Benchmarks showed that certain floating point instructions are performing worse and AES is disabled, probably to comply with US export restrictions. Cryptography extensions are replaced by Chinese variants.


List of applications of ARM cores

This is a list of applications of ARM cores. It lists products using the various ARM microprocessor cores, sorted by generation release and name.


UserLinux

UserLinux was a project to create an operating system based on Debian, and targeted at business customers. The goal was to provide businesses with a freely available, high quality operating system accompanied by certifications, service, and support options.
The project was initiated by Bruce Perens in late 2003. Subsequent to 2005 and the major success of Ubuntu, a commercial Linux distribution based on Debian by Canonical Ltd. with much the same aims as UserLinux, the project lost steam. No software was shipped, and the project was ultimately abandoned.


SWISH-E

SWISH-E stands for "Simple Web Indexing System for Humans - Enhanced". It is used to index collections of documents ranging up to one million documents in size and includes import filters for many document types.
SWISH-E is based on SWISH, developed by Kevin Hughes. When Kevin Hughes stopped maintaining it, Roy Tennant (then at the University of California, Berkeley Library) requested in the mid-1990s to take responsibility for developing it further as a web indexing tool. Hughes assented, and for several years afterwards UC Berkeley Library staff developers and other volunteers maintained and enhanced it. It is no longer maintained, with an offline website and an archived repository at GitHub.


Shortcut (computing)

In computing, a file shortcut is a handle in a user interface that allows the user to find a file or resource located in a different directory or folder from the place where the shortcut is located. Similarly, an Internet shortcut allows the user to open a page, file or resource located at a remote Internet location or Web site.
Shortcuts are typically implemented as a small file containing a target URI or GUID to an "object", or the name of a target program file that the shortcut represents. The shortcut might additionally specify parameters to be passed to the target program when it is run. Each shortcut can have its own icon. Shortcuts are very commonly placed on a desktop, in an application launcher panel such as the Microsoft Windows Start menu, or in the main menu of a desktop environment. The functional equivalent in the Macintosh operating system is called an alias, and a symbolic link (or symlink) in UNIX-like systems.
Implementations.
Microsoft Windows.
File shortcuts (also known as "shell links") were introduced in Windows 95. Microsoft Windows uses .lnk as the filename extension for shortcuts to local files, and .URL for shortcuts to remote files, like web pages. Commonly referred to as "shortcuts" or "link files", both are displayed with a curled arrow overlay icon by default, and no filename extension. (The extension remains hidden in Windows Explorer even when "Hide extensions for known file types" is unchecked in "File Type" options, because it is controlled by the NeverShowExt option in HKEY_CLASSES_ROOT\lnkfile in the Registry. The IsShortcut option causes the arrow to be displayed.) Shortcut files can be used to launch programs in minimized or maximized window states if the program supports it.
Microsoft Windows .lnk files operate as Windows Explorer extensions, rather than file system extensions. As a shell extension, .lnk files cannot be used in place of the file except in Windows Explorer, and have other uses in Windows Explorer in addition to use as a shortcut to a local file (or GUID). These files also begin with "L".
Although shortcuts, when created, point to specific files or folders, they may break if the target is moved to another location. When a shortcut file that points to a nonexistent target is opened, Explorer will attempt to repair the shortcut. Windows 9x-based versions of Windows use a simple search algorithm to fix broken shortcuts. On Windows NT-based operating systems and the NTFS file system, the target object's unique identifier is stored in the shortcut file and Windows can use the "Distributed Link Tracking" service for tracking the targets of shortcuts, so that the shortcut may be silently updated if the target moves to another hard drive. Windows Installer, introduced in Windows 2000, added another special type of shortcuts called "Advertised Shortcuts."
File shortcuts in Windows can store a working directory path besides the target path. Environment variables can be used. A hotkey can be defined in the shortcut's properties for shortcuts that are located in the Start Menu folders, pinned to the Taskbar or the Desktop. In Windows 2000 onwards, file shortcuts can store comments which are displayed as a tooltip when the mouse hovers over the shortcut.
Generally, the effect of double-clicking a shortcut is intended to be the same as double-clicking the application or document to which it refers, but Windows shortcuts contain separate properties for the target file and the "Start In" directory. If the latter parameter is not entered, attempting to use the shortcut for some programs may generate "missing DLL" errors not present when the application is accessed directly.
File system links can also be created on Windows systems (Vista and up). They serve a similar function, although they are a feature of the file system. Windows shortcuts are files and work independently of the file system, through Explorer.
Beginning with Windows 7, some shortcuts also store Application User Model IDs (AppUserModelIDs). Instead of the target command line, AppUserModelIDs may directly be used to launch applications. Shortcuts with AppUserModelIDs are used by some desktop programs and all WinRT Modern/Universal Windows Platform apps for launching.
Although Windows does not provide convenient tools to create it, Explorer supports a "folder link" or "shell link folder": a folder with the system attribute set, containing a hidden "desktop.ini" (folder customization) file which tells Explorer to look in that same folder for a "target.lnk" shortcut file pointing to another folder. When viewed in Explorer, the shell link folder then appears to have the contents of the target folder in it—that is, the customized folder becomes the effective shortcut. This technique is used by Microsoft Windows for items like WebDAV folders. The advent of file system links in Windows Vista and up has made shell link folders less useful.
There is another type of file that is similar to a “.lnk” file, but has the extension “.cda”. This is used to reference a track (song) on a CD (in standard CDDA / RedBook format).
Unix.
Some desktop environments for Unix-like operating systems, such as GNOME or KDE provide freedesktop.org .desktop files. These can be used to point to local or remote files, folders, and applications. Symbolic links can also be created on Unix systems, which serve a similar function, although they are a feature of the file system.
List of X window managers that support .desktop shortcuts.
Following are some of the window managers which support the use of shortcut icons on the desktop:
Mac.
Macintosh does not have extensions for shortcuts. A file type called "alias" was introduced in Macintosh System 7; it tracks information like inode number to handle moves. Aliases in System 7 through Mac OS 9 were distinguished from other files by using names in italics. In Mac OS 8 and later, another distinguishing mark was added: an "alias arrow"a black arrow on a small white square similar to that used for shortcuts in Microsoft Windows. In Mac OS X, the names of aliases are no longer italicized, but the arrow badge remains. Additionally, an alias retains its dynamic reference to an object and does not have to be specified even when calling files on remote servers.
In addition, symbolic links can be created within the Unix subsystem. The Safari browser has its own property list-based format, , for storing Internet URLs.
History.
To execute an application or render a file in early graphical user interfaces, the user had to click on the representation of the actual file or executable in the location where the application or file was. The concept of disassociating the executable from the icon representing an instruction to perform a task associated with that file or executable so that they may be grouped by function or task rather than physical organisation in the file structure was first described in the research paper "A Task Oriented Front End For The Windows Graphical User Interface", published in 1991 by Kingston University and presented to both Microsoft and Xerox EuroPARC that same year under an academia/business technology sharing agreement. A simplified form of this research was incorporated into System 7 in 1991, and four years later into Windows 95.


Go!Cam

The PSP Camera is a digital camera peripheral by Sony Computer Entertainment for the PlayStation Portable handheld video game system. In Japan, the PSP-300 was released as the Chotto Shot (ちょっとショット, "Quick Shot") on November 2, 2006, and was released in Singapore in the same year. For PAL regions, it is named the Go!Cam and was released May 25, 2007. A lower resolution version, the PSP-450x, was introduced in 2009. The PSP-450x camera was released in North America bundled with "Invizimals" on October 12, 2010, and was also bundled with "EyePet" on November 2, 2010.
The camera mounts on top of the PSP via the Mini USB connection slot and a screw. It can take still photographs and record video with audio. The microphone can also be used with the Talkman program and others.
PSP-300 E.
The PSP-300 E is a silver 1.3 megapixel camera, similar to cameras found in cellular phones. It can record video at up to 480x272 at 30 frames/s and take photographs at up to 1280x960. It requires Official Firmware 2.82 or later.
PSP-450x.
On October 12, 2010, when "Invizimals" was released, it came bundled with a new, redesigned PSP camera, model PSP-450x, which is a 0.3-megapixel camera taking photographs at a maximum resolution of 640x480 and video at up to 480x272 at 30 frames/s. The PSP-450x requires Official Firmware 6.00 or later.
Editing software.
The Chotto Shot camera comes with a UMD used to edit photos and video clips, though the UMD is in Japanese, so non-Japanese users who imported it might have difficulty using the software.
The Go!Cam camera does not come with a UMD but instead has an available download for it called Go!Edit. Go!Edit is a program that enables extended usage of the Go!Cam and includes features that enable pictures and videos to be edited. Go!Edit requires PSP system firmware of 3.40 or above to be used. Aside from English, the Go!Edit program is also available in Danish, Dutch, Spanish, Italian, French, Suomi (Finnish), Norwegian, Portuguese, and Swedish, and all the languages are packaged with the program itself.
The PSP camera can use firmware version 3.00 or higher to take photographs or videos with English on-screen instructions. Users can do so by selecting "CAMERA" under the "PHOTO" menu. Once taken, the photo or video will then be saved to the user's Memory Stick. Saved videos can be uploaded to the Internet from any wireless connection.
Video recording length.
Go!Edit videos can only be taken for a length of 15 seconds and then edited; however, accessing the camera through the XMB menu means the video recording length depends on the size of the Memory Stick. Video quality can be changed, so the lower the quality, the longer the recording time and vice versa.
Using the best quality setting (480x272 and Fine quality), one-and-a-half hours of video can be recorded on a 4 GB Memory Stick Duo.


Nokia N85

The Nokia N85 is a high-end smartphone produced by Nokia, announced on 27 August 2008 as part of the Nseries line. The N85 runs on Symbian OS v9.3 with S60 3rd Edition platform with Feature Pack 2. It was released in October, retailing for 450 euros before taxes.
The major feature N85 introduced was an AMOLED display, giving brighter and sharper colours. The N85 has a dual-slider like the Nokia N95 to access either media playback buttons or a numeric keypad, and is about 25% slimmer in size. The upper sliding keys illuminate between four multimedia keys in music or video playback, and two gaming keys during the playing of N-Gage 2.0 games. It also has a Navi wheel like the Nokia N81 which it replaced and bases its design from, as well as a GPS receiver, 5-megapixel camera with dual LED flash, and an FM transmitter.
The N85 was well received as a decent upgrade to the N95, as well as better than the actual flagship, Nokia N96, which costed 100 euros more with few additions and was somewhat critically negative. Compared to the N96, the N85 is thinner and lighter, has a camera lens cover, has a larger battery capacity, USB charging (via the microUSB port), and an AMOLED screen; although without large internal memory or a DVB-H receiver.
Specifications.
Dimensions.
Two-way slider with spring assistance mechanism
Digital TV.
With optional DVB-H Nokia Mobile TV Receiver SU-33W it is possible to watch television on the screen of the phone.


FASTOPEN.COM


Micro Machines V3

Micro Machines V3 (Micro Machines 64 Turbo for the Nintendo 64 port) is a racing video game developed by Codemasters and Novalicious for PlayStation, Microsoft Windows, Nintendo 64, and Game Boy Color.
Development and release.
A Sega Saturn version of the game was demonstrated at the 1996 Electronic Entertainment Expo, at which time Codemasters stated that they were hoping to release the PlayStation and Saturn versions simultaneously. However, in mid-1997 they announced that development on the Saturn version had been halted.
Initially "Micro Machines V3" was published only in Europe, but in late 1997 Midway Games acquired the U.S. distribution rights and announced a November 1997 U.S. release for the PlayStation version.
An N64 port of "Micro Machines V3" was released in 1999 entitled "Micro Machines 64 Turbo". This port lets 8 people play simultaneously while using a Pad Share, where one person uses one side of the controller, steering with the Directional pad, while the other player uses the four C-buttons on the N64. The vehicles accelerate automatically in these modes. A Micro Machines vehicle was packaged with each copy.
Reception.
On the review aggregation website GameRankings, the PlayStation version held a score of 78% based on 13 reviews, "Micro Machines 64 Turbo" held a score of 73% based on 8 reviews, and the Game Boy Color version held an 85% based on 4 reviews. "Next Generation" said that the PlayStation version "may not be the next "Formula 1", but it is brilliant in its own right. One of the few truly great multiplayer PlayStation games".


Series 90 (software platform)

The Series 90 (formerly "Hildon") is a platform for mobile phones that use Symbian OS. It was developed by Nokia in collaboration with Psion. It was released in 2003 and was going to be the platform for the Nokia 7700 which was cancelled, but did eventually make it to market with the Nokia 7710.
Nokia discontinued Series 90 as a platform, but merged its technology into S60. Although only one production Series 90 device was made, a form of the GUI continued on as Nokia's Hildon user interface in the Maemo shipped with Nokia Internet Tablets.
Compatibility.
Series 90 is completely incompatible with Series 60 (S60) and UIQ, the most popular platforms for Symbian smartphones. However, some applications from Nokia Series 80 Communicator devices – such as the Nokia 9300 – will function under Series 90.
History.
Essentially, Series 90 is a development of the Psion Eikon GUI as used on the Series 5, Series 5mx, Revo, netPad, Series 7 and netBook machines. It has been modified to be controlled entirely through the touchscreen, supplemented by the 77x0's seven hardware buttons and rocker-dial. The Nokia 7700, which was never released, had only an on-screen keyboard for text input; the 7710 added basic handwriting recognition. Applications now have only a single menu tree, accessible from the title bar at the top of the screen; there is no Exit or Quit option in most apps; and a button bar has been added to the right hand side of the screen, resembling that of the Nokia Communicator smartphones.


List of VIA C3 microprocessors

The C3 microprocessor from VIA Technologies is a fifth-generation CPU targeted at the desktop and mobile markets.


USER.DAT


ICL Transaction Machine Environment


VDSO

vDSO (virtual dynamic shared object) is a kernel mechanism for exporting a carefully selected set of kernel space routines to user space applications so that applications can call these kernel space routines in-process, without incurring the performance penalty of a mode switch from user mode to kernel mode that is inherent when calling these same kernel space routines by means of the system call interface.
Virtual dynamic shared object.
vDSO uses standard mechanisms for linking and loading i.e. standard Executable and Linkable Format (ELF) format. vDSO is a memory area allocated in user space which exposes some kernel functionalities. vDSO is dynamically allocated, offers improved safety through address space layout randomization, and supports more than 4 system calls. Some C standard libraries, like glibc, may provide vDSO links so that if the kernel does not have vDSO support, a traditional syscall is made. vDSO helps to reduce the calling overhead on simple kernel routines, and it also can work as a way to select the best system-call method on some computer architectures such as IA-32. An advantage over other methods is that such exported routines can provide proper DWARF (Debug With Attributed Record Format) debugging information. Implementation generally implies hooks in the dynamic linker to find the vDSOs.
Vsyscall.
vDSO was developed to offer the vsyscall features while overcoming its limitations: a small amount of statically allocated memory, which allows only 4 system calls, and the same addresses application binary interface (ABI) in each process, which compromises security. This security issue has been mitigated by emulating a virtual system call, but the emulation introduces additional latency.


High-level language computer architecture

A high-level language computer architecture (HLLCA) is a computer architecture designed to be targeted by a specific high-level language, rather than the architecture being dictated by hardware considerations. It is accordingly also termed language-directed computer design, coined in and primarily used in the 1960s and 1970s. HLLCAs were popular in the 1960s and 1970s, but largely disappeared in the 1980s. This followed the dramatic failure of the Intel 432 (1981) and the emergence of optimizing compilers and reduced instruction set computing (RISC) architecture and RISC-like CISC architectures, and the later development of just-in-time compilation for HLLs. A detailed survey and critique can be found in .
HLLCAs date almost to the beginning of HLLs, in the Burroughs large systems (1961), which were designed for ALGOL 60 (1960), one of the first HLLs. The most well-known HLLCAs are the Lisp machines of the 1970s and 1980s (for Lisp, 1959). At present the most popular HLLCAs are Java processors, for Java (1995), and these are a qualified success, being used for certain applications. A recent architecture in this vein is the Heterogeneous System Architecture (2012), which HSA Intermediate Layer (HSAIL) provides instruction set support for HLL features such as exceptions and virtual functions; this uses JIT to ensure performance.
Definition.
There are a wide variety of systems under this heading. The most extreme example is a Directly Executed Language, where the instruction set architecture of the computer equals the instructions of the HLL, and the source code is directly executable with minimal processing. In extreme cases the only compilation required is tokenizing the source code and feeding the tokens directly to the processor; this is found in stack-oriented programming languages running on a stack machine. For more conventional languages the HLL statements are grouped into instruction + arguments, and infix order is transformed to prefix or postfix order. DELs are typically only hypothetical, though they were advocated in the 1970s.
In less extreme examples the source code is first parsed to bytecode, which is then the machine code that is passed to the processor. In these cases the system typically lacks an assembler, as the compiler is deemed sufficient, though in some cases (such as Java) assemblers are used to produce legal bytecode which would not be output by the compiler. This approach was found in the Pascal MicroEngine (1979), and is currently used by Java processors.
More loosely, a HLLCA may simply be a general-purpose computer architecture with some features specifically to support a given HLL or several HLLs. This was found in Lisp machines from the 1970s onward, which augmented general-purpose processors with operations specifically designed to support Lisp.
Examples.
The Burroughs Large Systems (1961) were the first HLLCA, designed to support ALGOL (1959), one of the earliest HLLs. This was referred to at the time as "language-directed design." The Burroughs Medium Systems (1966) were designed to support COBOL for business applications. The Burroughs Small Systems (mid-1970s, designed from late 1960s) were designed to support multiple HLLs by a writable control store. These were all mainframes.
The Wang 2200 (1973) series were designed with a BASIC interpreter in micro-code.
The Pascal MicroEngine (1979) was designed for the UCSD Pascal form of Pascal, and used p-code (Pascal compiler bytecode) as its machine code. This was influential on the later development of Java and Java machines.
Lisp machines (1970s and 1980s) were a well-known and influential group of HLLCAs.
Intel iAPX 432 (1981) was designed to support Ada. This was Intel's first 32-bit processor design, and was intended to be Intel's main processor family for the 1980s, but failed commercially.
Rekursiv (mid-1980s) was a minor system, designed to support object-oriented programming and the Lingo programming language in hardware, and supported recursion at the instruction set level, hence the name.
A number of processors and coprocessors intended to implement Prolog more directly were designed in the late 1980s and early 1990s, including the Berkeley VLSI-PLM, its successor (the PLUM), and a related microcode implementation. There were also a number of simulated designs that were not produced as hardware , . Like Lisp, Prolog's basic model of computation is radically different from standard imperative designs, and computer scientists and electrical engineers were eager to escape the bottlenecks caused by emulating their underlying models.
Niklaus Wirth's Lilith project included a custom CPU geared toward the Modula-2 language.
The INMOS Transputer was designed to support concurrent programming, using occam.
The AT&T Hobbit processor, stemming from a design called CRISP (C-language Reduced Instruction Set Processor), was optimized to run C code.
In the late 1990s, there were plans by Sun Microsystems and other companies to build CPUs that directly (or closely) implemented the stack-based Java virtual machine. As a result, several Java processors have been built and used.
Ericsson developed ECOMP, a processor designed to run Erlang. It was never commercially produced.
The HSA Intermediate Layer (HSAIL) of the Heterogeneous System Architecture (2012) provides a virtual instruction set to abstract away from the underlying ISAs, and has support for HLL features such as exceptions and virtual functions, and include debugging support.
Implementation.
HLLCA are frequently implemented via a stack machine (as in the Burroughs Large Systems and Intel 432), and implemented the HLL via microcode in the processor (as in Burroughs Small Systems and Pascal MicroEngine). Tagged architectures are frequently used to support types (as in the Burroughs Large Systems and Lisp machines). More radical examples use a non-von Neumann architecture, though these are typically only hypothetical proposals, not actual implementations.
Application.
Some HLLCs have been particularly popular as developer machines (workstations), due to fast compiles and low-level control of the system with a high-level language. Pascal MicroEngine and Lisp machines are good examples of this.
HLLCAs have often been advocated when a HLL has a radically different model of computation than imperative programming (which is a relatively good match for typical processors), notably for functional programming (Lisp) and logic programming (Prolog).
Motivation.
A detailed list of putative advantages is given in .
HLLCAs are intuitively appealing, as the computer can in principle be customized for a language, allowing optimal support for the language, and simplifying compiler writing. It can further natively support multiple languages by simply changing the microcode. Key advantages are to developers: fast compilation and detailed symbolic debugging from the machine.
A further advantage is that a language implementation can be updated by updating the microcode (firmware), without requiring recompilation of an entire system. This is analogous to updating an interpreter for an interpreted language.
An advantage that's reappearing post-2000 is safety or security. Mainstream IT has largely moved to languages with type and/or memory safety for most applications. The software those depend on, from OS to virtual machines, leverage native code with no protection. Many vulnerabilities have been found in such code. One solution is to use a processor custom built to execute a safe high level language or at least understand types. Protections at the processor word level make attackers' job difficult compared to low level machines that see no distinction between scalar data, arrays, pointers, or code. Academics are also developing languages with similar properties that might integrate with high level processors in the future. An example of both of these trends is the SAFE project. Compare language-based systems, where the software (especially operating system) is based around a safe, high-level language, though the hardware need not be: the "trusted base" may still be in a lower level language.
Disadvantages.
A detailed critique is given in .
The simplest reason for the lack of success of HLLCAs is that from 1980 optimizing compilers resulted in much faster code and were easier to develop than implementing a language in microcode. Many compiler optimizations require complex analysis and rearrangement of the code, so the machine code is very different from the original source code. These optimizations are either impossible or impractical to implement in microcode, due to the complexity and the overhead. Analogous performance problems have a long history with interpreted languages (dating to Lisp (1958)), only being resolved adequately for practical use by just-in-time compilation, pioneered in Self and commercialized in the HotSpot Java virtual machine (1999).
The fundamental problem is that HLLCAs only simplify the code generation step of compilers, which is typically a relatively small part of compilation, and a questionable use of computing power (transistors and microcode). At the minimum tokenization is required, and typically syntactic analysis and basic semantic checks (unbound variables) will still be performed – so there is no benefit to the front end – and optimization requires ahead-of-time analysis – so there is no benefit to the middle end.
A deeper problem, still an active area of development , is that providing HLL debugging information from machine code is quite difficult, basically because of the overhead of debugging information, and more subtly because compilation (particularly optimization) makes determining the original source for a machine instruction quite involved. Thus the debugging information provided as an essential part of HLLCAs either severely limits implementation or adds significant overhead in ordinary use.
Further, HLLCAs are typically optimized for a single language, supporting other languages more poorly. Similar issues arise in multi-language virtual machines, notably the Java virtual machine (designed for Java) and the .NET Common Language Runtime (designed for C#), where other languages are second-class citizens, and often must hew closely to the main language in semantics. For this reason lower-level ISAs allow multiple languages to be well-supported, given compiler support. However, a similar issue arises even for many apparently language-neutral processors, which are well-supported by C, and where transpiling to C (rather than directly targeting the hardware) yields efficient programs and simple compilers.
The advantages of HLLCAs can be alternatively achieved in HLL Computer "Systems" (language-based systems) in alternative ways, primarily via compilers or interpreters: the system is still written in a HLL, but there is a trusted base in software running on an lower-level architecture. This has been the approach followed since circa 1980: for example, a Java system where the runtime environment itself is written in C, but the operating system and applications written in Java.
Alternatives.
Since the 1980s the focus of research and implementation in general-purpose computer architectures has primarily been in RISC-like architectures, typically internally register-rich load/store architectures, with rather stable, non-language-specific ISAs, featuring multiple registers, pipelining, and more recently multicore systems, rather than language-specific ISAs. Language support has focused on compilers and their runtimes, and interpreters and their virtual machines (particularly JIT'ing ones), with little direct hardware support. For example, the current Objective-C runtime for iOS implements tagged pointers, which it uses for type-checking and garbage collection, despite the hardware not being a tagged architecture.
In computer architecture, the RISC approach has proven very popular and successful instead, and is opposite from HLLCAs, emphasizing a very simple instruction set architecture. However, the speed advantages of RISC computers in the 1980s was primarily due to early adoption of on-chip cache and room for large registers, rather than intrinsic advantages of RISC .


Software Guard Extensions

Intel Software Guard Extensions (SGX) is a set of security-related instruction codes that are built into some modern Intel central processing units (CPUs). They allow user-level as well as operating system code to define private regions of memory, called "enclaves", whose contents are protected and unable to be either read or saved by any process outside the enclave itself, including processes running at higher privilege levels.
SGX involves encryption by the CPU of a portion of memory. The enclave is decrypted on the fly only within the CPU itself, and even then, only for code and data running from within the enclave itself. The processor thus protects the code from being "spied on" or examined by other code. The code and data in the enclave utilize a threat model in which the enclave is trusted but no process outside it can be trusted (including the operating system itself and any hypervisor), and therefore all of these are treated as potentially hostile. The enclave contents are unable to be read by any code outside the enclave, other than in its encrypted form. Applications running inside of SGX must be written to be side channel resistant as SGX does not protect against side channel measurement or observation.
SGX is designed to be useful for implementing secure remote computation, secure web browsing, and digital rights management (DRM). Other applications include concealment of proprietary algorithms and of encryption keys.
As of Intel's 11th-generation Tiger Lake and Rocket Lake CPUs, Intel CPUs no longer include SGX.
Details.
SGX was first introduced in 2015 with the sixth generation Intel Core microprocessors based on the Skylake microarchitecture.
Support for SGX in the CPU is indicated in CPUID "Structured Extended feature Leaf", EBX bit 02, but its availability to applications requires BIOS/UEFI support and opt-in enabling which is not reflected in CPUID bits. This complicates the feature detection logic for applications.
Emulation of SGX was added to an experimental version of the QEMU system emulator in 2014. In 2015, researchers at the Georgia Institute of Technology released an open-source simulator named "OpenSGX".
One example of SGX used in security was a demo application from wolfSSL using it for cryptography algorithms.
Intel Goldmont Plus (Gemini Lake) microarchitecture also contains support for Intel SGX.
Attacks.
Prime+Probe attack.
On 27 March 2017 researchers at Austria's Graz University of Technology developed a proof-of-concept that can grab RSA keys from SGX enclaves running on the same system within five minutes by using certain CPU instructions in lieu of a fine-grained timer to exploit cache DRAM side-channels. One countermeasure for this type of attack was presented and published by Daniel Gruss et al. at the USENIX Security Symposium in 2017. Among other published countermeasures, one countermeasure to this type of attack was published on September 28, 2017, a compiler-based tool, DR.SGX, that claims to have superior performance with the elimination of the implementation complexity of other proposed solutions.
M.M.MM
Spectre-like attack.
The LSDS group at Imperial College London showed a proof of concept that the Spectre speculative execution security vulnerability can be adapted to attack the secure enclave. The Foreshadow attack, disclosed in August 2018, combines speculative execution and buffer overflow to bypass the SGX.
Enclave attack.
On 8 February 2019, researchers at Austria's Graz University of Technology published findings, which showed that in some cases it is possible to run malicious code from within the enclave itself. The exploit involves scanning through process memory, in order to reconstruct a payload, which can then run code on the system. The paper claims that due to the confidential and protected nature of the enclave, it is impossible for Antivirus software to detect and remove malware residing within it. However, since modern anti-malware and antivirus solutions monitor system calls, and the interaction of the application with the operating system, it should be possible to identify malicious enclaves by their behavior, and this issue is unlikely to be a concern for state-of-the-art antiviruses. Intel issued a statement, stating that this attack was outside the threat model of SGX, that they cannot guarantee that code run by the user comes from trusted sources, and urged consumers to only run trusted code.
MicroScope replay attack.
There is a proliferation of Side-channel attack plaguing modern computer architecture. Many of these attacks measure slight, nondeterministic variations in the execution of some code, so the attacker needs many, possibly tens of thousands, of measurements to learn secrets. However, the Microscope attack allows a malicious OS to replay code an arbitrary number of times regardless of the programs actual structure, enabling dozens of side-channel attacks.
Plundervolt.
Security researchers were able to inject timing specific faults into execution within the enclave,
resulting in leakage of information. The attack "can" be executed remotely, but requires
access to the privileged control of the processor's voltage and frequency.
LVI.
Load Value Injection injects data into a program aiming to replace the value loaded from memory which is then used for a short time before the mistake is spotted and rolled back, during which LVI controls data and control flow.
SGAxe.
SGAxe, a SGX vulnerability, extends a speculative execution attack on cache, leaking content of the enclave. This allows an attacker to access private CPU keys used for remote attestation. In other words, a threat actor can bypass Intel's countermeasures to breach SGX's enclaves confidentiality. The SGAxe attack is carried out by extracting attestation keys from SGX's private quoting enclave, that are signed by Intel. The attacker can then masquerade as legitimate Intel machines by signing arbitrary SGX attestation quotes.


Input Field Separators

For many command line interpreters (“shell”) of Unix operating systems, the input field separators variable (abbreviated IFS, and often referred to as internal field separators) refers to a variable which defines the character or characters used to separate a pattern into tokens for some operations.
The value of , which typically includes the space, tab, and the newline by default, can be printed with the command or in Bash.
From the Bash man page:
The shell treats each character of as a delimiter, and splits the results of the other expansions into words on these characters.
If is unset, or its value is exactly , the default, then sequences of , , and at the beginning and end of the results of the previous expansions are ignored, and any sequence of characters not at the beginning or end serves to delimit words.
If has a value other than the default, then sequences of the whitespace characters and are ignored at the beginning and end of the word, as long as the whitespace character is in the value of (an whitespace character).
Any character in that is not whitespace, along with any adjacent whitespace characters, delimits a field. A sequence of whitespace characters is also treated as a delimiter. If the value of is null, no word splitting occurs.
IFS abbreviation.
According to the Open Group Base Specifications, IFS is an abbreviation for "input field separators". A newer version of this specification mentions that "this name is misleading as the IFS characters are actually used as field terminators."
However, IFS is often referred to as "internal field separators" on the internet.
Exploits.
IFS was usable as an exploit in some versions of Unix. A program with root permissions could be fooled into executing user-supplied code if it ran (for instance) codice_1 and was called with set to , in which case it would run the program "" (in the current directory and thus writable by the user) with root permissions. This has been fixed by making the shells not inherit the IFS variable.


Radeon HD 2000 series

The graphics processing unit (GPU) codenamed Radeon R600 is the foundation of the Radeon HD 2000 series and the FireGL 2007 series video cards developed by ATI Technologies. The HD 2000 cards competed with nVidia's GeForce 8 series.
Architecture.
This article is about all products under the brand "Radeon HD 2000 Series". They all contain a GPU which implements TeraScale 1, ATI's first Unified shader model microarchitecture for PCs.
Video acceleration.
The Unified Video Decoder (UVD) SIP core is on-die in the HD 2400 and the HD 2600. The HD 2900 GPU dies do not have a UVD core, as its stream processors were powerful enough to handle most of the steps of video acceleration in its stead except for entropy decoding and bitstream processing which are left for the CPU to perform.
Other features.
HDTV encoding support is implemented via the integrated AMD Xilleon encoder; the companion "Rage Theater" chip used on the Radeon X1000 series was replaced with the digital "Theater 200" chip, providing VIVO capabilities.
For display outputs, all variants include two dual-link TMDS transmitters, except for HD 2400 and HD 3400, which include one single and one dual-link TMDS transmitters. Each DVI output includes dual-link HDCP encoder with on-chip decipher key. HDMI was introduced, supporting display resolutions up to 1,920×1,080, with integrated HD audio controller with 5.1-channel LPCM and AC3 encoding support. Audio is transmitted via DVI port, with specially designed DVI-to-HDMI dongle for HDMI output that carries both audio and video.
All variants support CrossFireX technology. CrossFire efficiency was improved and shows performance approaching the theoretical maximum of twice the performance of a single card.
Desktop products.
The R600 family is called the "Radeon HD 2000" series, with the enthusiast segment being the "Radeon HD 2900 series" which originally comprised the Radeon HD 2900 XT with GDDR3 memory released on May 14, and the higher-clocked GDDR4 version in early July.
The mainstream and budget segment products were the Radeon HD 2600 and Radeon HD 2400 series respectively, both launched June 28, 2007.
Previously there were no HD 2000 series products being offered in the performance segment while ATI used models from the previous generation to address that target market; this situation did not change until the release of variants of the Radeon HD 2900 series, the Radeon HD 2900 Pro and GT, which filled the gap of the performance market for a short period of time.
Radeon HD 2400.
The Radeon HD 2400 series was based on the codenamed RV610 GPU. It had 180 million transistors on a 65 nm fabrication process. The Radeon HD 2400 series used a 64-bit-wide memory bus. The die size is 85 mm2. The official PCB design implements only a passive-cooling heatsink instead of a fan, and official claims of power consumption are as little as 35 W. The core has 16 kiB unified vertex/texture cache away from dedicated vertex cache and L1/L2 texture cache used in higher end model.
Reports has that the first batch of the RV610 core (silicon revision A12), only being released to system builders, has a bug that hindered the UVD from working properly, but other parts of the die operated normally. Those products were officially supported with the release of Catalyst 7.10 driver, which the cards were named as Radeon HD 2350 series.
Several reports from owners of HD 2400 Pro suggest the card do not fully support hardware decoding for all H.264/VC-1 videos. The device driver, even with the latest stable version, seem to only honor hardware decoding for formats specified in the Blu-ray and HD-DVD specification. As a result of such restriction, the card is not deemed very useful for hardware video decoding since the majority of the H.264/VC-1 videos on the net are not encoded in those formats (even though the hardware itself is fully capable of doing such decoding work). This device driver restriction has led to the development of a third party driver patch, "ExDeus ATI HD Registry Tweak", to unlock the potential of HD 2400 Pro for full support of H.264/VC-1 hardware video decoding.
Radeon HD 2600.
The Radeon HD 2600 series was based on the codenamed RV630 GPU and packed 390 million transistors on a 65 nm fabrication process. The Radeon HD 2600-series video cards included GDDR3 support, a 128-bit memory ring bus and 4-phase digital PWM, spanning a die size of 153 mm2. Neither of the GDDR3 reference PCI-E designs required additional power connectors whereas the HD 2600 Pro and XT AGP variants required additional power through either 4-pin or 6-pin power connectors, Official claims state that the Radeon HD 2600 series consumes as little as 45 W of power.
Radeon HD 2600 X2.
The Radeon HD 2600 X2 is a dual-GPU product which includes 2 RV630 dies on a single PCB with a PCI-E bridge splitting the PCI-E ×16 bandwidth into two groups of PCI-E ×8 lanes (each 2.0 Gbit/s). The card provides 4 DVI outputs or HDMI outputs via dongle and supports CrossFire configurations. AMD calls this product the "Radeon HD 2600 X2" as seen by some vendors and as observed inside the INF file of Catalyst 7.9 version 8.411. Sapphire and other vendors including PowerColor and GeCube have either announced or demonstrated their respective dual GPU (connected by crossfire) products. Catalyst 7.9 added support for this hardware in September 2007. However, AMD did not provide much publicity to promote it. A vendor may offer cards containing 256 MiB, 512 MiB, or 1 GiB of video memory. Although the memory technology utilized is at a vendor's discretion, most vendors have opted for GDDR3 and DDR2 due to lower manufacturing cost and positioning of this product for the mainstream rather than performance market segment and also a big success.
Radeon HD 2900.
The Radeon HD 2900 series was based on the codenamed R600 GPU and was launched on May 14, 2007. R600 packed 700 million transistors on an 80 nm fabrication process and had a 420 mm2 die size. The Radeon HD 2900 XT was launched with 320 Stream Processors and a core clock of 743 MHz. The initial model was released with 512 MB of GDDR3 clocked at 828 MHz (1,656 MHz effective) with a 512-bit interface. A couple months after release ATI released the 1 GB GDDR4 model with a memory frequency of 1,000 MHz (2,000 MHz effective). Performance was on par compared to the 512 MB card. The HD 2900 XT introduced a lot of firsts. It was the first to implement a digital PWM on board (7-phase PWM), first to use an 8-pin PEG connector, and was the first graphics card from ATI to support DirectX 10.
The Radeon HD 2900 Pro was clocked lower at 600 MHz core and 800 MHz memory (1,600 MHz effective), configured with 512 MB of GDDR3 or 1 GB of GDDR4. It was rumored that some of the 1 GB GDDR4 models were manufactured using a 12" cooler borrowed from the prototype HD 2900 XTX. The HD 2900 Pro had both 256-bit and 512-bit interface options for the 512 MB versions of the card. A few AIB partners offered a black and silver cooler exclusive to the 256-bit model of the Pro.
The Radeon HD 2900 GT was a 240 Stream Processor variant clocked the same as the HD 2900 Pro, but with 256 MB of video memory on a 256-bit interface.
Mobile products.
All Mobility Radeon HD 2000 series share the same feature set support as their desktop counterparts, as well as the addition of the battery-conserving PowerPlay 7.0 features, which are augmented from the previous generation's PowerPlay 6.0.
The Mobility Radeon HD 2300 is a budget product which includes UVD in silica but lacks unified shader architecture and DirectX 10.0/SM 4.0 support, limiting support to DirectX 9.0c/SM 3.0 using the more traditional architecture of the previous generation. A high-end variant, the Mobility Radeon HD 2700, with higher core and memory frequencies than the Mobility Radeon HD 2600, was released in mid-December 2007.
The Mobility Radeon HD 2400 is offered in two model variants; the standard HD 2400 and the HD 2400 XT.
The Mobility Radeon HD 2600 is also available in the same two flavors; the plain HD 2600 and, at the top of the mobility lineup, the HD 2600 XT.
The half-generation update treatment had also applied to mobile products. Announced prior to CES 2008 was the Mobility Radeon HD 3000 series. Released in the first quarter of 2008, the Mobility Radeon HD 3000 series consisted of two families, the Mobility Radeon HD 3400 series and the Mobility Radeon HD 3600 series. The Mobility Radeon HD 3600 series also featured the industry's first implementation of on-board 128-bit GDDR4 memory.
About the time of late March to early April, 2008, AMD renewed the device ID list on its website with the inclusion of Mobility Radeon HD 3850 X2 and Mobility Radeon HD 3870 X2 and their respective device IDs. Later in Spring IDF 2008 held in Shanghai, a development board of the Mobility Radeon HD 3870 X2 was demonstrated alongside a Centrino 2 platform demonstration system. The Mobility Radeon HD 3870 X2 was based on two M88 GPUs with the addition of a PCI Express switch chip on a single PCB. The development board used for demonstration was a PCI Express 2.0 ×16 card, while the final product is expected to be on AXIOM/MXM modules.
Graphics device drivers.
AMD's proprietary graphics device driver "Catalyst".
AMD Catalyst is being developed for Microsoft Windows and Linux. As of July 2014, other operating system are not officially supported. This may be different for the AMD FirePro brand, which is based on identical hardware but features OpenGL-certified graphics device drivers.
AMD Catalyst supports of course all features advertised for the Radeon brand.
Microsoft Windows.
The Purple Pill tool issue, which could allow unsigned drivers to be loaded into Windows Vista and tamper with the operating system kernel, was resolved in the Catalyst 7.8 release (version 8.401). The AVIVO video converter for Windows Vista, and color temperature control in Catalyst Control Center was added with the release of Catalyst 7.9, package version 8.411. Software CrossFire was enabled for HD 2600 and HD 2400 series video cards with the release of Catalyst 7.10 (package version 8.421)
The Catalyst 8.1, package version 8.451, supports for MultiView technology for accelerated OpenGL rendering on multiple video card setup (CrossFire). The driver also allows CrossFire configurations for Radeon HD 3850 and HD 3870 video cards.
The Catalyst 8.3 is described by AMD as a milestone release, supporting DirectX 10.1, ATI CrossFire X technology and allowing the mixing of different Radeon HD 3800 series video cards to form a CrossFire X setup with 2 to 4 GPUs. Catalyst 8.3 introduced to new video controls to further enhance the video playback quality, these controls includes edge enhancement and noise reduction settings. There is also the support for extended desktop in CrossFire X mode. The anti-aliasing support for Unreal Engine 3.0 in DirectX 9.0 games, support for CFAA filters (wide tent and box tent) to be enabled when Super AA is enabled, and other features as developer support for hardware surface tessellation, hardware accelerated wide aspect ratio LCD scaling, HydraVision support for Windows Vista allowing to add maximum 9 virtual desktops and new Folding@home client are also officially supported in this release.
The Catalyst 8.5, package version 8.493 brought new features include component video with 480i and 480p resolutions, SECAM TV output support, 1080p HDTV custom mode via HDMI, 1080p24 (1080p resolution at 24 Hz) support, HDMI Audio for non-standard TV modes (CEA 861b), support for adaptive anti-aliasing (and later, in Catalyst 8.6, also support for custom filters ) under OpenGL, Windows XP SP3 support and un-install utility enhancements. The driver also includes performance improvements and fixes some instability issues and rendering issues on some games.
The Radeon HD 2000 series has been transitioned to legacy support, where drivers will be updated only to fix bugs instead of being optimized for new applications.
Current Catalyst drivers do not support the AGP versions of Radeon HD 2000/3000 series cards with RIALTO bridge. Installing Catalyst drivers on those cards will yield the following error message: "setup did not find a driver compatible with your current hardware or operating system." or simply fail outright. The AGP cards in question are supported unofficially by ATI/AMD with a hot-fixed Catalyst driver-set each month since May 2008 with the Catalyst 8.5 hotfix. Their PCI vendor IDs are listed below:
Free and open-source graphics device driver "Radeon".
The free and open-source drivers are primarily developed on Linux and for Linux, but have been ported to other operating systems as well. Each driver is composed out of five parts:
The free and open-source "Radeon" graphics driver supports most of the features implemented into the Radeon line of GPUs.
Documentation release.
The free and open-source "Radeon" graphics device drivers are "not" reverse engineered, but based on documentation released by AMD.
Initial register documentation and parser code to execute the AtomBIOS ROM routines were released in September 2007. The R600 family Instruction Set Architecture guide was released on June 11, 2008. Sample code and register headers for the R600 and R700 3D engines were released in December 2008. AMD released the specifications for both the r6xx and r7xx families on January 26, 2009.


UltraSPARC IIe


Executive (operating system)


Nokia Xseries

The Nokia Xseries is a line of mobile phones from Nokia introduced in September 2009 as the successor of the XpressMusic series. It was targeted towards a young audience, and are more focused on music and entertainment with special dedicated keys, inbuilt storage and other facilities. The X2-02, released in January 2012, was the last handset of the series.
In May 2018, HMD Global launched the new Nokia X6 on the Chinese market but not officially classified it as new member of Xseries.


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