ND812

The 12-bit ND812, produced by Nuclear Data, Inc., was a commercial minicomputer developed for the scientific computing market.
Nuclear Data introduced it in 1970 at a price under $10,000 ().
Description.
The architecture has a simple programmed I/O bus, plus a DMA channel.
The programmed I/O bus typically runs low to medium-speed peripherals, such as printers,
teletypes, paper tape punches and readers, while DMA is used for cathode ray tube
screens with a light pen, analog-to-digital converters, digital-to-analog converters,
tape drives, disk drives.
The word size, 12 bits, is large enough to handle unsigned integers from 0 to 4095 –
wide enough for controlling simple machinery. This is also enough to handle signed numbers from -2048 to +2047.
This is higher precision than a slide rule or most analog computers. Twelve bits could also store two
six-bit characters (note, six-bit isn't enough for two cases, unlike "fuller" ASCII
character set). "ND Code" was one such 6-bit character encoding that included upper-case alphabetic, digit,
a subset of punctuation and a few control characters.
The ND812's basic configuration has a main memory of 4,096 twelve-bit words
with a 2 microsecond cycle time. Memory is expandable to 16K words in 4K word increments. Bits within the word
are numbered from most significant bit (bit 11) to
least significant bit (bit 0).
The programming model consists of four accumulator registers: two main accumulators, J and K,
and two sub accumulators, R and S. A rich set of arithmetic and logical operations are provided for the
main accumulators and instructions are provided to exchange data between the main and sub accumulators.
Conditional execution is provided through "skip" instructions. A condition is tested and the subsequent
instruction is either executed or skipped depending on the result of the test. The subsequent instruction
is usually a jump instruction when more than one instruction is needed for the case where the test fails.
Input/Output.
The I/O facilities include programmable interrupts with 4-levels of priority that can trap to any location in
the first 4K words of memory. I/O can transmit 12 or 24 bits, receive 12 or 24 bits, or transmit and receive
12 bits in a cycle. I/O instructions include 4 bits for creating pulses for peripheral control. I/O peripherals
can be attached via 76 signal connector that allows for direct memory access by peripherals.
DMA is accomplished by "cycle stealing" from the CPU to store words directly into
the core memory system.
Nuclear Data provided interfaces to the following peripherals:
Programming facilities.
The ND812 did not have an operating system, just a front panel and run and halt switches.
The I/O facility allowed for peripherals to directly load programs into memory while the computer
was halted and not executing instructions. Another option was to enter a short loader program
that would be used to bootstrap the desired program from a peripheral such as a teletype or
paper tape reader. Since core memory is non-volatile, shutting off the computer did not result
in data or program loss.
A number of system programs were made available by Nuclear Data for use with the ND812: BASC-12
assembler, symbolic text editor, NUTRAN interpreter, and disk-based symbolic text editor,
BASC-12 Assembler.
An assembler called BASC-12 was provided. BASC-12 was a two-pass assembler,
with an optional third pass. Pass one generates a symbol table, pass two produces a
binary output tape and pass three provides a listing of the program.
A sample of the assembler from the Principles of Programming the ND812 Computer manual
is shown below:
 /Input two unequal numbers "A" and "B", compare the two numbers
 /and determine which is larger, and output a literal statement
 /"A > B", or "B > A" as applicable.
 /Input and store values for A & B
 *200
 Start, TIF /Clear TTY flag
 JPS Input /Get value for A
 STJ A
 JPS Input /Get value for B
 STJ B
 /Determine which of the two values is larger
 LDJ A
 SBJ B /Subtract B from A
 SIP J /Test for A positive
 JMP BRAN /No! B > A
 LDJ ABCST /Yes! A > B
 SKIP /Skip next instruction
 BRAN, LDJ BACST
 /Set up and output expression
 JPS OUT
 STOP
 JMP START
 /Working or data storage area
 A, 0 /Constant A
 B, 0 /Constant B
 ABCST, AB /Address of A > B literal
 BACST, BA /Address of B > A literal
 C260, 260 /ASCII zone constant
 /Input routine + ASCII zone strip
 Input, 0 /Entry point
 TIS
 JMP .-1
 TRF
 TCP /Echo input at teletype
 TOS
 JMP .-1
 SBJ C260
 JMP@ INPUT
 /Output routine - Output ASCII expression
 Out, 0 /Entry point
 STJ LOOP+1
 LDJ C5 /Set number of character constant
 STJ CTR
 /Output data loop
 Loop, TWLDJ
 0
 TCP
 TOS
 JMP .-1
 ISZ LOOP+1
 DSZ CTR /Test for all characters out
 JMP LOOP /No
 JMP@ Out /Return
 C5, 5
 CTR, 0
 /Output messages
 AB, 215
 212
 301 /A
 276 />
 302 /B
 BA, 215
 212
 302 /B
 276 />
 301 /A
 $ /End character
NUTRAN.
NUTRAN, a conversational, FORTRAN-like language, was provided. NUTRAN was intended for
general scientific programming. A sample of NUTRAN is shown below:
 1 PRINT 'INPUT VALUES FOR X AND Y'
 2 INPUT X,Y
 3 Z=X+Y
 4 PRINT 'X+Y= ',Z
 5 STOP
An example of the conversational nature of NUTRAN is shown below. codice_1 is the command prompt
and codice_2 is the input prompt.
 >1.G
 INPUT VALUES FOR X AND Y
 :3
 :2
 X+Y= .5000000E 1
 >
Instruction Formats.
The instruction set consists of single and double word instructions.
Operands can be immediate, direct or indirect. Immediate operands are
encoded directly in the instruction as a literal value. Direct operands
are encoded as the address of the operand. Indirect operands encode the
address of the word containing a pointer to the operand.
Single Word Instructions.
The displacement and sign bit allow single word instructions to address locations between
-63 and +63 of the location of the instruction. Bit 4 of the instruction allows for a
choice between indirect and direct addressing. When the displacement is used as an
indirect address, the contents of the location which is +/-63 locations from the instruction
location is used as a pointer to the actual operand.
Many single word instructions do not reference memory and use bits 4 and 5 as part of the
specification of the operation.
Group 1 Format.
Group 1 instructions perform arithmetic, logical, exchange and shifting functions
on the accumulator registers. This includes hardware multiply and divide instructions.
Bit 4 is set if the K register is affected. Bit 5 is set if the J register is affected.
Both bits are set of both registers are affected.
Group 2 Format.
Group 2 format instructions test for internal conditions of the J and K
accumulator registers, manipulate the overflow and flag status bits and
provide complement, increment and negation operations on the J and K accumulator
registers. Bits 9, 10 and 11 select the condition to be tested.
Two Word Instructions.
Bit 9, Change Fields, inhibits the absolute address from referencing a different field than
the one containing the instruction. When bit 8 is 1, the upper accumulator K is used with
the instruction, otherwise the lower accumulator J is used. When bit 7 is 1, indirect
addressing is used, otherwise direct addressing is used.
Status Word Format.
The status register doest not exist as a distinct register. It is the contents
of several groups of indicators that are all stored in the J register when
desired. The JPS and Int bits hold the current field contents that would
be used during a JPS instruction or interrupt. The flag and overflow bits
can be set explicitly from the J register contents with the RFOV instruction,
but the other bits must be set by distinct instructions.
Subroutines.
The ND812 processor provides a simple stack for operands, but
doesn't use this mechanism for storing subroutine return addresses. Instead, the return
address is stored in the target of the codice_3 instruction and then the codice_4
register is updated to point to the location following the stored return address. To
return from the subroutine, an indirect jump through the initial location of the
subroutine restores the program counter to the instruction following the codice_3
instruction.