Alternate Instruction Set

The Alternate Instruction Set (AIS) is a second 32-bit instruction set architecture found in some x86 CPUs made by VIA Technologies. On these VIA C3 processors, the second hidden processor mode is accessed by executing the x86 instruction codice_1 (). If AIS mode has been enabled, the processor will perform a JMP EAX and begin executing AIS instructions at the address of the EAX register. Using AIS allows native access to the Centaur Technology-designed RISC core inside the processor.
Instruction format.
The manufacter describes the Alternate Instruction Set as "an extended set of integer, MMX, floating-point, and 3DNow! instructions along with additional registers and some more powerful instruction forms".
Every AIS instruction is prefixed with the 3-byte sequence codice_2 followed by the 32-bit instruction; this prefix form for the AIS instructions makes them appear to be x86 Load Effective Address (codice_3) instructions.
In 2018 researcher Christoper Domas reported that the prefix codice_4 (x86 codice_5) also worked.
A proposal made in 2002 to add AIS support to the Netwide Assembler (NASM) was partially declined in 2005, on the basis that NASM was an x86 assembler, and AIS is a separate instruction set. An assembler is available from Domas's 2018 research.
In 2007 a patent named some microcode instructions as codice_6 and codice_7 to/from main RAM, and codice_8 and codice_9 to/from private-RAM inside the processor.
The Centaur Technologies verification team, in a 2014 paper about the VIA Nano, included some short lists of micro-instructions including codice_10, codice_11, codice_12, codice_13, codice_14, codice_15, plus micro-operations codice_16 and codice_17. Micro-operations were shown to have a format that includes the fields codice_18, codice_19, codice_20, codice_21, codice_22, codice_23, codice_24, codice_25 and codice_26.
Availability.
From x86 mode, the availability of the Alternate Instruction Set can be detected by executing a CPUID with the EAX register set to codice_27 and then examining the EDX register. If EDX is set to 1, then AIS is supported. If EDX is also set to 1, then AIS is enabled. If AIS is supported by the CPU, then its status can be checked and altered through the Model-specific registers, by checking and setting the Feature Control Register (FCR, register 0x1107). If ("codice_1") is set to 1, then AIS is enabled.
The Microsoft Windows NT kernel codice_29 initialisation function proactively disables Alternate Instruction mode on boot up.
If the x86 codice_1 jump instruction is executed when AIS mode is disabled, then the processor will generate an Invalid Instruction exeception.
Setting the AIS-enabled bit requires privileged access, and should be set using a read-modify-write sequence.
Privilege elevation.
In 2018 Christopher Domas discovered that some Samuel 2 processors came with the Alternate Instruction Set enabled by default and that by executing AIS instructions from user space, it was possible to gain privilege escalation from Ring 3 to Ring 0. Domas had partially reverse engineered the AIS instruction set using automated fuzzing against a cluster of seven thin clients. Domas used the terms "deeply embedded core" (DEC) plus "deeply embedded instruction set" (DEIS) for the RISC instruction set, "launch instruction" for codice_1, "bridge instruction" for the x86 prefix wrapper, "global configuration register" for the Feature Control Register (FCR), and documented the privilege escalation with the name "Rosenbridge".