VIA PadLock

VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced Encryption Standard (AES), SHA-1, SHA256, and Montgomery modular multiplication.
Instructions.
The PadLock instruction set can be divided into four subsets:
The padlock capability is indicated via a codice_12 instruction with codice_13. If the resultant codice_14, the CPU is aware of Centaur features. An additional request with codice_15 then returns PadLock support in codice_16. The padlock capability can be toggled on or off with codice_17. 
VIA PadLock found on some Zhaoxin CPUs have SM3 hashing and SM4 block cipher added.