Intel Microcode

Intel microcode is microcode that runs inside x86 processors made by Intel. Since the P6 microarchitecture introduced in the mid-1990s, the microcode programs can be patched by the operating system or BIOS firmware to workaround bugs found in the CPU after release. Intel had originally designed microcode updates for processor debugging under its design for testing (DFT) initiative.
Following the Pentium FDIV bug the patchable microcode function took on a wider purpose to allow in-field updating without needing to do a product recall.
In the P6 and later microarchitectures, x86 instructions are internally converted into simpler RISC-style micro-operations that are specific to a particular processor and stepping level.
Micro-operations.
On the Intel 80486 and AMD Am486 there are approximately 250 lines of microcode, totalling 12,032 bits stored in the microcode ROM.
On the Pentium Pro, each micro-operation is 72-bits wide, or 118-bits wide. This includes an opcode, two source fields, and one destination field, with the ability to hold a 32-bit immediate value. The Pentium Pro is able to detect parity errors in its internal microcode and report these via the Machine Check Architecture.
Micro-operations have a consistent format with up to three source inputs, and two destination outputs. The processor performs register renaming to map these inputs to and from the real register file (RRF) before and after their execution. Out-of-order execution is used, so the micro-operations and instructions they represent may not appear in the same order.
During development of the Pentium Pro, several microcode fixes were included between the A2 and B0 steppings. For the Pentium II (based on the P6 Pentium Pro), additional micro-operations were added to support the MMX instruction set. In several cases, "microcode assists" were added to handle rare corner-cases in a reliable way.
The Pentium 4 can have 126 micro-operations in flight at the same time. Micro-operations are decoded and stored in an Execution Trace Cache with 12,000 entries, to avoid repeated decoding of the same x86 instructions. Groups of six micro-operations are packed into a trace line. Micro-operations can borrow extra immediate data space within the same cache-line. Complex instructions, such as exception handling, result in jumping to the microcode ROM. During development of the Pentium 4, microcode accounted for 14% of processor bugs versus 30% of processor bugs during development of the Pentium Pro.
The Intel Core microarchitecture introduced in 2006 added "micro-operations fusion" for some common pairs of instructions including comparison followed by a jump. The instruction decoders in the Core convert x86 instructions into microcode in three different ways:
For Intel's hyper-threading implementation of simultaneous multithreading, the microcode ROM, trace cache, and instruction decoders are shared, but the micro-operation queue is not shared.
Update facility.
In the mid-1990s, a facility for supplying new microcode was initially referred to as the Pentium Pro BIOS Update Feature. It was intended that user-mode applications should make a BIOS interrupt call to supply a new "BIOS Update Data Block", which the BIOS would partially validate and save to nonvolatile BIOS memory; this could be supplied to the installed processors on next boot.
Intel distributed a program called codice_1, renamed codice_2 that could be run under DOS. Collections of multiple microcode updates were concatencated together and numerically numbered with the extension codice_3, such as codice_4.
Processor interface.
The processor boots up using a set of microcode held inside the processor and stored in an internal ROM. A microcode update populates a separate SRAM and set of "match registers" that act as breakpoints within the microcode ROM, to allow jumping to the updated list of micro-operations in the SRAM. A match is performed between the Microcode Instruction Pointer (UIP) all of the match registers, with any match resulting in a jump to the corresponding destination microcode address. In the original P6 architecture there is space in the SRAM for 60 micro-operations, and multiple match/destination register pairs. It takes one processor instruction cycle to jump from ROM microcode to patched microcode held in SRAM. Match registers consist of a microcode match address, and a microcode destination address.
The processor must be in protection ring zero ("") in order to initiate a microcode update. Each CPU in a symmetric multiprocessing arrangement needs to be updated individually.
An update is initiated by placing its address in codice_5 register, setting codice_6, and executing a codice_7 (Write model-specific register).
Microcode update format.
Intel distributes microcode updates as a 2,048 (2 kilobyte) binary blob. The update contains information about which processors it is designed for, so that this can be checked against the result of the CPUID instruction. The structure is a 48-byte header, followed by 2,000 bytes intended to be read directly by the processor to be updated:
Each block is encoded differently, and the majority of the 2,000 bytes are not used as configuration program and SRAM micro-operation contents themselves are much smaller. Final determination and validation of whether an update can be applied to a processor is performed during decryption via the processor. Each microcode update is specific to a particular CPU revision, and is designed to be rejected by CPUs with a different stepping level. Microcode updates are encrypted to prevent tampering and to enable validation.
With the Pentium there are two layers of encryption and the precise details explicitly documented by Intel, instead being only known to fewer than ten employees.
Microcode updates for Intel Atom, Nehalem and Sandy Bridge additionally contain an extra 520-byte header containing a 2048-bit RSA modulus with an exponent of 17 decimal.
! Micro architecture !! Example processors !! Supplied length !! Functional length !! Suspected encoding