Zen 3

Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7nm process for the chiplets and GlobalFoundries's 14 nm process for the I/O die (as it did with the Ryzen 3000XT processors). Zen 3 powers Ryzen 5000 mainstream desktop processors (codenamed "Vermeer") and Epyc server processors (codenamed "Milan"). Zen 3 is supported on motherboards with 500 series chipsets; 400 series boards will also see support on select B450 / X470 motherboards with certain beta BIOSes. Zen 3 is expected to be the last microarchitecture before AMD switches to DDR5 memory and new sockets. According to AMD, Zen 3 has a 19% higher instructions per cycle (IPC) on average than Zen 2.
Features.
Zen 3 is a significant incremental improvement over its predecessors, with an IPC increase of 19%, and being capable of reaching higher clock speeds.
Like Zen 2, Zen 3 is composed of up to 2 core complex dies (CCD) along with a separate IO die containing the I/O components. A Zen 3 CCD is composed of a single core complex (CCX) containing 8 CPU cores and 32MB of shared L3 cache, this is in contrast to Zen 2 where each CCD is composed of 2 CCX, each containing 4 cores each as well as 16MB of L3 cache. The new configuration allows all 8 cores of the CCX to directly communicate with each other and the L3 Cache instead of having to use the IO die through the Infinity Fabric.
Zen 3 also features "Smart Access Memory" (SAM), a technology allowing Zen 3 processors to directly access all of a compatible graphic card's VRAM. According to AMD, this allows an increased FPS of up to 11% in certain games. SAM is an implementation of resizable BAR, an optional feature introduced in PCIe2.0 that, as of the launch of Zen 3, only AMD has explored. As of December 2020, Intel and Nvidia are reportedly working on implementing Resizable BAR in the near future.
In Zen 3, a single 32MB L3 cache pool is shared among all 8 cores in a chiplet, vs Zen 2's two 16MB pools each shared among 4 cores in a core complex, of which there were two per chiplet. This new arrangement improves the cache hit rate as well as performance in situations that require cache data to be exchanged among cores, but increases cache latency from 39 cycles in Zen 2 to 46 clock cycles and halves per-core cache bandwidth, although both problems are partially mitigated by higher clock speeds. Total cache bandwidth on all 8 cores combined remains the same due to power consumption concerns. L2 cache capacity and latency remain the same at 512KB and 12 cycles. All cache read and write operations are done at 32 bytes per cycle.
Improvements.
Zen 3 has made the following improvements over Zen 2:
Products.
On October 8, 2020, AMD announced four Zen 3-based desktop Ryzen processors, consisting of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and featuring between 6 and 16 cores.
Epyc microprocessors.
The Epyc server line of chips based on Zen 3 is to be named Milan and will be the final generation of chips using the SP3 socket. Epyc Milan is set to be revealed on March 15, 2021.