QCDPAX

The QCDPAX was a processor array designed and built jointly by the University of Tsukuba and Anritsu Corporation for the simulation of the lattice QCD.
PAX (Processor Array eXperiment) was the name of the series 
of the parallel computers since 1977 for the study of parallel high-speed computation 
in scientific and engineering applications.
The first and second machines were made at Kyoto University in 1978 and 1980 respectively, and the project was moved to the University of Tsukuba in 1981.
It utilized the MIMD processor array architecture with the two-dimensional
nearest-neighbor connection and the broadcasting bus.
QCDPAX was the fifth model in the PAX series. A prototype with four
processing units was constructed in the April 1988, and a practical
system with 288 processing units was built in the April 1989.
In the spring of 1990, it was increased with PU number to 480
and achieved a peak speed of 14GFLOPS.
Each processing unit was an independent one-board microcomputer. 
Motorola's microprocessor MC68020 (25 MHz) was used as the CPU.
The local memory was 4MBytes with 100ns 1Mbit DRAM.
The QCDPAX utilized LSI Logic's floating-point processing unit L64133 on
the market. L64133 had peak performance of the 33MFLOPS.
The floating-point processing unit controller, newly developed by the gate array, was also
utilized to derive the performance from the FPU by controlling the direct memory access
between the data memory and floating-point processing unit.
The QCDPAX was followed by the 2048 processor CP-PACS with a speed of 614.4 GFlops, which itself has been succeeded by a range of successively faster computers dedicated to computational physics. From the CP-PACS onwards all were located at and operated by the dedicated Center for Computational Physics of the University of Tsukuba.