PIC instruction listings

The PIC instruction set refers to the set of instructions that Microchip Technology PIC or dsPIC microcontroller supports. The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup.
PICmicro chips have a Harvard architecture, and instruction words are unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.
In the instruction set tables that follow, register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.
Architecture.
Memory operands are also referred to as "registers". Most are simply general-purpose storage (RAM), while some locations are reserved for "special function registers". Except for a single accumulator (called codice_1), almost all other registers are memory-mapped, even registers like the program counter and ALU status register. (The other exceptions, which are not memory-mapped, are the return address stack, and the tri-state registers used to configure the GPIO pins.)
The instruction set does not contain conditional branch instructions. Instead, it contains conditional skip instructions which cause the following instruction to be ignored. A conditional skip followed by an unconditional branch performs a conditional branch. The skip instructions test any bit of any register. The ALU status register is one possibility.
Memory operands are specified by absolute address; the location is fixed at compile time. To provide indirect addressing, a pair of special function registers are provided:
This mechanism also allows up to 256 bytes of memory to be addressed, even when the instruction set only allows 5- or 7-bit memory operands. Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them:
PIC processors with more than 256 words of program use paged memory. The internal program counter and return stack are as wide as necessary to address all memory, but only the low 8 bits are visible to software in the codice_5 ("PC low") register. There is an additional codice_6 ("PC latch high") register which is only modified by software. Any operation which does not specify the full destination address (such as a 9-bit codice_7 or an 8-bit write to the PC register) fills in the additional high bits from the corresponding part of PCLATH. (Some PIC18 processors extend this beyond 16 bits with a PCLATU register to supply bits 16–23.)
Baseline core devices (12 bit).
†: Extended instruction, only available on "enhanced baseline" PICs. Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.
ELAN Microelectronics clones (13 bit).
ELAN Microelectronics Corp. make a series of PICmicro-like microcontrollers with a 13-bit instruction word. The instructions are mostly compatible with the mid-range 14-bit instruction set, but limited to a 6-bit register address (16 special-purpose registers and 48 bytes of RAM) and a 10-bit (1024 word) program space.
The 10-bit program counter is accessible as R2. Reads access only the low bits, and writes clear the high bits. An exception is the TBL instruction, which modifies the low byte while preserving bits 8 and 9.
The 7 accumulator-immediate instructions are renumbered relative to the 14-bit PICmicro, to fit into 3 opcode bits rather than 4, but they are all there, as well as an additional software interrupt instruction.
There are a few additional miscellaneous instructions, and there are some changes to the terminology (the PICmicro OPTION register is called the CONTrol register; the PICmicro TRIS registers 1–3 are called I/O control registers 5–7), but the equivalents are obvious.
†: Instruction unique to EM78 instruction set with no PIC equivalent
Some models support multiple ROM or RAM banks, in a manner similar to other PIC microcontrollers.
There is also a 15-bit variant of the instruction set, which is almost identical except that the register numbers are enlarged to 8 bits and the call and jump addresses are enlarged to 12 bits. Other differences:
A second generation 15-bit instruction set includes several additional instructions:
†: Only on EM89F768N; operands and results in special registers
‡: Only on EM88F794N, MTF213 and MTF351
Mid-range core devices (14 bit).
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.
Enhanced mid-range core devices (14 bit).
Enhanced mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and C programming language optimizations. In particular. there are two codice_8 (codice_9 and codice_10), and two corresponding codice_2 register pairs (codice_12 and codice_13). Special instructions use codice_14 registers like address registers, with a variety of addressing modes.
Holtek clones (14 or 16 bit).
Holtek make numerous 8-bit microcontrollers with a 14-bit instruction word equivalent to the (non-enhanced) mid-range core. The instruction encodings all fit into 14 bits and provide 7-bit operand addresses, but models with 4K or 8K words of program ROM provide 15- or 16-bit wide ROM and extend the basic 11-bit destination address using bits 14–15 of the instruction as bits 11–12 of the address. Some models extend the 7-bit RAM addresses by using bit 14 of the instruction as bit 7 of the operand address.
The instruction format is identical to Microchip's, but the opcodes are assigned in a different order, and the manufacturer uses different instruction mnemonics. The accumulator is called ACC rather than W, and the destination is specified by a suffix to the instruction mnemonic rather than an operand.
In addition to the opcode assignment, there are semantic differences in a few instructions:
Several operations have been added to the 14-bit PICmicro repertoire:
Padauk microcontrollers (13, 14, 15 or 16 bit).
Padauk Technology make a series of PIC-like microcontrollers notable for their extremely low cost, beginning at in quantity, with many models costing less than .
Although clearly PIC-derived, there are some significant differences:
The 14-, 15- and 16-bit instruction sets primarily differ in having wider address fields, although some encoding changes are made to allow a few additional instructions (such as , which performs a compare and skip if "not" equal.)
PIC18 high end core devices (16 bit).
In 2000, Microchip introduced the PIC18 architecture. Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.
The PIC18 has a 12-bit RAM address space, divided into 16 pages of 256 bytes. The 8-bit codice_15 field determines the address in combination with the codice_16 bit and the 4-bit bank select register (codice_17). If codice_16=0, the codice_17 is ignored and the codice_15 field is sign-extended to the range 0x000–0x07F (global RAM) or 0xF80–0xFFF (special function registers). If codice_16=1, the codice_15 field is extended with the codice_17 to generate the 12-bit address.
The PIC18 extends the codice_2/codice_3 mechanism used in previous PICmicro processors for indirect addressing in two ways:
First, it provides "three" file select registers. The codice_14 registers are 12 bits long (each split into two 8-bit portions codice_27 through codice_28), and access to the corresponding codice_29 register (codice_9 through codice_31) acts as an alias for the addressed byte.
Second, there are addressing modes. For each of the three, there is not just one codice_29 register, but five, and the one used determines the addressing mode:
There are also instructions to directly load an FSR pair with a 12-bit address, and a codice_46 instruction that moves a byte between two 12-bit addresses.
PIC24 and dsPIC 16-bit microcontrollers.
In 2001, Microchip introduced the dsPIC series of chips, which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.
Instructions come in two main varieties. One is like the classic one-operand PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result. The W registers are memory-mapped, so the f operand may specify a W register.
The other form, new to the PIC24, specifies three W register operands, two of which allow a 3-bit addressing mode specification:
The register offset addressing mode is only available for the codice_48 instruction, where the Ww register may be used as a register offset for the source, destination, or both. All other instructions use this encoding for an unsigned 5-bit immediate source instead.
For the operands to codice_49 and codice_50 which access program memory, only the indirect modes are allowed, and refer to addresses in code memory.
A few instructions are 2 words long. The second word is a NOP, which includes up to 16 bits of additional immediate operand.