Transactional Synchronization Extensions

Transactional Synchronization Extensions (TSX), also called Transactional Synchronization Extensions New Instructions (TSX-NI), is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory support, speeding up execution of multi-threaded software through lock elision. According to different benchmarks, TSX/TSX-NI can provide around 40% faster applications execution in specific workloads, and 4–5 times more database transactions per second (TPS).
TSX/TSX-NI was documented by Intel in February 2012, and debuted in June 2013 on selected Intel microprocessors based on the Haswell microarchitecture. Haswell processors below 45xx as well as R-series and K-series (with unlocked multiplier) SKUs do not support TSX/TSX-NI. In August 2014, Intel announced a bug in the TSX/TSX-NI implementation on current steppings of Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a microcode update.
In 2016, a side-channel timing attack was found by abusing the way TSX/TSX-NI handles transactional faults (i.e. page faults) in order to break KASLR on all major operating systems.
Support for TSX/TSX-NI emulation is provided as part of the Intel Software Development Emulator. There is also experimental support for TSX/TSX-NI emulation in a QEMU fork.
Features.
TSX/TSX-NI provides two software interfaces for designating code regions for transactional execution. Hardware Lock Elision (HLE) is an instruction prefix-based interface designed to be backward compatible with processors without TSX/TSX-NI support. Restricted Transactional Memory (RTM) is a new instruction set interface that provides greater flexibility for programmers.
TSX/TSX-NI enables optimistic execution of transactional code regions. The hardware monitors multiple threads for conflicting memory accesses, while aborting and rolling back transactions that cannot be successfully completed. Mechanisms are provided for software to detect and handle failed transactions.
In other words, lock elision through transactional execution uses memory transactions as a fast path where possible, while the slow (fallback) path is still a normal lock.
Hardware Lock Elision.
Hardware Lock Elision (HLE) adds two new instruction prefixes, codice_1 and codice_2. These two prefixes reuse the opcodes of the existing codice_3 / codice_4 prefixes (codice_5 / codice_6). On processors that do not support HLE, codice_3 / codice_4 prefixes are ignored on instructions for which the codice_1 / codice_2 are valid, thus enabling backward compatibility.
The codice_1 prefix hint can only be used with the following instructions with an explicit codice_12 prefix: codice_13, codice_14, codice_15, codice_16, codice_17, codice_18, codice_19, codice_20, codice_21, codice_22, codice_23, codice_24, codice_25, codice_26, codice_27, codice_28, codice_29, and codice_30. The codice_30 instruction can be used without the codice_12 prefix as well.
The codice_2 prefix hint can be used both with the instructions listed above, and with the codice_34 and codice_35 instructions.
HLE allows optimistic execution of a critical section by skipping the write to a lock, so that the lock appears to be free to other threads. A failed transaction results in execution restarting from the codice_1-prefixed instruction, but treating the instruction as if the codice_1 prefix were not present.
Restricted Transactional Memory.
Restricted Transactional Memory (RTM) is an alternative implementation to HLE which gives the programmer the flexibility to specify a fallback code path that is executed when a transaction cannot be successfully executed. Unlike HLE, RTM is not backward compatible with processors that do not support it. For backward compatibility, programs are required to detect support for RTM in the CPU before using the new instructions.
RTM adds three new instructions: codice_38, codice_39 and codice_40. The codice_38 and codice_39 instructions mark the start and the end of a transactional code region; the codice_40 instruction explicitly aborts a transaction. Transaction failure redirects the processor to the fallback code path specified by the codice_38 instruction, with the abort status returned in the codice_45 register.
codice_46 instruction.
TSX/TSX-NI provides a new codice_46 instruction that returns whether the processor is executing a transactional region. This instruction is supported by the processor if it supports HLE or RTM or both.
TSX Suspend Load Address Tracking.
TSX/TSX-NI Suspend Load Address Tracking (TSXLDTRK) is an instruction set extension that allows to temporarily disable tracking loads from memory in a section of code within a transactional region. This feature extends HLE and RTM, and its support in the processor must be detected separately.
TSXLDTRK introduces two new instructions, codice_48 and codice_49, for suspending and resuming load address tracking, respectively. While the tracking is suspended, any loads from memory will not be added to the transaction read set. This means that, unless these memory locations were added to the transaction read or write sets outside the suspend region, writes at these locations by other threads will not cause transaction abort. Suspending load address tracking for a portion of code within a transactional region allows to reduce the amount of memory that needs to be tracked for read-write conflicts and therefore increase the probability of successful commit of the transaction.
Implementation.
Intel's TSX/TSX-NI specification describes how the transactional memory is exposed to programmers, but withholds details on the actual transactional memory implementation. Intel specifies in its developer's and optimization manuals that Haswell maintains both read-sets and write-sets at the granularity of a cache line, tracking addresses in the L1 data cache of the processor. Intel also states that data conflicts are detected through the cache coherence protocol.
Haswell's L1 data cache has an associativity of eight. This means that in this implementation, a transactional execution that writes to nine distinct locations mapping to the same cache set will abort. However, due to micro-architectural implementations, this does not mean that fewer accesses to the same set are guaranteed to never abort. Additionally, in CPU configurations with Hyper-Threading Technology, the L1 cache is shared between the two threads on the same core, so operations in a sibling logical processor of the same core can cause evictions.
Independent research points into Haswell’s transactional memory most likely being a deferred update system using the per-core caches for transactional data and register checkpoints. In other words, Haswell is more likely to use the cache-based transactional memory system, as it is a much less risky implementation choice. On the other hand, Intel's Skylake or later may combine this cache-based approach with "memory ordering buffer" (MOB) for the same purpose, possibly also providing multi-versioned transactional memory that is more amenable to speculative multithreading.
In August 2014, Intel announced that a bug exists in the TSX/TSX-NI implementation on Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a microcode update. The bug was fixed in F-0 steppings of the vPro-enabled Core M-5Y70 Broadwell CPU in November 2014.
The bug was found and then reported during a diploma thesis in the School of Electrical and Computer Engineering of the National Technical University of Athens.
According to Intel 64 and IA-32 Architectures Optimization Reference Manual from May 2020, Volume 1, Chapter 2.5 Intel Instruction Set Architecture And Features Removed, HLE has been removed from Intel products released in 2019 and later. RTM is not documented as removed. However, Intel 10th generation Comet Lake and Ice Lake CPUs, which were released in 2020, do not support TSX/TSX-NI, including both HLE and RTM.
In Intel Architecture Instruction Set Extensions Programming Reference revision 41 from October 2020, a new TSXLDTRK instruction set extension was documented and slated for inclusion in the upcoming Sapphire Rapids processors.