Single-chip Cloud Computer

The Single-Chip Cloud Computer (SCC) is a computer processor (CPU) created by Intel Corporation in 2009 that has 48 distinct physical cores that communicate through architecture similar to that of a cloud computer data center. Cores are a part of the processor that carry out instructions of code that allow the computer to run. The SCC was a product of a project started by Intel to research multi-core processors and parallel processing (doing multiple calculations at once). Additionally Intel wanted to experiment with incorporating the designs and architecture of huge cloud computer data centers (Cloud computing) into a single processing chip. They took the aspect of cloud computing in which there are many remote servers that communicate with each other and applied it to a microprocessor. It was a new concept that Intel wanted to experiment with. The name "Single-chip Cloud Computer" originated from this concept.
Uses.
The SCC is currently still being used for research purposes. It currently can run the GNU operating system on the chip, but cannot boot Windows. Some applications of the SCC are web servers, data informatics, bioinformatics, and financial analytics.
Technical details.
Intel developed this new chip architecture based on huge cloud data centers, the cores are separated across the chip but are able to directly communicate with each other. The chip contains 48 P54C Pentium cores connected with a 4×6 2D-mesh. This mesh is a group of 24 tiles set up in four rows and six columns. Each tile contained two cores and a 16 KB (8 per core) message passing buffer (MPB) shared by the two cores, essentially a router. This router allows each core to communicate with each other. Previously cores had to send information back to the main memory and there it would be re-routed to other cores. The SCC contains 1.3 billion 45 nanometers (nm) long transistors that can amplify signals or act as a switch and turn core pairs on and off. These transistors use anywhere from 25 to 125 watts of power depending on the processing demand. For comparison the Intel i7 processor uses 156 watts of power. Four DDR3 memory controllers are on each chip, connected to the 2D-mesh as well. These controllers are capable of addressing 64 GB of random-access memory. The DDR3 memory is used to help each tile communicate with the others, without them the chip would not be functional. These controllers also work with the transistors to control when certain tiles are turned on and off to save power when not in use. When proper coding is implemented all of these pieces are put together you get a functional processor that is fast, powerful, and energy efficient with a framework resembling a network of cloud computers.
Modes of operation.
The SCC comes with RCCE, a simple message passing interface provided by Intel that supports basic message buffering operations. The SCC has two modes that it can operate under, processor mode and mesh mode:
Processor mode.
In processor mode cores are on and executing code from the system memory and programmed I/O (inputs and outputs) through the system which is connected to the system board FPGA. Loading memory and configuring the processor for bootstrapping (sustaining after the initial load) is currently done by software running on the SCC's management console that's embedded in the chip.
Mesh mode.
Cores are turned off. Only the routers, transistors and RAM controllers are on and they are sending and receiving large packets of data. Additionally there is no memory map.
The future.
Intel plans to share this technology with other companies such as HP, Yahoo, and Microsoft to have multiple companies researching the SCC to more efficiently and quickly advance the technology. They hope to make the SCC scalable to 100+ cores. One way they hope to achieve this is by having each chip be able to communicate with another chip, and they could put two chips together to get double the cores. They hope to improve the parallel programming productivity and power management to take advantage of the chip's architecture and large number of cores. Additionally they plan to experiment more with this architecture and similar chip architectures to develop a many-core scalable processors that maximizes the processing power of the cores while being power efficient.