F16C

The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats.
History.
The CVT16 instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set.
CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007, which is supplemented by the XOP and FMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged.
In recent documents, the name F16C is formally used in both Intel and AMD x86-64 architecture specifications.
Technical information.
There are variants that convert four floating-point values in an XMM register or 8 floating-point values in a YMM register.
The instructions are abbreviations for "vector convert packed half to packed single" and vice versa:
The 8-bit immediate argument to codice_5 selects the rounding mode. Values 0–4 select nearest, down, up, truncate, and the mode set in codice_6.
Support for these instructions is indicated by bit 29 of ECX after CPUID with EAX=1.