Advanced Synchronization Facility

Advanced Synchronization Facility (ASF) is a proposed extension to the x86-64 instruction set architecture that adds hardware transactional memory support. It was introduced by AMD; the latest specification was dated March 2009. , it was still in the proposal stage. No released microprocessors implement the extension.
Features.
ASF provides the capability to start, end and abort transactional execution and to mark cache lines for protected memory access in transactional code regions. It contains four new instructions—codice_1, codice_2, codice_3 and codice_4—and turns the otherwise invalid codice_5-prefixed codice_6, codice_7 and codice_8 instructions into valid ones inside transactional code regions. Up to 256 levels of nested transactional code regions is supported.
The codice_1 and codice_2 instructions mark the start and end of a transactional code region. Inside transactional code regions, the codice_5-prefixed codice_12, codice_7 and codice_8 instructions can mark up to four cache lines for protected memory access. Accesses from other processor cores to the protected cache lines result in exceptions, which in turn cause transaction aborts. Stores to protected cache lines must be performed using the codice_15 instructions. Marked cache lines can be released from protection with the codice_4 instruction. Transaction aborts generated by hardware or explicitly requested through the codice_3 instruction rolls back modifications to the protected cache lines and restarts execution from the instruction following the top-level codice_1 instruction.