IBM System/360 architecture

The IBM System/360 architecture is the model independent architecture for the entire S/360 line of mainframe computers, including but not limited to the instruction set architecture. The elements of the architecture are documented in the "IBM System/360 Principles of Operation" and the "IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information" manuals.
Features.
The System/360 architecture provides the following features:
Memory.
Memory ("storage") in System/360 is addressed in terms of 8-bit bytes. Various instructions operate on larger units called "halfword" (2 bytes), "fullword" (4 bytes), "doubleword" (8 bytes), "quad word" (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as big-endian. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term "word" refers to a "fullword".
The original architecture of System/360 provided for up to 224 = 16,777,216 bytes of memory. The later Model 67 extended the architecture to allow up to 232 = 4,294,967,296 bytes of virtual memory.
Addressing.
System/360 uses truncated addressing similar to that of the UNIVAC III. That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15 general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.
Data formats.
The S/360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Character and integer instructions are mandatory, but decimal and floating point instructions are part of the Decimal arithmetic and Floating-point arithmetic features.
Instruction formats.
Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats:
Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0.
Program Status Word (PSW).
The Program Status Word (PSW) contains a variety of controls for the currently operating program. The 64-bit PSW describes (among other things) the address of the current instruction being executed, condition code and interrupt masks. 
Load Program Status Word (LPSW) is a privileged instruction that loads the Program Status Word (PSW), including the program mode, protection key, and the address of the next instruction to be executed. LPSW is most often used to "return" from an interruption by loading the "old" PSW which is associated with the interruption class. Other privileged instructions (e.g., SSM, STNSM, STOSM, SPKA, etcetera) are available for manipulating subsets of the PSW without causing an interruption or loading a PSW; and one non-privileged instruction (SPM) is available for manipulating the program mask.
Interruption system.
The architecture defines 5 classes of interruption. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous and asynchronous events. 
There are two storage fields assigned to each class of interruption on the S/360; an old PSW double-word and a new PSW double-word. The processor stores the PSW, with an interruption code inserted, into the old PSW location and then loads the PSW from the new PSW location. This generally replaces the instruction address, thereby effecting a branch, and (optionally) sets and/or resets other fields within the PSW, thereby effecting a mode change.
The S/360 architecture defines a priority to each interruption class, but it is only relevant when two interruptions occur simultaneously; an interruption routine can be interrupted by any other enabled interruption, including another occurrence of the initial interruption. For this reason, it is normal practice to specify all of the mask bits, with the exception of machine-check mask bit, as 0 for the "first-level" interruption handlers. "Second-level" interruption handlers are generally designed for stacked interruptions (multiple occurrences of interruptions of the same interruption class).
Input/Output interruption.
An I/O interruptionPoOps occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also for asynchronous events detected by the device, control unit or channel, e.g., completion of a mechanical movement. The system stores the device address into the interruption code and stores channel status into the CSW at location 64 ('40'X).
Program interruption.
A Program interruption occurs when an instruction encounters one of 15 exceptions; however, if the Program Mask bit corresponding to an exception is 0 then there is no interruption for that exception. 
On 360/65, 360/67 and 360/85 the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0.
The Interruption code may be any of
Supervisor Call interruption.
A Supervisor Call interruptionPoOps occurs as the result of a Supervisor Call instruction; the system stores bits 8-15 of the SVC instruction as the Interruption Code.
External interruption.
An ExternalPoOps interruption occurs as the result of certain asynchronous events. Bits 16-24 of the External Old PSW are set to 0 and one or more of bits 24-31 is set to 1
Machine Check interruption.
A Machine Check interruptionPoOps occurs to report unusual conditions associated with the channel or CPU that cannot be reported by another class of interruption. The most important class of conditions causing a Machine Check is a hardware error such as a parity error found in registers or storage, but some models may use it to report less serious conditions. Both the interruption code and the data stored in the scanout area at '80'x (128 decimal) are model dependent.
Input/Output.
This article describes I/O from the CPU perspective. It does not discuss the channel cable or connectors, but there is a summary elsewhere and details can be found in the IBM literature.
I/O is carried out by a conceptually separate processor called a channel. Channels have their own instruction set, and access memory independently of the program running on the CPU. On the smaller models (through 360/50) a single microcode engine runs both the CPU program and the channel program. On the larger models the channels are in separate cabinets and have their own interfaces to memory. A channel may contain multiple subchannels, each containing the status of an individual channel program. A subchannel associated with multiple devices that cannot concurrently have channel programs is referred to as shared; a subchannel representing a single device is referred to as unshared.
There are three types of channels on the S/360:
Conceptually peripheral equipment is attached to a S/360 through "control units", which in turn are attached through channels. However, the architecture does not require that control units be physically distinct, and in practice they are sometimes integrated with the devices that they control. Similarly, the architecture does not require the channels to be physically distinct from the processor, and the smaller S/360 models (through 360/50) have integrated channels that steal cycles from the processor.
Peripheral devices are addressed with 16-bit addresses., referred to as "cua" or "cuu"; this article will use the term "cuu". The high 8 bits identify a channel, numbered from 0 to 6, while the low 8 bits identify a device on that channel. A device may have multiple "cuu" addresses.
Control units are assigned an address "capture" range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, a channel might have three disk control units at 20-2F, 50-5F, and 80-8F. Not all of the captured addresses need to have an assigned physical device. Each control unit is also marked as High or Low priority on the channel.
Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain the selection process continues in reverse back towards the channel. If the selection returns to the channel then no control unit accepted the command and SIO returns Condition Code 3. Control units marked as High Priority check the outbound CUU to be within their range. If so, then the I/O was processed. If not, then the selection was passed to the next outbound CU. Control units marked as Low Priority check for inbound (returning) CUU to be within their range. If so, then the I/O is processed. If not, then the selection is passed to the next inbound CU (or the channel). The connection of three controls unit to a channel might be physically -A-B-C and, if all are marked as High then the priority would be ABC. If all are marked low then the priority would be CBA. If B was marked High and AC low then the order would be BCA. Extending this line of reasoning then the first of N controllers would be priority 1 (High) or 2N-1 (Low), the second priority 2 or 2N-2, the third priority 3 or 2N-3, etc. The last physically attached would always be priority N.
There are three storage fields reserved for I/O; a double word I/O old PSW, a doubleword I/O new PSW and a fullword "Channel Address Word" (CAW). Performing an I/O normally requires the following:
A channel program consists of a sequence of "Channel Control Words" (CCWs) chained together (see below.) Normally the channel fetches CCWs from consecutive doublewords, but a control unit can direct the channel to skip a CCW and a "Transfer In Channel" (TIC) CCW can direct the channel to start fetching CCWs from a new location.
There are several defined ways for a channel command to complete. Some of these allow the channel to continue fetching CCWs, while others terminate the channel program. In general, if the CCW does not have the chain-command bit set and is not a TIC, then the channel will terminate the I/O operation and cause an I/O interruption when the command completes. Certain status bits from the control unit suppress chaining.
The most common ways for a command to complete are for the count to be exhausted when chain-data is not set and for the control unit to signal that no more data transfers should be made. If Suppress-Length-Indication (SLI) is not set and one of those occurs without the other, chaining is not allowed. The most common situations that suppress chaining are unit-exception and unit-check. However, the combination of unit-check and status-modifier does not suppress chaining; rather, it causes the channel to do a command retry, reprocessing the same CCW.
In addition to the interruption signal sent to the CPU when an I/O operation is complete, a channel can also send a Program-Controlled interruption (PCI) to the CPU while the channel program is running, without terminating the operation, and a delayed device-end interruption after the I/O completion interruption.
Channel status.
These conditions are detected by the channel and indicated in the CSW.PoOps
Unit status.
These conditions are presented to the channel by the control unit or device.PoOps In some cases they are handled by the channel and in other cases they are indicated in the CSW. There is no distinction between conditions detected by the control unit and conditions detected by the device.
 Search Id Equal
 TIC *-8
 Read Data
Channel Address Word.
The fullword "Channel Address Word" (CAW) contains a 4-bit storage protection key and a 24-bit address of the channel program to be started.
Channel Command Word.
A "Channel Command Word" is a doubleword containing the following:
CCW Command codes.
The low order 2 or 4 bits determine the six types of operations that the channel performs;. The encoding is
The meaning of the high order six or four bits, the modifier bits, M in the table above, depends upon the type of I/O device attached, see e.g., DASD CKD CCWs. All eight bits are sent to and interpreted in the associated control unit (or its functional equivalent).
Control is used to cause a state change in a device or control unit, often associated with mechanical motion, e.g., rewind, seek.
Sense is used to read data describing the status of the device. The most important case is that when a command terminates with unit check, the specific cause can only be determined by doing a Sense and examining the data returned. A Sense command with the modifier bits all zero is always valid.
A noteworthy deviation from the architecture is that DASD use Sense command codes for Reserve and Release, instead of using Control.
CCW flags.
The flags in a CCW affect how it executes and terminates.
Channel Status Word.
The "Channel Status Word" (CSW) provides data associated with an I/O interruption.
Operator controls.
The architecture of System/360 specified the existence of several common functions, but did not specify their means of implementation. This allowed IBM to use different physical means, e.g., dial, keyboard, pushbutton, roller, image or text on a CRT, for selecting the functions and values on different processors. Any reference to "key" or "switch" should be read as applying to, e.g., a light-pen selection, an equivalent keyboard sequence.
Optional features.
Byte-aligned operands.
On some models the alignment requirements for some problem-state instructions were relaxed. There is no mechanism to turn off this feature, and programs depending on receiving a program check type 6 (alignment) on those instructions must be modified.
Decimal arithmetic.
The decimal arithmetic feature provides instructions that operate on packed decimal data. A packed decimal number has 1-31 decimal digits followed by a 4-bit sign. All of the decimal arithmetic instructions except PACK and UNPACK generate a Data exception if a digit is not in the range 0-9 or a sign is not in the range A-F.
Direct Control.
The "Direct Control"PoOps feature provides six external signal lines and an 8-bit data path to/from storage.
Floating-point arithmetic.
The floating-point arithmetic feature provides 4 64-bit floating point registers and instructions to operate on 32 and 64 bit hexadecimal floating point numbers. The 360/85 and 360/195 also support 128 bit extended precision floating point numbers.
Interval timer.
If the interval timer feature is installed, the processor decrements the word at location 80 ('50'X) at regular intervals; the architecture does not specify the interval but does require that value subtracted make it appear as though 1 were subtracted from bit 23 300 times per second. The smaller models decremented at the same frequency (50 Hz or 60 Hz) as the AC power supply, but larger models had a high resolution timer feature. The processor causes an External interruption when the timer goes to zero.
Multi-system operation.
"Multi-system operation"PoOps is a set of features to support multi-processor systems, e.g., Direct Control, direct address relocation (prefixing).
Storage protection.
If the storage protection feature is installed, then there is a 4-bit storage key associated with every 2,048-byte block of storage and that key is checked when storing into any address in that block by either a CPU or an I/O channel. A CPU or channel key of 0 disables the check; a nonzero CPU or channel key allows data to be stored only in a block with the matching key.
Storage Protection was used to prevent a defective application from writing over storage belonging to the operating system or another application. This permitted testing to be performed along with production. Because the key was only four bits in length, the maximum number of different applications that could be run simultaneously was 15.
An additional option available on some models was fetch protection. It allowed the operating system to specify that blocks were protected from fetching as well as from storing.
Deviations and extensions.
The System/360 Model 20 is radically different and should not be considered to be a S/360.
The System/360 Model 44 is missing certain instructions, but a feature allowed the missing instructions to be simulated in hidden memory thus allowing the use of standard S/360 operating systems and applications.
Some models have features that extended the architecture, e.g., emulation instructions, paging, and some models make minor deviations from the architecture. Examples include:
Some deviations served as prototypes for features of the S/370 architecture.