SuperH

SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. This was a novel approach; at the time, RISC processors always used an instruction size that was the same as the internal data width, typically 32-bits. Using smaller instructions had consequences, the register file was smaller and instructions were generally two-operand format. But for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency.
Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely separate instructions. This concept is now known as a compressed instruction set and is also used by other companies, the most notable example being ARM for its Thumb instruction set.
, many of the original patents for the SuperH architecture are expiring and the SH-2 CPU has been reimplemented as open source hardware under the name J2.
History.
SH-1 and SH-2.
The SuperH processor core family was first developed by Hitachi in the early 1990s. The design concept was for a single instruction set (ISA) that would be upward compatible across a series of CPU cores.
In the past, this sort of design problem would have been solved using microcode, with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, an instruction to perform a 32 x 32 -> 64-bit multiply, a "long multiply", might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models.
One of the key realizations during the development of the RISC concept was that the microcode had a finite decoding time, and as processors became faster, this represented an unacceptable performance overhead. To address this, Hitachi instead developed a single ISA for the entire line, with unsupported instructions causing traps on those implementations that didn't include hardware support. For instance, the initial models in the line, the SH-1 and SH-2, differed only in their support for 64-bit multiplication; the SH-2 supported , and , whereas the SH-1 would cause a trap if these were encountered.
The ISA uses 16-bit instructions for better code density than 32-bit instructions, which was a great benefit at the time, due to the high cost of main memory. The downsides to this approach were that there were fewer bits available to encode a register number or a constant value. In the SuperH ISA, there were only 16 registers, requiring four bits for the source and another four for the destination. The instruction itself was also four bits, leaving another four bits unaccounted. Some instructions used these last four bits for offsets in array accesses, while others combined the second register slot and last four bits to produce an 8-bit constant.
Two models were initially introduced. The SH-1 was the basic model, supporting a total of 56 instructions. The SH-2 added 64-bit multiplication and a few additional commands for branching and other duties, bringing the total to 62 supported instructions. The SH-1 and the SH-2 were used in the Sega Saturn, Sega 32X and Capcom CPS-3.
SH-3.
A few years later, the SH-3 core was added to the family; new features included another interrupt concept, a memory management unit (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68. The SH-3 was bi-endian, running in either big-endian or little-endian byte ordering.
The SH-3 core also added a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core unified the DSP and the RISC processor world. A derivative of the DSP was also used with the original SH-2 core.
Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.
SH-4.
In 1997, Hitachi and STMicroelectronics (STM) started collaborating on the design of the SH-4 for the Dreamcast. SH-4 featured superscalar (2-way) instruction execution and a vector floating-point unit (particularly suited to 3d graphics). SH-4 based standard chips were introduced around 1998.
Licensing.
In early 2001, Hitachi and STM formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi.
In 2003, Hitachi and Mitsubishi Electric formed a joint-venture called Renesas Technology, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores. Renesas Technology later became Renesas Electronics, following their merger with NEC Electronics.
The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; ARM processors have a 16-bit Thumb mode (ARM licensed several patents from SuperH for Thumb) and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.
The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for symmetric multiprocessing.
Continued availability.
Since 2010, the SuperH CPU cores, architecture and products are with Renesas Electronics and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms. The System-on-chip products based on SH-3, SH-4 and SH-4A microprocessors were subsequently replaced by newer generations based on licensed CPU cores from Arm Ltd., with the many of the existing models still marketed and sold until March 2025 through the Renesas Product Longevity Program.
As of 2021, the SH-2A based SH72xx microcontrollers continue to be marketed by Renesas with guaranteed availability until February 2029, along with newer products based on several other architectures including Arm, RX, and RH850.
J Core.
The last of the SH-2 patents expired in 2014. At LinuxCon Japan 2015, j-core developers presented a cleanroom reimplemention of the SH-2 ISA with extensions (known as the "J2 core" due to the unexpired trademarks). Subsequently, a design walkthrough was presented at ELC 2016.
The open source BSD licensed VHDL code for the J2 core has been proven on Xilinx FPGAs and on ASICs manufactured on TSMC's 180 nm process, and is capable of booting µClinux. J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, and a machine generated Instruction Decoder supporting the densely packed and complex (relative to other RISC machines) ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift (using the SH-3 and later instruction patterns), extended atomic operations (used for threading primitives) and locking/interfaces for symmetric multiprocessor support. Plans to implement the SH-2A (as "J2+") and SH-4 (as "J4") instruction sets as the relevant patents expire in 2016-2017.
Several features of SuperH have been cited as motivations for designing new cores based on this architecture:
Models.
The family of SuperH CPU cores includes:
SH-2.
The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.
The SH-2 has a cache on all ROM-less devices.
It provides 16 general purpose registers, a vector-base-register, global-base-register, and a procedure register.
Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.
SH-2A.
The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006.
New features on the SH-2A core include:
The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as CAN, Ethernet, USB and more as well as more application specific peripherals such as motor control timers, TFT controllers and peripherals dedicated to automotive powertrain applications.
SH-4.
The SH-4 is a 32-bit RISC CPU and was developed for primary use in multimedia applications, such as Sega's Dreamcast and NAOMI game systems. It includes a much more powerful floating-point unit and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.
SH-4 features include:
There is no FPU in the custom SH4 made for Casio, the SH7305.
SH-5.
The SH-5 is a 64-bit RISC CPU.
Almost no non-simulated SH-5 hardware was ever released, and unlike the still live SH-4, support for SH-5 was dropped from gcc and Linux.