Atmel AVR instruction set

The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage.
Processor registers.
There are 32 general-purpose 8-bit registers, R0–R31. All arithmetic and logic operations operate on those registers; only load and store instructions access RAM.
A limited number of instructions operate on 16-bit register pairs. The lower-numbered register of the pair holds the least significant bits and must be even-numbered. The last three register pairs are used as pointer registers for memory addressing. They are known as X (R27:R26), Y (R29:R28) and Z (R31:R30). Postincrement and predecrement addressing modes are supported on all three. Y and Z also support a six-bit positive displacement.
Instructions which allow an immediate value are limited to registers R16–R31 (8-bit operations) or to register pairs R25:R24–R31:R30 (16-bit operations ADIW and SBIW). Some variants of the MUL operation are limited to eight registers, R16 through R23.
Special purpose registers.
In addition to these 32 general-purpose registers, the CPU has a few special-purpose registers:
Status bits.
The status register bits are:
Addressing.
The following address spaces are available:
The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as "0x00 (0x20)" through "0x3F (0x5F)", where the first item is the I/O address and the second, in parentheses, the data address.
The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 KiB of addressable memory.
A typical ATmega memory map may look like:
where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at 0x0060.
Instruction timing.
Arithmetic operations work on registers R0–R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.
RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.
Instruction list.
Instructions are one 16-bit long word, save for those including a 16-bit or 22-bit address, which take two words.
There are two types of conditional branches: jumps to address and skips. Conditional branches (BRxx) can test an ALU flag and jump to specified address. Skips (SBxx) test an arbitrary bit in a register or I/O and skip the next instruction if the test was true.
In the following:
Instruction set inheritance.
Not all instructions are implemented in all Atmel AVR controllers. This is the case of the instructions performing multiplications, extended loads/jumps/calls, long jumps, and power control.
The optional instructions may be grouped into three categories:
While higher-end processors tend to have both more capable cores and more memory, the presence of one does not guarantee the presence of the other.
Core CPU instructions.
Beginning with the original "classic" core, enhancements are organized into the following levels, each of which includes all the preceding:
Less capable than the "classic" CPU cores are two subsets: the "AVR1" core, and the "AVR tiny". Confusingly, "ATtiny" branded processors have a variety of cores, including AVR1 (ATtiny11, ATtiny28), classic (ATtiny22, ATtiny26), classic+ (ATtiny24) and AVRtiny (ATtiny20, ATtiny40).
The AVR1 subset was not popular and no new models have been introduced since 2000. It omits all RAM except for the 32 registers mapped at address 0–31 and the I/O ports at addresses 32–95. The stack is replaced by a 3-level hardware stack, and the codice_7 and codice_8 instructions are deleted. All 16-bit operations are deleted, as are codice_9, codice_10, and all load and store addressing modes except indirect via Z.
A second, more successful attempt to subset the AVR instruction set is the "AVR tiny" core.
The most significant change is that the AVRtiny core omits registers R0–R15. The registers are also not memory-mapped, with I/O ports from 0–63 and general-purpose RAM beginning at address 64. The 16-bit arithmetic operations (codice_11, codice_12) are omitted, as are the load/store with displacement addressing modes (codice_13, codice_14), but the predecrement and postincrement addressing modes are retained. The codice_1 instruction is omitted; instead program ROM is mapped to the data address space and may be accessed with normal load instructions.
Finally, the AVRtiny core deletes the 2-word codice_16 and codice_17 instructions for direct RAM addressing, and instead uses the opcode space previously assigned to the load/store with displacement instructions for new 1-word codice_16 and codice_17 instructions which can access the first 128 locations of general-purpose RAM, addresses 0x40 to 0xBF. (The codice_20 and codice_21 instructions provide direct access to I/O space from 0 to 0x3F.)
Memory addressing instructions.
The smallest cores have ≤256 bytes of data address space (meaning ≤128 bytes of RAM after I/O ports and other reserved addresses are removed) and ≤8192 bytes (8 KiB) of program ROM. These have only an 8-bit stack pointer (in SPL), and only support the 12-bit relative jump/call instructions codice_22/codice_23. (Because the AVR program counter counts 16-bit words, not bytes, a 12-bit offset is sufficient to address 213 bytes of ROM.)
Additional memory addressing capabilities are present as required to access available resources:
Optional feature instructions.
Three instructions are present only on models which have the corresponding hardware facility
Architectures other than AVR1 are named according to avr-libc conventions.
Instruction encoding.
Bit assignments:
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/store with offset instructions are the most extreme example where a 6-bit offset is broken into three pieces.