/*
 * Copyright (c) 2016-2017, Texas Instruments Incorporated
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <inc/hw_types.h>
#include <driverlib/prcm.h>

/*
 * CMSIS IRQn_Type enum is broken relative to ARM GNU compiler.
 *
 * So redefine the IRQn_Type enum to a unsigned int to avoid
 * the ARM compiler from sign extending IRQn_Type values higher than 0x80
 * into negative IRQ values, which causes hard-to-debug Hard Faults.
 */
typedef u32_t IRQn_Type;

/* Need to keep the remaining from cmsis.h, as Zephyr expects these. */
enum {
	Reset_IRQn                    = -15,
	NonMaskableInt_IRQn           = -14,
	HardFault_IRQn                = -13,
#if defined(CONFIG_ARMV7_M)
	MemoryManagement_IRQn         = -12,
	BusFault_IRQn                 = -11,
	UsageFault_IRQn               = -10,
#endif /* CONFIG_ARMV7_M */
	SVCall_IRQn                   =  -5,
	DebugMonitor_IRQn             =  -4,
	PendSV_IRQn                   =  -2,
	SysTick_IRQn                  =  -1,
} CMSIS_IRQn_Type;

#define __CM4_REV        0
#define __MPU_PRESENT                  0 /* Zephyr has no MPU support */
#define __NVIC_PRIO_BITS               CONFIG_NUM_IRQ_PRIO_BITS
#define __Vendor_SysTickConfig         0 /* Default to standard SysTick */

/*
 * Copyright (c) 2016, Texas Instruments Incorporated
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <inc/hw_types.h>
#include <driverlib/prcm.h>

--- 
+++ 
@@ -1,7 +1,38 @@
 /*
- * Copyright (c) 2016, Texas Instruments Incorporated
+ * Copyright (c) 2016-2017, Texas Instruments Incorporated
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
 #include <inc/hw_types.h>
 #include <driverlib/prcm.h>
+
+/*
+ * CMSIS IRQn_Type enum is broken relative to ARM GNU compiler.
+ *
+ * So redefine the IRQn_Type enum to a unsigned int to avoid
+ * the ARM compiler from sign extending IRQn_Type values higher than 0x80
+ * into negative IRQ values, which causes hard-to-debug Hard Faults.
+ */
+typedef u32_t IRQn_Type;
+
+/* Need to keep the remaining from cmsis.h, as Zephyr expects these. */
+enum {
+	Reset_IRQn                    = -15,
+	NonMaskableInt_IRQn           = -14,
+	HardFault_IRQn                = -13,
+#if defined(CONFIG_ARMV7_M)
+	MemoryManagement_IRQn         = -12,
+	BusFault_IRQn                 = -11,
+	UsageFault_IRQn               = -10,
+#endif /* CONFIG_ARMV7_M */
+	SVCall_IRQn                   =  -5,
+	DebugMonitor_IRQn             =  -4,
+	PendSV_IRQn                   =  -2,
+	SysTick_IRQn                  =  -1,
+} CMSIS_IRQn_Type;
+
+#define __CM4_REV        0
+#define __MPU_PRESENT                  0 /* Zephyr has no MPU support */
+#define __NVIC_PRIO_BITS               CONFIG_NUM_IRQ_PRIO_BITS
+#define __Vendor_SysTickConfig         0 /* Default to standard SysTick */
cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int

Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with
the NWP interrupt number of 171 caused a hard fault during a
subsequent svc #0 instruction during _Swap().

GNU compiler is generating a bit extension instruction (sxtb) which
converts a positive IRQ value argument to a negative value when
casting to the CMSIS IRQn_Type enum parameter type.

This generates a negative index, which then writes to an SCB
control register instead of NVIC register, causing a hard
fault later on.

This issue only occurs when passing interrupt numbers > 0x80
(eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis.

The solution here is simply to redefine IRQn_Type to be an
unsigned 32 bit integer, while redefining the CMSIS IRQn_Type
enum definitions for interrupts less than zero.

Jira: ZEP-1958

Signed-off-by: Gil Pitney <477da50908f0a7963c2c490cce0ff096d2cac162@linaro.org>
