text:
Patent US20010010092 - Semiconductor integrated circuit with a reduced skew and layout method in ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the...http://www.google.com/patents/US20010010092?utm_source=gb-gplus-sharePatent US20010010092 - Semiconductor integrated circuit with a reduced skew and layout method in design for semiconductor integrated circuitAdvanced Patent SearchPublication numberUS20010010092 A1Publication typeApplicationApplication numberUS 09/764,295Publication dateJul 26, 2001Filing dateJan 19, 2001Priority dateJan 20, 2000Also published asDE10102141A1, DE10102141C2, US6543042Publication number09764295, 764295, US 2001/0010092 A1, US 2001/010092 A1, US 20010010092 A1, US 20010010092A1, US 2001010092 A1, US 2001010092A1, US-A1-20010010092, US-A1-2001010092, US2001/0010092A1, US2001/010092A1, US20010010092 A1, US20010010092A1, US2001010092 A1, US2001010092A1InventorsAkitoshi KatoOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (15), Classifications (10), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuit with a reduced skew and layout method in design for semiconductor integrated circuitUS 20010010092 A1Abstract The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. Images(12) Claims(33)
What is claimed is: 1. A layout method in design for a semiconductor integrated circuit having clock tree paths, said method comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 2. The method as claimed in claim 1 , wherein the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. 3. The method as claimed in claim 1 , wherein a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. 4. The method as claimed in claim 3 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 5. The method as claimed in claim 4 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 6. The method as claimed in claim 1 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 7. A layout method in design for a semiconductor integrated circuit having clock tree paths, said method comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than: the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 8. The method as claimed in claim 7 , wherein the delay circuits are extracted from a delay circuit library. 9. The method as claimed in claim 7 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 10. The method as claimed in claim 9 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 11. The method as claimed in claim 10 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 12. The method as claimed in claim 1 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 13. A computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths, said computer program comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 14. The computer program as claimed in claim 13 , wherein the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. 15. The computer program as claimed in claim 13 , wherein a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. 16. The computer program as claimed in claim 15 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 17. The computer program as claimed in claim 16 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 18. The computer program as claimed in claim 13 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 19. A computer program for layout processes in design for a semiconductor integrated circuit having clock free paths, said computer program comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 20. The computer program as claimed in claim 19 , wherein the delay circuits are extracted from a delay circuit library. 21. The computer program as claimed in claim 19 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 22. The computer program as claimed in claim 21 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 23. The computer program as claimed in claim 22 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 24. The computer program as claimed in claim 19 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 25. A semiconductor integrated circuit having a common clock input terminal, plural Slip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having a delay which compensates a difference between the average delay value and the maximum value. 26. The semiconductor integrated circuit as claimed in claim 25 , wherein the second type flip-flop circuit comprises a flip-flop circuit configuration only, and the second type flip-flop circuit comprises both the flip-flop circuit configuration and a delay circuit configuration provided on a previous stage of the flip-flop circuit configuration. 27. The semiconductor integrated circuit as claimed in claim 25 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 28. The semiconductor integrated circuit as claimed in claim 27 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 29. The semiconductor integrated circuit as claimed in claim 28 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 30. A semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a first range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having delay values in a second range between the average delay value and a minimum value of the individual delay values of all of the clock tree paths, and wherein delay circuits having a delay which compensates a difference between the average delay value and the maximum value are provided on previous stages of the second type flip-flop circuits. 31. The semiconductor integrated circuit as claimed in claim 30 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 32. The semiconductor integrated circuit as claimed in claim 31 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 33. The semiconductor integrated circuit as claimed in claim 32 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. Description
BACKGROUND OF THE INVENTION [0001] The present invention relates to a semiconductor integrated circuit with a reduced clock skew and a layout method in design of a semiconductor integrated circuit with a reduced clock skew. [0002] In recent years, semiconductor integrated circuits have been on the improvements in high density integration, large scale integration and high speed performances. It is necessary that the high density integration of the semiconductor integrated circuits is realized, whist a clock skew which may cause a hold defective is reduced to improve the reliability of the semiconductor integrated circuit. [0003] As the high density integration has been progressed with change of the design rules from 0.25 micrometers-rule through 0.18 micrometers-rule to 0.13 micrometers-rule, a difference between a maximum value and a minimum value of an interconnection delay becomes remarkable, whereby a phase difference of the clock signals, for example, a clock skew is increased. If the phase difference of the clock signals or the clock skew becomes larger than a holding value of a flip-flop circuit, then a holding defective appears on the flip-flop circuits. [0004]FIG. 1 is a circuit diagram illustrative of first and second flip-flop circuits provided in a semiconductor integrated circuit to explain a holding defective of the flip-flop circuits. If a clock signal delay �N� becomes lower than a sum of a delay value �L�, a first internal delay value of a first flip-flop circuit F/F1, a delay value �M�, and a second internal delay value of a second flip-flop circuit F/F2, then the holding defective appears. [0005] The clock skew value as the difference in delay of the clock signals is presumable but only after the layout and placement have been completed. For this reason, it is possible that after an automatic layout has been completed, the clock skew value is increased to cause the holding defective on the flip-flop circuit, whereby a malfunction of the flip-flop circuit may appear. [0006] The following has been proposed to have solved the above problem. On the basis of delay informations after the automatic layout has been completed, then change of the circuit configuration, re-study and re-execution of the automatic layout are repeated until the clock skew is reduced. [0007]FIG. 2 is a flow chart illustrative of a first conventional circuit design method. [0008] In a step S81, the process is started. [0009] In a step S82, a circuit design is carried out to form a net-list. [0010] In a step S83, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0011] In a step S84, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0012] In a step S85, a circuit design operation is confirmed and further a timing and the clock skew value are also confirmed. [0013] In a step S86, it is verified whether or not any delay adjustment is needed. If the delay adjustment is needed, then the process will back to the step S82 for changing the circuit design or the step S83 for changing the cell layout. Those automatic layout processes will be repeated until the delay adjustment is not needed. If the delay adjustment is not needed, then the process is ended in a step S87. [0014] In Japanese laid-open patent publication No. 10-327047, a second conventional technique is disclosed. A data input terminal or a data output terminal of a flip-flop circuit is coupled with a logic cell having a flip-flop circuit and being free of any delay circuit. Subsequently, a logic simulation is executed on the basis of the layout information. A timing information as the result of the logic simulation is investigated with reference to a design specification of the semiconductor integrated circuit to verify a possibility of malfunction due to the timing variation. The logic cell is replaced by another logic cell which has a delay circuit, so that the logic cell with the delay circuit is connected to the data input or output terminal of the flip-flop circuit. [0015] It is considered that the clock signal is supplied from the common clock input terminal to the plural flip-flop circuits. A clock tree system causes that the number of the buffer circuits between the individual flip-flop circuits and the common clock input terminal becomes the same, whereby the clock skew value is reduced. [0016] In this case, however, it is necessary, to compensate the delay amount. A second conventional technique has been proposed. FIG. 3 is a flow chart illustrative of a second conventional circuit design method. [0017] In a step S91, the process is started. [0018] In a step S92, a circuit design is executed to form a let-list. [0019] In a step S93, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0020] In a step S94, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0021] In a step S95, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted. [0022] In a step S96, on the basis of the delay value of all paths of the clock-tree, a difference between the delay value of all paths of the clock-tree and a maximum value is calculated. [0023] In a step S97, a delay circuit, which compensates to the calculated difference between the delay value of all paths of the clock-tree and the maximum value, is selected from a delay circuit library and the delay circuit is inserted into a logic cell to form a delay circuit cell. [0024] In a step S98, a layout of tie delay circuit cell is executed to form real interconnection data. [0025] In a step S99, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S100. [0026] The above first and second conventional circuit layout methods prepare individual logic cell libraries for individual paths to verify the individual delays, whereby a design turnaround time is long. [0027] In case of the above clock tree shown in FIG. 3, the individual delay circuits, which compensate the difference between the delay value of all circuits of the clock tree and the maximum value, is inserted into the logic cell connected to the data input or output terminal of the flip-flop circuit. There are a large number of inserting positions into which the delay circuits are inserted. In case, a layout correction is difficult. As another method, it is possible to increase the length of the interconnections so that the fast path is adjusted to a delay path. This method is, however, unavailable to the high density interconnection region. [0028] In the above circumstances, it had been required to develop a novel layout method in design of a semiconductor integrated circuit free from the above problem. SUMMARY OF THE INVENTION [0029] Accordingly, it is an object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit free from the above problems. [0030] It is a further object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit. [0031] It is a still further object of the present invention to provide a novel method in design of a semiconductor integrated circuit to reduce a clock skew to a half of a maximum clock skew value for increasing a design efficiency and shortening a turnaround time. [0032] It is yet a further object of the present invention to provide a novel semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit. [0033] The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0034] The present invention also provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0035] The above and other objects, features and advantages of the present invention will be apparent from the following descriptions. BRIEF DESCRIPTION OF THE DRAWINGS [0036] Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings [0037]FIG. 1 is a circuit diagram illustrative of first and second flip-flop circuits provided in a semiconductor integrated circuit to explain a holding defective of the flip-flop circuits. [0038]FIG. 2 is a flow chart illustrative of a first conventional circuit design method. [0039]FIG. 3 is a flow chart illustrative of a second conventional circuit design method. [0040]FIG. 4 is a flow hart illustrative of a first novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a first embodiment in accordance with the present invention. [0041]FIG. 5 is a diagram illustrative of a distribution of a delay value of clock tree paths to extracted flip-flop circuits in a first embodiment in a Accordance with the present invention. [0042]FIG. 6 is a block diagram illustrative of an extracted clock tree in a first novel design method in a first embodiment in accordance with the present invention. [0043]FIG. 7 is a block diagram illustrative of a substituted clock tree in a first novel design method in a first embodiment in accordance with the present invention. [0044]FIG. 8 is a circuit diagram illustrative of a substituted delay flip-flop circuit in FIG. 7. [0045]FIG. 9 is a diagram illustrative of a distribution of a delay value of clock tree paths to the substituted delay flip-flop circuits in a first embodiment in accordance with the present invention. [0046]FIG. 10 is a flow hart illustrative of a second novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a second embodiment in accordance with the present invention. [0047]FIG. 11 is a block diagram illustrative of a batch-processed clock tree in a second novel design method in a second embodiment in accordance with the present invention. [0048]FIG. 12 is a circuit diagram illustrative of a delay circuit in FIG. 11. DISCLOSURE OF THE INVENTION [0049] The first present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0050] It is preferable that the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. [0051] It is preferable that a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. [0052] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0053] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0054] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. [0055] The second present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0056] It is preferable that the delay circuits are extracted from a delay circuit library. [0057] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0058] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0059] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0060] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted, flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. [0061] The third present invention provides a computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths. The computer program comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0062] It is preferable that the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. [0063] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. [0064] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0065] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0066] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. [0067] The fourth present invention provides a computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths. The computer program comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0068] It is further preferable that the delay circuits are extracted from a delay circuit library. [0069] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0070] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0071] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0072] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on: the basis of both the read interconnection data and a previously prepared delay library. [0073] The fifth present invention provides a semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common Clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of; the clock tree paths, and second type flip-flop circuits having a delay which compensates a difference between the average delay value and the maximum value. [0074] It is preferable that the second type flip-flop circuit comprises a flip-flop circuit configuration only, and the second type flip-flop circuit comprises both the flip-flop circuit configuration and a delay circuit configuration provided on a previous stage of the flip-flop circuit configuration. [0075] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0076] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0077] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0078] The sixth present invention provides a semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a first range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having delay values in a second range between the average delay value and a minimum value of the individual delay values of all of the clock tree paths, and wherein delay circuits having a delay which compensates a difference between the average delay value and the maximum value are provided on previous stages of the second type flip-flop circuits. [0079] It is preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0080] It is also preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0081] It is further preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. PREFERRED EMBODIMENT FIRST EMBODIMENT [0082] A first embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 4 is a flow hart illustrative of a first novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a first embodiment in accordance with the present invention. [0083] In a step S11, the process is started. [0084] In a step S12, a circuit design is executed to form a let-list. [0085] In a step S13, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0086] In a step S14, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0087] In a step S15, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted. [0088] In a step S16, on the basis of the delay values of all paths of the clock-tree, an average of the delay values is calculated. [0089] In a step S17, it is verified whether or not the calculated average is within an acceptable range which has previously been set, wherein the acceptable range has a range center which corresponds to an intermediate value between the maximum and minimum values of the delay values. FIG. 5 is a diagram illustrative of a distribution of a delay value of clock tree paths to extracted flip-flop circuits in a first embodiment in accordance with the present invention. The distribution of the delay value of the clock tree paths is symmetrical with reference to the average value �C� which is intermediate between the maximum and minimum delay values. It is preferable that the distribution of the delay value of the clock tree paths is the normal distribution, wherein the average value corresponds to the center of the acceptable range. If the calculated average is within the acceptable range, then the calculated average is not so different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is almost symmetrical with reference to the center of the maximum and minimum delay values. In this case, the following batch process is carried out. If the calculated average is out the acceptable range, then the calculated average is largely different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is largely asymmetrical with reference to the center of the maximum and minimum delay values. In this case, individual processes are executed in place of the batch-process. [0090] In a step S18, if the calculated average is within the acceptable range, then each of the extracted individual delay values of the individual clock tree paths is compared to the calculated average value. [0091] In a step S19, clock tree paths faster than the average value are extracted. [0092]FIG. 6 is a block diagram illustrative of an extracted clock tree in a first novel design method in a first embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three flip-flop circuits 42. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three flip-flop circuits 43. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three flip-flop circuits 44. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 6, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three flip-flop circuits 41. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three flip-flop circuits 42. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three flip-flop circuits 43. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three flip-flop circuits 44. Whereas the four clock tree paths are faster than the average delay value, it is probable that six clock tree paths are extracted as faster than the average value in cause of the twelve flip-flop circuits. [0093] In a step S20, a batch-replacing process is carried out, wherein the flip-flop circuits coupled to the clock tree paths faster in delay value than the average value are substituted with substitute flip-flop circuits with delays which compensate to a difference between the average value and the maximum value. The substitute delay flip-flop circuits are selected from a previously prepared delay flip-flop circuit library. [0094]FIG. 7 is a block diagram illustrative of a substituted clock tree in a first novel design method in a first embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three substituted delay flip-flop circuits 41A. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three substituted delay flip-flop circuits 42A. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three substituted delay flip-flop circuits 43A. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three substituted delay flip-flop circuits 44A. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 7, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three substituted delay flip-flop circuits 41A. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three substituted delay flip-flop circuits 42A. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three substituted delay flip-flop circuits 43A. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three substituted delay flip-flop circuits 44A. The three substituted delay flip-flop circuits 41A, the three substituted delay flip-flop circuits 42A, the three substituted delay flip-flop circuits 43A, and the three substituted delay flip-flop circuits 44A are the same as each other in delay amount. Each of the three substituted delay flip-flop circuits 41A, the three substituted delay flip-flop circuits 42A, the three substituted delay flip-flop circuits 43A, and the three substituted delay flip-flop circuits 44A has the same circuit configuration. FIG. 8 is a circuit diagram illustrative of a substituted delay flip-flop circuit in FIG. 7. Each of the substituted delay flip-flop circuits 41A, 42A, 43A and 44A comprises a flip-flop circuit region and a delay circuit region, wherein the flip-flop circuit region comprises series connections of plural flip-flop circuits and the delay circuit region comprises series connections of plural delay circuits. Each of the flip-flop circuits comprises a pair of first and second inverter circuits, wherein an input terminal of the first inverter circuit is connected to an output terminal of the second inverter circuit, and further an output terminal of the first inverter Circuit is connected to an input terminal of the second inverter circuit. Each of the delay circuits comprises a pair of an inverter circuit and a capacitance, wherein the capacitance is connected between an output terminal of the inverter and a ground line. The series connection of the plural delay circuits is provided on the pre-stage of the series connection of the flip-flop circuit. [0095]FIG. 9 is a diagram illustrative of a distribution of a delay value of clock tree paths to the substituted delay flip-flop circuits in a first embodiment in accordance with the present invention. The delay value is limited between the maximum value and the average value, wherein the variation in delay values is reduced. Namely, the clock skew value is reduced to a half. This �-reduced clock skew value is in the acceptable delay value range, wherein no malfunction appears on the flip-flop circuits. For this reason, in the acceptable range, the number of the paths is larger at both ends, for example, just over the average value and just under the maximum value than the center of the acceptable range, for example, intermediate between the average value and the maximum value as well shown in FIG. 9, whereby a possible uniform distribution can be obtained. [0096] In a step S21, layout of the substitute delay flip-flop circuit cells is carried out to prepare real interconnection data. [0097] In a step S22, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S23. [0098] As described above, in accordance with the first novel method of the present invention, clock tree paths faster in delay value than the average delay value are extracted. A batch-substitution process is carried out for batch-substituting all flip-flop circuits connected to the extracted clock tree paths into substitute delay flip-flop circuits which have a delay compensating a difference between the average value of the delay values and a maximum value of the delay values to reduce the clock skew value into a half. The batch-substitution process results in a reduction in the number of the processes for obtaining the reduced clock skew. SECOND EMBODIMENT [0099] A second embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 10 is a flow hart illustrative of a second novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a second embodiment in accordance with the present invention. [0100] In a step S11, the process is started. [0101] In a step S12, a circuit design is executed to form a let-list. [0102] In a step S13, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0103] In a step S14, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0104] In a step S15, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted. [0105] In a step S16, on the basis of the delay values of all paths of the clock-tree, an average of the delay values is calculated. [0106] In a step S17, it is verified whether or not the calculated average is within an acceptable range which has previously been set, wherein the acceptable range has a range center which corresponds to an intermediate value between the maximum and minimum values of the delay values. As shown in FIG. 5, the distribution of the delay value of the clock tree paths is symmetrical with reference to the average value �C� which is intermediate between the maximum and minimum delay values. It is preferable that the distribution of the delay value of the clock tree paths is the normal distribution, wherein the average value corresponds to the center of the acceptable range. If the calculated average is within the acceptable range, then the calculated average is not so different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is almost symmetrical with reference to the center of the maximum and minimum delay values. In this case, the following batch process is carried out. If the calculated average is out the acceptable range, then the calculated average is largely different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is largely asymmetrical with reference to the center of the maximum and minimum delay values. In this case, individual processes are executed in place of the batch-process. [0107] In a step S18, if the calculated average is within the acceptable range, then each of the extracted individual delay values of the individual clock tree paths is compared to the calculated average value. [0108] In a step S19, clock tree paths faster than the average value are extracted. [0109] As shown in FIG. 6, a clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three flip-flop circuits 42. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three flip-flop circuits 43. The clock signal is furthermore transmitted from the seventh buffer, circuit 57 through a tree path 64 to three flip-flop circuits 44. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 6, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three flip-flop circuits 41. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three flip-flop circuits 42. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three flip-flop circuits 43. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three flip-flop circuits 44. Whereas the four clock tree paths are faster than the average delay value, it is probable that six clock tree paths are extracted as faster than the average value in cause of the twelve flip-flop circuits. [0110] In a step S30, a batch-insertion process is carried out, so that insertion delay circuits are inserted onto previous stages of the flip-flop circuits coupled to the clock tree paths faster in delay value than the average value, wherein the insertion delay circuits have a delay which compensates to a difference between the average value and the maximum value. The insertion delay circuits are selected from a previously prepared delay circuit library. [0111]FIG. 11 is a block diagram illustrative Of a batch-processed clock tree in a second novel design method in a second embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 41A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 41A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three extracted flip-flop circuits 42A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 42A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 42A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three extracted flip-flop circuits 43A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 43A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 43A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three extracted flip-flop circuits 44A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 44A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 44A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 11, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 and the delay circuit 40 to the three extracted flip-flop circuits 41A. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 and the delay circuit 40 to the three extracted flip-flop circuits 42A. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 and the delay circuit 40 to the three extracted flip-flop circuits 43A. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 and the delay circuit 40 to the three extracted flip-flop circuits 44A. The delay circuits 40 are the same as each other in delay amount. Each of the delay circuits 40 has the same circuit configuration. FIG. 12 is a circuit diagram illustrative of a delay circuit in FIG. 11. Each of the delay circuits 40 comprises series connections of plural pairs of inverters and capacitors, wherein the capacitor is connected between an output terminal of the inverter and a ground line. The series connection of the plural sets of the inverters and capacitors is provided on the pre-stage of the flip-flop circuit. [0112] As shown in FIG. 9, the delay value is limited between the maximum value and the average value, wherein the variation in delay values is reduced. Namely, the clock skew value is reduced to a half. This �-reduced clock skew value is in the acceptable delay value range, wherein no malfunction appears on the flip-flop circuits. For this reason, in the acceptable range, the number of the paths is larger at both ends, for example, just over the average value and just under the maximum value than the center of the acceptable range, for example, intermediate between the average value and the maximum value as well shown in FIG. 9, whereby a possible uniform distribution can be obtained. [0113] In a step S31, layout of the flip-flop circuit cells is carried out to prepare real interconnection data. [0114] In a step S32, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S33. [0115] As described above, in accordance with the second novel method of the present invention, clock tree paths faster in delay value than the average delay value are extracted. A batch-insertion process is carried out for batch-inserting, inserting delay circuits onto a previous stage of all of flip-flop circuits connected to the extracted clock tree paths, wherein the inserting delay circuits have a delay compensating a difference between the average value of the delay values and a maximum value of the delay values to reduce the clock skew value into a half. The batch-insertion process results in a reduction in the number of the processes for obtaining the reduced clock skew. [0116] Whereas modifications of the present invention will be apparent to a person having ordinary skill in the art, to which the invention pertains, it is to be understood that embodiments as shown and described by way of illustrations are by no means intended to be considered in a limiting sense. Accordingly, it is to be intended to cover by claims all modifications which fall within the spirit and scope of the present invention. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6550045 *Nov 20, 2001Apr 15, 2003Lsi Logic CorporationChanging clock delays in an integrated circuit for skew optimizationUS6557152 *Oct 19, 2000Apr 29, 2003Nec Electronics CorporationMethod of designing signal distribution circuit and system for supporting the sameUS6698006 *Dec 14, 2001Feb 24, 2004Sequence Design, Inc.Method for balanced-delay clock tree insertionUS6782519 *Aug 29, 2002Aug 24, 2004Cadence Design Systems, Inc.Clock tree synthesis for mixed domain clocksUS6800633Dec 1, 2000Oct 5, 2004Osi Pharmaceuticals, Inc.Pyrrolo[2,3d]pyrimidine compositions and their useUS6944840 *Feb 13, 2002Sep 13, 2005Hitachi, Ltd.Design method and system for achieving a minimum machine cycle for semiconductor integrated circuitsUS7302657 *Sep 26, 2002Nov 27, 2007Telefonaktiebolaget L M Ericsson (Publ)Optimization of the design of a synchronous digital circuitUS7818705 *Apr 8, 2005Oct 19, 2010Altera CorporationMethod and apparatus for implementing a field programmable gate array architecture with programmable clock skewUS8640067Sep 17, 2010Jan 28, 2014Altera CorporationMethod and apparatus for implementing a field programmable gate array clock skewUS20130145331 *Oct 31, 2012Jun 6, 2013Synopsys, Inc.Sequential sizing in physical synthesisEP1308862A1 *Oct 29, 2001May 7, 2003Telefonaktiebolaget Lm EricssonOptimization of the design of a synchronous digital circuitEP1456784A1 *Dec 13, 2002Sep 15, 2004Cadence Design Systems, Inc.Clock tree synthesis for mixed domain clocksEP2040381A1 *Jul 25, 2007Mar 25, 2009Panasonic CorporationSemiconductor integrated circuit and layout technique thereofWO2003038687A2 *Sep 26, 2002May 8, 2003Ericsson Telefon Ab L MOptimization of the design of a synchronous digital circuitWO2003052643A1 *Dec 13, 2002Jun 26, 2003Silicon Perspective CorpClock tree synthesis for mixed domain clocks* Cited by examinerClassifications U.S. Classification716/113International ClassificationH01L21/82, H01L21/822, H01L27/04, G06F1/10, G06F17/50Cooperative ClassificationG06F17/5045, G06F1/10European ClassificationG06F1/10, G06F17/50DLegal EventsDateCodeEventDescriptionMay 29, 2007FPExpired due to failure to pay maintenance feeEffective date: 20070401Apr 1, 2007LAPSLapse for failure to pay maintenance feesOct 19, 2006REMIMaintenance fee reminder mailedMar 27, 2003ASAssignmentOwner name: NEC ELECTRONICS CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013892/0309Effective date: 20021101Owner name: NEC ELECTRONICS CORPORATION 1753 SHIMONUMABE NAKAHFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION /AR;REEL/FRAME:013892/0309Jan 19, 2001ASAssignmentOwner name: NEC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KATO, AKITOSHI;REEL/FRAME:011479/0681Effective date: 20010116Owner name: NEC CORPORATION MINATO-KU 7-1, SHIBA 5-CHOME TOKYOOwner name: NEC CORPORATION MINATO-KU 7-1, SHIBA 5-CHOMETOKYO,Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KATO, AKITOSHI /AR;REEL/FRAME:011479/0681RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google

value: Google Patents is a search engine from Google that indexes patents and patent applications.


text:
Rafaelly Condessa (rafaellycondessa) on Pinterest
Rafaelly Condessa
Elegant Homecoming DressesModest Prom DressesGraduation DressesProm Dress LongHigh Low Prom DressesProm Dresses For TeensProm GownsBlue DressesFormal DressesClothesDream WeddingForward
Charming Prom Dress,High/Low Prom Dress,Sweetheart Prom Dress,Appliques Prom Dress sold by Reliable Dress. Shop more products from Reliable Dress on Storenvy, the home of independent small businesses all over the world.
Navy Blue Prom DressesHigh Low Prom DressesBackless Prom DressesHalter Prom DressProm Dresses 2017Prom Party DressesQuinceanera DressesGrad DressesProm GownsGraduationEveningTricksForward
High Low Prom DressesProm Dresses 2015Party QueenQuinceanera IdeasGreen LaceMint GreenGowns OnlineDress Party15 YearsForward
High Low Prom Dresses 2015 Mint Green Lace Top Ruffled Organza Sleeveless Sheer Neck College 8th Homecoming Dresses Hi-Lo Party Queen Gowns Online with $111.96/Piece on Sweet-life's Store | DHgate.com

type: global

value: Pinterest is an American image sharing and social media service designed to enable saving and discovery of information (specifically "ideas") on the internet using images and, on a smaller scale, animated GIFs and videos, in the form of pinboards. The site was created by Ben Silbermann, Paul Sciarra, and Evan Sharp and had over 478 million global monthly active users as of March 2021.


text:
Beauties Who Brunch Event Tickets, Sun, Jul 23, 2017 at 1:00 PM | Eventbrite
by Portland Women of Color
Sun, July 23, 2017, 1:00 PM – 4:30 PM PDT
Go to pdxwomenofcolor.wordpress.com to join our email list. Portland Women of Color is an inclusive empowerment movement to connect, inspire and share through conversation and event-based networking. Our vision is to become the center point for women of color in the greater Portland/ Vancouver metro areas. In addition to building a platform that allows us the opportunity to promote women owned businesses, encourage one another and unite as women. Our mission is to encourage, inspire and support women of color in their personal and professional goals. Ways that you can support Portland Women of Color: Help spread the word by sharing on social media. Join us at our next event as an attendee, event sponsor or as a vendor. We love input! Share with us ways that Portland Women of Color can serve you personally or professionally. Get involved with our upcoming events as a speaker, vendor or volunteer.
We are so excited to host Beauties who Brunch Portland, Sunday, July 23rd. Our theme is Beautifully Flawed. Our mission is to empower, encourage, and inspire women through hair, makeup, and fashion. We'll beautify you from the inside out. Together we'll learn, share, and inspire one another.
Connect with a panel of industry leaders in make-up, hair and fashion, and shop local vendors.
Don't miss this amazing event. Get your tickets today!
Limited Vendor & Sponsorship Opportunities Email: pdxwomenofcolor@gmail.com
Beauties Who Brunch Event at The Village Ballroom
704 NE Dekum Street, Portland, OR 97211
PFSA VIP/Sponsor Exclusive Invitation
Progressive and Regressive Textile Design

value: Eventbrite is an American event management and ticketing website. The service allows users to browse, create, and promote local events.


text:
PHP development | AJAX | CakePHP | MySQL | PHP | Thiết kế trang web
Need development work done in PHP, layout and HTML/CSS files will be provided. When an account created is approved (will have a form to complete as part of registration) they will be able to upload resume, complete profile. They will also be able to login and edit profile and update resume with new document.
• Potential customers registration have to be manually approved by site admin before profile page can be updated.
• Resumes can be uploaded in word document format.
• Approved customers will get a notification when their profile is approved.
• Customers can choose their password while signing up.
• Customers can update their profile ONLY when the account is approved.
• Backend features will be listed of approved customer details including their profile page information so admin can edit if required.
The site structure should be built with the capacity to expand in future with more development and social networking model. I am looking for long term provider for more projects:
Your team should be on this site for more than 2 years, feedback more than 4, you should have a mix of good design and technical team with PHP, Flash, AJAX and be able to do small to large scale projects with proven testing and bug free coding skills.
Please provide 5 of your best design work and 5 biggest projects you ever did. If you do not provide this, you bid will be rejected automatically.
Xem thêm: website development projects in php, Update resume, updated resume, testing resume, technical skills resume, technical skills for resume, technical resumes, technical resume format, social work resumes, social work resume, resume technical skills, resume layout, php development website, layout html 5 free, large website development for free, good resumes, good resume layout, get website development projects, get php projects work, get php projects, free php coding, free backend html 5, flash to html 5 development, edit mix, design resumes
Mã Dự Án: #1083378
Professional team at your service. Kindly review PMB. Thanks !!
Please find out work in pm
Hi,i am very interested in your project,i am sure i can do a great job for [url removed, login to view] you!
Will love to help..
I'm a 13+ year experienced expert in web app development. Please consider my offer
366474 Implement 3dcart layout 2 (N/A)
146639 ASP Bug fixing (N/A)
3dcart template changes ($30-250 USD)

value: Freelance (sometimes spelled free-lance or free lance), freelancer, or freelance worker, are terms commonly used for a person who is self-employed and not necessarily committed to a particular employer long-term. Freelance workers are sometimes represented by a company or a temporary agency that resells freelance labor to clients; others work independently or use professional associations or websites to get work.


text:
Uncategorized | Transparent Moments
I am changing this to be kind of a way for me to vent. It has been a while and since no one has really ever read my blog anyway, this will be an easy way for me to get some stuff off of my chest.
My name is Carey Edmond Pointer III and There are many things that I am and as hard as I try it is ver difficult to balance them all.
1. I am a Christian – First and foremost! I believe the Bible and all it says.
2. I am a Husband and Father – Wife Tyra. Kids Hope, Courtlyn, and Caleb, all of whom I love very much along with the rest of my family.
3. I am called to preach and proclaim the Gospel of Jesus Christ. – I am a pulpit preacher. I work hard and study and pray to be the best I can be and after all of that I still have nothing if God does not give it to me. My family name is known in preaching circles but I am the least known of us all. I have struggled with some envy in this aspect but that is another blog for another time.
4. I am an Entrepreneur – I operate a home based network marketing business. I still have a 9-5 but I do not want to be there forever. I want to commit myself to full time ministry but I still need an income as well as providing for my family, thus the business. What’s Up 5linx?!?!
That’s about it. Most of my posts whether here or on Social Media center around one of the above topics. Others will be sprinkled in but they usually are just a subset of these 4.
Tags: gospel of jesus christ, network marketing business
I Gave this assignment to our preachers class and thought I would share. This is rough to admit publicly but I feel doing it will help me be accountable on a much larger level. So if anyone reads this, let me know what you think.
Elder Carey E. Pointer III
2010 Ministry Assessment
In 2010 I can honestly say I feel I have not been the man or Minister that God has called me to be. As I reviewed the first three chapters of “What the Bible Says to the Minister” I have found several areas in which I fall short of this call. The hardest hitting chapter for me has been chapter 3. To me it feels as though I have lost focus of what my purpose of the ministry is supposed to be.
Mentoring others and teaching them about Christ is and should be the single most important thing in Ministry. My Witness has not been bold enough or strong enough to affect anything. I have allowed circumstances of life to shift my focus to other things. Even before preaching, my mind would often shift to “what will I do with this money?” I would even go to outside engagements with one of my main thoughts being “How much will I get”. This shift in focus has caused me to abandon consistent study and prayer time. Many times in 2010 I re-preached sermons not because I felt led by God, but because I had not taken the time to listen to Him for anything else. The “Saturday Night Special” was used several times this year.
Do I know God? Do I believe Him? Do I understand Him? Have I been faithful? These are questions I have asked myself as I looked over myself this year. Though my mouth has always said yes, my actions have too many times said no!
Do I know Him? Not the way I have acted in my home and sometimes in public.
Do I believe Him? Only when it is convenient or if I am trying to show off.
Have I been faithful? Not in my ministry, teaching, preaching, or in pursuit of what He has called me to do specifically the pursuit of a full time Pastorate.
What are the answers? I don’t know. I have prayed and thought and God has given me some goals and things to pursue in order to get back where he would have me to be.
I will be back soon. I really want to start posting more.
It’s like I’m tired of life/ Lord i’m wrong why I cant get right/ And when it’s dark why I cant get light/ eh why it cant be light it’s so heavy why my sin won’t let me see the end/ come get me/ please come get me/ my thoughts my mind/ my ways all evil/ I’m sposed to be your people I’m sposed to see your sequal/ I said I’ll never leave you/ But I’m so left i aint right Lord I’m sleeping with death/man, I am cheating with death/ am I deaf Its like I don’t hear you/ I say that I’m a Christian but it’s like I don’t fear you/ I’m on a selfish island and i am no where near you/ God i really need you even tho I don’t appear to/ I’m drinking out a broken cistern that could never hold water and I’m gonna get burned/ tho I try i never satisfy or quench this yearn/ I hear you calling but it’s like a fight for me to just turn/Lord I deserve to burn
I ain’t living I’m just breathing to death (echo)
I’m fellin’ skitzophrenic / maybe I ain’t saved cause i gotta get high just to block out all the pain/ seen death, seen hurt seen a whole lotta thangs/ instead of running from it I’m running away from change/ it’s like I’m outside in the ice cold weather/the rains coming down and I keep getting wetter/ I know I’m getting sick and I could die any second/ but still I refuse to let your truths make me better/ I’d rather eat flies and maggots instead of bread/ and its killing me slow but i cant get it through my head/ you were stabbed you were murdered/ and for me is why you bled/ but I spit on your bloody face as If i never cared/ And Lord how dare i compare my pain/ your father turned his back/ and you were left to hang/ I don’t know why you did it that I cant explain/ how can you love this sinner whose desecrated your name/Lord I deserve the flames
I know I tell lies/ I know I do dirt/ Apart from you I’m nothing but you can give me worth/ I don’t know if I know you/ But still I know I should/ I know the days are evil and only you are Good/ I’ve come to this conclusion I would like to change cause all the worlds money and fame cannot sustain/ I know that i should turn but thats the hardest thang/ cause do I really feel that havin’ Jesus is my gain/ the world is so tempting/ Satan is a beast/ he hypnotizes my eyes to say the least/ But Jesus be my treasure to know you is live/ and I am here dying trying everything there is/ All I need here is you/ help me turn away from sin/ Lord give me grace to turn away and the fear not to give in/ I know that I’m not perfect but if I could rest in Him/ I know i don’t deserve it but still I’ll take your hand/Lord let me take your hand
…your Theology was put under a microscope every time you spoke?
…everything you did was reported on by the media?
…you were really good at something and because you were really good at it people put you on a pedestal only waiting for a chance to knock you down?
…people ignored any good you said or did because they were too busy talking about the one thing you said/did they didn’t agree with?
…every past mistake in your life was news worthy?
Would your witness stand the test?
Would you hold up under the spotlight?
Or would you need some grace, some mercy and some more time to get things right?
Consider this…(emphasis mine)
I will be back soon with an explanation of why I apused blogging after just starting( not that anyone cares).

value: WordPress (WP, WordPress.org) is a free and open-source content management system (CMS) written in PHP and paired with a MySQL or MariaDB database. Features include a plugin architecture and a template system, referred to within WordPress as Themes.


text:
Waiting and waiting, and… Waiting. – A slice of Heaven
Waiting and waiting, and… Waiting.
Sometimes I think it’s frustrating to be your girlfriend.
I hate it that I have to always wait around for you. As much as work is highly important, and at all cost should you put it before me. I feel that it is ridiculous that your can never plan at all, what you should do in chronological order.
“Play it by ear” should only be used when you have already set a time to meet. Not when I am left hanging not sure of my next step. But oh wells, you know what, just forget it. Absolutely forget it. I am a fool to think that you will be slightly more mindful.
Urgh, plus my damn hormones. I can’t keep my emotional in check. I am officially quite pissed off.
Posted on April 25, 2014 April 25, 2014 Author Just another girlCategories Not to self
Next Next post: Brunch and tulips.


text:
Pinky's Favorite Reads: The Wolf Bride - Release and Giveaway
Goodreads: https://www.goodreads.com/ElizabethMoss Giveaway

value: Blogger is an American online content management system (CMS) which enables multi-user blogs with time-stamped entries. Pyra Labs developed it before being acquired by Google in 2003.


text:
Jim's Music Notes: September 2011
..quick notes from XMass..
New housemate's band, Wizard Boots, plays Kelly's Olympian Knife Shop this Thursday. Haven't heard them yet myself, but the name cracks me up! On Oct. 7, I will be doing the cross town dash - first Lost Lander (Matt Sheehy's and Brent Knopf's new band) will preview their up coming CD and opening for Loch Lomond at Mississippi Studios, then Richmond Fontaine's record release at the newly re-furbished Star Theatre on NW 6th across from The Roseland. The Oregon Music Hall of Fame gala is Oct. 8th at a new location, The Newmark Theatre on SW Broadway....and with Johnny and the Distractions for us old rockers. Oct. 12, Baaba Maal at the Alberta Rose, brings music and stories from Mali.
The Joys of working many jobs...
..instead of one good one, is that I have been too tired to even think about adding my two cents here..and trust me, that ain't easy for an Italian girl...but here's is something to add to the dance card for Saturday, Sept. 24 - Mango Madness African Dance Party, a benefit for Ko-Falen Cultural Center in Bamako, Mali. My friends, Baba Wague Diakite and Ronna Neuenshwander, local ceramic artists, started this center in Wague's native Mali to provide a resource for native artisans and visiting artists to educate, inspire and preserve the arts in Mali. It's at The Plant, 939 SE Alder, 7 PM to midnite, tickets at the door or at www.ko-falen.org. Music by Jujuba, DJS, there will be food, no-host bar, African market and a raffle and silent auction. African dancing and helping a good cause - what's not to love?Also, a little bird has told me that Paula Sinclair will be one of the openers for John Doe at Dante's on Oct. 22....
James Low Kickstarter Campaign
Music artists fan-funding their projects has become an extremely viable way to get the funds necessary to record, mix, market, press, etc., a new recording (not cheap to do if you want to do it right). If you follow my blog, you know that James Low is one of those artists in town that I think should be know far and wide. I have had the chance to preview the tracks of his new CD, Whiskey Farmer, and think it's the best recording he has produced. Please think about joining his Kickstarter campaign to help fund the final pieces necessary to properly do the release of this outstanding recording. BTW, there's a very cool video of the title track at the site too ... check it out ... Thanks for your attention! - Jim Posted by
Three excellent touring acts in town tonight - McMurtry, Rev. Payton, Flaming Lips
In case you missed knowing about these ...
James McMurtry at the Aladdin ... 8 pm, $20
Rev. Payton's Big Damn Band at Dante's ... 9 pm, $14
and... the Flaming Lips are at Keller Auditorium ... 8 pm, $50/$65
There's always more, so do check the local music calendars for complete info .... Posted by
Midweek picks ... Wednesday and Thursday
Casey Neill contines his week's residency at Al's Den in the Crystal Hotel (thru Saturday) ... Matt Brown joins him tonight ... 7 pm, no cover
Colin Hay will be the man at work at the Alberta Rose ... show is sold out, but if you really want to go, show up early and be patient ... 7:30 pm, $30
Swing Papillion will django-ize the Press Club ... 8:30 pm, no cover
Fine jazz with pianist Gordon Lee and Duncan Branom, Ed Bennett @ Vie de Boheme ... 8 pm, $7
Sublime vocals of Nancy King can be heard at Touche ... 8:30 pm, no cover
ThursdayHappy hour music? Catch the Portland Playboys at Duff's or Lewi Longmire at the Laurelthirst ... 6 pm
Bob Shoemaker is at the White Eagle ... 8:30 pm, no cover
Thad Beckman (back in town after extensive summer touring) and Kurtis Piltz will be at O'Connor's ... 8 pm, $5
Cecilio & Kapono - a "household name throughout Hawaii and the Pacific" bring their island sounds to the Aladdin ... 8 pm, $30
Memphis-based singer/songwriter/bassist Amy LaVere is at Mississippi Studios ... 9 pm, $10 ... and she'll be at Music Millennium at 6 pm for a free in-store performance.
It will be a delightful night of Celtic music with Molly's Revenge and Coleen Raney at the Secret Society ... 9 pm, $7
Another fine singer/songwriter, Austin-based Matt the Electrician, is at the The Woods ... 9 pm, $12
Galactic's drummer Stanton Moore is in town with his trio tonight at Dante's ... 9 pm, $15
Friday Woodbrain plays the Laurelthirst happy hour ... 6 pm, no cover
If you're in the mood to head out of town this weekend, the always wonderful and nationally-respected Sisters Folk Festival starts Friday. This weekend there's also LiveWire Radio at the Alberta Rose, Widmer Octoberfest, John Prine and Ani Defranco at Edgefield, Mary Flower's CD release at the Secret Society ...
I have two tickets for Slaid Cleaves and Mary Gauthier at Alberta Rose tomorrow, Thursday, that a friend sent from Seattle because she can't make it down. If you are interested, call me at 503-516-6090. See you at TBA Fest or Music Fest NW!XMass
OMN’s guide to MFNW 2011 « Oregon Music News
Here's Oregon Music News' guide to Musicfest NW ... five days of music begins today!
September already?!! This is a relatively quiet weekend before Music Fest NW (here's Oregon Music New's guide to the fest to check out) and a few other big shows coming next week. But there's still some great choices for enjoying live music ... Friday
OK .... get out, enjoy the sunshine while we have it, then out for an evening of live music! Posted by
Three excellent touring acts in town tonight - McM...


text:
Beautiful Modern Corazon Condo - Kondominiji za najam - Dublin, Ohio, Sjedinjene Države
Bret & Diane
Bret & Diane je Superhost · Superhostovi su iskusni domaćini s izvrsnim ocjenama koji se iznimno trude gostima osigurati savršen boravak.
We enjoyed our stay at Bret and Diane's condo. It was very spacious and clean. The community is very beautiful and the condo is very close to shopping and restaurants. We definitely recommend this condo!
What a fantastic home. Bret and Diane have thought of everything. They are super responsive (even when we arrived late in the night for check-in), provided us all the information we needed and left us with all the amenities we could have asked for, including a lovely bottle of wi…
Your condo was the perfect spot for our family to be able to spend time together over the holiday. The layout was perfect, the furnishings very comfortable, you thought of everything we would need (including a pizza cutter, which by the way we needed) Loved the patio, it was ni…
Bret and Diane’s place was amazing. We were there for a wedding and it was secluded and an absolutely beautiful getaway spot. Their condo was stocked more than most homes I’ve been in and had everything we needed and more. We would definitely recommend it for anyone wanting to st…
This was our first time staying in an Airbnb home, and this one set the bar very high. I think it is safe to say that all future trips will have a difficult time measuring up to Bret and Diane's home. Our hosts were gracious with their provisions and generous in every way. The ho…
Domaćin – Bret & Diane
Columbus, Ohio, Sjedinjene Države · Član od Listopad 2016.

value: Airbnb, Inc. (pronounced  AIR-bee-ehn-bee and stylized as airbnb) is an American company that operates an online marketplace for lodging, primarily homestays for vacation rentals, and tourism activities.


text:
Sean Hellman: Dough bowl, flour scoop and bread
I have been making my own bread for years now, but only this year I got rid of the bread maker. This has been a liberating experience and I find making bread is now much more fun. I decided to start from scratch by making my own yeast. This is easy, by putting flour in a small bowl and leaving for a few weeks, adding a bit more flour and water every 3 days. The natural yeasts in the flour and atmosphere soon get to work. People have been known to have had their yeast 'starter', or 'mother', for decades.
Next I put my flour in a bowl with a bit of salt and water with most of the starter. This is mixed up and left all day. I come home from work and after dinner, empty the risen bread into a baking tin and let rise again for a few hours, depending on how warm it is. Then, into the oven it goes.
You may have been told that you need to knead your dough for 10 minutes or so. I have found no need for this, I may knead a bit more flour into the mix if it is a bit wet or if I need to divide it up into tins and rolls. This kneading will only take a minute at most. The actual time it takes me to make bread, including washing up is maybe 15 minutes.
After adzing out the bowl, (as shown in the last post), I used long handled hook knives to finish the inside and a Mora push knife on the outside. I wanted to have a smooth inside as I will be washing this bowl out regularly. The best and quickest way to do this is by scraping. As you can see the shavings are paper thin and leave a very good finish. Scraping is always far quicker and easier than going through the grades of sandpaper, and if you want a smooth finish then learn about scrapers. I will be doing a video on how to sharpen a scraper.
As you may have noticed from my Kuksas, I like handles. The handles on this bowl took a fair amount of time to do. This is one reason that we rarely see handles like this on wooden artefacts.
I also now buy some of my flour in the sack and need to decant from sack into a smaller container. So I made a scoop from a half log of birch.
I have found that even with a busy life, I have easily found time to make all my own wheat bread as well as rye bread for my wife. I even look forward to it. It is hard for me to explain why but it certainly has to do with working with a living organism (yeast) and also, I have control over what goes into my food. Another pleasure of this about being connected to the process of producing natural and slow food. I find a sort of meditation in the making of bread. We, as a culture, are losing connection to meaningful daily work with the hands, the everyday acts of creation. Making my own bread is a way of reclaiming that in another area of my life.


text:
A Labor Leader’s Devotion to His Cause - The New York Times
A Labor Leader’s Devotion to His Cause
Cesar Chavez in the documentary “Cesar’s Last Fast.”CreditCathy Murphy/Participant Media
Directed by Richard Ray Perez, Lorena Parlee
“I think I know what my mission is,” says the labor leader Cesar Chavez in “Cesar’s Last Fast.” “Righting the wrongs that were committed against workers for 100 years.” Chavez (1927-1993), a founder of what became the United Farm Workers union, faced brutal odds, as this compelling documentary demonstrates.
The film frames the life of Chavez around the 36-day water-only fast he underwent in 1988 to bring attention to the impact of grape and lettuce growers’ pesticides on farmworkers and their children (cancer, birth defects, he and others claimed). He saw his fast as penance for not having done enough for such laborers in the San Joaquin Valley in California. But Chavez, a tireless, charismatic organizer, had done plenty: leading striking grape workers on a protest march from Delano to Sacramento in 1966; orchestrating boycotts to raise workers’ wages in the early 1970s; and, with help from Jerry Brown, California’s governor at the time, pushing through the California Agricultural Labor Relations Act in 1975.
To its credit, the film doesn’t ignore the factionalism that hobbled his movement; Chavez’s messianic tendencies (there were other fasts, in 1968, 1970 and 1972); and his misguided espousal of the group therapy techniques of Synanon, a drug rehabilitation program that later evolved into a notorious cult.
A press secretary for Chavez, Lorena Parlee, who died in 2006, shot much of the intimate footage here; images of him as a withering bed-ridden 61-year-old are devastating. A haggard Chavez resumed his crusade afterward, only to die five years later. Farmworkers continue to struggle.
Richard Ray Perez, Lorena Parlee
Opens on Friday in Manhattan. Directed by Richard Ray Perez 1 hour 40 minutes; not rated
A version of this article appears in print on , on Page C8 of the New York edition with the headline: Cesar’s Last Fast. Order Reprints | Today’s Paper | Subscribe

value: The New York Times (N.Y.T. or N.Y. Times) is an American daily newspaper based in New York City with a worldwide readership. Founded in 1851, the Times has since won 132 Pulitzer Prizes (the most of any newspaper), and has long been regarded within the industry as a national "newspaper of record".


text:
Design Jobs [Page 17] - BusinessWeek
Viewing 161 - 170 of 657,111 jobs
Category: Instructional Design Location: Chicago, Illinois Caveo Learning is a learning consulting firm, providing learning solutions to Fortune 1000 and other leading organizations.We partner with Chief Learning Officers and other...
11 hours ago from Caveo Learning
Assistant Store Manager-Design Services
Requisition Number: PB-5864 Area of Interest: Retail Division: Retail Pottery Barn Position Type: Full Time JOB DESCRIPTION Job Purpose: Support the management team, delivering store results through sales floor leadership and completion of...
11 hours ago from Williams-Sonoma Inc.
Epic Radiant Instructional Designer /Analyst II Job
training projects for assigned application(s) including the design, development, delivery, evaluation, continuous ... attends meetings as required. 7. Performs complex analysis, design, development, testing and support services for...
Developer/Designer for FX Trading company
A new direct-with-manager role has opened up at a major foreign exchange electronic trading company Manhattan. The manager is looking to hire RIGHT AWAY for this position and will be holding INTERVIEWS next week. The manager is searching...
Contribute to product design for type/ graphic treatments ... and prioritize daily workload. Fluent in illustrator, in-design, and Photoshop; Excellent typography WHAT WE’RE...
13 hours ago from Centers Health CARE
factors in a cost effective manner. • Evaluate design issues related to output performance, amplification, ... design process. • Apply state of the art design concepts to an emerging technology that represents the future...
14 hours ago from Custom Sensors & Technologies
Sr Designer, Product Development (Home & Stationery)
Jobnewsusa - Pasadena, CA
Top, and Stationery product and components in regards to design and development * Able to suggest on trend, ... or equivalent work experience in related field * Graphic Design Experience - 3-5 years experience preferred *...
GAAP in the Graphic Design industry is seeking a full time Design Associate. The company offers the following ... to customer desires, Taking feedback and critiques into the design process to ensure customer satisfaction, Use of...
Sr. IC Design Engineer (WiFi/DSP)
dsp systems team o Algorithm design/implementation, RTL design/implementation, pre and post-silicon validation, and ... languages, RTL design/verification, and of ASIC design methodology - Experience in one or more of the...
15 hours ago from Broadcom
Business Management Training ProgramInsurance Sales AgentSales Representative - TraineeProject ManagerSoftware EngineerJava DeveloperSeasonal Team MemberSee More »
OraclePlatinum Supplemental InsuranceNw RecruitersDellU.S. Navy ReserveSaudi AramcoCovenant TransportAmazonSee More »
New York CityChicagoHoustonSan FranciscoAtlantaWashingtonSeattleBostonLos AngelesDallasSan DiegoAustinCharlottePhoenixMinneapolisPhiladelphiaSan JoseColumbusBaltimoreDenverSee More »

value: Bloomberg Businessweek, previously known as BusinessWeek, is an American weekly business magazine, published 50 times a year. Since 2009, the magazine is owned by New York City-based Bloomberg L.P. The magazine debuted in New York City in September 1929.