text:
Capital Gaines: Smart Things I Learned Doing Stupid Stuff book by Chip Gaines | 7 available editions | Alibris Books
Now available in paperback with bonus content and a new cover. "National Bestseller-New York Times, USA Today, Publisher's Weekly, Wall Street Journal" The funny and talented Chip Gaines is well known to millions of people as a TV star, renovation expert, bestselling author, husband to Joanna, and father of five in Waco, Texas. But long before the world took notice, Chip was a serial entrepreneur who was always ready for the next challenge, even if it didn't quite work out as planned. Whether it was buying a neighborhood ... Read More
Now available in paperback with bonus content and a new cover. "National Bestseller-New York Times, USA Today, Publisher's Weekly, Wall Street Journal" The funny and talented Chip Gaines is well known to millions of people as a TV star, renovation expert, bestselling author, husband to Joanna, and father of five in Waco, Texas. But long before the world took notice, Chip was a serial entrepreneur who was always ready for the next challenge, even if it didn't quite work out as planned. Whether it was buying a neighborhood laundromat or talking a bank into a loan for some equipment to start a lawn-mowing service, Chip always knew that the most important thing was to take that first step. Now a #1 New York Times bestselling book, Capital Gaines offers readers a ringside seat as Chip relives some of his craziest antics and the lessons learned along the way. His mentors taught him to never give up and his family showed him what it meant to always have a positive attitude despite your circumstances. Throw in a natural daredevil personality and a willingness to do (or eat!) just about anything, and you have the life and daily activity of Chip Gaines. Capital Gaines is the perfect book for anyone looking to succeed not only in business but more importantly in life. Read Less
Alibris ID: 15526270952
Alibris ID: 15541739085
Alibris ID: 15528403936
Alibris ID: 15443841824
Alibris ID: 15537774061
Good. The dust jacket shows normal wear and tear. This is a hard cover book. It may have a minor bump or bruise. Minor cover or page wear/markings may be present as signs of previous use. Any additional materials( access codes/ CD, tables, charts, cards, letters, etc. ) are NOT promised to be included. The pages are slightly stained or discolored, but not excessive. There may be creases or discoloration on the binding/spine of the book. The corners of the book may be slightly curled or frayed. Page corners may be turned down as a page marker from previous use. Fast Shipping Monday through Friday-Safe and Secure! Please verify your shipping address at time of purchase to ensure delivery.
Alibris ID: 15543719718
Alibris ID: 15534428686
Alibris ID: 15524530417
Alibris ID: 15542114829
Alibris ID: 15446205588
ISBN-13: 9781978671799
ISBN-13: 9781978671805
ISBN-13: 9781543637304
ISBN-13: 9781543637328
ISBN-13: 9781543637311
All Editions of Capital Gaines: Smart Things I Learned Doing Stupid Stuff
9781978671799
9781978671805
9780785216247
9781543637304
9781543637328

value: Alibris is an online store that sells new books, used books, out-of-print books, rare books, and other media through an online network of independent booksellers.


text:
Vector - Illustrator Skills - Designer Wanted For Long-Term Job. | Illustration | Illustrator
Vector - Illustrator Skills - Designer Wanted For Long-Term Job.
'm looking for a dedicated designer for Vector Illustration daily tasks.
Someone that is fast, skilled and is willing to create given designs 6h/day Monday to Friday.
Long-Term Collaboration and possible raise upon quality.
*** READ THIS BEFORE YOU APPLY ***
I'm LOOKING FOR STARTERS, INTERNS, I will teach them our 10 years experience in Design.
DON'T APPLY if you want single-projects!
I want someone that is available full time 6h/day on Skype.
****And salary is per month****
See more: why are you looking for a new job, what are you looking for sales job seekers west rand, salaries in zar for graphic designer with 23 years experience, looking for amazing illustrator graphic designer, are you looking for a vacancy as graphic designer cor, are you looking for a psychic online job, are you looking for an illustrator west virginia, are you looking for a home based bookkeeping job, long term romance writers wanted, illustrate something logo, illustrate something for, illustrate something for unicorn kingdom cover, illustrate something for my eliquid company, illustrate something for maritime logistics for lng, illustrate something for greeting card, illustrate something for bachelorette, illustrate something for a swimming pig, illustrate something for a power, illustrate something for a jewelry design, illustrate something for a banner size 600mm x 1600mm
( 0 reviews ) Sibiu, Romania
Project ID: #12200880
39 freelancers are bidding on average $255 for this job
Buna ziua, Va rog sa-mi spuneti mai multe detalii. Am peste 10 ani experienta si sunt disponibil zilnic 10-12 ore. Multumesc Adrian exemple vectori [login to view URL]
Hi! I'm designer-illustrator with medium level expirience of vector works. High expirience of drawing /painging. Let's discuss the conditions! Look my portfolio pls! [login to view URL]
Hi, I am ready to accept your projects for $250 within the allocated time with best of my efforts. Please check my portfolio. https://www.freelancer.in/u/logosuit.html?page=portfolio Thanks.
Hello, We are very interested for this project. we have all the experience and expertise on similar work. Want to along time relation ship for multiple project not a single project. You can check our work at htt More
$210 USD in 26 days
Hello sir/madam. I am Hau from VietNam. I read through the job details extremely carefully and I am absolutely sure that I can do the project with 6 hours/day. We can discuss more when talk. I also attach my sample wo More
Regards, I am interested in your proposal of fixed work. I am an illustrator with several years of experience, my specialty is vector illustration. I can work full time if the salary is competitive and functional. Y More
Buna ziua, Sunt un grafician specializat in Ilustratii si design 2D. Pot realisa designul pentru orice document destinat printari sau internet (bannere, flyere, business card, logo-uri etc...).Deasemenea pot realiza More
Hello, I can create daily illustrations and I can deliver SVG images. My proposal is with "salary per month", for up to 30 illustrations for the calendar month. Best regards, Valentin Novakov
Need a logo for product labelling (₹660 INR)
Quick colouring job ($10-30 USD)

type: global

value: Freelance (sometimes spelled free-lance or free lance), freelancer, or freelance worker, are terms commonly used for a person who is self-employed and not necessarily committed to a particular employer long-term. Freelance workers are sometimes represented by a company or a temporary agency that resells freelance labor to clients; others work independently or use professional associations or websites to get work.


text:
9780896038240: Twentieth Symposium on Biotechnology for Fuels and Chemicals: Presented as Volumes 77–79 of Applied Biochemistry and Biotechnology Proceedings of the 1998, Gatlinburg, Tennesee (ABAB Symposium) - AbeBooks: 0896038246
Twentieth Symposium on Biotechnology for Fuels and Chemicals: Presented as Volumes 77–79 of Applied Biochemistry and Biotechnology Proceedings of the 1998, Gatlinburg, Tennesee (ABAB Symposium)
ISBN 13: 9780896038240
ISBN 10: 0896038246 ISBN 13: 9780896038240
Publisher: Humana Press, 1999
active industrial participation in the organizing committee. Recently, the conference has begun a regular informal industrial roundtable (Session 4). This has become very popular as it allows industrial participants to speak more openly. For a broader perspective, R. James Woolsey, Former Direc tor of Central Intelligence Agency, gave an after-dinner address on "Wagon Trains for the 21st Century: The Role for Biorefineries. " He urged the attendees of the importance of their efforts to develop renewable, benign processes for the United States and the world based on both security and prosperity reasons. These related to energy supply, support of domestic agriculture, global warming, and other issues. With the Twentieth Symposium, we continued the tradition of pro viding an informal, congenial atmosphere that our participants find condu cive to pursuing technical discussion of program topics. The technical program consisted of 35 oral presentations, a roundtable forum, two spe cial topic discussions, and a poster session of 133 posters. This year, tech nical topics included: Session 1: Feedstocks: New Supplies and Processing Session 2: Applied Biological Research Session 3: Bioprocessing Research Session 4: Emerging Opportunities for Industrial Chemicals Session 5: Bioprocess Evaluation and Confirmation Session 6: Enzymatic Processes and Enzyme Production Special topic discussions were held on "Defining the Future Separa tions Needs Derived from Bioprocessing" by Earl Beaver, Monsanto Com pany, St.
ISBN 10: 1461272149 ISBN 13: 9781461272144
1. Twentieth Symposium on Biotechnology for Fuels and Chemicals: Presented as Volumes 77?79 of Applied Biochemistry and Biotechnology Proceedings of the . 1998, Gatlinburg, Tennesee (ABAB Symposium)
Book Description Humana Press. Hardcover. Condition: New. 0896038246 Brand new *sealed* copy. Never been opened or read. No dust jacket as issued. Couple small holes in seal. Seller Inventory # SKU1005537
2. Twentieth Symposium on Biotechnology for Fuels and Chemicals: Presented as Volumes 77-79 of Applied Biochemistry and Biotechnology Proceedings of the . 1998, Gatlinburg, Tennesee (ABAB Symposium)
Book Description Condition: New. This book is hardcover. The item is Brand New! Fast Shipping - Safe and Secure - Ships from Utah! Book may have minor shelf wear and/or sticker residue. SPINE DAMAGE ALONG BOTTOM LEFT EDGE, HOWEVER TEXT IN PERFECT CONDITION. PRICED ACCORDINGLY. Seller Inventory # 2RU7DC00026J
3. Twentieth Symposium on Biotechnology for Fuels and Chemicals: Presented as Volumes 77?79 of Applied Biochemistry and Biotechnology Proceedings of the 1998, Gatlinburg, Tennesee (ABAB Symposium)
Published by Humana Press (1999)
Book Description Humana Press, 1999. Condition: New. book. Seller Inventory # M0896038246
4. Twentieth Symposium on Biotechnology for Fuels and Chemicals: Presented as Volumes 77-79 of Applied Biochemistry and Biotechnology Proceedings of the . 1998, Gatlinburg, Tennesee (ABAB Symposium)
Brian H. Davison (Editor), Mark Finkelstein (Editor)
Book Description Humana Press, 1999. Hardcover. Condition: New. 1999. Seller Inventory # DADAX0896038246
5. Twentieth Symposium on Biotechnology for Fuels and Chemicals
Book Description Humana Press. Condition: New. pp. 904. Seller Inventory # 7591332
6. TWENTIETH SYMPOSIUM ON BIOTECHNOLOGY FOR FUELS AND CHEMICALS (ABAB SYMPOSIUM)
FINKELSTEIN, MARK; DAVISON, B.
Book Description Condition: Brand New. Brand New Original US Edition, Perfect Condition. Printed in English. Excellent Quality, Service and customer satisfaction guaranteed!. Seller Inventory # AIND-11415
7. TWENTIETH SYMPOSIUM ON BIOTECHNOLOGY FOR FUELS AND CHEMICALS (ABAB SYMPOSIUM)
Book Description Condition: New. Brand New Original US Edition.We Ship to PO BOX Address also. EXPEDITED shipping option also available for faster delivery.This item may ship fro the US or other locations in India depending on your location and availability. Seller Inventory # AUSBNEW-11415
8. BIOTECHNOLLGY FOR FUELS AND CHEMICAL: PROCEEDINGS OF THE TWENTIETH SYMPOSIUM ON BIOTECHNOLOGY FOR FUELS AND CHEMICALS
Book Description Condition: New. This is Brand NEW. Seller Inventory # Star-07062018-17454
9. Twentieth Symposium on Biotechnology for Fuels and Chemicals: Presented as Volumes 77-79 of Applied Biochemistry and Biotechnology Proceedings of the Twentieth Symposium on Biotechnology for Fuels and Chemicals Held May 3-7, 1998, Gatlinburg, Tennesee (Hardback)
Published by Humana Press Inc., United States (1999)
Book Description Humana Press Inc., United States, 1999. Hardback. Condition: New. 1999 ed.. Language: English . This book usually ship within 10-15 business days and we will endeavor to dispatch orders quicker than this where possible. Brand New Book. active industrial participation in the organizing committee. Recently, the conference has begun a regular informal industrial roundtable (Session 4). This has become very popular as it allows industrial participants to speak more openly. For a broader perspective, R. James Woolsey, Former Direc- tor of Central Intelligence Agency, gave an after-dinner address on Wagon Trains for the 21st Century: The Role for Biorefineries. He urged the attendees of the importance of their efforts to develop renewable, benign processes for the United States and the world based on both security and prosperity reasons. These related to energy supply, support of domestic agriculture, global warming, and other issues. With the Twentieth Symposium, we continued the tradition of pro- viding an informal, congenial atmosphere that our participants find condu- cive to pursuing technical discussion of program topics. The technical program consisted of 35 oral presentations, a roundtable forum, two spe- cial topic discussions, and a poster session of 133 posters. This year, tech- nical topics included: Session 1: Feedstocks: New Supplies and Processing Session 2: Applied Biological Research Session 3: Bioprocessing Research Session 4: Emerging Opportunities for Industrial Chemicals Session 5: Bioprocess Evaluation and Confirmation Session 6: Enzymatic Processes and Enzyme Production Special topic discussions were held on Defining the Future Separa- tions Needs Derived from Bioprocessing by Earl Beaver, Monsanto Com- pany, St. Seller Inventory # LIE9780896038240
10. Twentieth Symposium on Biotechnology for Fuels and Chemicals
Davison, Brian H.
Published by Humana Press Inc. (1999)
Book Description Humana Press Inc., 1999. HRD. Condition: New. New Book. Shipped from US within 10 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # IQ-9780896038240

value: AbeBooks is an e-commerce global online marketplace with seven websites that offer books, fine art, and collectables from sellers in over 50 countries. Launched in 1996, it specialises in used, rare and out-of-print books.


text:
Motel 168 Nanjing Zhongshan East Road Jiefang Road - รีวิวใหม่ล่าสุดและภาพถ่ายจริงจากนักท่องเที่ยว หนานจิง - TripAdvisor
โมเตล Motel 168 Nanjing Zhongshan East Road Jiefang Road หนานจิง
ที่ 1,080 จาก 2,143 ด้านโรงแรม ใน หนานจิง
No.42 Jiefang Road, Baixia District, หนานจิง 210017, จีน
คุณเคยไป Motel 168 Nanjing Zhongshan East Road Jiefang Road มาหรือยัง
南京莫泰168中山东路解放路店
210017白下区解放路42号
ห่างออกไป 4.5 กม. จาก ท่าอากาศยานนานกิง
{"BOOKING_FEATURES": ["IB_PRICES_OUTSIDE_ROOM_BUTTON","IB_STREAMLINED_SELECTED_ROOM","IB_HIDE_MSNBC_LARGEST_SITE_QUOTE","IB_SHOW_EMAIL_FOR_INSECURE_LOGIN","IB_EXIT_INTERRUPTER","RCMS_INLINE_ROOM_GRID_MAX_OCC","IB_SHOW_AMENITIES_AS_ICONS","IB_POST_BOOKING_LOGIN","IB_IRG_PERFORMANCE_METRICS","IB_IRG_MATCH_META","META_AIR","CHILDREN_SEARCH","IB_INLINE_ROOM_GRID","HR_IB_EXCLUDE_TAXES_AND_FEES","IB_TIME_OF_STAY_PAYMENT_TYPES_V3","IB_DW_CCNAME_WITH_AUTOCOMPLETE","IB_IRG_PERFORMANCE_METRICS_MOBILE","IBEX_HIGH_EQUITY_BRANDING","IB_PRICE_WINS_POST_TX","IB_BOOKING_FORM_FAVICON","STORED_CARDS","IB_PRICE_WINS_COPY","IB_URGENCY_BLOCK"] , "IMPRESSION_KEY": "7faf8e44350548f68bf1de629c5d9528", "roomSelectionModel": {"partnerInfos":[],"multiplePartners":false,"polling":{"locationId":2555064,"bookingSessionId":null,"detailedAvailabilityKey":null,"commerceContentIds":[],"additionalContentIds":[],"pollCount":0,"checkin":{"day":23,"month":12,"year":2018},"checkout":{"day":24,"month":12,"year":2018},"adults":2,"child_rm_ages":"","rooms":1,"display_rooms":300,"entryPrice":-1,"entryCurrency":"USD","complete":false,"formKey":"","showAllRooms":true,"genNewBookingSessionId":false,"winningProviderAtClick":"","selectedRoomKey":"","impressionKey":"7faf8e44350548f68bf1de629c5d9528","navArea":null,"referringServlet":"Hotel_Review","highestMetaPrice":0,"lowestMetaPrice":0,"additionalPartner":false,"highestMetaPriceDisplay":0,"roomsToVerify":[],"clazz":null},"summary":null,"unavailable":true,"metaOffers":[],"mismatchCheckModel":null,"totalMediaCount":0,"hotelPhotos":[],"noticeHeaderMessage":null,"moreProviders":null,"lowestPricePartner":null,"showAllRooms":true,"isMetaCheaper":false,"isBookingLessThanOrEqualToMeta":null,"avgHistoricalPrice":0.0,"avgHistoricalDisplayPrice":null,"expressBookState":null,"highestMetaPrice":-1,"lowestMetaPrice":-1,"highestMetaPriceDisplay":-1,"hotelName":"Motel 168 Nanjing Zhongshan East Road Jiefang Road","hasSpecialTimeOfStayTaxes":false,"trackingTree":null,"trackingTreeId":null,"showPriceHoverTooltip":false,"trackingContext":"eyJzdGF0ZSI6IkhPVEVMX0FVQ1RJT04iLCJwIjoiSFJfTWFpbkNvbW1lcmNlIiwiaWRzIjp7IkJGSyI6IjdmYWY4ZTQ0MzUwNTQ4ZjY4YmYxZGU2MjljNWQ5NTI4IiwiQUlLIjoiYTZkZjQ5NmZlZDVkNDg1ODg4Y2JhNDdhZGRiOTBlMDYifSwiZW50cnlTZXJ2bGV0IjoiSG90ZWxfUmV2aWV3In0=","cheaperPricesExist":false,"enableLPF":false,"priceDropPercent":0,"canExpandRooms":false,"expandRoomsToAllPartners":false,"roomSelectionKey":null,"useSupplierDirectTreatment":false,"isSupplierDirect":false,"showProviderSeparator":false,"clazz":null,"seeMoreMessage":null,"seeMoreIFrameMessage":null,"isPricelineCom":false,"isPriceDrawerEnabled":false,"isMetaMarketingLandOnBookingFormEnabled":false}, "ibAvailability": false, "metaAvailability": false, "topOfferIsIB": false, "numHacTries": 1, "checkIn": "23/12/2018", "checkOut": "24/12/2018", "lowestPrice": null, "hasDates": true, "hacComplete": false, "contentIdMappings": {}, "pollingEnabled": false, "preventScroll": false, "offerClickToken": null, "conditionalUpdate": false, "mightGetRooms": false, "divClasses": "ppr_rup ppr_priv_resp_hr_room_grid", "singlePartnerRoomGridWidget": {"containerAttributes":null,"scriptFlags":null,"containerClass":null,"widget":{"moduleList":["handlers","tracking"],"divClasses":"prw_rup prw_ibex_room_grid_responsive","js":{"handlers":"(ta.prwidgets.getjs(this,'handlers'))","tracking":"(ta.prwidgets.getjs(this,'tracking'))"},"dust":{"sub_header":"ibex_room_grid_responsive__sub_header"},"name":"ibex_room_grid_responsive","template":"ibex_room_grid_responsive__widget"}}, "multiPartnerRoomGridWidget": null, "mismatchMessage": {"containerAttributes":null,"scriptFlags":null,"containerClass":null,"widget":{"moduleList":["handler"],"divClasses":"prw_rup prw_ibex_mismatch_message","js":{"handler":"(ta.prwidgets.getjs(this,'handler'))"},"dust":{},"name":"ibex_mismatch_message","template":"ibex_mismatch_message__widget"}}, "maxRoomsToShow": 300, "isTablet": false, "roomGridRowWidget": {"containerAttributes":null,"scriptFlags":null,"containerClass":null,"widget":{"moduleList":[],"divClasses":"prw_rup prw_ibex_room_grid_row_responsive","js":{},"dust":{"amenities":"ibex_room_grid_row_responsive__amenities","occupancy":"ibex_room_grid_row_responsive__occupancy","condition_col":"ibex_room_grid_row_responsive__condition_col","price_text":"ibex_room_grid_row_responsive__price_text","reservation_col":"ibex_room_grid_row_responsive__reservation_col"},"name":"ibex_room_grid_row_responsive","template":"ibex_room_grid_row_responsive__widget"}}, "mismatchMessageLightbox": null, "deviceInfo": "OtherOS OtherBrowser", "bookOnTripAdvisor": "จองบน <img class=\"ibHeaderImg\" alt=\"TripAdvisor\" src=\"https:\/\/static.tacdn.com\/img2\/branding\/rebrand\/TA_logo_primary.png\"\/>"}
รับคำตอบอย่างรวดเร็วจากพนักงานของ Motel 168 Nanjing Zhongshan East Road Jiefang Road และผู้ที่เคยใช้บริการ

value: Tripadvisor, Inc. is an American online travel company that operates a website and mobile app with user-generated content and a comparison shopping website.


text:
Patent US20050269629 - Fin field effect transistors and methods of fabricating the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin....http://www.google.com/patents/US20050269629?utm_source=gb-gplus-sharePatent US20050269629 - Fin field effect transistors and methods of fabricating the sameAdvanced Patent SearchPublication numberUS20050269629 A1Publication typeApplicationApplication numberUS 11/084,922Publication dateDec 8, 2005Filing dateMar 21, 2005Priority dateMar 23, 2004Also published asUS7332386Publication number084922, 11084922, US 2005/0269629 A1, US 2005/269629 A1, US 20050269629 A1, US 20050269629A1, US 2005269629 A1, US 2005269629A1, US-A1-20050269629, US-A1-2005269629, US2005/0269629A1, US2005/269629A1, US20050269629 A1, US20050269629A1, US2005269629 A1, US2005269629A1InventorsChul Lee, Min-Sang Kim, Dong-gun Park, Choong-ho Lee, Chang-Woo Oh, Jae-Man Yoon, Dong-won Kim, Jeong-Dong Choe, Ming Li, Hye-Jin ChoOriginal AssigneeChul Lee, Min-Sang Kim, Park Dong-Gun, Lee Choong-Ho, Chang-Woo Oh, Jae-Man Yoon, Kim Dong-Won, Jeong-Dong Choe, Ming Li, Hye-Jin ChoExport CitationBiBTeX, EndNote, RefManReferenced by (16), Classifications (25), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetFin field effect transistors and methods of fabricating the sameUS 20050269629 A1Abstract A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin. Images(14) Claims(25)
1. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a gate electrode covering sides and a top of a portion of the fin; a gate insulation layer between the gate electrode and the fin; and a source region and a drain region in the fin adjacent to opposite sides of the gate electrode, wherein the source region of the fin has a different width than the drain region of the fin. 2. The FinFET of claim 1, wherein: the source region of the fin has a smaller width than the drain region of the fin. 3. The FinFET of claim 1, wherein a portion of the fin under the gate electrode has an abrupt change in width. 4. The FinFET of claim 3, wherein the abrupt change in width of the fin under the gate electrode forms sidewalls of the fin having a T-shape. 5. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a gate electrode covering sides and a top of a portion of the fin; a source region and a drain region in the fin adjacent to opposite sides of the gate electrode, wherein the drain region of the fin has a greater width than the source region of the fin; and a channel region in the fin between the source region and the drain region, wherein an impurity concentration of the channel region that is adjacent to the drain region is higher than the impurity concentration of the channel region that is adjacent to the source region. 6. The FinFET of claim 5, wherein a portion of the fin under the gate electrode has an abrupt change in width. 7. The FinFET of claim 6, wherein the abrupt change in width of the fin under the gate electrode forms sidewalls of the fin having a T-shape. 8. The FinFET of claim 5, wherein the fin tapers off from the drain region to the source region. 9. The FinFET of claim 5, wherein: the channel region adjacent to the source region has about the same impurity concentration as the substrate, and the channel region adjacent to the drain region has a higher impurity concentration than the substrate. 10. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a pair of gate electrodes, each of the gate electrodes covering sides and a top of adjacent portions of the fin; a gate insulation layer between the pair of gate electrodes and the fin; and a common drain region in the fin between the pair of gate electrodes; and a pair of source regions in the fin, each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region, wherein the source region of the fin has a different width than the common drain region of the fin. 11. The FinFET of claim 10, wherein: the source regions of the fin have a smaller width than the common drain region of the fin. 12. The FinFET of claim 10, wherein a portion of the fin under each of the pair of gate electrodes has an abrupt change in width. 13. The FinFET of claim 10, wherein the fin tapers off in width from the common drain region to the source regions. 14. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a pair of gate electrodes, each of the gate electrodes covering sides and a top of adjacent portions of the fin; a gate insulation layer between the pair of gate electrodes and the fin; and a common drain region in the fin between the pair of gate electrodes; a pair of source regions in the fin, each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region; and a channel region in the fin between the common drain region and the source regions, wherein the channel region adjacent to the common drain region has a higher impurity concentration than the channel region adjacent to the source regions. 15. The FinFET of claim 14, wherein: the source regions of the fin have a smaller width than the common drain region of the fin. 16. The FinFET of claim 15, wherein a portion of the fin under each of the pair of gate electrodes has an abrupt change in width. 17. The FinFET of claim 14, wherein the fin tapers off in width from the common drain region to the source regions. 18. The FinFET of claim 14, wherein: the channel region adjacent to the source region has about the same impurity concentration as the substrate, and the channel region adjacent to the common drain region has a higher impurity concentration than the substrate. 19. A method for fabricating a fin field effect transistor (FinFET), the method comprising: providing a substrate; forming a fin on the substrate and extending laterally along and vertically away from the substrate, wherein a first region of the fin has a first fin width and a second region of the fin has a second fin width, wherein the second fin width is larger than the first fin width; forming a gate insulation layer on a portion of the fin; and forming a gate electrode on the gate insulating layer and covering sides and a top of a portion of the fin. 20. The method of claim 19, wherein forming a fin comprises: patterning the substrate to form the fin therefrom, wherein the formed fin has the second fin width; forming a mask pattern on the fin; oxidizing a sidewall of the fin to form a sacrificial oxide layer while using the mask pattern as an oxidation barrier layer; removing the sacrificial oxide layer to form the first region of the fin having the first fin width; and removing the mask pattern to expose the second region of the fin having the second fin width. 21. The method of claim 20, wherein providing a substrate comprises: providing a support substrate; forming a buried insulating layer on the support substrate; forming a semiconductor layer on the buried insulating layer, and wherein patterning the substrate to form the fin therefrom comprises patterning the semiconductor substrate to form the fin therefrom. 22. The method of claim 19, wherein: providing a substrate comprises providing a semiconductor substrate; and forming a fin on the substrate comprises patterning the semiconductor substrate to form the fin therefrom, and further comprising forming a device isolation layer on the semiconductor substrate and the fin. 23. The method of claim 22, wherein forming a device isolation layer comprises: forming a liner layer on the semiconductor substrate and the fin; forming an insulation layer on the liner layer; recessing a portion of the insulation layer to expose the liner layer; and recessing the liner layer to partially expose sidewalls of the fin. 24. A method for fabricating a fin field effect transistor (FinFET), the method comprising: providing a substrate; forming a fin on the substrate and extending laterally along and vertically away from the substrate, wherein a first region of the fin has a first fin width and a second region of the fin has a second fin width, wherein the second fin width is larger than the first fin width; forming a gate insulation layer on a portion of the fin; forming a gate electrode on the gate insulating layer and covering sides and a top of a portion of the fin; implanting impurities of a first conduction type into one side of the gate electrode; and implanting impurities of a second conduction type into the fin, using the gate electrode as an ion implanting mask, to form a source region in the first region, to form a drain region in the second region, and to form a first diffusion layer in a channel region adjacent to the drain region, wherein the source and drain regions define the channel region. 25. The method of claim 24, wherein: implanting impurities of a second conduction type into the fin comprises implanting the second conduction type impurities with a shorter lateral diffusion distance than a lateral diffusion distance of the first conduction-type impurities. Description
RELATED APPLICATION This application claims the benefit of and priority to Korean Patent Application No. 10-2004-0019711, filed Mar. 23, 2004, and to Korean Patent Application No. 10-2004-0071798, filed Sep. 8, 2004, the disclosures of which are hereby incorporated herein by reference. FIELD OF THE INVENTION The present invention relates to semiconductor devices, and, more particularly, a fin field effect transistor with a vertical channel and related methods of fabricating fin field effect transistors. BACKGROUND OF THE INVENTION The continuing trend to fabricate semiconductor devices with smaller device features has led to some difficulties when trying to scale-down transistors that have a horizontal channel (hereinafter referred to as �horizontal channel transistors�). Two difficulties that can arise when trying to scale-down horizontal channel transistors are short channel effect and drain induced barrier lower (DIBL) effect. When a channel length of a transistor is reduced to 50 nanometers or less, the dispersion of device characteristics can become high due to fabrication process variations. When the channel length is 30 nanometers or less, the channel effect and DIBL effect can become so severe that the resulting transistor will operate abnormally. Various different types of transistors have been developed to overcome some of the limitations associated with fabricating horizontal channel transistors. One such transistor is a double gate transistor. The double gate transistor includes a channel that may have a length of 30 nanometers or less, and a single gate on the channel or two gates on opposite sides of the channel. Because a conventional transistor has a gate electrode formed only over a horizontal channel, an electric field is asymmetrically applied to a top and bottom of the channel to prevent the turning on/off of the transistor from being controlled by the gate electrode. In contrast, because a double gate electrode has two gate electrodes on opposite sides of a thin channel, an entire area of the channel is affected by the gate electrode. Thus, when the transistor is turned off, charge flow between a source and a drain may be suppressed to reduce power dissipation and to control the turning on-off of the transistor. A double gate transistor using a damascene gate is disclosed in U.S. Patent Publication No. 2002/0177263 entitled �DAMASCENE DOUBLE-GATE MOSFET WITH VERTICAL CHANNEL REGIONS�, issued to Hussein et al. FIG. 1 is a perspective view of a damascene double gate MOS transistor, such as that disclosed in U.S. Patent Publication No. 2002/0177263. As illustrated in FIG. 1, a transistor 14 includes a silicon layer 10 on an insulator 12 and a gate electrode 28 that extends across the silicon layer 10. A hard mask pattern 18 is on the silicon layer 10, and the gate electrode 28 is on the hard mask pattern 18. A gate insulator 30 is between the gate electrode 28 and a sidewall of the silicon layer 10. A source/drain region 22 is formed in the silicon layer 10 adjacent to opposite sides of the gate electrode 28. As previously discussed, a double MOS transistor with a vertical channel has a narrow silicon layer in which a channel is formed. The gate may thereby exhibit a high controllability for the channel. Because a typical silicon layer has a width ranging from several nanometers to dozens of nanometers, the transistor is often called a fin field effect transistor (hereinafter referred to as �FinFET�) due to its shape. One difficulty in using FinFETs is that threshold voltages can vary considerably depending upon variations in their fabrication processes. Consequently, it can be difficult to control the threshold voltage of the transistor and provide cell uniformity in a high-density memory device. Lowering of the threshold voltage of a transistor can increase the sub-threshold voltage leakage. Leakage current of a transistor results in degradation of the devices made therefrom. For example, leakage current can result in degradation of the data retention characteristics of a DRAM device. Consequently, it can be important to minimize leakage current of, for example, a source region to which a capacitor is connected. A channel concentration can be raised to increase a threshold voltage of the transistor. However, increased threshold voltage can cause a decrease in the turn-on current of the transistor, and increased channel concentration can cause an increase in junction current. Therefore, when such a transistor is used in a DRAM device, the decreased turn-on current can reduce a write margin, and the increased storage node junction leakage can deteriorate a data retention characteristic of the DRAM device. SUMMARY OF THE INVENTION In some embodiments of the present invention, a fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region are in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin. In some further embodiments of the present invention, the source region of the fin has a smaller width than the drain region of the fin. A portion of the fin under the gate electrode can have an abrupt change in width. The abrupt change in width of the fin under the gate electrode can form sidewalls of the fin that have a T-shape. In some other embodiments of the present invention, a FinFET includes a substrate, a fin, a gate electrode, source and drain regions in the fin, and a channel region in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top portion of the fin. The source region and the drain region in the fin are adjacent to opposite sides of the gate electrode. The drain region of the fin has a greater width than the source region of the fin. The channel region in the fin is between the source region and the drain region. An impurity concentration of the channel region that is adjacent to the drain region is higher than the impurity concentration of the channel region that is adjacent to the source region. In some further embodiments of the present invention, a portion of the fin under the gate electrode has an abrupt change in width. The abrupt change in width of the fin under the gate electrode can form sidewalls of the fin that have a T-shape. The fin can taper off from the drain region to the source region. The channel region that is adjacent to the source region can have about the same impurity concentration as the substrate, and the channel region that is adjacent to the drain region can have a higher impurity concentration than the substrate. In some other embodiments of the present invention, a FinFET includes a substrate, a fin, a pair of gate electrodes, a gain insulating layer, a common drain region in the fin, and a pair of source regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. Each of the gate electrodes cover sides and a top of adjacent portions of the fin. The gate insulating layer is between the pair of gate electrodes and the fin. The common drain region in the fin is between the pair of gate electrodes. Each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region. The source regions of the fin have a different width than the common drain region of the fin. In some further embodiments of the present invention, the source regions of the fin have a smaller width than the common drain region of the fin. A portion of the fin under each of the pair of gate electrodes can have an abrupt change in width. The fin can taper off in width from the common drain region to the source regions. In some other embodiments of the present invention, a FinFET includes a substrate, a fin, a pair of gate electrodes, a gain insulating layer, a common drain region in the fin, a pair of source regions in the fin, and a channel region in the fin. The fin is on and extends laterally along and vertically away from the substrate. Each of the gate electrodes cover sides and a top of adjacent portions of the fin. The gate insulating layer is between the pair of gate electrodes and the fin. The common drain region in the fin is between the pair of gate electrodes. Each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region. The channel region in the fin is between the common drain region and the source regions. The channel region adjacent to the common drain region has a higher impurity concentration than the channel region adjacent to the source regions. In some further embodiments of the present invention, the source regions of the fin have a smaller width than the common drain region of the fin. A portion of the fin under each of the pair of gate electrodes can have an abrupt change in width. The fin can taper off in width from the common drain region to the source regions. The channel region that is adjacent to the source region can have about the same impurity concentration as the substrate, and the channel region that is adjacent to the common drain region can have a higher impurity concentration than the substrate. In some other embodiments of the present invention, a method for fabricating FinFET includes providing a substrate. A fin is formed on the substrate and extends laterally along and vertically away from the substrate. A first region of the fin has a first fin width and a second region of the fin has a second fin width, where the second fin width is larger than the first fin width. A gate insulation layer is formed on a portion of the fin. A gate electrode is formed on the gate insulating layer and covers sides and a top portion of the fin. In some further embodiments of the present invention, formation of the fin includes patterning the substrate to form the fin with the second fin width therefrom. A mask pattern is formed on the fin. A sidewall of the fin is oxidized to form a sacrificial oxide layer while using the mask pattern as an oxidation barrier layer. The sacrificial oxide layer is removed to form the first region of the fin having the first fin width. The mask pattern is removed to expose the second region of the fin having the second fin width. In yet some further embodiments of the present invention, providing the substrate includes providing a support substrate and patterning the semiconductor substrate to form the fin therefrom. A buried insulating layer is formed on the support substrate. A semiconductor layer is formed on the buried insulating layer. In yet some further embodiments of the present invention, the substrate comprises a semiconductor substrate. The semiconductor substrate is patterned to form the fin therefrom. A device isolation layer is formed on the semiconductor substrate and the fin. In yet some further embodiments of the present invention, formation of the device isolation layer includes forming a liner layer on the semiconductor substrate and the fin, forming an insulation layer on the liner layer, recessing a portion of the insulation layer to expose the liner layer, and recessing the liner layer to partially expose sidewalls of the fin. In some other embodiments of the present invention, a method for fabricating a FinFET includes providing a substrate. A fin is formed on the substrate and extends laterally along and vertically away from the substrate. A first region of the fin has a first fin width and a second region of the fin has a second fin width, where the second fin width is larger than the first fin width. A gate insulation layer is formed on a portion of the fin. A gate electrode is formed on the gate insulating layer and covers sides and a top portion of the fin. Impurities of a first conduction type are implanted into one side of the gate electrode. Impurities of a second conduction type are implanted into the fin using the gate electrode as an ion implanting mask, and to form a source region in the first region, to form a drain region in the second region, and to form a first diffusion layer in a channel region adjacent to the drain region. The source and drain regions define the channel region. In some further embodiments of the present invention, the impurities of the second conduction type are implanted into the fin with a shorter lateral diffusion distance than a lateral diffusion distance of the first conduction-type impurities.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a conventional vertical double gate transistor. FIG. 2 is a perspective view of a FinFET according to a first embodiment of the present invention. FIG. 3 is a graph that illustrates an exemplary threshold voltage of the FinFET shown in FIG. 2. FIG. 4 is a top plan view of a portion of a DRAM cell array with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. FIGS. 5, 6, 7A, 8A, and 9A are top plan views that illustrate a method of fabricating a DRAM cell array with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. FIGS. 7B, 7C, 7D, 8B, and 9B are cross-sectional views that illustrate a method of fabricating the DRAM cell with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. FIGS. 10A and 10B are top plan views of alternate embodiments of the FinFET of FIG. 2 in accordance with some other embodiments of the present invention. FIG. 11 is a top plan view of a FinFET according to a second embodiment of the present invention. FIGS. 12A and 12B are graphs that illustrate doping concentrations and an energy band that vary along a line II-II′ in FIG. 11. FIGS. 13A and 13B are graphs that illustrate energy band shapes during operation of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIGS. 14A and 14B are top plan views of alternate embodiments of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIG. 15 is a perspective view of an alternate embodiment of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIGS. 16A through 16D are diagrams that illustrate methods of fabricating the FinFET of FIG. 15 in accordance with some embodiments of the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like reference numbers signify like elements throughout the description of the figures. It will be understood that when an element or layer is referred to as being �on,� �connected to,� or �coupled to� another element or layer, it can be directly on, connected, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being �directly on,� �directly connected to,� or �directly coupled to� another element or layer, there are no intervening elements or layers present. As used herein, the term �and/or� includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout the description. It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention. Furthermore, relative terms, such as �lower� or �bottom� and �upper� or �top� may be used herein to describe one element's relationship to another elements as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the �lower� side of other elements would then be oriented on �upper� sides of the other elements. The exemplary term �lower� can, therefore, encompass both an orientation of �lower� and �upper,� depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as �below� or �beneath� other elements would then be oriented �above� the other elements. The exemplary terms �below� or �beneath� can, therefore, encompass both an orientation of above and below. Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from an implanted to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms �a,� �an,� and �the� are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms �comprises� and/or �comprising,� when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. FIG. 2 is a perspective view of a FinFET in accordance with a first embodiment of the present invention. The FinFET includes a fin 200 that is on a substrate, such as the substrate 12 of FIG. 1, and that extends laterally along the substrate and vertically away from the substrate. Accordingly, fin 200 may be referred to as vertically extending fin 200. The fin 200 includes a first region having a first fin width W1 and a second region having a second fin width W2 that is larger than the first fin width W1. A gate electrode 210 covers sides and a top of a portion of the fin 200. A gate insulation layer 208 is between the gate electrode 210 and the fin 200. A source region 202 s and a drain regions 202 d are formed in the fin 200 adjacent to opposite sides of the gate electrode 210. The source region 202 s is formed in the first region of the fin 200, and the drain region 202 d is formed in the second region 202 s of the fin 200. The gate electrode 210 covers a portion of the fin 200 that includes a boundary region between the first and second regions. The portion of the fin 200 that is covered by the gate electrode 210 corresponds to a channel region of the FinFET. The channel region is between the source region 202 s and the drain regions 202 d. As shown, a portion of the fin 200 under the gate electrode 210 can have an abrupt change in width, and sidewalls of the fin 200 may have a T-shape. Instead of having an abrupt change in width, the fin 200 may taper off from the drain region 202 d to the source region 202 s. FIG. 3 is a graph of an exemplary threshold voltage of the FinFET of FIG. 2 in accordance with some embodiments of the present invention. In the graph, a transversal axis denotes a fin width and a longitudinal axis denotes a threshold voltage. As illustrated in this figure, as the fin width decreases below a determined width, the threshold voltage rapidly decreases. For example, when the fin width is W1, a threshold voltage Vth1 is located where the rate of change (ΔVth/ΔW) is high, and where a small change in the fin width can significantly change the threshold voltage. When the fin width is W2, a threshold voltage Vth2 is located where the rate of change is low, and where a relatively larger change in fin width, such as due to fabrication process variations, does not cause a significant change in the threshold voltage. Accordingly, it can be preferable for a FinFET to have a fin width that is of sufficient width such that small changes in the width do not cause significant changes in the threshold voltage. A FinFET in accordance with some embodiments of the present invention has two different fin widths, and can include a larger fin width region and a smaller fin width region. A source region can be formed in the small fin width region, which may lower source junction leakage current and suppress occurrences of soft error. Accordingly, the threshold voltage may be made less sensitive to fabrication process variations without increasing the fin width. The FinFET may be used in DRAM devices because the source junction leakage current can be low and the generation of soft errors can be suppressed. A FinFET can operate when the gate overlapped fin inside is fully depleted. As a result, the FinFET can have a much higher current driving efficiency than a typical planar transistor. When the fin that is adjacent to a source is wide and the fin that is adjacent to a drain is narrow, the driven current may be effectively increased with little or no increase in drain current. FIG. 4 is a top plan view showing a portion of a DRAM cell array with the FinFET shown in FIG. 2 in accordance with some embodiments of the present invention. Referring to FIG. 4, a DRAM cell array includes a plurality of fins 112 that are formed on a substrate. The substrate may be a SOI substrate or a bulk semiconductor substrate. If the substrate is a SOI substrate, the fins are disposed on an insulation layer. If the substrate is a bulk semiconductor substrate, the fins may be formed by etching the bulk semiconductor substrate. The fin 122 includes a first region 112 a having a first fin width and a second region 112 b having a second fin width. The first region 112 a is adjacent to opposite sides of the fin, and the second region 112 b is between the first regions 112 a. A pair of gate electrodes 10 p cross over the respective fins 112, so that each of the gate electrodes 10 p cover sides and a top of adjacent portions of the fins 112. Each gate electrode 110 overlaps an upper part of a boundary region of the first region 112 a and the second region 112 b. Source region 112 s are formed in the fins 112 and are adjacent to a side of a different one of the pair of gate electrodes 110 and opposite to a common drain region 112 d. The common drain region 112 d is formed in the fin 112 between the gate electrodes 110. Although not shown in this figure, a capacitor is connected to the source region 112 s and a bitline is connected to the common drain region 112 d. A channel region can be defined in each of the fins 112 between the source region and the source regions 112 s and the common drain regions 112 d. The channel region can include two channel portions having different threshold voltages. The source region 112 s can be formed in the smaller width region of the fins 112, and the drain regions 112 d can be formed in the larger width region of the fins 112, which may lower source junction leakage current and suppress the generation of soft errors. Because, the fin width is larger along a portion of a gate electrode 110, a threshold voltage of the FinFETs may be increased which may enhance its controllability and avoid lowering of the drain current. The FinFETs of FIGS. 2 and 4 may be formed on a SOI substrate or a bulk silicon substrate, and may be formed using a conventional gate process or a damascene gate process, but modified as described herein in accordance with some embodiments of the present invention. FIGS. 5, 6, 7A, 8A, and 9A illustrate methods of fabricating a DRAM cell array in accordance with the first embodiment of the present invention. FIGS. 7B, 7C, 7D, 8B, and 9B are cross-sectional views that illustrate a method of fabricating the DRAM cell with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. Referring to FIG. 5, a substrate is provided, and a plurality of fins 52 are formed on the substrate. The fins 52 are formed on the substrate and extend laterally along and vertically away from the substrate. The substrate may be a SOI substrate or a semiconductor bulk substrate. In case of a SOI substrate, the fins 52 are formed on an insulation layer. In case of a semiconductor bulk substrate, the fins 52 can be on and extend away from the substrate. A semiconductor layer of the SOI substrate or the semiconductor bulk substrate may be formed from silicon, germanium, silicon germanium, germanium silicon germanium and/or combinations thereof. Referring to FIG. 6, a mask pattern 53 is formed on the substrate and crossing over center portions of the fins 52. Using the mask pattern 53 as an oxidation barrier layer, the fin 52 is thermally oxidized to form a sacrificial oxide layer 54 on sidewalls of the fins 52. Through the thermal oxidation, a layer of the exposed portion of the fins 52 is removed so that the width of the exposed portions of the fins 52 is reduced. Thus, a thermal oxidation layer is formed on first regions 52 a on both sides of the fins 52, and is not formed on a second region 52 b between the first regions 52 a. The first region 52 a has a first fin width, and the second region 52 b has a second fin width that is greater than the first fin width (i.e., the second fin width is the initial fin width of the fins 52). Referring to FIG. 7A, the mask pattern 53 and the sacrificial oxide layer 54 are removed to form a first region 52 a at both sides of the fins 52 and to expose the second region 52 b between the first regions 52 a. The first region 52 a has a first fin width, and the second region 52 b has a second fin width which larger than the first fin width. FIG. 7B illustrates a cross-sectional view of fins 52 formed on an SOI substrate. The vertically extending fins 52 are on a buried insulation layer 51, and on a support substrate 50. In FIG. 7B, the fins 52 are formed on a bulk substrate and extend vertically away from the substrate. When the fins 52 are formed on an SOI substrate, the fins 52 are formed on an insulation layer 51 that is isolated from the substrate. When the fins 52 are formed over a bulk substrate, the fins 52 are interconnected to the substrate. Thus, when a FinFET is formed using a bulk substrate, a device isolation layer 55 is formed between the fins 52 to isolate the fins 52 from one another, as illustrated in FIG. 7D. Although not shown in the figures, a conventional gate process or a damascene gate process may be applied to form a gate electrode on and crossing over the fins 52. Some other methods for isolating fins that are formed on a bulk substrate will now be described hereinafter. Referring to FIGS. 8A and 8B, after the first and second regions of the fins 52, a liner layer 56 is conformally formed on the surface of the substrate and the fins 52. The liner layer 56 may include a material having an etch selectivity with respect to the fins 52. For example, the liner layer 56 may include silicon nitride. An insulation layer 58 is formed on the liner 56. The insulation layer 58 may include a material having an etch selectivity with respect to the liner 56 and the substrate, may have good gap-filling efficiency. For example, the insulating layer 58 may include PECVD, HDPCVD, and/or P3-TEOS. Referring to FIGS. 9A and 9B, the insulation layer 58 is recessed to expose the liner layer 56. The exposed liner layer 56 is recessed to expose at least a portion of the sidewalls of the fins 52. A device isolation layer, which includes the recessed insulation layer 58 and the liner layer 56, is formed on a region between the fins 52 to isolate the respective fins 52. Impurities can be implanted into the fins 52 to form a channel diffusion layer. The implantation of the impurities may be carried out using oblique ion implantation. The channel diffusion layer may be formed by implanting boron or boron fluoride at a dose of 1011 atoms/cm2 to about 1014 atoms/cm2 and at a concentration of 1015 atoms/cm3 to about 1019 atoms/cm3. Impurities may be further implanted vertically into a bottom of an exposed portion of the fins 52 according to a projection range (Rp). As a result, the impurities diffused from the channel diffusion layer may overlap the vertically implanted impurities to form an anti-punch-through diffusion layer of a high concentration. The anti-punch-through diffusion layer inhibits punch-through from occurring through a bottom of a channel diffusion layer which is not readily controlled by a gate. The channel diffusion layer and the anti-punch-through diffusion layer may be formed after formation of the fins shown in FIG. 5, or in the step of FIG. 7D in which a sidewall of the fins is partially recessed and a device isolation layer is formed. When the fins 52 are formed on a SOI substrate, formation of an anti-punchthrough diffusion layer is not needed because an underlying insulation layer can prevent punch-through. Referring to FIGS. 9A and 9B, a gate insulation layer 59 is formed on the exposed sidewall of the fin 52. The gate insulation layer 59 may be made from metal oxide, silicon oxide and/or silicon oxynitride, and may be formed by thermal oxidation or chemical vapor deposition (CVD). A conductive layer is formed on the substrate and the gate insulation layer 59. The conductive layer is patterned to form a gate electrode 60 crossing over the fin 52. As illustrated, because a device isolation layer is disposed between the fins, a width of the gap area is smaller than that of the gap area shown in FIG. 7D. The conductive layer may have a planar top surface. The gate electrode 60 may be formed using a damascene process. More particularly, formation of the gate electrode 60 may include forming a mold layer to cover an entire surface, patterning the mold layer to form an opening exposing the fin 52, forming a gate insulation layer on a surface of the exposed fin 52, and filling the opening with a conductive layer to form the gate electrode 60. The gate electrode 60 overlaps an upper portion of a boundary region of the first and second regions 52 b of the fin 52. Using the gate electrode 60 as an ion implanting mask, impurities are implanted into the fin 52 to form a source region 62 s and a drain region 62 d. FIGS. 10A and 10B are top plan views of alternate embodiments of the FinFET of FIG. 2 in accordance with some other embodiments of the present invention. Referring to FIGS. 10A and 10B, although a width of the gate electrode 110 is constant, the threshold voltage may be controlled by the overlap between the gate electrode 110 and the fin 112. When the gate electrode 110 overlaps more of the first region 112 a than the second region 112 b of the fin 112, the threshold voltage of the transistor decreases. In contrast, when the gate electrode 110 overlaps more of the second region 112 b than the first region 112 a, the threshold voltage of the transistor increases. FIG. 11 is a top plan view of a FinFET according to a second embodiment of the present invention. Similar to the first embodiment of FIG. 2, the FinFET illustrated in FIG. 11 has a vertically extending fin 202. The fin 202 includes a first region having a first fin width and a second region having a second fin width which is larger than the first fin width. A gate electrode 210 crosses over and covers a portion of the fin 202. A gate insulation layer 208 is between the gate electrode 210 and the fin 202. A source region 202 s and a drain region 202 d are formed in the fin 202 and adjacent to opposite sides of the gate electrode 210. The source region 202 s is formed in a first region having a relatively smaller width, and the drain region 202 d is formed in a second region having a relatively larger width. A channel region 201 of the transistor is defined in a portion of the fin 202 that is covered by the gate electrode 210, and is between the source region 202 s and the drain region 202 d. Therefore, the channel region 201 is also disposed through the first and second regions. An impurity diffusion layer 204 of a higher doping concentration than the other channel regions 201 is formed in a channel region adjacent to the drain region 202 d. A conduction type of the impurity diffusion layer 204 is different from that of the source region 202 s and the drain region 202 d. FIGS. 12A and 12B are graphs that illustrate doping concentrations and an energy band that vary along a line II-II′ in FIG. 11. In these figures, a region (1) denotes a source region, a region (2) denotes a channel region, a region (3) is a channel region adjacent to a drain region, and a region (4) denotes a drain region. A doping concentration of the source region (1) and the drain region (4) is higher than a doping concentration of the channel region (2), such as illustrated in these figures. When the FinFET is used in a DRAM cell transistor, the channel region (2) may have a typical p-type well concentration or p-type substrate concentration. P-type impurities such as boron or boron fluoride are additionally implanted into the p-type well or p-type substrate to more heavily dope the channel region (3) adjacent to the drain region. The source region (1) and the drain region (4) are doped with n-type impurities such as phosphorus (P) or arsenic (As). As illustrated in FIG. 12B, an impurity concentration of the channel region (3) adjacent to the drain region is higher than that of the channel region (2) adjacent to the source region. For this reason, a potential barrier Φd is formed between a channel region and a drain region to offer a very advantageous characteristic to the FinFET according to the present invention. FIG. 13A and FIG. 13B are graphs that illustrate energy band shapes during operation of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIG. 13A illustrates the state that charges are stored in a storage capacitor of a memory cell in which the storage capacitor is connected to the source region 202 s and a bitline is connected to the drain region 202 d. The impurity diffusion layer 204 produces a potential barrier Φd in a channel region (3) adjacent to the drain region 202 d. Thus, while the transistor is turned off, the potential barrier Φd prevents electrons from flowing from the drain region (4) to reduce a transistor off leakage. FIG. 13B illustrates a turn-on state of a transistor in which Vcc is applied to the drain region 202 d through the bitline of a memory cell. Since the potential barrier Φd is disposed around a drain region of a high voltage level while a transistor is turned on, a peak of Φd is at a level which is Φd lower than a channel of the source side. Accordingly, there is a rare influence on the flow of electrons from the source region (1) to the drain region (4). Thus, the transistor has a low threshold voltage depending on a channel region (2) adjacent to the source region. As previously explained, the FinFET according to the second embodiment of the present invention may have a high threshold voltage while being turned off, so that the off leakage is low. The FinFET may also have a low threshold voltage while being turned on, so that a transistor on current is low. Because a doping concentration of the channel region that is adjacent to the source region is low, a junction leakage between a source region and a channel may be suppressed. As shown in FIG. 11, the boundary region of the first region and the second region is covered by the gate electrode 210. In accordance with some embodiments of the present invention, the FinFET may include a fin that tapers off from a drain region 302 d to a source region 302 s (see FIG. 14A), or it may have a fin that has a larger width as it extends toward the drain region 312 d than as it extends toward the source region 212 s (e.g., FIG. 14B). FIG. 15 is a perspective view of an alternate embodiment of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. Referring to FIG. 15, a fin 300 tapers down from a drain region 302 d to a source region 302 s. Accordingly, in contrast to the fin 200 of FIG. 11 that has an abrupt change in width, with an associated T-shape sides, in the channel region 201, the fin 300 shown in FIG. 15 does not have an abrupt change in width in a channel region 301. As illustrated in this figure, the fin 300 is on and extends away from a substrate. A gate electrode 310 crosses over the fin 300 and is on sidewalls and a top surface of a portion of the fin 300. A gate insulation layer 308 is between the gate electrode 310 and the fin 300. The source region 302 s and the drain region 302 d are formed in the fin 300 and are adjacent to opposite sides of the gate electrode 310. The fin 300 becomes increasingly wider from the source region 302 s to the drain region 302 d. Because the cross-sectional area of the fin 300 in the source region 302 s is small, the junction leakage is decreased. Because the area of the fin 300 in the drain region 302 d increases, the transistor on current increases. The channel region 301 is defined in the fin 300 in a portion that is covered by the gate electrode 310 and between the source region 302 s and the drain region 302 d. An impurity concentration of a portion of the channel region 301 that is adjacent to the drain region 302 d is higher than a portion of the channel region 301 that is adjacent to the source region 302 s. Accordingly, the impurity concentration of the channel region 301 can be lowered to increase the on current of the transistor, while a high-concentration diffusion layer 304 that is adjacent to the drain region 302 d can inhibit electrons from flowing from the drain region 302 d to the source region 302 s. Consequently, the channel region 301 may be maintained at the initial impurity concentration of the substrate without forming a channel diffusion layer. FIG. 16A through FIG. 16D are diagrams that illustrate methods of fabricating the FinFET of FIG. 15 in accordance with some embodiments of the present invention. Referring to FIG. 16A, a vertically extending fin 300 is formed on a semiconductor substrate. As was described above, the fin 300 may be defined using a device isolation layer and etching a semiconductor bulk substrate, and/or it may be formed on a buried oxide layer and isolated by patterning a silicon layer of a SOI substrate. The fin 300 can taper off in width from one end to another, such as shown in FIG. 15, or it may have an abrupt change in width, such as shown in FIG. 11. Alternatively, the fin 300 may have an asymmetry taper shape (see FIG. 14A) or it may have a central region that is narrower than end portions of the fin 300 (see FIG. 14B). Referring to FIG. 16D, a gate insulation layer 308 is formed on the fin 300. A gate electrode 310 is formed on the fin and covering sidewalls and a top surface of a portion of the fin 300. A thick insulation layer may be formed on the top surface of the fin 300 between the gate electrode 310 and the top surface of the fin 300. When the gate electrode 310 is on sidewalls and a top surface of the fin 300, a channel may be formed through three faces of the fin 300. When a thick insulation layer is between the gate electrode 310 and a top surface of the fin 300, a channel may be formed in a portion of the fin 300 that is under the gate electrode 310. Referring to FIG. 16C, impurities of a first conduction type are implanted into the fin 300 using the gate electrode 310 as a mask, and forming a diffusion layer 303 of the first conduction type. The impurities of the first conduction type are implanted into a wider portion of a fin 300, i.e., a portion where a drain of the transistor is to be formed (which will be used as a bitline-connected area in a DRAM cell array). The impurities of the first conduction type have the same conduction type as initial impurities of the fin 300. For example, in a DRAM device that uses NMOS transistors and a p-type substrate or a p-type well, the impurities of the first conduction type may be p-type impurities such as boron or boron fluoride. The diffusion layer 303 of the first conduction type may be laterally diffused to a lower portion of the gate electrode 310. Referring to FIG. 16D, using the gate electrode 310 as an ion implanting mask, impurities of a second conduction type are implanted into the fin 300 to form a source region 302 s and a drain region 302 d in the fin 300 on opposite sides of the gate electrode 310. The source region 302 s is in a narrow portion of the fin 300, and the drain region 302 d is in a wider portion of the fin 300. The impurities of the second conduction type may be phosphorus or arsenic. The impurities of the second conduction type form the drain region 302 d by inverting the first conduction type of the diffusion layer 303. The lateral diffusion distance of the first conduction type impurities can be longer than that of the second conduction type impurities. The diffusion layer 304 of the first conduction type may be in the fin 300 adjacent to the drain region 302 d. The channel region 301 is defined by the source region 302 s and the drain region 302 d. A portion of the fin 300 that is adjacent to the drain region 302 d has a higher impurity concentration than the portion of the fin 300 that is adjacent to the source region 302 s. The operations for forming the first conduction type diffusion layer and the second conduction type diffusion layer can be interchanged. The first conduction type diffusion layer can be subjected to more thermal oxidation than the second conduction type diffusion layer to control the associated diffusion distances. As was explained with reference to FIGS. 9A and 9B, when a plurality of the fins 300 are used in FinFETs in a DRAM device, a device isolation layer can be used to isolate the fins 300. An impurity-implanting dose of the second embodiment can be lower than that of the first embodiment, and a channel diffusion layer may, or may not, be used as was previously explained. An anti-punch-through diffusion layer may be formed on a lower portion of the fin 300. A pair of gate electrodes may be formed on, and crossing over, the fin 300. Impurities of a first conduction type can be implanted into the fin 300 between gate electrodes to form a diffusion layer of the first conduction type. Using the gate electrodes as an ion implanting mask, impurities are implanted into the fin 300 to form a common drain region 302 d in the fin 300 between the gate electrodes 310 and to form a source region 302 s in the fin 300 on opposite sides adjacent to the common drain region 302 d. A bitline can be connected to the common drain region 302 d and a storage capacitor can be connected to the source region 302 s. In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7102181 *Apr 22, 2005Sep 5, 2006International Business Machines CorporationStructure and method for dual-gate FET with SOI substrateUS7312504 *Jul 1, 2005Dec 25, 2007Hynix Semiconductor Inc.Transistor for memory device and method for manufacturing the sameUS7323374 *Sep 19, 2005Jan 29, 2008International Business Machines CorporationDense chevron finFET and method of manufacturing sameUS7906802 *Jan 28, 2009Mar 15, 2011Infineon Technologies AgSemiconductor element and a method for producing the sameUS8048723Dec 5, 2008Nov 1, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Germanium FinFETs having dielectric punch-through stoppersUS8106459May 6, 2008Jan 31, 2012Taiwan Semiconductor Manufacturing Company, Ltd.FinFETs having dielectric punch-through stoppersUS8114723 *Jun 7, 2010Feb 14, 2012International Business Machines CorporationMethod of forming multi-high-density memory devices and architecturesUS8227301 *Dec 9, 2009Jul 24, 2012International Business Machines CorporationSemiconductor device structures with floating body charge storage and methods for forming such semiconductor device structuresUS8263462 *Dec 31, 2008Sep 11, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Dielectric punch-through stoppers for forming FinFETs having dual fin heightsUS8293616Nov 13, 2009Oct 23, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Methods of fabrication of semiconductor devices with low capacitanceUS20100087037 *Dec 9, 2009Apr 8, 2010International Business Machines CorporationSemiconductor device structures with floating body charge storage and methods for forming such semiconductor device structuresUS20120299110 *Jul 31, 2012Nov 29, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin HeightsUS20130207079 *Feb 9, 2012Aug 15, 2013International Business Machines CorporationTapered Nanowire Structure With Reduced Off CurrentEP2446466A2 *Jun 2, 2010May 2, 2012International Business Machines CorporationFet with replacement gate structure and method of fabricating the sameWO2007035788A2 *Sep 19, 2006Mar 29, 2007Jochen BeintnerDENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAMEWO2010032174A1 *Sep 10, 2009Mar 25, 2010Nxp B.V.Fin field effect transistor (finfet)* Cited by examinerClassifications U.S. Classification257/327, 257/E21.336, 257/E21.703, 438/157, 257/E29.279International ClassificationH01L21/00, H01L21/20, H01L21/84, H01L31/062, H01L29/786, H01L21/265, H01L29/76, H01L21/336, H01L31/119, H01L29/94, H01L31/113Cooperative ClassificationH01L21/845, H01L29/78624, H01L29/785, H01L21/26513, H01L29/66795European ClassificationH01L21/84F, H01L29/66M6T6F16F, H01L29/786B4B2, H01L29/78SLegal EventsDateCodeEventDescriptionJul 29, 2011FPAYFee paymentYear of fee payment: 4Jun 10, 2008CCCertificate of correctionAug 12, 2005ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, CHUL;KIM, MIN-SANG;PARK, DONG-GUN;AND OTHERS;REEL/FRAME:016635/0678;SIGNING DATES FROM 20050315 TO 20050316RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

value: Google Patents is a search engine from Google that indexes patents and patent applications.


text:
For the promotion of rigour and rationality: Maps lie more than one usually thinks
Maps lie more than one usually thinks
I performed the following experiment with students of mathematics. I showed them a map of Russia on google and took a point very far to the east (Uelen, a village in the Chukotsky District next to the Bering Sea) and a point very far to the west (Venekyulya, a region in the Leningrad Oblast, at the border with Estonia). The distance between Uelen and Venekyulya is, roughly, the largest distance between two points in Russia, which is about 6000 km. I asked the students to draw a path between Uelen and Venekyulya whose length is 6000 km. Some drew the path P1 shown below which is a straight line between Uelen and Venekyulya on the google map. Others, realizing that the map is a projection of a sphere, drew path P2, slightly curved upwards.
When I showed them the actual path (see below), they were all surprised. They thought it was wrong. How can it be that the "straight line path" is so much curved upwards? Well, that's because the distortion of the map increases very rapidly when we move away from the equator.
If I had shown them the actual map, on a sphere, then they would have known what to do: they would have drawn an arc between Uelen and Venekyulya that is part of the unique great circle between them, that is, the circle centered at the Earth's center and containing Uelen and Venekyulya. This arc almost (but not quite) passes from the North Pole. To see this, we need to look at the Earth downwards from the North Pole. The picture then becomes clear and the apparent contradiction is resolved.
(Credits for this image go to https://www.jasondavies.com/maps/rotate/)
The moral of this is that we should never believe what we see. (In fact, we should never believe in anything.) Only when we have further evidence, provided by experiment, measurements, or mathematical proof should we "believe" what we see. But then the verb "believe" becomes irrelevant; at this point, we know, we do not believe. We may believe something, temporarily, until further evidence, or we may believe something because someone else we trust has done the work for us. But we should never believe something because our eyes saw it, or because a teacher once told us, or because the government or administration says so, or because a religious, for example, book writes.
One thing that bothers me with some students (and some teachers) of mathematics is that they may be comfortable with the geometry of a 5-dimensional hyperbolic space because they may have seen it in class, passed an exam on it, or doing research on it, but may be uncomfortable with down-to-Earth [sic] geometry, including knowing 2-3 proofs of the Pythagorean theorem. O tempora o mores!
Nobel peace prize for Greek islanders

value: Blogger is an American online content management system (CMS) which enables multi-user blogs with time-stamped entries. Pyra Labs developed it before being acquired by Google in 2003.


text:
Facebook App which generates Mobile Phonenumbers by contest | Veri Girişi | Facebook Pazarlama | Elektronik Pazarlama | Leadler | Pazarlama
Facebook App which generates Mobile Phonenumbers by contest
We are looking for a programmer or team of programmers who is able to program a Facebook app which is a competition to win a great price. We want to motivate young people (age of 16-30) to ask they're friends in Facebook to give us they're mobile phone number and e-mail adress. Every person, who is able to motivate 3 person, should be in the pot to win. Therefore we also need a database running in the backend which is able to collect the data, this should be programmed as well.
The usability should be very easy, after selecting friends (and adding the own e-mail adress & mobile phone number), the friends should get a message from the sender to support the sender to win a price. After they filled in the required details, they should be able to play it as well and send the competiton to theire friends and so on and on and on... like a viral campaigne.
Design Guidelines and Translation into german will be send and made by me.
Beceriler: Veri Girişi, Facebook Pazarlama, Elektronik Pazarlama, Leadler, Pazarlama
Daha fazlasını gör: young programmers, we are looking for a programmer team, the design pot, programmers competition, programmer contest, programmer competition, program competition, price of app, need programmers for app, need a translation app, mobile design contest, marketing in facebook, looking for young programmers, looking for facebook app, in need of app programmers, in need of app programmer, get a phone number for support, get a app programmer, facebook as marketing, e mail programmer, contest for internet marketing, ask programmers, facebook support team, mobile phone price, mobile app programmers
Proje NO: #755940
Bu iş için 2 freelancer ortalamada $213 teklif veriyor
Privat Project for morethanathread ($30-250 USD)
Website: Get ringtone for a tweet_v2 ($250-750 USD)
Swiss Twitter Followers ($30-250 USD)


text:
Arrowmounts Universal Flat Wall Mount for 23- to 32-inch LED/LCD TVs AM-F3220B | Overstock.com
Arrowmounts Universal Flat Wall Mount for 23- to 32-inch LED/LCD TVs AM-F3220B
$18.99 Compare $31.93 Save
$12.94 (41%)
Item #: 13441219
Mount your 23-inch to 32-inch flat screen TV close to the wall with this mount from Arrowmounts. This mount is compatible with all hole patterns, including VESA standard and features a heavy-gauge steel construction....more
Sonax LM-1350 Wall Mount for Flat Panel Display Today $57.59 Arrowmounts Full Motion Articulating Wall Mount for 23-40-inch LED/LCD TVs AM-P19B Today $44.99 Compare $87.04 Save 48% (14) Mount-It! Articulating 17-37 LED/ LCD TV Wall Mount Today $27.99 (124) Mustang MV-TILT2B Flat Panel TILT 23 to 40-inch Wall Mount Today $42.99 AVF Nexus Eco-Mount ESL822B Tilt & Turn TV Mount Today $121.99 Pyle 23 to 50-inch Flat Panel TV Tilting Wall Mount Today $44.40 Compare $71.85 Save 38% (42) Arrowmounts Ultra-Slim Tilting Wall Mount for 23" to 42" TVs Today $28.99 Compare $45.76 Save 37% (5) Arrowmounts Ultra-Slim Tilting Wall Mount for TVs 23 to 42-inches Today $23.80 Compare $60.65 Save 61% (3) PyleHome PSW578UT Wall Mount for Flat Panel Display Today $28.99 (15) Windsor 24-inch Shelf Kit with Mahogany Finish Sale $26.99 Was $29.99 Belvedere 36-inch Shelf Kit with Black Finish Sale $31.94 Was $35.49 OmniMount WorldMount 3N1-S Tilt and Pan Flat Panel Wall Mount Today $17.08 Compare $42.17 Save 59% (1) Black Wall Mount Bracket for Flat Panel TVs Today $20.49 (13) Windsor 36-inch Shelf Kit with Mahogany Finish Sale $27.89 Was $30.99 Atlantic Medium Articulating Mount for 10" to 37" Flat Panel TV's Today $36.99 (4) PyleHome PSW710S Mounting Arm for Flat Panel Display Today $34.99 Compare $46.52 Save 25% (68) AltraMount Quick Mount with Two Shelves Today $63.99 Compare $89.75 Save 29% (3) Arrowmounts Tilting Wall Mount for Plasma/LED/LCD TVs from 32 to 52 inches AM-T3252B Today $27.99 Compare $49.95 Save 44% (122) Next Sponsored Links What's This?
23" to 32" Screen Support - 80.00 lb Load Capacity - Steel, Metal - Black
AM-F3220B
LED TV LCD TV Warranty:
Thank you. Your feedback will help us create the best experience for our customers. Arrowmounts Universal Flat Wall Mount for 23- to 32-inch LED/LCD TVs AM-F3220B
Low profile: Installs only 1 inch from wall Lift-and-hook design makes installation fast and easy Compatibility:
http://www.overstock.com/Electronics/Arrowmounts-Universal-Flat-Wall-Mount-for-23-to-32-inch-LED-LCD-TVs-AM-F3220B/5701275/product.html
Product is perfect for mounting a small tv. Just note that the bracket is not very wide so it is somewhat difficult to center depending on where the studs are.
How did the image on site compare with the actual product? Yes, a little smaller than expected
Just What I needed and the price
It was right for the price and didn't take no time to come in.
Please tell us about the quality of the product. it was nice for the price
blackgal7575
from Lake Charles,
Good product at a more reasonable price
I had been shopping for one of these TV mounts, but they are very expensive which seems crazy for a little bit of metal and a couple of screws. This one was a much better price than I had found anywhere and the quality was good.
How did the image on site compare with the actual product? Product was as pictured.
Perfect wall mount, perfect price!
This product looked exactly as it did in the picture, and was easier to install than other mounts I have purchased and installed in the past. I HIGHLY recommend this product.
jfvasquezjr
Works great on a 32" flat screen. Could not be happier with the purchase. Easy to install and hang the tv.
from Stillwater Ok,
this is a great wall mount for a 40 inch tv and could handle heavier ones i am sure. we had no issues installing at all. all hardware has held up well and did not need anything beyond standard tools and drills. we also did not experience any problems with the bracket attachments as others describe. tightened fine for me, and we have had not problems. the only negative i could find, is the swinging arm is difficult to move - however we have ours in a corner where we do not need to move it, so it is not an issue for us. perhaps some wd-40 would loosen it up if you needed to swing it often. otherwise, very happy.

value: Overstock, excessive stock, excess2sell, B-stock, or excess inventory, is the result of poor management of stock demand or of material flow in process management. Excessive stock is also associated with loss of revenue owing to additional capital bound with the purchase or simply storage space taken.


text:
Office/Playroom, The Before {My Newest Project} – And Then We Laughed
Office/Playroom, The Before {My Newest Project}	July 29, 2013 ~ Karen	On the main floor on our house, a room that we call the office/playroom sits just a step above the living room. With great natural light, it is a bit of an awkward space. The previous tenants used the room as an office (complete with one of the largest wooden desks I’ve ever seen) but because the basement is just too damn cold in the winter, we knew we had to use the space as a playroom too. Yay for dual purpose rooms!
Posted in Musings	officeplayroomredecorating	Published by Karen
‹ PreviousFinding Our New NormalNext ›The Brightest Rainbow of All
2 thoughts on “Office/Playroom, The Before {My Newest Project}”	Trina says:	July 29, 2013 at 5:59 pm	Karen,
I can’t wait to see what you do with your office area. My family and I just returned Stateside and will be converting the den of our rental into an office/play space. I need inspiration! 🙂
Reply	Krisjand says:	August 5, 2013 at 4:44 am	Hi! I have been following your blog a while. I am also Army and have been dragging my wife around the world a number of years now as well. Try searching “IKEA hacks” (most popular result: http://www.ikeahackers.net/) for some interesting and thrifty solutions. It seems like we are always going from big houses to small ones and storage is the challenge. Our daughter and her toys has made this even more difficult. Anyway, good luck!

value: WordPress (WP, WordPress.org) is a free and open-source content management system (CMS) written in PHP and paired with a MySQL or MariaDB database. Features include a plugin architecture and a template system, referred to within WordPress as Themes.


text:
Difference between spinor and vector field - Physics Stack Exchange
vector-fields spinors share|improve this question edited Feb 6 '13 at 21:38
marked as duplicate by Qmechanic♦ Feb 7 '13 at 1:38
Possible duplicate: physics.stackexchange.com/q/41211/2451
Feb 6 '13 at 21:45
The answer to your question depends on the context, but the basic unifying theme distinguishing different kinds of fields (like vector fields, scalar fields, etc.) is how these fields transform when they are acted on by Lie Groups (and or Lie Algebras) which falls under the mathematical subject of representation theory of Lie groups and Lie algebras. Here are some examples to illustrate what I mean:
Consider a real field $V^\mu(x)$ defined on 4-dimensional Minkowski space $\mathbb R^{3,1}$. We say that this field is a Lorentz 4-vector field provided when it is acted on by a Lorentz transformation $\Lambda = (\Lambda^{\mu}_{\phantom\mu\nu})$ (an element of the Lorentz Group $\mathrm{SO}(3,1)$), it transforms as follows:
V^\mu(x) \to V'^\mu(x) = \Lambda^{\mu}_{\phantom\mu\nu} V^\nu(\Lambda^{-1}x)
Now Consider instead a field $\Psi^a(x)$ defined on 4-dimensional Minkowski space $\mathbb R^{3,1}$. We say that such a field is a Dirac Spinor provided when it is acted on by Lorentz transformations, it transforms as follows:
\Psi^a(x) \to \Psi'^a(x) = R_{\mathrm{dir}}(\Lambda)^a_{\phantom a b}\Psi^a(\Lambda^{-1}x)
where $R_{\mathrm{dir}}$ is called the Dirac spinor representation of the Lorentz Group.
There are also other kinds of spinors, all of whom transform according to different representations of different Lie groups.
share|improve this answer edited Feb 6 '13 at 21:33
answered Feb 6 '13 at 19:16
Nice answer, maybe an extenstion of this to a blog post would be nice too ...?
@Dilaton. Thanks; that's a great idea. I'll do my next post on this and extend the concepts with more detail!
It might be good to expand a bit on the spinor representation itself, since a transformation law of the form $\Psi^a \rightarrow M(\Lambda)^a_b \Psi^b$ is completely general.
Feb 7 '13 at 9:31
Often we use spinors to rotate things. Using clifford algebra, you get a rotation formula looking like this:
$$a' = \psi a \psi^{-1}$$
where $a$ is some vector. This shows how vectors are rotated in a double-sided way.
If you chain two rotations together, you might get something like this:
$$a'' = \phi \psi a \psi^{-1} \phi^{-1} = \psi' a {\psi'}^{-1}$$
So $\psi' = \phi \psi$. Spinors transform in a single-sided way.
Geometrically, vectors are the oriented lines that you're used to, with a weight equal to the vector's magnitude. Spinors represent linear combinations of scalars and bivectors, oriented planes. Any two vectors can define a spinor, and in 3d, that spinor has components related to both the dot product and cross product. It measures, in a redundant way, how the two vectors are both aligned and not-aligned (including what plane they lie in). These vectors are related geometrically to the rotation as the two reflection vectors you can build up a rotation from--any rotation can be built up from two reflections.
share|improve this answer answered Feb 6 '13 at 17:01
+1, thanks for the beginnings of my geometric intuition about spinors :) Please could you give a reference or two where I could read a bit more about this geometric interpretation of spinors?
Feb 6 '13 at 23:50
By double-sided you mean the inverse transformation matrix included?
– pkjag
Aug 3 at 19:57
Some mathematical representation has been given by others. If you like some discussion on the physics difference between these two objects you can consider the following. The difference is in the rotational symmetry of these fields. The wave function of a vector particle needs to be rotated once (360 degrees) in order to return to its original configuration (to be identical). The wave function of a spinor particle, must be rotated twice (720 degrees) to return to its original configuration. This is because of the spin difference of these two objects being $S = 1\hbar$ and $S = 1/2\hbar$ respectively. For a rotation by an arbitrary angle 'a' the rotation matrix operator is of the general form $R(a)=\exp (iS.a/\hbar)$. So you can see that if $S = 1\hbar$ then an angle $a = 2\pi$ returns the field to its original configuration, while if $S = (1/2)\hbar$ then you need $a = 4\pi$ to return the "object" to its original configuration. I hope this helps see the difference in the physics of these two fields.
share|improve this answer edited Feb 14 '13 at 18:20
answered Feb 7 '13 at 1:08
add a comment | Not the answer you're looking for?	Browse other questions tagged vector-fields spinors or ask your own question.	asked
Concrete example of divergence of a vector field
Restriction on vector fields
How could flux can be a vector and a scalar?
Question on spinor brackets
What are differences between Spin(3,1), SL(2,C), SO(3,1) and SU(2) representations? Which one is correct exact representation for spinor fields?

value: Stack Exchange is a network of question-and-answer (Q&A) websites on topics in diverse fields, each site covering a specific topic, where questions, answers, and users are subject to a reputation award process. The reputation system allows the sites to be self-moderating.


text:
Easter In My Heart | Christa Sterken
Posted on March 16, 2011 by christasterken
PIcked up a little gem of a book a few years ago, Easter In My Heart b Joseph Wheeler. I have rarely seen a book of Easter stories and this is truly engaging. I love this quote he used as the introduction by Phillips Brooks, author of the song “O Little Town of Bethlehem”.
Let every man and woman count themselves imorotal. Let him catch the revelation of Jesus in His Resurrection. Let him say not merely, “Christ is risen,,” but “I shall rise…In me there is something that no stain on earth can tarnish and no stroke of the world can erase. I,too, am a part of God and have God’s immortality in me.”
Gram on March 16, 2011 at 5:40 pm said:
Whoa, Christa! I’ve never seen a better description of what Easter is all about. I’m passing this along, if you don’t mind…


text:
SALMON: Recipe for broiled sockeye salmon salad with blueberries and sweet potatoes
04/15/2015 10:53 EDT | Updated 06/24/2015 06:59 EDT
Sockeye, also called red salmon, is known for its distinct, bright red flesh that retains its colour even once cooked. It is prized for its firm, fatty meat, and its pronounced, yet versatile flavour. Though less buttery than king, many chefs say sockeye stars on the plate just as easily.
Sockeye takes well to added butter and other fats, chefs say, as well as to flavourful seasonings.
Sockeye is eaten for both its meat and for its roe, which is used as salmon caviar for sushi. Nearly all of the country's sockeye comes from Alaska, according to the National Oceanic and Atmospheric Administration, with the world's largest harvest landing at Bristol Bay in the southwestern part of the state. Sockeye's colour and texture make it ideal for canning, but today more than half of the annual catch is sold fresh or frozen.
Often found: Most often see as lox; as the sushi salmon roe called "ikura;"at the centre of the restaurant plate; and as steaks, fillets and whole fish at fish counters.
In a small bowl, mix together the brown sugar, mustard, hot sauce and 1/2 teaspoon salt. Arrange the salmon pieces on the prepared pan and spread the brown sugar mixture over the top of each piece. Cook the salmon 4 inches from the broiler for 2 minutes, or until browned and cooked to the desired level.
Nutrition information per serving: 360 calories; 150 calories from fat (42 per cent of total calories); 17 g fat (3 g saturated; 0 g trans fats); 100 mg cholesterol; 19 g carbohydrate; 3 g fiber; 8 g sugar; 36 g protein; 400 mg sodium.

value: HuffPost, formerly The Huffington Post until 2017 and sometimes abbreviated HuffPo, is an American news aggregator and blog, with localized and international editions. The site offers news, satire, blogs and original content, and covers politics, business, entertainment, environment, technology, popular media, lifestyle, culture, comedy, healthy living, women's interests and local news featuring columnists.


text:
Amazon.com: yaya's review of HDE 2 Pc Screen Protector Set for Nintendo...
My granddaughter loves them, December 30, 2012
This review is from: HDE 2 Pc Screen Protector Set for Nintendo DSi XL (Video Game)
Bought them for my granddaughter and it's a good thing or her DS would be a mess since she plays it all the time.
HDE 2 Pc Screen Protector Set for Nintendo DSi XL B003F18CTM
Top Reviewer Ranking: 1,927,030

value: Amazon.com, Inc. ( AM-ə-zon) is an American multinational conglomerate which focuses on e-commerce, cloud computing, digital streaming, and artificial intelligence.