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Patent US6483344 - Interconnect circuitry for implementing logic functions in a field ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThere is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic...http://www.google.com/patents/US6483344?utm_source=gb-gplus-sharePatent US6483344 - Interconnect circuitry for implementing logic functions in a field programmable gate array and method of operationAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6483344 B2Publication typeGrantApplication numberUS 09/773,320Publication dateNov 19, 2002Filing dateJan 31, 2001Priority dateJan 31, 2001Fee statusPaidAlso published asUS20020101259Publication number09773320, 773320, US 6483344 B2, US 6483344B2, US-B2-6483344, US6483344 B2, US6483344B2InventorsVidyabhusan GuptaOriginal AssigneeStmicroelectronics, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (2), Referenced by (64), Classifications (12), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetInterconnect circuitry for implementing logic functions in a field programmable gate array and method of operation
US 6483344 B2Abstract
There is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches. The interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes the first and second interconnects to be coupled to a third interconnect, and causes the third interconnect to be coupled to a pull-up device coupled to a power supply source of the field programmable gate array. The first, second and third interconnects and the pull-up device thereby form a two-input OR gate.
What is claimed is: 1. A field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a two-input NOR gate. 2. The field programmable gate array as set forth in claim 1 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
3. The field programmable gate array as set forth in claim 2 wherein said memory comprises a static read only memory.
4. The field programmable gate array as set forth in claim 3 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
5. The field programmable gate array as set forth in claim 1 wherein said pull-up device is a pull-up transistor.
6. The field programmable gate array as set forth in claim 1 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
7. The field programmable gate array as set forth in claim 6 wherein said buffer is a non-inverting line driver.
8. The field programmable gate array as set forth in claim 6 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
9. A system-on-a-chip integrated circuit comprising:
a main memory for storing main program instructions; a processing circuit capable of executing said main program instructions; a plurality of embedded circuit components; and a field programmable gate array comprising: a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a two-input NOR gate. 10. The system-on-a-chip integrated circuit as set forth in claim 9 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
11. The system-on-a-chip integrated circuit as set forth in claim 10 wherein said memory comprises a static read only memory.
12. The system-on-a-chip integrated circuit as set forth in claim 11 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
13. The system-on-a-chip integrated circuit as set forth in claim 9 wherein said pull-up device is a pull-up transistor.
14. The system-on-a-chip integrated circuit as set forth in claim 9 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
15. The system-on-a-chip integrated circuit as set forth in claim 14 wherein said buffer is a non-inverting line driver.
16. The system-on-a-chip integrated circuit as set forth in claim 14 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
17. A field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration couples N interconnects between N CLB outputs and a common interconnect, each of said N interconnects being coupled between one CLB output and said common interconnect, and wherein said interconnect switch controller couples said common interconnect to a pull-up device coupled to a power supply source of said field programmable gate array, said N interconnects, said common interconnect, and said pull-up device thereby forming an N-input NOR gate. 18. The field programmable gate array as set forth in claim 17 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
19. The field programmable gate array as set forth in claim 18 wherein said memory comprises a static read only memory.
20. The field programmable gate array as set forth in claim 17 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
21. The field programmable gate array as set forth in claim 17 wherein said pull-up device is a pull-up transistor.
22. The field programmable gate array as set forth in claim 17 further comprising a buffer having an input coupled to said common interconnect and an output coupled to an input of a CLB.
23. The field programmable gate array as set forth in claim 22 wherein said buffer is a non-inverting line driver.
24. The field programmable gate array as set forth in claim 23 wherein said buffer is an inverting line driver, said N interconnects, said common interconnect, said pull-up device, and said buffer thereby forming an N-input OR gate.
25. The field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a logic state. 26. The field programmable gate array as set forth in claim 25 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
27. The field programmable gate array as set forth in claim 26 wherein said memory comprises a static read only memory.
28. The field programmable gate array as set forth in claim 27 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
29. The field programmable gate array as set forth in claim 25 wherein said pull-up device is a pull-up transistor.
30. The field programmable gate array as set forth in claim 25 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
31. The field programmable gate array as set forth in claim 30 wherein said buffer is a non-inverting line driver.
32. The field programmable gate array as set forth in claim 30 wherein saif first, second and third interconnects, said pull-up device, and said buffer form a two-input NOR gate.
33. The field programmable gate array as set forth in claim 30 wherein said buffer in an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
34. A system-on-a-chip integrated circuit comprising:
a main memory for storing mean program instructions; a processing circuit capable of executing said main program instructions; a plurality of embedded circuit components; and a field programmable gate array comprising: a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be couple to an output of a first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a logic gate. 35. The system-on-a-chip integrated circuit as set forth in claim 34 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
36. The system-on-a-chip integrated circuit as set forth in claim 35 wherein said memory comprises a static read only memory.
37. The system-on-a-chip integrated circuit as set forth in claim 36 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
38. The system-on-a-chip integrated circuit as set forth in claim 34 wherein said pull-up device is a pull-up transistor.
39. The system-on-a-chip integrated circuit as set forth in claim 34 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
40. The system-on-a-chip integrated circuit as set forth in claim 39 wherein said buffer is a non-inverting line driver.
41. The system-on-a-chip integrated circuit as set forth in claim 40 wherein said first, second and third interconnects, said pull-up device, and said buffer from a two-input NOR gate.
42. The system-on-a-chip integrated circuit as set forth in claim 39 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
43. A field programmable gate array comprising:
a plurality of configurable logic blocks )CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration couples N interconnects between N CLB outputs and a common interconnect, each of said N interconnects being coupled between one CLB output and said common interconnect, and wherein said interconnect switch controller couples said common interconnect to a pull-up device coupled to a power supply source of said field programmable gate array, said N interconnects, said common interconnect, and said pull-up device thereby forming a logic gate. 44. The field programmable gate array as set forth in claim 43 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
45. The field programmable gate array as set forth in claim 44 wherein said memory comprises a static read only memory.
46. The field programmable gate array as set forth in claim 43 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
47. The field programmable gate array as set forth in claim 43 wherein said pull-up device is a pull-up transistor.
48. The field programmable gate array as set forth in claim 43 further comprising a buffer having an input coupled to said common interconnect and an output coupled to an input of a CLB.
49. The field programmable gate array as set forth in claim 48 wherein said buffer is a non-inverting line driver.
50. The field programmable gate array as set forth in claim 49 wherein said N interconnects, said common interconnect, said pull-up device, and said buffer from an N-input NOR gate.
51. The field programmable gate array as set forth in claim 48 wherein said buffer is an inverting line driver, said N-interconnects, said common interconnect, said pull-up device, and said buffer thereby forming an N-input OR gate.
The present invention is related to that disclosed in U.S. patent application Ser. No. 09/774,891 filed concurrently herewith, entitled “INTERCONNECT CIRCUITRY FOR IMPLEMENTING BIT-SWAP FUNCTIONS IN A FIELD PROGRAMMABLE GATE ARRAY AND METHOD OF OPERATION”. Patent application Ser. No. 09/774,891 is commonly assigned to the assignee of the present invention. The disclosure of this related patent application is hereby incorporated by reference for all purposes as if fully set forth herein.
The present invention is generally directed to field programmable gate array (FPGA) circuits, a more specifically to an FPGA circuit in which logic functions may be implemented by the interconnect circuitry between logic blocks.
The speed, power, and complexity of integrated circuits, such as microprocessor chips, random access memory (RAM) chips, application specific integrated circuit (ASIC) chips, and the like, have increased dramatically in the last twenty years. More recently, these increases have led to development of so-called system-on-a-chip (SoC) devices. A SoC device allows nearly all of the components of a complex system, such as a cell phone or a television receiver, to be integrated onto a single piece of silicon. This level of integration greatly reduces the size and power consumption of the system, while generally also reducing manufacturing costs.
A key component in many highly integrated circuits, including SoC devices, is the field programmable gate array (FPGA). FPGA circuits are a particular class of general purpose integrated circuits (ICs) that can be configured (i.e., programmed) to perform a wide range of tasks. There are a number of different types of FPGA circuit topologies, including symmetrical array, row-based, sea-of-gates, and hierarchical programmable logic device (PLD). Each of these FPGA types has certain advantages over other types, depending on the specific application.
FPGA circuits generally are implemented using one of four technologies: static RAM cells, anti-fuse, EPROM transistors, and EEPROM transistors. In static RAM technology, programmable connections in the FPGA are made using pass transistors, transmission gates, or multiplexers controlled by a static random access memory (RAM) cell. Static RAM cells technology allow fast reconfiguration of a FPGA circuit. Anti-fuse technology uses an anti-fuse that is initially a high-impedance connection path (i.e., open circuit). The anti-fuse is then programmed into a low impedance (i.e., short circuit) or fused state. While anti-fuse technology is simple and less expensive than static RAM technology, an anti-fuse is a “program once” device. EPROM and EEPROM technologies use the same methods that are used in EPROM memories.
There are three primary configurable elements in a FPGA circuit: configurable logic blocks (CLBs), input/output (I/O) blocks, and programmable interconnects. The configurable logic blocks contain a variety of different logic functions, such as look-up tables (LUTs), registers, multiplexer (MUX) gates, programmable logic arrays (PLDs) programmable logic devices (PLDs), and the like. A programmable interconnect generally connects a single output of a CLB to an input of another CLB. An interconnect comprises metal wires and transistors that act as pass gates and signal buffers that preserve the signal integrity. Control of the interconnect transistors may be provided by an SRAM cell, a flash RAM cell, or external pins. The programming of an interconnect is usually done in a static fashion, such as at the power-up of a stand-alone FPGA circuit, especially for flash RAM and SRAM based configurations. The I/O blocks provide the interface between the external pins of the IC package and the internal signals lines, including the programmable interconnects.
Despite the considerable advancements made in field programmable gate array circuits, however, there remains room for improvement. There is a limitation to the complexity of the logic functions that may be implemented in a FPGA circuit of a particular size and density. More complex functions call for still greater FPGA density. However, this greater density must be achieved without incurring larger latencies due to increased propagation times through the FPGA circuit.
Therefore, there is a need in the art for system-on-a-chip (SoC) devices and other large scale integrated circuits that implement improved field programmable gate array (FPGA) circuits. In particular, there is a need for FPGA circuits, including embedded FPGA circuits, that achieve greater density and/or utilization over standard FPGA technologies. More particularly, there is a need for improved FPGA circuits that are capable of performing more complex logical functions while minimizing propagation times.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a field programmable gate array capable of performing in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, that are normally performed in the configurable logic blocks of the FPGA. According to an advantageous embodiment of the present invention, the field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches capable of coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller capable of controlling the plurality of interconnect switches. The interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes the first and second interconnects to be coupled to a third interconnect, and causes the third interconnect to be coupled to a pull-up device coupled to a power supply source of the field programmable gate array. The first, second and third interconnects and the pull-up device thereby form a two-input NOR gate.
According to one embodiment of the present invention, the interconnect switch controller comprises a memory capable of storing the first switch configuration.
According to another embodiment of the present invention, the memory comprises a static read only memory.
According to still another embodiment of the present invention, the interconnect switch controller comprises at least one configurable logic block in the field programmable gate array.
According to yet another embodiment of the present invention, the pull-up device is a pull-up transistor.
According to a further embodiment of the present invention, the field programmable gate array further comprises a buffer having an input coupled to the third interconnect and an output coupled to an input of a third CLB.
According to a still further embodiment of the present invention, the buffer is a non-inverting line driver.
According to a yet further embodiment of the present invention, the buffer is an inverting line driver, such that the first, second and third interconnects, the pull-up device, and the buffer thereby form a two-input OR gate.
FIG. 1 illustrates a processing system that includes an exemplary system-on-a-chip (SoC) device according to one embodiment of the present invention;
FIGS. 2A-2D illustrate various circuit topologies of the field programmable gate array (FPGA) in the exemplary SoC device in FIG. 1;
FIGS. 3A and 3B illustrate an exemplary bit swap device implemented with programmable interconnects that is operable to receive an N-bit input value and generate a re-ordered N-bit output value according to one embodiment of the present invention; and
FIG. 4 illustrates an exemplary Boolean logic gate in the embedded FPGA implemented with programmable interconnects according to one embodiment of the present invention.
FIGS. 1 through 4, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged field programmable gate array (FPGA).
FIG. 1 illustrates processing system 100, which includes exemplary system-on-a-chip (SoC) device 105 according to one embodiment of the present invention. SoC device 105 is a single integrated circuit comprising embedded field programmable gate array (FPGA) 115, optional FPGA built-in self test (BIST) circuit 116, peripheral circuits 120 and 125, microprocessor 130, random access memory (RAM) 135, read-only memory (ROM) 140, configurable bus 150, main (or system) bus 160, and bridge circuit 150. In an exemplary embodiment of the present invention, processing system 100 also comprises external memory 110, which may be, for example, a flash memory, a random access memory, a disc storage device, or the like. Optional FPGA built-in self test (BIST) circuit 116 is used to perform BIST testing on embedded FPGA device 115 in the event of a reboot or other event that requires the execution of BIST functions.
Processing system 100 is shown in a general level of detail because it is intended to represent any one of a wide variety of electronic devices, particularly consumer appliances. For example, processing system 100 may be a printer rendering system for use in a conventional laser printer. Processing system 100 also may represent selected portions of the video and audio compression-decompression circuitry of a video playback system, such as a video cassette recorder or a digital versatile disk (DVD) player. In another alternative embodiment, processing system 100 may comprise selected portions of a cable television set-top box or a stereo receiver.
Embedded FPGA 115 and peripheral circuits 120 and 125, which are arbitrarily labeled Circuit Block 1 and Circuit Block 2, respectively, may be configured to implement any designated function in processing system 100. For example, peripheral circuit 120 may be a video codec and peripheral circuit 125 may be an audio code. In the ordinary operation of processing system 100, embedded FPGA 115 also may be a video codec, and audio coded, or some other functional unit, such as a bus controller for configurable bus 150.
In an exemplary embodiment of the present invention, microprocessor 130 executes an application program that may be stored in RAM 135. ROM 140 stores a start-up program that is executed by microprocessor 130 after a system reboot. Address and data information is transferred between microprocessor 130, RAM 135 and ROM 140 via main bus 160. Similarly, address and data information may be transferred between peripheral devices 120 and 125 and embedded FPGA 115 via configurable bus 150. Data traffic may be transferred between configurable bus 160 and main bus 160 via bridge 170, which provides isolation between configurable bus 150 and main bus 160 to increase overall system throughput.
According to the principles of the present invention, embedded FPGA 115 comprises configuration static random access memory (SRAM) 117, configurable logic blocks (CLBs), input/output (I/O) blocks, and programmable interconnects. The configurable logic blocks contain a variety of different logic functions, such as look-up tables (LUTs), registers, multiplexer (MUX) gates, programmable logic arrays (PLDs), programmable logic devices (PLDs), and the like. However, the programmable interconnects in FPGA 115 differ from the interconnects of prior art FPGA circuits, which merely provide connections between the outputs of some CLBs and the inputs of other CLBs. The programmable interconnects in FPGA 115 are selectively connected under the control of configuration SRAM 117 (or designated CLBS) in order to implement selected logical operations, including Boolean operators (i.e., AND, NAND, OR, NOR, and similar functions).
FIGS. 2A-2D illustrate various circuit topologies of field programmable gate array (FPGA) 115 in exemplary SoC device 105. FIG. 2A illustrates FPGA 115A, which uses a symmetrical array topology. A symmetrical array topology comprises a plurality of configurable logic blocks (CLBs), such as exemplary CLB 205A, arranged in an N×M matrix and separated by vertical columns and horizontal rows of interconnects, such as exemplary interconnect 210A. The inputs and outputs of the CLBs are selectively connectable to the rows and columns of interconnects. FIG. 2B illustrates FPGA 115B, which uses a row-based topology. A row-based topology comprises a plurality of configurable logic blocks (CLBs), such as exemplary CLB 205B, arranged in a plurality of rows and separated by horizontal rows of interconnects, such as exemplary interconnect 210B. The inputs and outputs of the CLBs are selectively connectable to the rows of interconnects.
FIG. 2C illustrates FPGA 115C, which uses a sea-of-gates topology. A sea-of-gates topology comprises a plurality of comparatively simple logic gates, such as exemplary logic gate 205C, arranged in an R×C matrix and separated by vertical columns and horizontal rows of interconnects, such as exemplary interconnect 210C. The inputs and outputs of the logic gates are selectively connectable to the rows and columns of interconnects. FIG. 2D illustrates FPGA 115D, which uses a hierarchical programmable logic device (PLD) topology. A hierarchical programmable logic device topology comprises a plurality of programmable logic devices, such as exemplary PLD 205D, that are selectively connectable by a plurality of interconnects, such as exemplary interconnect 210D. An FPGA circuit having programmable interconnects that perform selected logical operations according to the principles of the present invention may be embodied as anyone of the foregoing circuit topologies, as well as other FPGA circuit topologies.
FIGS. 3A and 3B illustrate exemplary bit swap device 300 in FPGA 115 that uses programmable interconnects to receive an N-bit input value and generate a re-ordered N-bit output value according to one embodiment of the present invention. The bit swap operation can be described as follows. Given a N-bit value X, where each of the bits is described by the concatenation [X(N−1), X(N−2), . . . , X2, X1, X0] and an N-bit value Y, where each of the bits is described by the concatenation [Y(N−1), Y(N−2), . . . , Y2, X1, X0], the value Y can be related to the value X according to the following relationship:
Y(N−1)=X 0, Y(N−2)=X 1, . . . Y 2=X(N−3), Y 1=X(N−2), Y 0=X(N−1).
This operation is often performed when handling data that has different “endianess”, thereby requiring the program to convert between little endian format (least significant bit or byte first) and big endian format (most significant bit or byte first). According to the principles of the present invention, the endian conversion operation may be executed by the programmable interconnects in FPGA 115, rather than in a configurable logic block, by reprogramming 2N switches between the interconnects. The 2N switches may be controlled by switch position settings stored in configuration SRAM 117 or by one or more configuration CLBs. This results in a bit swap operation that is carried out with very little circuit overhead and with a major reduction in circuit area. One key point is that the configuration bits of the routing array are able to be set by the logic inside of the FPGA itself.
In the exemplary circuit in FIG. 3A, it is assumed that the X value and the Y value have the same endian format (i.e., both big endian format or both little endian format). For the sake of simplicity in explaining the operation of the bit swap device, it is assumed that X and Y are 16-bit values. Thus, X0=Y0, X1=Y1, . . . , X15=Y15. The sixteen bits of the value X are coupled to programmable vertical interconnects that are labeled X0, X1, X2, . . . , X15 for convenience. The sixteen bits of the value Y are coupled to programmable vertical interconnects that are labeled Y0, Y1, Y2, . . . , Y15 for convenience.
Bit swap device 300 in FPGA 115 also comprises programmable horizontal interconnects, including exemplary programmable horizontal interconnects 341, 342, 343 and 344. Any one of the programmable vertical interconnects, X0, X1, . . . , X15 and Y0, Y1, . . . , Y15 may be selectively coupled to anyone of the programmable horizontal interconnects by closing interconnect switches, such as exemplary interconnect switches 301-310, disposed at the junctions of the vertical and horizontal interconnects. In FIGS. 3A and 3B, closed interconnect switches are shown as a square with an X therein and open interconnect switches are shown as an empty square. Thus, interconnect switch 301 and interconnect switches 304-310 are closed and interconnect switches 302 and 303, among others, are open.
As FIG. 3A shows, vertical interconnect X0 and vertical interconnect Y0 are both connected to horizontal interconnect 341. Similarly, vertical interconnect X1 and vertical interconnect Y1 are both connected to horizontal interconnect 342. This connection scheme continues through vertical interconnect X15 and vertical interconnect Y15, which are both connected to horizontal interconnect 344. In this manner, the X value and the Y value have the same endian format, such that X0=Y0, X1=Y1, . . . , X15=Y15. The interconnect switches are set by switch select lines that may be controlled by, for example, a static random access memory (SRAM). Groups of exemplary switch select lines (shown as dotted lines) are designated by reference numbers 320 and 330. The exemplary switch select lines designated by reference number 320 control exemplary interconnect switches 301-304.
However, the endian format can easily be reversed by selectively resetting the interconnect switches that couple the vertical interconnects and the horizontal interconnects. As FIG. 3B illustrates, the interconnect switches that couple the vertical interconnects Y0-Y15 to the horizontal interconnects have been reset to reverse the endian format. Thus, interconnect switch 307 is open and interconnect switch 311 is closed, so that vertical interconnect Y0 is now coupled to vertical interconnect X15, rather that to vertical interconnect X0. Similarly, interconnect switch 308 is open and interconnect switch 312 is closed, so that vertical interconnect Y1 is now coupled to vertical interconnect X14, rather that to vertical interconnect X1. Continuing this process, it can be seen that the X value and the Y value have different endian formats, such that X0=Y15, X1=Y14, . . . , X15=Y0.
In the exemplary embodiment described above, bit swap device 300 reverses the order of all of the N-bits in the X value and Y value. More generally speaking, however, bit swap device 300 may re-order bits according to any selected algorithm. For instance, in the example above, bit swap device 300 may instead be configured to swap the most significant byte (MSB) and least significant byte (LSB) in the 16-bit X and Y values, while preserving order within each byte. Thus, the initial ordering may be as follows:
LSB=X 0=Y 0, X 1=Y 1, . . . , X 7=Y 7;
MSB=X 8=Y 8, X 9=Y 9, . . . , X 15=Y 5.
However, after bit swap device 300 re-orders the bits, the final ordering may be as follows:
LSB=X 0=Y 8, X 1=Y 9, . . . , X 7=Y 15;
MSB=X 8=Y 0, X 9=Y 1, . . . , X 15=Y 7.
Another way to improve the computational capability of the programmable interconnects in an FPGA is to increase the signal aggregation ability. For instance, if a number of CLBs are able to transmit data over the same wiring, there is a corresponding reduction in the required routing complexity of the FPGA. Examples of logical functions that benefit from this type of improvement are Logic 1 detectors and Logic 0 detectors. These functions are used to detect at least one Logic 1 value or all Logic 0 values in a set of data bits. More complex functions like overflow detection and threshold detection rely on these more basic functions. Implementing a conventional Logic 1 detector or Logic 0 detector in a FPGA consumes a fair amount of CLB resources. However, an FPGA that implements logical functions using the programmable interconnects in accordance with the principles of the present invention eases these requirements.
FIG. 4 illustrates exemplary Boolean logic gate 400 in FPGA 115 implemented with programmable interconnects according to one embodiment of the present invention. Boolean logic gate 400 comprises transistors 411-416, output interconnects 421-426, horizontal interconnects 431 and 432, vertical interconnects 441 and 442, interconnect switches 451-456, interconnect switches 461-464, buffer 470, and pull-up transistor 480. As will be explained below in greater detail, Boolean logic gate 400 may function as a wired OR gate or a wired NOR gate, depending on whether buffer 470 is an inverting buffer or a non-inverting buffer. Boolean logic gate 400 may be used to detect the presence of at least one Logic 1 value and to detect the presence of all Logic 0 values.
Transistors 411-416 are N-type transistors that may comprise the output drive transistors in configurable logic blocks, programmable logic devices, or simple logic gates in FPGA 115. The outputs of transistors 411-416 are the output interconnects 421-426, respectively. Output interconnects 421-423 may be coupled to vertical interconnect 441 by interconnect switches 451-453, respectively. Output interconnects 424-426 may be coupled to vertical interconnect 442 by interconnect switches 454-456, respectively.
Vertical interconnect 441 may be coupled to horizontal interconnects 431 and 432 by interconnect switches 461 and 462, respectively. Vertical interconnect 442 may be coupled to horizontal interconnects 431 and 432 by interconnect switches 463 and 464, respectively. In FIG. 4, closed interconnect switches are shown as a square with an X therein and open interconnect switches are shown as an empty square. Thus, interconnect switches 451-454 and interconnect switches 462 and 464 are closed and interconnect switches 455, 456, 461 and 463 are open.
In effect, the outputs of transistors 411-414 are shorted to each other and are connected to pull-up transistor 480. This forms a wired-OR gate. The gates of transistors 411-416 are the signals A, B, C, D, E and F. The outputs of transistors 415 and 416 are not used (i.e., open-circuited). Thus, the input of buffer 470 is the OR result of A, B, C and D. If buffer 470 is non-inverting, the OUT signal is equal to the OR result of A, B, C and D (i.e., A OR B OR C OR D). If buffer 470 is inverting, the OUT signal is equal to the NOR result of A, B, C and D.
Advantageously, the interconnect switches may be reset to give different OR and NOR results. For example, if interconnect switches 453 and 454 are opened and interconnect switches 455 and 456 are closed, the input of buffer 470 is the OR result of A, B, E and F. Similarly, buffer 470 may be reset to switch between an OR result (non-inverting) and a NOR result (inverting).
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temperature-compensated rc oscillator circuitUS20080309393 *Oct 31, 2007Dec 18, 2008Actel CorporationClock-generator architecture for a programmable-logic-based system on a chipUS20090128186 *Jan 8, 2009May 21, 2009Actel CorporationProgrammable system on a chip for power-supply voltage and current monitoring and controlCN101273507BJul 26, 2006Dec 29, 2010德克萨斯仪器股份有限公司System and method for protecting IC componentsWO2007014270A3 *Jul 26, 2006Jul 12, 2007Texas Instruments IncSystem and method for protecting ic components* Cited by examinerClassifications U.S. Classification326/41, 326/38, 326/47, 326/39International ClassificationG06F15/78, H03K19/177Cooperative ClassificationG06F15/7867, H03K19/1778, H03K19/17736European ClassificationH03K19/177J, H03K19/177F, G06F15/78RLegal EventsDateCodeEventDescriptionJan 31, 2001ASAssignmentOwner name: STMICROELECTRONICS, INC., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GUPTA, VIDYABHUSAN;REEL/FRAME:011493/0590Effective date: 20010131Apr 27, 2006FPAYFee paymentYear of fee payment: 4Apr 29, 2010FPAYFee paymentYear of fee payment: 8Apr 28, 2014FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

value: Google Patents is a search engine from Google that indexes patents and patent applications.


text:
BBC NEWS | England | Wiltshire | Club is bailed out by shareholder
EDITORS' BLOG	Last Updated: Friday, 5 October 2007, 09:27 GMT 10:27 UK
Club is bailed out by shareholder
The club has previously said it will stay at the County Ground
Swindon Town FC has been bailed out by its main shareholder again as negotiations continue on a takeover. Unpaid players wages contributed to the demand for money to the majority shareholder, the Wills family.
It has also been revealed that the club owes Cheltenham Town FC £25,000 in ticket sales. In August the club said Best Holdings SGPS S.A had taken formal control, but a spokesman on Friday said that negotiations were continuing.
The spokesman said: "We are confident [the deal] will go through."
He would not say how much the club had asked the Wills family for, only that it was for short-term cover. When Swindon Town FC came out of administration in 2002, it agreed to pay £1m within five years to creditors but still owes about £900,000.
A statement on the club's website said: "As the protracted negotiations with Best Holdings with regards to the takeover of the club continue, the STFC Board of Directors has, in the meantime, sought from the club's major shareholder additional funds to fulfil the immediate obligations and financial liabilities of the company." The club has previously said a new consortium of investors would include the Wills family, their advisor and club general manager Mike Diamandis, and a new investor, thought to be Portuguese. The Wills family has two directors on the club's board, Sir Seton and his son James.
Deal done on town football club
15 Aug 07 | Wiltshire
New backers for Swindon Town FC
Football boss investigated by DTI
05 Jan 07 | Wiltshire
New bid for Swindon football club
20 Dec 06 | Wiltshire
24 Nov 06 | Wiltshire

type: global

value: The British Broadcasting Corporation (BBC) is the national broadcaster of the United Kingdom. Headquartered at Broadcasting House in  London, it is the world's oldest national broadcaster, and the largest broadcaster in the world by number of employees, employing over 22,000 staff in total, of whom approximately 19,000 are in public-sector broadcasting.


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CNN report about superbug – Natural Health with theCamel Milk
Tag: CNN report about superbug	Posted in Natural Health and Camel Milk	Superfood (Camel Milk) can Beat the Challenge of Superbug (Bacterial Resistance to Antibiotics)	Posted on December 12, 2014August 22, 2016 by raziqkakar	The microbiologists continuously exploring camel milk for its unique antimicrobial characteristics. They revealed that camel milk’s (CM) antimicrobial attributes are more important than other multi-dimensional benefits especially in the scenario as scientists have warned about the future threat of superbug 1.
Camel milk fortified with natural antibiotics (lactoferrin, lactic acid bacteria, and others)2 with symbiotic effect to the good bacteria is a silver lining in the clouds. Such natural food provides needed nourishment to good bacteria and restricts bad bacteria to harm the body. I hope the scientist will conduct some more serious scientific studies to explore the hidden treasure of camel milk to combat the challenge of superbug.

value: WordPress (WP, WordPress.org) is a free and open-source content management system (CMS) written in PHP and paired with a MySQL or MariaDB database. Features include a plugin architecture and a template system, referred to within WordPress as Themes.


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Harvest Lane Cottage: Living on His Income Mrs. Sharon White
Thank you Mrs. White!
Have you ever started reading a book and found yourself reading it every spare moment until you finished? I did that this week. Mrs. Sharon White sent me a copy of her new book, Living on His Income Remembrances and Advice for The Christian Housewife to review. You may know her from her blog, The Legacy of Home. I've read her blog for years and was eager to read her book. I just didn't want to put this little book down.
Mrs. White has been a housewife for 28 years. She shares her story as well as that of her mother, grandmother, aunt, and mother-in-law. This is the remembrance part. It made me remember my Grandma Bern and my mom before she went to work. Ah, nostalgia!
The second part is advice. She writes like she's talking to you over a cup of tea and cookies in her parlor. Some of the topics are: Standard of Living, The Vision of Home, The Content Wife, Homemade, and Dependent on Him. She also includes a resource list at the end.
I felt validated... not a stay-at-home mom or homeschool mom but as a housewife.
I felt inspired... to be a housewife proudly... to declutter and organize... to beautify my home with handmade or thrifted treasures... and to be thankful to my husband for making it possible for me to be a housewife as well as a mother and a homeschool mom.
I also found some tips that will help me to do a better job in my chosen profession.
Mrs. White is Titus 2 woman. This is a great book for young women and older women alike.
It is available at Amazon. I encourage you to use the link on Mrs. White's blog. Look around while you're there. I think you'll find something that encourages you. I always do.
See my review of one of her earlier books, A Mother's Faith.
*Note: I am not an Amazon affiliate. The link is Mrs. White's.
Wendi February 10, 2015 at 7:25 AM
Sounds like a book I would enjoy. I will add it to my reading list.
Anne in the kitchen February 10, 2015 at 12:05 PM
Checking it out. Thanks for the review!
Amy February 10, 2015 at 12:08 PM
This sounds like a very encouraging book and who doesn't need that from time to time. I think I will pop in to her blog and check things out.
I hope you have a wonderful week and a special and fun Valentine's Day!
JES February 11, 2015 at 4:54 AM
Thanks for the review Laura. I love the writings of Mrs. White too and have her books in my Amazon cart for that next order when I can... Now I am really eager!! :) Hope you are having a lovely week!
Teresa @ Simply Farmhouse February 11, 2015 at 10:42 AM
Thank you for sharing this..I love to be inspired as a keeper of the home. Sounds like a great book.
Have a wonderful day..Spring is coming!
Laura Lane February 11, 2015 at 4:56 PM
Have a wonderful week. Tomorrow is supposed to be in the low thirties. I need the springtime reminder. ~smile~
Laura Lane February 11, 2015 at 5:03 PM
I hadn't thought of adding things to my cart like that Jes. Thanks for talking back!
Laura Lane February 11, 2015 at 5:08 PM
It's a great place for encouragement Amy. Thanks for talking back!
Laura Lane February 11, 2015 at 5:09 PM
You're welcome Anne.
Laura Lane February 11, 2015 at 5:16 PM
Rhonda IfYouDoStuffStuffGetsDone February 11, 2015 at 5:29 PM
I've liked Mrs White for a long time too. I've never read one of her books. This one sounds great and and month is not too lean so I happily ordered it just now.
Terri Presser February 11, 2015 at 10:48 PM
Hey Laura, this looks like a great book, and definitely worth reading. I would love you to share this with us at Good Morning Mondays, I have missed you this week. Blessings
Rose @ Walnut Acre February 16, 2015 at 8:01 PM
This sounds like a really good book. I enjoy learning new ways to run my home well.
Scrappy quilter February 17, 2015 at 6:08 PM
Laura Lane February 17, 2015 at 9:50 PM
I thought so SQ.
Stephanie February 18, 2015 at 8:03 AM
Well, you are adding books to my reading list left and right :) This one sounds delightful and quite encouraging.
I appreciate your reviews and honesty. Thanks for sharing at ROI. Hugs!
Laura Lane February 18, 2015 at 8:16 AM
We need something to do during this cold winter, Stephanie!
Donna Reidland February 20, 2015 at 11:06 AM
Laura, it sounds like a wonderful book. I went to Mrs. White's website and enjoyed it. Thanks so much for linking up at "Mondays @ Soul Survival." Pinning on my "Mondays @ ..." board. Blessings!
Laura Lane February 20, 2015 at 12:42 PM
You're welcome, Donna. I find Mrs. White's site to be encouraging.
Thanks so much for talking back.
Terri Presser February 20, 2015 at 1:22 PM
Hi Laura, I just wanted to say thank you for linking up at Good Morning Mondays. Thank you for taking the time and I look forward to reading this book one day.Blessings
Laura Lane February 20, 2015 at 4:03 PM
JES February 21, 2015 at 7:27 AM
I love Mrs. White too! Thanks for spreading her lovely work on the Art of Home-Making Mondays!
Laura Lane February 21, 2015 at 8:53 PM
Sure, Jes. I enjoy your link up.
Laura Lane February 21, 2015 at 8:55 PM
You're welcome, Terri.
Have a good Lord's Day!
Jann Olson March 2, 2015 at 8:30 PM
Well this sounds like a wonderful book. Glad that you enjoyed it so much! Thanks for sharing with SYC.
Laura Lane March 3, 2015 at 11:58 AM
Mary Hill June 6, 2015 at 7:08 AM
Hi, thanks again for linking up. I enjoyed this review. I love Titus and the impact it has on women's lives. :)
Here is my pin: https://www.pinterest.com/pin/249246160604354280/ Be sure to repin and like. :)
At Rivercrest Cottage May 24, 2018 at 8:18 AM
Sounds like a great book. I haven't been to her blog, but plan to stop in when I leave here. Thanks for sharing.
Rhonda November 10, 2018 at 5:38 PM
I have this book and it’s really a good one for homemakers. I’m so glad you wrote it,
Kristie Schubert February 10, 2019 at 10:43 PM
I found your blog after you followed me on Twitter. Do you have an Instagram? Well anyway, I’m ordering this book.
Laura Lane February 12, 2019 at 10:27 PM
I am glad you're ordering the book. I think you'll like it. I hope you'll visit me again. I do not have Instagram yet. I still have an old slide phone. The thrifty side of me hasn't caved yet, though I think it would make it easier to list things for sale online. ~smile~
Be blessed, and do come back and visit!

value: Blogger is an American online content management system (CMS) which enables multi-user blogs with time-stamped entries. Pyra Labs developed it before being acquired by Google in 2003.


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Smallest Smykay: Sick of 2009
These pictures are so cute! They really show how much Fletcher is turning into a little boy. Must be the new haircuts!


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lorasater: brilliant cut engagement rings
images The ring which he gifted was Cut 0.44 ct. ROUND
SpotanAnti10-08 06:37 PMWhen you are not that smart how come you applied for EB2 ?? I smell an anti here.!!! Mr.Smuggy - Easy buddy. Relax. I am not as bright as you. I am trying to understand how it works. Since you know it all, what if Company A cant get me a job after i got GC and Company C is ? wallpaper Cut 0.44 ct. ROUND Pear Shaped Engagement Rings
abhisam07-09 06:31 PMYou said your employer is agreable, in that case, If you did not get your EAD before your current EAD expires, you can choose to work for free for those days and try to get paid for it after your EAD comes in effect. Or even if you don't get paid for it, you are building some good will and you are not jeopardizing your job. It will definitely keep you in the good books of this employer. Yes Augustus, thats a good idea. my employer will understand and I will continue to work. but will ask him not to pay me for the duration.
2011 Pear Shaped Engagement Rings Ring Is Beautifully Made By
Cushion cut with Micro-Pave
2010 Brilliant Cut Diamond The ring which he gifted was
SAPGURU06-30 02:36 PMNothing is going to happen...I think rumor is spread by AILA itself so that all people can submit the papers before 2nd July and attorneys can file the cases on 3rd before they go on July 4th vacation, Just watch nothing going to happen in July, No new bulletin. more...
hair Ring Is Beautifully Made By Engagement Ring clad in 18K
2ctw Brilliant cut Simulated
hot Engagement Ring Round Brilliant Cut Diamond
house Princess cut with Micro-Pave Brilliant Cut Cathedral
tattoo Marquise Brilliant Cut Diamond White Gold Engagement Ring
pictures Cushion cut with Micro-Pave ring is crafted in platinum
dresses Round Brilliant Cut Diamond Five stone rilliant cut
makeup Round Brilliant Cut Diamond, Princess cut with Micro-Pave
girlfriend White Gold Engagement Ring Kraiko Round Brilliant Cut
hairstyles 2ctw Brilliant cut Simulated Diamond Engagement Ring –


text:
Whether it be something quirky, fun or practical, we have just the thing you are looking for.
We encourage you to stop by our Blackberry Gift Shop where our artists/artisans are constantly bringing in new items that are sure to please. See you all soon!
Wow! How did it get to be October already!!
No time to waste. Need to shop, shop, shop before October rolls away too!
New items added constantly at the our Blackberry Gift Shop. Every item is hand made by our local artists/artisans. We hope to see you soon.
We welcome you to our Blackberry Gift Shop where there are always new selections of original works from our local artists/artisans. Summer may be winding down but there are always flowers and such for your shopping pleasure at our shop! See you soon.
All our artists and artisans at Blackberry Gift Shop certainly practice it!
Please stop in soon and often to check out the latest fun our artists/artisans have been having!
Rumour has it we are the place you should be heading for!
Blackberry Gift Shop is the place where you will always find great selections of art and handmade crafts. Every item in our artists-managed shop are designed and created with care by local artists and artisans.
Come explore the truth of the rumour! You will be pleasantly surprised.
LAST CALL FOR 2016 MEMBERS
Applications must be received by August 1, 2016, 4 pm at Blackberry Gift Shop or by email notification.
Applicants must attend the jury session to discuss their work August 10, 2016 at 7 pm.
When you shop at the Blackberry Gift Shop, you know you are always getting the best from our local artists and artisans.
All creations are unique and lovingly created for your collection or gift-giving.
Come in often and discover new works.
detail of Water Colour by Elizabeth Wallace
Summertime Blues of the good kind only! At the Blackberry Gift Shop we do not know of any other kind of blues except for the happy bright ones!
In all hues of blue, do come and discover for yourself. New works from local artists are now in the gift shop.
Open everyday 12 noon to 5pm. Closed statutory holidays.
Drop in anytime Monday - Sunday 12 noon to 4pm.
Every item in our Blackberry Gift Shop is created by a local artist/artisan. Never two are the same. Mom would surely love to receive a special gift such as these that you can find in our gift shop.
There is still time! Do not disappoint Mom.
We are open everyday noon to 4pm.
detail of ceramic pendant by Jan Pavlic Falkenberg
From sushi trays to intricate hand woven tea towels, and everything in between, we have new stock from our local artists/artisans now available in our Blackberry Gift Shop.
We encourage you to celebrate spring with us and help support our local artists and art centre.
Yes! At the Blackberry Gift Shop, we do declare Spring has sprung and before you know it, Easter will be upon us!! New selections are available now at our gift shop. Be sure to hop in soon!


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Patent US8030655 - Thin film transistor, display device having thin film transistor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device in a high yield are provided. In the thin film transistor, a gate electrode, a gate insulating film, crystal...http://www.google.com/patents/US8030655?utm_source=gb-gplus-sharePatent US8030655 - Thin film transistor, display device having thin film transistorAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8030655 B2Publication typeGrantApplication numberUS 12/326,495Publication dateOct 4, 2011Filing dateDec 2, 2008Priority dateDec 3, 2007Fee statusPaidAlso published asUS8343821, US20090140259, US20120009742Publication number12326495, 326495, US 8030655 B2, US 8030655B2, US-B2-8030655, US8030655 B2, US8030655B2InventorsShunpei YamazakiOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (77), Non-Patent Citations (13), Referenced by (18), Classifications (25), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetThin film transistor, display device having thin film transistor
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