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Patent US4682302 - Logarithmic arithmetic logic unit - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction...http://www.google.com/patents/US4682302?utm_source=gb-gplus-sharePatent US4682302 - Logarithmic arithmetic logic unitAdvanced Patent SearchPublication numberUS4682302 APublication typeGrantApplication numberUS 06/681,453Publication dateJul 21, 1987Filing dateDec 14, 1984Priority dateDec 14, 1984Fee statusLapsedPublication number06681453, 681453, US 4682302 A, US 4682302A, US-A-4682302, US4682302 A, US4682302AInventorsTim A. WilliamsOriginal AssigneeMotorola, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Non-Patent Citations (12), Referenced by (63), Classifications (14), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetLogarithmic arithmetic logic unitUS 4682302 AAbstract In a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation is provided. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range is provided.
I claim: 1. In a digital signal processing system, a logarithmic arithmetic logic unit for receiving first and second operands and implementing predetermined alogrithms, comprsing:first calculating means for selectively receiving the frist and second operands, each operand being in a logarithmic number representation, and for either multiplying or dividing said operands by effecting an addition or subtraction, respectively, of said first and second operands to provide an intermediate resultant operand at an output, said first calcualting means having a zero value operand detector for detecting when either the first or second operand has a quantized zero logarithmic value and having zero force means for outputting a quantized zero value without effecting said addition or subtraction, thereby minimizing quantization error; and second calculating means having a first input coupled to the output of the first calcualting means for receiving said intermediate resultant operand, and a second input for selectively receiving a third operand in a logarithmic number representation, said second calculating means selectively effecting a subtraction or addition of the intermediate resultant operand with the third operand to provide a final resultant operand in an logarithmic number representation, said second calculating means having bypass means for selectively directly outputting a predetermined one of the intermediate resultant operand or the third operand without effecting an addition or subtraction, said selective coupling being effected without use of a bypass path external to the second calculating means. 2. The logarithmic arithmetic logic unit of claim 1 further comprising coupling means for selectively coupling the final resultant operand to the second input of the second calculating means as the third operand.
4. The logarithmic arithmetic logic unit of claim 1 further comprising:a first data bus coupled to the first calculating means, for selectively coupling logarithmic operands to the first calculating means. 5. The logarithmic arithmetic logic unit of claim 4 wherein said first data bus is further coupled to the second input of the second calculating means, for selectively coupling logarithmic operands to the second calculating means.
7. The logarithmic arithmetic logic unit of claim 1 further comprising:a second data bus coupled to the first calculating means, for selectively coupling logarithmic operands to the first calculating means. 8. The logarithmic arithmetic logic unit of claim 7 wherein said second data bus is further coupled to the second input of the second calculating means, for selectively coupling logarithmic operands to the second calculating means.
10. A method of processing digital operands in logarithmic number representation, comprising the steps of:selectively receiving first and second operands in logarithmic number representation; effecting either multiplication or division of the first and second operands by addition or subtraction, respectively, to provide an intermediate resultant operand in logarithmic number representation; selectively receiving a third operand in logarithmic number representation; and either directly outputting one of said intermediate resultant operand or said third operand to provide a final resultant operand in logarithmic number representation in response to detecting either the third operand or the intermediate resultant operand having a quantized zero value; or subtracting or adding the intermediate resultant and third operands in logarithmic number representation to provide a final resultant operand in logarithmic number representation. 11. The method of claim 10 further comprising the step of:selectively coupling the final resultant operand as the third operand to the second calculating means. Description
CROSS REFERENCE TO RELATED APPLICATIONS 1. Application Ser. No. 06/681,455 entitled "A METHOD OF ADDING AND SUBTRACTING NUMBERS IN LOGARITHMIC REPRESENTATION", filed simultaneously herewith by Tim A. Williams.
TECHNICAL FIELD This invention relates to signal processors, and more particularly, to a logarithmic arithmetic logic unit (ALU) for use in a digital signal processing system.
BACKGROUND OF THE INVENTION Digital signal processors have previously selectively utilized both linear and logarithmic number representations in an effort to perform signal processing as fast and efficiently as possible. For example, finite impulse response (FIR) filters have been implemented by using logarithms to perform multiplication and division operations which can be readily accomplished by only adding and subtracting, respectively, numbers in logarithmic representation. However, addition and subtraction operations are much more complicated to perform in a logarithmic system rather than in a linear number system. Therefore, others have typically converted from logarithmic to linear to perform addition and then, if necessary, back to a logarithmic number representation to accomplish a multiplication or division operation. By effecting numerous conversions of number systems, the inherent advantages of the logarithmic number representation with respect to multiplication and division operations are typically lost.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an improved logarithmic arithmetic logic unit.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates in block diagram form a signal processor known in the art for use with the present invention;
DETAILED DESCRIPTION OF THE PRESENT INVENTION Shown in FIG. 1 is a signal processor 10 for implementing a plurality of algorithms commonly used in digital signal processing applications. A stack register 11 is coupled to a program counter 12 for transfer of data between program counter 12 and stack register 11. An output of program counter 12 is coupled to an input of a program ROM 13 having an output thereof coupled to an input of an instruction register 15. A first output of instruction register 15 is coupled to a first data bus labeled "X Data Bus". The X data bus is coupled to a first input of a plurality of output registers 16 and to a first input of an address controller 17. An arithmetic logic unit (ALU) 18 and a random access memory circuit 20 each has, first terminals coupled to the X data bus. The X data bus is also coupled to a second input of a digital to analog converter 21, to a second output of a plurality of input registers 23 and to a second output of an analog to digital converter 22. A second output of instruction register circuit 15 is coupled to a second data bus labeled "Y Data Bus", and a third output of instruction register circuit 15 is coupled to a control terminal of program counter 12. The Y data bus is coupled to a second input of address controller 17, to a second terminal of ALU 18, to a second terminal of memory circuit 20, to a second input of the plurality of output registers 16, to a first input of digital to analog converter 21, to a first output of analog to digital converter 22 and to a first output of the plurality of input registers 23. Address controller 17 has a first output coupled to a first address bus labeled "X Address Bus" and a second output coupled to a second address bus labeled "Y Address Bus". The X address bus is coupled to a third input of output registers 16, to a third input of digital to analog converter 21, to a first input of the input registers 23, to a first input of analog to digital converter 22 and to a third input of memory circuit 20. Similarly, the Y address bus is coupled to a fourth input of output registers 16, to a fourth input of digital to analog converter 21, to a second input of analog to digital converter 22, to a second input of input registers 23 and to a fourth input of random access memory circuit 20. Analog to digital converter 22 receives a plurality of analog input signals at a third input thereof, and digital to analog converter 21 provides a plurality of analog output signals at an output thereof. A plurality of digital inputs are coupled to a third input of input registers 23, and output registers 16 provide a plurality of digital outputs at an output thereof.
An illustration of a logarithmic number representation is provided in FIG. 2(a). An entire number is shown containing N bits beginning with bit X.sub.0 and ending with bit X.sub.N-1. The logarithmic representation of the number shown in FIG. 2(a) and denoted as "X" is:
X=signum (X')log.sub.D where D represents the base of the number system, the "prime" symbol represents the real number system, and "signum" represents the sign of the function. The first bit X.sub.0 is a sign bit, X.sub.S, and the remaining bits are represented as X.sub.L as shown by the second representation of the N bit number in FIG. 2(a). The sign bit X.sub.S is zero if the value of X' is positive and is one if the value of X' is negative. This number representation is a sign magnitude representation. In a preferred form, the bits comprising X.sub.L represent a two's complement number. The second bit X.sub.1, labeled X.sub.MS, represents the sign of the number X.sub.L as shown by the last detailed representation of the N bit number in FIG. 2(a). The remaining bits of X.sub.L are represented as X.sub.M and theoretically contain an integer portion and a fractional portion.
Shown in FIG. 2(b) is an example of the range of real numbers which may be represented by the number system of FIG. 2(aall numbers greater than +1 or less than -1, X.sub.MS is negative. For all numbers falling within either the range of +(1/M) to +1 or the range of -(1/M) to -1, X.sub.MS is positive. The largest real number which can be represented by X.sub.M is 2(.sup.N- 2-1or B. The largest real number which can be represented by X.sub.L is D.sup.-B which is equal to M. The smallest real number which can be represented by X.sub.L is +D.sup.+ (B) which is equal to (1/M). Therefore, X.sub.L has a range of values between +M and +(1/M). The base of the number system, D, is defined to always be less than one. Upon reviewing FIG. 2 (a), it should be apparent why two separate sign bits are needed in this number represenation. The first sign bit X.sub.S extends the representable range of numbers not only to positive real values but also to negative real values. The second sign bit X.sub.MS provides the ability to distinguish between numbers above or below +1 or -1. If all bits which comprise X.sub.L have a value of zero, the real number represented is 1. As X.sub.L increases in the positive direction, the real value number represented decreases toward zero. Similarly, as X.sub.L increases in the negative direction, the real value number represented increases toward +M.
To perform an addition or subtraction in a logarithmic number system is somewhat more difficult to implement than multiplication and division. However, the process of converting from a logarithmic to a linear system for the purpose of addition and subtraction operations is even more cumbersome than performing the addition and subtraction in the logarithmic system. Therefore, a discussion of the steps required to effect an addition and a subtraction arithmetic operation via logarithms will be discussed. Shown in Appendix One is a set of exponential equations derived from the addition of two linear numbers P' and Z' to provide a sum Q'. Equations (2) thru (9) define the linear/logarithmic relationship associated with addends P' and Z' and sum Q'. For example, equation 2 expresses the logarithmic value P.sub.L as a log to the base D of the absolute value of the magnitude of linear number P'. Equations 2-9 define the sign and magnitude logarithmic representations of P', Z' and Q' Equation 10 is a restatement of equation 1 in terms of sign and magnitude representations. Substituting previously defined values, equation 11 provides the logarithmic relationship of the sum of linear numbers P' and Z'. The resulting logarithmic sum depends upon four possible relationships of P.sub.S and Z.sub.S. In the first possibility, assume that the sign of numbers P and Z are equal, whether both are positive or both are negative. Therefore, the sign of the resulting sum will be the same as the sign of linear number P' (equation (13). Equation (15) defines the logarithmic sum Q.sub.L in terms of the logarithm of the linear numbers P' and Z'. The value of the logarithmic sum depends upon the relative magnitudes of logarithmic values P.sub.L and Z.sub.L. If the value of D.sup.P L is greater than the value of D.sup.Z L, the logarithmic sum, Q.sub.L, is defined by equation (18). However, if the maximum value of Z.sub.L is greater than the maximum value of P.sub.L, the logarithmic sum Q.sub.L is defined by equation (21).
The second possible relationship of P.sub.S and Z.sub.S is the case where the sign of P is positive and the sign of Z is negative. In this situation, the sign of the sum depends upon the relationship of the values of P.sub.L and Z.sub.L as shown by equations (24) and (28). When the real value represented by addend P.sub.L is greater than the real value represented by addend Z.sub.L, the value of the logarithmic sum is expressed by equation (27). However, when the real value represented by addend Z.sub.L is greater than the real value represented by addend P.sub.L, the value of the logarithmic sum is expressed by equation (32). The derivation of equations (27) and (32)is illustrated in detail by the intervening equations.
The third possible relationship of P.sub.S and Z.sub.S is the case where the sign of P is negative and the sign of Z is positive. Once again, the sign of the sum depends upon the relationship of the values of P.sub.L and Z.sub.L and is stated in equations (35) and (39) for the cases when the maximum value is P.sub.L and Z.sub.L, respectively. When the real value represented by addend P.sub.L is greater than the real value represented by addend Z.sub.L, the value of the logarithmic sum is expressed by equation (38). However, when the real value represented by addend Z.sub.L is greater than the real value represented by addend P.sub.L, the value of the logarithmic sum is expressed by equation (43). The derivation of equations (38) and (43) is also illustrated in detail by intervening equations.
The fourth possible relationship of P.sub.S and Z.sub.S is the case where the signs are opposite and the logarithmic values of the numbers P and Z are equal. When this situation occurs for an addition operation, the sum should be zero. Therefore, the value of the sign of the sum, Q.sub.S, is arbitrary. However, the number zero does not exist in a logarithmic system by definition. As a result, a quantized minimum value must be substituted for zero. Equation (45) defines the minimum value as being equal to 1/M. A discussion of how to minimize errors associated with this quantization error will be provided below.
Shown in Appendix Two is an illustration of the mathematical relationships between logarithmic and linear numbers in a subtraction operation. Equation (1) illustrates the subtraction of two linear numbers P' and Z' to provide a linear difference Q'. Equations (2) thru (9) define the linear/logarithmic relationship associated with minuend P', subtrahend Z' and resultant Q'. Equation (10) is a restatement of equation (1) in terms of sign and magnitude representations. Substituting previously defined values, equation (11) provides the logarithmic relationship of the difference of linear numbers P' and Z'. The resulting logarithmic difference also depends upon four possible relationships of P.sub.S and Z.sub.S. In the first possibility, assume that the signs of the linear numbers P' and Z' are equal, whether both are positive or negative. If the maximum value of P.sub.L is greater than the maximum value of Z.sub.L, the sign of the resulting difference will be the same as the sign of number P' as shown in equation (13). Equations (14) thru (16) illustrate the derivation of the logarithmic value of the difference of numbers P' and Z' which is provided in equation (17) for the above stated conditions. If the maximum value of P.sub.L is less than the maximum value of Z.sub.L, the sign of the resulting difference will be the negative of number P' as shown in equation (18). Under this condition, equations (19) and (20) illustrate the derivation of the logarithmic value of the difference of numbers P' and Z' which is provided in equation (21).
The second possible relationship of P.sub.S and Z.sub.S is the case where the sign of P is positive and the sign of Z is negative. In this situation, the sign of the difference is positive regardless which number has the greater magnitude. Equation (26) defines the value of the logarithmic difference when the maximum value of P.sub.L is greater than the maximum value of Z.sub.L, and equation (30) defines the value of the logarithmic difference when the maximum value of Z.sub.L is greater than the maximum value of PL. The derivation of equations (26) and (30) is shown by preceding equations in Appendix Two.
The third possible relationship of P.sub.S and Z.sub.S is the case where the sign of P is negative and the sign of Z is positive. In this situation, the sign of the difference is negative regardless which number has the greater magnitude. Equation 36 defines the value of the logarithmic difference when the maximum value of P.sub.L is greater than the maximum value of Z.sub.L, and equation (40) defines the value of the logarithmic difference when the maximum va1ue of Z.sub.L is greater than the maximum value of P.sub.L. The derivation of equations (36) and (40) is also shown by preceding equations.
The fourth possible relationship of P.sub.S and Z.sub.S is the case where the signs are equal and the logarithmic values of the numbers P and Z are equal. When this situation occurs in subtraction, the difference should be zero. Therefore, the value of the sign of the resulting difference is arbitrary. However, the number zero must again be quantized and a minimum value substituted for zero. Again, the value of 1/M is chosen as the minimum value in this situation as shown by equation 42.
In theory, an addition or subtraction may be readily accomplished by obtaining the value of either P.sub.L or Z.sub.L and adding a correction factor. Furthermore, the correction factor may be easily identified depending upon the sign values as always being either log.sub.D (1+D.sup.Y) or log.sub.D (1-D.sup.Y) where Y is the magnitude of the difference between P.sub.L and Z.sub.L. The present invention involves the use of a logarithmic number system where arithmetic calculations are performed by storing the derived correction factors in any of a plurality of possible ways to selectively accomplish an arithmetic operation. Since use of the present invention with processor 10 of FIG. 1 requires that all analog inputs received by A/D converter 22 be converted from real values to logarithmic values by a converter (not shown) in addition to an analog to digital conversion. Another way to accomplish this conversion is to use a conventional modified codec to effect both the A/D and the linear/logarithmic conversion. To effect a conversion back to real analog units, a conversion is made by D/A converter 21 to analog units and a conversion from logarithmic values to linear values is made by a converter not shown. However, it should be readily understood that the present invention may also use conversion representations other than purely logarithmic such as the conventional A law/Mu law logarithmic approximation code by using a conventional codec.
In operation, data is coupled to multiplier/divider 30 via the X and Y data buses. Multiplexers 26 and 27 respectively choose which data bus is coupled to latch circuits 28 and 29 in response to the "AMC" and "BMC" control signals, respectively. Latch circuits 28 and 29 respectively hold the coupled data in response to control signals ALC and BLC, respectively. Logic circuit 40 forms the reciprocal or one's complement of the logarithmic number A.sub.L in response to the "A recip" control signal. Logic circuit 41, in response to the "One" control signal, automatically forces the output thereof to be equal to a real value of one which logarithmically is represented by all zeroes. Logic circuit 42 functions to detect when an output of zero which is represented by 1/M is present and provides the AZD status signal in response thereto. Logic circuit 42 detects a zero and couples the zero detect signal AZD to the zero force logic circuit 52 so that no additional quantization error is realized by utilizing a value other than zero. Either the value of A or the one's complement of A is coupled to the "A" input of adder 50. In contrast, the B number side operates similarly with circuits 46, 47 and 48 respectively performing analogously to circuits 40, 41 and 42 described above. However, the B number side also includes sign logic circuit 45 which functions to make the B input number either positive or negative one. Typical DSP alogrithms require that a signum operation be effected in only one of the two number paths A and B although it should be readily understood that a sign logic circuit such as circuit 45 may be coupled between multiplexer circuit 26 and latch circuit 28 if necessary to perform an algorithm. Since a multiplication or divivion may be respectively effected by an addition or subtraction using logarithmic arithmetic, adder circuit 50 which selectively adds or subtracts numbers A and B is used to effect both multiplication and division in response to the multiply/divide (Mul/Div) control signal having a high or a low logic state, respectively. Adder 50 may be implemented as a conventional two's complement adder which performs either addition or subtraction of numbers A and B. Since reciprocal logic circuits 40 and 46 perform a reciprocal operation by forming a one's complement when enabled, a "1" needs to be coupled to a carry input of adder 50 to effect a two's complement and a subtraction of the reciprocaled operand. If both operands are reciprocaled, a two's complement of both operands may be formed to offset the effect of circuits 40 and 46 and allow two's complement adder 50 to perform an addition. Should an overflow or an underflow of data result from the calculation provided by adder circuit 50, detection and correction logic circuit 51 detects such a condition, corrects the condition and provides a status signal indicating an overflow/underflow condition. The status signal is coupled to condition code register 37 of FIG. 3 for other use as previously mentioned. Furthermore, if a zero is detected by either or both of circuits 42 and 48, 1/M force circuit 52 forces a real value of 1/M at the P output of circuit 52. Therefore, multiplier/divider circuit 30 eliminates additional quantization error associated with the use of the number zero in logarithmic arithmetic.
Shown in FIG. 5 is adder/subtractor circuit 32 of FIG. 3 including multiplexer circuit 33 controlled by a control signal labeled "ZMC" and latch circuit 34 controlled by a control signal labeled "ZLC". Adder/subtractor circuit 32 implements a logarithmic addition or subtraction operation. The output of multiplier/divider circuit 30 labeled "P" is coupled to an input of a zero (1/M) detect logic circuit 56 which is analogous to zero (1/M) detect logic circuits 42 and 48 of FIG. 4. Zero (1/M) detect logic circuit 56 provides a zero detect signal labeled "PZD" in response to detecting the 1/M condition and passes the output signal P to a first input, of a function logic circuit 58 labeled "GFCN" for a G function which is an arbitrary labeling of the functions of computing the absolute value of the difference between P and Z. Function logic circuit 58 also provides a switch control signal labeled "SW" to be explained below. As shown by the equations derived in Appendices One and Two, a logarithmic sum and difference always comprise a term which uses the difference between the two numbers D.sup.P L-Z.sub.L and D.sup.Z -P.sub.L. An input of a zero force circuit 60 is coupled to an output of the Z latch circuit 34 to provide an output of zero in response to a zero detect signal labeled "Zero" coupled to a control input thereof. An output of zero force circuit 60 is coupled to an input of a zero detect circuit 62 which provides a Z zero detect signal labeled "ZZD". The Z zero detect signal is coupled to condition code register 37 for storage. An output of zero detect circuit 62 is coupled to a second input of function logic circuit 58. Function logic circuit 58 receives zero detect signals "PZD" and "ZZD" at first and second control inputs, respectively. Function logic circuit 58 also provides a "P=Z" status signal and a switch control signal labeled "SW" at first and second outputs thereof. A third output of function logic circuit 58 provides an overrange control signal which is coupled to a first input of a programmable logic array (PLA) 63. A fourth output of function logic circuit 58 provides the absolute value of the difference between P and Z and is coupled to a second input of PLA 63. An add or subtract control signal (ADD/SUB), a P sign control signal (PS) and a Z sign control signal (ZS) are respectively coupled to third, fourth and fifth inputs of PLA 63. The "P=Z" status signal provided by function logic circuit 58 is coupled to a sixth input of PLA 63, and the switch control signal also provided by function logic circuit 58 is coupled to a seventh input of PLA 63. PLA 63 provides a bypass control signal at a first output and a zero force signal labeled "Q Force" at a second output. A third output of PLA 63 is coupled to a first input labeled "H" of a two's complement adder circuit 64. A multiplexer 65 has a first input coupled to the output of zero detect logic circuit 56 for receiving operand P and a second input coupled to the output of zero detect logic circuit 62 for receiving operand Z. A control input of multiplexer 65 is coupled to the switch control signal provided by PLA 63. An output of multiplexer 65 is coupled to a second input of adder circuit 64 labeled "J". The bypass control signal provided by PLA 63 is coupled to a control input of adder circuit 64. An output of adder circuit 64 is coupled to an input of an overflow/underflow detection and correction logic circuit 66. Logic circuit 66 provides an adder overflow status signal at a first output and an adder underflow status signal at a second output. A third output of logic circuit 66 is coupled to a first input of a zero force circuit 67. A second input of zero force circuit 67 receives the zero force signal "Q Force" provided by PLA 63. An output of zero force circuit 67 provides the output Q.
In operation, operands P and Z are coupled to function logic circuit 58. If either P or Z are detected as being zero by zero detect circuits 56 and 62, respectively, function logic circuit 58 in response to either of the PZD or ZZD control signals generates a switch control signal which is used by multiplexer 65 to couple the nonzero operand, if any, to the J input of adder circuit 64. Simultaneously, the switch control signal provided by function logic circuit 58 is coupled to PLA 63 which provides a bypass signal in response thereto. The bypass signal is coupled to adder 64 which causes, the operand at the J input of adder 64 to be directly fed through to the Q output. When neither P nor Z are zero, the switch signal provided by function logic circuit 58 is coupled to multiplexer 65 which couples the input operand having the greatest real value to the output thereof. The output value of function logic circuit 58 is used to index a predetermined value in PLA 63 which is coupled as an input to the H input of adder circuit 64. Function logic circuit 58 forms the magnitude of the difference of operands P and Z. The function of logic circuit 58 is accomplished by first computing the values of P-Z and Z-P by using two subtractor circuits. Logic is used as described below to then couple the positive value of the two values to the output of function logic circuit 58. If the difference value is so great that the value is not indexed by PLA 63, the overrange signal causes PLA 63 to provide a predetermined output indicating this condition. If PLA 63 provides a signal "Q Force", 1/M force circuit 67 automatically outputs a minimum value as the value of Q. The output of PLA 63 which is coupled to the H input of adder 64 represents the term log.sub.D (1-D.sup.X) of Appendix One where X is either P.sub.L -Z.sub.L or Z.sub.L -P.sub.L. Multiplexer 65 couples either the operand P.sub.L or Z.sub.L representing the greater real number to the J input of adder circuit 64. If an overflow or underflow of data results from the addition, correction logic circuit 66 forces a correction before the logarithmic sum is coupled as operand Q to the output of circuit 67.
Shown in FIG. 6 is a block diagram of function logic circuit 58 of FIG. 5. A logic circuit 70, comprising in part two subtractor circuits as mentioned above, is provided for calculating the difference between operands P and Z and for providing an absolute value of the operands. A first input of logic circuit 70 is coupled to operand P, and a second input of logic circuit 70 is coupled to operand Z. Logic circuit 70 also provides a first status signal labeled "Z>P" to indicate whether the magnitude of Z is greater than the magnitude of P. A second status signal labeled "equal" is provided by logic circuit 70 to indicate if the magnitudes of P and Z are equal. A third status signal labeled "Over Range" is provided by logic circuit 70 to indicate if the magnitude of the difference between P and Z is greater than the maximum number of bits being used. An output of logic circuit 70 provides the absolute value of the difference between P and Z. A function logic circuit 72 labeled "F1" provides the switch "SW" control signal at an output thereof. A first input of logic circuit 72 receives a P magnitude sign bit labeled PMS, and a second input receives a Z magnitude sign bit labeled ZMS which respectively represent the sign of the two's complement numbers P.sub.L and Z.sub.L. The "Over Range" status signal provided by logic circuit 70 is coupled to a third input of logic circuit 72. The first status signal (Z>P) provided by logic circuit 70 is coupled to a fourth input of logic circuit 72. The P zero detect (PZD) and Z zero detect (ZZD) status signals provided by zero detect circuits 56 and 62 of FIG. 5, respectively, are respectively coupled to fifth and sixth inputs of logic circuit 72. An output of logic circuit 72 provides the switch "SW" control signal which is coupled to multiplexer circuit 64.
In operation, both logic circuits 70 and 72 are required to implement the G function logic circuit 58. Logic circuit 70 provides the absolute value of the difference between P and Z by performing the operations P.sub.L -Z.sub.L and Z.sub.L -P.sub.L. A logic determination is made as to whether Z is greater than P, is equal to P or whether the difference is outside the range of the number representations. Depending upon which of P and Z is greater, one of the calculated differences is outputted as the absolute value of P minus Z. Near simultaneously, logic circuit 72 provides the SW control signal which allows multiplexer 65 to switch the input operand having the greater real value. Logic circuit 72 receives the Z and P zero detect signals to determine whether either or both of Z and P are zero. Logic circuit 72 receives from logic circuit 70 the over range control signal and the Z>P control signal indicating that Z is larger than P in magnitude. Logic circuit 72 also receives sign magnitude bits P.sub.MS and Z.sub.MS which provide the sign magnitudes associated with operands P and Z. The sign magnitude bits are used to determine the operand of greater real value. Logic circuit 72 uses the sign bit magnitude to determine whether or not the switch signal will switch operand P or operand Z to adder 64.
Shown in FIG. 7(a) is a block diagram of a preferred form of PLA 63 of FIG. 5. A function logic circuit 76 labeled "F2" has a plurality of inputs for receiving a plurality of control signals. An addition or subtraction mode control signal (ADD/SUB) is coupled to a first input. Sign control signals for operands P and Z labeled "PS" and "ZS", respectively, are coupled to second and third inputs thereof. The equal operand status signal labeled "Equal" provided by logic circuit 70 indicating that operands P and Z have an equal magnitude is coupled to a fourth input of logic circuit 76. Switch control signal SW provided by logic circuit 72 is coupled to a fifth input of logic circuit 76. Logic circuit 76 provides a FP/FM table select signal, a Q.sub.S sign signal and the minimum value Q Force signal.
In operation, logic circuit 76 generates the sign of the output signal Q.sub.S. The Q force signal of logic circuit 76 also determines whether a value of 1/M will be forced onto the output. The FP/FM signal provided by logic circuit 76 determines which one of two tables (not shown) of values existing in PLA 63 is used to provide the H operand provided by PLA 63. This is implemented as can be seen from the equations in Appendices I and II by using a positive table (FP) of PLA values if a logarithmic addition operation is occuring and the signs of P and Z are the same. Otherwise, in a logarithmic addition operation a negative table of values (FM) in the PLA table is used. For example, if a logarithmic addition is occurring and the signs of P and Z are not equal, the FM table is used to provide either log.sub.D (1-D.sup.(Z.sbsp.L.sup.-P.sbsp.L.sup.)) or log.sub.D (1-D.sup.(Z.sbsp.L.sup.-P.sbsp.L.sup.)) depending upon the relative magnitudes of P.sub.L and Z.sub.L. The positive and negative tables are used in an analogous manner to provide the H operand for a logarithmic subtraction operation.
In operation, logic circuit 77 generates the bypass signal by implementing the truth table illustrated in Appendix Three. An "X" in the truth table represents an irrelevent logic state. When the bypass signal is provided by circuit 77, the value of H is bypassed in adder circuit 64 and the J input operand of adder 64 is coupled straight through to the Q output of circuit 67. The bypass signal is generated when the absolute value of the differential between the logarithmic operands P and Z is greater than the last value of H represented in the positive and negative tables of PLA 63. The last value is where PLA 63 is truncated and is a function of the base of the logarithmic number representation and the number of bits comprising the operands. Basically, when the differential between operands P and Z becomes greater than the last value indexed in PLA 63, the contribution of the H operand to the outputted Q operand is minuscule. Therefore, the H operand is bypassed totally. The number is provided by logically comparing the absolute value of P-Z to a predetermined coded value which is the last non-zero index into PLA 80. The bypass signal is also provided by circuit 77 when the overrange signal is active indicating that the value of the H operand is not valid.
Appendix I Q'=P'+Z'                                                   (1)
P.sub.L =log.sub.D
Z.sub.L =log.sub.D
Q.sub.L =log.sub.D
Q.sub.s  Q.sub.s D.sup.Q.sub.L =P.sub.s D.sup.P.sub.L +Z.sub.s D.sup.Z.sub.L (11)
CASE 1: P.sub.s =Z.sub.s
if MAX (P.sub.L, Z.sub.L)=Z.sub.L,
CASE 2: P.sub.s is positive, Z.sub.s is negative
if MAX (P.sub.L, Z.sub.L)=P.sub.L,
CASE 3: P.sub.s is negative, Z.sub.s is positive
if MAX (P.sub.L, Z.sub.L)=Z.sub.L
CASE 4: P.sub.s =Z.sub.s and P.sub.L =Z.sub.L
Appendix II Q'=P'-Z'                                                   (1)
Q.sub.s  Q.sub.s D.sup.Q.sub.L =P.sub.s D.sup.P.sub.L -Z.sub.s D.sup.Z.sub.L (11)
if MAX (P.sub.L, Z.sub.L)=P.sub.L
______________________________________APPENDIX III                      OVERRANGE  PZD    ZZD      LAST VALUE                                BYPASS______________________________________1          X      X        X         10          1      X        X         10          0      1        X         10          0      0        1         1______________________________________
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4531124 *Dec 4, 1981Jul 23, 1985Thomson CsfDevice for processing logarithmic signals, and its application to a frequency diversity radarUS4555768 *Jun 7, 1983Nov 26, 1985Rca CorporationDigital signal processing system employing logarithms to multiply and divideDE3326044A1 *Jul 20, 1983Feb 7, 1985Licentia GmbhMethod for carrying out the Galois field multiplication or division and circuit arrangement for carrying out the methodJPS5572252A * Title not available* Cited by examinerNon-Patent CitationsReference1E. Hall et al., "Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications" IEEE Trans. On Comp. 2/1970, pp. 97-105.2 *E. Hall et al., Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications IEEE Trans. On Comp. 2/1970, pp. 97 105.3J. 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Disclosure Bull., vol. 14, No. 10, Mar. 1972, pp. 2930 2933.10Sofer et al., Parallel Pipeline Organization of Execution Unit, IBM Tech. Disclosure Bull., vol. 14, No. 10, Mar. 1972, pp. 2930-2933.11T. Brubaker et al., "Multiplication Using Logarithms Implemented With Read-Only Memory", IEEE Trans. on Comp. vol. C-24, No. 8, 8/1975, pp. 761-765.12 *T. Brubaker et al., Multiplication Using Logarithms Implemented With Read Only Memory , IEEE Trans. on Comp. vol. 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deviceUS8549055Mar 3, 2010Oct 1, 2013Altera CorporationModular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitryUS8577951Aug 19, 2010Nov 5, 2013Altera CorporationMatrix operations in an integrated circuit deviceUS8589463Jun 25, 2010Nov 19, 2013Altera CorporationCalculation of trigonometric functions in an integrated circuit deviceUS8589465May 8, 2013Nov 19, 2013Altera CorporationDigital signal processing circuit blocks with support for systolic finite-impulse-response digital filteringUS8601044Mar 2, 2010Dec 3, 2013Altera CorporationDiscrete Fourier Transform in an integrated circuit deviceUS8620977Aug 7, 2013Dec 31, 2013Altera CorporationModular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitryUS8620980Jan 26, 2010Dec 31, 2013Altera CorporationProgrammable device with specialized multiplier blocksUS8626815Mar 3, 2009Jan 7, 2014Altera CorporationConfiguring a programmable integrated circuit device to perform matrix multiplicationUS8645449Mar 3, 2009Feb 4, 2014Altera CorporationCombined floating point adder and subtractorUS8645450Mar 2, 2007Feb 4, 2014Altera CorporationMultiplier-accumulator circuitry and methodsUS8645451Mar 10, 2011Feb 4, 2014Altera CorporationDouble-clocked specialized processing block in an integrated circuit deviceWO1997008611A1 *Aug 7, 1996Mar 6, 1997Motorola IncMethod and system for performing an iir filtering operationWO1997008612A1 *Aug 7, 1996Mar 6, 1997Motorola IncMethod and system for performing an l2 norm operation* Cited by examinerClassifications U.S. Classification708/670, 708/620, 708/650, 708/517International ClassificationG06F7/48, G06F1/03, G06F7/556Cooperative ClassificationG06F7/556, G06F2207/3868, G06F1/0307, G06F7/4833European ClassificationG06F7/556, G06F1/03D, G06F7/483LLegal EventsDateCodeEventDescriptionSep 28, 1999FPExpired due to failure to pay maintenance feeEffective date: 19990721Jul 18, 1999LAPSLapse for failure to pay maintenance feesFeb 9, 1999REMIMaintenance fee reminder mailedDec 15, 1994FPAYFee paymentYear of fee payment: 8Nov 14, 1990FPAYFee paymentYear of fee payment: 4Dec 14, 1984ASAssignmentOwner name: MOTOROLA INC., SCHUAMBURG ILLINOIS A CORP OF DEFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WILLIAMS, TIM A.;REEL/FRAME:004345/0781Effective date: 19841210RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


text:
Patent US4399424 - Semiconductor films of tin oxide doped with alumins; hydrogen sulfide - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA semiconductor gas sensor comprises an insulating substrate (11) on which a resistive heater track (15) coupled to a pair of electrodes (12, 14) is deposited. A film (16) of a semiconductive metal oxide, typically a doped oxide, is ion-plated on to the assembly so as to contact the resistive track (15)...http://www.google.com/patents/US4399424?utm_source=gb-gplus-sharePatent US4399424 - Semiconductor films of tin oxide doped with alumins; hydrogen sulfideAdvanced Patent SearchPublication numberUS4399424 APublication typeGrantApplication numberUS 06/308,290Publication dateAug 16, 1983Filing dateOct 5, 1981Priority dateOct 7, 1980Fee statusLapsedAlso published asCA1178824A1Publication number06308290, 308290, US 4399424 A, US 4399424A, US-A-4399424, US4399424 A, US4399424AInventorsLeslie J. RigbyOriginal AssigneeItt Industries, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (3), Referenced by (77), Classifications (6), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor films of tin oxide doped with alumins; hydrogen sulfideUS 4399424 AAbstract A semiconductor gas sensor comprises an insulating substrate (11) on which a resistive heater track (15) coupled to a pair of electrodes (12, 14) is deposited. A film (16) of a semiconductive metal oxide, typically a doped oxide, is ion-plated on to the assembly so as to contact the resistive track (15) and a further electrode (13). Exposure of the device to a particular gas, e.g. hydrogen sulphide, reduces the resistivity of the semiconductive film (16), this change being detected via an amplifier circuit (not shown). In an alternative version of the sensor (FIGS. 5a, 5b and 6) the heater is disposed under a dielectric layer, the semiconductive film being ion-plated onto the dielectric layer and electrodes therein.
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dielectric films which are Hf-O richUS7369435Aug 30, 2005May 6, 2008Micron Technology, Inc.Write once read only memory employing floating gatesUS7402876Aug 31, 2004Jul 22, 2008Micron Technology, Inc.Zr� Sn�Ti�O filmsUS7405454Aug 26, 2005Jul 29, 2008Micron Technology, Inc.Electronic apparatus with deposited dielectric layersUS7410668Aug 31, 2004Aug 12, 2008Micron Technology, Inc.Introducing gas into a closed inner chamber within an outer chamber through a gas-distribution fixture;operating a pump to evacuate gas from the outer chamber through the gas-distribution fixture, changing relative position of the gas-distribution fixture and a substrate to form the closed inner chamberUS7410917Aug 29, 2005Aug 12, 2008Micron Technology, Inc.Atomic layer deposited Zr-Sn-Ti-O films using TiI4US7429515Jan 14, 2005Sep 30, 2008Micron Technology, Inc.Low-temperature grown high quality ultra-thin CoTiO3 gate dielectricsUS7439194Jan 7, 2005Oct 21, 2008Micron Technology, Inc.Lanthanide doped TiOx dielectric films by plasma oxidationUS7441440 *Apr 23, 2004Oct 28, 2008Sacmi Cooperativa Meccanici Imola Soc. Coop. A.R.L.Thin semiconductor film gas sensor deviceUS7554161Aug 31, 2004Jun 30, 2009Micron Technology, Inc.HfAlO3 films for gate dielectricsUS7560793Aug 30, 2004Jul 14, 2009Micron Technology, Inc.Atomic layer deposition and conversionUS7563730Aug 31, 2006Jul 21, 2009Micron Technology, Inc.Hafnium lanthanide oxynitride filmsUS7589029May 2, 2002Sep 15, 2009Micron Technology, Inc.Atomic layer deposition and conversionUS7611959Mar 21, 2005Nov 3, 2009Micron Technology, Inc.Zr-Sn-Ti-O filmsUS7622355Jun 28, 2006Nov 24, 2009Micron Technology, Inc.Write once read only memory employing charge trapping in insulatorsUS7662729Apr 28, 2005Feb 16, 2010Micron Technology, Inc.Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layerUS7670646Jan 5, 2007Mar 2, 2010Micron Technology, Inc.inner chamber has a smaller volume than the outer chamber, which leads to less time to fill and purge during cycle times for deposition of materials such as alumina; making integrated circuitsUS7687409Mar 29, 2005Mar 30, 2010Micron Technology, Inc.Atomic layer deposited titanium silicon oxide filmsUS7687848Jul 31, 2006Mar 30, 2010Micron Technology, Inc.Memory utilizing oxide-conductor nanolaminatesUS7709402Feb 16, 2006May 4, 2010Micron Technology, Inc.Conductive layers for hafnium silicon oxynitride filmsUS7728626Sep 5, 2008Jun 1, 2010Micron Technology, Inc.Memory utilizing oxide nanolaminatesUS7804144Jul 21, 2008Sep 28, 2010Micron Technology, Inc.Low-temperature grown high quality ultra-thin CoTiO3 gate dielectricsUS7869242Apr 28, 2009Jan 11, 2011Micron Technology, Inc.Transmission lines for CMOS integrated circuitsUS7872291Sep 17, 2007Jan 18, 2011Round Rock Research, LlcEnhanced atomic layer depositionUS7923381Jul 11, 2008Apr 12, 2011Micron Technology, Inc.Methods of forming electronic devices containing Zr-Sn-Ti-O filmsUS7989362Jul 20, 2009Aug 2, 2011Micron Technology, Inc.Hafnium lanthanide oxynitride filmsUS8026161Aug 30, 2001Sep 27, 2011Micron Technology, Inc.Highly reliable amorphous high-K gate oxide ZrO2US8067794May 3, 2010Nov 29, 2011Micron Technology, Inc.Conductive layers for hafnium silicon oxynitride filmsUS8076249Mar 24, 2010Dec 13, 2011Micron Technology, Inc.Structures containing titanium silicon oxideUS8093638Jan 9, 2007Jan 10, 2012Micron Technology, Inc.Systems with a gate dielectric having multiple lanthanide oxide layersUS8125038Jul 11, 2005Feb 28, 2012Micron Technology, Inc.Nanolaminates of hafnium oxide and zirconium oxideUS8178413Sep 23, 2010May 15, 2012Micron Technology, Inc.Low-temperature grown high quality ultra-thin CoTiO3 gate dielectricsUS8188533Nov 20, 2009May 29, 2012Micron Technology, Inc.Write once read only memory employing charge trapping in insulatorsUS8228725May 28, 2010Jul 24, 2012Micron Technology, Inc.Memory utilizing oxide nanolaminatesUS8362576Jan 14, 2011Jan 29, 2013Round Rock Research, LlcTransistor with reduced depletion field widthUS8399365Dec 12, 2011Mar 19, 2013Micron Technology, Inc.Methods of forming titanium silicon oxideUS8445952Oct 30, 2009May 21, 2013Micron Technology, Inc.Zr-Sn-Ti-O filmsUS8501563Sep 13, 2012Aug 6, 2013Micron Technology, Inc.Devices with nanocrystals and methods of formationUS8652957Sep 26, 2011Feb 18, 2014Micron Technology, Inc.High-K gate dielectric oxide* Cited by examinerClassifications U.S. Classification338/34, 338/309, 338/308International ClassificationG01N27/12Cooperative ClassificationG01N27/12European ClassificationG01N27/12Legal EventsDateCodeEventDescriptionOct 24, 1995FPExpired due to failure to pay maintenance feeEffective date: 19950816Aug 13, 1995LAPSLapse for failure to pay maintenance feesMar 21, 1995REMIMaintenance fee reminder mailedSep 4, 1990FPAYFee paymentYear of fee payment: 8Dec 22, 1986FPAYFee paymentYear of fee payment: 4Oct 5, 1981ASAssignmentOwner name: ITT INDUSTRIES INC 320 PARK AVE NEW YORK NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:RIGBY, LESLIE J.;REEL/FRAME:003936/0286Effective date: 19810910RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google

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Magnuson Lake Wales hotels in Waverly, Lakeland
Check Availability Situated in the historical district, this motel is within 3 mi (5 km) of Mountain Lake, Tiger Creek Preserve, and Grand …More
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Susan N.G. Geiger - Semantic Scholar
Susan N.G. Geiger
What's So Feminist About Women's Oral History?
There's a long running review in Minneapolis called "Whaf s so funny about being female?" While the cast of comedians changes, the show usually features six or seven women whose routines are as… (More)
Women and Gender in African Studies@@@Engendering African Social Sciences@@@In the Shadow of Marriage@@@Woman between Two Worlds@@@The Invention of Women
Susan N.G. Geiger, Ayesha Imam, +4 authors Oyèrónkẹ́ Oyěwùmí
As the first three quotations with which this paper begins suggest, the rhetoric of "women's liberation" became quite acceptable in Tanzania during the 1970s with President Nyerere himself taking the… (More)
Specificities: Citizens and Subjects Engendering and Gendering African Nationalism: Rethinking the Case of Tanganyika (Tanzania)
Women and African Nationalism
The history of studies of women's involvement in African nationalist struggle, mobilization, and party politics can be traced along intellectual and political paths that initially followed, later… (More)

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Leann Jester Daus, Faculty
Dominic Villarente
, Owner at Sa Puso at Isip Niya
at Sa Puso at Isip Niya
thanks for helping me in my homework..
Aljun Bulatao
nice 1 i just took 5 mins. to do my presentation because of this :) it helps a lot
Ian Kit Lituanas
thanks a lot, it helped me
at Boon Electrical Contractors Pty Ltd
kritrika verma
, Dubai gems , Bur Dubai, mathematics teacher
at Dubai gems
, ESP, HPS & HSE Artificial Lift specialist & Instructor
at APPLUS-VELOSI Co.
, Student at Industrial Training International
Sowmya Rani
OBJECTIVES 1) State the relationship between voltage, current and resistance; 2) Apply ohm’s law in solving problems 3.

Electric Current

Current is the rate of flow of electrons/charge

- It is abbreviated as I

- It is measured in amperes

- One ampere is defined as one coulomb of electrons flowing past a point each second (Q/s)

VOLTAGE

- Voltage is a force that pushes/drives the electrons/charge

- It is also referred to as electromotive force or difference in potential.

- It is abbreviated as E or EMF

- Voltage is measured in volts (v)

Voltage source will have a polarity (negative and positive side)

Current flows from negative to positive (changing conventions)

AC/DC: Alternating current (polarity of source reverses) or Direct current (polarity is constant)

RESISTANCE Resistances are the barriers to the flow of charge It is abbreviated as R It is measured in ohms 6.
S.MORRIS 2006 ELECTRICAL CIRCUITS More free powerpoints at www.worldofteaching.com 7.
The CELL The cell stores chemical energy and transfers it to electrical energy when a circuit is connected. When two or more cells are connected together we call this a Battery . The cells chemical energy is used up pushing a current round a circuit. 8.
What is an electric current? An electric current is a flow of microscopic particles called electrons flowing through wires and components. + - In which direction does the current flow? from the Negative terminal to the Positive terminal of a cell. 9.
simple circuits Here is a simple electric circuit. It has a cell, a lamp and a switch. To make the circuit, these components are connected together with metal connecting wires. cell lamp switch wires 10.
simple circuits When the switch is closed, the lamp lights up. This is because there is a continuous path of metal for the electric current to flow around. If there were any breaks in the circuit, the current could not flow. 11.
circuit diagram cell switch lamp wires Scientists usually draw electric circuits using symbols; 12.
circuit diagrams In circuit diagrams components are represented by the following symbols; cell battery switch lamp motor ammeter voltmeter buzzer resistor variable resistor 13.
types of circuit There are two types of electrical circuits; SERIES CIRCUITS PARALLEL CIRCUITS 14.
The components are connected end-to-end, one after the other. They make a simple loop for the current to flow round. SERIES CIRCUITS If one bulb ‘blows’ it breaks the whole circuit and all the bulbs go out. 15.
PARALLEL CIRCUITS The current has a choice of routes. The components are connected side by side. If one bulb ‘blows’ there is still be a complete circuit to the other bulb so it stays alight. 16.
measuring current Electric current is measured in amps (A) using an ammeter connected in series in the circuit. A 17.
measuring current A A This is how we draw an ammeter in a circuit. SERIES CIRCUIT PARALLEL CIRCUIT 18.
measuring current SERIES CIRCUIT PARALLEL CIRCUIT

current is the same

at all points in the

circuit.

2A 2A 2A

current is shared

between the

components

2A 2A 1A 1A 19.
copy the following circuits and fill in the missing ammeter readings. ? ? 4A 4A 4A 3A ? ? 1A ? 3A 1A 1A 20.
measuring voltage The ‘electrical push’ which the cell gives to the current is called the voltage . It is measured in volts (V) on a voltmeter V 21.
Different cells produce different voltages. The bigger the voltage supplied by the cell, the bigger the current. measuring voltage Unlike an ammeter a voltmeter is connected across the components Scientist usually use the term Potential Difference (pd) when they talk about voltage. 22.
measuring voltage V This is how we draw a voltmeter in a circuit. SERIES CIRCUIT PARALLEL CIRCUIT V 23.
V measuring voltage V V V 24.
series circuit 1.5V

voltage is shared between the components

1.5V 3V 25.

voltage is the same in all parts of the circuit.

3V parallel circuit 3V 3V 26.
measuring current & voltage copy the following circuits on the next two slides. complete the missing current and voltage readings. remember the rules for current and voltage in series and parallel circuits. 27.
measuring current & voltage V V 6V 4A A A a) 28.
measuring current & voltage V V 6V 4A A A A b) 29.
answers 3V 3V 6V 4A 4A 6V 6V 6V 4A 4A 2A 2A 4A a) b) Recommended

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text:
Finding things on the web with Yahoo! BOSS: IIT Delhi
Hacking & everything you need to su...
by Jai Santhosh
Let the hacking continue - Post Ope...
YQL: Hacking on steroids - Yahoo! O...
Finding things with BOSS
Introduction to Yahoo! Search & Content analysis APIs Introduction to Yahoo! Search & Content analysis APIs Published in:
Rathod Ay
Tags boss web
http://developer.yahoo.com/search/boss/ 2.
• Flexibility	to	Blend	and	Re-‐rank	Results	• Create	your	own	look	and	feel	• Mix	it	with	other	API’s	h>p://www.ﬂickr.com/photos/balajijegan/6242907231/in/photostream	3.
for	your	hacks	4.
Where do I start? 5.
http//www.flickr.com/photos/friarsbalsam/5736126308/sizes/o/in/photostream/.jpg 6.
select * from boss.search where q="The Artist"and service="images" and ck="…" andsecret="…" 7.
select * from boss.search where q="The Artist"and sites="imdb.com,movies.yahoo.com" andck="…" and secret="…" 8.
•  select * from boss.search where q="The Aartist" and service="spelling" and ck="…" and secret="…" 9.
•  select * from boss.search where q="The Artist" and service="news" and ck="…" and secret="…" 10.
•  select * from contentanalysis.analyze where url="http://www.cnn.com/" 11.
•  Find images of “The Artist”•  Select * from boss.search where q="The Artist” and service "images" and ck="…" and secret="…"•  Look for “The Artist” reviews:•  select * from boss.search where q="reviews intitle:The Artist" and service="web" and ck="…" and secret="…”•  Search for Artist but not the movie:•  select * from boss.search where q="Artist -movie” and ck="…" and secret="…”•  Search pdfs about “The Artist”:•  Select * from boss.search where q="The Artist” and type="pdf" 12.
•  Find all news about “The Artist”•  select * from boss.search where q="The Artist" and service="news" and ck="…" and secret="…"•  Get long abstracts in results•  select * from boss.search where q="The Artist" and abstract="long" and ck="…" and secret="…"•  Retrieve 51-100 results for the query•  select * from boss.search where q="Artist” and start=51 and ck="…" and secret="…" 13.
Interceder	14.
Hack:	h>p://www.inquisitorx.com/ﬁrefox/index_en.php	38	15.
Ø  Yahoo! BOSS: http://developer.yahoo.com/bossØ  BOSS Technical Documentation: http://developer.yahoo.com/ search/boss/boss_api_guide/Ø  YQL: http://developer.yahoo.com/yqlØ  Google App Engine: http: //appengine.google.comØ  Amazon Web Services: http://aws.amazon.comØ  oAuth: http://oauth.net/Ø  Open Social: http://www.opensocial.org/Ø  Open Data: http://theinfo.orgØ  Alt Search Engines: http://www.altsearchengines.com/ 16.
http://www.slideshare.net/saurabhsahni/finding-things-with-boss 17.
http://slideshare.net/saurabhsahnihttp://twitter.com/saurabhsahnihttp://github.com/saurabhsahnihttp://www.saurabhsahni.com Recommended
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niftylegacy6105
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BOSS: HackU IIT Delhi


text:
Giraffes Can't Dance 17-Dec-2015
by Giles Andreae , Guy Parker-Rees
£4.06 (22 Used & New offers)
There's A House Inside My Mummy 17-Dec-2015
by Giles Andreae , Vanessa Cabban
Commotion In The Ocean 17-Dec-2015
by Giles Andreae , David Wojtowycz
£5.43 £6.99
Rumble in the Jungle 17-Dec-2015
£3.63 (19 Used & New offers)
Mad About Dinosaurs! 17-Dec-2015
£9.44 (13 Used & New offers)
Be Brave Little Penguin 12-Jan-2017
£2.04 (19 Used & New offers)
£1.02 (30 Used & New offers)
Mad About Minibeasts! 26-Nov-2012
£0.99 (20 Used & New offers)
I Love My Mummy 26-Nov-2012
by Giles Andreae , Emma Dodd
£3.99 (16 Used & New offers)
The Lion Who Wanted To Love 17-Dec-2015
I Love My Grandad 09-Feb-2017
£0.73 (13 Used & New offers)
£2.76 (21 Used & New offers)
Farmyard Hullabaloo 03-Nov-2016
£22.33 (8 Used & New offers)
[Captain Flinn and the Pirate Dinosaurs] [By: Andreae, Giles] [September, 2005] 05-Sep-2005

value: This website is an American multinational technology company which focuses on e-commerce, cloud computing, digital streaming, and artificial intelligence.


text:
Capita slumps more than 4% after cautious outlook, as FTSE falters again | Business | The Guardian
Capita slumps more than 4% after cautious outlook, as FTSE falters again
Outsourcing group Capita reveals tough market, while leading shares continue to be undermined by eurozone woes
Friday 18 November 2011 04.10 EST
Last modified on Friday 18 November 2011 04.34 EST
With the David Cameron and Angela Merkel pow-wow to come, markets are heading lower again as the fear of the eurozone crisis escalating and spreading to the rest of the global economy gripped investors.
Mining shares - on concerns of a slowdown in demand - and banks - thanks to their exposure to eurozone debt - are among the leading fallers. Xstrata has lost 26.4p to 932.4p while Rio Tinto is down 46.5p at 3277.5p.
Lloyds Banking Group has hit a new 32 month low, down 0.665p at 25.04p, although worries about growing competition after the sale of Northern Rock to Richard Branson surely look misplaced.
But the biggest faller in the leading index is outsourcing specialist Capita, down 30p at 637.5p. In an interim statement the company behind collecting the TV licence and running the criminal records bureau said its clients were feeling the pinch of austerity. First half revenues fell by 7% and a similar decline is expected for the full year. Without a number of acquisitions which added 14% to revenue growth, the position would have been even worse.
The company maintained that cutbacks in both the private and the public sector would provide opportunities in 2012 and beyond.
Analyst Robert Morton at Investec kept his hold rating, but cut his target price from 725p to 630p. He said:
Today's statement from Capita has a more cautious tone than recent announcements, reflecting a continued tough background in the second half of the year. The group has had a reasonable year in terms of contract wins but the expected pick-up in the second half is clearly not coming through at the levels hoped for earlier in the year. We are going to edge down our forecasts for the full year and hence our target price.
Mike Allen at Panmure Gordon also kept his hold rating following the figures:
A third quarter statement from Capita implies that organic growth has not improved since the first half results, with attrition rates and the spot businesses remaining under pressure.
That said, the company has been more acquisitive to offset this effect, while margins are expected to remain robust as well. The company is bullish on the potential to win major new contracts in the near term, but we suspect these need to be delivered for the market to take notice. We would expect consensus to edge down on the back of this, and we maintain a cautious stance and target price of 700p for now, preferring Serco and Babcock at present.
Overall the FTSE 100 has fallen 50.65 to 5372.49, with the German market down nearly 2% and France 1% lower. Italy has edged down 0.3% while Wall Street is forecast to open virtually unchanged.
Concerns about a slowdown in China - which the Europeans seem to hope will cough up to help bail them out - is adding to the uncertain mood. Jonathan Bristow at Valbury Capital said:
Contagion is probably the word on everyone's lips this Friday. China's house prices have fallen and there are concerns on the number of defaulted loans. Seen by some as the saviour of the debt crisis, China is now starting to slip into it. The big unanswered worry is who is big enough to bailout China if things continue? This issue needs to be fixed soon before it gets much bigger.
Defensive stocks were in demand, with National Grid up 2.5p at 644p following Thursday's figures, while Scottish and Southern Energy is up 2p at £12.88 and GlaxoSmithKline is 4.5p better at 1391.5p.

value: This website is a British news and media website owned by the Guardian Media Group. It contains nearly all of the content of the newspapers The Guardian and The Observer, as well as a substantial body of web-only work produced by its own staff, including a rolling news service.


text:
white. sometimes they say was one hispanic. after the trial we learned the one juror was clearly of african descent. porter began at least as african as barack obama but for the three weeks she was part of the all white jury? this is how the media works. put the case was coming to trial and what made it interesting. where the whole industry got behind the media the president the attorney general sending in the in the sand to a trial in a place he could not get a fair trial. with the research i have done i am used to exposing something than the media kicks the can down the road just one quick example i did a book 10 years ago in this story broke the news documentary out with six whistle-blowers yes we did cover it up so i felt vindicated i knew the major media would not follow up i was asked to be on and cnn to talk about it. only five or six minutes they have on another guy who produced about this documentary and they said i have one minute left the host says why is it a cover-up? i said let me just take one of the questions. why the cover-up? in 1996 a reelection in your of clin Book TV
-span.org/localcontent. >> next on booktv joshua dubois, former executive director of the white house office of faith based and neighborhood partnership talks about the devotional e-mails he has been sending since barack obama since he was a senator. this is about half an hour. [applause] >> it is great to be here. change in plans, i wasn't able to update the book but cooking dishes for michele obama since this evening. american grow. we can get to that after the devotional. thank you for being here. so wonderful to see so many friends, old and new. like a family reunion. i am excited to share it this book with you. my wonderful wife, michele. [applause] >> we have been married precisely 82 days. you see this blow on my face, that is why. thank you so much for being here. when i started working for barack obama i had no idea i would be sending in a devotional every morning. i was a young kid from nashville, tenn. working on the 2008 campaign, in the senate office for couple years but didn't know him that well. i was doing out reach around a company like so many others including many folks that i see and pr Search Results 0 to 1 of about 2

value: This website is an American digital library with the stated mission of "universal access to all knowledge". It provides free public access to collections of digitized materials, including websites, software applications/games, music, movies/videos, moving images, and millions of books.


text:
Philly Model Face Off Modeling Event Casting Calls Tickets, Thu, Mar 29, 2018 at 5:30 PM | Eventbrite
Thu, March 29, 2018, 5:30 PM – 7:30 PM EDT

value: This website is an American event management and ticketing website. The service allows users to browse, create, and promote local events.


text:
Advertising age international. (eJournal / eMagazine, 1990s) [WorldCat.org]
I thought you might be interested in this item at http://www.worldcat.org/oclc/123532285 Title: Advertising age international. Publisher: New York, N.Y. : Ad Age Group, -2000. OCLC:123532285
New York, N.Y. : Ad Age Group, -2000.
Full text available 7/1/1996 - 7/1/2000. Available on EBSCOhost.
MacEwan University Access: 1996-2000
University of Alberta Access: 1996-2000
search.ebscohost.com Full text available from Business Source Complete: 01/07/1996 to 31/07/2000
search.ebscohost.com Full text from Business Source Premier: 01/07/1996 to 31/07/2000 (Requires University Computer Account login off-campus)
find.galegroup.com Full text from Expanded Academic ASAP: 01/05/1999 to 31/07/2000 (Requires University Computer Account login off-campus)
search.ebscohost.com 07/01/1996 to 07/31/2000
link.galegroup.com 05/01/1999 to 07/31/2000
0-search.ebscohost.com.emu.londonmet.ac.uk Full text available from Business Source Complete: 01/07/1996 to 31/07/2000
0-search.ebscohost.com.emu.londonmet.ac.uk Full text available from Business Source Ultimate: 01/07/1996 to 31/07/2000
0-search.ebscohost.com.pugwash.lib.warwick.ac.uk Full text available from Business Source Complete: 01/07/1996 to 31/07/2000
Full text available 5/1/1999 - 7/1/2000. Available on EBSCOhost.
123532285
volumes : illustrations (some color) ; 37 cm
Add tags for "Advertising age international.". Be the first.
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schema:alternateName "Ad age international" ;
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schema:name "Advertising age international." ;
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wdrs:describedby <http://www.worldcat.org/title/-/oclc/123532285> ;
<http://0-link.galegroup.com.arthur.searchmobius.org/apps/pub/0BPH/AONE?sid=kbart?&u=west1012>
<http://0-search.ebscohost.com.emu.londonmet.ac.uk/direct.asp?db=bsu&jid=AVI&scope=site>
rdfs:comment "Full text available from Business Source Ultimate: 01/07/1996 to 31/07/2000" ;
<http://0-search.ebscohost.com.emu.londonmet.ac.uk/direct.asp?db=bth&jid=AVI&scope=site>
rdfs:comment "Full text available from Business Source Complete: 01/07/1996 to 31/07/2000" ;
<http://0-search.ebscohost.com.pugwash.lib.warwick.ac.uk/direct.asp?db=bth&jid=AVI&scope=site>
<http://dewey.info/class/659/a13/>
<http://experiment.worldcat.org/entity/work/data/33089848#Agent/ad_age_group> # Ad Age Group
schema:name "Ad Age Group" ;
<http://experiment.worldcat.org/entity/work/data/33089848#Place/new_york_n_y> # New York, N.Y.
<http://experiment.worldcat.org/entity/work/data/33089848#Topic/advertising> # Advertising
<http://experiment.worldcat.org/entity/work/data/33089848#Topic/marketing> # Marketing
<http://find.galegroup.com/openurl/openurl?url_ver=Z39.88-2004&url_ctx_fmt=info:ofi/fmt:kev:mtx:ctx&res_id=info:sid/gale:EAIM&ctx_enc=info:ofi:enc:UTF-8&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.issn=1524-8984&req_dat=info:sid/gale:ugnid:stand>
rdfs:comment "Full text from Expanded Academic ASAP: 01/05/1999 to 31/07/2000 (Requires University Computer Account login off-campus)" ;
<http://link.galegroup.com/apps/pub/0BPH/CPI?sid=kbart?&u=uvictoria>
rdfs:comment "05/01/1999 to 07/31/2000" ;
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<http://search.ebscohost.com/direct.asp?db=bth&jid=AVI&scope=site>
rdfs:comment "07/01/1996 to 07/31/2000" ;
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rdfs:comment "Full text from Business Source Premier: 01/07/1996 to 31/07/2000 (Requires University Computer Account login off-campus)" ;
<http://search.ebscohost.com/direct.asp?db=f5h&jid=%22AVI%22&scope=site>
<http://search.ebscohost.com./login.aspx?direct=true&db=bth&jid=AVI&loginpage=Login.asp&site=bsi>
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<http://worldcat.org/entity/work/id/33089848> # Advertising age international (Online)
schema:name "Advertising age international (Online)" ;
<http://www.worldcat.org/title/-/oclc/123532285>
schema:about <http://www.worldcat.org/oclc/123532285> ; # Advertising age international.
<http://www.worldcat.org/title/-/oclc/123532285#PublicationEvent/new_york_n_y_ad_age_group_2000>
schema:location <http://experiment.worldcat.org/entity/work/data/33089848#Place/new_york_n_y> ; # New York, N.Y.
schema:organizer <http://experiment.worldcat.org/entity/work/data/33089848#Agent/ad_age_group> ; # Ad Age Group
<http://YJ2RX5VX3S.search.serialssolutions.com/?sid=sersol&SS_jc=ADVEAGEINT&title=Advertising%20age%20international>
<https://elib.southwest.tn.edu:3443/login?url=http://search.ebscohost.com/direct.asp?db=ofm&jid=%22AVI%22&scope=site>
<https://search.ebscohost.com/direct.asp?db=bth&jid=AVI&scope=site>

value: This website is a union catalog that itemizes the collections of 15,637 libraries in 107 countries that participate in the OCLC global cooperative. It is operated by OCLC, Inc.