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Patent US5864162 - Apparatus and method of making a self-aligned integrated resistor load on ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA thin silicon layer transistor integrated with a resistor. The resistor is self-aligned and contiguous with the transistor and is also formed of the same thin silicon layer as the transistor. This structure is particularly suitable for an SRAM circuit in order to simplify processing steps and to conserve...http://www.google.com/patents/US5864162?utm_source=gb-gplus-sharePatent US5864162 - Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphireAdvanced Patent SearchPublication numberUS5864162 APublication typeGrantApplication numberUS 08/571,661Publication dateJan 26, 1999Filing dateDec 13, 1996Priority dateJul 12, 1993Fee statusPaidAlso published asUS6090648Publication number08571661, 571661, US 5864162 A, US 5864162A, US-A-5864162, US5864162 A, US5864162AInventorsRonald E. Reedy, Mark L. BurgenerOriginal AssigneePeregrine Seimconductor CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (71), Non-Patent Citations (68), Referenced by (27), Classifications (43), Legal Events (13) External Links: USPTO, USPTO Assignment, EspacenetApparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire
US 5864162 AAbstract
A thin silicon layer transistor integrated with a resistor. The resistor is self-aligned and contiguous with the transistor and is also formed of the same thin silicon layer as the transistor. This structure is particularly suitable for an SRAM circuit in order to simplify processing steps and to conserve area on SOS designs.
1. An integrated circuit device comprising:an insulating substrate having a major face; a thin silicon layer provided on the major face; a transistor formed in the thin silicon layer comprising a source, a drain and a channel which forms a conductive path between the source and the drain; a polycrystalline silicon layer provided near the thin silicon layer to form a gate of the transistor; a resistor load provided in the thin silicon layer wherein the resistor load is self-aligned to and contiguous with the transistor. 2. The integrated circuit device of claim 1, wherein the thin silicon layer has a thickness of less than about 1,100 Å.
3. An integrated circuit device comprising:a sapphire substrate having a major face; a thin silicon layer provided on the sapphire substrate; a first field effect transistor (FET) provided in the thin silicon layer wherein the first FET has a source region, a drain region and a channel region such that the channel region forms a conductive path between the source region and the drain region; a polycrystalline silicon layer provided near the thin silicon layer to form a gate of the first field effect transistor (FET); a first resistor load provided in the thin silicon layer integral with at least one of the source region and drain region wherein the resistor load is self-aligned to and contiguous with the first FET; a contact means provided in the silicon layer contiguous with the first resistor load for providing electrical connection thereto. 4. The integrated circuit device of claim 3, wherein conductivity of the first resistor load is controlled by ion implantation.
8. The integrated circuit device of claim 3 wherein the first resistor load is contiguous with the drain of the first FET and the integrated circuit device further comprises:a second field effect transistor provided in the thin silicon layer wherein the second FET has a source region, a drain region and a channel region such that the channel region of the second FET forms a conductive path between the source region and the drain region of the second FET; a second polycrystalline silicon layer provided near the thin silicon layer to form a gate of the second field effect transistor; a second resistor load provided in the thin silicon layer contiguous with the drain region of the second FET and self-aligned to the second FET wherein the first FET and the second FET are cross coupled by coupling the first resistor load and the drain of the first FET to the gate of the second FET and by coupling the second resistor load and the drain of the second FET to the gate of the first FET. 9. The integrated circuit device of claim 8, wherein the thin silicon layer has a thickness of less than about 1,100 Å.
This application is a continuation-in-part of patent application Ser. No. 08/389,671, filed Feb. 16, 1995 by inventor Ronald E. Reedy, entitled "Apparatus and Method Of Making A Self-Aligned Integrated Resistor Load On Ultrathin Silicon On Sapphire," now abandoned which is a continuation-in-part of patent application Ser. No. 08/090,400, filed Jul. 12, 1993 by inventors Burgener and Reedy, and entitled "Minimum Charge FET Fabricated On An Ultrathin Silicon On Sapphire Wafer," now U.S. Pat. No. 5,416,043. The present application is also a continuation-in-part of patent application Ser. No. 08/218,561, filed Mar. 24, 1994 by inventors Mark L. Burgener and Ronald E. Reedy, entitled "High Frequency Wireless Communication System On A Single Ultrathin Silicon On Sapphire Chip," now U.S. Pat. No. 5,572,040 which is a continuation-in-part of patent application Ser. No. 08/090,400, filed Jul. 12, 1993 by inventors Burgener and Reedy, entitled "Minimum Charge FET Fabricated On An Ultrathin Silicon On Sapphire Wafer," now U.S. Pat. No. 5,416,043.
The field of the invention relates generally to a method for fabricating a semiconductor on insulator composite substrate, such as silicon-on-sapphire (SOS). More particularly, the field of the invention relates to a method for making a resistor, transistor, or memory cell utilizing an ultra thin silicon layer on a sapphire structure and for providing a resistive load which is self-aligned to a corresponding transistor, thereby eliminating a polysilicon layer and providing an extremely compact memory cell or analog circuit.
A six transistor (6T) SRAM, typically includes four NMOS transistors and two PMOS transistors. In these 6T SRAMs, the two PMOS transistors replace the high resistance resistors used in the 4T SRAMs. In a typical 6T SRAM, the complimentary n and p channel transistors are adjacent. Accordingly, an additional layer of material (like that used to form the 4T SRAM resistors) ordinarily is not required. As a result, the 6T SRAM fabrication process can eliminate some of the processing steps used to fabricate a 4T SRAM. The 6T SRAM technology also can reduce (by as much as a factor of 1000) the high leakage currents that are commonly found in 4T SRAMs. This is due to the off current of a PMOS device being typically 10-12 Amps, whereas the resistors typically draw 10-8 to 10-9 Amps.
The advantages of utilizing a composite substrate comprised of a monocrystalline semiconductor layer, such as silicon, epitaxially deposited on a supporting insulative substrate are well recognized. These advantages include the substantial reduction of parasitic capacitance between charged active regions and the substrate and the effective elimination of leakage currents flowing between adjacent active devices. This is accomplished by employing as the substrate an insulative material, such as sapphire (Al2 O3) and providing that the conduction path of any interdevice leakage current must pass through the substrate.
However, in the absence of a high temperature anneal, a second problem appears. The crystalline quality of the silicon layer, as epitaxially deposited, is of insufficient quality to permit the fabrication of active devices therein. It was discovered that the dominant crystal defects, i.e., twins, could be eliminated by solid phase epitaxial (SPE) regrowth, a process described in U.S. Pat. No. 4,177,084, entitled "METHOD FOR PRODUCING A LOW DEFECT LAYER OF SILICON-ON-SAPPHIRE WATER", issued to Lau et al. As described by Lau et al., the SPE process provides a low temperature subprocess for improving the crystallinity of the silicon epitaxial layer of a silicon-on-sapphire composite substrate. The SPE process involves the high energy implantation (typically at 40 KeV to 550 KeV) of an ion species, such as silicon, into the silicon epitaxial layer at a sufficient dose (typically 1015 to 1016 ions/cm2) to create a substantially amorphous silicon layer lying adjacent the silicon/sapphire interface while leaving a substantially crystalline layer at the surface of the original epitaxial layer. The thickness of the silicon epitaxial layer is substantially that intended for the completed silicon-on-sapphire composite substrate (typically 3000A-6000A). The ion species is implanted through the majority of the epitaxial layer so that the maximum disruption of the silicon crystal lattice is near, but not across, the silicon/sapphire interface to ensure that the amorphous region is adjacent the sapphire substrate. Throughout the ion implantation, the sapphire substrate is kept below about 100� C. by cooling with Freon or liquid Nitrogen. A single step low temperature (600� C.) annealing of the composite substrate is then performed to convert the amorphous silicon layer into crystalline silicon. During this regrowth, the remaining crystalline surface portion of the silicon layer effectively acts as a nucleation seed so that the regrown portion of the silicon epitaxial layer has a common crystallographic orientation and is substantially free of crystalline defects.
While Lau's SPE process does significantly improve the crystallinity of the silicon epitaxial layer, it also facilitates the diffusion of aluminum from the sapphire substrate (Al2 O3) into the silicon epitaxial layer, which dopes the silicon film p-type. The contaminant concentration resulting from the use of the SPE process is, unfortunately, sufficient to preclude the practical use of integrated circuits fabricated on composite substrates, such as silicon on sapphire, processed with this SPE subprocess. The reasons for the failure of active devices to operate correctly are essentially the same as given above with regard to composite substrates fabricated utilizing high temperature processing steps. Additionally, it has been observed that the method described by Lau et al., can leave enough electrically active states in the silicon epitaxial layer to preclude its use for fabrication of integrated circuits using silicon on sapphire.
U.S. Pat. No. 4,509,990, entitled "SOLID PHASE EPITAXY AND REGROWTH PROCESS WITH CONTROLLED DEFECT DENSITY PROFILING FOR HETEROEPITAXIAL SEMICONDUCTOR ON INSULATOR COMPOSITE SUBSTRATES", issued to Vasudev, also describes use of ion implantation and solid phase regrowth to prepare a silicon-on-sapphire wafer. In a first principle embodiment, a method for fabricating a silicon-on-sapphire wafer very similar to that taught by Lau et al. is described with the additional requirement that the implantation energy and the ion dose are constrained such that they are sufficiently low so as not to exceed the damage density threshold of the sapphire substrate. In a second principle embodiment, the method describes a residual high defect density in the silicon layer near the sapphire substrate. Both embodiments utilize a method for controlling the temperature of the rear surface of the sapphire substrate by mounting the substrate on a heat sink with either a thin film of thermal paste or a thin film of silicon positioned intermediate to the rear surface of the substrate and the heat sink to provide a high heat conductivity interface therebetween. During the ion implantation, the temperature of the heat sink is held at a constant temperature (typically between -20� C. and 250� C.) resulting in a substantial thermal gradient between the rear surface of the sapphire and the silicon layer (typically 150� C. to 200� C.). Thus, it follows that the silicon layer is at a temperature falling in the range of 130� C. to 450� C.
The paper entitled "THIN (100 nm) SOS FOR APPLICATION TO BEYOND VLSI MICROELECTRONICS", published in the Mat. Res. Soc. Symp. Proc. Vol. 107, pp. 365-376, 1988, authored by Reedy et al. discusses preparation techniques for SOS films using a double anneal with temperatures as high as 1050� C. Mention is made that adequate thermal contact must be made to prevent self annealing, however, no method of providing such contact is disclosed. Characteristics of bulk silicon and the SOS films thus produced are compared. Likewise, it is noted that n and p channel transistors which were fabricated in these SOS films exhibited performance characteristics which rivaled those of similar devices fabricated in bulk silicon. However, there is no discussion of fully depleted transistor operation in this paper.
Therefore, what is needed is a method for fabricating a thin layer of substantially pure silicon on a sapphire or other insulating substrate which layer is extremely uniform in thickness. The transistors and/or resistors of an SRAM could be manufactured in this layer eliminating some of the disadvantages of conventional SRAMs. Such a uniform layer, if fabricated on a sapphire substrate would advantageously have its conductivity controlled by normal ion implantation due to the uniform definition imposed by the sapphire substrate. Such a layer would initially have no dopant atoms or electrically active states. Substantially no electrically active states is defined as an areal density of electrically active states which is approximately 3�1011 cm-2 to 5�1011 cm-2.
In order to overcome the above-described disadvantages and problems in conventional logic devices and methods of manufacturing such devices, an aspect of the present invention provides an ultra thin silicon on sapphire film which is used to manufacture a FET and a resistor load for example a four transistor (4T) SRAM. However, the invention is not limited to an application to SRAM but rather encompasses an integral resistor load which can be integrated with analog components or formed as part of an integrated circuit for electrostatic discharge (ESD) circuitry, mixed signal circuitry, or the like. The resistor load can be integrally formed from the same silicon island which forms a corresponding transistor. Because the resistor load can be made from and integral with the ultra thin silicon material, it can be automatically self-aligned to the transistor.
FIGS. 1A-1E illustrate steps in the process of converting an epitaxial silicon on sapphire wafer into a substantially pure silicon on sapphire wafer.
The following description is presented to enable a person skilled in the art to make and use the invention. Descriptions of specific applications are provided only as examples. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the described or illustrated embodiments, but should be accorded the widest scope consistent with the principles and features disclosed herein. It is understood that both n- and p-type MOSFETs can be made simultaneously on the same sapphire substrate, thereby comprising complimentary MOS (or CMOS) circuits.
An SRAM exhibiting improved features can be manufactured on an ultrathin intrinsic silicon film on an insulating substrate. Accordingly, a first aspect of the invention is to provide an ultrathin silicon film on an insulating substrate and processes for making such a film. Ideally, the intrinsic silicon contains no dopant atoms or electrically active states, either within the silicon film or at the interface between the silicon and the sapphire. While complete elimination of all charge states and dopant atoms is not feasible, trace amounts are acceptable within tolerances determined by the application. For example, if a threshold voltage is to be set to an accuracy of δ Volts, the total-charge in the silicon film should be less than about δ/Cox, where Cox is the gate oxide capacitance per unit area. Other tolerances can be determined similarly. For example, if the threshold voltage is to be accurate to within ΔVt =50 mV (0.05 V) of the desired value as determined by the metal work function, and a 5 nm thick SiO2 dielectric layer is the gate insulator, then the total number of fixed charges ΔN (i.e., dopant charge plus band gap states plus interface states plus fixed charge in the insulators) in the structure should be less than ΔVt Cox /q, where q is the charge on the electron. Thus, in this example, ΔN should be less than approximately 2�1011 cm-2, which is typical of most current devices. However, certain applications may require tighter threshold voltage control, thereby requiring that the total allowable fixed charge in the silicon film be less than approximately 3�1011 cm-2 while other applications may tolerate total allowable fixed charge up to as much as 5�1011 cm-2.
Referring to FIG. 1B, a 185 kev Beam of Si ions 20 is implanted into the silicon film 22 to a dose of approximately 6�1014 cm-2, thus creating a subsurface amorphous region 22A and leaving a surface monocrystalline silicon region 22S. The energy and dose of the beam of Si ions 20 are selected so that the amorphous region 22A extends from an interface 18 formed between the sapphire substrate 12 and the Si film 22 up into the Si film 22 to a thickness which is greater than the desired final thickness of Silicon film. In this aspect, the amorphous region 22A is approximately 200 nm thick.
The amorphous region 22A in the 270 nm thick intrinsic silicon film 22 is created by implantation with the Si ion beam having an energy of 185 kev at a dose of 6�1014, cm-2 while maintaining the silicon film 22 at a uniform temperature at or below about 0� C. It has been found that this process will uniformly amorphize layer 22A without causing aluminum atoms to be released from the sapphire substrate 12 into the silicon film 22. While others have reported cooling the substrate by placing it on a cooled heat sink during implantation, none have paid particular attention to the temperature of the silicon film 22 during the implantation nor have they adequately addressed the issue of uniform cooling of the silicon film.
Previous cooling techniques include various techniques for placing the sapphire substrate 12 in contact with a cooled heat sink. Contact between the sapphire substrate and the heat sink was accomplished in a variety of ways including the use of a thermal paste layer interposed between the sapphire and the heat sink; depositing a layer of indium on the sapphire to provide more uniform contact with the heat sink; polishing the sapphire surface to improve contact with the heat sink; etc. However, these techniques created other problems and have been found to be inadequate for forming silicon films free of defects, dopants and charge states. A common shortcoming of these techniques is that it is very difficult to insure that the thermal contact between the sapphire and the heat sink is uniform over the entire sapphire surface. Non-uniform contact results in a nonuniform temperature within the overlying silicon film 22 which creates an amorphous layer 22A which is not uniformly amorphous due to partial self annealing. If the silicon film 22 is held at higher temperatures, the dose and/or energy must be increased to insure amorphization of layer 22A. If the temperature of the silicon film 22 is maintained at too high a temperature or not controlled at all, the ion implantation will cause the substrate temperature to rise, thereby increasing the required dose and/or energy required to amorphize layer 22A to a level where aluminum will out diffuse from the sapphire 12 into the silicon 22. An aspect of the present invention overcomes these shortcomings by cooling the sapphire with a flow of cooled gas and by adjusting the gas flow and/or temperature of the gas to insure that the silicon layer 22 is maintained at or below a predetermined temperature. For the dose and energy cited above, the substrate 12 is cooled to a temperature which maintains the surface of the silicon film 22 at a temperature preferably lower than about 0� C. One configuration for accomplishing these objectives is illustrated in FIG. 1B.
Shown in FIG. 1B is a configuration for maintaining the silicon film 22 at a uniform temperature at or below about 0� C. The SOS wafer 11 is positioned on a support structure 17 in a manner which creates a chamber 21 between the sapphire substrate 12 and the support structure 17, for example, by placing an O-ring 19 between the support structure 17 and the SOS wafer 11. Cooled gas is circulated through the chamber 21 to cool the substrate 12. Since the gas has the same thermal contact with all areas of the substrate 12, uniform cooling is assured. Gas enters the chamber 21 through an inlet 23 and exits the chamber through an outlet 25.
After creating the amorphous region 22A through silicon ion implantation, the SOS wafer 11 is subjected to a thermal anneal step at approximately 550� C. in an inert atmosphere (e.g. nitrogen) to induce solid phase epitaxial regrowth from the surface of the monocrystalline silicon region 22S downward through the amorphous region 22A to the interface 18. Thus the amorphous region 22A is regrown as a single crystal region 26. The direction of the regrowth from the monocrystalline silicon region 225 to the interface 18 is depicted by arrows 25 in FIG. 1C. Upon completion of this solid phase epitaxial regrowth, the anneal temperature is increased to approximately 900�-950� C. in an inert atmosphere (e.g. nitrogen) to remove any remaining defects or states, thereby converting the amorphous region 22A (FIG. 1B) into a substantially pure single crystal region 26 (FIG. 1C) devoid of the twins 14 and the bandgap states 16 (FIG. 1A).
Design and fabrication of a fully depleted MOSFET are described with reference to FIGS. 2 and 3. In the following described aspects, all of the MOSFET processing steps are preferably limited to temperatures less than approximately 950� C. in order to maintain the purity of the silicon in channel regions. Additionally, all anneals performed in non-oxidizing conditions are performed at temperatures less than approximately 950� C. Such depletion mode FETs also can be used to fabricate logic devices such as SRAMs in accordance with an aspect of the present invention.
In one MOSFET aspect, formation of isolated n-type and p-type regions in the silicon layer 28 is accomplished using a well-known process often referred to as "local oxidation of silicon" (LOCOS). Unless otherwise stated, it will be understood throughout that there may be other standard semiconductor processing steps which will achieve the same or functionally similar results as described below. Substitution of these alternatives are considered to be within the scope of the present invention as long as they do not result in a processing step performed in non-oxidizing conditions which subjects the silicon layer 28 or any subsequent regions fabricated in the silicon layer 28 to temperatures in excess of approximately 950� C. For example, instead of using the LOCOS process to form the isolated n-type and p-type regions, alternative isolation techniques may also be employed. One such alternative process etches the silicon layer 28 (FIG. 1E) into individual islands (sometimes called "mesas"), to form the isolated n-type and p-type regions. Additional alternative processing procedures are disclosed in a book entitled "VLSI Technology", Second Edition, edited by S. M. Sze, published by McGraw-Hill, New York, 1988, hereby incorporated herein by reference.
As shown in FIG. 2C, the silicon n-type region 22N is isolated from the silicon p-type region 22P by the growth of a silicon dioxide region 34. The silicon dioxide regions 34 are grown by introducing the wafer 29 shown in FIG. 2B into a high temperature (less than approximately 950� C.) oxidizing ambient environment. The silicon dioxide isolation regions 34 extend down to the sapphire substrate 12. Although the wafer 29 is in an oxidizing ambient, the silicon nitride layer 32 shields the silicon regions 22N and 22P, thereby keeping those regions from oxidizing. After growing the isolation regions 34, the silicon nitride layer 32 and the stress relief oxide layer 36 are stripped away.
P+ and N+ polysilicon gate materials, used in various combinations in n-type MOSFETS and p-type MOSFETS, are-useful in designing and fabricating digital and analog circuits, voltage reference circuits and memory type circuits. P+ polygermanium is a good choice for high performance digital logic where symmetric threshold voltages for n- and p-type MOSFETs are desired. Any conductive material which has a metal work function at the center of silicon's band gap (i.e., equal to silicon's electron affinity plus half the band gap or more specifically a metal work function of 4.5-4.7 eV) results in symmetric threshold voltages for n- and p-channel MOSFETs. Examples of such materials are tungsten, chrome, indium tin oxide, and titanium nitride, among others. The material may be different or the same for each transistor type (regions 48 and 58) depending on the desired threshold voltage. Examples of choice of material and resultant threshold voltages are approximately as follows: N+ polysilicon gate conductor results in Vtn =0 V and Vtp =-1 V; P+ polysilicon gate conductor results in Vtn =+1 V and Vtp =0 V; P+ polygermanium, tungsten, indium tin oxide or titanium nitride gate conductors result in Vtn =+1/2 V and Vtp =-1/2 V; where Vtn and Vtp are the threshold voltages of n- and p-channel MOSFETs, respectively.
The gate dielectric material 40 is grown and the gate conducting materials 48 and 58 are deposited using process conditions which avoid introduction of states or fixed charges into the channel regions 44 and 54. Specifically, processing temperatures and ambients are chosen to avoid generation of interface states or fixed charge in the dielectric. Therefore, as previously discussed, processing temperatures should be kept below approximately 950� C. Also, for P+ doped conductors as gate material 48 or 58, processing temperatures, times and ambients should be chosen to avoid diffusion of the dopant atoms from the gate conductors 48 and 58 through the gate dielectric insulator 40 into the silicon films 44 and 54. Diffusion barriers such as silicon nitride as part of the gate dielectric insulator 40 can be used to prevent such dopant migration.
A maximum amount of dopant charge can be introduced into channel regions 44 and 54. If the maximum amount is exceeded, the depletion region will not reach the sapphire 12, thus eliminating fully depleted operation. The maximum dopant charge is dependent on the silicon film thickness in the channel regions 44 and 54. For the preferred aspect, the regions 44 and 54 are approximately 100 nm thick and the maximum dopant density is approximately 1�1012 cm-2.
In a self-aligned silicide (salicide) aspect of the present invention, a sidewall spacer 60 is deposited and etched adjacent to the gate structure comprising the gate insulator 40 and conductor 48, 58. Referring to FIG. 3B, final self-aligned sources and drains 42S, 42P, 52S and 52D are formed by ion implantation or diffusion. For appropriate gate conductors 48 and 58 (such as polysilicon or polygermanium) the structure is coated with a metallic material and reacted to form metallic compounds 48M and 58M in the upper portion of gate conductors 48 and 58 as well 42M and 52M in source and drain regions 42S, 42P, 52S and 52D. Stripping unreacted metal from sidewall spacers 60 completes the salicide (or germanide) processing. Referring to FIG. 3B, silicide regions 42M, 52M, 48M, and 58M are separated from each other by the sidewall spacers 60. The thickness of metallic regions 42M, 48M, 52M and 58M is controlled by the amount of metallic material which is deposited. Obviously, the salicide option exists independently of LDD doping level. Referring to FIG. 3C, a complementary MOS structure is shown with both LDD and salicide options included after metallization as described above for FIG. 2. The MOSFET can be completed according to processes well known in the art, maintaining temperatures below approximately 950� C.
Referring to FIGS. 4A and 4B, the sapphire substrate 75 forms a diffusion barrier to the dopant atoms. This advantageously enables new thin source/drain regions with closely controlled resistivity to be formed by means of ion implantation or diffusion. For very thin doped regions, it is difficult to implant without going too deeply. For the aspect of the invention shown in FIG. 4A, wherein region 76 is an n+ region approximately 100 nm thick, ion implantation is actually more effective than diffusion doping. Diffusion doping may be more effective at 50 nm thick films. Further, the depth of source and drain regions 72 and 76, respectively, is controlled by the structure of the diffusion barrier formed by the interface between the thin silicon layer or island 70 and sapphire substrate 75. This advantageously enables a higher doping concentration to be achieved. Thus, MOSFET 71, for example, may be an intrinsic surface channel MOSFET which is formed on silicon island 70 as was explained with reference to FIG. 2D.
Referring to FIG. 4A, a single silicon island formed in accordance with the process described with reference to FIGS. 2A-2C provides a silicon processing base for MOSFET 71 and resistor 80. In FIG. 4A, an n-channel MOSFET 71 comprises a source 72, a gate 74 and drain 76 fabricated in ultrathin silicon on a sapphire substrate in accordance with the processes described with reference to FIG. 2D. A region 78 of the silicon island 70 extends from MOSFET 71. Silicon island 70 is formed by patterning nitride layer 32 of FIGS. 2A-2C to result in the geometry shown in FIG. 4A. Thus, region 78 comprises a portion of and is integral with the ultra-thin silicon island 70 which makes up the MOSFET 71. An integrated resistor load 80 is formed within region 78 of island 70. Resistor load 80 is doped sufficiently to make it conductive to the desired degree, or can be left undoped for the highest possible resistivity. For example, resistor load 80 may be doped with phosphorus atoms at a concentration of less than 1016 cm-2. The desired resistance value of the resistor load 80 is typically in the range of 108 -109 ohms for SRAMs. For analog components, resistor values in the range of 10-10,000 ohms are used. The resistance of resistor load 80 can be closely controlled by an ion implantation process as was set forth in the discussion referencing FIG. 2D. Of course, such ion implantation would occur prior to or during processing of MOSFET 71. For example, region 80 could be implanted during a threshold implant or LDD implant, or by means of special masking and implant steps prior to the N+ source/drain implant. Region 80 is photolithographically protected from the N+ implantation processes used to form MOSFET 71 and contact area 82.
Alternatively, resistor load 80 can be formed by selectively amorphizing it throughout its thickness. The process for creating such an amorphous region was set forth in the discussion with reference to FIG. 1B and following. However, in this application the ion implant energy and dose are chosen to amorphize the entire film thickness. It is necessary to mask the remainder of the integrated circuit before using the step of FIG. 1B to a amorphize resistor region 80. Only the resistor regions should be amorphized, otherwise the transistors may be damaged. The amorphized region 80 of island 70 is then annealed at a temperature sufficient to convert the amorphized portion to polycrystalline silicon. Such a thermal anneal step comprises heating the wafer to a temperature above 650� C. in an atmosphere of nitrogen gas. The thermal anneal to polycrystalline silicon normally occurs as part of the MOSFET source/drain dopant activation step. Subsequently, doping techniques as described with reference to FIG. 2D may be employed to precisely control the desired resistance of resistor load 80.
A heavily doped n+ region 82, bounded by W�Lc provides a contact to the resistor load 80. Heavily doped n+ region 82 is also formed by patterning and during the NMOS source/drain implant. The doped region 82 will be contacted by metal during subsequent processing. The resistor load 80 can be lightly doped in accordance with techniques which are well known in order to control its polarity. Alternatively, resistor load 80 can comprise single crystal silicon on polycrystalline silicon. Its resistance value equals its length divided by its width times Ps or sheet resistivity (Ω/□); R=ρs �L/W, where ρs equals the sheet resistivity of the ultrathin silicon layer.
FIG. 4C shows a cross sectional view of a MOSFET and a resistor from a conventional four transistor SRAM cell. The location of transistors and connections are well known to those skilled in the art and are omitted for the sake of simplicity. A principal disadvantage of the SRAM cell of FIG. 4C is the high topography which must be present in the metal layers (metal 1 and 2), and in the layers of polycrystalline silicon (Poly 1 and 2). In order to build such a conventional SRAM with the required resistance levels, an extra layer of polysilicon (Poly 2) must be used. Typically the first polysilicon layer (Poly 1) is characterized by a thickness of approximately 300 nm. A layer of CVD oxide (for example, SiO2) is disposed above the first polysilicon layer. The SiO2 layer typically has a thickness of approximately 500 nm to successfully protect and stabilize the underlying channel region. A second layer of polycrystalline silicon (Poly 2) is disposed over the CVD oxide layer. The Poly 2 layer further must be fabricated with a thickness on the order of 300 nm and a high resistivity to provide sufficient resistance values. The result is a device having disadvantageously high topography, as shown in FIG. 4C.
For the sake of example, analog cell 200 comprises a first transistor 204 having a drain 206, a source 208 and a gate 212. A first low resistivity layer of polycrystalline silicon 212 is provided over gate oxide 210 in a well known manner. A CVD oxide, for example, SiO2 layer 214 is provided over the polycrystalline silicon layer 212. SiO2 layer 214 provides insulation between a first metal layer 216 and polysilicon 212. Metal interconnect 216A connects drain 206 and resistor 218 made in a second polysilicon layer to ensure higher resistivity than the first polysilicon layer 212. A second metal interconnect 216B connects the other side of resistor 218 to another part of the circuit.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3309586 *Nov 6, 1961Mar 14, 1967IttTunnel-effect semiconductor system with capacitative gate across edge of pn-junctionUS3492511 *Dec 22, 1966Jan 27, 1970Texas Instruments IncHigh input impedance circuit for a field effect transistor including capacitive gate biasing meansUS3562425 *Aug 2, 1967Feb 9, 1971CsfImage signal generating systemUS3562608 *Mar 24, 1969Feb 9, 1971Westinghouse Electric CorpVariable integrated couplerUS3699544 *May 26, 1971Oct 17, 1972Gen ElectricThree transistor memory cellUS3798508 *Jul 10, 1972Mar 19, 1974Matsushita Electric Ind Co LtdVariable capacitance deviceUS3829743 *Jul 10, 1972Aug 13, 1974Matsushita Electric Ind Co LtdVariable capacitance deviceUS3829881 *Jul 10, 1972Aug 13, 1974Matsushita Electric Ind Co LtdVariable capacitance deviceUS4037140 *Apr 14, 1976Jul 19, 1977Rca CorporationProtection circuit for insulated-gate field-effect transistors (IGFETS)US4065781 *Jun 21, 1974Dec 27, 1977Westinghouse Electric CorporationInsulated-gate thin film transistor with low leakage currentUS4072910 *Apr 1, 1977Feb 7, 1978Rca CorporationVoltage controlled oscillator having equally controlled current source and current sinkUS4177084 *Jun 9, 1978Dec 4, 1979Hewlett-Packard CompanyMethod for producing a low defect layer of silicon-on-sapphire waferUS4183134 *Dec 11, 1978Jan 15, 1980Westinghouse Electric Corp.High yield processing for silicon-on-sapphire CMOS integrated circuitsUS4198649 *Jul 3, 1978Apr 15, 1980Fairchild Camera And Instrument CorporationMemory cell structure utilizing conductive buried regionsUS4282556 *May 21, 1979Aug 4, 1981Rca CorporationInput protection device for insulated gate field effect transistorUS4385937 *May 14, 1981May 31, 1983Tokyo Shibaura Denki Kabushiki KaishaRegrowing selectively formed ion amorphosized regions by thermal gradientUS4418470 *Oct 21, 1981Dec 6, 1983General Electric CompanyMethod for fabricating silicon-on-sapphire monolithic microwave integrated circuitsUS4420743 *Dec 24, 1981Dec 13, 1983Rca CorporationVoltage comparator using unequal gate width FET'sUS4425700 *Aug 7, 1981Jan 17, 1984Fujitsu LimitedSemiconductor device and method for manufacturing the sameUS4463492 *Sep 24, 1982Aug 7, 1984Tokyo Shibaura Denki Kabushiki KaishaMethod of forming a semiconductor device on insulating substrate by selective amorphosization followed by simultaneous activation and reconversion to single crystal stateUS4488230 *Jun 20, 1983Dec 11, 1984At&T Bell LaboratoriesProgrammed logic array with external signals introduced between its AND plane and its OR planeUS4509990 *Nov 15, 1982Apr 9, 1985Hughes Aircraft CompanySolid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substratesUS4523963 *Feb 27, 1984Jun 18, 1985Tokyo Shibaura Denki Kabushiki KaishaMethod of fabricating MOS device on a SOS wafer by stabilizing interface region with silicon and oxygen implantUS4549198 *Aug 29, 1984Oct 22, 1985Tokyo Shibaura Denki Kabushiki KaishaSemiconductor deviceUS4588447 *Jun 25, 1984May 13, 1986Rockwell International CorporationMethod of eliminating p-type electrical activity and increasing channel mobility of Si-implanted and recrystallized SOS filmsUS4598305 *Jun 18, 1984Jul 1, 1986Xerox CorporationDepletion mode thin film semiconductor photodetectorsUS4607176 *Aug 22, 1984Aug 19, 1986The United States Of America As Represented By The Secretary Of The Air ForceTally cell circuitUS4615762 *Apr 30, 1985Oct 7, 1986Rca CorporationMethod for thinning siliconUS4617066 *Nov 26, 1984Oct 14, 1986Hughes Aircraft CompanyProcess of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealingUS4659392 *Jul 30, 1986Apr 21, 1987Hughes Aircraft CompanySelective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuitsUS4682055 *Mar 17, 1986Jul 21, 1987Rca CorporationCFET inverter having equal output signal rise and fall times by adjustment of the pull-up and pull-down transconductancesUS4717836 *Feb 4, 1986Jan 5, 1988Burr-Brown CorporationCMOS input level shifting circuit with temperature-compensating n-channel field effect transistor structureUS4766482 *Dec 9, 1986Aug 23, 1988General Electric CompanySemiconductor device and method of making the sameUS4775641 *Sep 25, 1986Oct 4, 1988General Electric CompanyMethod of making silicon-on-sapphire semiconductor devicesUS4843442 *Jul 29, 1987Jun 27, 1989Bull S.A.Method for memorizing a data bit in an integrated mos-type static random access memory cell, a transistor for performing the method, and and the memory so obtainedUS4843448 *Apr 18, 1988Jun 27, 1989The United States Of America As Represented By The Secretary Of The NavyThin-film integrated injection logicUS4851721 *Feb 24, 1988Jul 25, 1989Mitsubishi Denki Kabushiki KaishaSemiconductor integrated circuitUS4872010 *Feb 8, 1988Oct 3, 1989Hughes Aircraft CompanyAnalog-to-digital converter made with focused ion beam technologyUS4876582 *May 2, 1983Oct 24, 1989Ncr CorporationCrystallized silicon-on-insulator nonvolatile memory deviceUS4907041 *Sep 16, 1988Mar 6, 1990Xerox CorporationIntra-gate offset high voltage thin film transistor with misalignment immunityUS4989057 *May 26, 1988Jan 29, 1991Texas Instruments IncorporatedESD protection for SOI circuitsUS5027171 *Aug 28, 1989Jun 25, 1991The United States Of America As Represented By The Secretary Of The NavyDual polarity floating gate MOS analog memory deviceUS5141882 *Dec 30, 1991Aug 25, 1992Mitsubishi Denki Kabushiki KaishaSemiconductor field effect device having channel stop and channel region formed in a well and manufacturing method thereforUS5145802 *Nov 12, 1991Sep 8, 1992United Technologies CorporationMethod of making SOI circuit with buried connectorsUS5166767 *Jan 19, 1989Nov 24, 1992National Semiconductor CorporationSidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layerUS5170373 *Oct 31, 1989Dec 8, 1992Sgs-Thomson Microelectronics, Inc.Three transistor eeprom cellUS5196802 *Apr 23, 1990Mar 23, 1993The United States Of America As Represented By The Secretary Of The NavyMethod and apparatus for characterizing the quality of electrically thin semiconductor filmsUS5229644 *Feb 5, 1992Jul 20, 1993Casio Computer Co., Ltd.Thin film transistor having a transparent electrode and substrateUS5242849 *May 22, 1992Sep 7, 1993Nippon Steel CorporationMethod for the fabrication of MOS devicesUS5294823 *Apr 9, 1992Mar 15, 1994Texas Instruments IncorporatedSOI BICMOS processUS5300443 *Jun 30, 1993Apr 5, 1994The United States Of America As Represented By The Secretary Of The NavyMethod for fabricating complementary enhancement and depletion mode field effect transistors on a single substrateUS5313077 *Apr 30, 1993May 17, 1994Semiconductor Energy Laboratory Co., Ltd.Insulated gate field effect transistor and its manufacturing methodUS5341009 *Jul 9, 1993Aug 23, 1994Harris CorporationFast charging MOS capacitor structure for high magnitude voltage of either positive or negative polarityUS5391903 *Dec 21, 1993Feb 21, 1995Harris CorporationSelective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuitsUS5416043 *Jul 12, 1993May 16, 1995Peregrine Semiconductor CorporationMinimum charge FET fabricated on an ultrathin silicon on sapphire waferUS5471070 *Feb 13, 1995Nov 28, 1995Sharp Kabushiki KaishaThin-film transistor circuit having an amorphous silicon load and a driver transistor and a method of producing the sameEP0273702A2 *Dec 23, 1987Jul 6, 1988General Electric CompanyRadiation hardening techniques for metal-oxide silicon devicesEP0600596A2 *Oct 19, 1993Jun 8, 1994National Semiconductor CorporationImproved bipolar transistorEP0605946A2 *Oct 20, 1993Jul 13, 1994National Semiconductor CorporationTransistor process for removing narrow base effectsFR2380637A1 * Title not availableGB2005073A * Title not availableGB2021346A * Title not availableJPH0555470A * Title not availableJPH04122020A * Title not availableJPS5690549A * Title not availableJPS57197848A * Title not availableJPS58222573A * Title not availableJPS61103530A * Title not availableJPS62176145A * Title not availableWO1989007367A2 *Dec 23, 1988Aug 10, 1989Hughes Aircraft CompanyAnalog-to-digital converter made with focused ion beam technologyWO1995002892A1 *Jun 10, 1994Jan 26, 1995Peregrine Semiconductor CorporationHigh-frequency wireless communication system on a single ultrathin silicon on sapphire chip* Cited by examinerNon-Patent CitationsReference1"Scaled Channel Length for N-Channel and P-Channel Transistors," Microprocessor Forum, Microprocessor Report, Nov. 12, 1992, pp. 1-10, and 4 pages drawings.2A. Schmitz et al., "A Deep-Submicrometer Microwave/Digital CMOS/SOS Technology," IEEE Electron Device Letters, (1991) Jan. vol. 12 No. 1, New York, pp. 16-17.3 *A. Schmitz et al., A Deep Submicrometer Microwave/Digital CMOS/SOS Technology, IEEE Electron Device Letters, (1991) Jan. vol. 12 No. 1, New York, pp. 16 17.4Betty Prince (Texas Instruments USA); "Semiconductor Memories, A Handbook of Design, Manufacture and Application", Second Edition; Copyright 1983, 1991 by John Wiley & Sons, Ltd., West Sussex, England; title pages pp. 141-145 and pp. 434-443.5 *Betty Prince (Texas Instruments USA); Semiconductor Memories, A Handbook of Design, Manufacture and Application , Second Edition; Copyright 1983, 1991 by John Wiley & Sons, Ltd., West Sussex, England; title pages pp. 141 145 and pp. 434 443.6 *Chen et al., Self Registered Gradually Doped Source Drain Extension Short Channel CMOS/SOS Devices, 8179 IEEE Device Letters vol. EDL 3, No. 12, Dec. 1982, New York.7Chen et al., Self Registered Gradually Doped Source Drain Extension Short Channel CMOS/SOS Devices, 8179 IEEE Device Letters vol. EDL-3, No. 12, Dec. 1982, New York.8G. Garcia et al., "High-Quality CMOS in Thin (100 nm) Silicon on Sapphire," IEEE Electron Device Letters, vol. 9, No. 1, Jan. 1988, pp. 32-34.9 *G. Garcia et al., High Quality CMOS in Thin (100 nm) Silicon on Sapphire, IEEE Electron Device Letters, vol. 9, No. 1, Jan. 1988, pp. 32 34.10Golecki et al., "Improvement of crystalline quality of epitaxial silicon-on-sapphire by ion implantation and furnace regrowth," Solid-State Electronics, vol. 23, pp. 803-806.11 *Golecki et al., Improvement of crystalline quality of epitaxial silicon on sapphire by ion implantation and furnace regrowth, Solid State Electronics, vol. 23, pp. 803 806.12 *H. Nishizawa et al., An Advanced Dielectric Isolation Structure for SOI CMOS VLSIs, Abstract No. 822, 1046b Extended Abstracts, Spring Meeting, (1993) May 16 21, Honolulu, 93/1 (1993) Pennington, NJ, pp. 1201 1202.13H. Nishizawa et al., An Advanced Dielectric Isolation Structure for SOI-CMOS VLSIs, Abstract No. 822, 1046b Extended Abstracts, Spring Meeting, (1993) May 16-21, Honolulu, 93/1 (1993) Pennington, NJ, pp. 1201-1202.14H. Veendrick, "Short-Circuit Dissipation of State CMOS Circuitry and Its Impact on the Design of Buffer Circuits," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 4, Aug. 1984.15 *H. Veendrick, Short Circuit Dissipation of State CMOS Circuitry and Its Impact on the Design of Buffer Circuits, IEEE Journal of Solid State Circuits, vol. SC 19, No. 4, Aug. 1984.16H. Woerlee et al., "Half-micron CMOS on Ultra-thin Silicon on Insulator," Technical Digest of the International Electron Devices Meeting, Dec. 3, 1989, pp. 821-824.17 *H. Woerlee et al., Half micron CMOS on Ultra thin Silicon on Insulator, Technical Digest of the International Electron Devices Meeting, Dec. 3, 1989, pp. 821 824.18I. Golecki et al., "Recrystallization of silicon-on-sapphire by cw Ar laser irradiation: Comparison between the solid-and the liquid-phase regimes," Applied Physics Letters, 37 (10), Nov. 15, 1980, pp. 919-921.19 *I. Golecki et al., Recrystallization of silicon on sapphire by cw Ar laser irradiation: Comparison between the solid and the liquid phase regimes, Applied Physics Letters, 37 (10), Nov. 15, 1980, pp. 919 921.20 *International Search Report Dated May 14, 1996; International Application No. PCT/US96/00139.21J. Lee et al. "Threshold adjustments for complementary metal-oxide-semiconductor optimization using B and As focused ion beams," Appl. Phys. Lett. 48 (10), Mar. 10, 1986, pp. 668-669.22 *J. Lee et al. Threshold adjustments for complementary metal oxide semiconductor optimization using B and As focused ion beams, Appl. Phys. Lett. 48 (10), Mar. 10, 1986, pp. 668 669.23J. Linnros et al., "Ion-bean-induced epitaxial regrowth of amorphous layers in silicon on sapphire," The American Physical Society, vol. 30, No. 7, Oct. 1, 1984, pp. 3629-3638.24 *J. Linnros et al., Ion bean induced epitaxial regrowth of amorphous layers in silicon on sapphire, The American Physical Society, vol. 30, No. 7, Oct. 1, 1984, pp. 3629 3638.25J. Whitehead and N. Duncan, "Design and Evaluation of CMOS-SOS On-Chip Input Protection Circuits," pp. 4.2.1-4.2.10, GEC Research Ltd., Hirst Research Centre, East Lane, Wembley, Middlesex HA9 7PP, United Kingdom.26 *J. Whitehead and N. Duncan, Design and Evaluation of CMOS SOS On Chip Input Protection Circuits, pp. 4.2.1 4.2.10, GEC Research Ltd., Hirst Research Centre, East Lane, Wembley, Middlesex HA9 7PP, United Kingdom.27 *Jean Pierre Colinge, Silicon on Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 1991, p. 112.28Jean-Pierre Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 1991, p. 112.29King et al., "A low-temperature (≦ 550C) silicon-germanium MOS thin-film transistor technology for large-area electronics," Technical Digest of the International Electron Devices Meeting, Dec. 8-11, 1991, pp. 567-570.30 *King et al., A low temperature ( 550C) silicon germanium MOS thin film transistor technology for large area electronics, Technical Digest of the International Electron Devices Meeting, Dec. 8 11, 1991, pp. 567 570.31N. Sasaki et al., "A CMOS/SOS Synchronous Static RAM Fabricated with an Advanced SOS Technology," Japanese Journal of Applied Physics, vol. 18 (1979), Supplements 18-1, pp. 57-62.32 *N. Sasaki et al., A CMOS/SOS Synchronous Static RAM Fabricated with an Advanced SOS Technology, Japanese Journal of Applied Physics, vol. 18 (1979), Supplements 18 1, pp. 57 62.33P.R. de la Houssaye et al., "Fabrication of n-channel metal-oxide-semiconductor field-effect transistors with 0.2 μ m gate lengths in 500Å thin film silicon on sapphire," Journal of Vacuum Science & Technology B, vol. 10, No. 6, Nov./Dec. 1992, pp. 2954-2957.34 *P.R. de la Houssaye et al., Fabrication of n channel metal oxide semiconductor field effect transistors with 0.2 m gate lengths in 500 thin film silicon on sapphire, Journal of Vacuum Science & Technology B, vol. 10, No. 6, Nov./Dec. 1992, pp. 2954 2957.35 *Patent Abstracts of Japan, vol. 005, No. 159 (E 077), Oct. 14, 1981 & JP 56 090 549 (Toshiba Corp.), Jul. 22, 1981.36Patent Abstracts of Japan, vol. 005, No. 159 (E-077), Oct. 14, 1981 & JP 56 090 549 (Toshiba Corp.), Jul. 22, 1981.37 *Patent Abstracts of Japan, vol. 007, No. 049 (E 161), Feb. 25, 1983 & JP 57 197848 (Tokyo Shibaura Denki KK), Dec. 4, 1982.38Patent Abstracts of Japan, vol. 007, No. 049 (E-161), Feb. 25, 1983 & JP 57 197848 (Tokyo Shibaura Denki KK), Dec. 4, 1982.39 *Patent Abstracts of Japan, vol. 008, No. 074 (E 236), Apr. 6, 1984 & JP, A, 58 222573 (Hitachi Seisakusho KK; Others; 01), Dec. 24, 1983.40Patent Abstracts of Japan, vol. 008, No. 074 (E-236), Apr. 6, 1984 & JP, A, 58 222573 (Hitachi Seisakusho KK; Others; 01), Dec. 24, 1983.41R. Reedy et al., "Characterization of Defect Reduction and Aluminum Redistribution in Silicon Implanted SOS Films," Journal of Crystal Growth, North-Holland Publishing Co., vol. 58, No. 1, Jun. 1982, pp. 53-60.42R. Reedy et al., "Suppressing A1 outdiffusion in implantation and recrystallized silicon on sapphire films," Applied Phys. Lett. 42 (8), 15 Apr. 1983, pp. 707-709.43 *R. Reedy et al., Characterization of Defect Reduction and Aluminum Redistribution in Silicon Implanted SOS Films, Journal of Crystal Growth, North Holland Publishing Co., vol. 58, No. 1, Jun. 1982, pp. 53 60.44 *R. Reedy et al., Suppressing A1 outdiffusion in implantation and recrystallized silicon on sapphire films, Applied Phys. Lett. 42 (8), 15 Apr. 1983, pp. 707 709.45Reedy et al., "Thin (100 nm) SOS for Application to Beyond VLSI Microelectronics," Materials Research Society Symp. Proc., vol. 107, Nov./Dec. 1988, pp. 365-376.46 *Reedy et al., Thin (100 nm) SOS for Application to Beyond VLSI Microelectronics, Materials Research Society Symp. Proc., vol. 107, Nov./Dec. 1988, pp. 365 376.47S. Chan et al., "Comparison of ESD Protection Capability of SOI and BULK CMOS Output Buffers," 1994 IEEE International Reliability Physics Proceedings, 23rd Annual, San Jose, CA, Apr. 12-14, 1994, pp. 292-297.48 *S. Chan et al., Comparison of ESD Protection Capability of SOI and BULK CMOS Output Buffers, 1994 IEEE International Reliability Physics Proceedings, 23rd Annual, San Jose, CA, Apr. 12 14, 1994, pp. 292 297.49S. Cohen et al., "An Improved Input Protection Circuit for C-MOS/SOS Arrays," IEEE Transactions on Electron Devices, vol. Ed. 25, No. 8, Aug. 1978.50 *S. Cohen et al., An Improved Input Protection Circuit for C MOS/SOS Arrays, IEEE Transactions on Electron Devices, vol. Ed. 25, No. 8, Aug. 1978.51S. Lau et al., "Improvement of crystalline quality of epitaxial Si layers by ion-implantation techniques," Applied Physics Letters, 34 (1), Jan. 1, 1979, pp. 76-78.52 *S. Lau et al., Improvement of crystalline quality of epitaxial Si layers by ion implantation techniques, Applied Physics Letters, 34 (1), Jan. 1, 1979, pp. 76 78.53 *S.M. Sze, Physics of Semiconductor Devices, Second Edition, John Wiley & Sons, Taipei, Taiwan, Sections 8.4.3 8.4.4. at pp. 344, 360, 477 485.54S.M. Sze, Physics of Semiconductor Devices, Second Edition, John Wiley & Sons, Taipei, Taiwan, Sections 8.4.3-8.4.4. at pp. 344, 360, 477-485.55 *Scaled Channel Length for N Channel and P Channel Transistors, Microprocessor Forum, Microprocessor Report, Nov. 12, 1992, pp. 1 10, and 4 pages drawings.56 *Search Report dated Jun. 24, 1996, International Application No. PCT/US96/01968.57Stanley Wolf, Ph.D. and Richard N. Tauber, Ph.D,; "Silicon Processing for the VLSI Era", vol. 1: Process Technology; Copyright 1986 by Lattice Press, Sunset Beach, California; title pages pp. 151-155.58 *Stanley Wolf, Ph.D. and Richard N. Tauber, Ph.D,; Silicon Processing for the VLSI Era , vol. 1: Process Technology; Copyright 1986 by Lattice Press, Sunset Beach, California; title pages pp. 151 155.59Stanley Wolf, Ph.D.; "Silicon Processing the VLSI Era", vol. 2: Process Integration; Copyright 1990 by Lattice Press, Sunset Beach, California; title pages pp. 66-83.60 *Stanley Wolf, Ph.D.; Silicon Processing the VLSI Era , vol. 2: Process Integration; Copyright 1990 by Lattice Press, Sunset Beach, California; title pages pp. 66 83.61Syed and Abidi, "Gigahertz Voltage-Controlled Ring Oscillator", Electronic Letters, Jun. 5, 1986, vol. 22, No. 12.62 *Syed and Abidi, Gigahertz Voltage Controlled Ring Oscillator , Electronic Letters, Jun. 5, 1986, vol. 22, No. 12.63T. Inoue et al., "Crystalline disorder reduction and defect-type change in silicon on sapphire films by silicon implantation and subsequent thermal annealing," Applied Physics Letters 36 (1) Jan. 1, 1980, pp. 64-67.64 *T. Inoue et al., Crystalline disorder reduction and defect type change in silicon on sapphire films by silicon implantation and subsequent thermal annealing, Applied Physics Letters 36 (1) Jan. 1, 1980, pp. 64 67.65T. Yamaguchi et al.: "Investigations of continuously variable threshold voltage devices (CVTD)," Solid State Devices, Proceedings of the 6th Conference on Solid State Devices, Tokyo, 1974, Supplement to the Journal of the Japan Society of Applied Physics, vol. 44, 1975, pp. 233-242, see abstract; p. 235, col. 2, line 34 --p. 236, col. 1, line 2; p. 239 col. 2, line 26 --p. 240, col. 2, line 11; figure 8a.66 *T. Yamaguchi et al.: Investigations of continuously variable threshold voltage devices (CVTD), Solid State Devices, Proceedings of the 6th Conference on Solid State Devices, Tokyo, 1974, Supplement to the Journal of the Japan Society of Applied Physics, vol. 44, 1975, pp. 233 242, see abstract; p. 235, col. 2, line 34 p. 236, col. 1, line 2; p. 239 col. 2, line 26 p. 240, col. 2, line 11; figure 8a.67W. Palumbo, M. Dugan, "Design and Characterization of Input Protection Networks for CMOS/SOS Applications" EOS/ESD Symposium Proceedings, 1986, pp. 182-187.68 *W. Palumbo, M. Dugan, Design and Characterization of Input Protection Networks for CMOS/SOS Applications EOS/ESD Symposium Proceedings, 1986, pp. 182 187.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6110765 *May 1, 1998Aug 29, 2000Micron Technology, Inc.Semiconductor devices and assembliesUS6143591 *Nov 12, 1998Nov 7, 2000Micron Technology, Inc.Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assembliesUS6174755Apr 29, 1999Jan 16, 2001Micron Technology, Inc.Methods of forming SOI insulator layers and methods of forming transistor devicesUS6245600Jul 1, 1999Jun 12, 2001International Business Machines CorporationMethod and structure for SOI wafers to avoid electrostatic dischargeUS6277680Oct 3, 2000Aug 21, 2001Micron Technology, Inc.Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assembliesUS6281056Dec 12, 2000Aug 28, 2001Micron Technology, Inc.Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assembliesUS6329689Jun 12, 2000Dec 11, 2001Micron Technology, Inc.Semiconductor devices comprising semiconductive material substrates and insulator layers over the substratesUS6331726Mar 21, 2000Dec 18, 2001International Business Machines CorporationSOI voltage dependent negative-saturation-resistance resistor ballasting element for ESD protection of receivers and driver circuitryUS6410962Apr 9, 2001Jun 25, 2002International Business Machines CorporationStructure for SOI wafers to avoid electrostatic dischargeUS6524870 *Apr 24, 2001Feb 25, 2003Pell, Iii Edwin A.Method and apparatus for improving resolution of objects in a semiconductor waferUS6835991Nov 7, 2002Dec 28, 2004Pell, Iii Edwin A.Method and apparatus for improving resolution of objects in a semiconductor waferUS6842318Mar 15, 2001Jan 11, 2005Microsemi CorporationLow leakage input protection device and scheme for electrostatic dischargeUS7375000Aug 22, 2005May 20, 2008International Business Machines CorporationDiscrete on-chip SOI resistorsUS8067280 *Nov 29, 2011Taiwan Semiconductor Manufacturing Co., Ltd.High performance CMOS devices and methods for making sameUS8080832 *Dec 20, 2011Pmc-Sierra Us, Inc.Semiconductor device for electrostatic discharge protectionUS8791529Apr 2, 2013Jul 29, 2014Semiconductor Energy Laboratory Co., Ltd.Semiconductor device including gate and conductor electrodesUS8962420Sep 3, 2009Feb 24, 2015Globalfoundries Inc.Semiconductor device comprising a buried poly resistorUS20030054604 *Nov 7, 2002Mar 20, 2003Mentor Graphics CorporationMethod and apparatus for improving resolution of objects in a semiconductor waferUS20050179483 *Nov 18, 2004Aug 18, 2005Hutchens Chriswell G.High-voltage transistors on insulator substratesUS20050195627 *Nov 18, 2004Sep 8, 2005Hutchens Chriswell G.High-temperature memory systemsUS20060091379 *Nov 18, 2004May 4, 2006Hutchens Chriswell GHigh-temperature devices on insulator substratesUS20070040236 *Aug 22, 2005Feb 22, 2007International Business Machines CorporationDiscrete on-chip soi resistorsUS20080169507 *Mar 24, 2008Jul 17, 2008International Business Machines CorporationDiscrete on-chip soi resistorsUS20080305590 *Aug 14, 2008Dec 11, 2008Taiwan Semiconductor Manufacturing Co., Ltd.High performance cmos devices and methods for making sameUS20100078645 *Apr 1, 2010Andreas KurzSemiconductor device comprising a buried poly resistorUS20130193787 *Jan 24, 2013Aug 1, 2013Asmo Co., Ltd.Motor and brushless motorDE102008049732B4 *Sep 30, 2008Jun 9, 2011Amd Fab 36 Limited Liability Company & Co. KgHalbleiterbauelement mit vergrabenem Polysiliziumwiderstand sowie Verfahren zu seiner Herstellung* Cited by examinerClassifications U.S. Classification257/379, 257/E21.004, 257/E21.121, 257/E27.101, 257/E27.112, 257/E29.286, 257/347, 257/E27.111, 257/E29.278, 257/E21.133, 257/57, 257/E29.287, 257/537International ClassificationH01L21/86, H01L29/8605, H01L27/12, H01L21/02, H01L29/786, H01L21/20, H01L27/11Cooperative ClassificationH01L21/02694, H01L21/02532, H01L21/0242, H01L27/12, H01L29/78657, H01L29/78621, H01L27/1112, H01L29/78654, H01L29/8605, H01L28/20, H01L27/1203, H01L21/86European ClassificationH01L28/20, H01L29/8605, H01L21/86, H01L29/786E2, H01L27/11R, H01L29/786E2B, H01L27/12, H01L21/20B4, H01L29/786B4B, H01L27/12B, H01L21/20DLegal EventsDateCodeEventDescriptionMar 25, 1996ASAssignmentOwner name: PEREGRINE SEMICONDUCTOR CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:REEDY, RONALD E.;REEL/FRAME:007859/0623Effective date: 19960320Dec 24, 1996ASAssignmentOwner name: PEREGRINE SEMICONDUCTOR CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:REEDY, RONALD E.;BURGENER, MARK L.;REEL/FRAME:008318/0200;SIGNING DATES FROM 19961209 TO 19961214Jun 15, 1999CCCertificate of correctionJun 23, 1999ASAssignmentOwner name: PATTON, JOHN B., OHIOFree format text: SECURITY AGREEMENT;ASSIGNOR:PEREGRINE SEMICONDUCTOR CORPORATION;REEL/FRAME:010043/0685Effective date: 19990517Feb 12, 2002ASAssignmentOwner name: MORGENTHALER PARTNERS VI, L.P., CALIFORNIAFree format text: SECURITY INTEREST;ASSIGNOR:PEREGRINE SEMICONDUCTOR CORPORATION;REEL/FRAME:012391/0034Effective date: 20020208Jul 3, 2002FPAYFee paymentYear of fee payment: 4Sep 6, 2002ASAssignmentOwner name: MORGENTHALER PARTNERS VI, L.P., CALIFORNIAFree format text: RELEASE OF SECURITY INTEREST IN PATENTS, PREVIOUSLY RECORDED AT REEL/FRAME 012391/0034, FILED FEB. 12, 2002;ASSIGNOR:PEREGRINE SEMICONDUCTOR CORPORATION;REEL/FRAME:013067/0166Effective date: 20020906Oct 8, 2002ASAssignmentOwner name: PEREGRINE SEMICONDUCTOR CORPORATION, CALIFORNIAFree format text: RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 010043/0685, FILED JUNE 23,1999);ASSIGNOR:PATTON, JOHN;REEL/FRAME:013362/0608Effective date: 19990623Aug 16, 2006REMIMaintenance fee reminder mailedSep 21, 2006SULPSurcharge for late paymentYear of fee payment: 7Sep 21, 2006FPAYFee paymentYear of fee payment: 8Jun 1, 2010FPAYFee paymentYear of fee payment: 12Oct 9, 2013ASAssignmentOwner name: PEREGRINE SEMICONDUCTOR CORPORATION, CALIFORNIAFree format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGENTHALER PARTNERS VI, L.P.;REEL/FRAME:031376/0194Effective date: 20131009RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


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ESPNMAG.com - 'Rent control
'Rent control
When and how exactly was it that everybody seemed to bury Casey Jacobsen? Wrote him off the "all-" teams. Took his frost-haired mug down from the "star" lists. Figured he was just another one-dimensional, point-crazy beach boy who couldn�t play without all those Stanford rebounders and passers and screeners who left him for the NBA.
Was it after his three-for-17 shooting flop in that early loss to Texas? His two-points-in-the-final-ten-minutes coughing fit in another upset to BYU? His scarcity of shots (barely seven in the first game?) and lack of impact while splitting that nonsensical, three-day doubleheader against hated rival Cal? Or maybe it was merely an avenging-angel, human nature kind of thing. Pure jealousy and joy that The Casester was always simply too ... too ... rich, preppy, clever, cocky and fine-looking. His spiked-up bleach job was the most talked-about cosmetic look on television until Greta Van Susteren had her eyes lifted back to 1984 -- and maybe Casey was finally getting his. But just when Pac-10 opponents thought it safe to emerge from his backwater, Jacobsen has exploded all over again -- firing away from outrageous angles and distances while lighting up Arizona State for 49 points and Oregon for 41 in two of his last four games -- as revived Stanford (whose other star, center Curtis Borchardt, may be the most underrated big man in the land) has moved to 15 wins (8-4 in the conference) and solidified another NCAA tournament bid. In the process Jacobsen has reminded all of us how really tough and ornery and big-occasion dedicated a kid can be -- he�s 2-0 career against the school which spurned him (a place commonly referred to as Duke) and he again bagged UCLA in Pauley in January -- who grew up laboring on his ultra-demanding father�s homemade court and taking severe hoop lickings from two older brothers. Oh yeah, and besides, who was supposed to be, for godsakes, a girl!
Boys came as easy as the ABC�s to Von and Becky Jacobsen of Glendora, Calif. So they named them as such: Adam, Brock, Casey and, most recently, Derek (14). "But sure, I always wished for a daughter," says Becky, an original surfer chick out of San Clemente, Calif. "We actually bought a book and tried to do some of the little tricks that are supposed to enhance your chances of a baby being a girl. They always say girls are conceived in acid, boys in alkaline, right? Like, vinegar is acid, baking soda is alkaline." The little tricks? "Have we met before? I don�t think we can talk about this anymore," Becky laughs, leaving an inquiring reporter more bewildered than ever. "We were sure Casey would be the girl," says Becky. "But then he came in at 12 pounds, big boned, very sharp. I think he must have stretched me or moved things around or something because when I got pregnant again, I didn�t get that big. So I thought, aha, this must be the girl. Lo and behold, Derek weighed 12 pounds, 8 ounces. Jeez. Von�s 6'4", I�m 5'10". But now Derek�s on the same size track as Casey at the same age. Only he outweighs him by about 25 pounds."
In other words, Derek will be the first power forward among the brotherhood of perimeter Jacobsen marksmen who are the first set of bros to swish 600 combined career NCAA trifectas. Adam made 311 treys at Pacific, Brock totaled 92 at the University of San Diego and Casey has 209. It wasn�t as if Von was The Great Santini (though he sometimes loudly DuValled the heck out of his boys) or even the second coming of Marv Marinovich -- who maniacally raised infamous son, Todd, into that RoboQB who wound up his career tragically wallowing in rebellion, naked surfing, garage bands, drugs and jail. Indeed, Jacobsen pere was a friend of Marinovich and employed many of his motivational techniques. "I�d tear �em down," says Von, referring to his sons. "But Becky was a complement to the whole deal. When they�d cry, she�d hug �em and build them right back up. It was a two-way thing." Ironically, the Jacobsen parents are both Mormons who attended Brigham Young University for varying periods at varying times. They didn�t meet until after college, when Von was beginning his construction career at the Mammoth Mountain ski resort following his basketball playing days at San Diego State and in Europe. "I was working at my dad�s hamburger stand at Mammoth, a place called The Barking Spider," says Becky. "We were both Mormon but we don�t really identify ourselves like that. We both left BYU and went elsewhere. Actually, after we got married and started raising the boys ... playing all those basketball games on Sundays, the church really frowned on us. "Von has taken some serious hits about how he raised Casey and all the boys on basketball," Becky continues. "It did consume our lives. But our relationships with them are so close and loving, we�ve always laughed and wondered, gee, is there really something wrong with us? The only thing I�d change is Von�s timing. He was so tough on Casey right after a game when things were so emotional, the car rides home could be brutal. But a day later, when everybody was much more accepting ... I thought that would be a better time to talk. Von just didn�t want to wait."
"I was intimidated most of the time by my dad," Casey says. "My mom was more my friend growing up. If I had a problem, I�d go to her. But after I got to Stanford I realized that everything my dad did helped prepare me for what was to come. Now we�re closer than we ever were before. He�s even more of a friend now than a dad." Meanwhile, it�s Becky who does the honors on Casey's frost job every few weeks or so. Comes up to Palo Alto on game days with the essential products and spikes up the color right there in the dorm room. "Surprisingly, I don�t take much ragging from the team about it," Casey says. "I�ve always been real straight with them. Told them I didn�t like my original color so I changed it. In the summers I bleach the whole thing. I would dye it blond if I could. But coach (Mike Montgomery) doesn�t like it. He�s an old-school guy and he doesn�t like anything that singles out anybody on the court. He wants a guy�s play to do that. My hair isn�t as important to me as keeping my coach happy."
Not that Jacobsen has completely succeeded in that. When John Montgomery, the coach�s 18-year old son, turned up with a similar dye job last year -- the coach subsequently hitting the roof -- John�s explanation was completely plausible. "If Casey can do it ..." he said.
At least Montgomery can find comfort in the fact that, as the events of the last few weeks on The Farm have proven, Casey can still do it.
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