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Patent US6889896 - Computer system for collaborative document markup - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe invention concerns a computer system enabling collaborative document markup. Employing the invention involves the use of one or more forms which support interaction with a computer system or network. Each form is printed on sheet material such as paper and includes printed data readable by the user...http://www.google.com/patents/US6889896?utm_source=gb-gplus-sharePatent US6889896 - Computer system for collaborative document markupAdvanced Patent SearchPublication numberUS6889896 B2Publication typeGrantApplication numberUS 10/853,356Publication dateMay 10, 2005Filing dateMay 26, 2004Priority dateJun 30, 1999Fee statusPaidAlso published asCA2414745A1, CA2414745C, CA2414759A1, CA2414759C, CN1205529C, CN1367891A, CN1658140A, CN100383715C, DE60039887D1, EP1203283A1, EP1203283A4, EP1203283B1, EP1203314A1, EP1203314A4, EP1203314B1, US6766942, US6976035, US6991153, US6991154, US7004390, US7044363, US7415668, US7571193, US7895159, US20030093757, US20030106018, US20030106024, US20040217160, US20050166145, US20050166146, US20050270577, US20080304888, US20090273807, US20110102845, US20110142520, WO2001002939A1, WO2001002995A1Publication number10853356, 853356, US 6889896 B2, US 6889896B2, US-B2-6889896, US6889896 B2, US6889896B2InventorsKia Silverbrook, Paul Lapstun, Jacqueline Anne LapstunOriginal AssigneeSilverbrook Research Pty LtdExport CitationBiBTeX, EndNote, RefManPatent Citations (23), Non-Patent Citations (1), Referenced by (13), Classifications (105), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetComputer system for collaborative document markupUS 6889896 B2Abstract The invention concerns a computer system enabling collaborative document markup. Employing the invention involves the use of one or more forms which support interaction with a computer system or network. Each form is printed on sheet material such as paper and includes printed data readable by the user and coded data which allows interaction with the computer system via a sensing device operated by a user.
The controlling processor 145 captures and decodes location data from tags from the surface via the image sensor 132, monitors the force sensor photodiode 144, controls the LEDs 30 116, 131 and 143, and handles short-range radio communication via the radio transceiver 153. It is a medium-performance (�40 MHz) general-purpose RISC processor.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4864618Oct 17, 1988Sep 5, 1989Wright Technologies, L.P.Automated transaction system with modular printhead having print authentication featureUS4977520Feb 3, 1988Dec 11, 1990Ibm Corp.Method to facilitate a reply to electronic meeting invitation in an interactive multi-terminal system employing electronic calendarsUS5051736Jun 28, 1989Sep 24, 1991International Business Machines CorporationOptical stylus and passive digitizing tablet data input systemUS5220657Apr 15, 1991Jun 15, 1993Xerox CorporationUpdating local copy of shared data in a collaborative systemUS5477012Apr 3, 1992Dec 19, 1995Sekendur; Oral F.Optical position determinationUS5486686May 18, 1992Jan 23, 1996Xerox CorporationHardcopy lossless data storage and communications for electronic document processing systemsUS5652412Jul 11, 1994Jul 29, 1997Sia Technology Corp.Pen and paper information recording systemUS5661506Nov 10, 1994Aug 26, 1997Sia Technology CorporationPen and paper information recording system using an imaging penUS5692073Jul 30, 1996Nov 25, 1997Xerox CorporationFormless forms and paper web using a reference-based mark extraction techniqueUS5852434Dec 18, 1995Dec 22, 1998Sekendur; Oral F.Coordinate sensorUS5862321Jun 21, 1995Jan 19, 1999Xerox CorporationSystem and method for accessing and distributing electronic documentsUS5869819Apr 7, 1997Feb 9, 1999Metrologic Instuments Inc.Internet-based system and method for tracking objects bearing URL-encoded bar code symbolsUS6076734Oct 10, 1997Jun 20, 2000Interval Research CorporationMethods and systems for providing human/computer interfacesUS6081261Nov 1, 1995Jun 27, 2000Ricoh CorporationManual entry interactive paper and electronic document handling and processing systemUS6330976 *Mar 25, 1999Dec 18, 2001Xerox CorporationMarking medium area with encoded identifier for producing action through networkUS6460766Mar 17, 2000Oct 8, 2002Francis OlschafskieGraphic symbols and method and system for identification of sameUS6466955Nov 25, 1996Oct 15, 2002Nec CorporationInformation processing apparatus and method for displaying same shared data in different formats among different terminalsUS6628847May 15, 2002Sep 30, 2003Carnegie Mellon UniversityMethod and apparatus for recognition of writing, for remote communication, and for user defined input templatesUS6666376May 26, 2000Dec 23, 2003Anoto AbCalendarUS6766942 *Jun 30, 2000Jul 27, 2004Silverbrook Research Pty LtdMethod and system for collaborative document markupGB2396669A Title not availableWO1999018487A2Oct 1, 1998Apr 15, 1999Interval Research CorpMethods and systems for providing human/computer interfacesWO1999050787A1Sep 30, 1998Oct 7, 1999Max CoppermanCross-network functions via linked hardcopy and electronic documents* Cited by examinerNon-Patent CitationsReference1Dymetman, M., and Copperman, M., Intelligtent Paper; in Electronic Publishing, Artistic Imaging, and Digital Typography, Proceedings of EP '98, Mar./Apr. 1998, Springer Verlag LNCS 1375, pp. 392-406.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6991153 *Mar 18, 2005Jan 31, 2006Silverbrook Research Pty LtdComputer system for enabling collaborative document markup between participantsUS6991154 *Mar 18, 2005Jan 31, 2006Silverbrook Research Pty LtdMethod for enabling collaborative document markup between participantsUS7542927 *Jul 18, 2007Jun 2, 2009International Business Machines CorporationProduct purchase system, product purchase method, a storage medium for storing a program for executing the product purchasing method, and a server used thereforUS7784514 *Jul 10, 2008Aug 31, 2010Silverbrook Research Pty LtdGlue wheel arrangement for a printer having a media feed assemblyUS7890920Apr 30, 2009Feb 15, 2011International Business Machines CorporationStorage medium for storing a program for executing the product purchasing method, and a server used thereforUS7913162 *Dec 20, 2005Mar 22, 2011Pitney Bowes Inc.System and method for collaborative annotation using a digital penUS7945595May 12, 2008May 17, 2011Adobe Systems IncorporatedSystem and method for generating an item list in electronic contentUS7949633May 12, 2008May 24, 2011Adobe Systems IncorporatedShared edit access of electronic contentUS8069226Sep 30, 2004Nov 29, 2011Citrix Systems, Inc.System and method for data synchronization over a network using a presentation level protocolUS8190676Apr 20, 2010May 29, 2012Citrix Systems, Inc.System and method for event detection and re-direction over a network using a presentation level protocolUS8290902Apr 6, 2011Oct 16, 2012Adobe Systems IncorporatedShared edit access of electronic contentUS8396900Apr 6, 2011Mar 12, 2013Adobe Systems IncorporatedSystem and method for editing an item list in electronic contentUS8768885Sep 12, 2012Jul 1, 2014Adobe Systems IncorporatedShared edit access of electronic content* Cited by examinerClassifications U.S. Classification235/375, 235/454International ClassificationG06F15/00, G06F3/042, G06F3/041, G06K17/00, G06F3/048, G06F17/21, B41J2/175, B65H29/34, B41J2/21, G06F3/033, H04N1/00, G06F3/12, H04N1/32, B41J13/10, B42C9/00, H04N1/327, B65H37/04, B42C19/02, G06K9/22Cooperative ClassificationB41J2/17503, H04N2201/3249, B41J13/103, G06K9/222, H04N2201/3247, B41J2/17513, H04N1/32778, B42P2261/04, H04N2201/3226, H04N1/00244, H04N2201/3207, B42C19/02, H04N2201/0082, H04N2201/3278, H04N1/00204, B65H37/04, B42C9/0006, H04N1/32771, G06F2203/0337, H04L12/1827, H04N1/00127, H04N2201/3242, H04N2201/327, B41J2/2114, H04N2201/3243, G06F3/04883, G06K17/00, B41J2/17523, H04N1/00968, B41J2/17563, H04N2201/3205, H04N1/00326, B42C9/0081, H04N1/00358, H04N1/32101, H04N1/00567, H04N1/00376, B41J2/17556, B41J13/106, G06F3/03545, H04N1/32128, H04N2201/3271, B41J2/17553, H04N2201/3269, H04N1/32122, B65H29/34, B41J2/17546, G06F3/1284, G06F3/1243, G06F17/242, G06F17/218, G06F3/1204European ClassificationG06K17/00, B41J2/175C, H04N1/00C22, H04N1/00C3K, H04N1/00D2B2, H04N1/00D2B4, H04N1/00W2, H04N1/327F4M, G06F3/0488G, G06F3/0354N, B41J13/10C, H04N1/32C, H04N1/00C3, H04N1/32C15D, G06K9/22H, B41J2/21B2, B41J2/175C8, H04N1/32C17, B42C19/02, B65H29/34, B42C9/00B, B42C9/00D, B41J2/175C7E, H04N1/00F, G06F3/12T, B41J2/175C9, H04N1/327F4, B65H37/04, B41J13/10B, B41J2/175C2, B41J2/175C3A, B41J2/175FLegal EventsDateCodeEventDescriptionOct 21, 2012FPAYFee paymentYear of fee payment: 8Nov 3, 2008FPAYFee paymentYear of fee payment: 4May 26, 2004ASAssignmentOwner name: SILVERBROOK RESEARCH PTY. LTD., AUSTRALIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SILVERBROOK, KIA;LAPSTUN, PAUL;LAPSTUN, JACQUELINE ANNE;REEL/FRAME:015385/0419Effective date: 20040415Owner name: SILVERBROOK RESEARCH PTY. LTD. 393 DARLING STREETBFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SILVERBROOK, KIA /AR;REEL/FRAME:015385/0419RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google

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Patent US5754802 - Increasing data transfer efficiency for a read operation in a non-split ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method and apparatus for increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation. The data transfer efficiency is increased and deadlocking is reduced by substituting two write operations (one from...http://www.google.com/patents/US5754802?utm_source=gb-gplus-sharePatent US5754802 - Increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operationAdvanced Patent SearchPublication numberUS5754802 APublication typeGrantApplication numberUS 08/648,424Publication dateMay 19, 1998Filing dateMay 15, 1996Priority dateMay 14, 1995Fee statusLapsedPublication number08648424, 648424, US 5754802 A, US 5754802A, US-A-5754802, US5754802 A, US5754802AInventorsKoichi Okazawa, Hideki Osaka, Kenichi SaitouOriginal AssigneeHitachi, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (8), Non-Patent Citations (2), Referenced by (7), Classifications (13), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetIncreasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation
US 5754802 AAbstract
A method and apparatus for increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation. The data transfer efficiency is increased and deadlocking is reduced by substituting two write operations (one from an I/O device to a bus controller and the other from the bus controller to the I/O device) for one read operation. Further, the present invention improves the efficiency of data transfer by maintaining the compatibility of a bus specification when DMA of an I/O bus having no split transfer function, such as a PCI bus or inter-I/O transfer, is executed. A processor instructs a data transfer operation to an I/O device or bus conversion adapter. The I/O device or bus conversion adapter connected to a bus outputs a write access, and a bus connection controller connected to the bus receives the write access and reads data in a main memory. The bus connection controller then transfers read data to the I/O device or the bus conversion adapter. Such an operation may also be performed between two I/O devices or bus conversion adapters.
1. A data transfer system for transmitting data between modules connected by a bus, comprising:a main memory; a processor bus connected to said memory; a bus connection controller connected to said processor bus; a system bus connected to said bus connection controller; an I/O device connected to said system bus, said I/O device executing a write access to said bus connection controller via said system bus; said bus connection controller receiving said write access, reading data from said main memory, and executing said write access so as to transfer said data to said I/O device, said bus connection controller including a storage portion for storing said data outputted by said write access; a processor connected to said processor bus, said processor issuing an operation instruction to said I/O device, and said I/O device executing said write access to said bus connection controller according to said operation instruction; said data outputted by said write access including:a request address indicating the address of said storage portion of said bus connection controller, a read address indicating the address where said bus connection controller reads said data from said main memory, and a return address indicating the address where said data transferred to said I/O device from said bus connection controller is stored; said bus connection controller further including:a request queue for queuing said write access to said bus connection controller, and a first request register for setting an address of said request queue by said request address; and said I/O device including:a second request address setting register for setting a request address which is the address of said request queue to which said write access to said bus connection controller is executed, and a return address setting register for setting an address indicating the destination of said data outputted by said bus connection controller. 2. A data transfer system according to claim 1, wherein upon receipt of a read access request from said I/O device, said system bus is occupied by said read access request during a period from said read access request until output of data according to said read access request to said I/O device.
3. A data transfer system according to claim 1, wherein said bus connection controller executes a read access to said main memory by said read address outputted as write access data from said I/O device and stores the return address for said I/O device in said request queue.
4. A data transfer system according to claim 3, wherein when an error occurs in said read access request to said main memory, said bus connection controller assigns an error code to a return address indicating the address of write access to said I/O device.
5. A data transfer system according to claim 1, wherein said I/O device is a bus conversion adapter.
6. A data transfer system for transmitting data between modules connected by a bus, comprising:a processor bus; a first and a second bus connection controller connected to said processor bus; a first system bus connected to said first bus connection controller and a second system bus connected to said second bus connection controller; a first I/O device connected to said first system bus and a second I/O device connected to said second system bus, said first I/O device executing a write access to said first bus connection controller via said first system bus; said first bus connection controller receiving said write access from said first I/O device, reading data from said second I/O device via said processor bus and said second bus connection controller, and executing said write access so as to transfer said data of said second I/O device to said first I/O device, said first bus connection controller including a storage portion for storing said data outputted by said write access; a processor connected to said processor bus, said processor issuing an operation instruction to said first I/O device, and said first I/O device executing said write access to said first bus connection controller according to said operation instruction; said data outputted by said write access including:a request address indicating the address of said storage portion of said first bus connection controller, a read address indicating the address where said first bus connection controller reads said data from said second I/O device, and a return address indicating the address where data transferred to said first I/O device from said first bus connection controller is stored; said first I/O device including:a first request address setting register for setting a request address which is the address of a request queue to which said write access to said bus connection controller is executed, and a return address setting register for setting an address indicating the destination of said data outputted by said first bus connection controller; and said second I/O device including:a second request address setting register for setting a second request address for discriminating said write access from said first I/O device. 7. A data transfer system according to claim 6, wherein said first I/O device is a bus conversion adapter.
The present invention relates to a data transfer system and a device relating to it, that is, a data transfer system used for an information processor such as a personal computer, a work station, or an office computer and more particularly to a data transfer system and a device relating to it for improving the bus use efficiency when each module transmits and receives data via a bus having no split transfer function.
In an information processor such as a personal computer, as a conventional data transfer method, a so-called direct memory access (hereinafter abbreviated to DMA) is carried out.
The DMA is a method that, for example, an I/O device and a bus conversion adapter become a bus master of the system bus respectively and the I/O device or the bus conversion adapter executes read or write access to the main memory according to the setting of the main CPU so as to transfer data between the I/O device or the bus conversion adapter and the main memory. In this case, the system bus is, for example, a PCI bus (peripheral component interconnect bus) and the I/O device is possibly a disk control unit or network control unit connected to the system bus. The bus conversion adapter is a device for connecting a low order bus such as an EISA bus.
An art with respect to this DMA is described in, for example, Japanese Patent Application Laid-Open 5-173936 (Prior Art 1).
Recently, an inter-I/O transfer method for directly transferring data between I/O devices or bus conversion adapters by applying the aforementioned DMA method to a plurality of I/O devices or bus conversion adapters has also been used.
With respect to an art for applying this DMA method to a plurality of I/O devices or bus conversion adapters, an inter-I/O transfer by an extension bus having no split transfer function such as a PCI bus is described in, for example, Japanese Patent Application Laid-Open 6-131295 (Prior Art 2).
"Split transfer" is a transfer method of transferring data by splitting the read access into two accesses such as a request of address transfer and a return of data transfer and it is a method of improving the use efficiency of bus by executing another access on the bus during the two accesses of request and return.
A bus to which the present invention is applied is a bus having no split transfer function such as a PCI bus and a system having one or a plurality of I/O buses having no split transfer function such as a PCI bus is described in "PCI As New Industrial Standard Of I/O Bus", Nikkei Electronics, Jun. 6, 1994 Issue (No. 609), p. 67-96.
The Prior Art 1 is an art with respect to DMA of directly transferring data between the main memory and the I/O device and the Prior Art 2 is an art of transferring data between I/O devices connected to a plurality of extension buses having no split transfer function.
In an information processor in recent years, as processing of a large amount of data such as video data increases, increasing of the speed of data transfer in an information processor using a system bus is a big problem. However, in a personal computer, increasing of the speed by modifying the system bus such as a PCI bus is restricted due to maintaining of the compatibility and it is necessary to improve the efficiency of data transfer with the compatibility of the bus specification maintained.
However, in DMA of the Prior Art 1 or inter-I/O transfer of the Prior Art 2, both of read access and write access are executed viewed from the I/O device which is a bus master or the bus conversion adapter. In this case, a problem arises that in a system bus having no split transfer function such as a PCI bus, the data transfer efficiency of read access is worse than that of write access. The reason is that in a system bus having no split transfer function such as a PCI bus, during the period from output of an address to the system bus for read access to output of data, the bus is occupied unnecessarily.
In inter-I/O transfer in a system bus having a plurality of I/O buses having no split transfer function such as a PCI bus, it is pointed out that if read accesses from a plurality of extension buses are in contention, there is a possibility of occurrence of a deadlock as described also in the Prior Art 2. The Prior Art 2 takes a countermeasure of preventing read accesses from occurring in a plurality of extension buses at the same time for it.
Buses having a transfer retry function can take a countermeasure of retrying read accesses occurring at the same time. However, a problem arises that since read accesses are suppressed in either case, the data transfer efficiency gets worse.
The present invention is designed to eliminate the difficulties of the prior arts mentioned above and an object thereof is to provide a means for eliminating a possibility of occurrence of a deadlock and improving the efficiency of data transfer by maintaining the compatibility of the bus specification when DMA of an I/O bus having no split transfer function such as a PCI bus or inter-I/O transfer is executed.
The present invention is a data transfer system for connecting each module by a bus and transferring data, and the system comprises a main memory, a processor bus connected to the main memory, a bus connection controller connected to the processor bus, a system bus connected to the bus connection controller, and an I/O device or a bus conversion adapter connected to the system bus, and the I/O device or the bus conversion adapter executes write access to the bus connection controller via the system bus, and the bus connection controller receives the write access, reads data from the main memory, and executes write access to the I/O device or the bus conversion adapter so as to transfer the data of the main memory to the I/O device or the bus conversion adapter.
The data transfer system of the present invention has a processor connected to the processor bus, and the processor issues an operation instruction to the I/O device or the bus conversion adapter, and the I/O device or the bus conversion adapter executes write access to the bus connection controller according to the operation instruction.
In the data transfer system of the present invention, the bus connection controller has a storage portion for storing data outputted by the write access from the I/O device or the bus conversion adapter.
In the data transfer system of the present invention, the data outputted by the write access to the bus connection controller from the I/O device or the bus conversion adapter includes a request address indicating the address of the storage portion of the bus connection controller, a read address indicating the address when the bus connection controller reads data from the main memory, and a return address indicating the address when data transferred to the I/O device or the bus conversion adapter from the bus connection controller is stored.
In the data transfer system of the present invention, the bus connection controller has a request queue for queuing the write access and a first request register for setting an address of the request queue by the request address and the I/O device or the bus conversion adapter has a second request address setting register for setting a request address which is the address of the request queue to which the write access of the bus connection controller is executed and a return address setting register for setting an address indicating the destination of the write access outputted by the bus connection controller.
In the data transfer system of the present invention, upon receipt of a read access request from the I/O device or the bus conversion adapter, the system bus is a bus occupied by the corresponding read access during the period from the read access request to output of data according to the read access request to the I/O device or the bus conversion adapter.
In the data transfer system of the present invention, the bus connection controller executes read access to the main memory by the read address outputted as write access data from the I/O device or the bus conversion adapter and stores the return address for the I/O device or the bus conversion adapter in the request queue.
In the data transfer system of the present invention, when an error occurs in the read access to the main memory, the bus connection controller assigns an error code to a return address indicating the address of write access to the I/O device or the bus conversion adapter.
By doing this, write access is executed to the bus connecting each module two times instead of read access being executed once. Namely, when a read access request is issued from the I/O device to the main memory, the bus is generally occupied during the period from the read access request until data is read from the main memory by the read access request and the data is transferred to the I/O device. However, according to the present invention, the bus can be released by executing write access to the bus connection controller from the I/O device, so that the released bus can be used for data transfer to another I/O device. Therefore, even if a bus having no split transfer function is used, a defect that the bus is occupied unnecessarily during read access can be avoided, and the bus use efficiency can be increased, and the data transfer efficiency can be increased.
When this protocol is used, even if data is transferred by using a plurality of buses, a deadlock will not occur.
Furthermore, the same bus specification as the conventional one can be used, so that a system having the compatibility with the conventional bus can be constructed.
According to the present invention, a plurality of I/O devices or bus conversion adapters are switched to the bus master alternately, so that a plurality of read accesses can be executed in parallel with substituting write accesses on the system bus. Furthermore, an I/O device or a bus conversion adapter can execute read access continuously in parallel with substituting write access without waiting for reception of data, so that the system bus use efficiency viewed from each I/O device or bus conversion adapter can be increased.
FIG. 1 is a system block diagram showing the hardware constitution of the data transfer system of the present invention.
FIG. 2 is a schematic diagram showing the access format of write access for request.
FIG. 3 is a timing chart showing data timing for executing DMA in comparison of the method by the prior art with the method of the present invention. (a) indicates the data timing by the prior art and (b) indicates the data timing of the present invention.
FIG. 4 is a system block diagram showing the hardware constitution of the second data transfer system of the present invention.
FIG. 5 is a flow chart showing the sequence operation of the sequencer in the I/O device 104 when DMA transfer of the data transfer system of the present invention is executed.
FIG. 6 is a flow chart showing the sequence operation of the sequencer in the bus connection controller 103 when DMA transfer of the data transfer system of the present invention is executed.
The embodiments of the present invention will be explained hereunder with reference to FIGS. 1 to 6.
Firstly, the system constitution of the data transfer system will be explained by referring to FIG. 1.
The present invention will be explained hereunder using a case that data stored in a main memory 102 is transferred to an I/O device 104 by DMA transfer.
A main CPU 101 and the main memory 102 are connected to a bus connection controller 103 by a processor bus 103 and data can be transmitted or received between the three devices.
The bus connection controller 103 and the I/O device 104 are connected to each other by a system bus 106 and data can be transmitted or received between them. The I/O device has a bus master function. The system bus 106 is a system bus such as, for example, a PCI bus having no split transfer function.
The bus connection controller 103 has a request address setting register 131 and a request queue 132.
On the other hand, the I/O device 104 has a mode setting register 141, a request address setting register 142, and a return address setting register 143.
The request address setting register 131, the mode setting register 141, the request address setting register 142, and the return address setting register 143 are assigned addresses on the system bus 106 and can be accessed via the system bus 106.
The mode setting register 141 is a flag register, which is set to ON when DMA transfer is executed by the data transfer method of the present invention and set to OFF when it is not executed. By default, it is set to OFF.
In this embodiment, the I/O device 104 is considered as an object of DMA. However, the same operation is available for the bus connection adapter.
In data transfer of the present invention, special operations are performed by the request address setting register 131 and the request queue 132 in the bus connection controller 103 and the mode setting register 141, the request address setting register 142, and the return address setting register 143 in the I/O device 104. However, functions other than the functions of the data transfer method of the present invention may be the same as those of the prior art.
Although not shown in FIG. 1, the bus connection controller 103 and the I/O device 104 have a sequencer for controlling the data transfer operation in the same way as with the prior art.
Next, the operation of the data transfer system will be explained by referring to FIGS. 2, 5, and 6 in addition to FIG. 1.
Firstly, the main CPU 101 sets a request address in the request address setting register 131 in the bus connection controller 103 and the request address setting register 142 in the I/O device 104.
This request address is used to issue a request to the bus connection controller 103 from the I/O device 104 and access the request queue 132 in the bus connection controller 103.
The main CPU 101 sets a return address in the return address setting register 143 in the I/O device 104. This return address is the address of the storage location when the bus connection controller 103 sends data of the main memory 102 to the I/O device 104. The main CPU 101 changes and sets the mode setting register 141 to ON.
The initialization is completed now.
The operation of the data transfer system varies with the value of the mode setting register 141.
When the value of the mode setting register 141 is OFF, the data transfer system performs the normal operation. Namely, when the I/O device 104 is instructed to execute DMA read access from the main CPU 101, the system executes DMA read access in the same way as with the prior art.
Therefore, when the value of the mode setting register 141 is OFF, the I/O device 104 can operate in compatibility with a conventional interface even on a system in which the method of the present invention is not executed.
When the mode setting register 141 is ON, the data transfer system performs the operation of the data transfer method of the present invention.
When the I/O device 104 is instructed to execute DMA read access from the main CPU 101 in this case, the device executes write access to the request address set in the request address setting register 142 instead of read access.
Next, the access format outputted from the I/O device 104 at this time will be explained by referring to FIG. 2.
The access format comprises an address of one word at the beginning and data of 2 words behind it as a write access format.
In this format, the request address (QA) set in the request address setting register 142 in the I/O device 104 is outputted as an address first and then the read address (DA) and the return address (TA) set in the return address setting register 143 are outputted as data. The read address (DA) indicates the address of the main memory for read access.
When write access in the aforementioned access format is issued via the system bus 106 and the address of the request address (QA) matches with the address stored in the request address setting register 131, the bus connection controller 103 judges it as "write access substituting for read access" (it is write access viewed from the I/O device 104 but aims at write access really; hereinafter the access procedure of the data transfer method of the present invention is referred to as it) and receives data.
The processor bus 105 receives this request, issues read access at the read address (DA) sent as data, and stores the return address (TA) in the request queue 132.
When the request queue 132 is saturated in this case (the queue is full and no more data can be stored), the processor bus 105 refuses the request by a means such as returning a retry response.
By this read access at the read address (DA), data is sent to the bus connection controller 103 from the main memory 102.
Next, the bus connection controller 103 becomes a bus master of the system bus 106 and executes write access in a format that data sent from the main memory 102 is added behind the return address (TA) stored in the request queue 132 which is set as an address.
When an error such as an ECC error (error checking code error) or a bus parity error occurs in the main memory 102, the bus connection controller 103 informs the I/O device 104 of the error by a means such as executing write access in a format that an error code is added to the return address (TA).
When the return address (TA) set in the return address setting register 143 in the I/O device 104 is write-accessed via the system bus 106, the I/O device 104 judges it as write access substituting for read access of the present invention and receives the data of the main memory 102 corresponding to the read address (DA).
By doing this, one read access generated on the system bus 106 is substituted by two write accesses including write access to the bus connection controller from the I/O device and write access to the I/O device from the bus connection controller. In this case, the two write accesses can be seen as general write access on the system bus, so that the interface compatibility with general write access can be maintained.
The sequencer in the I/O device 104 just performs an operation of outputting the read address (DA) and receiving data corresponding to it. Therefore, although read access to the system bus 106 is issued in the general procedure, it is desirable to just convert it to write access of the method of the present invention. Therefore, to realize a function other than it, it is desirable to just allow the sequencer to operate in the same way as with the prior art.
Next, the I/O device 104 for playing an important part of the system and the sequence operation of the sequencer of the bus connection controller 103 will be explained with reference to FIGS. 5 and 6 according to the procedure of the data transfer method of the aforementioned system.
As shown in FIG. 5, when read access starts, the sequencer in the I/O device 104 checks first whether the mode setting of the mode setting register 141 is ON or not (Step 501).
When the mode setting is OFF, the sequencer performs the sequence operation of general read access (Step 504).
When the mode setting is ON, the sequencer starts the sequence operation of write access substituting for read access by the data transfer method of the present invention.
In this case, the sequencer ensures the read data buffer first in the same way as with general read access (Step 502).
Next, the sequencer executes write access in the access format explained with reference to FIG. 2 by the same sequence operation as that of general write access (Step 503). The sequencer waits for the bus connection controller 103 to execute write access by the return address (TA) (Step 505).
When the bus connection controller 103 executes write access by the return address (TA) and the I/O device 104 discriminates it, the sequencer stores data sent from the main memory 102 in the ensured read buffer and ends the read access.
On the other hand, as shown in FIG. 6, the bus connection controller 103 discriminates write access to the request address (QA) in the access format shown in FIG. 2 at Step 503 (Step 601).
In this case, the bus connection controller 103 checks first whether the internal request queue 132 is full or not (Step 602). When the request queue 132 is full, the bus connection controller 103 outputs a retry response (Step 605).
When the request queue 132 is not full, the bus connection controller 103 accepts write access and enqueues the return address (TA) in the request queue 132 (Step 603). The bus connection controller 103 executes read address to the main memory 102 at the address indicated by the read address (DA) by the same sequence operation as general read access.
Upon receipt of data from the main memory (Step 606) by this read access, the bus connection controller 103 dequeues the return address (TA) from the request queue 132 (Step 607) and executes write access to the return address (TA) by the same sequence operation as general write access (Step 608).
By doing this, the present invention can execute DMA transfer by substituting write access for read access in compatibility with a conventional sequencer interface.
Next, characteristics of the present invention will be explained by considering the timing of the data transfer method of the present invention by referring to FIG. 3.
FIG. 3 is a timing chart showing data timing for executing. DMA in comparison of the method by the prior art with the method of the present invention. (a) indicates the data timing by the prior art and (b) indicates the data timing of the present invention. Also in this case, the system bus is a system bus having no split transfer function such as a PCI bus.
In this embodiment, the system bus is of a clock synchronization type and the DMA read access requires 8 clock cycles between output of an address to the system bus and output of data. (C10 to C2 correspond to 8 clocks.)
In this embodiment, the unit of one read access is set at, for example, 4 words. (Data from C10 to C13)
Numeral 301 shown in FIG. 3(a) indicates timing of address and data indicating the DMA read access by the prior art.
In the timing of 301, the system bus is occupied for 13 clock cycles from output of the read address (RA) as an address at C2 to output and end of the data (D) at C13.
On the other hand, as shown in FIG. 3(b), in the data transfer of the present invention, read access equivalent to 301 is substituted by two write accesses of 302 and 303. As explained above, in the write access substituting for read access of the present invention, the request address (QA) is outputted as an address first at 302 and then the read address (RA) and the return address (TA) are outputted as data.
Response data to the write access 302 is transferred as write access 303. In this case, the period from output of the read address (RA) at 302 to data output at 303 is 8 clock cycles.
Therefore, according to the data transfer method of the present invention, the system bus is occupied for 10 clock cycles of 302 and 303. As shown by 304 in FIG. 3(b), another transfer can be executed on the system bus between 302 and 303.
Therefore, when the efficiency of the system bus by the data transfer method of the DMA access by the prior art is compared with that of the DMA access of the present invention, the use efficiency of the system bus of the present invention is higher by about 23% (=3/13).
According to the data transfer method of the present invention, the time occupying the system bus by one access is shorter such as 4 clock cycles at 302 and 6 clock cycles at 303 than 13 clock cycles at 301. Therefore, from a mean point of view by arbitration, there is an advantage that the waiting time for acquiring a bus becomes shorter.
If the I/O device 104 can control a plurality of read data buffers ensured at Step 502 shown in FIG. 5 and the sequence operation explained in FIG. 5 can be reinputted (reentrant), the I/O device 104 can execute a plurality of read accesses in parallel by executing accesses at 302 and 303 shown in FIG. 3 as well as the same accesses in the timing of 304 and 305. By doing this, one I/O device can execute a plurality of read accesses in parallel, so that the use efficiency of the system bus viewed from each I/O device can be increased.
Another embodiment will be explained by referring to FIG. 4.
The first embodiment relates to a method of executing DMA transfer between the main memory and the I/O device. On the other hand, this embodiment relates to a method of executing data transfer between an I/O device and an I/O device.
Firstly, the system constitution of the data transfer system of the second embodiment of the present invention will be explained by referring to FIG. 4.
FIG. 4 is a system block diagram showing the hardware constitution of the data transfer system of the second embodiment of the present invention.
A processor 401 comprises N processors as a multiprocessor. The processor 401 and a main memory 402 are connected to bus connection controllers 403 and 404 via a processor bus 407 and data can be transmitted and received between them.
The bus connection controller 403 is connected to an I/O device 405 via a system bus 408 and the other bus connection controller 404 is connected to an I/O device 406 via a system bus 409.
The I/O devices are modules which are a request source and a request destination for inter-I/O transfer.
There are a plurality of system buses constituting the system of this embodiment as mentioned above and it is assumed that each system bus has no split transfer function such as a PCI bus.
The I/O device 405 has a mode setting register 451, a request address setting register 452, and a return address setting register 453. The other I/O device 406 has a request address setting register 461.
In this embodiment, special operations are performed by these registers in the I/O devices. However, general functions other than them may be the same as those of the prior art.
Although not shown in FIG. 4, the I/O devices 405 and 406 have sequencers for controlling the data transfer operation in the same way as with the prior art. In this embodiment, the system buses 408 and 409 are assigned an exclusive address space and mutual access can be executed only by designation of an address.
The mode setting register 451, the request address setting register 452, and the return address setting register 453 are assigned addresses on the system bus 408, and the request address setting register 461 is assigned an address on the system bus 409, and they can be accessed from the system buss 408 and 409.
As in the first embodiment, the mode setting register 451 is a flag register and it is required that the flag is set to ON when inter-I/O transfer is executed by the data transfer method of the present invention and set to OFF when it is not executed.
Next, the operation of the data transfer system of the present invention will be explained also by referring to FIG. 4.
Firstly, the processor 401 sets a request address in the request address setting register 461 in the I/O device 406 and in the request address setting register 452 in the I/O device 405.
This request address is used to output a request to the I/O device 406 from the I/O device 405.
The processor 401 sets a return address in the return address setting register 453 in the I/O device 405. This return address is the address of the storage location when the I/O device 406 sends data retained by it to the I/O device 405. The processor 401 changes and sets the mode setting register 451 to ON.
The operation of the data transfer system varies with the value of the mode setting register 451 which is set just now.
When the value of the mode setting register 451 is OFF, the data transfer system performs the normal operation. Namely, when the I/O device 405 is instructed to execute inter-I/O transfer read access from the processor 401, the system executes inter-I/O transfer read access in the same way as with the prior art.
Therefore, when the value of the mode setting register 451 is OFF, the I/O device 405 can operate in compatibility with a conventional interface even on a system in which the method of the present invention is not executed.
When the mode setting register 451 is ON, the data transfer system performs the operation of the data transfer method of the present invention.
When the I/O device 405 is instructed to execute inter-I/O transfer read access from the processor 401 in this case, the device executes write access to the request address set in the request address setting register 451 instead of read access.
As an access format at this time, the same one as that explained by referring to FIG. 2 in the first embodiment may be used.
Namely, this is a format that there is the request address (QA) set in the request address setting register 452 in the I/O device 405 as an address first and there are the read address (DA) and the return address (TA) set in the return address setting register 453 as data behind it.
The read address (DA) indicates the address of the data storage location of the I/O device for read access.
When write access in the aforementioned access format is issued via the system bus 408, the bus connection controller 403 informs the other bus connection controller 404 of this data from the processor 407.
The bus connection controller 404 informs the I/O device 406 of this data via the system bus 409.
When the address of the request address (QA) matches with the address stored in the request address setting register 461, the I/O device 406 judges it as "write access substituting for read access" of the present invention and receives data.
The I/O device 406 executes write access to the address data of the requested read data (RD) on the system bus 409 with the header assigned the return address (TA).
This data is sent to the bus connection controller 403 via a route of the bus connection controller 404 and the processor 407.
The bus connection controller 403 becomes a bus master of the system bus 408 and executes write access by sent data.
When the return address (TA) set in the return address setting register 453 in the I/O device 405 is write-accessed via the system bus 408, the I/O device 405 judges it as write access substituting for read access of the present invention and receives the data of the I/O device 406 corresponding to the read address (DA).
By doing this, one read access generated on the system bus 408 is substituted by two write accesses including one write access to each of the I/O device 405 and the I/O device 406. In this case, the two write accesses can be seen as general write access on the system bus 408 and the system bus 409, so that the interface compatibility with general write access can be maintained.
The sequencer in the I/O device 405 just performs an operation of outputting the read address (DA) and receiving data corresponding to it. Therefore, although read access to the system bus 408 is issued in the general procedure, it is desirable to just convert it to write access of the method of the present invention. Therefore, to realize a function other than it, it is desirable to just allow the sequencer to operate in the same way as with the prior art.
In the aforementioned inter-I/O transfer operation, the bus connection controllers 403 and 404 perform only the same operation as that of the prior art. However, also the bus connection controller for performing the DMA operation of the present invention explained in the first embodiment can be applied as this bus connection controller.
It is obvious that in the I/O device 406, a queue means which is the same as the request queue 132 in the bus connection controller 103 shown in FIG. 1 in the first embodiment can be installed and an I/O device having a function which can serve both as a request source and a request destination of inter-I/O transfer can be structured.
According to the present invention, when DMA or inter-I/O transfer of an I/O device having no split transfer function such as a PCI bus is executed, a means for eliminating a possibility of occurrence of a deadlock, maintaining the compatibility of the bus specification, and improving the data transfer efficiency can be provided.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3997896 *Jun 30, 1975Dec 14, 1976Honeywell Information Systems, Inc.Data processing system providing split bus cycle operationUS5191649 *Dec 21, 1990Mar 2, 1993Intel CorporationMultiprocessor computer system with data bus and ordered and out-of-order split data transactionsUS5353415 *Oct 2, 1992Oct 4, 1994Compaq Computer CorporationMethod and apparatus for concurrency of bus operationsUS5533204 *Apr 18, 1994Jul 2, 1996Compaq Computer CorporationSplit transaction protocol for the peripheral component interconnect busUS5535340 *May 20, 1994Jul 9, 1996Intel CorporationMethod and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridgeUS5544331 *Sep 30, 1993Aug 6, 1996Silicon Graphics, Inc.System and method for generating a read-modify-write operationJPH05173936A * Title not availableJPH06131295A * Title not available* Cited by examinerNon-Patent CitationsReference1 *Nikkei Electronics 1994.6.6 (No. 609) pp. 67 97.2Nikkei Electronics 1994.6.6 (No. 609) pp. 67-97.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5953538 *Nov 12, 1996Sep 14, 1999Digital Equipment CorporationMethod and apparatus providing DMA transfers between devices coupled to different host bus bridgesUS6202112 *Dec 3, 1998Mar 13, 2001Intel CorporationArbitration methods to avoid deadlock and livelock when performing transactions across a bridgeUS6988160 *Feb 12, 2001Jan 17, 2006P-Cube Ltd.Method and apparatus for efficient messaging between memories across a PCI busUS8386668Mar 23, 2012Feb 26, 2013Intel CorporationQuerying a device for informationUS8396996Mar 23, 2012Mar 12, 2013Intel CorporationQuerying a device for informationUS20020112105 *Feb 12, 2001Aug 15, 2002Mordechai DanielMethod and apparatus for efficient messaging between memories across a PCI busUS20090228612 *Mar 6, 2008Sep 10, 2009Barinder Singh RaiFlexible Bus Interface and Method for Operating the Same* Cited by examinerClassifications U.S. Classification710/305International ClassificationG06F13/40, G06F13/36, G06F13/42, G06F13/12Cooperative ClassificationG06F13/4036, G06F13/126, G06F13/4027, G06F13/423European ClassificationG06F13/40D5A2, G06F13/12P2, G06F13/40D5, G06F13/42C2SLegal EventsDateCodeEventDescriptionMay 15, 1996ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OKAZAWA, KOICHI;OSAKA, HIDEKI;SAITOU, KENICHI;REEL/FRAME:008020/0761Effective date: 19960423Nov 15, 2001FPAYFee paymentYear of fee payment: 4Nov 11, 2005FPAYFee paymentYear of fee payment: 8Dec 21, 2009REMIMaintenance fee reminder mailedMay 19, 2010LAPSLapse for failure to pay maintenance feesJul 6, 2010FPExpired due to failure to pay maintenance feeEffective date: 20100519RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text:
The Adventures of Pinocchio by Collodi, C., Illustrated by Maud & Miska Petersham: Garden City, 1932 - Reader's Corner, Inc.
Collodi, C., Illustrated by Maud & Miska Petersham
Published by Garden City, 1932, 1932
Cloth. Very Good/No Jacket. 8vo - over 7¾" - 9¾" tall. Pasted color plate on front cover. Ink signature on front endpaper. Marks where bookplate was removed. Bookseller Inventory # 002910
Publisher: Garden City, 1932

value: This website is an e-commerce global online marketplace with seven websites that offer books, fine art, and collectables from sellers in over 50 countries. Launched in 1996, it specialises in used, rare and out-of-print books.


text:
Shimano Deore XT BR-M732 Cantilever Brake Set Vintage Mountain Bike
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MPN: EPDM8020
by jmboyz Jun 12, 2019
Great pedals for XC MTB
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text:
Patent US4212460 - Hollow water-filled game toy - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA hollow body is provided having two complementary parts releasably joined about interfitting rim portions. When the parts are joined, the hollow body may be compressed to partially deform a portion of the rim structure into an opening thereby allowing the filling of water into the body interior. After...http://www.google.com/patents/US4212460?utm_source=gb-gplus-sharePatent US4212460 - Hollow water-filled game toyAdvanced Patent SearchPublication numberUS4212460 APublication typeGrantApplication numberUS 05/928,382Publication dateJul 15, 1980Filing dateJul 27, 1978Priority dateJul 27, 1978Publication number05928382, 928382, US 4212460 A, US 4212460A, US-A-4212460, US4212460 A, US4212460AInventorsDonald J. KraftOriginal AssigneeKraft Donald JExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (45), Classifications (14) External Links: USPTO, USPTO Assignment, EspacenetHollow water-filled game toy
US 4212460 AAbstract
A hollow body is provided having two complementary parts releasably joined about interfitting rim portions. When the parts are joined, the hollow body may be compressed to partially deform a portion of the rim structure into an opening thereby allowing the filling of water into the body interior. After deformation the parts resume their original shape. An effective hermetic seal to retain the water within the interior is formed by squeezing the body and purging air through vents in the rim portions. The water-filled body may then be thrown against a stationary object whereby the force of impact will release the seal and allow the water to become suddenly released causing a splashing action. The complementary hollow parts may be subsequently rejoined and refilled with water to repeat the throwing and splashing action.
1. A hollow game toy comprising:two resilient manually deformable complementary parts each having matching rim structures which are engaged to form a substantially hermetically sealed hollow body, said rim structure including at least one evacuation vent for purging fluid from the body interior during deformation of the body. 2. The toy of claim 1 wherein said rim structure comprises an outer offset lip about the rim of one of said parts and an inner offset lip about the rim of the other of said parts forming a lapped joint.
3. The toy of claim 2 wherein said evacuation vent is located on the inner lip of said joint.
4. The toy of claim 3 wherein said evacuation vent comprises a plurality of indentations extending across the top edge of said inner lip.
5. The toy of claim 1 wherein said rim structure comprises a groove formed in and concentrically around the top edge of one of said parts and a corresponding projection extending from and concentrically around the top edge of the other of said parts forming a tongue and groove joint.
6. The toy of claim 2 or 5 wherein said evacuation vent comprises a plurality of channels extending across a major portion of said joint beginning with an opening at the interior surface of said body.
7. The toy of claim 6 wherein the approximate overall shape of said hollow body may be selected from the group consisting of sphere, ovoid, ellipse and cylinder.
The present invention relates to water-filled game toys and, more particularly, to a resealable two-part hollow body filled with water.
Various ball games are known in the prior art which allow for a splitting into separate parts upon impact. Such devices may have a latching mechanism contained within the ball halves which, when impacted, will unlatch allowing the halves to split apart. Such a split ball device is shown and described in U.S. Pat. No. 3,687,452.
Another ball game which is constructed of multiple interconnecting parts is shown in U.S. Pat. No. 3,740,036. The ball disclosed in this patent provides that the assembled parts of the ball will progressively disintegrate when thrown or rolled in a particular manner due to the particular geometrical configuration of the interfitting parts.
Insofar as water-filled toys are concerned, U.S. Pat. No. 2,645,486 discloses a transparent ball partially filled with water containing a floating card. Each ball half is glued together and the card is permanently sealed therein. Probably the best known prior art, however, is the rubber balloon filled with water. Such balloons are typically thrown and the force of water upon impact ruptures the balloon creating a vivid splashing action. The disadvantages of such balloons is their cumbersome handling and throwing characteristics and their inability to be reused.
It will be appreciated that the present invention provides complementary resilient hollow parts which have matching rim structures which are self-centering and adapted to form a substantially water-tight seal. Due to the resilience of the hollow parts, the rim structure may be deformed to create an opening therein to allow for the filling of water. Upon allowing the parts to return to their original shape, the rim structure becomes completely sealed to form a water-filled hollow body which can be thrown against another object. Upon impact the force of the throw will cause the parts to open and allow the water to suddenly escape in a striking display.
FIG. 1 is a view of a spherical embodiment of the assembled hollow game toy of the present invention.
FIG. 2 is an exploded perspective view showing two complementary halves of the toy shown in FIG. 1.
FIG. 3 illustrates the manipulation of the complementary halves of FIG. 2 to open a portion of the rim structure allowing for the filling of the toy interior with water.
FIG. 4 illustrates the throwing, impact and splashing of water upon the complementary halves of FIG. 2 breaking open during impact.
FIG. 5 is a cross-section taken along lines 5--5 of FIG. 1.
FIG. 7 is an enlarged fragmentary view taken along line 7 of FIG. 5.
FIG. 9 is an enlarged fragmentary cross-section of a modified lap joint.
FIG. 10 is an enlarged fragmentary cross-section illustrating a further modified lap joint.
FIG. 11 is a fragmentary enlarged cross-section showing a further modified rim structure showing a tongue and groove joint.
Referring now to the drawings and, more particularly, to FIGS. 1 and 2 thereof, a spherical hollow game toy or ball is shown generally by reference numeral 10. The ball is formed by two complementary hollow parts shown by reference numerals 12 and 14. Each of the complementary hollow parts have matching rim structure shown as 12' and 14'. In the embodiment shown in FIGS. 2-7, a beveled lap joint configuration is depicted. The rim structure 14a presents an annular flat shoulder portion 16 extending inwardly from the ball exterior surface to an inwardly inclined wall portion 18. The inclined wall merges into an annular flat top edge portion 20 which extends to the interior surface of the ball.
The hollow part 12 is provided with corresponding surfaces complementary to rim 14a comprising a flat annular shoulder portion 16a having a width about equal to the width of shoulder portion 16 of part 14. The shoulder portion extends into an inwardly inclined wall portion 18a which merges into an inner flat annular top edge 20a. It will be understood that the widths of top edges 20 and 20a are about equal and the angle of inclination of wall portion 18 and wall portion 18a are complementary angles such that contact is made substantially throughout the overall rim structure. In this manner a seal is formed that will retain water within the ball interior.
The rim structure forming the inner lip portion 34 is provided with at least one or more evacuation vents to allow for the purging of air from the interior of the game toy body when enclosed. In the embodiments shown in FIGS. 2-8, the vents comprise a plurality of spaced-apart indentations 36 in top edge 20. The manner of operating the evacuation vents will be described in more detail hereinafter.
It wil be appreciated that since the vents 36 are for air form the interior of the hollow body, they must have communication with the ball interior. In all the embodients shown, the vents take the form of transversely extending channels formed across at least a major portion of the rim structure having an open end 38 at the body interior surface. Of course, the vent should not extend across the entire rim structure because such would obviate an effective hermetic seal. Generally, it is convenient for the outer lip structure shown by reference numeral 44 to be free of any grooves or the like.
Alternative lap joint rim structures are shown in FIGS. 9 and 10. In particular, FIG. 9 shows matching perpendicular wall portions 50 and 50a interconnecting upper and lower flat annular shoulder portions 52, 52a and 54 and 54a, which interconnect the body shell interior and exterior, respectively. At least one evacuation vent channel 56 is shown in phantom in part 12 extending from interior opening 58 to the junction of wall 50 and shoulder 54. In this manner the complementary annular shoulder portions 54 and 54a will remain continuous to form an effective seal. FIG. 10 illustrates arcuate matching wall portions 60 and 60a which terminate at outer annular flat sealing surfaces 64, 64a, respectively. The arcuate wall 60 is provided at least one channel 66 shown in phantom extending transversely from body interior opening 68 to annular sealing surface 64.
Another alternative rim structure is the tongue and groove joint shown in FIG. 11. In this joint a groove 70 is formed in and around a top edge of the rim structure of part 12. A corresponding annular projection is formed to extend concentrically from around the rim of part 14. When engaged, the tongue and groove joint provides additional surface area for effecting an especially strong seal in the case where the hollow body side walls are thick but soft or limp making an effective seal more difficult. As to the case of the previous joints, a transversely extending channel 74 is formed across the major portion of the rim structure having an opening 76 at the interior surface of the hollow body. In this way, an annular seal will still be formed at the flat annular mating surfaces 78, 78a formed adjacent the body exterior surface.
To describe the operation of the hollow game toy of the invention, reference will be made to north and south poles of the spherical embodiment shown in FIG. 1. The north and south poles are shown by reference letters N and S, respectively, and are located where the central axis perpendicular to the plane formed by the rim structure intersects the sphere. As best shown in FIGS. 2 and 3, the complementary hollow parts will be frictionally engaged about their respective rim structures 12' and 14' forming a substantially hermetically sealed hollow body. The body is subsequently manually squeezed or compressed with mild force furthermost from the circumferential seal line at opposing sides generally proximate points N and S. When the hollow parts are so compressed, a portion of the rim structure of each hollow part will be puckered outwardly creating a slight opening shown by reference numeral 80. While maintaining such an opening, tap water 82 or other flowable material such as powder or the like may be directed into the interior of the hollow body until the volume thereof is substantially full, i.e., until water overflows the opening 80. When such occurs, the opposing manual pressure is released thereby allowing the deformed rim structure to return to its original shape to form a complete reseal about the engaged rim structure. To further enhance an effective seal, it is appropriate to again depress the areas proximate points N and S to a point where all remaining air and a slight amount of water will be expelled through the aformentioned evacuation vents. Upon release of the compressive pressure, a seal will be immediately reformed due to the resilience of the hollow parts. It will be noted, however, that upon release of the compressive pressure, a vacuum will be formed in the body interior due to the inability of ambient air to refill the volume of water previously expelled. In this manner a more effective seal will be created caused by the ambient atmospheric pressure operating against the external body surfaces and the outer lip structure forcing it in an increasingly tight manner against the matching surfaces of the various inner lip surfaces.
After completing the vacuum forming step, the ball is now ready to be thrown against an object. Upon striking the object, as shown in FIG. 4, the force of impact will break the seal about the rim structure and allow the water to splash in an ostentatious manner creating excitement and a vivid impression in a youthful user's mind. The resilient hollow parts may be retrieved and reassembled for refilling of water and the procedure may be repeated again and again.
It will be noted that alternative structures may be used in place of the spherical embodiment shown in the drawings. For example, ellipsoidal or cylindrical bodies may be utilized depicting toy grenades, toy dynamite, simulated bombs, shell casings, torpedoes. Also various types of athletic balls may be simulated such as baseballs, footballs, tennis balls or the like. In this regard, note that the exterior surfaces may be imprinted, embossed and/or colored to simulate such items.
The hollow body may be constructed of several types of plastic materials such as rubber, organosols, plastisols, vinyl dispersions or thermoplastic molded materials. It is essential that such materials have sufficient resilience to allow the ready deformation of the hollow body parts to create an opening about the rim structure for the filling of fluid materials while having sufficient capability to recover the original shape and retain such during the force of a throw. It will also be appreciated that the hollow parts will have sufficient thickness to enable the formation of an effective sealing area about the rim structure. It is expected that the greater the flexibility of the body material, the greater the body wall thickness that will be needed to effect a proper seal. Rubber-like materials having durometer readings of 25-65 have been effective in carrying out the objectives of the invention.
While the invention has been described with respect to preferred embodiments, it will be apparent to those skilled in the art that other modifications may be made without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrative embodiments hereinabove described but only by the scope of the appended claims.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS2091684 *Apr 17, 1936Aug 31, 1937Mabee Daniel CTable tennis ballUS2645486 *Apr 24, 1951Jul 14, 1953Joseph R MonahanCard ballUS2939246 *Feb 24, 1958Jun 7, 1960Glos Edmond AToy ballUS3687452 *Dec 2, 1970Aug 29, 1972Thompson Rayford LGame ballUS3740036 *Mar 16, 1971Jun 19, 1973Ames AGame ball* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4684137 *Sep 6, 1985Aug 4, 1987Armer Jr Leon NSimulated war game weaponUS4697807 *Apr 16, 1986Oct 6, 1987Boundy Francis JNovelty golf ballUS4991847 *Nov 13, 1989Feb 12, 1991Elliot RudellTimed water release toyUS5066018 *Oct 16, 1990Nov 19, 1991Hinton Dean SDeformable sphere with a suction cup exteriorUS5150906 *Mar 10, 1989Sep 29, 1992Lisco, Inc.Multi-piece golf balls and methods of manufactureUS5181724 *Oct 28, 1991Jan 26, 1993Vittorio SpadoniWing shooting targetUS5213538 *Jan 2, 1992May 25, 1993Mattel, Inc.Pop-action bouncing dollUS5240450 *Feb 27, 1992Aug 31, 1993Graham David BToy hand grenade apparatusUS5277641 *Dec 28, 1992Jan 11, 1994Gable Derek JSpinning flying toy with fluid releaseUS5290041 *Feb 1, 1993Mar 1, 1994Paradigm International, Inc.Lawn game using hand-thrown projectilesUS5335907 *Aug 9, 1991Aug 9, 1994Donald SpectorVariable weight playballUS5380002 *Dec 11, 1992Jan 10, 1995Spector; DonaldVariable-weight play piecesUS5462273 *Jul 28, 1994Oct 31, 1995Spector; DonaldVariable weight playballUS5529525 *Oct 5, 1994Jun 25, 1996Deal; Jeffry T.Water bomb - mounted water gunUS5531626 *Jul 8, 1994Jul 2, 1996Deal; Jeffry T.Toy water bomb deviceUS5531627 *Feb 15, 1995Jul 2, 1996Deal; Jeffry T.Cartridge-type water bomb water gun conversion deviceUS5538456 *Aug 9, 1994Jul 23, 1996Lcd International, L.L.C.Toy water bombUS5538457 *Oct 5, 1994Jul 23, 1996Deal; Jeffry T.Water gun with turreted multiple water bomb launchersUS5553570 *Nov 14, 1994Sep 10, 1996Vannatter, Iii; Charlie H.Disc-shaped animal retrieval toy having treat containerUS5758800 *Jun 28, 1996Jun 2, 1998D'andrade; Bruce M.Bladder for water gunUS5799616 *Sep 9, 1996Sep 1, 1998Charlie Van NatterAnimal interaction methodUS5799827 *Jun 28, 1996Sep 1, 1998D'andrade; Bruce M.Bladder water gunUS5810602 *Feb 20, 1997Sep 22, 1998Menelly; Daniel JamesGravity teaching aidUS5906295 *Mar 31, 1998May 25, 1999D'andrade; Bruce M.Bladder for water gunUS5975983 *Jun 12, 1998Nov 2, 1999Panec; Donald J.Reusable water-containing toyUS6012609 *Feb 8, 1999Jan 11, 2000Larami LimitedBladder water gunUS6073588 *Aug 31, 1998Jun 13, 2000Mcclung, Iii; Guy L.Throwing plate system and methodUS6193107Nov 23, 1999Feb 27, 2001Larami LimitedBladder water gunUS6223658Nov 6, 1998May 1, 2001Steven P. RosaNon-lethal weapon firing a frangible, weighted paint ballUS6257448Jan 5, 1999Jul 10, 2001D'andrade Bruce M.Backpack externally chargeable bladder gun assemblyUS6296252Apr 20, 2000Oct 2, 2001Frank HubkaWater game systems and methodsUS6471564 *Dec 6, 2001Oct 29, 2002Thomas J. ColemanSplattle paddleUS6532947Nov 3, 2000Mar 18, 2003Steven P. RosaNon-lethal weapon firing and frangible, weighted paint ballUS6585555Oct 18, 2001Jul 1, 2003Prime Time Toys, Ltd.Temperature sensitive color changing water toyUS6699097Feb 9, 2001Mar 2, 2004Elliot RudellToys with timer-activated controllable operation timeUS6939193Jul 22, 2004Sep 6, 2005Mcdowell William C.Aquatic game deviceUS7008679 *Dec 14, 2001Mar 7, 2006Wayne CohenShell article constructionUS7444938 *Nov 1, 2005Nov 4, 2008Kee Action Sports I LlcPaintball grenadeUS7481727 *Apr 2, 2007Jan 27, 2009Francis See Chong ChiaWater-release toyUS20110223826 *Mar 12, 2010Sep 15, 2011Gibson Edward GUnderwater play ballCN101954194BJul 13, 2009Sep 12, 2012张帆Emotion abreaction and expression instrumentWO1990007961A1 *Dec 18, 1989Jul 26, 1990Elliot RudellGame and ball with water-releasing deviceWO1993012852A1 *Aug 10, 1992Jul 8, 1993Mattel IncPop-action bouncing dollWO1998000214A1Jun 27, 1997Jan 8, 1998Andrade Bruce M DBladder water gun, improved bladder and nozzleWO1998041290A2 *Mar 13, 1998Sep 24, 1998Cadera TomThrowing object* Cited by examinerClassifications U.S. Classification473/577, 446/267, 428/11, 273/127.00A, 273/317, 446/4, 446/125International ClassificationA63B65/00Cooperative ClassificationA63H23/10, A63H33/18, A63B65/00European ClassificationA63B65/00, A63H23/10, A63H33/18RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text:
Moon Lightporno | eBay Please enable JavaScript Our new search experience requires JavaScript to be enabled. Please enable JavaScript on your browser, then try again.
Skip to main contenteBayShop by categoryEnter your search keywordAll CategoriesAntiquesArtBabyBooksBusiness & IndustrialCameras & PhotoCell Phones & AccessoriesClothing, Shoes & AccessoriesCoins & Paper MoneyCollectiblesComputers/Tablets & NetworkingConsumer ElectronicsCraftsDolls & BearsDVDs & MovieseBay MotorsEntertainment MemorabiliaGift Cards & CouponsHealth & BeautyHome & GardenJewelry & WatchesMusicMusical Instruments & GearPet SuppliesPottery & GlassReal EstateSpecialty ServicesSporting GoodsSports Mem, Cards & Fan ShopStampsTickets & ExperiencesToys & HobbiesTravelVideo Games & ConsolesEverything ElseAdvanced or register':' style="margin-right:3px">Hi -User-!'.replace(/-User-/,escape(a)))+"")}catch(b){document.write("")}})();Hi (Sign in to bid or buy)Daily DealsGift CardsSellHelp & ContactMy eBayExpand My eBaySummaryBids/OffersWatch listWish listAll listsPurchase historySellingMy CollectionsFollowed searchesMessagesNotification Refine your search for Moon Lightporno
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1978 Press Photo Full moon lights up downtown Portland - oro14781
Italy Venezia di Notte Ca d'Oro Moonlight
Italia Venezia di notte - Ca' d'Oro at night, moonlight, notte 1955


text: $29.99 Was $44.99 Save $15.00 ONN 7" Portable DVD Player with Matching Headphones and Bag 3.5 stars (8) ratings Free shipping on orders over $50 Free store pickup 1 2 3 4 5 6 25 Next Showing 40 of 107,258 results Departments TV Accessories All TVs Shop TVs by Type Media Players & Recorders DVD & Blu-ray Players 4K Ultra HDTVs Portable DVD Players Cut the Cable: Stream TV Shipping & Pickup Show all Ship to Home FREE Pickup FREE Pickup Today Special Deliveries Premium Delivery Screen Size 20" & Smaller 21" - 29" 30" - 39" 40" - 49" 50" - 59" 60" - 69" 70" & Larger Brand Samsung VIZIO Sony LG RCA Sceptre Panasonic Sanyo Philips TCL Hisense Element Sharp Haier ProScan Roku Apple @.com Hitachi V7 See more brands Price $ to $ Go $0 - $100 $100 - $150 $150 - $200 $200 - $300 $300 - $350 $350 - $400 $400 - $450 $450 - $500 $500 - $700 $700+ See more prices Special Offers New Special Buy Rollback Clearance Reduced Price As Advertised Price at Checkout Only at Walmart Price Shown at Cart See more special offers Customer Rating 4.0 stars & Up 3.0 stars & Up 2.0 stars & Up 1.0 stars & Up Retailer Walmart.com UnbeatableSale Buy Smart Tasharina Corp Zoro Beach Audio Inc bargainstation BuyVPC pcRUSH Gomadic Corp. antonline Mega Retail Store OutletPC My Goods SIM Supply Inc BidDeal Monoprice Inc HPP Enterprises Unlimited Cellular ShopLadder See more retailers Save Big Bundle Store for Good Sustainability Women-Owned Businesses Popular in TV & Video TV Antenna Amplifiers VIZIO 4K TV Wall Mounts for 32" TV Samsung TV TV Brackets Antennas VIZIO Smart TV Coax Cables Compute- app-11031821-7-59262972, DC- prod-dal3, ENV- prod-a, Ver- 44.0.0, SHA- 4ccde6630b54173e13bf9646401e57ff2c4cccd4, Log- 45b2098c-506c-1561f725400000 Site Information Be the first to save! Email Address Sign up Privacy policy Stay connected Mobile apps Help Feedback MoneyCenter Privacy & security CA privacy rights Terms of use Financial services Walmart MoneyCenter Walmart Credit Card Apply now Manage card account Product Care Plans Walmart Pay Get to know us About Walmart.com Corporate Suppliers Marketplace Careers @Walmartlabs Walmart.com Terms of use About our ads Affiliate program CA privacy rights Privacy & security Customer service Returns policy Product recalls Int’l customers Tax exempt program Contact us Feedback Store pickup In the spotlight Expand Baby Cribs Strollers Diapers Baby feeding Car seats Expand Electronics Cut the Cable Computers TVs iPads & tablets Expand Fitness Exercise machines Vitamins Ellipticals Treadmills Fitbit Expand Keep cool Air conditioners Fans Swimming pools Pool toys Expand International sites Argentina Brazil Canada Chile China Japan Mexico United Kingdom © Walmart Stores, Inc. To ensure we’re able to help you as best we can, please include your reference number: Ref:

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text:
Great location - Review of The Granville Hotel, Brighton, England - TripAdvisor
Great location - The Granville Hotel
Room was light & airy, with a sea view.
Great location for accessing central Brighton.
Would be nice to have a proper shower, rather than a hand held one, instead of the jacuzzi bath.
Could do with a little be of TLC, and updating.
Ask John S about The Granville Hotel
All reviews west pier jacuzzi bath balcony room noel coward brighton rock sea view four poster bed sea front themed rooms quirky hotel brighton seafront comfy bed breakfast was excellent a bit tired car park regency square good nights sleep
Just had a weekend break at the Granville. On Arrival we were warmly welcomed and given our keys. We stayed in the Noel coward room which was very spacious with an equally spacious bathroom. The room was clean with lovely Art Deco furniture. The spa bath was amazing yes some areas of the hotel
Decoration is a bit tired but it didn’t worry us. Breakfast down stairs at Smokey’s was great. The hotel is a 2 minute walk from the i360 which is one of the things we went for and about 10 minutes walk from the lanes. Would definitely recommend and hope to go back in the near future.
Ask Nicola S about The Granville Hotel
We picked the hotel because of price, availability and location and it did the job. The check in was easy, service was friendly, the room (Beardsley) was excellent and, once it stopped raining, it was very easy to walk to where we needed to be...happy to recommend
Ask Broncos010770 about The Granville Hotel
I'm a realist when it comes to hotels , and this old seafront hotel is definitely worth a look everything clean , comfortable bed, awesome breakfast, will stay there again. It's a golden oldie, friendly staff , clean , great bfast what more can you ask for !
Ask Inmycompfortzone about The Granville Hotel
1 Thank Inmycompfortzone
Great location, good views, crippling shower!
The hotel could do with a decorate. The lift, of which it does need, works when it wants to or they are cutting back on the power bill! Breakfast is fab and plentiful but who ever thought that putting in jacuzzi baths with a hand held shower hose must need their head tested. I have doddering knees and trying to stand, sit, lather my head, wash out soap all with one hand is not easy. When asked why was there not a wall holder for the shower head, we were advised one could not be fitted as the water would go over the side! Well that’s funny as we have one set up like that at home and with a have curved screen the problem disappears! The only room with a walk in shower is on the ground floor.
Please please do something about this issue as the hotel has 2 rooms to the front with balcony’s which would be great to watch Pride from. Car parking is just 2 mins away and for Brighton isn’t that bad. Not far from the gay village or lanes either. I have stayed in better and cheaper but this place could be much better without too much effort. They keep their loo rolls in reception in a filing cupboard too!!!
Ask Kris B about The Granville Hotel
First time to stay here and was not disappointed, nice friendly staff, room was really nice clean, airy and not too cluttered, huge bathroom with a spa bath and funky shower but in a good way, would recommend and will use again, Great Breakfast too. Many thanks
Ask rj_watters about The Granville Hotel

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text: their language. one of their first actions was to stop written english on the streets. don cartwrights a cultural geographer who studies langge use in quebec. cartwright: as a geographer, signs of the landscape-- the streetscape-- are vital.ds to take back the streetscape, and consequently in the '70s, they passed legislation which de unilengl he placeishethe siaw which meant that only french-language signs could appear on the streetscape. narrator: because of these laws, many english-speaking companies, like this one, sun life, began to leave in droves. overall, nearly 20% of the english population left quebec in the early '70s and '80s. today, this law has been relaxed, and bilingual signs are permitted. but the french language now dominates this landscape. even old landmar like the queeelizabethotel and windsor statio now show their compliance with these laws. the québécois have succeeded in their battle with the english-speaking minority. but it is quebec's rapidly growing immigrant population that currently presents an even greater challenge to the québécois. in this immigration office, Search Results 0 to 1 of about 2

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text:
Words containing idostere | Words that contain idostere
https://www.thefreedictionary.com/words-containing-idostere
Dictionary, Encyclopedia and Thesaurus - The Free Dictionary 10,944,355,306 visitors served
Found 1 words containing idostere. Browse our Scrabble Word Finder, Words With Friends cheat dictionary, and WordHub word solver to find words that contain idostere. Or use our Unscramble word solver to find your best possible play!
13 letter words containing idostereSee also
13 letter words containing idostere

value: This website is an American online dictionary and encyclopedia that aggregates information from various sources.


text:
Lawrence, Iain 1955- [WorldCat.org]
65 works in 483 publications in 13 languages and 31,710 library holdings
Fiction Juvenile works History Adventure stories Action and adventure fiction Detective and mystery fiction Young adult works Children's audiobooks Sea stories Anecdotes
PS3612.A9, FIC
Publications about Iain Lawrence
Publications by Iain Lawrence
0 Publications by Iain Lawrence
3 Publications by Iain Lawrence
1 Publication about Iain Lawrence
1 Publication by Iain Lawrence
14 Publications by Iain Lawrence
23 Publications by Iain Lawrence
41 Publications by Iain Lawrence
40 Publications by Iain Lawrence
36 Publications by Iain Lawrence
29 Publications by Iain Lawrence
25 Publications by Iain Lawrence
24 Publications by Iain Lawrence
27 Publications by Iain Lawrence
13 Publications by Iain Lawrence
11 Publications by Iain Lawrence
38 Publications by Iain Lawrence
16 Publications by Iain Lawrence
2 Publications by Iain Lawrence
4 Publications by Iain Lawrence
18 Publications by Iain Lawrence
8 Publications by Iain Lawrence
Most widely held works about Iain Lawrence
Sea stories of the Inside Passage : in the wake of the Nid by Iain Lawrence( Book )
Most widely held works by Iain Lawrence
The convicts by Iain Lawrence( Book )
23 editions published between 2005 and 2014 in 3 languages and held by 2,970 libraries worldwide
The castaways by Iain Lawrence( Book )
12 editions published between 2007 and 2014 in English and German and held by 2,943 libraries worldwide
The cannibals by Iain Lawrence( Book )
12 editions published between 2005 and 2014 in English and German and held by 2,724 libraries worldwide
The wreckers by Iain Lawrence( Book )
46 editions published between 1998 and 2013 in 11 languages and held by 2,514 libraries worldwide
B for Buster by Iain Lawrence( Book )
8 editions published between 2004 and 2006 in English and held by 2,228 libraries worldwide
The séance by Iain Lawrence( Book )
3 editions published in 2008 in English and held by 2,079 libraries worldwide
In 1926, magician Harry Houdini arrives in the city to perform magic and to expose fraudulent mediums but thirteen-year-old Scooter King, who works for his mother making her séances seem real, needs Houdini's help to solve a murder
The smugglers by Iain Lawrence( Book )
39 editions published between 1999 and 2009 in 11 languages and held by 1,583 libraries worldwide
Lord of the Nutcracker men by Iain Lawrence( Book )
26 editions published between 2001 and 2014 in 5 languages and held by 1,553 libraries worldwide
Ghost boy by Iain Lawrence( Book )
25 editions published between 2000 and 2014 in 4 languages and held by 1,487 libraries worldwide
The buccaneers by Iain Lawrence( Book )
35 editions published between 2000 and 2009 in 9 languages and held by 1,239 libraries worldwide
The winter pony by Iain Lawrence( Book )
9 editions published between 2011 and 2013 in English and held by 1,099 libraries worldwide
The lightkeeper's daughter by Iain Lawrence( Book )
17 editions published between 2002 and 2017 in 3 languages and held by 1,041 libraries worldwide
The giant-slayer by Iain Lawrence( Book )
6 editions published between 2009 and 2012 in English and held by 1,034 libraries worldwide
The skeleton tree by Iain Lawrence( Book )
12 editions published between 2016 and 2017 in English and held by 943 libraries worldwide
The convicts by Iain Lawrence( file )
15 editions published between 2005 and 2011 in English and held by 669 libraries worldwide
11 editions published between 2006 and 2009 in English and held by 644 libraries worldwide
The buccaneers by Iain Lawrence( file )
14 editions published between 2002 and 2014 in English and held by 632 libraries worldwide
The séance by Iain Lawrence( file )
15 editions published between 2008 and 2014 in English and held by 610 libraries worldwide
The castaways by Iain Lawrence( file )
13 editions published between 2007 and 2014 in English and held by 589 libraries worldwide
Ghost boy by Iain Lawrence( file )
12 editions published between 2001 and 2011 in English and held by 547 libraries worldwide
Unhappy in a home seemingly devoid of love, a fourteen-year-old albino boy who thinks of himself as Harold the Ghost runs away to join the circus, where he works with the elephants and searches for a sense of who he is. Some strong language
Audience level: 0.07 (from 0.00 for The convic ... to 0.32 for Something ...)
Wikipedia Iain Lawrence
Adventure stories Alaska Albinos and albinism Antarctica Antarctica--South Pole British Antarctic ("Terra Nova") Expedition British Columbia Brothers Brothers and sisters Caribbean Area Circus Discoveries in geography Elephants England England--London Fate and fatalism Fathers and daughters Fathers and sons France Houdini, Harry, Imagination Islands Lighthouse keepers Magicians Medical fiction Military operations, Aerial--Canadian Murder Ocean travel Pacific Ocean--Islands of the Pacific Parent and child People with disabilities Pirates Poliomyelitis Prisoners Resourcefulness Runaway teenagers Seafaring life Self-acceptance Ships Shipwrecks Slave trade Smuggling Spiritualists Storytelling Survival Teenage mothers West Indies Wilderness areas World War (1914-1918) World War (1939-1945)
Iain Lawrence Canadees auteur van jeugdliteratuur
Iain Lawrence Canadian children's writer
Iain Lawrence escritor de literatura infantil canadiense
Lawrence, Iain Raymond Norman 1955-
ローレンス, イアン

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text:
Certified 2.40cttw Turquoise 0.30cttw Diamond 14KT Yellow Gold Ring | eBay
14KT YELLOW GOLD 2.40CTTW GREEN TOURMALINE & DIAMOND RING SIZE 6 (14R 160-10074)
Details about Certified 2.40cttw Turquoise 0.30cttw Diamond 14KT Yellow Gold Ring
Certified 2.40cttw Turquoise 0.30cttw Diamond 14KT Yellow Gold Ring
253892512333
Total Carat Weight: 2.40cttw
Main Stone: Turquoise Centerstone Shape: Oval
Sizable: Yes Diamond: 0.30cttw
Country of Origin: Iranian
Ring Size: 7 (Sizeable) Centerstone: Turquoise
Total Carat Weight (TCW): 2.40cttw Main Stone Color: Aqua
Turquoise Yellow Gold 6 Ring Fine Rings,
Turquoise Yellow Gold 6.5 Ring Fine Rings,
Turquoise Yellow Gold Fine Rings 5.5 Ring,
Turquoise Yellow Gold Fine Rings 7.25 Ring


text:
Live Today by Derrick Hodge | 5099968289225 | CD | Barnes & Noble
Derrick HodgeDerrick Hodge
Bassist and composer Derrick Hodge has spent much of his life absorbing, studying, and playing music: from gospel and classical to hip-hop, Philly, and neo-soul; from post-bop and modern jazz, to cinema music. Live Today, his debut for Blue Note, reflects the sum total of his professional experience -- working with Mulgrew Miller
Live Today available in
Bassist and composer Derrick Hodge has spent much of his life absorbing, studying, and playing music: from gospel and classical to hip-hop, Philly, and neo-soul; from post-bop and modern jazz, to cinema music. Live Today, his debut for Blue Note, reflects the sum total of his professional experience -- working with Mulgrew Miller, Terrence Blanchard, Stefon Harris, Common, Jill Scott, Q-Tip, Maxwell, and the Robert Glasper Experiment, composing film scores, etc. -- that has resulted in his rarified musical vision. Hodge's self-produced album is a sprawling, hour-long set, that displays a mercurial, adventurous aesthetic, which is as disciplined as it is fluid and welcoming. Live Today is polished, not slick; it frames and colors a music that is purposely raw and kinetic -- most of the album was composed just weeks before recording -- and preserves moments of unplanned inspiration. Opener "The Real," embodies almost everything at once. Commencing with samples, loose percussion, and tight kit work from Chris Dave, a vampish melody from keyboardist James Poyser emerges and gradually invites the horn section (Keyon Harrold, trumpet; Marcus Strickland, tenor saxophone; Corey King, trombone), turntables, synths, and Hodge playing electric and acoustic basses. It's a groover; equal parts contemporary and post-bop jazz, and funky neo-soul. On "Message of Hope," Hodge plays a nearly hummable melody in the upper register of his electric, accompanied by drummer Mark Colenburg and Travis Sayles on keyboards. The bass solo builds on the repetitive vamp frenetically, becoming an encounter with jazz-rock. Common rhymes breezily and soulfully on the jazzy hip-hop of the title track, with Glasper's instantly recognizable pianos (acoustic and Rhodes), and Dave's rolling, in-the-pocket restrained snare and hi hat. Hodge moves underneath, pushing at the tune's edges until it expands. "Dances with Ancestors" is a nocturnal ballad with numerous interlocking parts from various keyboards, killer breakbeats, a post-bop horn chart, and Hodge's bass interludes tying it together. "Anthem in 7" is a syncopated, dazzling, bass-driven groover that embodies dubstep, contemporary jazz, and neo-soul. "Holding On to You," a nearly straight-ahead folk-pop number, features vocalist/guitarist Alan Hampton, and is adorned only by the leader's upright bass and his arrangement for the American String Quartet. They also appear on on the haunting "Solitude," with pianist Aaron Parks on top, and Dave keeping slippery time; Hodge solos around the entire frame, almost like a singing voice. On the public domain Christian hymn, "Doxology (I Remember)," the bassist bows his upright on the melody, accompanied by Sayles' B-3 sounding like church organ. Closer "Night Vision," on which Hodge plays all instruments, is the last of several interludes interspersed throughout the set, denoting the album's various sections. For all its exploration and diversity, Live Today would be a cipher, were it not for Hodge's intense focus that reins the entire sprawling encounter, into a provocative, utterly engaging whole.
5099968289225
001847702
Derrick Hodge Primary Artist,Synthesizer,Percussion,Electric Bass,Keyboards,Electric Piano,Vocals,Spoons,Fretless Bass Guitar,Acoustic Bass,Synthesizer Bass,Distortion,Musician
Robert Glasper Piano,Spoons,fender rhodes
Travis Sayles Synthesizer,Keyboards,Hammond B3
Aaron Parks Piano,fender rhodes
Keyon Harrold Trumpet,Flugelhorn,Muted Trumpet
Chris Dave Percussion,Drums,Spoons
Sophia Kessinger Violin
Alan Hampton Acoustic Guitar,Vocals
Keyon Harold Trumpet,Muted Trumpet
Mark Colenburg Percussion,Drums,Snare Drums
Derrick Hodge Arranger,Composer,Producer,String Arrangements
Cem Kurosman Publicity
Vincent Bennett Executive Producer
American String Quartet String Section
Stephanie Darden Art Direction

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text:
DE3175 DE3022 T10 194 168 921 578 2825 Ba9s 212 211 super size led panel white | eBay
2pcs White 24COB LED Panel Light For Car Interior Door Trunk Map Dome Bulb 12v
White 12 LED Map Dome Panel Light 211-2 578 194 Ba9 194
One piece New 24 chips COB LED Panel Light w/ T10+Festoon+BA9S HID Xenon White
Details about DE3175 DE3022 T10 194 168 921 578 2825 Ba9s 212 211 super size led panel white
DE3175 DE3022 T10 194 168 921 578 2825 Ba9s 212 211 super size led panel white
wx_led (4597 )
170712136436
Last updated on Jun 24, 2015 11:20:39 PDT View all revisions
Ba9 T4W 53 57 182 257 363 1445 6253
Surface Finish: Dome ,map, trunk,RV,Truck Interchange Part Number: Ba9 T4W 53 57 182 257 363 1445 6253 W5W 168NA
Warranty: Yes Other Part Number: Festoon 211 211-2 212 212-2 2122 214-2 2142 DE3423
Part Brand: 5050 smd HID Xenon cool white 6500K
If you are looking for more light output then this is it, made with 5050 smd led 3 chips more light than even 0603,0805,1210 or super flux, with wide view angle and loaded with numbers of led and does not need a lot of space, a lot better than use bulb type.