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Clean room and fresh smelling sheets....makes for... - Review of Hampton Inn Altoona - TripAdvisor
Clean room and fresh smelling sheets....makes for... - Review of Hampton Inn Altoona
“Easy access into and out of the parking lot”
“Wonderful staff, great breakfast, easy on to...”
“This location did not disappoint”
“Located next to the interstate and in a...”
“Near commercial mall, close to highway... and...”
“We thought we got a decent deal $98 on a...”
“The location is great right off of the...”
“Proximity to Champs Sports Bar and Restaurant”
“Typical hotel with the typical "hot" breakfast”
Beautiful upgrade to lobby and breakfast area, since our last stay in Decemember. The staff is still the same friendly smiling Front desk. Clean room and fresh smelling sheets....makes for it peaceful tired travelers sleep! Ample space for a king room and large bath. Great houskeeping staff and breakfast staff. One cannot go hungry with the vast verity of food! Coming back from a fourth of July picnic we wittnessed the beautiful firework display from Lakemont Park! What a nice surprise for us. Family oriented for holiday travel. Our grandchildren received three bracelets wjich they proudly displayed! A must stay hotel if traveling to Altoona. Impressive for a couple who travel various states 8 months of the year! Kudos to your staff!! Fantastic and ease of location to the mall and dining. Right off the intersate which made it easy to get to!
Room Tip: Call the hotel for the GPS address as it is different from the mailing. End rooms are great for chil...
Helpful? Thank lucky_lucy411 Report Ask lucky_lucy411 about Hampton Inn Altoona
This review is the subjective opinion of a TripAdvisor member and not of TripAdvisor LLC. Jeffrey C, General Manager at Hampton Inn Altoona, responded to this review,
Thank you very much for taking the time to right a review concerning your stay! I am glad to hear that you enjoyed the newly renovated first floor and breakfast area. We are very excited to show off the beautiful renovations. I am glad that you enjoyed the breakfast and the other amenities and were able to enjoy the fireworks at nearby Lakemont Park. I hope to you see again on your next trip to the Altoona area!Sincerely,Jeffrey CiprianiGeneral Manager
English first French first Italian first Portuguese first Any Kathryn D
8 helpful votes “one night only,business”
Great mattress & wonderful pillows-we hope to order pillows when home. Duvet cover clean & neat.View out our window was of heat/ac roof vents, ugly, but not noisy. Temp easy to maintain w/ controls, which was good since the window didn't open & it was over 80F outside. King NS room, only 1 sink w/ very little space on vanity.Micro & frig in rm.Entry way tile to lobby was being laid-loose,hard to roll luggage over them. Breakfast good-hot & cold choices. Cracker Barrel next door. Not in scenic area.Rms in front face highway,not that close,but don't know about noise level.Rms in back face parking lot/shops. Pool looked nice,jacuzzi.
Helpful? Thank Kathryn D Report Ask Kathryn D about Hampton Inn Altoona
Thank you so much for staying with us! we are glad that you enjoyed your stay and the amenities that we have to offer. I am glad that you liked the Hampton cloud nine bedding that we offer in our hotel.If you are ever in the area again, we hope you will choose to stay with us!Regards,Jeffrey CiprianiGeneral ManagerHampton Inn Altoona
what a place clean room large king size bed, swimming pool with hot tub. staff went out of the way to make sure all was good with room. They will have mini fridgerators in room but until then just call front desk and ask for one. I will be back again. Breakfest was either hot or cold your choice plus a on the go bag if you need one.
Helpful? Thank Daniel Z Report Ask Daniel Z about Hampton Inn Altoona
Thank you for taking the time to fill out a survey concerning your stay at our hotel! I am glad to hear that our team was able to meet your needs. We hope to see you again soon if your travels are bringing you to the Altoona area!Regards,Jeffrey CiprianiGeneral ManagerHampton Inn Altoona
62 helpful votes “Rooms need a major update”
First, the hotel is undergoing a renovation. The new breakfast area looks very nice. We stayed for one night in a king bedroom with sofa bed. The first thing I noticed were was wooden doors to enter the room. When we entered the room I could tell the rooms have not been updated for quite a long time.Red carpets and the sofa was a bright flower print form the 80's. Carpet was torn in some areas. Glad to see a nice flat screen t.v. The phones were older models and the lights and lamps were worn as well. the bathroom area was nice with a nice marble like countertop. The bead was comfortable and the linens wre plush. I will say the indoor pool area was clean with older furnishings. The bathroom in the pool area was horrible with stained walls, rust and needed a big cleaning. The temp. in the pool was perfect. I would love to know if the rooms, aka, carpet, sofas, lights will be updated during the removation process? The breakfast was good and had lots to offer.
Helpful? Thank Brian03 Report Ask Brian03 about Hampton Inn Altoona
Thank you very much for sending a response concerning your stay at our hotel in Altoona, PA. We are going to be renovating the entire hotel including the guest rooms with all new furniture, as a complete renovation. We are making a brand new hotel for our valued guests like yourself!Regards,Jeffrey CiprianiGeneral ManagerAltoona Hampton Inn
10 helpful votes “will be better once remodeling is done, but its CLEAN”
here again, clean hotel, nice breakfast, just some uneven floors and odor due to remodeling, which is to be expected IF you know in advance that this is being done. pool was very nice and very refreshing, clean, hot tub was a nice temp.
Review collected in partnership with Hampton This business uses tools provided by TripAdvisor (or one of its official Review Collection Partners) to encourage and collect guest reviews, including this one. Helpful? Thank skipsmammal Report Ask skipsmammal about Hampton Inn Altoona
Thank you for taking the time to write a review of your stay our hotel in Altoona, PA. We are very excited about our newly remodeled lobby and breakfast areas as we are almost completed with this first phase. We are remodeling to serve our valued guests better and are very pleased with the outcome. I am glad to hear that you enjoyed our amenities such as our pool and hot tub. i hope to see you again in the future,Best Wishes,Jeffrey CiprianiGeneral ManagerHampton Inn Altoona
we are Diamond Club members. Stay at Hilton Honors hotels mainly Embassy Suites over 100 nights a year for the past 3 years. When we check into a hotel owned by the Hilton group we always ask for an upgrade.We have never had a problem getting an upgrade which is common courtesy for Diamond Club members. We have stayed all over the world and have never had an issue with this request. Staff at desk were courteous however were unable to give upgrade for our stay. Seemed to indicate needed manager approval for the days we would be staying.As a Diamond Club member we usually always get free bottled water, had to ask for it instead of it being offered to us.. As we were checking in at a late hour after driving over 1200 miles to come to our home town of Altoona, PA. When we got to our room no refrig..had to go back to desk to ask for room with a refrig...next morning had do not disturb sign on door until 10:15 am..left hotel, arrived back to hotel after 5 PM neither of our hotel keys worked to open room door. Got those fixed after going back down to desk..entered room, room not made up....went down to desk they said there had been a do not disturb sign on door..which was correct until 10:15am..was handed a stack of clean towels and a bag with soap and shampoo and sent on our way to our room which had not been touched....this was unacceptable after coming down to the desk 4 times for various problems....hotel front desk was polite but not accommadating and we really got the impression they did not really care about all the blunders of this short stay at this hotel...They are going through remodeling of the lobby and were jack hammering early in the morning on Monday June 3rd. When we arrived back to the hotel on the evening of June 3rd. a sign at the front door said to go to the back door due to remodeling lobby floor. This stay was just not relaxing and everything was a big HASSLE. We were to stay 4 nights however after our room was not made up on Monday we checked out of the hotel and went down the street to the Holiday Inn Express which was very accommadating. The rooms there come with a refrigerator, granola bar and popcorn in the room, two free bottles of water everyday in refrigerator and little peppermints also! Alot of other extra ammenities and no hassles...It was an unfortunate situation in our hometown. The rooms were not that clean or in great shape and the lobby was a mess ( mainly from remodeling)..I would recommend people stay down the boulevard at the Holiday Inn Express...
Room Tip: Ask for one facing Cracker Barrel
Thank WendyLynn16 Report Ask WendyLynn16 about Hampton Inn Altoona
Thank you so much for letting me know about your concerns with your stay on at our hotel. I sincerely apologize as it sounds like we did not do our best by you and your family during your stay. Our hotel has always been known for clean and comfortable rooms, which we are very proud of. I am sorry that you did not get to experience that part of our hotel during your stay. Diamond and Gold upgrades are very common as you mention in most facets of the Hilton portfolio, however in the case of a Hampton Inn it is actually the best available room. Most Hampton Inn's do not have suites so the best available room is what you would be upgraded to. We at this Hampton have 15 suites, all of which were occupied when you checked into your hotel room. Again no excuses as we strive to make sure that each and every guest leaves our hotel feeling satisfied and happy wth their stay. Again I appreciate your comments concerning your stay , and I hope you will give us another chance will staying in the Altoona area.Regards,Jeffrey CiprianiGeneral ManagerAltoona Hampton Inn
33 helpful votes “Hardest Part - finding a parking space”
I cannot say enough about the service provided at this hotel. They are/were undergoing reservations. Room was fine, clean, and comfortable. The lobby was used for breakfast and while crowded and uncomfortable, we understood this was part of the process. Mind you, this was in April so it may be done. The indoor pool was nice and we were able to enjoy all to ourselves. If I return to this area, I will stay here again!
Helpful? Thank whpiman Report Ask whpiman about Hampton Inn Altoona
Thank you very much for choosing to write a response concerning your stay our hotel!I am very excited about our remodeled lobby and front desk areas. It is a clean and very upscale look that invites our valued guests like yourself to come and enjoy the wonderful deluxe continental breakfast! The renovations to the main part of our lobby have been completed and the staff and guests have been very pleased. I am glad you and your family were able to enjoy our pool during your stay. We all hope to see you again on your next visit to the Altoona areaRegards,Jeffrey CiprianiGeneral ManagerAltoona Hampton Inn
#5 of 15 in Altoona 456 reviews
Address: 180 Charlotte Drive, Altoona, PA 16601 Phone Number: Location:
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Crystalluria and urinary tract abnormalities associated with indinavir. - PubMed - NCBI
AbstractFormatSummarySummary (text)AbstractAbstract (text)MEDLINEXMLPMID ListApplySend to:Choose DestinationFileClipboardCollectionsE-mailOrderMy BibliographyCitation managerFormatSummary (text)Abstract (text)MEDLINEXMLPMID ListCSVCreate File1 selected item: 9230000FormatSummarySummary (text)AbstractAbstract (text)MEDLINEXMLPMID ListMeSH and Other DataE-mailSubjectAdditional textE-mailDidn't get the message? Find out why...Add to ClipboardAdd to CollectionsOrder articlesAdd to My BibliographyGenerate a file for use with external citation management software.Create File
See comment in PubMed Commons belowAnn Intern Med. 1997 Jul 15;127(2):119-25.Crystalluria and urinary tract abnormalities associated with indinavir.Kopp JB1, Miller KD, Mican JA, Feuerstein IM, Vaughan E, Baker C, Pannell LK, Falloon J.Author information1National Institute of Diabetes and Digestive and Kidney Diseases, Warren Grant Magnuson Clinical Center, National Institutes of Health, Bethesda, Maryland, USA.AbstractBACKGROUND: Indinavir, a protease inhibitor widely used to treat patients with HIV infection, has been associated with nephrolithiasis. Distinctive urinary crystals and a spectrum of urologic disorders were noted in patients receiving indinavir.OBJECTIVE: To determine the composition of urinary crystals and the frequency of asymptomatic crystalluria and urinary tract symptoms in patients receiving indinavir.PATIENTS: Patients with HIV infection who were enrolled in studies conducted at the National Institutes of Health.MEASUREMENTS: Microscopic urinalysis, high-performance liquid chromatography (HPLC) and mass spectrometry of urinary crystals and stones, and clinical evaluation of patients with urologic symptoms.RESULTS: Of 240 patients receiving indinavir, 142 provided urine specimens for analysis. Twenty-nine (20%) had crystals consisting of plate-like rectangles and fan-shaped or starburst forms. Mass spectrometry and HPLC confirmed that these crystals were composed of indinavir. Of 40 patients who were not receiving indinavir, none had similar crystals (P < 0.001). Nineteen of the 240 patients receiving indinavir (8%) developed urologic symptoms. Of these, 7 (3%) had nephrolithiasis and the other 12 (5%) had previously undescribed syndromes: crystalluria associated with dysuria and crystalluria associated with back or flank pain. Four of the patients with the latter syndrome had radiographic evidence of intrarenal sludging.CONCLUSIONS: Indinavir forms characteristic crystals in the urine. This crystalluria may be associated with dysuria and urinary frequency, with flank or back pain associated with intrarenal sludging, and with the classic syndrome of renal colic.Comment inLight microscopy of indinavir urinary crystals. [Ann Intern Med. 1998]Indinavir and interstitial nephritis. [Ann Intern Med. 1998]PMID: 9230000 [PubMed - indexed for MEDLINE] ShareMeSH Terms, SubstancesMeSH TermsAdultAnti-HIV Agents/adverse effects*Chromatography, High Pressure LiquidFemaleHIV Protease Inhibitors/adverse effects*HumansIndinavir/adverse effects*Kidney Calculi/chemically inducedMaleMass SpectrometryMiddle AgedPain/chemically inducedRisk FactorsUrination Disorders/chemically inducedUrine/chemistryUrologic Diseases/chemically induced*Urologic Diseases/urine*SubstancesAnti-HIV AgentsHIV Protease InhibitorsIndinavirLinkOut - more resourcesFull Text SourcesSilverchair Information SystemsEBSCOOvid Technologies, Inc.Other Literature SourcesCOS Scholar UniverseAccess more work from the authors - ResearchGateMedicalClinicalTrials.govRenal Manifestations of HIV - HIV InSiteHIV/AIDS Medicines - MedlinePlus Health InformationPubMed Commons home

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Katrina Mae Azcarraga Bautista
Chapter 1 Commands
Over the last few decades, technology has evolved in leaps and bounds. The people cannot deny how technology has drastically changed the way the world lives, works and learns. Technology has taken the world into a whole new level of knowledge that became the new standard in the industry. Today, it has not only improved the world of work but also the world of education. Learning was taken into new grounds because of technology. From the dusty and screechy traditional chalkboards that the teachers have to use to educate their students with was now changed to computers and mobile devices. Lectures and lessons through books given to students before were now replaced with power point presentations and PDFs on mobile devices. Aside from the rise of learning through mobile devices, e-learning system was also introduced to academes to provide a better modernized teaching technique in honing individuals to be future professionals.
FEU-East Asia Colleges E-learning system plays a vital role in giving the students the opportunity to learn anywhere at any time as long as they have an online access. Through this, academic resources could be distributed by the professor to the class, online quizzes could also be conducted, and completion of requirements could be easily managed. This system bridges the communication between the educational instructors to the students.
Through this study, the proponents decided to reengineer the design of the E-Learning System of FEU-East Asia College to give the users ease in accessing the system. This study aims to integrate and use the database of enrollment to make the e-learning system more organized and efficient.
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Ella M Brannigan Boyle (1899-1943) - Find A Grave Memorial
Ella M Brannigan Boyle
Death 18 Aug 1943
Burial Holy Cross Cemetery Mendota, LaSalle County, Illinois, USA
Memorial ID 86132036
Created by: Terence Lewnard
Find A Grave Memorial 86132036
Find A Grave, database and images (https://www.findagrave.com : accessed ), memorial page for Ella M Brannigan Boyle (27 Dec 1899–18 Aug 1943), Find A Grave Memorial no. 86132036, citing Holy Cross Cemetery, Mendota, LaSalle County, Illinois, USA ; Maintained by Terence Lewnard (contributor 47134985) .
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Patent US8067235 - Optimized human T1R2 nucleic acid molecule - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention relates to a screening system for modulators of GPCRs. Further it relates to recombinant vector systems for the heterologous expression of heterodimeric g-protein coupled receptors (GPCRs) in eukaryotic host cells. Preferably the functional expression of engineered GPCRs for the...http://www.google.com/patents/US8067235?utm_source=gb-gplus-sharePatent US8067235 - Optimized human T1R2 nucleic acid moleculeAdvanced Patent SearchPublication numberUS8067235 B2Publication typeGrantApplication numberUS 12/616,340Publication dateNov 29, 2011Filing dateNov 11, 2009Priority dateJun 7, 2006Fee statusPaidAlso published asCN101086499A, CN101086499B, DE602006012460D1, EP1865316A1, EP1865316B1, US8067236, US20090004651, US20100112688, US20100120141, US20130210046Publication number12616340, 616340, US 8067235 B2, US 8067235B2, US-B2-8067235, US8067235 B2, US8067235B2InventorsMichael Krohn, Holger ZinkeOriginal AssigneeNutrinova Nutrition Specialties & Food Ingredients GmbhExport CitationBiBTeX, EndNote, RefManPatent Citations (18), Non-Patent Citations (70), Referenced by (1), Classifications (18), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetOptimized human T1R2 nucleic acid molecule
By recombinant heterologous expression in eucaryotic cell systems a functional expression and tastant specific activation of an artificially linked G-Protein dependent signaling cascade was demonstrated by calcium imaging. T1R receptors assemble to build up functional taste receptors. As a result of several investigations it was shown that the heterodimeric T1R1/T1R3 functions as a glutamate (umami) and L-amino acid receptor whereas the heterodimeric T1R2/T1R3 functions as a high affinity sugar and artificial sweetener receptor. Particularly, heterodimeric co-expression of T1R1 and T1R3 results in taste receptors that respond to umami taste and monosodium glutamate stimuli whereas heterodimeric co-expression of T1R2 and T1R3 results in taste receptors that respond to sweet stimuli like diverse sugars (e.g. glucose and sucrose), artificial sweetener (e.g. acesulfam K, cyclamat, saccharin) and sweet proteins like monellin, thaumatin, brazzein (Li et al., 2002; Nelson et al., 2002; Nelson et al., 2001; Zhao et al., 2002). A similar chronicle could be generated for the identification of GPCRs for the perception of bitter taste with the exception that so far no homo- or oligomerisation has b

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Patent US7529137 - Methods of operating bandgap engineered memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMemory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having...http://www.google.com/patents/US7529137?utm_source=gb-gplus-sharePatent US7529137 - Methods of operating bandgap engineered memoryAdvanced Patent SearchPublication numberUS7529137 B2Publication typeGrantApplication numberUS 11/830,582Publication dateMay 5, 2009Filing dateJul 30, 2007Priority dateJan 3, 2005Fee statusPaidAlso published asUS8264028, US20060202261, US20070268753Publication number11830582, 830582, US 7529137 B2, US 7529137B2, US-B2-7529137, US7529137 B2, US7529137B2InventorsHang-Ting Lue, Szu-Yu WangOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (64), Non-Patent Citations (37), Referenced by (4), Classifications (15), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethods of operating bandgap engineered memory
US 7529137 B2Abstract
Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
This application is a continuation of U.S. patent application Ser. No. 11/324,540, filed Jan. 3, 2006, which is based upon, and claims priority under 35 U.S.C. �119(e) of: provisional U.S. Patent Application No. 60/640,229, filed on Jan. 3, 2005; provisional U.S. Patent Application No. 60/647,012, filed on Jan. 27, 2005; provisional U.S. Patent Application No. 60/689,231, filed on Jun. 10, 2005; and provisional U.S. patent application No. 60/689,314, filed on Jun. 10, 2005; the entire contents of each of which are incorporated herein by reference.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
The present invention relates to non-volatile memory devices, and more specifically, to non-volatile memory devices including a tunnel dielectric structure that facilitates self-converging erase operations while also maintaining charge retention in a charge storage layer of the memory device during retention states.
The present invention also includes non-volatile memory devices which comprise a plurality of memory cells (i.e., an array) in accordance with one or more of the embodiments described herein. As used herein, a “plurality” refers to two or more. Memory devices in accordance with the present invention exhibit significantly improved operational properties including increased erase speeds, improved charge retention and larger windows of operation.
The present invention also includes methods of operating non-volatile memory cells and arrays. Methods of operation in accordance with the present invention include resetting the memory devices by applying a self-converging method to tighten Vt distribution of the memory devices; programming at least one of the memory devices by channel +FN injection; and reading at least one of the memory devices by applying a voltage between an erased state level and a programmed state level of at least one of the memory devices. As used herein, the term “tighten” refers to the narrowing of the threshold voltage distribution among the many memory cells of an array. In general, threshold voltage distribution is “tightened” where the threshold voltages of several cells are within a narrow range of one another such that operation of the array is improved over conventional designs. For example, in some preferred embodiments, such as in a NAND array comprising memory cells in accordance with one or more embodiments of the present invention, a “tightened” threshold voltage distribution indicates that the threshold voltages of the various memory cells are within a 0.5V range of one another. In other array architectures employing memory cells in accordance with the present invention, the “tightened” threshold voltage distribution may have a range of about 1.0V from the upper limit to the lower limit.
As used herein, the phrase “small hole tunneling barrier height” refers generally to values which are less than the approximate hole tunneling barrier height of silicon dioxide. In particular, a small hole tunneling barrier height is preferably less than about 4.5 eV. More preferably, a small hole tunneling barrier height is less than or equal to about 1.9 eV.
Reference will now be made in detail to the invention and the presently preferred embodiments thereof, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the non-graph drawings are in greatly simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as top, bottom, left, right, up, down, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms used in conjunction with the following description of the drawings should not be construed to limit the scope of the invention in any manner not explicitly set forth in the appended claims. Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of entire integrated circuits. The present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are known in the art or to be developed.
Thus, for example, as depicted in FIGS. 1 a and 1 b, memory cells in accordance with the present invention may include: a multi-layer thin film tunnel dielectric structure, including a first silicon oxide layer O1, a first silicon nitride layer N1, and a second silicon oxide layer O2; a charge-storage layer, such as a second silicon nitride layer N2; and an insulating layer such as a third silicon oxide layer O3, on or over (“above”) a substrate, such as a semiconductor substrate (e.g., a silicon substrate). The tunneling dielectric structure allows hole tunneling from the substrate to the charge-storage layer during an erase/reset operation of the memory device. Preferably, the tunnel dielectric structure in a non-volatile memory cell of the present invention has a negligible charge-trapping efficiency, and more preferably, does not trap charge at all during memory operations.
FIGS. 14 a and 14 b illustrate possible electrical RESET schemes for an exemplary virtual ground array incorporating 2 bits/cell memory cells having a tunnel dielectric design discussed above. Before performing further P/E cycles, all the devices may first undergo an electrical “RESET”. A RESET process may ensure the Vt uniformity of memory cells in the same array and raise the device Vt to the convergent erased state. For example, applying Vg=−15 V for 1 sec, as shown in FIG. 14 a, may have the effect of injecting some charge into a charge trapping layer of silicon nitride to reach a dynamic balancing condition. With the RESET, even memory cells that are non-uniformly charged due, for example, to the plasma charging effect during their fabrication processes may have their Vt converged. An alternative way for creating a self-converging bias condition is to provide bias for both gate and substrate voltages. For example, referring to FIG. 14 b, Vg=−8 V and P-well=+7 V may be applied.
Referring to FIG. 23 a, in one example, the spaces (Ls) between word lines (WLs) may be formed with shallow junctions, such as shallow junctions of N+-doped regions, which may serve as source or drain regions of the memory devices. As illustrated in FIG. 23A, additional implantation and/or diffusion process, such as a tilt-angle pocket implantation, may be carried out to provide one or more “pocket” regions or pocket extensions of junctions that neighbor one or more of the shallow junction regions. In some examples, such configuration may provide better device characteristics.
After a memory array is manufactured, a reset operation may be performed to tighten the Vt distribution first before other operations of the memory array. FIG. 24 a illustrates an example of such operation. In one example, before other operations start, one may first apply VG=about −7 V and VP-well=+8 V to reset the array (The voltage drop of VG and VP-Well can be partitioned into the gate voltage into each WL and p-well). During RESET, the BL's can be floating, or raised to the same voltage as the P-Well. As illustrated in FIG. 24 b, the reset operation may provide excellent self-convergent properties. In one example, even SONONOS devices are initially charged to various Vts, the reset operation can “tighten” them to a Reset/Erase state. In one example, the reset time is about 100 msec. In that example, the memory array may use n-channel SONONOS devices with ONONO=15/20/18/70/90 angstroms having an N+-polysilicon gate with Lg/W=0.22/0.6 μm.
Generally, traditionally floating-gate devices are not capable of providing self-converging erase. In contrast, SONONOS devices may be operated with converging Reset/Erase methods. In some examples, this operation may become essential because the initial Vt distribution is often in a wide range due to certain process issues, such as process non-uniformity or plasma charging effects. The exemplary self-converging “Reset” may help to tighten, or narrow the range of, the initial Vt distribution of memory devices.
In examples of read operations, the selected WL may be raised to a voltage that is between an erased state level (EV) and a programmed state level (PV). Other WLs may serve as the “PASS gates” so that their gate voltages may be raised a voltage higher than PV. In some examples, erase operations may be similar to the reset operation noted above, which may allow self-convergence to the same or similar reset Vt.
In some examples, a split-gate design, such as a split-gate SONONOS-NAND design, may be used to achieve a more aggressive down-scaling of a memory array. FIG. 31 illustrates an example of using such design. Referring to FIG. 31, the spaces (Ls) between each word line, or between two neighboring memory devices sharing the same bit line, may be reduced. In one example, Ls may be shrunk to about or less than 30 nm. As illustrated, the memory devices using a split-gate design along the same bit line may share only one source region and one drain region. In other words, a split-gate SONONOS-NAND array may use no diffusion regions or junctions, such as N+-doped regions, for some of the memory devices. In one example, the design may also reduce or eliminate the need for shallow junctions and neighboring “pockets”, which in some examples may involve a more complicated manufacturing process. Furthermore, in some examples, the design is less affected by short-channel effects, because the channel length has been increased, such as increased to Lg=2F-Ls in one example.
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Digest, 2002, 931-934.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8264028 *Sep 11, 2012Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS8304911Nov 6, 2012Macronix International Co., Ltd.Semiconductor structure and manufacturing method of the sameUS9019764Nov 19, 2012Apr 28, 2015Aplus Flash Technology, Inc.Low-voltage page buffer to be used in NVM designUS20060202261 *Jan 3, 2006Sep 14, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays* Cited by examinerClassifications U.S. Classification365/185.28, 365/185.18, 365/185.01International ClassificationG11C16/04Cooperative ClassificationH01L29/66833, H01L27/11568, H01L27/115, G11C16/0491, G11C16/0475, G11C16/0483, H01L29/792European ClassificationH01L29/66M6T6F18, H01L29/792, H01L27/115, H01L27/115G4Legal EventsDateCodeEventDescriptionJan 19, 2010CCCertificate of correctionOct 1, 2012FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


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Bank Of Africa - Kenya Limited: Private Company Information - Bloomberg
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Bank Of Africa - Kenya Limited provides wholesale and consumer banking, and treasury products and services to corporate, SME, and retail clients. The company offers deposit products, including current accounts, fixed deposit accounts, call deposits, goodwill accounts, accounts for law firms, savings products, and BOA packs. It also provides loan products, such as Tiba finance, working capital, commercial motor loans, invoice discounting, overdrafts, and contract financing; and retail loans. In addition, the company offers letters of credit/documentary credit; and other trade services, such as documentary collection, bank guarantees, foreign bill discounting, invoice discounting, and bill ava...
Bank Of Africa - Kenya Limited provides wholesale and consumer banking, and treasury products and services to corporate, SME, and retail clients. The company offers deposit products, including current accounts, fixed deposit accounts, call deposits, goodwill accounts, accounts for law firms, savings products, and BOA packs. It also provides loan products, such as Tiba finance, working capital, commercial motor loans, invoice discounting, overdrafts, and contract financing; and retail loans. In addition, the company offers letters of credit/documentary credit; and other trade services, such as documentary collection, bank guarantees, foreign bill discounting, invoice discounting, and bill avalization. Further, it provides mobile and Internet banking, money transfer, and Visa cards; and treasury products and services, which comprise spot transactions, forward contracts, currency swaps, treasury bonds, repurchase agreements, and treasury sales and purchases. Bank Of Africa - Kenya Limited has strategic partnerships with Banque du Marocaine du commerce exterieur, Proparco, International Finance Corporation, West African Development Bank, Netherlands Development Finance Company, Belgium Investment Company for Developing Countries, and Investment Fund – Aureos. The company was founded in 2004 and is based in Nairobi, Kenya with additional branches in Nairobi, Kisumu, Nakuru, Eldoret, Bungoma, Kericho, Rongai, Kitengela, Meru, Kisii, Thika, and Mombasa. Bank Of Africa - Kenya Limited operates as a subsidiary of Bank of Africa-Benin.
Reinsurance PlazaTaifa RoadP.O. Box 69562Nairobi, 00400KenyaFounded in 2004
Phone: 254 20 327 50 00
Fax: 254 20 221 41 66
www.boakenya.com
Mr. Anis Kaddouri
Mr. Antony Oduor
Mr. Mohamed Bennani
Non Executive Director, Chairman of The Board - Bank of Africa and Managing Director of Bank of Africa
Mr. Jean-Geo Pastouret
Ms. Jane Kilonzo
Deputy Managing Director of Operations and Support
Chase Bank (Kenya) Limited Middle East/Africa Co-opholdings Co-operative Society Limited Middle East/Africa Commercial Bank of Africa Limited Middle East/Africa Consolidated Bank of Kenya Limited Middle East/Africa Credit Bank Limited Middle East/Africa
To contact Bank Of Africa - Kenya Limited, please visit www.boakenya.com. Company data is provided by S&P Global Market Intelligence. Please use this form to report any data issues.

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Same Parent, Connectivity for PubChem Substance (Select 172097219) - PubChem Substance - NCBI
Select item 2519712281.152121-30-7; 4-[4-(4-fluorophenyl)-5-pyridin-4-yl-1,3-dihydroimidazol-2-ylidene]-1-cyclohexa-2,5-dienoneSource: A2Z Chemical (AZM14730)Deposit Date: 2015-06-17 Available Date: 2015-06-17 Modify Date: 2015-06-17SID: 251971228 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 2519173492.SB 202190; 152121-30-7Source: AvaChem Scientific (2552)Deposit Date: 2015-06-01 Available Date: 2015-06-01 Modify Date: 2015-06-01SID: 251917349 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivityPubMed (MeSH Keyword)Select item 2519160013.SB 202190; 152121-30-7Source: AvaChem Scientific (152121-30-7)Deposit Date: 2015-05-30 Available Date: 2015-05-30 Modify Date: 2015-05-30SID: 251916001 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivityPubMed (MeSH Keyword)Select item 2518949274.152121-30-7; SC-27980; 4-(4-(4-fluorophenyl)-5-(pyridin-4-yl)-2H-imidazol-2-yl)phenolSource: labseeker (SC-27980)Deposit Date: 2015-05-21 Available Date: 2015-05-21 Modify Date: 2015-05-21SID: 251894927 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 2497556295.152121-30-7; Phenol, 4-[4-(4-fluorophenyl)-5-(4-pyridinyl)-1H-imidazol-2-yl]-Source: Day Biochem (DAYBIOCHEM6835)Deposit Date: 2015-03-31 Available Date: 2015-03-31 Modify Date: 2015-03-31SID: 249755629 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 2497163346.152121-30-7; CF-035; 4-[4-(4-Fluorophenyl)-5-(pyridin-4-yl)-2H-imidazol-2-yl]phenolSource: ChangChem (CF-035)Deposit Date: 2015-03-20 Available Date: 2015-03-20 Modify Date: 2015-03-20SID: 249716334 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 2411822857.SB 202190; 152121-30-7; 4-[4-(4-Fluorophenyl)-5-(4-pyridinyl)-1H-imidazol-2-yl]phenolSource: Tocris Bioscience (1264)Deposit Date: 2015-02-23 Available Date: 2015-02-23 Modify Date: 2015-02-23SID: 241182285 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivityPubMed (MeSH Keyword)Select item 2321454158.SCHEMBL6420498Source: SureChEMBL (SCHEMBL6420498)Deposit Date: 2015-02-12 Available Date: 2015-02-12 Modify Date: 2015-02-12SID: 232145415 [CID: 10382290]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 2307772239.SCHEMBL4893304Source: SureChEMBL (SCHEMBL4893304)Deposit Date: 2015-02-12 Available Date: 2015-02-12 Modify Date: 2015-02-12SID: 230777223 [CID: 6419751]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 22746138810.SCHEMBL1230814Source: SureChEMBL (SCHEMBL1230814)Deposit Date: 2015-02-12 Available Date: 2015-02-12 Modify Date: 2015-02-12SID: 227461388 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 22652247211.SCHEMBL158854Source: SureChEMBL (SCHEMBL158854)Deposit Date: 2015-02-12 Available Date: 2015-02-12 Modify Date: 2015-02-12SID: 226522472 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 22608739912.MolPort-035-395-127Source: MolPort (MolPort-035-395-127)Deposit Date: 2015-02-07 Available Date: 2015-02-07 Modify Date: 2015-02-07SID: 226087399 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 22370446613.SB 202190; MLS006010258; SMR001230795Source: MLSMR (MLS006010258)Deposit Date: 2015-01-16 Available Date: 2015-01-16 Modify Date: 2015-01-16SID: 223704466 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivityPubMed (MeSH Keyword)Select item 22366009814.AN-5323; 4-[4-(4-fluorophenyl)-5-(4-pyridyl)-1,3-dihydroimidazol-2-ylidene]cyclohexa-2,5-dien-1-oneSource: AN PharmaTech (AN-5323)Deposit Date: 2015-01-06 Available Date: 2015-01-06 Modify Date: 2015-01-06SID: 223660098 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 22363765715.AJ-128486Source: A&J Pharmtech CO., LTD. (AJ-128486)Deposit Date: 2015-01-05 Available Date: 2015-01-05 Modify Date: 2015-01-05SID: 223637657 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 22344429216.SB 202190; SB202190; CHEBI:79090 ...Source: ChEBI (CHEBI:79090)Deposit Date: 2014-12-18 Available Date: 2014-12-18 Modify Date: 2014-12-18SID: 223444292 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivityPubMed (MeSH Keyword)Select item 22314812717.AGN-PC-0O4BXT; 152121-30-7; Phenol, 4-[4-(4-fluorophenyl)-5-(4-pyridinyl)-1H-imidazol-2-yl]-Source: Angene Chemical (AGN-PC-0O4BXT)Deposit Date: 2014-11-04 Available Date: 2014-11-04 Modify Date: 2014-11-04SID: 223148127 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 20826555818.SB 202190 Hydrochloride; IN2325; 350228-36-3Source: HDH Pharma (IN2325)Deposit Date: 2014-10-03 Available Date: 2014-10-03 Modify Date: 2014-10-03SID: 208265558 [CID: 6419751]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 20826477419.FHPI and SB 202190; IN1113Source: HDH Pharma (IN1113)Deposit Date: 2014-10-03 Available Date: 2014-10-03 Modify Date: 2014-10-03SID: 208264774 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivitySelect item 20826477120.SB 202190; 152121-30-7; IN1110Source: HDH Pharma (IN1110)Deposit Date: 2014-10-03 Available Date: 2014-10-03 Modify Date: 2014-10-03SID: 208264771 [CID: 5353940]Summary PubChem Same CompoundSame Parent, ConnectivityPubMed (MeSH Keyword)
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Patent US7193298 - Lead frame - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA lead frame (1) has a first portion (2) adapted to have a semiconductor device (10) mounted thereon and a second portion (3) including a main member (5), a number of first contact members (6) and a number of second contact members (7). The first and second contact members (6, 7) depend from the main...http://www.google.com/patents/US7193298?utm_source=gb-gplus-sharePatent US7193298 - Lead frameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7193298 B2Publication typeGrantApplication numberUS 10/903,495Publication dateMar 20, 2007Filing dateJul 30, 2004Priority dateFeb 1, 2002Also published asEP1470587A1, US20050056914, USRE41510, WO2003065452A1Publication number10903495, 903495, US 7193298 B2, US 7193298B2, US-B2-7193298, US7193298 B2, US7193298B2InventorsHeng Wan Hong, Tian Siang Yip, Joo Hong Tan, Choon Muah Lee, Liang Kng Ian KohOriginal AssigneeInfineon Technologies AgExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (57), Classifications (28), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetLead frame
US 7193298 B2Abstract
A lead frame (1) has a first portion (2) adapted to have a semiconductor device (10) mounted thereon and a second portion (3) including a main member (5), a number of first contact members (6) and a number of second contact members (7). The first and second contact members (6, 7) depend from the main member (5). The second portion (3) at least partially surrounds the first portion (6). The first contact members (6) extend form the main member (5) in a direction away for the first portion (2) and the second contact members (7) extend from the main member (5) in a direction towards the first portion (2).
1. A lead frame comprising a first portion adapted to have a semiconductor device mounted thereon and a second portion comprising a main member, a first set of electrical contact members and a second set of electrical contact members, the contact members of the first and second sets extending in directions away from the main member, the second portion at least partially surrounding the first portion, wherein the first set of electrical contact members extend from the main member in a direction away train the first portion and the second set of electrical contact members extend from the main member in a direction towards the first portion, and wherein the first set of electrical contact members is electrically isolated from the second set of electrical contact members.
2. A lead frame according to claim 1, wherein the ends of the first and second sets of electrical contact members remote from the main member are substantially coplanar.
3. A lead frame according to claim 1, wherein the first portion is substantially co-planar with the remote ends of the second set of electrical contact members.
4. A lead frame according to claim 1, wherein the first set of electrical contact members are offset along the main member from the second set of electrical contact members.
5. A lead frame according to claim 1, wherein the spacing between the first set of electrical contact members adjacent the main member is greater than the width of the second set of electrical contact members adjacent to the main member.
6. A lead frame according to claim 1, wherein the spacing between the second set of electrical contact members adjacent to the main member is greater than the width of the first set of electrical contact members adjacent to the main member.
7. A lead frame according to claim 1, wherein the second portion further comprises a bond member for each of the first set of electrical contact members.
8. A lead frame according to claim 7, wherein the bond members extend from the main member in a direction towards the first portion.
9. A lead frame according to claim 8, wherein the bond members are in line with the first set of electrical contact members.
10. A lead frame according to claim 8, wherein each of the second set of electrical contact members is separated from its adjacent second set of electrical contact members by a bond member.
11. A semiconductor device package comprising a substrate, a semiconductor device mounted on the substrate and a number of electrical interconnects electrically coupling electrical contacts on the semiconductor device to contact members on the substrate, the semiconductor device and the electrical interconnects being encapsulated in an electrically insulating material, and the contact members comprising a first set of electrical contact members extending from the encapsulation material, and a second set of electrical contact members located on a surface of the encapsulating material, wherein the second set of electrical contact members have a different pitch as compared to the first set of electrical contact members, and wherein the first set of contact members is electrically isolated from the second set of contact members.
12. A semiconductor device package according to claim 11, wherein the substrate comprises a lead frame having a first portion having the semiconductor device mounted thereon and a second portion comprising a main member, wherein the electrical contact members of the first and second sets depend from the main member, the second portion at least partially surrounding the first portion, wherein the first set of electrical contact members extend from the main member in a direction away from the first portion and the second set of electrical contact members extend from the main member in a direction towards the first portion.
13. A semiconductor device package according to claim 11, wherein the second set of electrical contact members located on the surface of the encapsulating material are substantially co-planar with the ends of the first set of electrical contact members extending from the encapsulating material.
14. A semiconductor device package according to claim 11, wherein the second set of electrical contact members are substantially flush with the surface of the encapsulating material.
15. A semiconductor device package according to claim 11, wherein the surface of the encapsulating material on which the second set of electrical contact members are located is the surface of the encapsulating material adjacent to the underside of the substrate, which is the side opposite to the side on which the semiconductor device is mounted.
16. A semiconductor device package according to claim 15, wherein the underside of the substrate is exposed on the same surface of the encapsulating material on which the second set of electrical contact members are exposed.
17. A semiconductor device package according to claim 16 wherein the exposed underside at the substrate is substantially co-planar with the second set of electrical contact members.
This application is a continuation of co-pending International Application No. PCT/SG02/00014, filed Feb. 1, 2002, which designated the United States and was published in English.
The invention relates to a lead frame, and especially a lead frame for mounting a semiconductor device thereon.
Due to higher system integration, there is a trend to increase the number of input/output pins (i.e., pin count) on integrated circuit packages. At the same time, there is also a desire to reduce the package size. However, the increase in pin count places a limitation on the reduction of the package size, unless the pitch of the pins is reduced. Reducing the pitch of the pins leads to more complication during fabrication as it requires processes, such as stamping tool fabrication, dambar cut process, testing and surface mount technology to be more accurate.
Therefore, there is a conflict between increasing system integration, which results in a higher pin count, and reducing the size of the integrated circuit package.
In accordance with a first aspect of the present invention, there is provided a lead frame comprising a first portion adapted to have a semiconductor device mounted thereon and a second portion comprising a main member, a number of first contact members and a number of second contact members, the first and second contact members depending from the main member, the second portion at least partially encircling the first portion and the first contact members extending from the main member in a direction away from the first portion and the second contact members extending from the main member in a direction towards the first portion.
An advantage of the invention is that by having contact members which extend both towards and away from the first portion, it is possible to increase the number of contact members for a given package size without requiring a decrease in the pitch of the contact members.
Preferably, the ends of the first and second contact members remote from the main member are substantially co-planar.
Typically, the first portion may also be co-planar with the remote ends of the first and second contact members.
Preferably, the first contact members are offset along the main member from the second contact members.
Typically, the spacing between the first contact members adjacent the main member is greater than the width of the second contact members adjacent to the main member.
Preferably, the spacing between the second contact members adjacent to the main member is greater than the width of the first contact members adjacent to the main member.
Typically, the second portion further comprises a bond member for each of the first contact members, the bond members extending from the main member in a direction towards the first portion. Typically, the bond members are in line with the first contact members and preferably each of the second contact members is separated from its adjacent second contact members by a bond member.
In accordance with a second aspect of the present invention, there is provided a semiconductor device package comprising a substrate, a semiconductor device mounted on the substrate and a number of electrical interconnects electrically coupling electrical contacts on the semiconductor device to contact members on the substrate, the semiconductor device and the electrical interconnects being encapsulated in an electrically insulating material, and the contact members comprising a number of contact members extending from the encapsulation material and a number of second contact members located on a surface of the encapsulating material.
Preferably, the substrate is a lead frame in accordance with the first aspect of the present invention.
Preferably, the second contact members located on the surface of the encapsulating material are substantially co-planar with the ends of the first contact members extending from the encapsulating material.
Preferably, the second contact members are substantially flush with the surface of the encapsulating material. However, it is possible that they may protrude from the surface.
Typically, the surface of the encapsulating material on which the second electrical contact members are located is the surface of the encapsulating material adjacent to the underside of the substrate, which is the side opposite to the side on which the semiconductor device is mounted.
In one example of the invention, the underside of the substrate is exposed on the same surface of the encapsulating material on which the second electrical contact members are exposed, and typically, the exposed underside of the substrate is substantially co-planar with the second electrical contact members.
An example of a lead frame in accordance with the present invention will now be described with reference to the accompanying drawings, in which:
FIG. 1 is plan view of part of a lead frame;
FIG. 2 is an enlarged view of detail “A” of FIG. 1;
FIG. 3 is a perspective view of an upside down packaged semiconductor device;
FIG. 4 is a cross-sectional view of the packaged semiconductor device;
FIG. 5 is a bottom view of the packaged semiconductor device;
FIG. 6 is a side view of the packaged semiconductor device; and
FIG. 7 is a plan view of the packaged semiconductor device.
FIG. 1 shows a part of a lead frame 1, which includes a die pad 2 and a contact pin portion 3, which surrounds the die pad 2. The die pad 2 is connected to the contact pin portion 3 by supports 4.
The contact pin portion 3 comprises a central section 5 commonly known as a dambar, which extends substantially parallel to each of the sides of the die pad 2. The dambar 5 has a set of first electrical contacts 6 extending from the dambar 5 in a direction away from the die pad 2. In addition, there are a set of second electrical contacts 7 extending from the dambar 5 in a direction towards the die pad 2. Located between each pair of adjacent second electrical contacts 7 is a bond member 8. The arrangement of the first and second contact members and the bond members 8 on the dambar 5 is shown in more detail in FIG. 2. The bond members 8 are arranged to be in-line with the first electrical contacts 6, and the second electrical contacts 7 are offset from the first electrical contacts 6.
In use, a semiconductor chip 10 is attached to the die pad 2 using a conventional die attach adhesive (see FIG. 4). Wire bonds 11, 12 are then formed, which extend from contact pads (not shown) on the chip 10 to the bond members 8 and the second contact members 7, respectively. An encapsulation process is then carried out to mold an electrically insulating encapsulating material 13 around the die pad 2, the chip 10, the wire bonds 11, 12, the second contacts 7 and the bond members 8.
After the encapsulation process, portions 9 of the dambar 5 are punched out during a trim/form process. It can be seen from FIG. 2 that after the portions 9 have been punched out of the dambar 5, the first contacts 6 are still connected to the bond members 8 but are electrically isolated from the second contacts 7, and the first contacts 6, bond members 8 and second contacts 7 are all held in their respective positions by the encapsulating material 13.
A finished molded semiconductor device package 20, which in this case is a quad flat package (QFP), is shown in FIGS. 3 to 7. The underside of the die pad 2 and the ends of the second contacts 7, which are remote from the dambar 5, are exposed through the surface of the encapsulating material 13.
The first contacts 6 extend from the sides of the packaged device 20 in the same way as the pins on a conventional lead frame based package.
It will also be noted from FIGS. 4 and 6 that ends 15 of the first contacts 6 are substantially co-planar with the exposed ends of the second contacts 7 and with the underside of the die pad 2. This helps to ensure that when the packaged device 20 is connected to a circuit board, the first contacts 6, the second contacts 7 and the underside of the die pad 2 all contact the circuit board.
The exposed underside of the die pad 2 is an optional feature and it is possible that the lead frame and the mold for molding the encapsulating material 13 could be configured such that the underside of the die pad 2 is not exposed but is covered with encapsulating material 13. In addition, it may be desirable to perform the molding process such that the exposed ends of the second contacts 7 and (optionally) the underside of the die pad 2 protrude from the surface of the encapsulating material 13 instead of being flush with the surface of the encapsulating material 13.
In the lead frame 1, the pitch of the first contact members 6 is defined as “A” and the pitch of the second contact members 7 is defined as “B” (see FIG. 1). Table 1 below shows typical pin counts for a package according to the invention compared with a standard QFP for different body sizes. It can be seen from Table 1 that the invention enables a QFP of a given size to have either a higher pin count for a similar pin pitch, a greater pin pitch for a similar pin count or a combination of both.
Accordingly, the invention has the advantage of permitting a higher pin count and/or a larger pin pitch for a given package size.
Package of Invention
Standard QFP
Total pin
pitch A (mm)
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package on package systemUS20100123227 *Nov 17, 2008May 20, 2010Frederick Rodriguez DahiligIntegrated circuit packaging system with increased connectivity and method of manufacture thereofUS20110068447 *Mar 24, 2011Zigmund Ramirez CamachoIntegrated circuit packaging system with circuitry stacking and method of manufacture thereof* Cited by examinerClassifications U.S. Classification257/666, 257/E23.031, 257/676, 257/787, 257/784, 257/E23.043, 257/E23.047International ClassificationH01L23/52, H01L23/48, H01L23/495, H01L23/28Cooperative ClassificationH01L2924/14, H01L2924/00014, H01L24/45, H01L2924/181, H01L2224/85399, H01L2224/45099, H01L2224/05599, H01L24/49, H01L24/48, H01L23/4334, H01L23/49551, H01L2224/48091, H01L2224/49109, H01L23/49541, H01L2224/48247European ClassificationH01L23/495G4B, H01L23/495GLegal EventsDateCodeEventDescriptionOct 19, 2004ASAssignmentOwner name: INFINEON TECHNOLOGIES AG, GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HONG, HENG WAN;KOH, LIANG KNG IAN;YIP, TIAN SIANG;AND OTHERS;REEL/FRAME:015262/0722Effective date: 20030127Apr 28, 2009RFReissue application filedEffective date: 20090320RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services