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Patent US20050074949 - Semiconductor device and a method for fabricating the semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; and forming gate lines on the field oxide regions and the gate oxide lines, the gate lines...http://www.google.com/patents/US20050074949?utm_source=gb-gplus-sharePatent US20050074949 - Semiconductor device and a method for fabricating the semiconductor deviceAdvanced Patent SearchPublication numberUS20050074949 A1Publication typeApplicationApplication numberUS 10/954,488Publication dateApr 7, 2005Filing dateOct 1, 2004Priority dateOct 1, 2003Publication number10954488, 954488, US 2005/0074949 A1, US 2005/074949 A1, US 20050074949 A1, US 20050074949A1, US 2005074949 A1, US 2005074949A1, US-A1-20050074949, US-A1-2005074949, US2005/0074949A1, US2005/074949A1, US20050074949 A1, US20050074949A1, US2005074949 A1, US2005074949A1InventorsSung Jung, Jum KimOriginal AssigneeDongbu Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (13), Classifications (11), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and a method for fabricating the semiconductor deviceUS 20050074949 A1Abstract A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; and forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions, wherein forming the gate lines also includes forming recesses in the semiconductor substrate between the gate lines, the recesses exposing portions of the semiconductor substrate. Images(9) Claims(21)
1. A semiconductor device, comprising: linear field oxide regions formed on a semiconductor substrate; gate oxide lines formed on active regions of the semiconductor substrate between the field oxide regions; gate lines formed on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions; and recesses in the semiconductor substrate below portions of the gate oxide lines between the gate lines, the recesses exposing portions of the semiconductor substrate. 2. The device of claim 1, wherein the recesses have a depth of 500�2500 Å measured from an upper surface of the semiconductor substrate. 3. The device of claim 1, wherein the field oxide regions include a trench having a depth of 1500�4000 Å measured from an upper surface of the semiconductor substrate. 4. The device of claim 1, wherein the gate lines have a thickness of 600�2500 Å. 5. The device of claim 1, wherein the gate lines comprise a first polycrystalline silicon layer, a dielectric layer, and a second polycrystalline silicon layer. 6. The device of claim 5, wherein the dielectric layer includes a stacking structure of oxide layer�nitride layer�oxide layer. 7. The device of claim 1, further comprising: cavities formed by removing portions of the field oxide regions between the gate lines; and a self-aligned source (SAS) region in the semiconductor substrate exposed through the recesses and cavities, wherein the self-aligned source region is formed by injecting impurity ions. 8. The device of claim 1, wherein the field oxide regions are substantially parallel to a bit line of the device, and the gate lines are substantially parallel to a word line of the device. 9. A method for fabricating a semiconductor device, comprising: forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; and forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions, wherein forming the gate lines also include forming recesses in the semiconductor substrate between the gate lines, the recesses exposing portions of the semiconductor substrate. 10. The method of claim 9, wherein the recesses have a depth of 500�2500 Å measured from an upper surface of the semiconductor substrate. 11. The method of claim 9, wherein the field oxide regions have a depth of 1500�4000 Å measured from an upper surface of the semiconductor substrate. 12. The method of claim 9, wherein the gate lines have a thickness of 600�2500 Å. 13. The method of claim 9, further comprising: etching portions of the field oxide regions between the gate lines to form cavities, after forming the gate lines; and forming a self-aligned source (SAS) region by injecting impurity ions into the semiconductor substrate exposed through the recesses and cavities. 14. The method of claim 9, wherein the field oxide regions are substantially parallel to a bit line of the device, and the gate lines are substantially parallel to a word line of the device. 15. A method for fabricating a semiconductor device, comprising: forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; forming first gate lines on the field oxide regions and the gate oxide lines, the first gate lines being substantially perpendicular to the field oxide regions and having openings exposing the gate oxide lines; forming a dielectric layer over the first gate lines; and forming second gate lines on the dielectric layer and the field oxide regions, the second gate lines being substantially perpendicular to the field oxide regions, wherein forming the second gate lines also includes forming recesses in the semiconductor substrate between the gate lines, the recesses exposing portions of the semiconductor substrate. 16. The method of claim 15, wherein the dielectric layer includes a stacking structure of oxide layer�nitride layer�oxide layer. 17. The method of claim 15, wherein the recesses have a depth of 500�2500 Å measured from an upper surface of the semiconductor substrate. 18. The method of claim 15, wherein the field oxide regions have a depth of 1500�4000 Å measured from the upper surface of the semiconductor substrate. 19. The method of claim 15, wherein the gate lines have a thickness of 600�2500 Å. 20. The method of claim 15, further comprising: etching portions of the field oxide regions between the first gate lines to form cavities, after forming the second gate lines; and forming a self-aligned source (SAS) region by injecting impurity ions into the semiconductor substrate exposed through the recesses and cavities. 21. The method of claim 15, wherein the field oxide regions are substantially parallel to a bit line of the device, and the gate lines are substantially parallel to a word line of the device.
RELATED APPLICATION This application is related to and claims priority to Korean Patent Application No. 10-2003-0068498, filed on Oct. 1, 2003, the entire contents of which are incorporated herein as a reference. BACKGROUND (a) Technical Field The present invention relates to a method for fabricating a semiconductor device and, in particular, to a method for decreasing the height difference between a field oxide region and an active region so as to reduce self-aligned source (SAS) resistance at a cell region. (b) Description of the Related Art Recently, with the wide applications of flash memories and growing competition in price thereof, various technologies have been developed to reduce the sizes of the memory devices. One such technology is a self-aligned source (SAS) technique. The SAS technique is a method for reducing the cell size in a bit line direction and was described in U.S. Pat. No. 5,120,671. The SAS technique is essentially adopted for below−0.25 μm line width technology. Because the SAS technology can reduce a gap between the gate and the source of a transistor, the size of a memory cell can be reduced by about 20% with the introduction of the SAS technique. However, the conventional SAS technique has a drawback in that junction resistance of the source per cell dramatically increases because the SAS region is formed along a trench profile. Moreover, the SAS technique has another drawback in that the resistivity at a sidewall of a trench, which is a boundary region between the trench region and an active region, is much greater than and may be about 10 times as much as that at the horizontal surfaces of the trench, because the depth and amount of the implantation of the impurity ions in the sidewall are smaller than those in the other regions, such as the horizontal surfaces of the trench and the active regions. SUMMARY It is therefore desirable to address the above problem and to provide a method for fabricating a semiconductor device, which is capable of reducing the resistance generated from adopting the SAS technique. It is also desirable to provide a method for fabricating a semiconductor device, which is capable of reducing the resistance at the sidewall of the SAS region. Consistent with an embodiment of the present invention, there is provided a semiconductor device that includes linear field oxide regions on a semiconductor substrate; gate oxide lines on active regions of the semiconductor substrate between the field oxide regions; gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions; and recesses in the semiconductor substrate below portions of the gate oxide lines between the gate lines, the recesses exposing portions of the semiconductor substrate. Consistent with the present invention, there is also provided a method for fabricating a semiconductor device that includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; and forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions, wherein forming the gate lines also includes forming recesses in the semiconductor substrate between the gate lines, the recesses exposing portions of the semiconductor substrate. Consistent with the present invention, there is further provided a method for fabricating a semiconductor device that includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; forming first gate lines on the field oxide regions and the gate oxide lines, the first gate lines being substantially perpendicular to the field oxide regions and having openingsexposing the gate oxide lines; forming a dielectric layer over the first gate lines; and forming second gate lines on the dielectric layer and the field oxide regions, the second gate lines being substantially perpendicular to the field oxide regions, wherein forming the second gate lines also includes forming recesses in the semiconductor substrate between the gate lines, the recesses exposing portions of the semiconductor substrate. Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings: FIG. 1A is a plan view illustrating a conventional memory cell without the SAS technique; FIG. 1B is a plan view illustrating a memory cell fabricated with the SAS technique; FIG. 1C is a cross sectional view of a portion of the memory cell of FIG. 1B taken along line I-I′; FIGS. 1D and 1E are cross sectional views illustrating a process of forming gate lines of the memory device of FIG. 1B taken along line II-II′ as shown in FIG. 1B; FIG. 1F is a plan view of a mask used for forming the gate lines of the memory device of FIG. 1B; FIG. 2 is a plan view of a memory device consistent with an embodiment of the present invention; FIGS. 3A and 3B illustrate cross-sectional views of the memory device of FIG. 2 along line III-III′ during a manufacturing process thereof; FIG. 4 is a plan view of a mask pattern used during the manufacturing process of the memory device of FIG. 2; and FIG. 5 is a cross sectional view of a portion of the memory device of FIG. 2 along line IV-IV′.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. The SAS technique is a technology for reducing the size of a memory cell in a bit line direction by decreasing a gap between a gate and a source of transistors. The SAS technique is an essential process for devices with a below−0.25 μm line width. Typically, a NOR type flash memory utilizes a common source and one source contact is formed per 16 memory cells. FIG. 1A is a plan view illustrating a conventional memory cell 100 without using the SAS technique, FIG. 1B is a plan view illustrating memory cell 100 fabricated with the SAS technique, and FIG. 1C is a cross sectional view of a portion of memory cell 100 taken along line I-I′ in FIG. 1B. In FIG. 1A, field oxide regions 10 as device isolation regions are formed in a semiconductor substrate (not numbered) in a bit line (BL) direction, and active regions 20 in which devices are formed are defined between field oxide regions 10. A drain contact 30 is formed at each cell formed in the active region 20. A plurality of gate lines 40 are formed in a word line (WL) direction, and a plurality of common source lines 50 are formed in parallel with the gate line 40 at a predetermined distance therefrom. Only one gate line 40 and one common source line 50 are shown in FIG. 1A. As shown in FIG. 1B and FIG. 1C, by introducing the SAS technique for forming memory cell 1, an SAS region 70 is formed by injecting impurity ions in a common source region which corresponds to common source line 50 after etching a plurality of field oxide trenches 60 in the semiconductor substrate. Oxide is then deposited in field oxide trenches 60 to form field oxide regions 10. FIGS. 1D and 1E are cross sectional views along line II-II′ of FIG. 1B illustrating a process of forming gate lines 40, wherein two gate lines 40 are shown. FIG. 1F is a plan view of a mask used for forming gate lines 40. In FIGS. 1D and 1E, it is assumed that memory cell 100 is a flash memory cell and that each of gate lines 40 comprises a first polycrystalline silicon (polysilicon) layer acting as a floating gate, a dielectric layer such as a stacking structure of oxide-nitride-oxide (ONO) layer, and a second polysilicon. Referring to FIG. 1D, a gate oxide layer such as tunneling oxide layer 110, a first polysilicon layer 120 acting as a floating gate, a dielectric layer 130, and a second polysilicon layer 140 are sequentially formed on a semiconductor substrate 100. A photoresist pattern 150 for forming gate lines 40 is formed on second polysilicon 140. Optionally, mask pattern 90 as shown in FIG. 1F may be used to pattern first polysilicon 120 prior to the deposition of dielectric layer 130. Next, with reference to FIG. 1E, second polysilicon layer 140, dielectric layer 130, and first polysilicon layer 120 are etched using photoresist pattern 150 as a mask. Accordingly, a plurality of gate lines 40 are formed. Because SAS region 70 (FIG. 1C) is formed along the trench profile of trenches 60 and because the actual junction resistance is proportional to a surface length of the SAS region 70, the actual junction resistance of the source per cell increases dramatically. Also, because the depth and amount of the implantation of the impurity ions in the sidewalls of trenches 60 are smaller than those in the other regions, such as the horizontal surfaces of trenches 60 and active regions 20, the resistivity of the sidewalls in trenches 60 is much greater than the resistivity in the other regions. Particularly, when injecting impurity ions for forming SAS region 70, impurity ions are injected with a tilt angle a into the sidewalls of trenches 60 and, therefore, the injection energy and the amount of impurity ions injected into each sidewall are less than those onto the horizontal surfaces of trenches 60 and active regions 20, and are proportional to sine α. Typically, the resistivity at the sidewall portions are about 10 times greater than that at the other surfaces such as the horizontal surfaces of trenches 60 and active region 20. Consistent with an embodiment of the present invention, a height of an active region of a memory device is reduced to decrease a height difference between a field oxide region and the active region. A memory device consistent with an embodiment of the present invention and the method thereof may be described with reference to FIGS. 2-4, wherein FIG. 2 is a plan view of a memory device 200, FIGS. 3A and 3B illustrate cross-sectional views of memory device 200 along line III-III′ in FIG. 2 during a manufacturing process of memory device 200, FIG. 4 is a plan view of a mask pattern used during the manufacturing process of memory device 200, and FIG. 5 is a cross sectional view of a portion of memory device 200 along line IV-IV′ in FIG. 2, wherein only active regions and field oxide regions of memory device 200 are shown in FIG. 5. Referring to FIG. 2 and FIGS. 3A-3B, a memory device 200 consistent with the embodiment of the present invention includes a plurality of field oxide regions 204 formed in a semiconductor substrate 202 for defining a plurality of active regions 206. Memory cells (not shown) are formed in active regions 206 and drain contacts 208 for providing contacts to the memory cells are shown in FIG. 2. A plurality of gate lines 210 (only one of which is shown in FIG. 2) are formed over the semiconductor substrate. Also as shown in FIG. 3B, each gate line 210 is isolated from semiconductor substrate 202 by gate oxide layer 212 and comprises a floating gate 214, a dielectric layer 216, and a control gate 218. A method for fabricating semiconductor device 200 consistent with the present invention will be described in detail. First, linear trench lines, i.e., field oxide regions 204, are formed on semiconductor substrate 202 by etching a plurality of trenches in parallel with a bit line direction. Next, after an oxide is filled in the trench, gate oxide lines 212 are formed on the semiconductor substrate between the trench lines. Next, gate lines 210 are formed on the trench lines and the gate oxide lines in a direction perpendicular to the trench lines, i.e., in parallel with a word line direction. Gate lines 210 are formed as follows. First, a first polysilicon layer 214 a is formed by depositing and etching a layer of polysilicon. A mask pattern 220 as shown in FIG. 4 is used to etch the first polysilicon to form first polysilicon layer 214 a. As shown in FIG. 4, mask pattern 220 includes openings (only one of which is shown in FIG. 4) having a width d. Accordingly, first polysilicon gate lines 214 a have the same pattern as mask pattern 220 and, as shown in FIG. 3A, first polysilicon gate lines 214 a are formed with openings 222 (only one of which is shown in FIG. 3A), exposing portions of gate oxide 212 on a portion of active region 206 where a source line of memory device 200 is to be formed, as shown in FIG. 3A. Second, a dielectric layer 216 a such as an ONO multilayer is deposited, followed by the deposition of a second polysilicon layer 218 a. Then, a photoresist pattern 224 in parallel to the word line direction is used to sequentially etch second polysilicon layer 218 a, ONO layer 216 a, and first polysilicon layer 214 a to form gate lines 210. Then, gate oxide layer 212 and semiconductor substrate 202 are further etched to form a plurality of recesses 226 (only one of which is shown in FIG. 3B) in a common source region of semiconductor substrate 202, as shown in FIG. 3B. FIG. 3B also indicates that recesses 226 have a depth R. Then, as shown in FIG. 5, after gate lines 210 are formed, the oxide in portions of the trench lines, i.e., field oxide regions 204 in the common source region located between gate lines 210, is etched away, forming a plurality of cavities 228 in the trench lines. Impurity ions are then injected into semiconductor substrate 202 exposed through recesses 226 and cavities 228 to form a SAS region 230. Because recesses 226 (FIGS. 3B and 5), which expose portions of semiconductor substrate 202 below gate oxide 212 between gate lines 210, are formed and have a depth R, the height of the top of SAS region 230 becomes lower by R, as compared to SAS region 70 of conventional memory device 100 as shown in FIG. 1C, provided other conditions are the same. Accordingly, the resistance of SAS region 230 becomes lower. The depth R of recesses 226 may be adjusted and may depend on the depth of cavities 228. In one aspect, R is equal to or less than the depth of cavities 228. For example, the cavities are formed to have a depth of 1500�4000 Å measured from the upper surface of semiconductor substrate 202, and recesses 226 may have a depth of 500�2500 Å measured from the upper surface of semiconductor substrate 202. Also, in an aspect of the embodiment of the present invention, the first polysilicon 214 has a thickness of 600�2500 Å. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed process without departing from the scope or spirit of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7368362Jun 8, 2006May 6, 2008Micron Technology, Inc.Methods for increasing photo alignment marginsUS7390746Aug 25, 2005Jun 24, 2008Micron Technology, Inc.Multiple deposition for integration of spacers in pitch multiplication processUS7393789Sep 1, 2005Jul 1, 2008Micron Technology, Inc.Protective coating for planarizationUS7396781Jun 9, 2005Jul 8, 2008Micron Technology, Inc.Method and apparatus for adjusting feature size and positionUS7413981Jul 29, 2005Aug 19, 2008Micron Technology, Inc.Pitch doubled circuit layoutUS7429536 *May 23, 2005Sep 30, 2008Micron Technology, Inc.Methods for forming arrays of small, closely spaced featuresUS7435536Jun 20, 2006Oct 14, 2008Micron Technology, Inc.Method to align mask patternsUS7455956Mar 26, 2007Nov 25, 2008Micron Technology, Inc.Method to align mask patternsUS7547640Jul 24, 2006Jun 16, 2009Micron Technology, Inc.Method for integrated circuit fabrication using pitch multiplicationUS7611944Aug 31, 2005Nov 3, 2009Micron Technology, Inc.Integrated circuit fabricationUS7659208Dec 6, 2007Feb 9, 2010Micron Technology, IncMethod for forming high density patternsUS8011090May 19, 2008Sep 6, 2011Micron Technology, Inc.Method for forming and planarizing adjacent regions of an integrated circuitUS8264010Jul 6, 2010Sep 11, 2012Round Rock Research, LlcLayout for high density conductive interconnects* Cited by examinerClassifications U.S. Classification438/424, 257/E27.103, 257/E21.682International ClassificationH01L21/336, H01L21/8247, H01L27/115, H01L21/76Cooperative ClassificationH01L27/115, H01L27/11521European ClassificationH01L27/115, H01L27/115F4Legal EventsDateCodeEventDescriptionJul 12, 2006ASAssignmentOwner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: CHANGE OF NAME;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:018094/0024Effective date: 20060324Owner name: DONGBU ELECTRONICS CO., LTD.,KOREA, REPUBLIC OFFree format text: CHANGE OF NAME;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:18094/24Free format text: CHANGE OF NAME;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:18094/24Apr 26, 2005ASAssignmentOwner name: DONGBUANAM SEMICONDUCTOR INC., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DONGBU ELECTRONICS CO., LTD.;REEL/FRAME:016498/0211Effective date: 20041221Oct 1, 2004ASAssignmentOwner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JUNG, SUNG MUN;KIM, JUM SOO;REEL/FRAME:015863/0708Effective date: 20041001RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


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Inheritance rules and estate planning
Cross Border Estate Planning An Italian Perspective London – 22 June 2010 Avv. Vincenzo Sinisi Sinisi Ceschini Mancini & Partners Law Offices Via Pasquale Stanislao Mancini 2 – Rome Phone +39 06 3221485 Fax +39 06 3613266 e-mail vsinisi@scm-partners.it

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Law applicable under Italian conflict of law rules

The conflict of law rules are codified and are dictated by Law 31 May 1995, n. 218.

The conflict rules regarding inheritance are covered by Article 46 through 50 of Law 218/95 which cover:

Law applicable to inheritance rights

Law applicable to the capacity to write a will

Formalities for a valid will

Succession rights of the State

Jurisdiction

Law Applicable to Inheritance Rights

The default principles provides that inheritance rights are governed by the law of the country of which the deceased was a citizen at the time of the death, irrespective of the location of the assets.

In the event of dual citizenship, the applicable law is the law of the country with which the deceased had the closest connection, however if the deceased was also Italian citizen, Italian law will prevail (art. 19)

Inheritance Rights and Choice of Law

The testator may derogate to the application of the law of citizenship with an express choice of law clause in the testament, however the only permitted alternative is the law of the country of residence at the time of the death

The applicability of the law of residence cannot derogate to the forced heirship entitlements in favour of heirs which are, at the time of the death:

of Italian nationality, and

resident in Italy

Division of inheritance

If the estate is left undivided to the heirs, the division is subject, by default, to the same law which governs inheritance rights.

However, the heirs may however jointly decided to apply either :

the law of the country the death eventuated; or

the law of the country where the majority of the assets are located.

Legal capacity to make a testament and law applicable to form

The capacity to make a testament, or to amend or revoke a testament is subject to the law of citizenship of the testator at the time the testament was made, amended or revoked.

A testament is valid, as to its form, if in compliance with the laws of:

Country of citizenship at the time of making the testament or at time of death; or

Country of residence or domicile at time of making of testament or at time of death; or

Country were the testament was made.

Jurisdiction

Italian courts will have jurisdiction over inheritance disputes when:

The deceased was an Italian citizen at the time of death

The death occurred in Italy

Most of the assets are located in Italy

Defendant is domiciled or resident in Italy or has accepted Italian jurisdiction (except when the litigation involved real estate situated outside Italy)

The litigation relates to assets located in Italy

Italian inheritance law and forced heirship rules Entitled parties

When the deceased has relatives he/she is not entirely free to dispose of its assets, as Italian law reserves a portion of the estate of the deceased to certain relatives:

Spouse

Children (and their offspring if children had died or are unwilling to accept inheritance)

Parents and progenitors (only when no children exist)

Those people are called “legittimari”.

A testament in violation of forced heirship rules is not, however, void per se, and a specific recovery action by the damaged heir is required.

Determining the assets of the Estate for forced heirship purposes

The estate on which the entitlement is calculated includes:

All assets owned by the deceased at the time of his death

Plus

All lifetime gifts made by the deceased, including gifts to heirs and third parties

Minus

All debts of the deceased at the time of the death

All Assets, including past gifts are considered with reference to their market value at the time of the death

Shares of entitlement Family relationhip Entitlement Spouse only with no children. 1/2 to the spouse. Spouse and one child 1/3 to the spouse 1/3 to the child Spouse and 2 or more children 1/ 3 to the spouse 1/ 3 to the children Spouse and parents. No children 1/2 to the spouse 1/4 to the parents 1 child with no surviving spouse 1/2 to the child 2 or more children with no surving spouse 2/3 divided in equal shares Only parent(s) and /or progenitors 1/3 to the parents/progenitors 11.
Challenging violation of forced heirship rules

The legal action

The action is aimed at revoking, in all or in part, the testamentary dispositions or the gifts made in excess of the share that could be freely disposed of by the deceased

Legitimate plaintiffs

The heirs which have a forced heirship entitlement, and their successors, with some limitations for people who had received gifts

Parties

All heirs and against the third parties who received a gift, if the gift is to be revoked

Challenging violation of forced heirship rules

Timing

The heir who did not received the appropriate share of the estate may claim it within 10 years from the death of the deceased. The sending of a simple claim letter will case the start of a new 10 year term

Voiding dispositions in violation of forced heirship rules

Revoking testamentary dispositions and gifts

Testamentary dispositions, including LEGATI, are the first ones to be revked. The revocation is proportional, without differentiating between heirs and legatees (art.558), however the testator may also indicate that certain dispositions must be preferred.

Gifts are revoked only if the revocation of the testamentary dispositions is not sufficient to safeguard forced heirship entitements. Gifts are revoked in reverse chronological order, starting from the most recent one

An alternative approach Family Agreements (Patti di famiglia) 15.
Introduction to death duties in Italy

Inheritance taxes, previously abolished, were reintroduced in Italy in 2006 with a rate ranging between 4% and 8%. In addition to inheritance taxes, if the Estate includes immovable properties, or registered movable properties, certain transfer taxes are also due

Territorial scope

If the deceased was an Italian resident, the relevant taxes are due on all assets. If the deceased was not an Italian resident, inheritance taxes are due only on Italian assets. Transfer taxes are always due on Italian assets only

Determining the value of assets

Value is determined at the date of the death, which is the date on which succession tales place

For real estate located in Italy, reference is made to tax value, which is normally quite lower than actual market value

For real estate located abroad, use of tax value accepted by foreign tax authorities is permitted. The tax office will normally rely on the value reported in the inheritance tax return

Debts are deducted . Debt that are not strictly related to a specific assets are used to redice proportionally each share of inheritance

Tax Burden: Spouse and children Type of asset Inheritance tax Cadastral tax Registration tax Real estate 4% 1% 2% Other properties 4% ------ -------- Exemptions 1.000.000 EUR ------ ------- 18.
Tax Burden: Brothers and Sisters Type of asset Inheritance tax Cadastral tax Registration tax Real estate 6% 1% 2% Other properties 6% ------ -------- Exemptions 100.000 EUR ------ ------- 19.
Tax Burden: Other relatives up to 4° degree and relatives in law up to 3° degree Type of asset Inheritance tax Cadastral tax Registration tax Real estate 6% 1% 2% Other properties 6% ------ -------- Exemptions ---------- ------ ------- 20.
Tax Burden: Unrelated heirs Type of asset Inheritance tax Cadastral tax Registration tax Real estate 8% 1% 2% Other properties 8% ------ -------- Exemptions --------- ------ ------- 21.
Tax Burden: Special Exemptions Ground for exemption Exemption Heir with Handicap No inheritance tax for first 1,5 million Residence Home for one of the heirs Cadastral and recording tax 168 Eur Only Family Agreements Not subject to taxation Government bonds Not subject to taxation 22.
Avoiding double taxation

Domestic rule (when no international treaty exists)

When the deceased a resident of Italy, taxes are levied on worldwide assets. Article 26 of the Inheritance Tax Act provides that Italy will recognize a tax credit for inheritance taxes paid abroad, in the country where the assets are located, up to the amount of the Italian tax proportionally charged on those assets.

Internationl Conventions

Italy has a very limited network of seven inheritance tax treaties)

International conventions on inheritance

Countries with inheritance tax treaty with Italy

Denmark

France

Greece

Israel

Sweden

United Kingdom

USA

Main Treaty provisions (Italy /UK)

Italy/UK Convention of 15 February 1966 (copy in the materials)

It does not deal directly with the issue of which country may levy inheritance taxes and provides rules

to identify domicile of deceased in case of conflicting provisions of UK and Italian law

to identify the situs of properties subject to inheritance when deceased is domiciled in Italy or UK

to avoid double taxation

It applies only to taxes applicable to the inheritance itself, and not to the transfer taxes levied when receiving an asset because of inheritance

Determining Domicile (Italy/UK)

Article 2 of the convention dictates the relevant principles.

Each country will apply its own law to determine whether the deceased was domiciled in its own territory.

Note that concept of domicile is not the same in all countries

In case of conflicting rules, the following criteria will apply, in order to determine domicile:

Permanent residence at time of death

If resident in both countries, preference is given to country with closest personal and economic connections (vital interest centre)

If vital interest centre was in both countries, or it cannot be identified, preference is given to usual living place

If leaving in both countries, citizenship will apply

Determining Situs (Italy/UK)

Article 4 of the Convention:

Real estate ……………………………….Location of real estate

Company holdings ………………………Place of incorporation

Bank deposit…………………………….. Location of bank branch

Money and other movable properties……Location of assets

Receivable ………………………………..Location of debtor

Patents…………………………………….Place of registration

Copyright…………………………………Place of exercise

Other non specified properties………….. Domicile

Situs is very important as taxation for non resident people depends on situs of property

Article 3 indicates that rules in Article 4 will not cause levy of taxation if that property would not be subject to taxation in that country under its own domestic rules on situs

Avoiding Double Taxation(Italy/UK)

Usually no taxes are levied on assets located in other country

If taxes are levied, the state will give a credit for the amount already paid in the other country, where the properties are located, however the tax credit cannot exceed the tax applied by the first country.

Use of Trust

Italy has ratified the 1985 Hague Convention on Trusts

Article 1, para. 74 and 75 of Law 296/2006 amended the consolidated tax code and regulated for the first time income tax for trusts, including non resident trusts

Tax legislation now distinguishes between

trusts with no identified beneficiaries, which are treated as commercial company (if involved in commercial activities) or as non commercial entities, if not involved in commercial activities, and

Trusts with identified beneficiaries, where the trust income is attributed, for tax reasons, directly to the beneficiaries

Use of Trust (transfer taxes)

Tax Office Circular of 6 August 2007, no. 48/E has clarified impact of new rules on transfer of assets to trust and inheritance taxes. According to the new rules, the transfer of Italian assets to a trust must be treated as a gift.

Gift taxes are same as inheritance taxes (with the consequence that when the beneficiary is a close relative (spouse or children) of the settlor, and teh beneficiaries of the trust are identified, the same deductions and benefits provided for direct gift shall apply.

No inheritance tax will be due upon death of settlor (controllare per reintestazione ai beneficiari .

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LANCASTER Mary On October 14th, 2019 peacefully in the loving care of Freckleton Lodge Nursing Home aged 95 years, formerly of Wrea Green. A much loved mother, sister, nana and great nana. 'Forever in our hearts'...
Published in The Lancashire Evening Post on 16 Oct. 2019
DEAN Brian John Christopher On September 29th, 2019 suddenly, at his home, aged 67 years and of Lytham St Annes. Dear brother of Alan and the late Carol, brother in law to Linda and Chris, uncle to Charlotte,...
Published in Lytham St Annes Express on 3 Oct. 2019
Jean Hitchen
HITCHEN Jean On August 9th, 2019 at her home in Lytham St Annes, aged 79 years surrounded by her loving family. 'Forever in our hearts and minds - will never be forgotten' Service and interment to take place at Park...
Gregson David Llewellyn Passed away peacefully at home in St. Annes on June 10th 2019 after a short illness, aged 80 years. Dearly loved husband of the late Carole, loving father of Garry and John, much loved...
Published in Blackpool Gazette on 18 June 2019
WALTON Mary Mary, aged 87, died peacefully in The Hamptons Care Centre, on Sunday May 26th. Beloved wife of the late Eric, also a dear Mother, Sister and Grandma. 'Will be sadly missed by all her family and friends'...
SAX Henry On May 29th 2019 peacefully at home in St Annes after a long illness aged 84 years. The dearly loved husband and friend of Estelle. 'Adored his many friends in St Annes' Service and cremation at Park...
HARRISON Jean On May 28th, 2019 peacefully in The Hamptons Care Centre, aged 84 years and of St Annes-on-Sea. The dearly loved mother of Mark and devoted late husband Richard. 'She was a wonderful woman, much loved...
Leslie Parsler
PARSLER Leslie John Thomas On May 15th 2019 peacefully in Victoria Hospital, aged 83 years and of St Annes-on-Sea. Beloved husband of the late Patricia, dear father of Simon and Sara, father in law of Monique,...
Published in Lytham St Annes Express on 23 May 2019
Valerie Eastham
VALERIE EASTHAM Val died peacefully in hospital on Sunday evening, 19 May. Loving wife to Kevin for 59 years. Much loved mum of Graeme, Sarah and Katharine, grandma to Joseph, Alice, Jackson, Lonnie, Felix and...
WARRILOW Stephen 29.12.1927 - 25.4.2019. Much loved by us all. Beloved husband to Amy (dec'd), Dad to Ruth, Ian and Keith. Grandad to Sarah, Stefan, Daisy, Aimee, Natalie, Jennie, Kathryn and Megan. Great Grandad to ...
Published in Lytham St Annes Express on 2 May 2019

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