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Patent US7145902 - Method for transmitting data in a telecommunications network and switch for ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA method for transferring data from a first switch to a second switch selectively by line-switching or by packet-switching as well as to a switch for carrying out the method. Data packets are thereby first transferred packet-switched through a packet-switching network to the second switch. With the presence...http://www.google.com/patents/US7145902?utm_source=gb-gplus-sharePatent US7145902 - Method for transmitting data in a telecommunications network and switch for implementing said methodAdvanced Patent SearchPublication numberUS7145902 B2Publication typeGrantApplication numberUS 11/165,280Publication dateDec 5, 2006Filing dateJun 22, 2005Priority dateOct 7, 1996Fee statusPaidAlso published asCA2265776A1, EP0929884A2, EP0929884B1, US6954453, US7483431, US20050243851, US20060239256, USRE44011, WO1998015933A2Publication number11165280, 165280, US 7145902 B2, US 7145902B2, US-B2-7145902, US7145902 B2, US7145902B2InventorsSigram Schindler, Andreas Illg, Karsten L�dtke, Frank PaetschOriginal AssigneeTeles Ag Informations-TechnologienExport CitationBiBTeX, EndNote, RefManPatent Citations (49), Non-Patent Citations (69), Referenced by (7), Classifications (58), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetMethod for transmitting data in a telecommunications network and switch for implementing said methodUS 7145902 B2Abstract A method for transferring data from a first switch to a second switch selectively by line-switching or by packet-switching as well as to a switch for carrying out the method. Data packets are thereby first transferred packet-switched through a packet-switching network to the second switch. With the presence of a corresponding control signal a line-switching connection is established from the first switch to the second switch and the data are then transferred through this connection.
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improving data throughput of a TCP/IP Network connection with slow return channelEP0848527A1Oct 28, 1997Jun 17, 1998AT&T Corp.Method of transferring connection management information in world wide web requests and responsesEP0868060A1Mar 24, 1998Sep 30, 1998Lucent Technologies Inc.A communication controllerEP0884860A2Jun 10, 1998Dec 16, 1998Nippon Telegraph And Telephone CorporationChannel allocation method for a satellite communication systemEP0929884B1Oct 7, 1997Oct 27, 1999Teles AG InformationstechnologienMethod for transmitting data in a telecommunications network and switch for implementing said methodGB2283154A Title not availableJPH03175855A Title not availableJPH03235555A Title not availableJPH05268296A Title not availableJPH06311183A Title not availableJPH07154426A Title not availableJPS6449456A Title not availableJPS57159153A Title not availableJPS62188451A Title not availableJPS62189823A Title not availableWO1990012466A1Dec 28, 1989Oct 18, 1990Bell Communications ResA technique for dynamically changing an isdn connection during a host sessionWO1995025407A1Mar 16, 1995Sep 21, 1995Sierra Wireless IncModem for packet and circuit switched communicationWO1995031060A1Mar 27, 1995Nov 16, 1995Motorola IncMethod for transmitting data packets based on message typeWO1996021184A1Dec 29, 1995Jul 11, 1996Jones International LtdMethod and system for two-way data transmission with secondary one-way circuitWO1996028947A1Mar 8, 1996Sep 19, 1996Janne JormalainenMultimode universal mobile telecommunications systemWO1997007625A1Jul 10, 1996Feb 27, 1997Northern Telecom LtdAn improved access to telecommunications networks in multi-service environment* Cited by examinerNon-Patent CitationsReference1"Cisco Expands ISDN Router Solutions with Introduction of Low-Cost ISDN Router Series for Enterprise Telecommuters" Cisco Systems, Nov. 1995.2"Delivery System Architecture and Interfaces" Digital Audio-Visual Council(DAVIC), 1.2 Specification Part 4 Genf, 1997.3"Einwahlknoten [dial-in node]," Wikipedia, German Version, de.wikipedia.org, Dec. 21, 2005, 1 page, Appendix NK 27 to Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Mar. 16, 2006, from Bardehle (Cisco Attorneys), Munich, Germany.4"Installation and ISDN Configuration Guide NetWare MultiProtocol Router for ISDN 3.1" Jun. 1996.5"Lexikon der Informatik und Daten-verarbeitung," 2nd Edition, Hans-Jochen Schneider, Oldenbourg. Munich, Germany(1986) pp. 149-151, 338-339, 418-419, 482-483 (With English translation, "Dictionary of Computer Science and Data Processing").6"Lucent Technologies announces Internet telephony servers to put voice, fax and voice mail on the Internet" Lucent Technologies, Sep. 17, 1996.7"Point of Presence," Wikipedia, English Version, en.wikipedia.org, May 9, 2006, 1 page.8"Point of Presence," Wikipedia, German Version, de.wikipedia.org, Jan. 5, 2006, 1 page, Appendix NK 26 to Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Mar. 16, 2006, from Bardehle (Cisco Attorneys), Munich, Germany.9"Support of Packet Mode Terminal Equipment by an ISDN," ITU-T Recommendation X.31, 67 pages, Nov. 1995, International Telecommunication Union, Geneva, Switzerland.10"Vocaltec Introduces the Internet Phone Telephony Gateway Linking Traditional and Internet Telephone Networks" VocalTec, Mar. 8, 1996.11"Vocaltec Links Phones to Web" Aug. 2, 1996.12"Zugang zu X.25-Netzen �ber Euro-ISDN mittels X.31," HST-ISDN for PC/LAN, 120 pages, Dec. 1995, HST GmbH, Bremerhaven, Germany.13Babbage, R. et al., "Internet Phone-Changing the Telephony Paradigm?", BT Technology Journal, vol. 15, No. 12, Apr. 1997, pp. 145-157.14Blumenhofer, Lars, "Der sichere Einstieg in die Datenfern�bertragung" Markt& Technik Verlag AG M�nchen, Germany 1991, pp. 80-91.15Brij Bhushan and Holger Opderbeck "The Evolution of Data Switching for PBX's" IEEE Journal on Selected Areas in Communications, pp. 569-573, vol. sac-3, No. 4 Jul. 1985.16Chen and Baras "Optimal Routing in Mixed Media Networks with Integrated Voice and Data Traffic" GLOBECOM '92, IEEE Global Telecommunications Conference pp. 335-339, vol. 1 of 3 vol. Dec. 1992.17Christina J. Jenny and Karl Kummerle "Distributed Processing Within an Integrated Circuit/Packet-Switching Node" IEEE Transactions on Communications, pp. 1088-1101, vol. com-24, No. 10 Oct. 1976.18Cisco Systems, Inc. v. Teles AG Informationstechnologien Civil Action No. 1:05CV02048 (RBW) U.S. District Court for the District of Columbia, Plaintiff's Original Complaint and Request for Declaratory Judgment with Proposed Order for Service by Publication (Oct. 18, 2005).19Cisco Systems, Inc., and Quintum Technologies, Inc., v. Teles AG, Informationstechnologien, Federal Patents Court, Minutes, Munich, Germany, Apr. 5, 2006 (German document, 2 pages, and English translation, 1 page).20Cisco Systems, Inc., v Teles Ag Informationstechnologien v. Cisco Systems, Inc., Civil Action No. 1:05-CV-02048 (RBW) U.S. District Court for the District of Columbia, Plaintiff CISCO Systems Inc.'s Reply to Defendant TELES AG Informationstechnologien's Counterclaim, Mar. 20, 2006.21Cisco Systems, Inc., v. Teles Ag Informationstechnologien v. Cisco Systems, Inc., Civil Action No. 1:05-CV-02048 (RBW) U.S. District Court for the District of Columbia, Answer and Counterclaim of Teles AG Informationstechnologien to Cisco Systems, Inc.'s Original Complaint and Request for Declaratory Judgment (Feb. 28, 2006).22Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Mar. 16, 2006, from Bardehle (Cisco Attorneys), Munich, Germany (English translation, 42 pages).23Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Mar. 29, 2006, from Maikowski & Ninnemann (TELES Patent Attorneys), Munich, Germany (German document, 15 pages, and English translation, 12 pages).24Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Mar. 30, 2006, from Maikowski & Ninnemann (TELES Patent Attorneys), Munich, Germany (German document, 9 pages, and English translation, 9 pages).25Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Nov. 30, 2004, from Bardehle (Cisco Attorneys), Munich, Germany (English translation, 33 pages).26Cisco v. Teles-Nullity Action against German Patent DE 19645368, Translation of Letter to Federal Patent Court dated Aug. 8, 2005.27Claude Wacker "Interconnection of LANs using ISDN" Computer Networks and ISDN Systems 23, pp. 203-208, May 1991.28David Skov and Nicolas Raguideau "WebIN-An Architecture for Fast Deployment of IN-based Personal Services" IEEE, 1996.29Draft ITU-T Recommendation H.323, "Visual Telephone Systems and Equipment for Local Area Networks Which Provide a Non Guaranteed Quality of Service," ITU-T Study Group 15, International Telecommunications Union, Geneva, Switzerland, May 28, 1996 (Final master version, and file h323wht8.doc showing changes to the previous version).30Draft Recommendation H.323: Visual Telephone Systems and Equipment For Local Area Networks Which Provide a Non-Guaranteed Quality of Service, International Telecommunication Union, May 28, 1996, 82 pages.31English translation of "Zugang zu X.25-Netzen uber Euro-ISDN mittels X.31, Dec. 1995, HST GmbH, Bremerhaven, Germany" (Access to X.25 Networks via Euro ISDN by means of X.31), 45 pages.32English Translation of Cisco v. Teles, Nullity action against European Patent EP 0929884, Decision of the Federal Patent Court dated Apr. 5th, 2006, 27 pages.33English Translation of Cisco v. Teles, Nullity action against German Patent DE 19645368, Decision of the Federal Patent Court dated Apr. 5th, 2006, 25 pages.34English translation of pp. 89 to 100 (DATEX-P: Gateway to the Data World-How it Works and What it Costs) of Spindler, Wolfgang, "Das Mailbox Jahrbuch '86," Eichborn Verlag, Frankfurt am Main, Germany, 1986 (12 pages of English translation).35English translation of Teles German Patent DE 19645368 C2 (Method and Communications Device for Transmitting Data in a Telecommunications Network), 34 pages.36English translation of Teles v. AVM, Case No. 70332/04, Decision of "Landgericht" (German District Court) Manheim, 7thCivil Chamber, Mar. 11, 2005, 32 pages.37English translation of Teles v. Cisco, Case No. 70340/04, letter from Dr. Klaus Brocker, (Attorney for Teles) to the Mannheim District Court, May 14, 2006, 21 pages.38English translation of Teles v. IP Telekom & Quintum, Case No. 70297/04, Decision of "Landgericht" (German District Court) Manheim, 7thCivil Chamber, Nov. 11, 2005, 30 pages.39English translation of Teles v. Nokia, German Infringement Action, letter from Reimann Osterrieth (Attorneys for Nokia) to the Mannheim District Court in answer to the Teles Complaint, Jun. 29, 2006, 16 pages.40English version: Focus On: Office Communication-The Integrated Office, LAN and Telecommunication Growing Together LANLine, Jul. 1995-(German version) "Lan and TK-Funktionen wachsen zusammen" Schwerpunkt:Burokommunikation, LanLine, Jul. 1995, pp. 110-113.41English version: Network Technology-Servers are turning into a Telecommunication System-Telephony on the Novell Network, LANLine, Feb. 1995-(German version) "Telefonieren auf dem Novell-Netz," Netzwerktechnik, LanLine, Feb. 1995, pp. 44-48.42Gino J. Coviello and Robert E. Lyons "Conceptual Approaches to Switching in Future Military Networks" IEEE Transactions on Communications, pp. 1491-1499, vol. com-28, No. 9 Sep. 1980.43Hansj�rg Troebner, "Presentation of Innovations in ISDN & Telecommunications," HST High Soft Tech, 28 pages, Mar. 6, 1996, HST GmbH, Bremerhaven, Germany.44Hisayoshi Inamori "Performance Evaluation Of Mutual Overflow Routing for Hierarchical Packet-Switching Networks" Electronics and Communications in Japan, pp. 111-122, Part 1, vol. 71, No. 6 1988.45IDB-64/2, "ISDN Dial Backup, " Manual-Deutch Version, Software Release 4.11, Controlware Communications Systems, Dietzenbach, Germany, Mar. 1996 (With English translation).46List of ITU I-Series: Integrated services digital network, 1 page, Appendix NK 20 to Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Mar. 16, 2006, from Bardehle (Cisco Attorneys), Munich, Germany.47List of ITU-T Recommendations, 1 page, Appendix NK 19 to Cisco v. Teles, Nullity action against German part of EP-Patent 0 929 884, letter to Federal Patent Court dated Mar. 16, 2006, from Bardehle (Cisco Attorneys), Munich, Germany.48Low, C. et al., "WEB-In-An Architecture for Fast Deployment of In-Based Personal Services", Workshop Record, Intelligent Network, Freedom and Flexibility: Realising the Promise of Intelligent Network Services, Apr. 21, 1996, pp. 1-12.49Manu Malek "Integrated Voice and Data Communications Overview" IEEE Communications Magazine, pp. 5-15, vol. 26, No. 6, Jun. 1988.50Manual for IDB-64/2 "ISDN Dial Backup".51Marco Listatni and Francesco Villani,"An X.25-compatible protocol for packet voice communications," Computer Communications, pp. 23-31, vol. 6, No. 1, Feb. 1983, Butterworth & Co., Ltd.52Mark J. Karol and Michael G. Hluchyj "Using A Packet Switch For Circuit-Switched Traffic: A Queueing System with Periodic Input Traffic" IEEE Transactions on Communications, pp. 623-625, vol. 37, No. 6, Jun. 1989.53Patent Abstracts of Japan, Pub. No. 06311183A, Nov. 4, 1994, one page.54Peter Schulthess, Konrad Froitzheim and Alfred Lupper "Relisierung von LAN-Diensten uber TK-Anlagen" ntz, Bd. 45 (1992) Heft 12 pp. 970-976 (With English Translation-"Providing LAN Services using telecommunication systems").55R. Babbage, I. Moffat, A. O'Neill and S. Sivaraj "Internet phone-changing the telephony paradigm", BT Technol 1, pp. 145-157 vol. 5 No. 2, Apr. 1997.56Spindler, Wolfgang, "Das Mailbox Jahrbuch '86" Eichborn Verlag, Frankfurt am Main, Germany 1986, pp. 1-127.57Stein, Erich, "Taschenbuch Rechnernetze und Internet" Fachbuchverlag Leipzig im Carl Hanser Verlag, pp. 22-27.58Stuart J. Yuill and Raymond L. Pickholtz "Performance Modeling for Packet Networks with Satellite Overflow" IEEE Transactions On Communications, pp. 808-815, vol. com-29, No. 6, Jun. 1981.59Tanenbaum, Andrew S., "Computernetzwerke" PEARSON Studium, Munich, Germany, pp. 54-59.60Taxi System (Manual)-Controlware GmbH-Manual Version 2.0; Dec. 1995.61Teles v. Cisco,, Case No. 70340/04, Decision of "Landgericht" (German District Court) Mannheim, 7th, Civil Chamber, Jun. 9, 2006, 24 pages.62Teles vs. Cisco Systems (German Infringement action) Translation of letter to District Court of Mannheim from Herbst Sendler (TELES) dated Jan. 18, 2006.63Tohru Kohashi, et al., "Integrated-Circuit and Packet-Switching Applications to a Loop System for Local Area Networks" IEEE Journal on Selected Areas in Communications, pp. 574-583, vol. sac-3, No. 4, Jul. 1985.64Wilfred K�tz, "Das LAN wird zur Telefonanlage," ntz, Heft 4 (1995) pp. 45-47 (with English Translation: "The LAN becomes a telephone system").65William Stallings, "ISDN and Broadband ISDN with Frame Relay and ATM", Prentice Hall-Third Edition , p. 108, 1995.66William Stallings, "ISDN and Broadband ISDN with Frame Relay and ATM", Prentice Hall-Third Edition-p. 108.67Y. Nakamura, et al., On a Hybrid Network System of Circuit Switching and Packet Switching, The Transactions of the IECE of Japan, vol. E 65, No. 6, Jun. 1982, pp. 679, 680-686 with partial English translation (Abstract).68Yatsuka Nakamura and Akishige Noda, "On a Hybrid Network System of Circuit Switching and Packet Switching" The Transactions of the IECE of Japan, pp. 678-687 vol. E 65, No. 6 Abstracts.69Zusammenfassung der Nichtigkeitsklageschrift vom Nov. 30, 2004 gegen den deutschen Teil des europ�ischen IntraStar-Patents, (8 pages).Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7346708 *May 19, 2004Mar 18, 2008Nec CorporationAccess point high-speed connecting method using presence serviceUS7936751 *Jan 26, 2009May 3, 2011Sigram Schindler Beteiligungsgesellschaft MbhMethod for transmitting data in a telecommunications network and switch for implementing said methodUS8149802 *Nov 5, 2007Apr 3, 2012At&T Intellectual Property I, LpWireless broadband serviceUS8532137 *Mar 26, 2004Sep 10, 2013At&T Intellectual Property Ii, L.P.Network architecture for a packet aware transport networkUS20080112379 *Nov 5, 2007May 15, 2008At&T Bls Intellectual Property, Inc.Wireless Broadband ServiceUSRE44011 *Jan 26, 2011Feb 19, 2013Sigram Schindler Beteiligungsgesellschaft MbhMethod for transmitting data in a telecommunications network and switch for implementing said methodWO2012022612A1Aug 2, 2011Feb 23, 2012Sigram Schindler Beteiligungsgesellschaft MbhThe fstp expert system* Cited by examinerClassifications U.S. Classification370/352, 370/395.2, 370/401, 370/465, 379/93.01International ClassificationH04L12/54, H04L12/725, H04L12/701, H04Q3/00, H04L12/64, H04M7/00, H04J3/16, H04Q11/04, H04M3/42, H04L12/66, H04L29/06, H04L12/28Cooperative ClassificationH04L69/18, H04M7/0057, H04L41/12, H04L41/5009, H04M7/006, H04L2012/6427, H04Q2213/13292, H04Q2213/13389, H04M3/4228, H04Q2213/13196, H04L2012/6475, H04Q2213/13031, H04Q2213/13175, H04Q2213/13209, H04L12/6418, H04Q2213/13298, H04L2012/6443, H04Q3/002, H04L29/06, H04L12/66, H04L45/30, H04L12/5692, H04L45/00, H04L2012/6472, H04Q2213/13174, H04L41/5025, H04Q11/0428European ClassificationH04L41/12, H04L12/66, H04L41/50B2, H04L45/30, H04L12/56F1, H04L41/50A2, H04L45/00, H04Q3/00D1, H04M3/42N, H04L29/06, H04Q11/04S, H04M7/00M, H04L12/64B, H04M7/00D18Legal EventsDateCodeEventDescriptionMay 19, 2014FPAYFee paymentYear of fee payment: 8Mar 5, 2010FPAYFee paymentYear of fee payment: 4Aug 6, 2009ASAssignmentOwner name: SIGRAM SCHINDLER BETEILIGUNGSGESELLSCHAFT MBH, GERFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TELES AG INFORMATIONSTECHNOLOGIEN;REEL/FRAME:023064/0490Effective date: 20090731Oct 30, 2007RRRequest for reexamination filedEffective date: 20070907Jan 23, 2007CCCertificate of correctionAug 9, 2005ASAssignmentOwner name: TELES AG INFORMATIONSTECHNOLOGIEN, GERMANYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCHINDLER, SIGRAM;ILLG, ANDREAS;LUDTKE, KARSTEN;AND OTHERS;REEL/FRAME:016371/0063Effective date: 19990317RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


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Frank sinatra by Silvia Nascetti 720 views
Las mejore canciones y letras de Frank Sinatra.
Gracias a todos por las visitas. Un cordial saludo.
1. Cada diapositiva, un tema con su letra correspondienteCada diapositiva, un tema con su letra correspondienteFrank SinatraMomentos musicales (1)Momentos musicales (1)
2. Fly me to the MoonFly me to the moon andLet me play amoung the starsLet me see what spring is likeOn jupiter and marsIn other words, hold my handIn other words, baby kiss meFill my heart with song andLet me sing for ever moreYou are all I long forAll I worship and adoreIn other words, please be trueIn other words, Im in love with youFill my heart with song andLet me sing for ever moreYou are all I long forAll I worship and adoreIn other words, please be trueIn other wordsIn other words,I, I love, I love you
3. As time goes byYou must remember thisA kiss is still a kissA sigh is just a sighThe fundamental things applyAs time goes byAnd when two lovers wooThey still say ,"I love you"On that you can relyNo matter what the future bringsAs time goes byMoonlight and love songsNever out of dateHearts full of passionJealousy and hateWoman needs manAnd man must have his mateThat no one can denyIts still the same old storyA fight for love and gloryA case of do or dieThe world will always welcome loversAs time goes byIts still the same old storyA fight for love and gloryA case of do or dieThe world will always welcome loversAs time goes by
4. Beguin the BeguineWhen they begin the beguineIt brings back the sound of music so tenderIt brings back a night of tropical splendorIt brings back a memory ever greenIm with you once more under the starsAnd down by the shore an orchestras playingEven the palms seem to be swayingWhen they begin the beguineTo live it again is past all endeavorExcept when that tune clutches my heartAnd there we are swearing to love foreverAnd promising never, never to partWhat moments divine, what rapture sereneTill clouds come along to disperse the joys we had tasted,And now when I hear people curse the chance that was wasted,I know but too well what they mean.So dont let them begin the beguine,Let the love that was once a fire remain an emberLet it sleep like the dead desire I only rememberWhen they begin the beguineOh yes, let them begin the beguine, make them playTill the stars that were there before return above youTill you whisper to me once more, Darling, I love youAnd we suddenly know what heaven were inWhen they begin the beguineWhen they begin the beguine
5. Cheek to CheekHeavenIm in heavenAnd my heart beats so that I can hardly speakAnd I seem to find the happiness I seekWhen were out together dancing cheek to cheekHeavenIm in heavenAnd the cares that hung around me through the weekSeem to vanish like a gamblers lucky streakWhen were out together dancing cheek to cheekOh, I love to climb a mountainAnd to reach the highest peakBut it doesnt thrill me half as much as dancing cheek to cheekOh, I love to go out fishingIn a river, or a creekBut I dont enjoy it half as much as dancing cheek to cheekDance with meI want my arm about youThat charm about you will carry me through to...HeavenIm in heavenAnd my heart beats so that I can hardly speakAnd I seem to find that happiness I seekWhen were out together swinging cheek to cheekCome on and dance with meI want my arm about youThat charm about you will carry me throughRight up to...HeavenIm in heavenAnd my heart beats so that I can hardly speakAnd I seem to find that happiness I seekWhen were out toghether dancingOut together dancingOut together dancing cheek to cheek!
6. Come fly with meCome fly with meLets fly, lets fly awayIf you can use some exotic booze theres a bar in far BombayCome fly with me lets fly, lets fly awayCome fly with me, lets float down to PeruIn Lamaland theres a one man band and hell toot his flute for youCome fly with me lets take off in the blueOnce I get you up there where the air is rarifiedWell just glide, starry eyedOnce I get you up there Ill be holding you so nearYou may hear all the angels cheer becuase were togetherWeather-wise its such a lovely dayJust say the words and well beat the birds down to Akapuko bayIts perfect for a flying honeymoon, they sayCome fly with me lets fly, lets fly awayOnce I get you up there, where the air is rarifiedWell just glide, starry eyedOnce I get you up there, Ill be holding you so very nearYou might even hear a whole gang of cheer because were togetherWeather-wise its such a cool, cool dayYou just say those words and well take out birds down to Akapuko bayIts perfect for a flying honeymoon, oooh babeCome fly with me lets fly, lets flyPack up! Lets fly awayPack a small bag...away
7. It was a very good yearWhen I was seventeenIt was a very good yearIt was a very good year for small town girlsAnd soft summer nightsWed hide from the lightsOn the village greenWhen I was seventeenWhen I was twenty-oneIt was a very good yearIt was a very good year for city girlsWho lived up the stairWith all that perfumed hairAnd it came undoneWhen I was twenty-oneWhen I was thirty-fiveIt was a very good yearIt was a very good year for blue-blooded girlsOf independent meansWed ride in limousinesTheir chauffeurs would driveWhen I was thirty-fiveBut now the days grow shortIm in the autumn of the yearAnd now I think of my life as vintage wineFrom fine old kegsFrom the brim to the dregsAnd it poured sweet and clearIt was a very good year
8. (I’ve got you) Under my skinIve got you under my skinIve got you deep in the heart of meSo deep in my heart that youre really a part of meIve got you under my skin.I try so not to give inI say to myself this affair, it never will go so wellBut why should I try to resist when baby, I know damn wellThat Ive got you under my skin.I`d sacrafice anything come what mightFor the sake of having you near,In spite of a warning voice that comes in the nightIt repeats, repeats in my earDont you know you fool, you never can winUse your mentality, wake up to reality"And each time I do, just the thought of youMakes me stop before I begin,Because Ive got you under my skin.(big-band instrumental break)I would sacrafice anything come what mightFor the sake of having you near,In spite of a warning voice that comes in the nightIt repeats, how it yells in my earDont you know you fool, ain`t no chance to winWhy not use your mentality, get up, wake up to reality"And each time I do, just the thought of youMakes me stop just before I begin,Because Ive got you under my skin.And I like you under my skin.
9. My WayAnd now the end is nearAnd so I face the final curtainMy friend, Ill say it clearIll state my case of which Im certainIve lived a life thats fullI traveled each and every highwayAnd more, much more than thisI did it my wayRegrets, Ive had a fewBut then again, too few to mentionI did what I had to doAnd saw it through without exemptionIve planned each charted courseEach careful step along the bywayAnd more, much more than thisI did it my wayYes there were times, Im sure you knewWhen I bit off more than I could chewBut through it all when there was doubtI ate it up and spit it outI faced it all and I stood tallAnd did it my wayIve loved, Ive laughed and criedIve had my fill, my share of losingAnd now as tears subsideI find it all so amusingTo think I did all thatAnd may I say, not in a shy wayOh no, oh no, not meI did it my wayFor what is a man, what has he got?If not himself, than he has naugthTo say the things he truly feelsAnd not the words of one who kneelsThe record shows, I took the blowsAnd did it my way
10. New York, New YorkStart spreading the newsIm leaving todayI want to be a part of itNew York, New YorkThese vagabond shoesAre longing to strayRight through the very heart of itNew York, New YorkI wanna wake up in a cityThat doesnt sleepAnd find Im king of the hillTop of the heapThese little town bluesAre melting a wayIll make a brand-new start of itIn old New YorkIf I can make it thereIll make it anywhereIts up to youNew York, New YorkNew York, New YorkNew York, New YorkNew York, New YorkI want to wake upIn a city that never sleepsAnd find Im a number one, top of the listKing of the hill, a number oneThese little town bluesAre melting a wayIm gonna make a brand-new start of itIn old New YorkAnd... if I can make it thereIm gonna make it anywhereIts up to youNew York, New YorkNew York
11. Night and DayLike the beat beat beat of the tom-tomWhen the jungle shadows fallLike the tick tick tock of the stately clockAs it stands against the wallLike the drip drip drip of the raindropsWhen the summer shower is throughSo a voice within me keeps repeating you, you, youNight and day, you are the oneOnly you beneath the moon or under the sunWhether near to me, or farIts no matter darling where you areI think of youNight and day, day and night, why is it soThat this longing for you follows wherever I goIn the roaring traffics boomIn the silence of my lonely roomI think of youNight and day, night and dayUnder the hide of meTheres an oh such a hungry yearning burning inside of meAnd this torment wont be throughUntil you let me spend my life making love to youDay and night, night and day
12. Singing in the rainIm singing in the rainJust singin in the rainWhat a glorious feelingIm happyagainIm laughing at cloudsSo dark up aboveThe suns in my heartAnd Imready for loveLet the stormy clouds chaseEveryone from the placeCome on with the rainIve a smile on myface I walk downthe lane Witha happy refrainJust singin singin, in the raindancing in the rainohh ia ohh ia iaIam happy againIamsinging and dancingin the rain...
13. Something StupidI know I stand in line,until you think you have the timeto spend an evening with meAnd if we go some place to danceI know that theres a chanceyou wont be leaving with meAnd afterwards we drop into a quiet little placeand have a drink or twoAnd then I go and spoil it allby saying something stupidlike :"I love you"I can see it in your eyesthat you still despise the same old linesyou heard the night beforeAnd though its just a line to youfor me its trueit never seemed so right beforeI practice everydayto find some clever lines to sayto make the meaning come trueBut then I think Ill waituntil the evening gets lateand Im alone with youThe time is rightyour perfume fills my headthe stars get redand oh, the nights so blueAnd then I go and spoil it allby saying something stupidlike: "I love you"The time is rightyour perfume fills my headthe stars get redand oh, the nights so blueAnd then I go and spoil it allby saying something stupidlike: "I love you""I love you""I love you""I love you"Con Nancy Sinatra
14. Stormy WeatherDont know whyThere’s no sun up in the skyStormy weatherSince my gal and IAint togetherKeeps raining all the timeLife is bareGloom and misery everywhereStormy weatherJust cant get my poor old self togetherIm weary all the timeThe timeSo weary all the timeWhen she went awayThe blues walked in and they metIf she stays away that old rocking chairs gonna get meAll I do is pray the Lord above will let meWalk in the sun once moreCant go onEverything I have is goneStormy weatherSince my gal and IAint togetherKeeps raining all the timeKeeps raining all the timeWhen she went awayThe blues walked in and met meIf he stays away old rocking chair will get meAll I do is pray the Lord above will let meWalk in the sun once moreCant go onEverything I had is goneStormy weatherSince my gal and IAint togetherKeeps raining all the timeThe timeKeeps raining all the time
15. Strangers in the NightStrangers in the night exchanging glancesWondering in the nightWhat were the chances wed be sharing loveBefore the night was through.Something in your eyes was so inviting,Something in your smile was so exciting,Something in my heart,Told me I must have you.Strangers in the night, two lonely peopleWe were strangers in the nightUp to the momentWhen we said our first hello.Little did we knowLove was just a glance away,A warm embracing dance away and -Ever since that night weve been together.Lovers at first sight, in love forever.It turned out so right,For strangers in the night.Love was just a glance away,A warm embracing dance away and -Ever since that night weve been together.Lovers at first sight, in love forever.It turned out so right,For strangers in the night.
16. YesterdayYesterday,All my troubles seemed so far away,Now it looks as thoughtheyre here to stay Oh I believe inyesterday Suddenly, Imnot half the man I used to be Theres a shadowhanging over me Oh yesterdaycame suddenly Why she hadto go I dontknow, she wouldnt say I saidsomething wrongnow Im long for yesterdayYesterday,Love was such an easy game toplayNow I need a place to hide awayOh I believe in yesterdayWhy she had to goI dont know, she wouldnt sayI said something wrongnow Im long foryesterday Yesterday,Love was such aneasy game to play Now I need aplace to hide away Oh I believe inyesterday
17. Frank SinatraLMG (Nov.LMG (Nov.2010)2010)

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Patent US6455364 - Semiconductor device and method for fabricating the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor...http://www.google.com/patents/US6455364?utm_source=gb-gplus-sharePatent US6455364 - Semiconductor device and method for fabricating the sameAdvanced Patent SearchPublication numberUS6455364 B1Publication typeGrantApplication numberUS 09/526,686Publication dateSep 24, 2002Filing dateMar 15, 2000Priority dateMar 15, 1999Fee statusPaidAlso published asCN1215569C, CN1267916A, DE60040812D1, EP1037284A2, EP1037284A3, EP1710842A1, EP1710842B1, US6713790, US20020197809Publication number09526686, 526686, US 6455364 B1, US 6455364B1, US-B1-6455364, US6455364 B1, US6455364B1InventorsAkira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo IchikawaOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Non-Patent Citations (2), Referenced by (33), Classifications (22), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method for fabricating the sameUS 6455364 B1Abstract In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
What is claimed is: 1. A method for fabricating a semiconductor device serving as a bipolar transistor having an emitter layer, a base layer, and a collector layer formed at an active region of a semiconductor substrate, the method comprising the steps of:
(a) forming device isolation regions in portions of the semiconductor substrate for surrounding the active region; (b) forming a collector layer of a first conductivity type in a region of the semiconductor substrate sandwiched by the device isolation regions; (c) after the steps (a) and (b), depositing a first insulating layer on the semiconductor substrate, thereafter removing a portion of the first insulating layer and forming a collector opening whose periphery is located on the device isolation regions so that the range of the collector opening covers the collector layer and portions of the device isolation regions; and (d) forming a semiconductor layer of a second conductivity type on the portion of the semiconductor substrate located inside the collector opening for defining at least an internal base and an external base surrounding the internal base. 2. The method of claim 1, further comprising the steps of:
(e) after the step (d), forming a second insulating layer on the semiconductor substrate, and then forming base junction openings by removing portions of the second insulating layer ranging from positions located above peripheries of the semiconductor layer to positions located above inner ends of the device isolation regions while remaining a portion of the second insulating layer located above a center of the semiconductor layer, by etching using a patterned photoresist; and (f) forming junction leak prevention layers by introducing impurities of the second conductivity type in regions of the semiconductor substrate located under the base junction openings. 3. The method of claim 1, further comprising the steps of:
(e) after the step (d), forming a second insulating layer on the semiconductor substrate, and then forming base junction openings by removing portions of the second insulating layer located above peripheries of the semiconductor layer while remaining a portion of the second insulating layer located above a center of the semiconductor layer, by etching using a patterned photoresist; (f) depositing a first conductor layer and a third insulating layer on the semiconductor substrate, and then forming a base opening through the first conductor layer and the third insulating layer to reach a portion of the second insulating layer left on the internal base; (g) forming a fourth insulating layer covering a side face of the first conductor layer exposed in the base opening; (h) removing a portion of the second insulating layer left on the internal base of the semiconductor layer exposed inside the base opening to expose a portion of the semiconductor layer on the bottom of the base opening; (i) after the step (h), forming a second conductor layer burying the base opening; and (j) after the step (i), removing side portions of the first conductor layer and the third insulating layer by etching to expose a portion of the semiconductor substrate to be used as a collector drawing layer. 4. A method for fabricating a semiconductor device including a bipolar transistor having at least an emitter layer, a base layer, and a collector layer and MISFET having at least a gate insulating film, a gate electrode, and source/drain regions, formed on a semiconductor substrate, the method comprising the steps of:
(a) forming the collector layer of the bipolar transistor in a bipolar transistor formation region and forming the gate insulating film, the gate electrode, and the source/drain regions of the MISFET in a MISFET formation region; (b) depositing a first insulating layer and a reductive film on the semiconductor substrate for protecting a region other than the bipolar transistor formation region, and then removing a portion of the first insulating layer and the reductive film located above the collector layer in the bipolar transistor formation region to form a collector opening; and (c) growing by epitaxy a semiconductor layer of a second conductivity type on a portion of the semiconductor substrate located inside the collector opening and the reductive film for forming at least an internal base and an external base surrounding the internal base. 5. The method of claim 4, wherein in the step (c) the semiconductor layer is formed so as to include at least one of Si1−xGex (0≦x≦1), Si1−x−yGexCy (0≦x+y≦1), and Si1−yCy (0≦y≦1).
(d) after the step (c), forming a second insulating layer on the semiconductor substrate, and then removing portions of the second insulating layer located above peripheries of the semiconductor layer while remaining a portion of the second insulating layer located above a center of the semiconductor layer to form base junction openings; (e) depositing a first conductor layer and a third insulating layer on the semiconductor substrate, and then forming a base opening through portions of the first conductor layer and the third insulating layer to reach a portion of the second insulating layer left on the internal base; (f) forming an inter-electrode insulating layer covering a side face of the first conductor layer exposed in the base opening; (g) removing a portion of the second insulating layer left on the internal base of the semiconductor layer exposed in the base opening by etching to expose a portion of the semiconductor layer on the bottom of the base opening; (h) forming a second conductor layer to be used as an emitter drawing electrode burying the base opening; (i) removing part of the third insulating layer, the first conductor layer, the semiconductor layer, and the reductive film in the bipolar transistor formation region, and the entire of the third insulating layer, the first conductor layer, the semiconductor layer, and the reductive film in the MISFET formation region; (j) after the step (i), depositing an insulating film on the semiconductor substrate and etching back the insulating film to form sidewalls on side faces of the first conductor layer, the semiconductor layer, and the reductive film in the bipolar transistor formation region and on the side faces of the gate electrode in the MISFET formation region; and (k) removing the first insulating layer to expose portions of the semiconductor substrate to be used as a collector drawing layer in the bipolar transistor formation region and the source/drain regions in the MISFET formation region. 8. The method of claim 7, wherein the steps (j) and (k) are performed simultaneously.
9. The method of claim 4, wherein at least one of the insulating layers comprises a silicon oxide film formed at a temperature of 700� C. or lower.
(d) after the step (c), forming a second insulating layer on the semiconductor substrate, and then removing portions of the second insulating layer located above peripheries of the semiconductor layer while remaining a portion of the second insulating layer located above a center of the semiconductor layer to form base junction openings; (e) depositing a first conductor layer and a third insulating layer on the semiconductor substrate, and then forming a base opening through portions of the first conductor layer and the third insulating layer to reach a portion of the second insulating layer left on the internal base; (f) forming an inter-electrode insulating layer covering a side face of the first conductor layer exposed in the base opening; (g) removing a portion of the second insulating layer left on the internal base of the semiconductor layer exposed in the base opening by etching to expose a portion of the semiconductor layer on the bottom of the base opening; (h) after the step (g), forming a second conductor layer to be used as an emitter drawing electrode burying the base opening; and (i) diffusing impurities of a first conductivity type to part of the Si layer from the second conductor layer to form an emitter layer in the Si layer. 11. The method of claim 10, further comprising the steps of:
(j) removing part of the third insulating layer, the first conductor layer, the semiconductor layer, and the reductive film in the bipolar transistor formation region, and the entire of the third insulating layer, the first conductor layer, the semiconductor layer, and the reductive film in the MISFET formation region; (k) after the step (j), depositing an insulating film on the semiconductor substrate and etching back the insulating film to form sidewalls on side faces of the first conductor layer, the semiconductor layer, and the reductive film in the bipolar transistor formation region and on the side faces of the gate electrode in the MISFET formation region; and (l) removing the first insulating layer to expose portions of the semiconductor substrate to be used as a collector drawing layer in the bipolar transistor formation region and the source/drain regions in the MISFET formation region. 12. The method of claim 11, wherein the steps (k) and (1) are performed simultaneously.
FIG. 12 is a cross-sectional view of HBT formed in the procedure of forming first MOSFET and thereafter HBT in the conventional fabrication process of SiGe-BiCMOS devices. Referring to FIG. 12, the upper portion of Si (001) substrate 500 constitutes a retrograde well 501 having a depth of 1 μm that contains n-type impurities such as phosphorous introduced therein by epitaxial growth, ion implantation, or the like. The density of the n-type impurities in the surface portion of the Si substrate 500 is adjusted to about 1�1017 atoms�cm−3. As device isolation, there are provided a shallow trench 503 filled with silicon oxide and a deep trench 504 composed of an undoped polysilicon film 505 and a silicon oxide film 506 surrounding the undoped polysilicon film 505. The depth of the shallow trench 503 is about 0.35 μm and that of the deep trench 504 is about 2 μm.
The Si1−xGex layer is mostly doped with p-type impurities such as boron (B) at about 2�1018 atoms�cm−3, while the Si layer is doped by diffusion of n-type impurities such as phosphorous (P) from the n+ polysilicon layer 529 in the density distribution between 1�1020 atoms cm−3 and 1�1017 atoms�cm−3. The Si layer is formed in succession on the Si1−xGex layer so that the lower surface of the overlying n+ polysilicon layer 529 be located farther from the pn junction so as to prevent recombination of carriers from being promoted by a number of interface states and defects existing in the n+ polysilicon layer 529.
In the step shown in FIG. 13(a), a Si single-crystalline layer is grown by epitaxy while being doped with n-type impurities, or grown by epitaxy followed by ion implantation, to form the n-type retrograde well 501 having a depth of about 1 μm in the upper portion of the Si (001) substrate 500. Alternatively, the retrograde well 501 may be formed by merely implanting ions in part of the Si substrate 500 without involving epitaxial growth. In either case, it is necessary to adjust the density of the n-type impurities to about 1�1017 atoms cm−3 in the surface region of the Si substrate 500 that is to be the collector layer of the HBT.
In the step shown in FIG. 13(b), the first oxide film 508 is deposited on the wafer to a thickness of about 30 nm by chemical vapor deposition (CVD) using tetraethoxysilane (TEOS) and oxygen at a temperature of 680� C. The first oxide film 508 is then wet-etched with hydrofluoric acid or the like to form the collector opening 510 having the width W3 that is narrower than the width W2 of the active region for the reason described above. The portion of the surface of the Si substrate 500 exposed inside the collector opening 510 is treated with a mixture of ammonium hydroxide and hydro peroxide to form a protection oxide film having a thickness of about 1 nm on the exposed portion. The resultant wafer in this state is placed in a chamber of a UHV-CVD apparatus, where the wafer is heat-treated in a hydrogen atmosphere to remove the protection oxide film and then a gas of disilane (Si2H6) and germane (GeH4) containing diboran (B2H6) for doping is introduced into the chamber while heating to 550� C., to allow the Si1−xGex layer to be grown by epitaxy to a thickness of about 60 nm on the exposed surface of the Si substrate 500 inside the collector opening 510. Subsequent to the formation of the Si1−xGex layer, the supply gas to the chamber is changed to disilane to grow the Si layer having a thickness of about 10 nm by epitaxy on the Si1−xGex layer, thereby forming the Si/Si1−xGex layer 511 a . At this time, while the Si1−xGex layer doped with boron (B) is of the p-type having a boron density of about 2�1018 atoms�cm−3, the Si layer is not doped with impurities. During the formation of the Si1−xGex layer, disilane, germane, and diboran are also deposited on the surface of the first oxide film 508, which are however not crystallized but form aggregates of Si and Ge atoms as the SiGe islands 511 b. In the step shown in FIG. 14(a), the second oxide film 512 having a thickness of 30 nm is formed on the resultant wafer, and then patterned by dry etching to form the base junction openings 514. By the formation of the base junction openings 514, the peripheries of the Si/Si1−xGex layer 511 a and part of the first oxide film 508 are exposed, while the center of the Si/Si1−xGex layer 511 a is covered with the second oxide film 512. Since the SiGe islands 511 b are formed on the first oxide film 508, the surface of the second oxide film 512 deposited on the first oxide film 508 has a considerably uneven profile.
In the step shown in FIG. 14(b), the p+ polysilicon layer 515 doped with impurities at a high density of about 1�1020 atoms�cm−3 or more is deposited to a thickness of about 150 nm on the wafer by CVD. Subsequently, the third oxide film 517 is deposited to a thickness of about 100 nm on the resultant wafer. The third oxide film 517 and the p+ polysilicon layer 515 are then patterned by dry etching to form the base opening 518 at the centers thereof so as to reach the second oxide film 512. The base opening 518 is made smaller than the center portion of the second oxide film 512 so as not to overlap the base junction openings 514. Thus, in this step, the external base 516 composed of the p+ polysilicon layer 515 and the portion of the Si/Si1−xGex layer 511 a excluding the center thereof is formed. During this step, in general, the side portions of the third oxide film 517 and the p+ polysilicon layer 515 as viewed from the figure are also etched away. It should be understood that a larger area of the p+ polysilicon layer 515 is left unetched on the left side as viewed from the figure for securing a region for base contact in a later stage.
Subsequently, the following processing is performed to obtain the structure shown in FIG. 12. First, Ti is deposited to a thickness of about 40 nm on the entire surface of the resultant wafer by sputtering, and the resultant surface is subjected to RTA (rapid thermal annealing) at 675� C. for 30 seconds to form the Ti silicide layers 524 on the exposed surfaces of the n+ polysilicon layer 529, the p+ polysilicon layer 515, and the n+ collector drawing layer 507. After selective removal of the non-reacted portions of the Ti films, the resultant wafer is annealed to change the crystal structure of the Ti silicide layers 524.
SUMMARY OF THE INVENTION An object of the present invention is providing semiconductor devices, serving as a hetero bipolar transistor and a SiGe-BiCMOS device, with a reduced transistor area, reduced leak current, and improved process controllability, and methods for fabricating such semiconductor devices.
At least one of the insulating layers may comprise a silicon oxide film formed at a temperature of 700� C. or lower. This minimizes degradation of the impurity density profile of the relevant components of the semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a bipolar transistor of a semiconductor device of EMBODIMENT 1 according to the present invention.
Referring to FIG. 1, the upper portion of a Si (001) substrate 100 constitutes a retrograde well 101 having a depth of 1 μm that contains n-type impurities such as phosphorous introduced therein by epitaxial growth, ion implantation, or the like. The density of the n-type impurities in the surface portion of the Si substrate 100 is adjusted to about 1�1017 atoms�cm−3. As device isolation, there are provided a shallow trench 103 filled with silicon oxide and a deep trench 104 composed of an undoped polysilicon film 105 and a silicon oxide film 106 surrounding the undoped polysilicon film 105. The thickness of the shallow trench 103 is about 0.35 m and that of the deep trench 104 is about 2 μm.
A first oxide film 108 having a thickness of about 30 nm is provided on the Si substrate 100. A collector opening 110 is formed through the first oxide film 108. A Si/Si1−xGex layer 111 is formed on the portion of the surface of the Si substrate 100 exposed inside the collector opening 110. The Si/Si1−xGex layer 111 is composed of a p-type impurity doped Si1−xGex layer having a thickness of about 60 nm and a Si layer having a thickness of about 10 nm. The Si/Si1−xGex layer 111 exists only on the portion of the surface of the Si substrate 100 exposed inside the collector opening 110 by selective growth. The lower portion of the center of the Si/Si1−xGex layer 111 (the center corresponds to a lower region of a base opening 118 to be described later) serves as an internal base 119, while the upper portion of the center of the Si/Si1−xGex layer 111 serves as an emitter layer. The Si1−xGex layer is mostly doped with p-type impurities such as boron (B) at about 2�1018 atoms�cm−3 while the Si layer is doped by diffusion of n-type impurities such as phosphorous (P) from an n+ polysilicon layer 129 to be described later in the density distribution between 1�1020 atoms�cm−3 and 1�1017 atoms�cm−3. The Si layer is formed in succession on the Si1−xGex layer so that the lower surface of the overlying n+ polysilicon layer 129 be located farther from the pn junction so as to prevent recombination of carriers from being promoted by a number of interface states and defects existing in the n+ polysilicon layer 129.
In this embodiment, the inner ends of the shallow trenches 103 are located at positions closer to the center of the HBT than the peripheries of the collector opening 110, so that the width W2 of the active region is smaller than the width W3 of the collector opening 110. With the shallow trenches 103 being closer to each other, the entire area of the HBT can. be reduced. Meanwhile, this arrangement results in that the active region-isolation junctions Rai exist inside a carrier migration region of the HBT. This may cause problems such as generation of a defect due to stress. In order to avoid such problems, p-type junction leak prevention layers 113 are provided in the vicinity of the active region-isolation junctions Rai by implanting p-type impurities in a self-aligned manner with respect to the collector opening 110. The density of the impurities in the surface portions of the p-type junction leak prevention layers 113 is preferably about 3�1017 atoms�cm−3.
In the step shown in FIG. 2(a), an Si single-crystalline layer is grown by epitaxy while being doped with n-type impurities, or grown by epitaxy followed by high-energy ion implantation, to form the n-type retrograde well 101 having a depth of about 1 μm in the upper portion of the Si (001) substrate 100. Alternatively, the retrograde well 501 may be formed by merely implanting ions in part of the Si substrate 100 without involving epitaxial growth. In either case, the density of the n-type impurities in the surface region of the Si substrate 100 should be adjusted to about 1�1017 atoms�cm−3 so that the surface region can serve as the collector layer of the HBT.
In the step shown in FIG. 2(b), the first oxide film 108 is deposited to a thickness of about 30 nm on the wafer by CVD using tetraethoxysilane (TEOS) and oxygen at a temperature of 680� C. The first oxide film 108 is then wet-etched with hydrofluoric acid or the like to form the collector opening 110 having the width W3 that is larger than the width W2 of the active region. That is, the collector opening 110 is made wider than the active region by forming the collector opening 110 so that the active region-isolation junctions Rai (boundaries between the shallow trenches 103 and the surface portion of the Si substrate 100) are located within the range of the collector opening 110. In fact, the width of the collector opening 110 is substantially the same as that of the conventional HBT. As a result that the distance between the shallow trenches 103 is made smaller than that of the conventional HBT, the width W3 of the collector opening 110 becomes relatively larger than the width W2 of the active region. This arrangement however may cause the problem of increased base-collector leak current through interface states or lattice defects due to stress generated at the junction of different materials if no measures are taken. In order to avoid this problem, the junction leak prevention layers 113 are formed as will be described later.
The portion of the surface of the Si substrate 100 exposed inside the collector opening 110 is treated with a mixture of ammonium hydroxide and hydro peroxide to form a protection oxide film having a thickness of about 1 nm on the exposed portion. The resultant wafer in this state is placed in a chamber of a UHV-CVD apparatus, where the wafer is heat-treated in a hydrogen atmosphere to remove the protection oxide film and then a gas of disilane (Si2H6) and germane (GeH4) containing diboran (B2H6) for doping is introduced into the chamber while heating to 550� C., to allow the Si1−xGex layer to be grown by epitaxy to a thickness of about 60 nm on the exposed surface of the Si substrate 100 inside the collector opening 110. Subsequent to the formation of the Si1−xGex layer, the supply gas to the chamber is changed to disilane, to grow the Si layer having a thickness of about 10 nm by epitaxy on the Si1−xGex layer, thereby forming the Si/Si1−xGex layer 111. At this time, while the Si1−xGex layer doped with boron (B) is of the p-type having a boron density of about 2�1018 atoms�cm−3, the Si layer is not doped with impurities. As in the conventional fabrication process, during the formation of the Si1−xGex layer, Si and Ge atoms may also be deposited on the surface of the first oxide film 108 forming SiGe islands. Such formation of SiGe islands is however avoided by strictly controlling the selective growth in this embodiment.
In the step shown in FIG. 3(a), the second oxide film 112 having a thickness of 30 nm as an etch stopper is formed on the resultant wafer, and then patterned by dry etching using a resist mask Re1 formed on the second oxide film 112 to form the base junction openings 114. As a result, the center of the Si/Si1−xGex layer 111 is covered with the second oxide film 112, while the peripheries of the Si/Si1−xGex layer 111 and part of the first oxide film 108 are exposed inside the base junction openings 114. Thereafter, p-type impurities such as boron (B) are implanted using the resist mask Re1 used for the formation of the base junction openings 114, to form the junction leak prevention layers 113 having a density of the impurities of about 3�1017 atoms�cm−3 in the surface portion as the measures for minimizing the influence of stress at the active region-isolation junctions Rai.
In the step shown in FIG. 3(b), the p+ polysilicon layer 115 doped with impurities at a high density of about 1�1020 atoms�cm−3 or more is deposited to a thickness of about 150 nm and subsequently the third oxide film 117 is deposited to a thickness of about 100 nm, on the resultant wafer by CVD. The third oxide film 117 and the p+ polysilicon layer 115 are then patterned by dry etching to form the base opening 118 at the. centers thereof so as to reach the second oxide film 112. The base opening 118 is made smaller than the center portion of the second oxide film 112 so as not to overlap the base junction opening 114. Thus, in this step, the external base 116 composed of the p+ polysilicon layer 115 and the portion of the Si/Si1−xGex layer 111 excluding the center thereof is formed. In this embodiment, unlike the step of the conventional HBT fabrication process shown in FIG. 14(b), the side portions of the third oxide film 117 and the p+ polysilicon layer 115 as viewed from the figure are left unetched, so as to minimize residues attaching to etched sidewalls.
Thereafter, the following processing is performed to obtain the structure shown in FIG. 1. First, Ti is deposited to a thickness of about 40 nm on the entire surface of the resultant wafer by sputtering, and the resultant surface is subjected to RTA (rapid thermal annealing) at 675� C. for 30 seconds to form the Ti silicide layers 124 on the exposed surfaces of the n+ polysilicon layer 129, the p+ polysilicon layer 115, and the n+ collector drawing layer 107. After selective removal of non-reacted portions of the Ti films, the resultant wafer is annealed to change the crystal structure of the Ti silicide layers 124.
In this embodiment, as in EMBODIMENT 1, the Si1−xGex layer is mostly doped with p-type impurities such as boron (B) at about 2�1018 atoms�cm−3, while the Si layer is doped by diffusion of n-type impurities such as phosphorous (P) from the n+ polysilicon layer 129 in the density distribution between 1�1020 atoms�cm−3 and 1�1017 atoms�cm−3. The Si layer is formed in succession on the Si1−xGex layer so that the lower surface of the overlying n+ polysilicon layer 129 be located farther from the pn junction so as to prevent recombination of carriers from being promoted by a number of interface states and defects existing in the n+ polysilicon layer 129.
In this embodiment, as in EMBODIMENT 1, the shallow trenches 103 are formed so that the inner ends thereof are located within the range of the collector opening 110 in the HBT formation region Rbp, resulting in that the width W2 of the active region is smaller than the width W3 of the collector opening 110. With this arrangement, the entire area of the HBT can be reduced. In this embodiment, also, the p-type junction leak prevention layers 113 are formed in the vicinity of the active region-isolation junctions Rai by implanting p-type impurities in a self-aligned manner with respect to the collector opening 110. The density of impurities in the surface portions of the p-type junction leak prevention layers 113 is preferably about 3�1017 atoms�cm−3.
In the step shown in FIG. 7(a), a Si single-crystalline layer is grown by epitaxy while being doped with n-type impurities, or grown by epitaxy followed by high-energy ion implantation, to form the n- type retrograde well 101 having a depth of about 1 μm in the upper portion of the Si (001) substrate 100 in the HBT formation region Rbp. Alternatively, the retrograde well 101 may be formed by merely implanting ions in part of the Si substrate 100 without involving the epitaxial growth. In either case, the density of the n-type impurities in the surface region of the Si substrate 100 in the HBT formation region Rbp should be adjusted to about 1�1017 atoms�cm−3 so that the surface region can serve as the collector layer of the HBT. In the MISFET formation region Rms, the retrograde well 151 is formed by ion implantation. The retrograde well 151 is a p-type well if a nMISFET is to be formed, while it is an n-type well if a pMISFET is to be formed.
In the step shown in FIG. 8(a), the first oxide film 108 having a thickness of about 30 nm is formed by CVD using tetraethoxysilane (TEOS) and oxygen at a temperature of 680� C. , and sequentially the polysilicon layer 109 having a thickness of about 50 nm is formed. Thereafter, the polysilicon layer 109 is patterned by dry etching or the like, and then the first oxide film 108 is wet-etched with hydrofluoric acid or the like, to form the collector opening 110 having the width W3 that is larger than the width W2 of the active region through the first oxide film 108 and the polysilicon layer 109 in the HBT formation region Rbp. That is, the collector opening 110 is made wider than the active region by forming the collector opening 110 so that the active region-isolation junctions Rai (boundaries between the shallow trenches 103 and the surface portion of the Si substrate 100) are located within the range of the collector opening 110. In fact, the width of the collector opening 110 is substantially the same as that of the conventional HBT. As a result that the distance between the shallow trenches 103 is made smaller than that of the conventional HBT, the width W3 of the collector opening 110 becomes relatively larger than the width W2 of the active region. This arrangement however may cause the problem of increased base-collector leak current due to stress generated at the junction of different materials if no measures are taken. In order to avoid this problem, the junction leak prevention layers 113 are formed as will be described later.
In the step shown in FIG. 8(b), the portion of the surface of the Si substrate 100 exposed inside the collector opening 110 is treated with a mixture of ammonium hydroxide and hydro peroxide to form a protection oxide film having a thickness of about 1 nm on the exposed portion. The resultant wafer in this state is placed in a chamber of a UHV-CVD apparatus, where the wafer is heat-treated in a hydrogen atmosphere to remove the protection oxide film and then a gas of disilane (Si2H6) and germane (GeH4) containing diboran (B2H6) for doping is introduced into the chamber while heating to 550� C., to allow the Si1−xGex layer to be grown by epitaxy to a thickness of about 60 nm over the area covering the exposed surface of the Si substrate 100 inside the collector opening 110 and the polysilicon layer 109. Subse-opening 110 and the polysilicon layer 109. Subsequent to the formation of the Si1−xGex layer, the supply gas to the chamber is changed to disilane, to grow the Si layer having a thickness of about 10 nm by epitaxy on the Si1−xGex layer, thereby forming the Si /Si1−xGex layer 111. In the MISFET formation region Rms, also, the Si/Si1−xGex layer 111 is formed on the polysilicon layer 109. At this time, while the Si1−xGex layer doped with boron (B) is of the p-type having a boron density of about 2�1018 atoms�cm−3, the Si layer is not doped with impurities.
In the step shown in FIG. 9(a), the second oxide film 112 having a thickness of 30 nm as an etch stopper is formed on the resultant wafer, and then patterned by dry etching using a resist mask Re2 formed on the second oxide film 112 to form the base junction openings 114 in the HBT formation region Rbp. As a result, the center of the Si/Si1−xGex layer 111 is covered with the second oxide film 112, while the portions of the Si/Si1−xGex layer 111 are exposed inside the base junction opening 114. Thereafter, p-type impurities such as boron (B) are implanted using the resist mask Re2 used for the formation of the base junction openings 114, to form the junction leak prevention layers 113 having a density of the impurities of about 3�1017 atoms�cm−3 in the surface portion as the measures for minimizing the influence of stress at the active region-isolation junctions Rai in the HBT formation region Rbp.
In the step shown in FIG. 9(b), the p+ polysilicon layer 115 doped with impurities at a high density of about 1�1020 atoms�cm−3 or more is deposited to a thickness of about 150 nm and subsequently the third oxide film 117 is deposited to a thickness of about 100 nm, on the resultant wafer by CVD. The third oxide film 117 and the p+ polysilicon layer 115 in the HBT region Rbp are then patterned by dry etching to form the base opening 118 at the centers thereof so as to reach the second oxide film 112. The base opening 118 is made smaller than the center portion of the second oxide film 112 so as not to overlap the base junction openings 114. Thus, in this step, the external base 116 composed of the p+ polysilicon layer 115 and the portion of the Si/Si1−xGex layer 111 excluding the center thereof is formed. In this embodiment, as in EMBODIMENT 1, unlike the step for the conventional HBT shown in FIG. 14(b), the side portions of the third oxide film 117, the p+ polysilicon layer 115, the Si/Si1−xGex layer 111, and the polysilicon layer 109 as viewed from the figure are left unetched. By doing this, as in EMBODIMENT 1, the problem caused by residual n+ polysilicon left on the side faces of the p+ polysilicon layer 115 and the like can be prevented. In addition, it is possible to prevent the MISFET formation region and the like from being polluted with Ge that may otherwise come from the exposed faces of the Si/Si1−xGex layer. The third oxide film 117 and the p+ polysilicon layer 115 in the MISFET formation region Rms are entirely left unetched.
Thereafter, the following processing is performed to obtain the structure shown in FIG. 6. First, Ti is deposited to a thickness of about 40 nm on the entire surface of the resultant wafer by sputtering, and the resultant surface is subjected to RTA (rapid thermal annealing) at 675� C. for 30 seconds to form the Ti silicide layers 124 on the exposed surfaces of the n+ polysilicon layer 129, the p+ polysilicon layer 115, and the n+ collector drawing layer 107 in the HBT formation region Rbp and the exposed surfaces of the gate electrode 153 and the source/drain regions 155 in the MISFET formation region Rms. After selective removal of non-reacted portions of the Ti films, the resultant wafer is annealed to change the crystal structure of the Ti silicide layers 124.
In the above embodiments, all the oxide films are preferably silicon oxide films formed at a temperature of 700� C. or lower. This minimizes degradation of the density profile of impurities in the relevant components of the semiconductor device.
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Harame et al., "Si/SiGe Epitaxial-Base Transistors�Part II: Process Integration and Analog Applications", IEEE Transactions on Electron Devices, vol. 42, No. 3, pp. 469-482, Mar. 1995.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6597016 *Jan 13, 2000Jul 22, 2003Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the sameUS6660607 *Mar 30, 2001Dec 9, 2003International Business Machines CorporationMethod for fabricating heterojunction bipolar transistorsUS6713790 *Aug 7, 2002Mar 30, 2004Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the sameUS6730586 *Mar 7, 2002May 4, 2004Fujitsu Quantum Devices LimitedSemiconductor device having an overhanging structure and method for fabricating the sameUS6767783Jul 12, 2002Jul 27, 2004Mississippi State University-Research And Technology Corporation (Rtc)Self-aligned transistor and diode topologies in silicon carbide through the use of selective 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257/E21.572International ClassificationH01L21/8249, H01L27/06, H01L21/763, H01L29/737, H01L21/331Cooperative ClassificationH01L29/7378, H01L21/8249, H01L27/0623, H01L29/66242, H01L21/763European ClassificationH01L29/66M6T2H, H01L21/763, H01L21/8249, H01L29/737B8, H01L27/06D4TLegal EventsDateCodeEventDescriptionJul 30, 2014FPAYFee paymentYear of fee payment: 12Jul 30, 2014SULPSurcharge for late paymentYear of fee payment: 11May 2, 2014REMIMaintenance fee reminder mailedMar 11, 2010FPAYFee paymentYear of fee payment: 8Feb 24, 2006FPAYFee paymentYear of fee payment: 4Mar 15, 2000ASAssignmentOwner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ASAI, AKIRA;OONISHI, TERUHITO;TAKAGI, TAKESHI;AND OTHERS;REEL/FRAME:010632/0571Effective date: 20000309Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, OAZRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google 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Picture This: AFRICA: EYE TO EYE WITH THE UNKNOWN BY MICHAEL BRIGHT | Daily Mail Online
PICTURE THISAFRICA: EYE TO EYE WITH THE UNKNOWN BY MICHAEL BRIGHT (Quercus £25)
13:31 EST, 17 January 2013
A male baby mountain gorilla sniffs his midday snack on the volcanic slopes of the Virunga Mountains in Rwanda. There are no more than 800 of these critically endangered creatures left in the world, although the dedicated work of conservationists means that the population is slowly building, rather than facing almost certain extinction as feared. A combination of shrinking habitat and warring humans are their greatest enemies. Share or comment on this article

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Patent US5704972 - Product and process for strong light-weight aggregate - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention provides a method and mixture for use in forming strong light-weight aggregate and includes by weight about; 68% to 95% fly-ash, 2% to 10% hydrated lime, and 3% to 12% alkali hydroxide such as Sodium Hydroxide. While many types of fly-ash may be used, Type F or Type C fly-ash are...http://www.google.com/patents/US5704972?utm_source=gb-gplus-sharePatent US5704972 - Product and process for strong light-weight aggregateAdvanced Patent SearchPublication numberUS5704972 APublication typeGrantApplication numberUS 08/787,605Publication dateJan 6, 1998Filing dateJan 23, 1997Priority dateJan 23, 1997Fee statusLapsedPublication number08787605, 787605, US 5704972 A, US 5704972A, US-A-5704972, US5704972 A, US5704972AInventorsDaniel P. IvkovichOriginal AssigneeTrans Ash, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (31), Referenced by (17), Classifications (21), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetProduct and process for strong light-weight aggregate
US 5704972 AAbstract
1. A method for making aggregate comprising:(a) preparing a mixture comprising by weight about, 68% to 95% fly-ash, 2% to 10% hydrated lime, and 3% to 12% alkali hydroxide; (b) preparing a slurry by adding water to the mixture of (a) in a range of 10% to 25%; (c) compacting said slurry; (d) introducing the compacted slurry into a rotary means to rotate the compacted slurry to form pellets; and (e) removing the pellets from the rotary means and allowing them to hydrolyze. 2. A method as claimed in claim 1 wherein step (d) comprises introducing the compacted slurry from step (c) into a rotary kiln wherein the compacted slurry is rotated and heated such that it is pelletized.
6. A method for making aggregate comprising:(a) preparing a mixture comprising by weight about, 68% to 95% fly-ash, 2% to 10% hydrated lime, and 3% to 12% alkali hydroxide; (b) preparing a slurry by adding water to the mixture of (a) in a range of 10% to 25%; (c) forming a compacted slurry in situ by spreading the slurry on a level surface and then compacting the slurry by rolling. 7. A method as claimed in claim 6 wherein the slurry is compacted by rolling using a vibratory roller.
4NaOH+2SiO2 →2Na2 SiO3 30 2H2 O 1.
2K(OH)2 +3SiO2 →2KSiO3 +4H2 O   2.
Na2 CO3 +Ca(OH)2 →CaCO3 +2NaOH→ to 13.
KCO3 +Ca(OH)2 →CaCO3 +2K(OH)2 → to 24.
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BBC Radio 7 - The Radio Detectives, Series 2, A Case for Dr Morelle The BBC has updated its cookie policy. We use cookies to ensure that we give you the best experience on our website. This includes cookies from third party social media websites if you visit a page which contains embedded content from social media. Such third party cookies may track your use of the BBC website. We and our partners also use cookies to ensure we show you advertising that is relevant to you. If you continue without changing your settings, we'll assume that you are happy to receive all cookies on the BBC website. However, you can change your cookie settings at any time. Continue Change settings Find out more ]]> Accessibility links Skip to content Accessibility Help BBC iD Notifications
Sorry, this episode is not currently available on BBC iPlayer Radio A Case for Dr Morelle The Radio Detectives, Series 2 Episode 4 of 5 Professor Jeffrey Richards investigates how the London Harley Street psychiatrist-turned-detective solved his cases. Add Release date: 15 July 2008 30 minutes Last on Sun 29 Aug 2010 05:00 BBC Radio 7 More episodes Previous The Wisdom of Miss Marple — Series 2 View Programme information Next On the Beat with PC 49 — Series 2 View Programme information See all episodes from The Radio Detectives Broadcasts See all broadcasts of A Case for Dr Morelle (10) You may also like View all Similar programmes By genre: Factual > Arts, Culture & the Media By format: Documentaries Home {{/each}}

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Ghost writer fashion blog Workers and Jobs | Freelancer
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This is my first book ever. I just concluded my first draft for a book I am writing, entitled "The Road I have travelled". It's a book that talks about different story or journey in my life from a very young age up to now. In this book I want to the take reader in a journey with me, just like if they were there and its meant to inspire and leave my readers more hopeful about Haiti...
I need a ghost writer for a book on weight loss describing my experiences with weight gain and how I battled my way to weight loss.
I want to write on religion and Christianity as of now
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Hello: I have a project that consist of a fashion consultant that can help me find various stores that sell clothing and accessories suited for all body types and sizes with prices ranging from being frugal to wearing top of the line fashions. You must know how to style all body types and know where to go to obtain clothes suited for their body types
Fashion Design, Buyer Sourcing
I need you to write some content for a website. We ROYAL LONDON CLUB are bespoke VIP services.
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Experienced Writer Required Hi! I am Joshua, I am looking looking for an experienced writer with skills in SEO and Keyword research. I need someone with knowledge in article/content and blog writing to starting working with me immediately. Writer should be able to create high quality articles and be fluent in English. Thank you.
We require an experienced ghost writer, adept in the English language to work on long term book writing engagement. The basic structure of the books will be provided and the ghost writer has to fill in and polish the contents, that's all. (REMOVED BY [url removed, login to view] ADMIN)
We are looking for a ghost writer who specializes in pulp fiction type novels. We prefer someone knowledgeable on punk rock and related subcultures. The book will be approximately 250-300 pages, standard [url removed, login to view] will provide details on characters, locations, etc.
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I am looking for a designer for ladies and men's urbanwear.
Feb 24, 20172d 12h
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