text: Translations Chinese (Simplified) (8) Danish (8) Dutch (8) English (8) French (8) German (8) Norwegian (8) Polish (8) Russian (8) Swedish (8) Chinese (Traditional) (7) Czech (7) Finnish (7) Hungarian (7) Indonesian (7) License OSI-Approved Open Source (9) Academic Free License (1) Adaptive Public License (1) Affero GNU Public License (1) GNU General Public License version 2.0 (6) GNU General Public License version 3.0 (1) GNU Library or Lesser General Public License version 2.0 (1) Creative Commons Attribution License (1) Creative Commons Attribution ShareAlike License V2.0 (1) Creative Commons Attribution ShareAlike License V3.0 (1) Other License (1) Programming Language JavaScript (5) C (2) PHP (2) Perl (2) ALGOL 68 (1) APL (1) ASP (1) AWK (1) ActionScript (1) C++ (1) Java (1) PL/SQL (1) Python (1) Ruby (1) Unix Shell (1) Status Production/Stable (6) Beta (3) Mature (3) Planning (1) Pre-Alpha (1) Alpha (1) Inactive (1) OS Modern (9) FreeBSD (4) Linux (8) NetBSD (5) OS X (7) OpenBSD (4) Solaris (5) Vista (5) WinXP (9) Windows 7 (5) Windows 8 (1) Windows (9) Grouping and Descriptive Categories (8) 32-bit MS Windows (95/98) (3) 32-bit MS Windows (NT/2000/XP) (6) 64-bit MS Windows (5) All 32-bit MS Windows (5) All BSD Platforms (5) All POSIX (5) Classic 8-bit Operating Systems (1) OS Independent (4) OS Portable (1) Project is OS Distribution-Specific (2) Project is an Operating System Distribution (2) Project is an Operating System Kernel (1) Linux (8) BSD (7) Mac (7) Other Operating Systems (6) AmigaOS (1) Apple Mac OS Classic (1) BSD/OS (1) BeOS (2) Console-based Platforms (1) GNU Hurd (2) HP-UX (1) Haiku (1) IBM AIX (2) IBM AS/400 (1) IBM OS/2 (1) MS-DOS (1) Microsoft Windows 3.x (1) Microsoft Windows Server 2003 (2) MorphOS (1) Freshness Recently updated (3) Collection Enterprise (3) Top Apps

value: This website is a web service that offers software consumers a centralized online location to control and manage open-source software projects and research business software. It provides source code repository hosting, bug tracking, mirroring of downloads for load balancing, a wiki for documentation, developer and user mailing lists, user-support forums, user-written reviews and ratings, a news bulletin, micro-blog for publishing project updates, and other features.


text:
Books ISBN: 9780801887734
by Morton, David L, Jr., and Gabriel, Joseph
13508687016
13529534803
13226762024
13111319136
Very Good. 0801887739 Crisp, clean, unread paperback with light shelfwear to the covers and a publisher's mark to one edge-Nice!
13507212744
13527279432
Good. Trade paperback (US). Glued binding. 201 p. Contains: Illustrations, black & white, Halftones, black & white, Line drawings, black & white.
13298969493
Fair. 0801887739 We guarantee all of our items-customer service and satisfaction are our top priorities. Please allow 4-14 business days for Standard shipping, within the US. Thank you for supporting our small, family-owned business!
by Stanley Sadie Starting at $1.51	Baker's Biographical Dictionary of Musicians
Starting at $0.99	Off the Record: The Technology & Culture of Sound Recording in America
Starting at $0.99	Playback: From the Victrola to MP3, 100 Years of Music, Machines, and Money
Starting at $0.99	Sound Recording: The Life Story of a Technology

type: global

value: This website is is an online store that sells new books, used books, out-of-print books, rare books, and other media through an online network of independent booksellers.


text:
Boulevard Bingo - Portsmouth, VA | Groupon
2880 Airline Boulevard, Portsmouth, VA 23701 2880 Airline Boulevard, Portsmouth Directions
+17574884911
2880 Airline Boulevard,
When you're ready to take on your next adventure, head to Portsmouth's Boulevard Bingo, VA for some fun. This weekend, don't do the same old thing. Head to this place!
Bingo is a great way to pass the time. You won't regret taking home a bingo set from Boulevard Bingo. This game is perfect for the family. Take it out on a rainy day or bring it with you on your next road trip.
Olde Towne (4.2 mi)
Groupon has verified that the customer actually visited Boulevard Bingo.

value: This website is an American global e-commerce marketplace connecting subscribers with local merchants by offering activities, travel, goods and services in 15 countries. Based in Chicago, Groupon was launched there in November 2008, launching soon after in Boston, New York City and Toronto.


text: Home Furniture > Refine Price $ to $ Go Top brands Aspire Home Accents Benzara Store availability Sort Best sellers Price: low to high Price: high to low Highest rating New Reduced Price $177.99 List price $310.0 Save $132.01 Aspire Josette Baker's Rack Sold & Shipped by Build.com Free shipping Special Buy $102.00 Aspire Corner Baker's Rack 5.0 stars (1) ratings Sold & Shipped by PlumStruck Free shipping Special Buy $115.99 3-Deck Corner Rack Sold & Shipped by Wayfair.com Free shipping 1 Showing 3 of 3 results Departments Kitchen & Dining Furniture Shipping & Pickup Show all Ship to Home Category TV Stands Beds Bookcases Kitchen & Dining Tables End Tables Coffee Tables Dressers Armchairs Desks Sofas Futons Night Stands Computer Desks Ottomans Storage Bins Armless Chairs Chests of Drawers Table & Chair Sets Bean Bags Barstools See more categories Price $ to $ Go $0 - $50 $50 - $75 $75 - $100 $100 - $150 $150 - $200 $200 - $250 $250 - $300 $300+ Color White Black Brown Off-White See more colors Special Offers Reduced Price New Special Buy Brand Aspire Home Accents Benzara Finish White Retailer Wayfair.com Build.com PlumStruck Width 22.0 23 27.0 Customer Rating 4.0 stars & Up Length 13.0 16.0 23 Style Traditional Contemporary/Modern Lifestage Adult Popular in Furniture Bakers Racks Pub Table Sets Entryway Storage Benches Indoor Benches Table Sets Futon Sofas Coffe Table Set Kitchen Islands Compute- app-11030446-4-54868065, DC- prod-dfw3, ENV- prod-a, Ver- 39.0.2, SHA- acabbc21b376ba1d6aaf7de2ef8f589ca8da4340, Log- cf9c567c-94dd-154df9bc430000 Site Information Be the first to save! Email Address Sign up Privacy policy Stay connected Mobile apps Help Feedback MoneyCenter Privacy & Security CA Privacy Rights Terms of Use Financial Services Walmart MoneyCenter Walmart Credit Card Apply Now Manage Card Account Product Care Plans Walmart Pay Get to Know Us About Walmart.com Corporate Suppliers Marketplace Careers @Walmartlabs Walmart.com Terms of Use About Our Ads Affiliate Program CA Privacy Rights Privacy & Security Customer Service Returns Policy Product Recalls Int'l Customers Tax Exempt Program Contact Us Feedback In the Spotlight Expand Baby Cribs Strollers Diapers Baby Feeding Car Seats Expand Electronics Cut the Cable Computers TVs iPad & Tablets Expand Fitness Exercise Machines Vitamins Ellipticals Treadmills Fitbit Expand Spring Cleaning Storage Containers Garage Storage Storage Sheds Expand International Sites Argentina Brazil Canada Chile China Japan Mexico United Kingdom © Walmart Stores, Inc. To ensure we’re able to help you as best we can, please include your reference number: Ref:

value: This website is an American multinational retail corporation that operates a chain of hypermarkets , discount department stores, and grocery stores from the United States, headquartered in Bentonville, Arkansas.


text:
Patent US20070298590 - Methods and apparatus for depositing a microcrystalline silicon film for ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMethods for depositing a microcrystalline silicon film layer with improved deposition rate and film quality are provided in the present invention. Also, photovoltaic (PV) cell having a microcrystalline silicon film is provided. In one embodiment, the method produces a microcrystalline silicon film on...http://www.google.com/patents/US20070298590?utm_source=gb-gplus-sharePatent US20070298590 - Methods and apparatus for depositing a microcrystalline silicon film for photovoltaic deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20070298590 A1Publication typeApplicationApplication numberUS 11/426,127Publication dateDec 27, 2007Filing dateJun 23, 2006Priority dateJun 23, 2006Also published asCN101322251A, CN101322251B, EP2041797A2, EP2041797A4, US7648892, US7655542, US7923354, US20090053847, US20100003780, WO2007149945A2, WO2007149945A3Publication number11426127, 426127, US 2007/0298590 A1, US 2007/298590 A1, US 20070298590 A1, US 20070298590A1, US 2007298590 A1, US 2007298590A1, US-A1-20070298590, US-A1-2007298590, US2007/0298590A1, US2007/298590A1, US20070298590 A1, US20070298590A1, US2007298590 A1, US2007298590A1InventorsSoo Young Choi, Takako Takehara, John M. White, Yong Kee ChaeOriginal AssigneeSoo Young Choi, Takako Takehara, White John M, Yong Kee ChaeExport CitationBiBTeX, EndNote, RefManPatent Citations (99), Referenced by (64), Classifications (28), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethods and apparatus for depositing a microcrystalline silicon film for photovoltaic device
US 20070298590 A1Abstract
[0002] The present invention relates to methods and apparatus for depositing microcrystalline silicon film for photovoltaic devices.
[0004] Photovoltaic devices (PV) or solar cells are devices which convert sunlight into direct current (DC) electrical power. PV or solar cells typically have one or more p-n junctions. Each junction comprises two different regions within a semiconductor material where one side is denoted as the p-type region and the other as the n-type region. When the p-n junction of the PV cell is exposed to sunlight (consisting of energy from photons), the sunlight is directly converted to electricity through the PV effect. PV solar cells generate a specific amount of electric power and cells are tiled into modules sized to deliver the desired amount of system power. PV modules are created by connecting a number of PV solar cells and are then joined into panels with specific frames and connectors.
[0005] Microcrystalline silicon film (μc-Si) is one type of film being used to form PV devices. However, a production worthy apparatus and process has yet to be developed to be able to provide PV devices at low cost. For example, insufficient crystallinity of the silicon film may cause incomplete formation and fraction of the film, thereby reducing the conversion efficiency in a PV solar cell. Additionally, conventional deposition processes of microcrystalline silicon film (μc-Si), have slow deposition rates, which disadvantageously reduce manufacturing throughput and increase production costs.
[0006] Therefore, there is a need for an improved method for depositing a microcrystalline silicon film.
[0007] The present invention provides methods for depositing a microcrystalline silicon layer with improved deposition rate greater than about 20 nm per minute suitable for use in a PV solar cell. The microcrystalline silicon film is deposited with improved deposition rate and good film qualities. In one embodiment, the method includes providing a substrate having a surface area greater than 1 square meters in a process chamber, flowing a gas mixture including a silane-based gas and H2 gas into the process chamber, maintaining a plasma formed from the gas mixture in the process chamber, and depositing a microcrystalline silicon film on the substrate at a deposition rate greater than about 20 nm per minute, wherein the microcrystalline silicon film has a crystallized volume between about 20 percent to about 80 percent.
[0008] In another embodiment, the method for depositing a microcrystalline silicon film includes providing a substrate having a surface area greater than about 1 square meters in a process chamber, flowing a gas mixture including a silane-based gas and H2 gas into the process chamber, wherein the silane based gas at a flow rate at least about 0.2 slm/m2 and H2 gas at a flow rate at least about 10 slm/m2, controlling the substrate temperature at a range between about 100 degrees Celsius to about 400 degrees Celsius, maintaining the process pressure at a range greater than about 3 Torr, applying a RF power density at least about 100 mWatts/cm2 to form a plasma from the gas mixture, and depositing a microcrystalline silicon film on the substrate at a deposition rate greater than about 20 nm per minute, wherein the microcrystalline silicon film has a crystallized volume between about 20 percent to about 80 percent and a hydrogen content between about 0.1 atomic percentage and about 20 atomic percentage.
[0009] In yet another embodiment, the method for manufacturing a silicon based photoelectric converter includes providing a substrate in a process chamber, forming a photoelectric converter on the substrate. The photoelectric converter comprises depositing a p-type semiconductor layer on the substrate, depositing an i-type semiconductor layer by a microcrystalline silicon film on the substrate at a deposition rate greater than about 20 nm per minute by a CVD process, wherein the microcrystalline silicon film has a crystallized volume between about 20 percent to about 80 percent, and depositing a n-type semiconductor layer on the microcrystalline silicon film.
[0010] In still another embodiment, the method of manufacturing a silicon based photoelectric converter includes providing a substrate on a substrate support assembly disposed in a process chamber, flowing a gas mixture including a silane-based gas and H2 gas through a gas distribution plate into the process chamber, wherein the gas distribution plate comprises a diffuser having a curvature surface, maintaining a spacing between the substrate support assembly and the gas distribution plate, maintaining a plasma formed from the gas mixture in the process chamber, and depositing a microcrystalline silicon film on the substrate at a deposition rate greater than about 20 nm per minute, wherein the microcrystalline silicon film has a crystallized volume between about 20 percent to about 80 percent.
[0011] In still another embodiment, the method of manufacturing a silicon based photoelectric converter includes providing a substrate on a substrate support assembly disposed in a process chamber, wherein the substrate support assembly includes cooling channels embedded therein, forming a photoelectric converter on the substrate by depositing a microcrystalline silicon film as an i-type semiconductor layer disposed between a p-type semiconductor layer and a n-type semiconductor layer, wherein the microcrystalline silicon film is deposited by a gas mixture supplied from a diffuser having a curvature surface.
[0013] FIG. 1 depicts a schematic cross-sectional view of one embodiment of a process chamber in accordance with the invention;
[0014] FIG. 2 depicts an exemplary cross sectional view of a crystalline silicon-based thin film PV solar cell in accordance with one embodiment of the present invention;
[0015] FIG. 3 depicts an exemplary cross sectional view of a tandem type PV solar cell 300 in accordance with one embodiment of the present invention;
[0016] FIG. 4 depicts an exemplary cross sectional view of a triple junction PV solar cell in accordance with one embodiment of the present invention;
[0017] FIG. 5A is a cross sectional view of a diffuser having a concave horizontal profile; and
[0018] FIG. 5B is a cross sectional view of a diffuser having a convex horizontal profile.
[0021] The present invention provides methods for depositing a microcrystalline silicon layer. Certain embodiments of the present invention provides a microcrystalline deposition process with improved deposition rate greater than about 20 nm per minute suitable for use in a PV solar cell. In certain embodiment, the microcrystalline silicon film layer has a crystallized volume between about 20 percent to about 80 percent. In certain embodiments, the microcrystalline silicon film has a hydrogen content between about 0.1 atomic percentage and about 20 atomic percentage. In certain embodiment, the microcrystalline silicon film has a crystal orientation plane (220) parallel to the surface of the film and an intensity ratio of the (111) diffraction peak relative to the (220) diffraction peak in X-ray diffraction between about 2 and about 0.1. In certain embodiments, the process for depositing the microcrystalline silicon layer utilizes a plasma formed from a gas mixture that includes a silane-based gas and H2 gas.
[0022] FIG. 1 is a schematic cross-sectional view of one embodiment of a plasma enhanced chemical vapor deposition system 100 in which the invention may be practiced. One suitable plasma enhanced chemical vapor deposition (PECVD) system is available from AKT, Inc., a subsidiary of Applied Materials, Inc., Santa Clara, Calif. It is contemplated that other plasma processing chambers, including those from other manufactures, may be utilized to practice the present invention.
[0023] The system 100 generally includes a processing chamber body 102 having walls 110 and a bottom 111 that partially define a process volume 180. The process volume 180 is typically accessed through a port and/or a valve 106 to facilitate movement of a substrate 140, such as a solar cell glass substrate, stainless steel substrate, or plastic substrate, semiconductor substrate, or other suitable substrate, into and out of the processing chamber body 102. The chamber 100 supports a lid assembly 118 surrounding a gas inlet manifold 114 that consists of a cover plate 116, a first plate 128 and a second plate 120. In one embodiment, the first plate 128 is a backing plate, and the second plate 120 is a gas distribution plate, for example, a diffuser. A vacuum pump 129 is disposed on the bottom of the chamber body 102 to maintain the chamber 100 at a desired pressure range. Optionally, the walls 110 of the chamber 102 may be protected by covering with a liner 138, such as a ceramic material, anodizing or other protective coating to prevent damage during processing.
[0024] The diffuser 120 may have a substantial planar surface adapted to provide a plurality of orifices 122 for a process gas or gasses from a gas source 105 coupled to the chamber body 102. The diffuser 120 is positioned above the substrate 140 and suspended vertically by a diffuser gravitational support 115. In one embodiment, the diffuser 120 is supported from an upper lip 155 of the lid assembly 118 by a flexible suspension 157. The flexible suspension 157 is disclosed in detail by U.S. Pat. No. 6,477,980, which issued Nov. 12, 2002 with the title “Flexibly Suspended Gas Distribution Manifold for A Plasma Chamber” and is herein incorporated by reference. The flexible suspension 157 is adapted to support the diffuser 120 from its edges to allow expansion and contraction of the diffuser 120.
[0025] In one embodiment, the flexible suspension 157 may have different configuration utilized to facilitate the expansion and contraction of the diffuser 120. In another embodiment, the flexible suspension 157 may be used with the diffuser gravitational support 115 to facilitate the curvature of the diffuser 120. For example, the diffuser 120 may have a concave surface contracted by the diffuser gravitational support 115 and/or flexible suspension 157, as shown in FIG. 5A. Alternatively, the diffuser 120 may have a convex surface expanded by the diffuser gravitational support 115 and/or flexible suspension 157, as shown in FIG. 5B. The surface configuration of the diffuser 120 is disclosed in detail by U.S. Patent Publication No. 2006/0,060,138, filed Sep. 20, 2004 by Keller et al, title “Diffuser Gravity Support”, and is herein incorporated by reference.
[0026] In the embodiment depicted in FIG. 5A, the diffuser 120 has a concave surface 502 having gradual changing distances between the curvature surface 502 and the flat surface 504, thereby creating different process spacing in the processing volume 180 to the substrate 140. The gradual transition of the narrow spacing region above the edge of the substrate 140 to the slightly wider spacing region above the center of the substrate 140 allows the substrate 140 being processing with different spacing. In another embodiment, the diffuser 120 may be configured to have planar surface, or convex surface, as shown in FIG. 5B, to facilitate different process conditions. The spacing between the diffuser surface 132 and the substrate surface, as shown in FIG. 1, is selected and adjusted to enable the deposition process to be optimized over a wide range of deposition conditions, while maintaining uniformity of film deposition. In one embodiment, the spacing is controlled about 100 mils or larger, such as between about 400 mils to about 1600 mils, such as between about 400 mils and about 1200 mils during processing.
[0027] The diffuser gravitational support 115 may supply a process gas to a gas blocks 117 mounted on the support 115. The gas block 117 is in communication with the diffuser 120 via a longitudinal bore 119, within the support 115, and supplies a process gas to the plurality of passages 122 within the diffuser 120. In one embodiment, one or more process gasses travel through the gas block 117, through the longitudinal bore 119, through angled bores 119 a, and are deposited in a large plenum 121 created between backing plate 128 and diffuser 120, and a small plenum 123 within the diffuser 120. Subsequently, the one or more process gasses travel from the large plenum 121 and the small plenum 123 through the plurality of orifices 122 within the diffuser 120 to create the processing volume 180 below the diffuser 120. In operation, the substrate 140 is raised to the processing volume 180 and the plasma generated from a plasma source 124 excites gas or gases to deposit films on the substrate 140.
[0028] The plurality of orifices 122 may have different configurations to facilitate different gas flow in the processing volume 180. In one embodiment, the orifices 122 may have flare openings having a diameter ranging between about 0.01 inch and about 1.0 inch, such as between about 0.01 inch and about 0.5 inch. The dimension and density of the flare openings of the orifices 122 may be varied across the surface of the diffuser 120. In one embodiment, dimension and densities of the orifices 122 located in the inner (e.g., center) region of the diffuser 120 may be higher than the orifices 122 located in the outer (e.g., edge) region. Examples of orifice configurations and a diffuser that may be used in the chamber 100 are described in commonly assigned U.S. Patent Publication No. 2005/0,251,990, filed Jul. 12, 2004, by Choi et al., U.S. Pat. No. 6,722,827, filed Aug. 8, 2001 by Keller et al.; U.S. Pat. No. 6,477,980, issued Nov. 12, 2002 to White et al; U.S. patent application Ser. No. 11/173,210, filed Jul. 1, 2005 by Choi et al; Ser. No. 10/337,483, filed Jan. 7, 2003 by Blonigan et al.; Publication No. 2005/0,255,257, filed Dec. 22, 2004 by Choi et al.; and Publication No. 2005/0,183,827, filed Feb. 24, 2004 by White et al., all of which are hereby incorporated by reference in their entireties.
[0029] A substrate support assembly 112 is generally disposed on the bottom of the chamber body 102. The support assembly 112 is grounded such that RF power, supplied by the plasma source 124, supplied to the diffuser 120 may excite gases, source compounds, and/or precursors present in the process volume 180 as stated above. The RF power from the plasma source 124 is generally selected commensurate with the size of the substrate 140 to drive the chemical vapor deposition process.
[0030] In one embodiment, a RF power is applied to the diffuser 120 to generate an electric field in the process volume 180. For example, a power density of about 100 mWatts/cm2 or greater during film depositing. The plasma source 124 and matching network (not shown) create and/or sustain a plasma of the process gases in the process volume 180. Various frequencies of the RF and VHF power may be used to deposit the silicon film. In one embodiment, a RF and VHF power at a range between about 0.3 MHz and about 200 MHz, such as about 13.56 MHz, or about 40 MHz, may be used. In another embodiment, a RF power of about 13.56 MHz and a low frequency RF power of about 350 KHz may be used. In yet another embodiment, a VHF power of about 27 MHz up to about 200 MHz may be utilized to deposit films with high deposition rate.
[0031] The substrate support assembly 112 has a lower side 126 and an upper side 108 adapted to support the substrate 140. A stem 142 is coupled to the lower side 126 of the substrate support assembly 112 and connected to a lift system (not shown) for moving the support assembly 112 between an elevated processing position and a lowered substrate transfer position. The stem 142 provides a conduit for coupling electrical and thermocouple leads to the substrate support assembly 112.
[0032] The substrate support assembly 112 includes a conductive body 194 having the upper side 108 for supporting the substrate 140 to dispose thereon. The conductive body 194 may be made of a metal or metal alloy material. In one embodiment, the conductive body 194 is made of aluminum. However, other suitable materials can also be used. The substrate support assembly 112 is temperature controlled to maintain a predetermined temperature range during substrate processing. In one embodiment, the substrate support assembly 112 includes one or more electrodes and/or heating elements 198 utilized to control the temperature of the substrate support assembly 112 during processing. The heating elements 198 controllably heat the substrate support assembly 112 and the substrate 140 positioned thereon to a determined temperature range, e.g., a set point temperature of about 100 degrees Celsius or higher. In an exemplary embodiment, the heating elements 198 may include an inner heating element embedded in the center portion of the substrate support assembly 112 and an outer heating element embedded in the edge portion of the substrate support assembly 112. As the outer edge of the substrate 140 may have a temperature lower than the center portion of the substrate 140 contributed by the plasma distribution, the outer heating element is configured to maintain a temperature slightly higher than the temperature of the inner heating element, such as higher than 20 degrees Celsius, thereby maintaining the uniform temperature across the substrate 140. It is contemplated that the temperature configuration of the inner and outer heating element may be varied based on process requirement.
[0033] In another embodiment, the substrate support assembly 112 may further include one ore more cooling channels 196 embedded within the conductive body 194. The one or more cooling channels 196 are configured to maintain temperature variation in the processing volume 180 within a predetermined temperature range during processing, a temperature variation less than 20 degrees Celsius. The cooling channels 196 may be fabricated from metals or metal alloys which provide desired thermal conductivity. In one embodiment, the cooling channels 196 are made of a stainless steel material.
[0034] In one embodiment, the temperature of the substrate support assembly 112 that includes the heating elements 198 and cooling channels 196 embedded therein may control the substrate 140 disposed thereon processed at a desired range that allow substrates with low melt point, such as alkaline glasses, plastic and metal, to be utilized in the present invention. In one embodiment, the heating elements 198 and the cooling channels 196 may maintain a temperature about 100 degrees Celsius or higher, such as between about 150 degrees Celsius to about 550 degrees Celsius.
[0035] FIG. 2 depicts an exemplary cross sectional view of a crystalline silicon-based thin film PV solar cell 200 in accordance with one embodiment of the present invention. The crystalline silicon-based thin film PV solar cell 200 includes a substrate 140. The substrate 140 may be thin sheet of metal, plastic, organic material, silicon, glass, quartz, or polymer, among others suitable materials. The substrate 140 may have a surface area greater than about 1 square meters, such as greater than about 2 square meters. An optional dielectric layer (not shown) may be disposed between the substrate 140 and a transmitting conducting oxide (TCO) layer 202. In one embodiment, the optional dielectric layer may be a SiON or silicon oxide (SiO2) layer. The transmitting conducting oxide (TCO) layer 202 may include, but not limited to, at least one oxide layer selected from a group consisting of tin oxide (SnO2), indium tin oxide (ITO), zinc oxide (ZnO), or the combination thereof. The TCO layer 202 may be deposited by a CVD process, a PVD process, or other suitable deposition process.
[0036] A photoelectric conversion unit 214 is formed on the TCO layer 202. The photoelectric conversion unit 214 includes a p-type semiconductor layer 204, a n-type semiconductor layer 208, and an intrinsic type (i-type) semiconductor layer 206 as a photoelectric conversion layer. The p-type and n-type semiconductor layers 204, 208 may be silicon based materials doped by an element selected either from group III or V. A group III element doped silicon film is referred to as a p-type silicon film, while a group V element doped silicon film is referred to as a n-type silicon film. In one embodiment, the n-type semiconductor layer 208 may be a phosphorus doped silicon film and the p-type semiconductor layer 204 may be a boron doped silicon film. The doped silicon film includes an amorphous silicon film (a-Si), a polycrystalline film (poly-Si), and a microcrystalline film (μc-Si) with a thickness between around 5 nm and about 50 nm. Alternatively, the doped element in semiconductor layer 204, 208 may be selected to meet device requirements of the PV solar cell 200. The n-type and p-type semiconductor layers 208, 204 may be deposited by a CVD process or other suitable deposition process.
[0037] The i-type semiconductor layer 206 is a non-doped type silicon based film. The i-type semiconductor layer 206 may be deposited under process condition controlled to provide film properties having improved photoelectric conversion efficiency. In one embodiment, the i-type semiconductor layer 206 includes i-type polyscrystalline silicon (poly-Si), or i-type microcrystalline silicon film (μc-Si). The i-type crystalline silicon-based film 206 may be deposited in the processing chamber 102 or other suitable processing chambers.
[0038] In the embodiment depicted in FIG. 2, the i-type semiconductor layer 206 is a microcrystalline silicon film (μc-Si) having a crystallized volume between about 20 percent and about 80 percent, for example, greater than about 50 percent. The substrate temperature during the deposition process is maintained at a predetermined range. In one embodiment, the substrate temperature is maintained at less than about 400 degrees Celsius so as to allow the substrates with low melt point, such as alkaline glasses, plastic and metal, to be utilized in the present invention. In another embodiment, the substrate temperature in the process chamber is maintained at a range between about 100 degrees Celsius to about 400 degrees Celsius. In yet another embodiment, the substrate temperature is maintained at a range about 150 degrees Celsius to about 400 degrees Celsius, such as 200 degrees Celsius.
[0039] During processing, a gas mixture is flowed into the process chamber 102 and used to form a RF plasma and deposit the i-type μc-Si film 206. In one embodiment, the gas mixture includes a silane-based gas and a hydrogen gas (H2). Suitable examples of the silane-based gas include, but not limited to, mono-silane (SiH4), di-silane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), and dichlorsilane (SiH2Cl2), and the like. The gas ratio of the silane-based gas and H2 gas is maintained to control reaction behavior of the gas mixture, thereby allowing a desired proportion of the crystallization, e.g., between about 20 percent and about 80 percent, of the formed silicon film. In one embodiment, the silane-based gas is SiH4. The SiH4 gas may be supplied at a flow rate at least about 0.2 slm/m2 and the H2 gas may be supplied at a flow rate at least about 10 slm/m2. The gas mixture may have a H2 gas flow controlled greater than SiH4 gas flow. Alternatively, the gas mixture of SiH4 gas and H2 gas may be supplied at a ratio of SiH4 to H2 of between about 1:20 and about 1:200, such as between about 1:80 and about 1:120, for example, about 1:100. Additionally, the process pressure is maintained at between about 1 Torr to about 100 Torr, for example, about 3 Torr to about 20 Torr, such as greater than 3 Torr.
[0040] Alternatively, one or more inert gases may be included with the gas mixture provided to the process chamber 102. The inert gas may include, but not limited to, noble gas, such as Ar, He, Xe, and the like. The inert gas may be supplied to the processing chamber 102 at a flow ratio of inert gas to H2 gas of between about 1:10 and about 2:1.
[0041] A RF power is applied to maintain the plasma during deposition. In one embodiment, the RF power density may be supplied at least about 100 mWatt/cm2 to obtain a deposition rate greater than 20 nm per minute. The RF power is provided between about 100 kHz and about 100 MHz, such as about 350 kHz or about 13.56 MHz. Alternatively, a VHF power may be utilized to provide a frequency up to between about 27 MHz and about 200 MHz. In embodiments where a high deposition rate is required, the RF power density may be applied at a high power density greater than 300 mWatt/cm2 to obtain a deposition rate greater than 60 nm per minute, such as 100 nm per minute.
[0042] The spacing of the substrate to the gas distribution plate assembly 118 may be controlled in accordance with the substrate dimension. In one embodiment, the processing spacing for a substrate greater than 1 square meters is controlled between about 400 mils and about 1200 mils, for example, between about 400 mils and about 800 mils, such as 500 mils.
[0043] To facilitate the deposition film quality of i-type μc-Si layer 206, a thin layer prior to the i-type μc-Si film 206 deposition may be deposited and utilized as a seed layer to provide better contact adhesion and interfacial qualities between the p-type semiconductor layers 204 and the i-type μc-Si film 206 for high quality and high fraction of microcrystalline phase formation. In one embodiment, the seed layer may be deposited at a relatively low deposition rate, such as less than 20 nm per minute, having a thickness between about 20 Å and about 500 Å, such as between about 50 Å and about 300 Å. The low deposition rate of the seed layer may be controlled by a gas mixture having a ratio of silane-based gas to H2 between about 1:100 and about 1:20000, such as between 1:200 and 1:1000, for example 1:500 with other process parameters substantially similar as the i-type μc-Si layer 206 deposition. In another embodiment, the i-type μc-Si film 206 deposition may include a two step deposition process having a first step depositing the seed layer and a second step depositing the bulk i-type μc-Si layer 206. The first step seed layer deposition process has a relatively lower deposition rate, such as less than 10 nm per minute, controlled by a gas mixture having a ratio of silane-based gas to H2 between about 1:100 and about 1:2000, such as between 1:200 and 1:1000, for example 1:500. The second step bulk i-type μc-Si layer 206 has a deposition rate greater than 20 nm per minute as stated above to facilitate manufacture throughout and cost. In yet another embodiment, the second step of bulk i-type μc-Si layer 206 is grown by gradual change of H2 gas ratio used to dilute the gas mixture, rending the deposited a desired graded film. For example, the gradual change of H2 gas ratio for gas mixture dilution may be varied between about 1:200 and about 1:20 during the seed layer deposition period, thereby rending the process starting from supplying a gas mixture with a relatively higher H2 dilution gas ratio to a gas mixture with relatively a lower H2 dilution gas ratio. As such, the fraction of microcrystalline phase may be controlled within a desired thickness of μc-Si layer 206. The gradual change of H2 dilution gas ratio may be achieved by controlled digital mode or analog mode of H2 gas flow. In still another embodiment, the first step of seed layer may be deposited as a portion of the p-type semiconductor layers 204.
[0044] The process gas mixture, process temperature, and RF power described above provide an i-type silicon film 206 having an advantageous crystalline structure. For example, small grained μc-Si film, e.g., about 20-30 nm, may be obtained while processing at a temperate of between about 150 degrees Celsius and about 350 degrees Celsius. Large grained poly-Si film, e.g., greater than about 100 nm, may be obtained while processing at a temperate of between about 350 degrees Celsius and about 600 degrees Celsius. Accordingly, as the RF power is selected at a relative high range to facilitate the deposition rate of the μc-Si film, a predetermined flow ratio of the gas mixture is utilized to deposit the μc-Si film having a desired crystalline and film property, thereby facilitating the PV solar cell working at desired photoelectric conversion efficiency.
[0045] In one embodiment, the deposited i-type μc-Si film 206 is a hydrogenated μc-Si film having a hydrogen content between about 0.1 atomic percentage and about 20 atomic percentage, for example between about 1 atomic percentage and about 10 atomic percentage, such as less than 10 atomic percentage. The grains of the deposited i-type μc-Si film 206 have a crystal orientation plane (220) parallel to the surface of the film and the intensity ratio of the (111) diffraction peak relative to the (220) diffraction peak in X-ray diffraction is between about 2 and about 0.1, for example, about less than 1.0. Additionally, the deposited i-type μc-Si film 206 may have a thickness between about 500 nm and about 10 μm, for example, about 1000 nm and about 5000 nm.
[0046] Referring back to FIG. 2, after the photoelectric conversion unit 214 is formed on the TCO layer 202, a backside electrode 216 is disposed on the photoelectric conversion unit 214. In one embodiment, the backside electrode 216 may be formed by a stacked film that includes a transmitting conducting oxide (TCO) layer 210 and a conductive layer 212. The conductive layer 212 may include, but not limited to, a metal layer selected from a group consisting of Ti, Cr, Al, Ag, Au, Cu, Pt, or an alloy of the combination thereof. The transmitting conducting oxide (TCO) layer 210 may be fabricated from a material similar as the TCO layer 202 formed on the substrate. Suitable transmitting conducting oxide (TCO) layer 210 include, but not limited to, tin oxide (SnO2), indium tin oxide (ITO), zinc oxide (ZnO), or the combination thereof. The metal layer 212 and TCO layer 210 may be deposited by a CVD process, a PVD process, or other suitable deposition process.
[0047] In operation, incident light 222 provided by the environment, e.g, sunlight or other photons, is supplied to the PV solar cell 200. The photoelectric conversion unit 214 in the PV solar cell 200 absorbs the light energy and converts the light energy into electrical energy by the operation of the p-i-n junctions formed in the photoelectric conversion unit 214, thereby generating electricity or energy. Alternatively, the PV solar cell 200 may be fabricated or deposited in a reversed order. For example, the substrate 140 may be disposed over backside electrode 216.
[0048] FIG. 3 depicts an exemplary cross sectional view of a tandem type PV solar cell 300 in accordance with another embodiment of the present invention. Tandem type PV solar cell 300 has a similar structure of the PV solar cell 200 including a TCO layer 302 formed on a sheet 140 and a first photoelectric conversion unit 322 formed on the TCO layer 302, as described above in FIG. 2. In one embodiment, the i-type semiconductor layer 306 in the first photoelectric conversion unit 322 is deposited as an amorphous Si film. Alternatively, the i-type semiconductor layer 306 in the first photoelectric conversion unit 322 may be deposited as a poly-Si or an μc-Si film. An optional interfacial layer 310 may be formed between the first photoelectric conversion unit 322 and a second photoelectric conversion unit 324. The optional interfacial layer 310 may be a TCO layer as the TCO layer 302 formed on the substrate 140. The combination of the first underlying conversion unit 322 and the second photoelectric conversion unit 324 increases the photoelectric conversion efficiency. The second photoelectric conversion unit 324 may be an μc-Si based photoelectric conversion unit 324 having an μc-Si film as the i-type semiconductor layer 314 sandwiched between a p-type semiconductor layer 312 and a n-type semiconductor layer 316. Alternatively, the i-type semiconductor layer 314 in the second photoelectric conversion unit 324 may be manufactured as the μc-Si film 206 utilized in the photoelectric conversion unit 214 of single junction PV solar cell 200 as described in FIG. 2. Alternatively, the p-type semiconductor layer 312 may be μc-Si layer.
[0049] A backside electrode 326 is disposed on the second photoelectric conversion unit 324. The backside electrode 326 may be similar to backside electrode 216 as described in FIG. 2. The backside electrode 326 may comprise a conductive layer 320 formed on a TCO layer 318. The materials of the conductive layer 320 and the TCO layer 318 may be similar to the conductive layer 212 and TCO layer 210 as described in FIG. 2.
[0050] In operation, incident light 328 provided by the environment is supplied to the PV solar cell 300. The photoelectric conversion unit 322, 324 in the PV solar cell 300 absorbs the light energy and converts the light energy into electrical energy by operation of the p-i-n junctions formed in the photoelectric conversion unit 324, 322, thereby generating electricity or energy. Alternatively, the PV solar cell 300 may be fabricated or deposited in a reversed order. For example, the substrate 140 may be disposed over the backside electrode 326.
[0051] Alternatively, a third overlying photoelectric conversion unit 410 may be formed on the second photoelectric conversion unit 324, as shown in FIG. 4. An optional interfacial layer 402 may be disposed between the second photoelectric conversion unit 324 and the third photoelectric conversion unit 410. The optional interfacial layer 402 may be a TCO layer 402 as the TCO layers of 310, 302 as described in FIG. 3. The third photoelectric conversion unit 410 may be substantially similar as the second photoelectric conversion unit 324 having an i-type semiconductor layer 406 disposed between a p-type semiconductor layer 404 and a n-type layer 408. The third photoelectric conversion unit 410 may be a μc-Si-type photoelectric conversion unit having an i-type semiconductor layer 406 formed by an μc-Si film. Alternatively, the i-type semiconductor layer 406 may be formed by a poly-Si or an amorphous silicon layer. Alternatively, the p-type semiconductor layer 312 may be μc-Si layer. It should be noted that one or more photoelectric conversion units may optionally deposited on the third photoelectric conversion unit utilized to promote photoelectric conversion efficiency.
[0052] Thus, improved methods for depositing an μc-Si film are provided. The method advantageously increases the deposition rate and film quality of the μc-Si film utilized in a PV solar cell, thereby increasing the photoelectric conversion efficiency and device performance of the PV solar cell as compared to conventional methods.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4063735 *Mar 15, 1976Dec 20, 1977Wendel Dan PCB Radio highway board game apparatusUS4068043 *Mar 11, 1977Jan 10, 1978Energy Development AssociatesPump battery systemUS4400577 *Jul 16, 1981Aug 23, 1983Spear Reginald GThin solar cellsUS4471155 *Apr 15, 1983Sep 11, 1984Energy Conversion Devices, Inc.Narrow band gap photovoltaic devices with enhanced open circuit voltageUS4476346 *Feb 8, 1983Oct 9, 1984Kanegafuchi Kagaku Kogyo Kabushiki KaishaPhotovoltaic deviceUS4490573 *May 20, 1981Dec 25, 1984Sera Solar CorporationSolar cellsUS4728370 *Aug 28, 1986Mar 1, 1988Sumitomo Electric Industries, Inc.Amorphous photovoltaic elementsUS4755475 *Feb 17, 1987Jul 5, 1988Sanyo Electric Co., Ltd.Method of manufacturing photovoltaic deviceUS4776894 *Aug 13, 1987Oct 11, 1988Sanyo Electric Co., Ltd.Photovoltaic deviceUS4841908 *Feb 16, 1988Jun 27, 1989Minnesota Mining And Manufacturing CompanyMulti-chamber deposition systemUS4878097 *Oct 21, 1988Oct 31, 1989Eastman Kodak CompanySemiconductor photoelectric conversion device and method for making sameUS5021100 *Dec 12, 1989Jun 4, 1991Mitsubishi Denki Kabushiki KaishaTandem solar cellUS5032884 *Feb 7, 1990Jul 16, 1991Kanegafuchi Kagaku Kogyo Kabushiki KaishaSemiconductor pin device with interlayer or dopant gradientUS5252142 *Nov 22, 1991Oct 12, 1993Canon Kabushiki KaishaPin junction photovoltaic element having an I-type semiconductor layer with a plurality of regions having different graded band gapsUS5256887 *Jul 19, 1991Oct 26, 1993Solarex CorporationPhotovoltaic device including a boron doping profile in an i-type layerUS5677236 *Feb 22, 1996Oct 14, 1997Mitsui Toatsu Chemicals, Inc.Process for forming a thin microcrystalline silicon semiconductor filmUS5700467 *Mar 21, 1996Dec 23, 1997Sanyo Electric Co. Ltd.Amorphous silicon carbide film and photovoltaic device using the sameUS5730808 *Jun 27, 1996Mar 24, 1998Amoco/Enron SolarProducing solar cells by surface preparation for accelerated nucleation of microcrystalline silicon on heterogeneous substratesUS5738732 *Jun 4, 1996Apr 14, 1998Sharp Kabushiki KaishaSolar cell and manufacturing method thereofUS5797998 *Mar 31, 1995Aug 25, 1998Pacific Solar Pty. LimitedMultiple layer thin film solar cells with buried contactsUS5913986 *Sep 19, 1997Jun 22, 1999Canon Kabushiki KaishaPhotovoltaic element having a specific doped layerUS5927994 *Jan 13, 1997Jul 27, 1999Canon Kabushiki KaishaMethod for manufacturing thin filmUS5942050 *Dec 1, 1995Aug 24, 1999Pacific Solar Pty Ltd.Method of manufacturing a multilayer solar cellUS6013155 *Jun 30, 1997Jan 11, 2000Lam Research CorporationGas injection system for plasma processingUS6100466 *Nov 23, 1998Aug 8, 2000Canon Kabushiki KaishaMethod of forming microcrystalline silicon film, photovoltaic element, and method of producing sameUS6121541 *Jul 28, 1997Sep 19, 2000Bp SolarexMonolithic multi-junction solar cells with amorphous silicon and CIS and their alloysUS6180870 *Aug 27, 1997Jan 30, 2001Canon Kabushiki KaishaPhotovoltaic deviceUS6190932 *Sep 3, 1999Feb 20, 2001Kaneka CorporationMethod of manufacturing tandem type thin film photoelectric conversion deviceUS6200825 *Sep 3, 1999Mar 13, 2001Kaneka CorporationMethod of manufacturing silicon based thin film photoelectric conversion deviceUS6222115 *Mar 14, 2000Apr 24, 2001Kaneka CorporationPhotovoltaic moduleUS6242686 *Jun 11, 1999Jun 5, 2001Sharp Kabushiki KaishaPhotovoltaic device and process for producing the sameUS6265288 *Sep 3, 1999Jul 24, 2001Kaneka CorporationMethod of manufacturing silicon-based thin-film photoelectric conversion deviceUS6288325 *May 4, 2000Sep 11, 2001Bp Corporation North America Inc.Producing thin film photovoltaic modules with high integrity interconnects and dual layer contactsUS6297443 *Feb 12, 1998Oct 2, 2001Kaneka CorporationThin film photoelectric transducerUS6307146 *Sep 23, 1999Oct 23, 2001Mitsubishi Heavy Industries, Ltd.Amorphous silicon solar cellUS6308908 *Dec 12, 1997Oct 30, 2001Darlet Marchante Technologie S.A.Machine for coiling a flat continuous element to form rollsUS6309906 *Oct 30, 1996Oct 30, 2001Universite De Neuchatel-Institut De MicrotechniquePhotovoltaic cell and method of producing that cellUS6337224 *Oct 28, 1998Jan 8, 2002Kaneka CorporationMethod of producing silicon thin-film photoelectric transducer and plasma CVD apparatus used for the methodUS6380480 *May 17, 2000Apr 30, 2002Nippon Sheet Glass Co., LtdPhotoelectric conversion device and substrate for photoelectric conversion deviceUS6392313 *Jul 15, 1999May 21, 2002Massachusetts Institute Of TechnologyMicroturbomachineryUS6395973 *Feb 23, 2001May 28, 2002Nippon Sheet Glass Co., Ltd.Photovoltaic deviceUS6444277 *Sep 9, 1994Sep 3, 2002Applied Materials, Inc.Method for depositing amorphous silicon thin films onto large area glass substrates by chemical vapor deposition at high deposition ratesUS6459034 *May 24, 2001Oct 1, 2002Sharp Kabushiki KaishaMulti-junction solar cellUS6566159 *Oct 2, 2001May 20, 2003Kaneka CorporationMethod of manufacturing tandem thin-film solar cellUS6602606 *May 18, 2000Aug 5, 2003Nippon Sheet Glass Co., Ltd.Glass sheet with conductive film, method of manufacturing the same, and photoelectric conversion device using the sameUS6632993 *Oct 2, 2001Oct 14, 2003Kaneka CorporationPhotovoltaic moduleUS6634572 *May 31, 2002Oct 21, 2003John A. BurgenerEnhanced parallel path nebulizer with a large range of flow ratesUS6645573 *Mar 3, 1999Nov 11, 2003Canon Kabushiki KaishaProcess for forming a microcrystalline silicon series thin film and apparatus suitable for practicing said processUS6750394 *Jan 10, 2002Jun 15, 2004Sharp Kabushiki KaishaThin-film solar cell and its manufacturing methodUS6777610 *Aug 16, 2002Aug 17, 2004Dai Nippon Printing Co., Ltd.Protective sheet for solar battery module, method of fabricating the same and solar battery moduleUS6793733 *Jan 25, 2002Sep 21, 2004Applied Materials Inc.Gas distribution showerheadUS6825104 *Jan 27, 2003Nov 30, 2004Interuniversitair Micro-Elektronica Centrum (Imec)Semiconductor device with selectively diffused regionsUS6825408 *Aug 21, 2002Nov 30, 2004Sharp Kabushiki KaishaStacked photoelectric conversion deviceUS6989553 *Jul 23, 2003Jan 24, 2006Matsushita Electric Industrial Co., Ltd.Semiconductor device having an active region of alternating layersUS7064263 *Sep 8, 2004Jun 20, 2006Canon Kabushiki KaishaStacked photovoltaic deviceUS7071018 *Jun 17, 2002Jul 4, 2006Bp Solar LimitedProcess for manufacturing a solar cellUS7074641 *Mar 21, 2002Jul 11, 2006Canon Kabushiki KaishaMethod of forming silicon-based thin film, silicon-based thin film, and photovoltaic elementUS7235810 *Dec 3, 1999Jun 26, 2007Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the sameUS7238545 *Apr 2, 2003Jul 3, 2007Kaneka CorporationMethod for fabricating tandem thin film photoelectric converterUS7256140 *Sep 20, 2005Aug 14, 2007United Solar Ovonic LlcHigher selectivity, method for passivating short circuit current paths in semiconductor devicesUS7264013 *May 13, 2005Sep 4, 2007Air Products And Chemicals, Inc.Enhanced purge effect in gas conduitUS7314526 *Mar 17, 2000Jan 1, 2008Lpe S.P.A.Reaction chamber for an epitaxial reactorUS7332226 *Nov 20, 2001Feb 19, 2008Nippon Sheet Glass Company, LimitedTransparent conductive film and its manufacturing method, and photoelectric conversion device comprising itUS7351993 *Dec 28, 2004Apr 1, 2008Translucent Photonics, Inc.Rare earth-oxides, rare earth-nitrides, rare earth-phosphides and ternary alloys with siliconUS7375378 *May 12, 2005May 20, 2008General Electric CompanySurface passivated photovoltaic devicesUS7402747 *Feb 18, 2004Jul 22, 2008Kyocera CorporationPhotoelectric conversion device and method of manufacturing the deviceUS20010035206 *Jan 12, 2001Nov 1, 2001Takashi InamasuThin film solar cell and method of manufacturing the sameUS20020033191 *May 30, 2001Mar 21, 2002Takaharu KondoSilicon-type thin-film formation process, silicon-type thin film, and photovoltaic deviceUS20030013280 *Dec 7, 2001Jan 16, 2003Hideo YamanakaSemiconductor thin film forming method, production methods for semiconductor device and electrooptical device, devices used for these methods, and semiconductor device and electrooptical deviceUS20030041894 *Jun 25, 2001Mar 6, 2003Solarflex Technologies, Inc.Thin film flexible solar cellUS20030044539 *Aug 7, 2002Mar 6, 2003Oswald Robert S.Process for producing photovoltaic devicesUS20030104664 *Apr 2, 2002Jun 5, 2003Takaharu KondoSilicon film, semiconductor device, and process for forming silicon filmsUS20040082097 *Oct 10, 2003Apr 29, 2004Schott GlasThin-film solar cells and method of makingUS20040187914 *Mar 24, 2004Sep 30, 2004Canon Kabushiki KaishaStacked photovoltaic element and method for producing the sameUS20040231590 *May 19, 2003Nov 25, 2004Ovshinsky Stanford R.Deposition apparatus for the formation of polycrystalline materials on mobile substratesUS20050115504 *Dec 1, 2003Jun 2, 2005Ishikawajima-Harima Heavy Industries Co., Ltd.Method and apparatus for forming thin films, method for manufacturing solar cell, and solar cellUS20050173704 *Jul 24, 2003Aug 11, 2005Canon Kabushiki KaishaSemiconductor element and its manufacturing methodUS20050189012 *Oct 28, 2003Sep 1, 2005Canon Kabushiki KaishaZinc oxide film, photovoltaic device making use of the same, and zinc oxide film formation processUS20050251990 *Jul 12, 2004Nov 17, 2005Applied Materials, Inc.Plasma uniformity control by gas diffuser hole designUS20060038182 *Jun 2, 2005Feb 23, 2006The Board Of Trustees Of The UniversityStretchable semiconductor elements and stretchable electrical circuitsUS20060060138 *Jul 25, 2005Mar 23, 2006Applied Materials, Inc.Diffuser gravity supportUS20060134496 *Nov 30, 2005Jun 22, 2006Applied Materials, Inc.Fuel cell conditioning layerUS20060137698 *Feb 23, 2006Jun 29, 2006Asthmatx, Inc.Methods for treating airwaysUS20060169317 *Apr 3, 2006Aug 3, 2006Asahi Glass Company LimitedSubstrate with transparent conductive oxide film, process for its production and photoelectric conversion elementUS20060240630 *Jan 30, 2006Oct 26, 2006Matthias BauerMethods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor depositionUS20060249196 *Apr 27, 2006Nov 9, 2006Sanyo Electric Co., Ltd.Stacked photovoltaic deviceUS20070039942 *Aug 16, 2005Feb 22, 2007Applied Materials, Inc.Active cooling substrate supportUS20070227579 *Mar 30, 2006Oct 4, 2007Benyamin BullerAssemblies of cylindrical solar units with internal spacingUS20070249898 *Dec 28, 2006Oct 25, 2007Olympus CorporationEndoscopeUS20080047599 *May 3, 2007Feb 28, 2008Benyamin BullerMonolithic integration of nonplanar solar cellsUS20080047603 *Aug 24, 2006Feb 28, 2008Guardian Industries Corp.Front contact with intermediate layer(s) adjacent thereto for use in photovoltaic device and method of making sameUS20080057220 *Jan 31, 2006Mar 6, 2008Robert BachrachSilicon photovoltaic cell junction formed from thin film doping sourceUS20080110491 *May 3, 2007May 15, 2008Solyndra, Inc.,Monolithic integration of non-planar solar cellsUS20080153280 *Dec 21, 2006Jun 26, 2008Applied Materials, Inc.Reactive sputter deposition of a transparent conductive filmUS20080156370 *Apr 11, 2006Jul 3, 2008Hahn-Meitner-Institut Berlin GmbhHeterocontact Solar Cell with Inverted Geometry of its Layer StructureUS20080160661 *Apr 5, 2007Jul 3, 2008Silicon Genesis CorporationMethod and structure for fabricating solar cells using a layer transfer processUS20080173350 *Jan 18, 2007Jul 24, 2008Applied Materials, Inc.Multi-junction solar cells and methods and apparatuses for forming the sameUS20080188033 *Feb 6, 2007Aug 7, 2008Applied Materials, Inc.Multi-junction solar cells and methods and apparatuses for forming the sameUS20080196761 *Dec 21, 2007Aug 21, 2008Mitsubishi Heavy Industries, LtdPhotovoltaic device and process for producing same* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7648892Oct 24, 2008Jan 19, 2010Applied Materials, Inc.Methods and apparatus for depositing a microcrystalline silicon film for photovoltaic deviceUS7687300 *Oct 22, 2007Mar 30, 2010Applied Materials, Inc.Method of dynamic temperature control during microcrystalline SI growthUS7741144Oct 31, 2008Jun 22, 2010Applied Materials, Inc.Plasma treatment between deposition processesUS7833885Nov 26, 2008Nov 16, 2010Applied Materials, Inc.Microcrystalline silicon thin film transistorUS7875486Jul 9, 2008Jan 25, 2011Applied Materials, Inc.Solar cells and methods and apparatuses for forming the same including I-layer and N-layer chamber cleaningUS7919398 *Jun 26, 2009Apr 5, 2011Applied Materials, Inc.Microcrystalline silicon deposition for thin film solar applicationsUS8026157Sep 2, 2009Sep 27, 2011Applied Materials, Inc.Gas mixing method realized by back diffusion in a PECVD system with showerheadUS8076222Sep 4, 2008Dec 13, 2011Applied Materials, Inc.Microcrystalline silicon thin film transistorUS8080727Nov 24, 2008Dec 20, 2011E. I. Du Pont De Nemours And CompanySolar cell modules comprising an encapsulant sheet of a blend of ethylene copolymersUS8084129Nov 24, 2008Dec 27, 2011E. I. Du Pont De Nemours And CompanyLaminated articles comprising a sheet of a blend of ethylene copolymersUS8203071Jul 23, 2008Jun 19, 2012Applied Materials, Inc.Multi-junction solar cells and methods and apparatuses for forming the sameUS8338699Jan 22, 2010Dec 25, 2012E I Du Pont De Nemours And CompanyPoly(vinyl butyral) encapsulant comprising chelating agents for solar cell modulesUS8399081Nov 2, 2009Mar 19, 2013E I Du Pont De Nemours And CompanySolar cell modules comprising encapsulant sheets with low haze and high moisture resistanceUS8399095Nov 2, 2009Mar 19, 2013E I Du Pont De Nemours And CompanySolar cells modules comprising low haze encapsulantsUS8445776Jun 1, 2009May 21, 2013E I Du Pont De Nemours And CompanySolar cell module having a low haze encapsulant layerUS8455310Jun 30, 2012Jun 4, 2013Applied Materials, Inc.Methods of manufacturing thin film transistor devicesUS8535760Aug 31, 2010Sep 17, 2013Air Products And Chemicals, Inc.Additives to silane for thin film silicon photovoltaic devicesUS8609777Jul 30, 2010Dec 17, 2013E I Du Pont De Nemours And CompanyCross-linkable encapsulants for photovoltaic cellsUS8609980Jul 30, 2010Dec 17, 2013E I Du Pont De Nemours And CompanyCross-linkable ionomeric encapsulants for photovoltaic cellsUS8895842Jun 9, 2009Nov 25, 2014Applied Materials, Inc.High quality TCO-silicon interface contact structure for high efficiency thin film silicon solar cellsUS8975513 *Jun 28, 2011Mar 10, 2015Seagate Technology LlcQuantum dot-sensitized wide bandgap semiconductor heterojunction photovoltaic devicesUS9054206 *Aug 1, 2008Jun 9, 2015Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing semiconductor deviceUS9287137Sep 28, 2012Mar 15, 2016Applied Materials, Inc.Methods for depositing a silicon containing layer with argon gas dilutionUS9328414 *Jun 30, 2008May 3, 2016Japan Display Inc.Method of manufacturing thin film semiconductor deviceUS20080223440 *Apr 25, 2008Sep 18, 2008Shuran ShengMulti-junction solar cells and methods and apparatuses for forming the sameUS20080245414 *Apr 9, 2007Oct 9, 2008Shuran ShengMethods for forming a photovoltaic device with low contact resistanceUS20080264480 *Jun 30, 2008Oct 30, 2008Soo-Young ChoiMulti-junction solar cells and methods and apparatuses for forming the sameUS20090000551 *Sep 4, 2008Jan 1, 2009Soo Young ChoiMethods and apparatus for depositing a uniform silicon film with flow gradient designsUS20090020154 *Jul 23, 2008Jan 22, 2009Shuran ShengMulti-junction solar cells and methods and apparatuses for forming the sameUS20090029530 *Jun 30, 2008Jan 29, 2009Sony CorporationMethod of manufacturing thin film semiconductor deviceUS20090029532 *Dec 27, 2007Jan 29, 2009Industrial Technology Research InstituteMethod for forming a microcrystalline silicon filmUS20090047759 *Aug 1, 2008Feb 19, 2009Semiconductor Energy Laboratory Co., Ltd.Method for manufacturing semiconductor deviceUS20090053847 *Oct 24, 2008Feb 26, 2009Soo Young ChoiMethods and apparatus for depositing a microcrystalline silicon film for photovoltaic deviceUS20090105873 *Oct 22, 2007Apr 23, 2009Yong Kee ChaeMethod of dynamic temperature control during microcrystalline si growthUS20090200551 *Sep 4, 2008Aug 13, 2009Tae Kyung WonMicrocrystalline silicon thin film transistorUS20090238972 *Mar 24, 2009Sep 24, 2009Applied Materials, Inc.Methods and apparatus for using reduced purity silane to deposit siliconUS20090242030 *Mar 26, 2009Oct 1, 2009E. I. Du Pont De Nemours And CompanyHigh performance anti-spall laminate articleUS20090250100 *Apr 3, 2009Oct 8, 2009E.I. Du Pont De Nemours And CompanySolar cell modules comprising high melt flow poly(vinyl butyral) encapsulantsUS20090263930 *Jun 26, 2009Oct 22, 2009Yong Kee ChaeMicrocrystalline silicon deposition for thin film solar applicationsUS20090288701 *Apr 27, 2009Nov 26, 2009E.I.Du Pont De Nemours And CompanySolar cell laminates having colored multi-layer encapsulant sheetsUS20100051098 *Jun 9, 2009Mar 4, 2010Applied Materials, Inc.High quality tco-silicon interface contact structure for high efficiency thin film silicon solar cellsUS20100101647 *Oct 21, 2009Apr 29, 2010E.I. Du Pont De Nemours And CompanyNon-autoclave lamination process for manufacturing solar cell modulesUS20100129665 *Nov 24, 2008May 27, 2010E.I. Du Pont De Nemours And CompanyLaminated articles comprising a sheet of a blend of ethylene copolymersUS20100136261 *Dec 1, 2009Jun 3, 2010Applied Materials, Inc.Modulation of rf returning straps for uniformity controlUS20100154867 *Nov 25, 2009Jun 24, 2010E. I. Du Pont De Nemours And CompanyMechanically reliable solar cell modulesUS20100163099 *Nov 2, 2009Jul 1, 2010E. I. Du Pont De Nemours And CompanySolar cell modules comprising encapsulant sheets with low haze and high moisture resistanceUS20100180943 *Jan 22, 2010Jul 22, 2010E. I. Du Pont De Nemours And CompanyPoly(vinyl butyral) encapsulant comprising chelating agents for solar cell modulesUS20110023943 *Jul 30, 2010Feb 3, 2011E. I. Du Pont De Nemours And CompanyCross-linkable encapsulants for photovoltaic cellsUS20110053356 *Sep 2, 2009Mar 3, 2011Applied Materials,Inc.Gas mixing method realized by back diffusion in a pecvd system with showerheadUS20110088762 *Sep 10, 2010Apr 21, 2011Applied Materials, Inc.Barrier layer disposed between a substrate and a transparent conductive oxide layer for thin film silicon solar cellsUS20110114177 *Jul 19, 2010May 19, 2011Applied Materials, Inc.Mixed silicon phase film for high efficiency thin film silicon solar cellsUS20110126875 *Dec 1, 2009Jun 2, 2011Hien-Minh Huu LeConductive contact layer formed on a transparent conductive layer by a reactive sputter depositionUS20110275200 *Apr 29, 2011Nov 10, 2011Applied Materials, Inc.Methods of dynamically controlling film microstructure formed in a microcrystalline layerUS20120003773 *Jun 28, 2011Jan 5, 2012Seagate Technology LlcQuantum dot sensitized wide bandgap semiconductor photovoltaic devices & methods of fabricating sameUS20130000706 *Sep 13, 2012Jan 3, 2013International Business Machines CorporationTandem solar cell with improved tunnel junctionUS20130017645 *Sep 13, 2012Jan 17, 2013Sharp Kabushiki KaishaPhotoelectric conversion device and method of producing the sameUS20140102530 *Mar 15, 2013Apr 17, 2014Institute Of Nuclear Energy Research Atomic Energy Council, Executive YuanMicrocrystalline silicon thin film solar cell and the manufacturing method thereofDE102008063737A1 *Dec 18, 2008Jun 24, 2010Forschungszentrum Jülich GmbHVerfahren zur Abscheidung von mikrokristallinem Silizium auf einem SubstratDE102008063737A9 *Dec 18, 2008Oct 7, 2010Forschungszentrum Jülich GmbHVerfahren zur Abscheidung von mikrokristallinem Silizium auf einem SubstratEP2298955A1Sep 13, 2010Mar 23, 2011Air Products And Chemicals, Inc.Additives to silane for thin film silicon photovoltaic devicesWO2010024814A1 *Aug 28, 2008Mar 4, 2010Applied Materials, Inc.Methods and apparatus for depositing a uniform silicon film with flow gradient designsWO2012016053A1Jul 28, 2011Feb 2, 2012E. I. Du Pont De Nemours And CompanyCross-linkable ionomeric encapsulants for photovoltaic cellsWO2014100301A1Dec 19, 2013Jun 26, 2014E. I. Du Pont De Nemours And CompanyCross-linked polymers and their use in photovoltaic modulesWO2015171575A1May 5, 2015Nov 12, 2015E. I. Du Pont De Nemours And CompanyEncapsulant composition comprising a copolymer of ethylene, vinyl acetate and a third comonomer* Cited by examinerClassifications U.S. Classification438/478, 136/261, 257/E21.102, 427/569International ClassificationH01L31/00, H01L21/20, H05H1/24, H01L21/36Cooperative ClassificationY02P70/521, C30B25/105, H01J37/32495, H01J37/32082, H01L31/1824, C30B29/06, H01J37/32449, Y02E10/545, H01L21/02532, H01L21/02576, H01L21/0262, H01L21/0237, H01L21/02579, C23C16/24European ClassificationH01J37/32M8, H01L31/18C5B, H01L21/205B, C30B25/10B, C30B29/06, C23C16/24Legal EventsDateCodeEventDescriptionMay 5, 2007ASAssignmentOwner name: APPLIED MATERIALS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOI, SOO YOUNG;TAKEHARA, TAKAKO;WHITE, JOHN M;AND OTHERS;REEL/FRAME:019252/0465;SIGNING DATES FROM 20060721 TO 20060727Owner name: APPLIED MATERIALS, INC.,CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOI, SOO YOUNG;TAKEHARA, TAKAKO;WHITE, JOHN M;AND OTHERS;SIGNING DATES FROM 20060721 TO 20060727;REEL/FRAME:019252/0465Owner name: APPLIED MATERIALS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOI, SOO YOUNG;TAKEHARA, TAKAKO;WHITE, JOHN M;AND OTHERS;SIGNING DATES FROM 20060721 TO 20060727;REEL/FRAME:019252/0465Oct 5, 2010CCCertificate of correctionSep 13, 2013REMIMaintenance fee reminder mailedFeb 2, 2014LAPSLapse for failure to pay maintenance feesMar 25, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140202RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

value: This website is a search engine provided by Google. Handling over 3.5 billion searches per day, it has a 92% share of the global search engine market.


text:
US stocks give up an early gain following slowdown in manufacturing | Fox News
US stocks give up an early gain following slowdown in manufacturing
Print FILE - This Oct. 8. 2014, file photo, shows a Wall Street address carved into the side of a building in New York. U.S. stocks are opening the year on a strong note, but energy stocks slipped as the price of crude oil resumed its slide, Friday, Jan. 2, 2015. (AP Photo/Mark Lennihan, File)
NEW YORK – U.S. stocks turned slightly lower as signs of a slowdown in manufacturing growth weighed on investor sentiment. The Dow Jones industrial was down 28 points, or 0.2 percent, at 17,793 as of 11:55 a.m. Eastern time Friday. The Dow as up as much as 128 points in early trading. The Standard & Poor's 500 index fell five points, or 0.3 percent, to 2,053. The Nasdaq composite fell 24 points, or 0.5 percent, to 4,712. Oil turned higher after an early slump. U.S. crude was up 32 cents at $53.59 a barrel. Oil lost 45 percent last year, its biggest yearly loss since 2008. Bond prices rose. The yield on the 10-year Treasury note fell to 2.11 percent. Advertisement

value: This website is an American multinational conservative cable news television channel based in New York City. It is owned by Fox News Media, which itself is owned by the Fox Corporation.


text:
Mack Bolan: Return to Vietnam by Don Pendleton: Gold Eagle Books Mass Market Paperback - OwlsBooks
Mack Bolan: Return to Vietnam
Published by Gold Eagle Books
Very Good copy, cover and pages show some wear from reading and storage. Binding may have light creases. Lots of life left in these pages. Bookseller Inventory # 2630120878
Title: Mack Bolan: Return to Vietnam

value: This website is an e-commerce global online marketplace with seven websites that offer books, fine art, and collectables from sellers in over 50 countries. Launched in 1996, it specialises in used, rare and out-of-print books.


text:
Patent US20070218620 - Structures and methods for making strained mosfets - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few...http://www.google.com/patents/US20070218620?utm_source=gb-gplus-sharePatent US20070218620 - Structures and methods for making strained mosfetsAdvanced Patent SearchPublication numberUS20070218620 A1Publication typeApplicationApplication numberUS 11/754,627Publication dateSep 20, 2007Filing dateMay 29, 2007Priority dateJan 5, 2004Also published asCN1638067A, CN100342507C, US7247912, US7749842, US20050145954Publication number11754627, 754627, US 2007/0218620 A1, US 2007/218620 A1, US 20070218620 A1, US 20070218620A1, US 2007218620 A1, US 2007218620A1, US-A1-20070218620, US-A1-2007218620, US2007/0218620A1, US2007/218620A1, US20070218620 A1, US20070218620A1, US2007218620 A1, US2007218620A1InventorsHuilong Zhu, Steven Bedell, Bruce Doris, Ying ZhangOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (3), Classifications (21), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetStructures and methods for making strained mosfets
US 20070218620 A1Abstract
A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few defects. The strained Si fin is formed by growing Si on the side of a relaxed SiGe block. A dielectric gate, such as, for example, an oxide, a high “k” material, or a combination of the two, may be formed on a surface of the strained Si film. Additionally, without substantially affecting the stress in the strained Si film, the relaxed SiGe block may be removed to allow a second gate oxide to be formed on the surface previously occupied by the relaxed SiGe block. Accordingly, a semiconductor device having a strained Si fin vertically oriented on a non-conductive substrate may be formed where the strained Si film is oriented such that it may form a channel of small dimensions allowing access to both sides and top in order to from single gate, double gate, or more gate MOSFETs and finFETs with a channel having a reduced number of defects and/or reduced dimensions. Images(11) Claims(24)
1. A method for forming a structure, comprising: forming a relaxed SiGe block on a substrate; and forming a strained Si film on a side of the relaxed SiGe block to form a strained channel region. 2. The method of claim 1, further comprising forming a gate comprising at least one of an oxide and a high k material on at least one side of the strained Si film. 3. The method of claim 2, further comprising removing the relaxed SiGe block to expose a side of the strained Si film and forming a gate comprising at least one of an oxide and a high k material on the exposed side of the strained Si film. 4. The method of claim 2, wherein the strained Si film is between about 50 Å and 200 Å thick, and the gate is between about 9 Å and 20 Å thick. 5. The method of claim 1, wherein the strained Si film is selectively epitaxially grown. 6. The method of claim 1, further comprising forming a first nitride spacer on a top of the relaxed SiGe block and forming a second nitride spacer on a second side of the relaxed SiGe block and a side of the first nitride spacer. 7. The method of claim 1, wherein the strained Si film has a height greater than a thickness. 8. The method of claim 1, wherein the SiGe block is formed by forming a relaxed SiGe layer on the substrate and etching away portions of the relaxed SiGe layer to form the relaxed SiGe block. 9. The method of claim 1, further comprising: forming a thin oxide layer over the relaxed SiGe layer; forming a polysilicon layer over the thin oxide layer; forming a photoresist on a portion of the polysilicon layer; and etching away an exposed portion of the polysilicon layer, and a portion of the oxide layer to expose a portion of the relaxed SiGe layer; and forming a first nitride spacer on a top portion of the relaxed SiGe layer adjacent to an edge of the thin oxide layer and the polysilicon layer. 10. The method of claim 9, further comprising: etching an exposed portion of the relaxed SiGe layer to expose a portion of the substrate; forming a second nitride spacer on the exposed substrate adjacent an edge of the relaxed SiGe layer and first nitride spacer; and etching away remaining portions of the polysilicon layer, the thin oxide layer and a portion of the relaxed SiGe layer underlying the thin oxide layer to form the relaxed SiGe block with the first and second nitride spacers. 11. A method, comprising: forming a relaxed SiGe block on an oxide substrate; forming a first nitride spacer on a first portion of the relaxed SiGe block; forming a second nitride spacer on the oxide substrate adjacent another portion of the relaxed SiGe block and a portion of the first nitride spacer; and epitaxially forming a strained Si film on an exposed side of the relaxed SiGe block. 12. The method of claim 11, wherein the strained Si film has a height greater than a thickness. 13. The method of claim 12, wherein the strained Si film forms a fin of strained Si film vertically oriented on the oxide substrate. 14. The method of claim 12, further comprising forming a gate comprising at least one of an oxide and a high k material on a first surface of the strained Si film opposite the SiGe block. 15. The method of claim 11, wherein the strained Si film is at a height substantially equal to a height of the SiGe block. 16. The method of claim 15, further comprising: forming a gate comprising at least one of an oxide and a high k material on a top of the strained Si film; removing the first and second nitride spacers; removing the SiGe block to expose a second side of the strained Si film; and forming a gate comprising at least one of an oxide and a high k material on a second side of the strained Si film. 17. A method of forming a semiconductor structure, comprising: forming a channel having a fin of strained Si vertically oriented on a non-conductive substrate; forming a gate comprising at least one of an oxide and a high k material on a first side, a second side and a top of the strained Si film; forming a poly silicon layer adjacent the at least one of an oxide and a high k material on the first side, the second side and the top of the strained Si film; and forming an oxide layer partially on the poly silicon layer. 18. The method of claim 17, wherein the strained Si film is between about 50 Å and 200 Å thick. 19. The method of claim 17, wherein the strained Si film is epitaxially grown on a block of relaxed SiGe, wherein the relaxed SiGe comprises a range of Ge ranging from about 0% to 100%. 20. The method of claim 17, wherein the Si film is a low defect strained Si film. 21. The method of claim 17, further comprising forming a second poly silicon layer over the oxide layer and the poly silicon layer. 22. The method of claim 17, wherein the oxide layer is formed substantially in a vertical orientation. 23. The method of claim 17, wherein the oxide layer is formed on a side wall of the fin. 24. A method of forming semiconductor structure, comprising: providing a strained Si vertically oriented fin on a non-conductive substrate; an oxide layer surrounding the Si vertically oriented fin; covering the oxide material surrounding the Si vertically oriented fin with a polysilicon layer; and forming an oxide layer partially on the poly silicon layer; providing a polysilicon spacer on the oxide layer; and forming a third polysilicon layer over the polysilicon spacers and the polysilicon layer. Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The invention generally relates to making MOSFETs with vertical gates of strained Si, and more particularly relates to making single gate and double gate MOSFETS and finFETS with vertical gates of strained Si. 2. Background Description As semiconductor devices shrink, traditional device fabrication techniques have approached practical limits in size scaling. For example, as channel lengths shrink below about 50 nm, devices start to exhibit short channel effects including threshold voltage rolling off for shortened channel lengths. Unwanted short channel effects may be reduced by higher doping concentrations, which lead to the unwanted effects of carrier mobility degradation, increased parasitic junction capacitance, and increased sub-threshold swing if doping concentrations become too high. One method to minimize short channel and reverse short channel effects includes striking an optimum doping profile by well controlled implantation and annealing. However, carefully controlling implantation and annealing adds costs to the fabrication process, and are ultimately limited in effectiveness as channel lengths are further reduced. Scaling limits imposed due to the limitation of gate oxide thickness and source/drain junction depth may also arise to impair function of the smaller devices. Another method to achieve further reduced scale includes difficult to manufacture profiles for the channel. Such profiles include double gate, triple gate, quadruple gate, omega-gate, pi-gate, and finFET MOSFET designs. Some of these designs are plagued with design problems such as gate alignment errors leading to increased parasitic capacitance. Another possible way to avoid some scaling problems is to improve device performance by improving material performance. For example, strained Si produces higher mobility of carriers resulting in faster and/or lower power consumption devices. Due to changes in strained Si crystalline structure (i.e. its symmetry and lattice constant are different due to its strain state), a strained Si film has electronic properties that are superior to those of bulk Si. Specifically, the strained Si could have greater electron and hole mobilities, which translate into greater drive current capabilities for n-type and p-type transistors, respectively. Accordingly, devices incorporating strained Si may have improved performance without necessarily reducing device size. However, where the strained Si does allow for further scaling, performance improvement will be further improved. It should be noted, however, an important criteria in enabling high-performance devices by utilizing strained Si is the fabrication of a low-defect-density strained Si film. In particular, reducing the number of dislocations in the strained Si film is especially important in order to reduce leakage and improve carrier mobility. Growing a Si layer on a substrate having lattice parameters different from the Si, generates the strained Si film. Accordingly, the number of defects in the strained Si film may be proportional to the number of defects in the underlying substrate on which the film is grown. An increase in the number of dislocations in the Si channel can increase the leakage current in the device while in the “off” stage. When formed improperly, the strained Si film can contain a high number of defects and the subsequent strained Si film will then exhibit poor performance characteristics, and any benefits of using a strained Si film will be substantially negated. Accordingly, producing strained Si films having minimal defects such as dislocations is desirable for further reduction in semiconductor device size and power requirements. Thin strained Si films having few defects may lead to improved semiconductor device performance. SUMMARY OF THE INVENTION In one aspect of the invention, a method comprises forming a relaxed SiGe block on a substrate and forming a strained Si film on the substrate adjacent at least one side of the relaxed SiGe block. The method further includes forming a gate oxide on a side of the strained Si film to form a strained channel region. In another aspect, the invention includes a method comprising forming a relaxed SiGe block on an oxide substrate and forming a first nitride spacer on a top of the relaxed SiGe block. A second nitride spacer is formed on the oxide substrate adjacent a first side of the relaxed SiGe block and a side of the first nitride spacer, and a strained Si film is epitaxially formed on a second side of the relaxed SiGe block. In still another aspect, the invention includes a channel for a semiconductor device comprising a fin of strained Si vertically oriented on a non-conductive substrate.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-8 illustrate steps in forming an embodiment in accordance with the invention; FIGS. 9-14 illustrate steps in forming devices in accordance with the invention; and FIGS. 15-19 illustrate further steps in forming an embodiment in accordance with the invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION The invention relates to forming MOSFETs with channels of strained Si. In the invention, transistor performance is enhanced by creating thin films of strained Si. Due to the small dimension of the strained Si, when it is formed, such as by epitaxial growth techniques, the defect density (i.e. dislocation) is typically very low. Such a low defect film may be produced by forming a vertical SiGe bar or block on a relaxed SiGe-on-oxide wafer. One side of the SiGe bar or block may be covered with nitride. The other side of the vertical SiGe bar or block may be covered with a small dimensioned Si film using a selective eptiaxial growth process. The Si film will be strained due to mismatch of the lattice constants with the SiGe substrate. Due to the small dimensions of the Si film and the relaxed structure of the SiGe substrate, the tendency for dislocation formation is reduced. After completion, the strained Si can be subjected to further processing to build various types of MOSFETS such as finFETs with single, double, or more gates. FIG. 1 illustrates a relaxed SiGe layer 12 on an oxide wafer 10. Although an oxide wafer is used in this example, any non-conductive substrate suitable for semiconductor device fabrication may be used. The relaxed SiGe layer 12 may be formed on the oxide wafer 10 by any of the suitable methods known in the art such as wafer binding or oxygen implantation annealing. In one embodiment, the SiGe layer 12 may range between 30 nm and 80 nm in thickness, although other thicknesses are contemplated by the invention. FIG. 2 shows a thin oxide layer 14 deposited over the relaxed SiGe layer 12. A first polysilicon layer 16 is formed on the oxide layer 14. Next, a photoresist 18 is deposited on the first polysilicon layer 16 and patterned so a portion of the first polysilicon layer 16 is covered by the photoresist 18 and a portion of the first polysilicon layer 16 is exposed. Typical thicknesses for the thin oxide layer 14 range from about 5 nm to 20 nm, and 40 nm to 100 nm for the first polysilicon layer 16. Each layer is formed by methods which are well known in the art. FIG. 3 illustrates the results of an etching process where the exposed portion of the first polysilicon layer 16 and underlying thin oxide layer 14 are etched away leaving a portion of the first polysilicon 16. The etching process uses known methods to selectively etch polysilicon and oxide. The photoresist layer 18 has also been removed after etching the first polysilicon 16 and oxide layer 14. Accordingly, a first portion of the SiGe layer 12 lies exposed and a second portion of the SiGe layer 12 is covered with the thin oxide layer 14 and first polysilicon layer 16. Next, a first nitride spacer 20 is formed on top of the SiGe layer 12 abutting the edge of the thin oxide layer 14 and first polysilicon layer 16 using any of the nitride forming processes well known in the art. FIG. 4 shows a further etching step in which the exposed SiGe layer 12 is selectively etched using an etching process similar to those described with reference to FIG. 3. In FIG. 4, the portion of the relaxed SiGe layer 12 not covered by the first nitride spacer 20, and the thin oxide layer 14 and first polysilicon layer 16, is etched away to expose a portion of the underlying oxide wafer 10. A second nitride spacer 22 is then formed on the exposed portion of the oxide wafer 10, abutting the edges of the etched relaxed SiGe layer 12. The first nitride spacer 20 lies adjacent to a second larger nitride spacer 22. FIG. 5 illustrates the results of selectively etching the remaining portions of the first polysilicon layer 16 and thin oxide layer 14. The portion of the relaxed SiGe layer 12 underlying the thin oxide layer 14 and first polysilicon layer 16 is etched away in this process. Consequently, the relaxed SiGe shaped as a SiGe block 24 remains from the original relaxed SiGe layer 12 on top of the oxide wafer 10. The SiGe block 24 is surrounded on one side by the second nitride layer 22 and on the top by the first nitride spacer 20, leaving one side of the SiGe block 24 exposed. FIG. 6 illustrates a “strained” Si film 26 epitaxially grown on the exposed side of the SiGe block 24. A selective growing process is used so that the Si film 26 is formed only on the exposed portion of the SiGe block 24. In this process, the Si film 26 has a height greater than its thickness and is vertically oriented on the surface of the oxide wafer 10. Because the Si film 26 may be formed with substantially any aspect ratio (height divided by thickness) including those greater than 1, the Si film 26 may be characterized as a “fin” vertically oriented on the oxide wafer 10. Additionally, the Si film 26 may be approximately the same height as the SiGe block 24. Accordingly, the height of the Si film 26 may be controlled by adjusting the height of the layer of the relaxed SiGe layer 12. The height of the SiGe layer 12 may be controlled during its formation by methods well known in the art. Furthermore, the thickness of the Si film 26 may be controlled during the growing process by suitable methods well know in the art of device fabrication. The Si film 26 may range from about 50 Å (Angstroms) to about 200 Å in thickness, although other thicknesses may be used where needed. The Si film 26 may be used as the channel in a semiconductor device in virtually any type of device benefiting from a channel having a reduced number of defects and/or having small dimensions. Accordingly, at least one gate oxide may be formed on a portion of the Si channel with source/drain regions formed in the Si film 26 on either side of the gate oxide. The resulting structure, because it is vertically oriented, allows access to both sides and a top of the channel from above the substrate. This geometry allows the gate oxide to surround the channel, and allow for almost total depletion of the channel to be achieved in the off state. It also allows both sides of the source/drain regions to be accessed for better doping and better lead connectivity. By growing the Si film 26 on a surface of the relaxed SiGe block 24, the number of defects such as dislocations in the resulting Si film 26 are reduced. Dislocations in the Si film 26 are also minimized because only a thin film of small size is grown. Additionally, the strained Si film acquires its internal strain due to its crystal lattice being formed on the SiGe crystal lattice. That is, the SiGe block 24 has a crystal lattice constant (different dimensions between the atoms) than that of the Si film, i.e., standing alone, Si would normally have a smaller lattice constant than the SiGe because the lattice constant of the Si material does not match the lattice constant of the SiGe. However, in the structure of the invention, the lattice structure of the Si layer will tend to match the lattice structure of the SiGe. By virtue of the lattice matching of the Si (which normally is smaller) to the SiGe mask, the Si layer is placed under a tensile stress. That is, the SiGe mask will try to obtain an equilibrium state thus resulting in a stress of an Si sidewall layer formed on the SiGe. This volume of stressed Si may act as a strained channel. Accordingly, the Si film 26 may be described as a low defect strained Si fin or channel. FIG. 7 shows the formation of a gate oxide 28 using ion implantation on the exposed side of the Si film 26. Vt (threshold voltage) ion implantation techniques may be used, for example, and the implantation angle may be tilted towards gate oxide 28 on the side. Examples of gate oxide 28 thicknesses range from about 9 Å to about 20 Å, although other thicknesses may be formed when required. It is also possible to use high “k” materials, such as HfO2, to replace the oxide as a gate dielectric. FIG. 8 shows a second polysilicon layer 30 deposited over the first and second nitride spacers, 20 and 22, SiGe block 24, Si film 26 and gate oxide 28. Although the second polysilicon layer 30 is shown as a conformal layer, a non-conformal layer, or a layer with a topography somewhere between conformal and non-conformal may be formed as required for subsequent steps of device formation. As an example, the polysilicon layer 30 may range from a thickness of about 700 Å to about 1500 Å. From the configuration illustrated in FIG. 8, various devices may be fabricated including, for example, strained Si MOSFETs such as, for example, a finFET with a single strained gate or a finFET with a strained double gate. FIGS. 9-14 show an example of fabricating a single-gate device, and FIGS. 15-19 show an example of fabricating a double-gate finFET type device. Additionally, a tri-gate device, with the gte dielectric wrapping around the top and two sides of the strained Si film may also be fabricated from the structure shown in FIG. 8. Although examples of a single-gate device and double-gate finFET type device are shown, any type of device which may benefit from a vertical strained Si film with reduced dislocations may be fabricated from the illustrated structure shown in FIG. 8. Referring to FIG. 9, a top view of the device being fabricated is illustrated with a photoresist 102 deposited and patterned over the second polysilicon layer 30. As shown in FIG. 9, the photoresist 102 is deposited over the second polysilicon layer 30 in the region of the Si film 26 which will form the gate of the resulting device. FIG. 10 illustrates a side view of the structure of FIG. 9 with the photoresist 102 over the second polysilicon layer 30. FIG. 11 illustrates a top view of the resulting structure after etching the photoresist 102 of FIG. 9 using etching processes known in the art such as wet etching. In particular, the etching step leaves what will become two source/drain regions 104, one on either side of a gate region 106. In the source/drain regions 104, the oxide wafer 10, gate oxide 28 on the side and top of the underlying Si film 26, and second nitride spacer 22 are exposed. The Si film 26 is not visible in FIG. 11. FIG. 12 illustrates a cross section of the device shown in FIG. 11. As illustrated in FIG. 12, an ion implantation is performed in the source/drain regions 104 to form extensions on either side of the gate region 106. Any ion implantation process appropriate for source/drain implantation for the device being fabricated may be used as is well known in the art. Large tilt angle ion implantation, with energy levels of, for example, of about 0.2-1 keV for boron implantation or 1-2 keV for arsenic, may additionally be used. FIG. 13 illustrates a top view of the device being fabricated after nitride spacers 108 are formed by nitride deposition onto the oxide wafer 10 adjacent the second polysilicon layer 30, and subsequent etching. FIG. 14 illustrates the nitride spacers 108 overlaying the gate oxide 28 and second nitride spacer 22. After forming the nitride spacers 108, further processing steps including source/drain implantation and annealing may be carried out, as appropriate for the device being fabricated. Starting with the structure shown in FIG. 8, FIG. 15 illustrates a subsequent step in the formation of a strained Si double gate finFET, which is an example of another type of device in which the strained Si film included in the invention may be implemented. As shown in FIG. 15, an oxide film 202 is deposited, and planarized using, for example, CMP (chemical mechanical planarizing). The remaining oxide film 202 is then etched leaving a portion of the second polysilicon layer 30 exposed above the oxide film 202. The oxide film 202 may be deposited using, for example, directional HDP (high density plasma) to preferentially deposit most of the oxide on the flat surfaces and less oxide on the top of the polysilicon 30 in the region above the nitride spacers, 20 and 22. FIG. 16 illustrates etching a portion of the second polysilicon layer 30 to leave a portion of the first and second nitride layers, 20 and 22, exposed. Suitable etching processes may include any process to selectively etch polysilicon and any etching process, such as a wet etch, to selectively etch the oxide. After etching, the first and second nitride spacers, 20 and 22, are exposed and protrude above the second polysilicon layer 30. The second polysilicon layer 30 will form a raised region in the vicinity of the bases of the first and second nitride spacers, 20 and 22, and gate oxide 28. FIG. 17 illustrates the results of wet selective etching of the two nitride spacers, 20 and 22 a wet etching of the SiGe block 24. Throughout the fabrication process, typical etchants which may be used to etch nitride include, for example, fluorine and chlorine. Selective etching of Si3N4 to SiO2 may be performed with a boiling H3PO4 solution (e.g., 85% H3PO4 at 180� C.) because this solution attacks SiO2 very slowly. The etch rate is ˜10 nm/min for Si3N4, but less than 1 nm/min for SiO2. Si3N4 is etchable at room temperature in concentrated HF or buffered HF. However, HF also etches SiO2. Using a reactive ion plasma etching process, the following etch chemistries may be used for Si3N4: CHF3/O2; CH2F2; CH2CHF2. By removing the SiGe block 24 and the first and second nitride spacers, 20 and 22, the strained Si 26 film has a side exposed for further processing, such as, for example, adding another gate oxide. FIG. 18 illustrates forming a second gate oxide 208 by a gate oxidation process which forms a thin oxide layer 204 and 205 over the exposed portions of the device and Si film 26, respectively. In particular, the portion of the thin oxide layer 205 formed over the Si film 26 constitutes a second gate oxide 208 portion of the gate oxide 205. The gate oxide 205 also includes the first gate oxide 207 formed in an earlier step. The second gate oxide 208 may be formed by, for example, a thermal oxide growing process to produce a high quality oxide. Also shown in FIG. 18 is a thin polysilicon layer deposited over the surface of the device. The structure is then subjected to a direct etch to form thin polysilicon spacers 206 on the sides of the thin oxide layer 204. In particular, a thin polysilicon spacer 206 is formed adjacent the second gate oxide 208. The polysilicon spacers 206 may protect the gate oxide 208 from further etching processes. The thin polysilicon spacers 206 may be, for example, about 100 Å thick. Additionally, the thin polysilicon spacers 206 are formed to leave portions of the thin oxide layer 204 exposed on the top portions of the second polysilicon layer 30. FIG. 19 illustrates etching the exposed portions of the thin oxide layer 204. Any process which selectively etches an oxide layer may be used to remove the exposed portions of the thin oxide layer 204. After the oxide etching is completed, polysilicon is deposited to form a third polysilicon layer 210 over the substrate. The resulting structure includes a fin of strained Si 26 standing vertical to the oxide wafer 10 surrounded on its sides and top by a gate oxide 205. Both of the sides of the vertical fin of strained Si 26 are accessible from above the surface of the oxide wafer 10. Furthermore, the vertical fin of strained Si 26 also includes source/drain regions with both of their sides and top accessible from above the oxide wafer 10. It is possible to continue processing the device illustrated in FIG. 19 to produce a completed double-gate finFET device having a strained Si film with fabrication steps well known in the art. While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. For example, the invention can be readily applicable to bulk substrates. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8021949 *Dec 1, 2009Sep 20, 2011International Business Machines CorporationMethod and structure for forming finFETs with multiple doping regions on a same chipUS8796085 *Jul 11, 2013Aug 5, 2014Viktor KoldiaevVertical super-thin body semiconductor on dielectric wall devices and methods of their fabricationUS20140106523 *Jul 11, 2013Apr 17, 2014Viktor KoldiaevVertical Super-Thin Body Semiconductor on Dielectric Wall Devices and Methods of Their Fabrication* Cited by examinerClassifications U.S. Classification438/212, 257/E21.442, 257/E29.298, 257/E29.275, 438/230, 257/E21.415International ClassificationH01L21/20, H01L21/336, H01L29/78, H01L29/76, H01L29/94, H01L29/786, H01L21/8238, H01L31/062Cooperative ClassificationH01L29/66795, H01L29/785, H01L29/7842, H01L29/78687European ClassificationH01L29/66M6T6F16F, H01L29/78R, H01L29/78SLegal EventsDateCodeEventDescriptionApr 11, 2014SULPSurcharge for late paymentApr 11, 2014FPAYFee paymentYear of fee payment: 4Feb 14, 2014REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services