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Patent US20090089510 - Speculative read in a cache coherent microprocessor - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative...http://www.google.com/patents/US20090089510?utm_source=gb-gplus-sharePatent US20090089510 - Speculative read in a cache coherent microprocessorAdvanced Patent SearchPublication numberUS20090089510 A1Publication typeApplicationApplication numberUS 11/864,363Publication dateApr 2, 2009Filing dateSep 28, 2007Priority dateSep 28, 2007Also published asUS8930634, US20140164714Publication number11864363, 864363, US 2009/0089510 A1, US 2009/089510 A1, US 20090089510 A1, US 20090089510A1, US 2009089510 A1, US 2009089510A1, US-A1-20090089510, US-A1-2009089510, US2009/0089510A1, US2009/089510A1, US20090089510 A1, US20090089510A1, US2009089510 A1, US2009089510A1InventorsWilliam Lee, Thomas Benjamin BergOriginal AssigneeMips Technologies, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (7), Classifications (8), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSpeculative read in a cache coherent microprocessor
US 20090089510 A1Abstract
A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.
a plurality of processing cores; and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, said cache coherence manager comprising:
a request unit configured to receive a coherent request from a first one of the plurality of cores and to selectively issue a speculative request in response;
an intervention unit configured to send an intervention message associated with the coherent request to the plurality of cores;
a memory interface unit configured to receive the speculative request and to selectively forward the speculative request to a memory; and
a response unit configured to supply data associated with the coherent request to the first one of the plurality of cores.
2. The microprocessor of claim 1 wherein said memory interface unit comprises first, second and third tables
3. The microprocessor of claim 2 wherein an entry in said first table represents an index to said second table and wherein an entry in said second table represents an index to said third table.
4. The microprocessor of claim 3 wherein an index to said first table is allocated before a response to the intervention message is stored in the first table and before the speculative request is received by the memory interface unit.
5. The microprocessor of claim 4 wherein an index to said second table is allocated when the speculative request is stored in the memory interface unit.
6. The microprocessor of claim 5 wherein an index to said third table is allocated when the speculative request is issued to the memory.
7. The microprocessor of claim 3 wherein said request unit comprises:
a fourth table storing a plurality of entries each associated with a different one of a plurality of pending coherent requests; and a logic block configured to compare an address associated with the received coherent request to the plurality of addresses stored in the fourth table to determine if there is an address match, said logic block configured to issue the speculative request if an address match is not detected, said request unit further configured to assign an identifier to the received coherent request, said identifier representing the index to the first entry in the first table. 8. The microprocessor of claim 3 wherein said request unit comprises:
a fourth table storing a plurality of entries each associated with a different one of a plurality of pending coherent requests; and a logic block configured to issue the speculative request and to subsequently compare an address associated with the received coherent request to the plurality of addresses stored in the fourth table to determine if there is an address match, said logic block configured to cancel the speculative request if an address match is detected, said request unit further configured to assign an identifier to the received coherent request, said identifier representing the index to the first entry in the first table. 9. The microprocessor of claim 2 wherein said request unit is configured not to issue the speculative request unless a number of pending speculative requests not having intervention responses is less than a number of possible entries in the third table.
10. A method of operating a microprocessor, said microprocessor comprising a plurality of processing cores and a cache coherence manager configured to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the method comprising:
receiving a coherent request from a first one of the plurality of cores; selectively issuing a speculative request in response to the received coherent request; sending an intervention message associated with the coherent request to the plurality of cores; and selectively forwarding the speculative request to a memory. 11. The method of claim 10 further comprising:
defining an entry in a first table for use as an index to said second table; and defining an entry in a second table for use as an index to a third table; said first, second and third tables being disposed in the cache coherence manager. 12. The method of claim 11 further comprising:
allocating an index to said first table before a response to the intervention message is stored in the first table and before the speculative request is stored in a first queue. 13. The method of claim 12 further comprising:
allocating an index to said second table when the speculative request is stored in a second queue. 14. The method of claim 13 further comprising:
allocating an index to said third table when the speculative request is issued to the memory. 15. The method of claim 14 further comprising:
comparing an address associated with the coherent request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests; issuing the speculative request if an address match is not detected; assigning an identifier to the issued speculative request; and using said identifier as an index to the first entry stored in the first table. 16. The method of claim 14 further comprising:
issuing the speculative request; comparing an address associated with the issued speculative request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests; canceling the speculative request if an address match is detected; assigning an identifier to the issued speculative request; and using said identifier as an index to the first entry stored in the first table. 17. The method of claim 14 further comprising:
issuing the speculative request only if a number of pending speculative requests not having intervention responses is less than a number of possible entries in the third table. 18. A computer readable storage medium including instructions defining logic blocks of a microprocessor comprising a plurality of processing cores and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the computer readable storage medium adapted for use by an electronic design automation application executed by a computer, wherein the logic blocks are configured to perform an operation comprising:
receiving a coherent request from a first one of the plurality of cores; selectively issuing a speculative request in response to the request received from the first one of the plurality of cores; sending an intervention message associated with the coherent request to the plurality of cores; and selectively forwarding the speculative request to a memory. 19. The computer readable storage medium of claim 18 wherein the logic blocks are configured to perform an operation comprising:
defining an entry in a first table for use as an index to a second table; and defining an entry in the second table for use as an index to a third table, said first, second and third tables being disposed in the cache coherence manager. 20. The computer readable storage medium of claim 19 wherein the logic blocks are configured to perform an operation comprising:
allocating an index to said first table before a response to the intervention message is stored in the first table and before the speculative request is stored in a first queue; allocating an index to said second table when the speculative request is stored in a second queue; and allocating an index to said third table when the speculative request is issued to the memory. 21. The computer readable storage medium of claim 20 wherein the logic blocks are configured to perform an operation comprising:
comparing an address associated with the coherent request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests; issuing the speculative request if an address match is not detected; assigning an identifier to the issued speculative request; and using said identifier as an index to the first entry stored in the first table. 22. The computer readable storage medium of claim 20 wherein the logic blocks are configured to perform an operation comprising:
issuing the speculative request; comparing an address associated with the issued speculative request to a plurality of stored addresses to detect if there is an address match, each stored address being associated with a different one of a plurality of pending coherent requests; canceling the speculative request if an address match is detected; assigning an identifier to the issued speculative request; and using said identifier as an index to the first entry stored in the first table. 23. A microprocessor comprising:
a plurality of processing cores; and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, said cache coherence manager comprising: a plurality of configurable ports; a plurality of configurable tables; and a plurality of configurable queues. 24. The microprocessor of claim 23 wherein said cache coherence manager is further adapted to selectively issue a speculative request to a memory and to further issue an intervention message to the plurality of cores in response to a coherent request, wherein a first one of the plurality of configurable table stores a response to the intervention message using an index defined by an identifier allocated to the coherent request if the selectively issued speculative request is in a first one of the plurality of configurable queues when the response to the intervention message is received.
25. The microprocessor of claim 24 wherein an entry is allocated to the coherent request in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first one of the plurality of configurable queues to a second one of the plurality of configurable queues, wherein after the allocation of the entry in the second one of the plurality of configurable tables, the response to the intervention message is transferred to the second one of the plurality of configurable tables from the first one of the plurality of configurable tables.
26. The microprocessor of claim 24 wherein an entry is allocated in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues, wherein the second one of the plurality of configurable tables stores the response to the intervention message if the selectively issued speculative request is in the second one of the plurality of queues when the response to the intervention message is received.
27. The microprocessor of claim 26 wherein an entry is allocated in a third one of the plurality of configurable tables when the selectively issued speculative request is issued to the memory, wherein the intervention message is copied from the second one of the plurality of configurable tables to the third one of the plurality of configurable tables.
28. A method of operating a microprocessor, said microprocessor comprising a plurality of processing cores and a cache coherence manager configured to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the method comprising:
enabling one or more of a plurality of configurable ports disposed in the cache coherence manager to be selected for transferring information to and from the cache coherence manager; enabling sizes of a plurality of configurable tables disposed in the cache coherence manager to be defined; and enabling sizes of a plurality of configurable queues disposed in the cache coherence manager to be defined. 29. The method of claim 28 further comprising:
selectively issuing a speculative request to a memory in response to a coherent request; allocating an identifier to the coherent request; issuing an intervention message to the plurality of cores in response to the coherent request; storing a response to the intervention message in a first one of the plurality of configurable tables at an index defined by the identifier if the selectively issued speculative request is in a first one of the plurality of queues when the response to the intervention message is received. 30. The method of claim 29 further comprising:
allocating an entry to the coherent request in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and transferring the response to the intervention message to the second one of the plurality of configurable tables from the first one of the plurality of configurable tables. 31. The method of claim 29 further comprising:
allocating an entry in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and storing the response to the intervention message in the second one of the plurality of configurable tables if the selectively issued speculative request is in the second one of the plurality of queues when the response to the intervention message is received. 32. The method of claim 31 further comprising:
allocating an entry in a third one of the plurality of configurable tables when the selectively issued speculative request is issued to the memory; and copying the intervention message from the second one of the plurality of configurable tables to the third one of the plurality of configurable tables. 33. A computer readable storage medium including instructions defining logic blocks of a microprocessor comprising a plurality of processing cores and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, the computer readable storage medium adapted for use by an electronic design automation application executed by a computer, wherein the logic blocks are configured to perform an operation comprising:
enabling one or more of a plurality of configurable ports disposed in the cache coherence manager to be selected for transferring information to and from the cache coherence manager; enabling sizes of a plurality of configurable tables disposed in the cache coherence manager to be defined; and enabling sizes of a plurality of configurable queues disposed in the cache coherence manager to be defined. 34. The computer readable storage medium of claim 33 wherein the logic blocks are configured to perform an operation comprising:
selectively issuing a speculative request to a memory in response to a coherent request; allocating an identifier to the coherent request; issuing an intervention message to the plurality of cores in response to the coherent request; storing a response to the intervention message in a first one of the plurality of configurable tables at an index defined by the identifier if the selectively issued speculative request is in a first one of the plurality of queues when the response to the intervention message is received. 35. The computer readable storage medium of claim 34 wherein the logic blocks are configured to perform an operation comprising:
allocating an entry to the coherent request in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and transferring the response to the intervention message to the second one of the plurality of configurable tables from the first one of the plurality of configurable tables. 36. The computer readable storage medium of claim 34 wherein the logic blocks are configured to perform an operation comprising:
allocating an entry in a second one of the plurality of configurable tables when the selectively issued speculative request is delivered from the first the one of the plurality of configurable queues to a second one of the plurality of configurable queues; and storing the response to the intervention message in the second one of the plurality of configurable tables if the selectively issued speculative request is in the second one of the plurality of queues when the response to the intervention message is received. 37. The method of claim 36 further comprising:
allocating an entry in a third one of the plurality of configurable tables when the selectively issued speculative request is issued to the memory; and copying the intervention message from the second one of the plurality of configurable tables to the third one of the plurality of configurable tables. Description
The present invention relates to multiprocessor systems, and more particularly to performing a speculative request in a cache coherent multi-core microprocessor system.
To improve performance at any given operating frequency, microprocessors with a multitude of cores that execute instructions in parallel have been developed. The cores may be integrated within the same semiconductor die, or may be formed on different semiconductor dies coupled to one another within a package, or a combination of the two. Each core typically includes its own level-1 cache and an optional level-2 cache.
A cache coherency protocol governs the traffic flow between the memory and the caches associated with the cores to ensure coherency between them. For example, the cache coherency protocol ensures that if a copy of a data item is modified in one of the caches, copies of the same data item stored in other caches and in the main memory are invalidated or updated in accordance with the modification.
In order to reduce the average latency associated with a coherent read request, a technique commonly referred to as speculative read may be used. In accordance with this technique, concurrently with searching for the requested data in the caches, a speculative read request is also issued to the memory. If the requested data is stored in any of the caches, the speculative read is cancelled. If the requested data is not stored in any of the caches, the speculative read is confirmed and the data identified by the confirmed request is transferred from the memory to the requesting core.
In accordance with one embodiment of the present invention, a multi-core microprocessor includes, in part, a cache coherence manager that maintains cache coherence among the multitude of cores and also minimizes latency associated with performing coherent requests. The cache coherence manager includes, in part, a request unit, an intervention unit, a response unit, and a memory interface unit. The request unit is configured to selectively issue a speculative request in response to a coherent request received from one of the cores. The intervention unit is configured to send an intervention message associated with the coherent request to the cores. The memory interface unit is configured to receive the speculative request and to selectively cancel or forward the speculative request to a memory.
In one embodiment, the memory interface unit includes at least three tables. An entry in the first table is an index to the second table. The entry in the second table is an index to the third table. The entry in the first table is allocated when a response to the intervention message is stored in the first table before the speculative request is stored in the memory interface unit. The entry in the second table is allocated when the request is stored in the memory interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.
In one embodiment, the request unit includes, in part, a fourth table storing a multitude of addresses, and a logic block configured to compare an address associated with the request to the multitude of addresses stored in the fourth table. Each address stored in the fourth table is associated with a pending coherent request. If an address match is not detected, the logic block issues the speculative request and assigns an identifier thereto. The identifier is used as an index to the first entry in the first table. In another embodiment, the logic block issues the speculative request first, assigns a corresponding identifier, and subsequently compares the requested address to the addresses stored in the fourth table. If an address match is detected, the logic block cancels the speculative request. In one embodiment, the request unit does not issue a speculative request unless the number of unresolved speculative requests is less than the total number of entries of the third table.
In accordance with one embodiment of the present invention, a method of operating a multi-core microprocessor having disposed therein a cache coherence manager includes, in part, receiving a coherent request from one of the cores, selectively issuing a speculative request in response, sending an intervention message associated with the coherent request to the cores, and selectively sending the issued speculative request to a memory.
In one embodiment, the memory interface unit includes at least three tables. An entry in the first table is an index to the second table. The entry in the second table is an index to the third table. The entry in the first table is allocated when a response to the intervention message arrives at the first table before the corresponding request is stored the memory interface unit. The entry in the second table is allocated when the speculative request is stored in the memory interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.
In one embodiment, the address associated with the coherent request is compared to a multitude of addresses stored in a fourth table. Each address stored in the fourth table is associated with a pending coherent request. If an address match is not detected, the request is speculatively issued and an identifier is assigned to this request. The identifier is used as an index to the first entry in the first table. In another embodiment, the speculative request is first issued and a corresponding identifier is assigned. If a match is thereafter detected between the address associated with the request and any one of the addresses stored in the fourth table, the speculative request is canceled. In one embodiment, the coherent request is not speculatively issued unless the number of unresolved speculative requests is less than the total number of entries of the third table.
FIG. 1 shows a multi-core microprocessor, in communication with a number of I/O devices and a system memory, in accordance with one embodiment of the present invention.
FIG. 2 is a block diagram of the cache coherence manger disposed in the microprocessor of FIG. 1, in accordance with one embodiment of the present invention.
FIG. 3 is a more detailed block diagram of the cache coherence manager of FIG. 2, in accordance with one embodiment of the present invention.
FIGS. 4A, 4B and 4C form a flowchart showing a speculative request, in accordance with one embodiment of the present invention.
FIG. 5 shows the flow of indices and data between a number of tables disposed in the cache coherence manager of in FIG. 3.
FIG. 6 shows the flow of speculative and non-speculative requests that may lead to a deadlock condition and which the present invention is adapted to inhibit.
FIG. 7 shows an exemplary computer system in which the present invention may be embodied.
In accordance with one embodiment of the present invention, a multi-core microprocessor includes, in part, a cache coherence manager that maintains coherence among the multitude of microprocessor cores, and further minimizes the latency associated with coherent read requests. The cache coherence manager includes, in part a request unit, an intervention unit, a memory interface unit and a response unit. The cache coherence manager supports speculative reads and includes an indexing scheme that efficiently manages the processing of the speculative requests and the corresponding intervention messages forwarded to and received from the cores.
FIG. 1 is a block diagram of a microprocessor 100, in accordance with one exemplary embodiment of the present invention, that is in communication with system memory 600 and I/O units 610, 620 via system bus 630. Microprocessor (hereinafter alternatively referred to as processor) 100 is shown as including, in part, four cores 105 1, 105 2, 105 3 and 105 4, a cache coherency manger 200, and an optional level-2 (L2) cache 605. Each core 105 i, where i is an integer ranging from 1 to N, where in this embodiment N=4, is shown as including, in part, a processing core 110 i, an L1 cache 115 i, and a cache control logic 120 i. Although exemplary embodiment of processor 100 is shown as including four cores, it is understood that other embodiments of processor 100 may include more or fewer than four cores.
Each processing core 110 i is adapted to perform a multitude of fixed or flexible sequence of operations in response to program instructions. Each processing core 110 i may conform to either CISC and/or RISC architectures to process scalar or vector data types using SISD or SIMD instructions. Each processing core 110 i may include general purpose and specialized register files and execution units configured to perform logic, arithmetic, and any other type of data processing functions. The processing cores 110 1, 110 2, 110 3 and 110 4, which are collectively referred to as either processing cores 110 i or processing cores 110, may be configured to perform identical functions, or may alternatively be configured to perform different functions adapted to different applications. Processing cores 110 may be single-threaded or multi-threaded, i.e., capable of executing multiple sequences of program instructions in parallel.
Each core 105 i is shown as including a level-1 (L1) cache. In other embodiments, each core 110 i may include more levels of cache, e.g., level 2, level 3, etc. Each cache 115 i may include instructions and/or data. Each cache 115 i is typically organized to include a multitude of cache lines, with each line adapted to store a copy of the data corresponding with one or more virtual or physical memory addresses. Each cache line also stores additional information used to manage that cache line. Such additional information includes, for example, tag information used to identify the main memory address associated with the cache line, and cache coherency information used to synchronize the data in the cache line with other caches and/or with the main system memory. The cache tag may be formed from all or a portion of the memory address associated with the cache line.
Each cache 115 i is partitioned into a number of cache lines, with each cache line corresponding to a range of adjacent locations in shared system memory 300. In one embodiment, each line of each cache, for example cache 115 1, includes data to facilitate coherency between, e.g., cache 151 1, main memory 600 and any other caches 115 2, 115 3, 115 4, intended to remain coherent with cache 115 1, as described further below. For example, in accordance with the MESI cache coherency protocol, each cache line is marked as being modified �M�, exclusive �E�, Shared �S�, or Invalid �I�, as is well known. Other cache coherency protocols, such as MSI, MOSI, and MOESI coherency protocols, are also supported by the embodiments of the present invention.
Each core 105 i is coupled to a cache coherency manager 200 via an associated bus 135 i. Cache coherency manager 200 facilitates transfer of instructions and/or data between cores 105 i, system memory 600, I/O units 310, 320 and optional shared L2 cache 605. Cache coherency manager 200 establishes the global ordering of requests, sends intervention requests, collects the responses to such requests, and sends the requested data back to the requesting core. Cache coherency manager 200 orders the requests so as to optimize memory accesses, load balance the requests, give priority to one or more cores over the other cores, and/or give priority to one or more types of requests over other requests. Although not shown, in some embodiments, one or more of cores 105 i include a dedicated Level-2 (L2) cache when optional shared L2 cache 605 is not used.
FIG. 2 is a block diagram of cache coherency manager 200, in accordance with one embodiment of the present invention. Cache coherency manager 200 is shown as including, in part, a request unit 220, an intervention unit 250, a response unit 280, and a memory interface unit 300. Request unit 220 includes input ports 202 adapted to receive, for example, read requests, write requests, write-back requests and any other cache memory related requests from cores 105 i. Request unit 220 serializes the requests it receives from cores 105 i and sends non-coherent read/write requests, speculative coherent read requests, as well as explicit and implicit writeback requests of modified cache data to memory interface unit 300 via port 204. Request unit 220 sends coherent requests to intervention unit 250 via port 216. In order to avoid a read after write hazard, the read address is compared against pending coherent requests that can generate write operations. If a match is detected as a result of this comparison, the read request is not started speculatively.
In response to the coherent intervention requests received from request unit 220, intervention unit 250 issues an intervention message via output ports 212. A hit will cause the data to return to the intervention unit via input ports 245. In another embodiment, the requested data is returned to the intervention unit 208. Intervention unit 250 subsequently forwards this data to response unit 205 via output ports 218. Response unit 280 forwards this data to the requesting (originating the request) core via output ports 212. If there is a cache miss and the read request was not performed speculatively, intervention unit 250 requests access to this data by sending a coherent read or write request to memory interface unit 300 via output ports 206. A read request may proceed without speculation when, for example, a request memory buffer disposed in request unit 220 and adapted to store and transfer the requests to memory interface unit 300 is full.
Memory interface unit 300 receives non-coherent read/write requests from request unit 220, as well as speculative requests and writeback requests from intervention unit 250. In response, memory interface unit 300 accesses system memory 600 and/or higher level cache memories such as L2 cache 605 via input/output ports 255 to complete these requests. The data retrieved from memory 600 and/or higher level cache memories in response to such memory requests is forwarded to response unit 215 via output port 260. The response unit 215 returns the data requested by the requesting core via output ports 265. As is understood, the requested data may have been retrieved from an L1 cache of another core, from memory 600, or from optional higher level cache memories.
FIG. 3 is a more detailed view of cache coherence manager 200 disposed in a microprocessor having N cores, in accordance with one embodiment of the present invention. Referring to FIGS. 1 and 3 concurrently, in order to reduce average latency of a coherent read request from any of the N cores 105 i, where i is an integer varying from 1 to N, coherence manager 200 issues speculative read requests to memory 600 via memory interface unit 300. The speculative read assumes that the requested data will not be found in any of the cores. If the requested data is found in response to the intervention message, the speculative read is canceled if it has not yet been issued by memory interface unit 300, or alternatively the response is dropped when it returns from system memory 600.
The response to an intervention message may arrive at the intervention unit 250 at different points in time relative to the speculative request. The request may still be in the request unit 220 when the response to the associated intervention message is received by the intervention unit 250. The request may be in the memory interface unit 300 when the response to the associated intervention message is received by intervention unit 250. The request may have been issued to the memory by the time the response to the associated intervention message arrives at the intervention unit 250. A number of data segments associated with the speculative read request may have been received by the memory interface unit 300 before the response to the associated intervention message is received by the intervention unit 250. Coherence manager 200 is configured to handle speculative requests for all possible timing conditions described above, notwithstanding the outcome of the intervention message, i.e., cancel or confirm.
Incoming coherent requests are serialized by serialized address register (SAR) 224 disposed in request unit 220. In one embodiment, the cache line address associated with each request is compared to the entries stored in the active address table (AAT) 222. An address match indicates that a coherent request is already pending for that address and hence no speculative request is issued for that request. If no address match is detected and a slot is available in request memory queue (RMQ) 228, serialized request handler (SRH) 226 loads the request in RMQ 228. If a slot is not available in RMQ 228, no speculative request is issued for that request even if no speculation is detected as being in progress for that address. Furthermore, if RQU 220 receives a coherent request that was erroneously issued due, for example, to software error, then RQU 220 will not issue a corresponding speculative request. Similarly, if RQU 220 issues a speculative request that bypasses the RMQ 228�via signal line 230�and subsequently detects an error with this request, RQU 220 will cancel this request. AAT 222 performs two functions. First, it keeps track of active coherent requests to inhibit read-after-write hazards. An intervention response to a coherent request may result in a read or write operation to the memory. AAT 222 is used to ensure that a speculative read to the same address does not occur before the updated data is written to the memory, thereby to avoid read-after-write hazards. Second, AAT 222 is used to tag the speculative requests to enable their identification as they flow between the IVU 250, RQU 220 and MIU 300.
The AAT number associated with a speculative request travels with that request to MIU 300. Accordingly, RMQ 228 stores both the speculative request as well as the AAT number associated with that request. In another embodiment, SAR 224 issues the speculative request before it looks-up the address in AAT 222. One clock cycle later, if the look-up in AAT 222 indicates that an earlier issued speculative request is still pending for that address, the newly issued speculative request is canceled. A speculative request issued before an AAT 222 look-up may get stored in memory request queue (MRQ) 310 or get issued to the memory. Under both conditions, the speculative request is canceled if the subsequent AAT 222 look-up results in an address match. The cancellation of such a request results in deallocation of any corresponding numbers that may have been assigned to that request in speculative table 302 and/or request data buffer table 306. The process of allocating and deallocating numbers in various tables disposed in memory interface unit 300 are described in detail below.
Coherent read requests are received from SRH 226 and stored in intervention queue (IQ) 252. Corresponding intervention messages are issued after these requests are stored in intervention output request queue 256. Intervention messages that have been forwarded to the cores are stored in pending intervention queue (PIQ) 262, and responses to these intervention messages are stored in intervention response queue 258. The AAT number associated with a request is stored in PIQ 262.
Memory interface unit 300 includes, in part, a speculative table (SPT) 302, an active address to speculation table (A2ST) 304, and a read data buffer table (RDBT) 306. As described further below, SPT 302 tracks the confirm/cancel results for speculative requests that have been received by MIU 300. An entry (alternatively referred to herein as number) in SPT 302 is allocated when a speculative request is received by MIU 300 from RQU 220. The SPT entry is loaded into memory request queue (MRQ) 310 together with the request. Response data buffer table (RDBT) 306 tracks information associated with the requests that have been issued to the memory. An entry in RDBT 306 is allocated for every read request that is issued to the memory. The response to a read request is stored in the response data buffer (RDB) 316 at an address defined by the corresponding entry in RDBT 306. A2ST 304 performs two functions. First, for each AAT entry, A2ST 304 supplies the corresponding SPT entry. Second, A2ST temporarily stores the confirm/cancel result for any speculative request that has not been received by MIU 300 and for which an SPT entry has not yet been allocated. In such conditions, when the request is received by MIU 300, the confirm/cancel result is copied from A2ST 304 to the associated SPT entry newly allocated. When a request stored in RMQ 228 is delivered and stored in MRQ 310, the AAT number associated with that request is also stored in the newly allocated entry in SPT 302.
Confirm/cancel results returned in response to an intervention message and the AAT entry associated with the corresponding read request are delivered from Intervention Response Handler (IRSH) 266 to speculative handler (SPH) 312. The confirm/cancel results are received in the same order as they are transmitted. This ordering ensures that the AAT number supplied by PIQ 262 and the confirm/cancel result supplied by IRSQ 258 are associated with the same request as they are delivered to IRSH 266. The confirm/cancel result, and the associated AAT number are subsequently delivered from IRSH 266 to speculative handler (SPH) 312.
Memory output register (MOR) 318 and memory input data register (MIDR) 314 are the interfaces between MIU 300 and memory 600. Outgoing requests are sent to memory 600 via MOR 318, and data received form memory 600 is loaded in MDIR 314. An entry is allocated for a request in RDBT 306 before that request is issued to memory 600. The data loaded in MDIR 314 is stored in RDB 316 at an address defined by the entry allocated in RDBT 306.
The response to an intervention message may arrive at IVU 250 before the corresponding speculative request has been issued to MIU 300. This condition may happen, for example, when MRQ 310 is full and cannot receive the speculative request at the time when the response to the corresponding intervention message arrives at IVU 250. To handle such conditions, the AAT entry and the intervention response, i.e., confirm/cancel result, associated with that request is delivered to SPH 312 by IRSH 266. The confirm/cancel result is subsequently stored in A2ST 304. After the speculative request is stored in MRQ 310, a corresponding entry in SPT 302 is allocated and the intervention response, i.e., confirm/cancel result is copied from A2ST 304 to that entry in SPT 302. If the intervention response is a speculative confirm, SPH 312 allocates an entry in RDBT 306 and deallocates the corresponding SPT entry. Subsequently, a read request is issued to the memory. If the intervention response is a speculative cancel, the speculative request is canceled and the corresponding SPT entry is deallocated.
The response to an intervention message may arrive at IVU 250 after the corresponding speculative request has been received by MIU 300. Since the request is already stored in MRQ 310, it has an assigned entry in SPT 302. When the request reaches the head of the queue in MRQ 310, the SPT entry associated with that request is looked-up. If the received intervention response is a speculative confirm, (i) an entry in RDBT 306 is allocated and its confirmed bit is set, (ii) the corresponding SPT entry is deallocated, and (iii) a read request is issued to the memory. If the received intervention is a speculative cancel, the speculative request is canceled and the corresponding SPT entry is deallocated. If no intervention response is received after the request reaches the head of the queue in MRQ 310, the speculative request is issued to the memory.
MIU arbitration logic 308 arbitrates access to MRQ 310 between IVU 250 and RQU 220. When no speculative request is made because RMQ 228 is full and it is subsequently determined that the none of the caches contain the requested data, a corresponding request is made to the memory by IVU 250. This request is received by MIU arbitration logic 308 and delivered to MRQ 310. This request is thereafter delivered to MOR 318�via MOR arbitration logic 330�for later submission to the memory. MRQ 310 is bypassed if it is empty, in turn, causing MIU arbitration logic 308 to transfer the request directly to MOR arbitration logic 308. SPH 312 transfers confirm/cancel results from SPT 302 to RDBT 306. MOR arbitration logic 308 gains access to SPT 302 and RDBT 306 via SPH 312.
The response to an intervention message may arrive at IVU 250 after the corresponding speculative request has been issued to the memory but before the requested data has been received from the memory. The RDBT's corresponding confirmed and canceled bits are both cleared if the intervention response is not known at the time the speculative request is issued to the memory. When the intervention response is received by SPH 312, A2ST 304 uses the AAT supplied by PIQ 262 to find the corresponding SPT entry. The SPT entry is then used to supply the corresponding RDBT entry. The RDBT entry is then updated with the confirm/cancel result of the intervention response. The corresponding entry in SPT 320 is then deallocated. Each speculative read request that is sent to the memory is allocated a corresponding entry in RDBT 306. The data supplied by the memory in response to the read request is received by MIDR 314 and is subsequently stored in RDB 316 at an address defined by the corresponding entry in RDBT 306. Memory response handler (MRSH) 322 looks-up the status of the corresponding RDBT entry when the data is returned and stored in RDB 306. If the speculative request has been confirmed, the data is delivered to controller 324, which in turn, stores this data in memory read data queue (MRDQ) 326. If the speculative request has been canceled, the RDB/RDBT entries are deallocated after all the segments of the requested data are received from the memory. Controller 324 may include a number of queues to accommodate the transfer of the data to MRDQ 326. Data stored in MRDQ 326 is subsequently transferred to response output register (RSOR) 282. RSOR 282 subsequently supplies this data to the requesting core. MRSH 322 is triggered to perform the look-up operation in RDBT 306 when the associated data is stored in RDB 316.
The response to an intervention message may arrive at IVU 250 after part or the entire data corresponding to the speculative request has been received from the memory. If the intervention response is not known by the time a segment, such as a double-word, of the requested data is received, the transaction is considered as a late completion. Late completions are handled by the late speculation completion handler (LCSH) 320. If a late completion is marked so as to cancel the speculative request, LCSH 320 retires the RDBT/RDB entry after the entire segments of the requested data are received from the memory. If a late completion is marked so as to confirm the speculative request, LCSH 320 waits for the entire segments of the requested data to arrive. The received data are thereafter delivered to controller 324, which in turn, stores this data in MRDQ 336. The data present in MRDQ 336 is supplied to the requesting core after being stored in RSOR 282. LSCH 320 is triggered when it receives the late intervention response. An AAT entry may be deallocated if the coherent request does not result in a required memory operation, such as a memory write-back operation to the memory, only if both the intervention response and the corresponding speculative request are received by MIU 300. If a coherent request results in a required memory access operation, the AAT entry is not deallocated until after the intervention response, the corresponding speculative request, and any required memory access operation resulting from the intervention are all received by MIU 300. This ensures that, for example, when a write-back to the memory is required, the memory write operation is in the MIU 300 ahead of the speculative request before the AAT entry is deallocated.
FIGS. 4A, 4B and 4C are a flowchart 700 of steps carried out to perform a speculative request, in accordance with one embodiment of the present invention. Referring to FIG. 4A, if the request is determined to be in the request unit when the response to the intervention message is received 702, the confirm/cancel result is stored 704 in the A2ST. After the request is stored 706 in the MRQ, the SPT is updated with the confirm/cancel result 708. If the speculative response is a confirm 710, an RDBT number is allocated and used as an index to the RDBT to store the confirm result 712. The SPT number is deallocated 714 and the request is thereafter sent to the memory. If the speculative response is a cancel 710, the request is canceled 718 and the SPT number is deallocated.
Referring to FIG. 4B, a request stored in the MRQ has an allocated SPT number 750. If an intervention response is available 754 after the request reaches 752 the top of the queue in the MRQ, the process moves to decision block 710 (FIG. 4A). If the intervention response is not available 754 after the request reaches 752 the top of the queue in the MRQ, an RDBT number is allocated to the request 758, and its confirm/cancel bits are cleared. The request is thereafter sent to the memory 760.
Referring to FIG. 4C, after the confirm/cancel result is received 770, the AAT number is used as an index to the A2ST to find the SPT number 772. The SPT number is then used to find the RDBT number 774. If the speculative response is a confirm 776, the data received from the memory is transferred to the requesting core 778, and the RDBT number is deallocated 782. If the speculative response is a cancel 776, the data received from the memory is discarded 780 and the RDBT number is deallocated.
FIG. 5 shows the flow of indices and entries associated with a request between AAT 22, SPT 302, A2ST 304, and RDBT 306 of coherence manager 200. For clarity, only a few of the blocks disposed in coherence manager 200 are shown in FIG. 4. The AAT number, allocated to each coherent request and used to track the associated speculative request as described above, is delivered to MIU 300 and IVU 250. An SPT number is allocated by MIU arbitration logic 308 when a slot become available in MRQ 310 for that request; MRQ 310 stores the SPT number. An RDBT number is allocated by MOR arbitration logic 330 when the request is issued to the memory via MOR 318. The SPT number is used as an index to store the AAT number in SPT 302, and the AAT number is used as an index to store the SPT number in A2ST 304.
When the response to an intervention message arrives at IVU 250 while the speculative read request is still in RMQ 228, the confirm/cancel (CC) result is first stored in A2ST table 340. The SPT number allocated after the request is stored in MRQ 310, is used as an index to store the AAT number in SPT 302. The AAT number stored in PIQ 262 is used as an index to A2ST 304 to look-up the CC. The retrieved CC is copied to SPT 302 at the index defined by the SPT number. If the CC is a speculative confirm, an RDBT 306 number is allocated. The SPT number is then used as an index to SPT 302 to retrieve and copy the CC result to RDBT 306. If the intervention response is a speculative cancel, the speculative request is canceled and the corresponding SPT entry is deallocated.
An SPT number exists if the request is already stored in MRQ 310. The allocated SPT number is used as an index to SPT 302 to store the AAT number. When the CC is received, the AAT number stored in PIQ 262 is used as an index to A2ST 304 to look-up the SPT number. The SPT number is then used as an index to SPT 302 to store the CC. When the request reaches the head of the queue in MRQ 310, the SPT number is interrogated. If the CC is a speculative confirm, a corresponding number in RDBT 306 is allocated. The RDBT number is used as an index to RDBT 306 to store the CC. The corresponding SPT number is deallocated, and a read request is issued to the memory. If the received intervention is a speculative cancel, the speculative request is canceled and the corresponding SPT entry is deallocated.
The response to an intervention message may arrive at IVU 250 after the corresponding speculative request has been issued to the memory but before the response to the request has been received from the memory. In such conditions, the AAT and RDBT numbers are stored in the SPT 302 at the index defined by the SPT number. The SPT number is stored in A2ST 304 at an index defined by the SPT number. The AAT number corresponding to the received CC is used to identify the corresponding SPT number in A2ST table 304. The SPT number so identified is then used to find the corresponding RDBT number. The RDBT number is subsequently used as an index to RDBT 306 to store the CC result; the corresponding SPT number is then deallocated. If the CC is a confirm, the data supplied by the memory is delivered to RSU 280. If the CC is a cancel, the RDB/RDBT entries are deallocated after all the segments of the requested data are received from the memory.
The response to an intervention message may arrive at IVU 250 after part or the entire data corresponding to the speculative request has been received from the memory. In such conditions, the AAT and RDBT numbers are stored in the SPT 302 at the index defined by the SPT number. The SPT number is stored in A2ST 304 at an index defined by the SPT number. The AAT number corresponding to the received CC is used to identify the corresponding SPT number in A2ST table 304. The SPT number so identified is then used to find the corresponding RDBT number. The RDBT number is subsequently used as an index to RDBT 306 to store the CC result. If the CC is a confirm, the data supplied by the memory is delivered to RSU 280 by LSCH 320. If the CC is a cancel, the RDB/RDBT entries are deallocated after all the segments of the requested data are received from the memory.
As described above, in accordance with one embodiment of the present invention, the queues, tables and the ports in coherence manager 200 are configurable to support different sizes and optimize power consumption and performance. A deadlock condition may thus occur when the sum of the sizes of IQ 252 and PIQ 262 is greater than the sum of the sizes of RDBT 306 and MRQ 310. To prevent this condition from occurring, in accordance with one embodiment of the present invention, SAR 224 is adapted so as not issue any speculative requests unless the number of unresolved speculative requests, i.e., speculative requests for which the associated intervention responses have not yet been completed, is less than the total number of entries in RDBT 306. For example, if RDBT 306 has a capacity to hold 16 entries, no more than 15 unresolved speculative requests may be pending at any given time.
Referring to FIGS. 3 and 6 concurrently, assume that a first stream of requests 400 followed by a second stream of requests 402 are delivered to request unit 220. Assume that RMQ 228 is full when the first stream of requests (RS) 400 is received; therefore these requests are not stored in RMQ 228 and are not speculated. Assume that RMQ 228 is empty when RS 402 is received; therefore these requests are stored in RMQ 228 and are speculated. Intervention messages (IM) 500 and 502, corresponding respectively to request streams 400 and 402, are forwarded to IVU 250. Intervention responses (IR) 600 and 602 are assumed to be respectively associated with IMs 500 and 502.
RS 402 is subsequently transferred to and stored in MRQ 310. Assume that a first portion 402 a of RS 402 is issued to the memory and their associated entries allocated in RDBT 306 fill all the slots in RDBT 306. Assume that MRQ 310 is filled with the remaining portion 402 b of RS 402, as well as with non-coherent stream of request 404 that subsequently arrive.
Assume that one or more of the responses in IR 600 contain cache misses. Because no speculative requests were issued for the associated RS 400, these requests must be supplied to the memory and thus must first be written in MRQ 310. However, MRQ 310 is full and cannot accept any new requests unless there is an entry available in RDBT 306. The entries in RDBT 306 cannot be cleared since the confirm/cancel results needed to clear these requests are present in IR 602, which is stuck behind IR 600. Accordingly, a deadlock is created where no entry can be cleared and no movement of requests can flow through the coherence manager 200. To prevent such deadlocks, in accordance with one embodiment of the present invention, SAR 224 is adapted so as not issue any speculative requests unless the number of unresolved speculative requests is at least one less than the total number of entries in RDBT 306.
In accordance with one embodiment of the present invention, the cache coherence manager includes, in part, a multitude of configurable ports, a multitude of configurable tables, and a multitude of configurable queues. The configurability of the ports enables a user to select the number of desired ports. For example, assume that the coherence manager has 16 configurable ports. A user may, however, need only four such ports to adapt the coherence manager to a microprocessor having four cores. The user accordingly configures the coherence manager so as to use only four of the 16 ports. The configurability of the tables and queues enable a user to define their respective sizes to balance the competing goals of achieving optimum processor performance and minimizing the die size.
FIG. 7 illustrates an exemplary computer system 1000 in which the present invention may be embodied. Computer system 1000 typically includes one or more output devices 1100, including display devices such as a CRT, LCD, OLED, LED, gas plasma, electronic ink, or other types of displays, speakers and other audio output devices; and haptic output devices such as vibrating actuators; computer 1200; a keyboard 1300; input devices 1400; and a network interface 1500. Input devices 1400 may include a computer mouse, a trackball, joystick, track pad, graphics tablet, touch screen, microphone, various sensors, and/or other wired or wireless input devices that allow a user or the environment to interact with computer system 1000. Network interface 1500 typically provides wired or wireless communication with an electronic communications network, such as a local area network, a wide area network, for example the Internet, and/or virtual networks, for example a virtual private network (VPN). Network interface 1500 can implement one or more wired or wireless networking technologies, including Ethernet, one or more of the 802.11 standards, Bluetooth, and ultra-wideband networking technologies.
Although some exemplary embodiments of the present invention are made with reference to a processor having four cores, it is understood that the processor may have more or fewer than four cores. The arrangement and the number of the various devices shown in the block diagrams are for clarity and ease of understanding. It is understood that combinations of blocks, additions of new blocks, re-arrangement of blocks, and the like fall within alternative embodiments of the present invention. For example, any number of I/Os, coherent multi-core processors, system memories, L2 and L3 caches, and non-coherent cached or cacheless processing cores may also be used.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS20010005873 *Dec 21, 2000Jun 28, 2001Hitachi, Ltd.Shared memory multiprocessor performing cache coherence control and node controller thereforUS20020133674 *Oct 19, 2001Sep 19, 2002Martin Milo M.K.Bandwidth-adaptive, hybrid, cache-coherence protocolUS20060282645 *Jun 14, 2005Dec 14, 2006Benjamin TsienMemory attribute speculationUS20080215815 *Apr 11, 2008Sep 4, 2008International Business Machines CorporationSystem and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7769957 *Jun 22, 2007Aug 3, 2010Mips Technologies, Inc.Preventing writeback race in multiple core processorsUS7934059 *Jan 29, 2008Apr 26, 2011International Business Machines CorporationMethod, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetchingUS7937533 *May 4, 2008May 3, 2011International Business Machines CorporationStructure for handling data requestsUS8032713May 5, 2008Oct 4, 2011International Business Machines CorporationStructure for handling data accessUS8131941Sep 21, 2007Mar 6, 2012Mips Technologies, Inc.Support for multiple coherence domainsUS8234455 *Sep 25, 2009Jul 31, 2012Imagination Technologies LimitedMethod and apparatus for ensuring data cache coherencyUS8392663Dec 10, 2008Mar 5, 2013Mips Technologies, Inc.Coherent instruction cache utilizing cache-op execution resources* Cited by examinerClassifications U.S. Classification711/141, 711/E12.001International ClassificationG06F12/00Cooperative ClassificationG06F12/0815, G06F12/0871, G06F2212/507, G06F12/0831European ClassificationG06F12/08B4P4Legal EventsDateCodeEventDescriptionJun 2, 2014ASAssignmentEffective date: 20140131Owner name: ARM FINANCE OVERSEAS LIMITED, GREAT BRITAINFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRIDGE CROSSING, LLC;REEL/FRAME:033074/0058Apr 12, 2013ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MIPS TECHNOLOGIES, INC.;REEL/FRAME:030202/0440Owner name: BRIDGE CROSSING, LLC, NEW JERSEYEffective date: 20130206Oct 19, 2007ASAssignmentOwner name: MIPS TECHNOLOGIES, INC,, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, WILLIAM;BERG, THOMAS BENJAMIN;REEL/FRAME:019989/0322Effective date: 20071009RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


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value: This website is a Singaporean online travel agency and metasearch engine for hotels, vacation rentals, flights, and airport transfer. It is owned by Agoda Company Pte.


text:
LOT of GLASS EYES - 10-11MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES | eBay
People who viewed this item also viewedLOT of GLASS EYES - 10-11MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES$21.92+ $2.64LOT of GLASS EYES - 12MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES$20.68+ $2.64LOT of GLASS EYES - 10MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES$21.00+ $2.64LOT of GLASS STARBURST EYES - 8MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES$19.84+ $2.62LOT of GLASS EYES - 9MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES$26.72+ $2.62
Details about LOT of GLASS EYES - 10-11MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES
LOT of GLASS EYES - 10-11MM - 2 COLORS - TEDDY BEAR MAKING SUPPLIES
21d 21h (Mar 17, 2017
18:48:16 PDT)
eBay item number:302226036334

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Lansing, IL Outdoor Activities and Deals | Groupon
Lansing, IL Outdoor Activities
Chicago Fire Soccer Match Against Philadelphia Union at Toyota Park on Saturday, May 11 at 12:30 p.m. (Up to 52% Off)
The Fire look to secure a second-straight playoff berth with return of many key players from a successful 2012 campaign
$99 for a 2.5-Hour Basic Introduction to Sailing Course at Chicago Yacht Share ($200 Value)

value: This website is an American global e-commerce marketplace connecting subscribers with local merchants by offering activities, travel, goods and services in 15 countries. Based in Chicago, Groupon was launched there in November 2008, launching soon after in Boston, New York City and Toronto.


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Upload xml file server Jobs, Employment | Freelancer
Upload xml file server jobs
1,000 upload xml file server jobs found, pricing in USD
Fix XML upload to mySQL 5 days left
Hi I'm looking for someone who can design a simple app (android and ios). In Ionic, the app will be based on two webpages, one remote -www.... one remote -www.example.com- and one local -192.168.x.x-, each will work in one tab. I need OAuth (google account sign in) for the remote server. Download -from remote- and upload -to local server- an XML file.
...application to download XML Files fron vendor via FTP , convert XML to BasdaXML format and upload then upload Client via SFTP/FTPS Server on completion. Original XML Format -> [login to view URL] Output BasdaXML Format -> BasdaXML_20161216 ( BasdaXML_Invoice) The App would need to perform the following functions; 1. Poll the vendor FTP Server...
...user inform a given xml file where the size may vary from 1mb to 6gb. when its submited to the server the server must recognize that given xml, parse and sent it back to a web interface in a grid format. Its a very important requirement performance and memory managent. What I see for a possible solution is to use html 5 file upload and send i...
...Specifically for Orders Functions & Requirements 1) Export orders from Odoo in XML format - exporting of orders will be done manually 1-a) ability to select tables that need to be exported / mapping 1-b) ability name field headers which will then be used for xml export file (these will create new records in our software) 1-c) ability to select
...read from Access tables and generate XML files and upload them in FTP server . I need a developer to load the product information from the XML file that we created to wordpress database. Requirement ; - i need button in desktop application to Run "operation" . - i need one i click the button all product in xml files created in Wordpress. ...
URGENT: Extract our order information into a .xml file, logic required based on order information. Ended
...integrating our orders from Woocommerce to send directly to our warehouse. We require someone to extract our order information and place it in a specific .xml format to upload to our warehouses FTP server. The flow should go something like this: 1. Order Received 2. Order Information Extracted 3. Check suburb/postcode, decide whether it's local or
...sitemap-XML generator , which will take as input a big .txt file which is a simple list of URLs (it must take this file from the server and not from browser upload). Also, it must make each sitemap to have 50,000 entries max, meaning if there are more than 50,000 entries, then it splits the resulting files into multiple files, like 1.xml, 2.xml...
...handset which I'd like to use WITHOUT a CUCM server. I would like to use the phone with a SIP provider such as Soho66, Sipgate or Voipfone - or another (cheap) UK provider. I do have the knowledge to upgrade/download firmware and upload an XML configuration file, but I'd prefer you to have a TFTP server which I can configure the phone to use. P...
...DONE SIMILAR WORK IN THE PAST WIT XML CONNECTION - CAR RENTAL PROJECT - ================ Hi, We are looking for someone to help and build a Car Rental Website that will make use of a XML connection. The XML Connection will be granted from our Europe Car Rental Partner and will have to pull Data from their server to our website. The Data will be
I'm looking for some code to install into a html webpage, I would upload a dated XML file to my server, the webpage would have a drop list of dates, when a date is selected the corresponding XML file will be displayed in a table format on the page, a CSS file is required to enable editing of the table style etc, width sizing, color of columns, ...
...web guy about, but I'm sure there's much more I could be doing: 1. Upload my site map into the "domain root folder of the site." I did get an XML file from an online service, but I'm not sure if it's the best one to use since it was the free version. Also, the instructions to upload to the root folder came from the free service, not G...
We need a very small website built that is about 4 pages. Home, Services, Quotes, and Contact Us.. It will also have an XML plugin that connects to another server through XML. We want the XML part to be configured to look like the rest of the web page The install directions are as follows: Step 1 - Make sure your web host has PHP support. Backup
...QEEG evaluation, the software on his end will have an upload button which will send 21 files to the server. The purchaser will need to pay for the service prior analysis. The software will receive the 21 files (xdf,xml), discern the subject’s name, date of birth, date of testing from an XML file and set up a directory to store the files and then copy
Remote Server Monitor Ended
...monitoring java tool which can read an XML file and parse it into a database and upload the data into a central server (public). Tool should have proper error handling and issue tracking capability. Tool should have really good User Interface, ideas are welcome to as how it will look. Example XML file is attached. Please see the attached docu...
Engineering Microsoft SQL Server Software Architecture Software Testing Windows Desktop
...use to upload files to a back-end email distribution server. Currently the uploading uses a simple HTML file element which gives no feedback to the users. We would like this modified to provide a progress bar, and also when a PDF file is selected for upload to also automatically select a file with the same name but an XML extension and upload<...
Engineering Java Software Architecture Software Testing Windows Desktop
Private project or contest #10850180 Ended
WSDL delivery method - open to bidding Ended
I am in search for someone who can create a develpment that enables me to send an xml file via WSDL with trust certificates. I would basically upload a file (excel or xml) to a certain system that would later send the message via WSDL to a specified server.
WSDL delivery method Ended
Other jobs related to upload xml file server

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1963 in Bass Guitars | eBay
7 results for 1963
Was: Previous Price C $943.70
Hofner made in Germany , 500/ 01 , 1963 reissue
C $1,782.98
Fender VI from 1963
C $14,127.03
Gretsch Country Gentleman Twelve Strings from 1963
1963 Fender Jazz Bass Guitar
Original 1963 Gibson EB-O BASS with Original Black Pebble Case Gibson Guitar EB0
C $3,626.57
New listing Gibson Thunderbird IV Ebony , Regular Condition
Mosrite: Electric Bass American Standard MARK-1 AS-1965 Bass 00 USED
C $2,718.78
Fender American Professional Precision Bass in Antique Olive W/Case - 0193610776
C $2,808.64
C $2,470.23
List price: Previous Price C $2,600.24
Fender USA American Professional Precision Bass ATO/R
C $3,611.45
Fender: American Deluxe Dimension Bass IV HH, Maple Fingerboard, Black 2013 USED
Gibson EB-0F Used Electric Bass FREE Shipping
C $6,826.55
Gibson Thunderbird IV Used Bass Free Shipping from Japan #sb29
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Amazon.co.uk: Hayley Lewis' review of Bohemian Hippie Big Size Batwing Sleeve Ch...
This review is from: ZANZEA Bohemian Hippie Big Size Batwing Sleeve Chiffon Blouse Loose Off Shoulder Tee Shirt (Apparel)
nice top but probably too small for anyone over a size 18
Bohemian Hippie Big Size Batwing Sleeve Chiffon Blouse Loose Off Shoulder Shirt (5851) B00JPAJ75K

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Changye Song - Semantic Scholar
Susumu Ikehara20
Qing Li16
Wenhao Cui14
Xiaoli Wang13
26Susumu Ikehara
19Qing Li
16Wenhao Cui
15Hiroko Hisha
15Yunze Cui
Mouse mesenchymal stem cells can support human hematopoiesis both in vitro and in vivo: the crucial role of neural cell adhesion molecule.
Xiaoli Wang, Hiroko Hisha, +9 authors Susumu Ikehara
BACKGROUND We previously established a mesenchymal stem cell line (FMS/PA6-P) from the bone marrow adherent cells of fetal mice. The cell line expresses a higher level of neural cell adhesion… (More)
Transformation potential of bone marrow stromal cells into undifferentiated high-grade pleomorphic sarcoma
Qing Li, Hiroko Hisha, +11 authors Susumu Ikehara
Bone marrow adherent cells contain conventional bone marrow stromal cells and mesenchymal stem cells and these cells constitute the hematopoietic microenvironment. Mesenchymal stem cells have the… (More)
Lin(-)CD34(-) bone marrow cells from adult mice can differentiate into neural-like cells.
Qiang Li, Naoki Hosaka, +9 authors Susumu Ikehara
Numerous studies have shown that some populations of bone marrow cells (BMCs) have the capacity to differentiate into neural cells, which is useful for repairing brain lesions. In this paper, we… (More)
Successful acceptance of adult liver allografts by intra-bone marrow-bone marrow transplantation.
Satoshi Okazaki, Hiroko Hisha, +7 authors Susumu Ikehara
Previously, we have shown that liver allografts obtained from the fetus or young mice are accepted when bone marrow cells (BMCs) from adult mice of the same strain are co-grafted. However, for… (More)

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text:
Patent US7804107 - Thyristor semiconductor device and method of manufacture - Google Patents
In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide...http://www.google.com/patents/US7804107?utm_source=gb-gplus-sharePatent US7804107 - Thyristor semiconductor device and method of manufacture
Publication number US7804107 B1
Application number US 11/906,619
Also published as US7279367
Publication number 11906619, 906619, US 7804107 B1, US 7804107B1, US-B1-7804107, US7804107 B1, US7804107B1
Inventors Andrew E. Horch, Fred Hause
Patent Citations (27), Non-Patent Citations (6), Classifications (15), Legal Events (7)
US 7804107 B1
US5807759 Feb 20, 1997 Sep 15, 1998 National Semiconductor Corporation Method of fabricating a contact structure for a raised source/drain MOSFET
US5982017 Feb 19, 1999 Nov 9, 1999 Taiwan Semiconductor Manufacturing Company Recessed structure for shallow trench isolation and salicide processes
US6258682 Oct 17, 2000 Jul 10, 2001 Vanguard International Semiconductor Corporation Method of making ultra shallow junction MOSFET
US6284613 Nov 5, 1999 Sep 4, 2001 Chartered Semiconductor Manufacturing Ltd. Method for forming a T-gate for better salicidation
US6294415 Apr 26, 2000 Sep 25, 2001 United Microelectronics Corp. Method of fabricating a MOS transistor
US6350656 Jan 31, 2000 Feb 26, 2002 United Microelectronics Corp. SEG combined with tilt side implant process
US6703646 * Sep 24, 2002 Mar 9, 2004 T-Ram, Inc. Thyristor with lightly-doped emitter
1 Hsiang-Jen Huang; "Improved Low Temperature Characteristics of P-Channel MOSFETs with Si1-xGex Raised Source and Drain"; IEEE Transactions On Electron DEvices, vol. 48, No. 8, Aug. 2001, pp. 1627-1632;0018-9383(01)05680-5 IEEE 2001.
2 K. De Meyer; "Raised Source/Drain with Disposable Spacers for Sub 100 nm CMOS Technologies"; Extended Abstracts of International Workship on Junction Technology 2001; pp. 87-90 ISBN 4-89114-019-4/020-8; Japan Society of Applied Physics 2001.
3 Mark Rodder and D. Yeakley; "Raised Source/Drain MOSFET with Dual Sidewall Spacer"; IEEE Electronic Device Letters; Mar. 1991; vol. 12, No. 3, pp. 89-91.
4 N. Lindert; "Quasi-Planar FinFETs with Selectively Grown Germanium Raised Source/Drain"; 2001 IEEE International SOI Conference; Oct. 2001; pp. 111-112; 0/7803-6739-1/01 2001 IEEE.
5 T. Ohguro; "High performance RF Characteristocs of Raised Gate/Source/Drain CMOS with Co Salicide"; Symposium on VLSI Technology Digest of Technical Paprs; 0/7803-4700-6/98 IEEE 1998.
6 Yang-Kyu Choi; "Nanoscale Ultrathin Body PMOSFETs with Raised Selective Germanium Source/Drain"; IEEE Electron Device Letters; Sep. 2001; vol. 22, No. 9, pp. 447-448;0741-3106(01)07740-0 2001 IEEE.
U.S. Classification 257/107, 257/133
Cooperative Classification H01L29/66378, H01L27/1027, H01L27/1203, H01L21/823835, H01L21/84, H01L21/823814
European Classification H01L29/66M6T4A2, H01L21/8238G2, H01L27/12B, H01L21/8238D, H01L21/84, H01L27/102U

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P. 1Core ToolsCore ToolsRatings: (0)|Views: 10
|Likes: 0Published by Rubén MndzaMore info:Published by: Rubén Mndza on Sep 08, 2013Copyright:Attribution Non-commercialAvailability:Read on Scribd mobile: iPhone, iPad and Android.download as PDF, TXT or read online from ScribdFlag for inappropriate content|Add to collectionSee moreSee lesshttps://www.scribd.com/doc/166401722/Core-Tools09/08/2013pdftextoriginal You're Reading a Free Preview
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