text:
Patent US20060184771 - Mini-refresh processor recovery as bug workaround method using existing ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed...http://www.google.com/patents/US20060184771?utm_source=gb-gplus-sharePatent US20060184771 - Mini-refresh processor recovery as bug workaround method using existing recovery hardwareAdvanced Patent SearchPublication numberUS20060184771 A1Publication typeApplicationApplication numberUS 11/055,823Publication dateAug 17, 2006Filing dateFeb 11, 2005Priority dateFeb 11, 2005Publication number055823, 11055823, US 2006/0184771 A1, US 2006/184771 A1, US 20060184771 A1, US 20060184771A1, US 2006184771 A1, US 2006184771A1, US-A1-20060184771, US-A1-2006184771, US2006/0184771A1, US2006/184771A1, US20060184771 A1, US20060184771A1, US2006184771 A1, US2006184771A1InventorsMichael Floyd, Larry Leitner, Sheldon Levenstein, Scott Swaney, Brian ThomptoOriginal AssigneeInternational Business MachinesExport CitationBiBTeX, EndNote, RefManPatent Citations (51), Referenced by (42), Classifications (8), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMini-refresh processor recovery as bug workaround method using existing recovery hardware
US 20060184771 A1Abstract
A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state and prevents instructions not checkpointed from checkpointing. After that, the method releases checkpointed state stores to a L2 cache, and drops stores not checkpointed. Next, the method blocks interrupts until recovery is completed. Then the method disables the power savings states throughout the processor. After that, the method disables an instruction fetch and an instruction dispatch. Next, the method sends a hardware reset signal. Then the method restores selected registers from the current checkpointed state. Next, the method fetches instructions from restored instruction addresses. Then the method resumes a normal execution after a programmable number of instructions. Images(5) Claims(20)
BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention generally relates to an improved data processing system and, in particular, to a method, apparatus, or computer program product for limiting performance degradation while working around a design defect in a data processing system. Still more particularly, the present invention provides a method, apparatus, or computer program product for enhancing performance of avoiding a microprocessor's design defects and recovering a microprocessor from failing due to a design defect. [0004] 2. Description of Related Art [0005] A microprocessor is a silicon chip that contains a central processing unit (CPU) which controls all the other parts of a digital device. Designs vary widely but, in general, the CPU consists of the control unit, the arithmetic and logic unit (ALU) and memory (registers, cache, RAM and ROM) as well as various temporary buffers and other logic. The control unit fetches instructions from memory and decodes them to produce signals which control the other part of the computer. This may cause it to transfer data between memory and ALU or to activate peripherals to perform input or output. A parallel computer has several CPUs which may share other resources such as memory and peripherals. In addition to bandwidth (the number of bits processed in a single instruction) and clock speed (how many instructions per second the microprocessor can execute, microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer). [0006] Bugs in the logic design of a microprocessor are often implemented in real hardware where they are then found during prototype testing in a lab or, even worse, in a product in the field. Methods have been employed in the past to work around these bugs when they are found in order to allow the hardware to continue to operate despite the presence of the bug, even if in a reduced performance mode of operation. However, not all bugs are easy to work around, especially if they cannot be detected and preemptively prevented from corrupting the architected state of the machine before evasive action can be taken. Prior machines have “piggybacked” on or used existing or similar hardware mechanisms, such as an instruction flush used to recover the pipeline from a branch mispredict. However, these techniques are not always successful to work around all classes of bugs, and bugs cannot always be detected in time to stop writeback of registers with incorrect data, thus corrupting the architected state. [0007] A more recent advance is the notion of processor instruction retry recovery. This method traditionally is intended to recover from a temporary run-time hardware failure, such as a soft-error. However, in many cases, full processor recovery is also successful in working around a design bug present in the hardware. This is because the architected state is restored, undoing the bad effects of the bug, and caches and translation buffers are invalidated to ensure coherency with the rest of the system is maintained in spite of the hardware bug. This method is often successful in recovering from a design bug because when the instruction stream that exposed the bug re-executes, the instructions are processed differently, either as a side effect of executing a slightly different order, or on purpose when the hardware intentionally throttles back the execution of the processor by engaging a reduced execution mode (such as slowing the dispatch rate) until the bug is avoided. This method is often successful, however is slow because all architected state is restored and measurably hurts performance because the level 1 cache and buffers are empty and must be reloaded from the memory subsystem. If instruction retry recovery was invoked for a frequent (every several seconds) event, the performance penalty could be large enough that the customer would realize measurable performance loss, which is unacceptable for a successful workaround to be employed. [0008] Therefore, it would be advantageous to have an improved method, apparatus, or computer program product for enhancing performance of avoiding a microprocessor's design defects and recovering a microprocessor from failing due to a design defect. SUMMARY OF THE INVENTION [0009] The present invention is a method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to a design defect. The method is comprised of the following steps: The method detects and reports a plurality of events which warn of an error. Then the method locks a current checkpointed state (the last known good execution point in the instruction stream) and prevents a plurality of instructions not checkpointed from checkpointing. After that, the method releases a plurality of checkpointed state stores to a L2 cache, and drops a plurality of stores not checkpointed. Next, the method blocks a plurality of interrupts until recovery is completed. Then the method disables the power savings states throughout the processor. E.g. Forces clocks to idle circuits in a low-power state. After that, the method disables an instruction fetch and an instruction dispatch. Next, the method sends a hardware reset signal. Then the method restores a plurality of selected registers from the current checkpointed state. Next, the method fetches a plurality of instructions from a plurality of restored instruction addresses. Then the method resumes a normal execution after a programmable number of instructions. [0010] One may note the similarity to the instruction retry recovery sequence, but with key differences. Mini-refresh, unlike full recovery, only restores a selected subset of the architected state and does not necessarily invalidate all caches and translation buffers because the coherency with the system has not necessarily been lost. The circuits are presumed functioning properly, and a functional reset is only required for predictably backing up the state of the processor, not for clearing an unpredictable error state from the circuitry. The processor is not necessarily logically removed from a symmetric multi-processing (SMP) system, so incoming invalidates to the processor are still monitored, performed, and responded to. The elements of the reduced performance mode operation are independently selected for the mini-refresh to further optimize (reduce) the performance impact. Finally, thresholding is not done for mini-refresh, and instead forward progress is guaranteed by disabling re-entry to the mini-refresh sequence until after progression beyond reduced execution mode. BRIEF DESCRIPTION OF THE DRAWINGS [0011] The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: [0012] FIG. 1 is a block diagram of a processor system for processing information according to the preferred embodiment; [0013] FIG. 2 is a block diagram of specific components used in a processor system for processing information according to the preferred embodiment; [0014] FIG. 3 is a diagram of the steps required for the mini-refresh in accordance with a preferred embodiment of the present invention; and [0015] FIG. 4 is a diagram of the steps required for one option to address the possibility of broken coherency between the L1 Data cache and the L2 cache, in accordance with a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT [0016] FIG. 1 is a block diagram of a processor 110 system for processing information according to the preferred embodiment. In the preferred embodiment, processor 110 is a single integrated circuit superscalar microprocessor. Accordingly, as discussed further herein below, processor 110 includes various units, registers, buffers, memories, and other sections, all of which are formed by integrated circuitry. Also, in the preferred embodiment, processor 110 operates according to reduced instruction set computer (“RISC”) techniques. As shown in FIG. 1, a system bus 111 is connected to a bus interface unit (“BIU”) 112 of processor 110. BIU 112 controls the transfer of information between processor 110 and system bus 111. [0017] BIU 112 is connected to an instruction cache 114 and to a data cache 116 of processor 110. Instruction cache 114 outputs instructions to a sequencer unit 118. In response to such instructions from instruction cache 114, sequencer unit 118 selectively outputs instructions to other execution circuitry of processor 110. [0018] In addition to sequencer unit 118, in the preferred embodiment, the execution circuitry of processor 110 includes multiple execution units, namely a branch unit 120, a fixed-point unit A (“FXUA”) 122, a fixed-point unit B (“FXUB”) 124, a complex fixed-point unit (“CFXU”) 126, a load/store unit (“LSU”) 128, and a floating-point unit (“FPU”) 130. FXUA 122, FXUB 124, CFXU 126, and LSU 128 input their source operand information from general-purpose architectural registers (“GPRs”) 132 and fixed-point rename buffers 134. Moreover, FXUA 122 and FXUB 124 input a “carry bit” from a carry bit (“CA”) register 139. FXUA 122, FXUB 124, CFXU 126, and LSU 128 output results (destination operand information) of their operations for storage at selected entries in fixed-point rename buffers 134. Also, CFXU 126 inputs and outputs source operand information and destination operand information to and from special-purpose register processing unit (“SPR unit”) 137. [0019] FPU 130 inputs its source operand information from floating-point architectural registers (“FPRs”) 136 and floating-point rename buffers 138. FPU 130 outputs results (destination operand information) of its operation for storage at selected entries in floating-point rename buffers 138. [0020] In response to a Load instruction, LSU 128 inputs information from data cache 116 and copies such information to selected ones of rename buffers 134 and 138. If such information is not stored in data cache 116, then data cache 116 inputs (through BIU 112 and system bus 111) such information from a system memory 160 connected to system bus 111. Moreover, data cache 116 is able to output (through BIU 112 and system bus 111) information from data cache 116 to system memory 160 connected to system bus 111. In response to a Store instruction, LSU 128 inputs information from a selected one of GPRs 132 and FPRs 136 and copies such information to data cache 116. [0021] Sequencer unit 118 inputs and outputs information to and from GPRs 132 and FPRs 136. From sequencer unit 118, branch unit 120 inputs instructions and signals indicating a present state of processor 110. In response to such instructions and signals, branch unit 120 outputs (to sequencer unit 118) signals indicating suitable memory addresses storing a sequence of instructions for execution by processor 110. In response to such signals from branch unit 120, sequencer unit 118 inputs the indicated sequence of instructions from instruction cache 114. If one or more of the sequence of instructions is not stored in instruction cache 114, then instruction cache 114 inputs (through BIU 112 and system bus 111) such instructions from system memory 160 connected to system bus 111. [0022] In response to the instructions input from instruction cache 114, sequencer unit 118 selectively dispatches the instructions to selected ones of execution units 120, 122, 124, 126, 128, and 130. Each execution unit executes one or more instructions of a particular class of instructions. For example, FXUA 122 and FXUB 124 execute a first class of fixed-point mathematical operations on source operands, such as addition, subtraction, ANDing, ORing and XORing. CFXU 126 executes a second class of fixed-point operations on source operands, such as fixed-point multiplication and division. FPU 130 executes floating-point operations on source operands, such as floating-point multiplication and division. [0023] As information is stored at a selected one of rename buffers 134, such information is associated with a storage location (e.g., one of GPRs 132 or CA register 139) as specified by the instruction for which the selected rename buffer is allocated. Information stored at a selected one of rename buffers 134 is copied to its associated one of GPRs 132 (or CA register 139) in response to signals from sequencer unit 118. Sequencer unit 118 directs such copying of information stored at a selected one of rename buffers 134 in response to “completing” the instruction that generated the information. Such copying is called “writeback.”
[0024] As information is stored at a selected one of rename buffers 138, such information is associated with one of FPRs 136. Information stored at a selected one of rename buffers 138 is copied to its associated one of FPRs 136 in response to signals from sequencer unit 118. Sequencer unit 118 directs such copying of information stored at a selected one of rename buffers 138 in response to “completing” the instruction that generated the information. [0025] Processor 110 achieves high performance by processing multiple instructions simultaneously at various ones of execution units 120, 122, 124, 126, 128, and 130. Accordingly, each instruction is processed as a sequence of stages, each being executable in parallel with stages of other instructions. Such a technique is called “pipelining.” In a significant aspect of the illustrative embodiment, an instruction is normally processed as six stages, namely fetch, decode, dispatch, execute, completion, and writeback. [0026] In the fetch stage, sequencer unit 118 selectively inputs (from instruction cache 114) one or more instructions from one or more memory addresses storing the sequence of instructions discussed further hereinabove in connection with branch unit 120, and sequencer unit 118. [0027] In the decode stage, sequencer unit 118 decodes up to four fetched instructions. [0028] In the dispatch stage, sequencer unit 118 selectively dispatches up to four decoded instructions to selected (in response to the decoding in the decode stage) ones of execution units 120, 122, 124, 126, 128, and 130 after reserving rename buffer entries for the dispatched instructions' results (destination operand information). In the dispatch stage, operand information is supplied to the selected execution units for dispatched instructions. Processor 110 dispatches instructions in order of their programmed sequence. [0029] In the execute stage, execution units execute their dispatched instructions and output results (destination operand information) of their operations for storage at selected entries in rename buffers 134 and rename buffers 138 as discussed further hereinabove. In this manner, processor 110 is able to execute instructions out-of-order relative to their programmed sequence. [0030] In the completion stage, sequencer unit 118 indicates an instruction is “complete.” Processor 110 “completes” instructions in order of their programmed sequence. [0031] In the writeback stage, sequencer 118 directs the copying of information from rename buffers 134 and 138 to GPRs 132 and FPRs 136, respectively. Sequencer unit 118 directs such copying of information stored at a selected rename buffer. Likewise, in the writeback stage of a particular instruction, processor 110 updates its architectural states in response to the particular instruction. Processor 110 processes the respective “writeback” stages of instructions in order of their programmed sequence. Processor 110 advantageously merges an instruction's completion stage and writeback stage in specified situations. [0032] In the illustrative embodiment, each instruction requires one machine cycle to complete each of the stages of instruction processing. Nevertheless, some instructions (e.g., complex fixed-point instructions executed by CFXU 126) may require more than one cycle. Accordingly, a variable delay may occur between a particular instruction's execution and completion stages in response to the variation in time required for completion of preceding instructions. [0033] A completion buffer 148 is provided within sequencer unit 118 to track the completion of the multiple instructions which are being executed within the execution units. Upon an indication that an instruction or a group of instructions have been completed successfully, in an application specified sequential order, completion buffer 148 may be utilized to initiate the transfer of the results of those completed instructions to the associated general-purpose registers. [0034] Additionally, processor 110 also includes interrupt unit 150, which is connected to instruction cache 114. Additionally, although not shown in FIG. 1, interrupt unit 150 is connected to other functional units within processor 110. Interrupt unit 150 may receive signals from other functional units and initiate an action, such as starting an error handling or trap process. In these examples, interrupt unit 150 is employed to generate interrupts and exceptions that may occur during execution of a program. [0035] A more robust method is desired to recover processor 110 from failing due to a logic bug in the design that has less performance impact than a full processor recovery. One method of recovery is to use a recovery unit 140 added to the microprocessor core design, as shown in FIG. 1, for the purpose of recovering from soft errors caused by technology problems or Alpha particles via processor instruction retry recovery. [0036] The normal processor recovery mechanism must assume the arrays (Static Random Access Memory—SRAM) such as instruction cache 114, L1 data cache 116, or translation buffers (not shown) are in an invalid state because the error may have occurred in or propagated into such arrays. However, most logic design bugs do not manifest themselves as corruption into the SRAMs, but rather cause incorrect processing of the instruction stream itself, processed in sequencer unit 118, which usually results in corruption of the architected state, such as GPRs 132, FPRs 136, and SPRs 137. [0037] This invention uses existing processor recovery unit 140 to restore the “checkpointed”—previously known good and protected—architected state 142 after the detection that a logic bug has been, or may be encountered. Selectable portions or all of the processor architected register state can then be “quickly” restored from the checkpointed state 142 without having to wait on SRAMs to be cleared or initialized, which happens during “normal” processor instruction retry recovery. Thus, the performance impact of the restore and reset is greatly reduced. [0038] Most importantly, not clearing the caches avoids the performance impact due to cache priming effects from invalidating the cache. [0039] After restoring the checkpointed state 142, processor 110 temporarily goes into a “safe mode” to prevent the same code stream scenario in sequencer unit 118 from causing the logic bug to be repeatedly exposed, because repeated exposure of the same code stream scenario could prevent forward progress from occurring. This “safe mode” of execution processes instructions in sequencer unit 118 in a reduced performance mode until a programmable (e.g., 128) number of instructions have been checkpointed; indicating processor 110 has made it safely past the problem code stream. [0040] Processor 110 supports simultaneous multi-threading (SMT) which is the processing of multiple (e.g. two) independent instruction streams at the same time, while maintaining separate architected register state for each thread. Processor 110 may also be attached via system bus 111 to many other such processors in a large, scaleable, symmetric multi-processor (SMP), capable of executing multiple independent (logically partitioned) operating systems. The control of the logical partitioning is provided by a firmware layer called a “hypervisor”, which has privileged access to some of the special-purpose registers within each processor. When the hypervisor firmware layer is executing, the processor is said to be in hypervisor mode, and this special privileged state is identified by a hypervisor bit (HV) in a machine state register (MSR). Interrupts and exception conditions are also handled by the hypervisor firmware. [0041] The “safe mode” of operation is also executed based on Hypervisor state because the original problem or condition may have occurred in non-hypervisor mode, but a pending interrupt could cause immediate entry to hypervisor mode after backing up to the checkpoint state. Care must be taken to ensure processing does not later resume to the original non-hypervisor code stream in sequencer unit 118 and simply encounter the original condition again. [0042] FIG. 2 is a block diagram of specific components used in a processor system for processing information according to the preferred embodiment, for enhancing performance of recovering a microprocessor from failing. The depicted processor 210 components used most frequently by the present invention include checkpointed state 242 in recovery unit 240, instruction addresses 252 in sequencer unit 218, store queue 246 in load/store unit 228, selected registers, such as GPRs 232, FPRs 236, and SPRs 237, interrupt unit 250, and the caches, such as instruction cache 214, L1 data cache 216, L2 cache 217, and L1 data cache directory 244. [0043] The store queue 246 in the load/store unit 228 is a queue of store instructions that are waiting to be transferred to the L2 cache 217. The L1 data cache directory 244 is a directory that contains the partial addresses and valid bits corresponding to the data entries in L1 data cache 216. L1 data cache 216 is a “store-through” cache, meaning that store data written to the L1 is also written to L2 cache 217 at about the same time, so that any modified data in L1 cache 216 is also available in L2 cache 217. L1 cache 216 is dedicated to the processor, whereas L2 cache 217 is shared coherently across all processors in an SMP system. [0044] Because data in L2 cache 217 is shared across all processors in the system, updates to L2 cache 217 must be held up until the store instructions which caused the updates have reached the checkpointed state. However, it is advantageous for performance to allow L1 cache 216 to be written “speculatively” (e.g. in anticipation of the store instruction reaching the checkpointed state) so that results are available to be accessed by subsequent load instructions as early as possible. However, speculatively updating L1 cache 216 creates the condition where a mini-refresh may back up to a checkpointed state prior to a store instruction which caused the update to L1 cache 216, thus L1 cache 216 contains incorrect, or “corrupted” data. [0045] The preferred embodiment of the mini-refresh sequence implements a selection of one of three ways to deal with this situation: 1) Delay all updates to L1 cache 216 until the corresponding store instructions reach the checkpoint state, and update L1 cache 216 at the same time the data is released to L2 cache 217; 2) Invalidate the entire L1 cache 216; 3) Selectively invalidate only the entries from L1 cache 216 which were speculatively updated for store instructions which did not yet reach the checkpoint state. Option 3 is the preferred solution, because option 1 delays all store data from being available in L1 cache 216, and option 2 incurs the penalty mentioned earlier of “priming” the contents of the L1 cache when processing is resumed from the checkpoint. [0046] FIG. 3 depicts the steps required for the invention's mini-refresh for enhancing performance of recovering a microprocessor from failing. These steps of the present invention can be implemented using specific components of a processor system, such as those depicted in FIG. 2, including checkpointed state 242 in recovery unit 240 and the caches, such as L1 data cache 216, L2 cache 217, and L1 data cache directory 244. [0047] The mini-refresh is invoked through an inter-unit trigger bus by the detecting and reporting of a programmable set and sequence of events which warn of an error (step 302). The triggers can be programmed to look for the particular workaround scenario. These triggers can be direct or can be event sequences such as A happened before B, or slightly more complex, such as A happened within three cycles of B. Depending on the nature of the design bug, the triggers may be selected to detect that the bug just occurred, or may be about to occur. Once invoked, mini-refresh uses a subset of the processor instruction retry recovery sequence. [0048] Mini-refresh locks the current checkpointed state and prevents any other instructions from checkpointing (step 304). All of the checkpointed state stores that in this implementation reside in the store queue, such as store queue 246 in FIG. 2, are released to the L2 cache, such as L2 cache 217 in FIG. 2, and the rest of the stores are dropped (step 306). Interrupts are temporarily cancelled or blocked in the interrupt unit, such as interrupt unit 250 in FIG. 2 (step 308). Power saving logic is overridden to ensure clocks are provided to all circuitry on the processor (step 310). Instruction fetch and instruction dispatch are disabled in sequencer unit, such as sequencer unit 218 in FIG. 2 (step 312). A hardware reset signal is sent to any logic that needs to be reset to an idle state or logic which must be reset to perform the refresh function (step 314). Mini-refresh can optionally reset the L1 data cache directory, such as L1 data cache directory 244 in FIG. 2, (step 316) to invalidate the entire L1 data cache, such as L1 data cache 216 in FIG. 2. Logic which monitors for and processes incoming invalidates remains active (e.g. not reset) to keep the L1 caches and translation buffers synchronized in a symmetric multi-processing (SMP) system. This logic also supports the option of not invalidating the L1 data cache. [0049] At this point, optionally a selectable Hypervisor Maintenance Interrupt (HMI) to the processor (hypervisor firmware) or a special attention interrupt to the service processor (out-of-band firmware) can be made pending in the interrupt unit (step 318). If a special attention to the service processor is selected, the sequence pauses at step 318 to allow immediate handling by the service processor. For example, if a particular latch value needed to be overridden, the service processor could potentially “fix” it through low-level LSSD scanning. A HMI may be made pending to indicate state which is backed by software instead of hardware (e.g. the Segment Lookaside Buffer) was modified after the checkpoint, so must be restored by software when instruction processing resumes. [0050] Next, selectable architected registers, such as GPRs 232, FPRs 236, and SPRs 237, as shown in FIG. 2, are then restored from the checkpointed state in the recovery unit to the units where the state resides (step 320). A sequencer, such as sequencer unit 218 from FIG. 2, accesses values from the recovery unit, such as recovery unit 240 in FIG. 2, and writes to the appropriate register using the normal writeback paths. This refresh from checkpointed state restores any architected register state that may have already been, or were potentially about to be “corrupted” by the design bug. [0051] The fetch unit will then fetch from the restored instruction addresses, such as instruction addresses 252 in FIG. 2, in the Sequencer unit (step 324). If a HMI was made pending in step 318, instruction processing may first start with the interrupt handler in hypervisor mode prior to resuming to the restored checkpoint if the checkpoint was not already in hypervisor mode. Processing will resume from the checkpoint after the hypervisor maintenance interrupt is handled. [0052] Upon restarting, the processor can be optionally put into a “safe mode” to execute a programmable number of instructions in a programmable reduced execution mode (step 326) in an attempt to avoid the design bug detected or warned by the inter-unit trigger. The trigger, or “warning” condition may or may not still be detected during re-execution of the program sequence in reduced performance mode, but re-entry to the beginning of the mini-refresh sequence is disabled when already in reduced performance mode. This “safe mode” consists of different methods of altering the instruction flow in the sequencer unit, such as serialize issue, serialize dispatch, single thread dispatch, force one instruction per group, stop pre-fetching, serialize floating point, etc. [0053] After the programmable number of instructions reaches the checkpointed state, the processor resumes normal execution (step 328). This is similar to a regular instruction retry recovery, but the parameters for the reduced performance mode are separately programmable to minimize the amount and duration of performance degradation for the known situation identified by the trigger. The parameters for the reduced performance “safe” mode are selected by configuration latches which are setup at processor initialization time. [0054] At this point the sequence is considered completed, and the presence of another intra-unit trigger will invoke the sequence again from the beginning. Any errors detected during the mini-refresh sequence will abort the sequence and invoke normal processor instruction retry recovery. [0055] As mentioned above, there is a possibility that stores may have been “speculatively” written into the L1 data cache. These stores will not be sent to the L2 cache because it would break coherency with a write-through cache structure. As an alternative to invalidating the entire L1 data cache as in step 316, the first solution is to prevent this from happening by delaying all writes to the L1 until the corresponding store instructions reach the checkpoint. This mode is selected by a configuration latch which is set during processor initialization. [0056] Waiting for store instructions to reach the checkpoint before updating the L1 cache obviously incurs a performance penalty due to an effectively deeper store pipeline. With aggressive operating frequencies, the time of flight for signals between the checkpoint controls in the recovery unit and the store queue in the LSU may be multiple cycles. Thus, determining whether store data in the store queue has checkpointed may take more than one machine cycle, which incurs the additional performance penalty of not being able to pipeline writes to the L1 cache every cycle. Although perhaps still useful in a bring-up lab environment, because this mode of operation penalizes performance for all stores, regardless of whether any inter-unit triggers are reported to invoke the mini-refresh sequence, this is unlikely to be tolerable in a real product environment. [0057] Another alternative to purging the entire L1 data cache as in step 316, without incurring the performance penalty of delaying all L1 cache updates is to selectively invalidate only L1 cache entries which were speculatively updated beyond the checkpoint. [0058] FIG. 4 depicts the steps for selectively purging only the L1 cache entries which were speculatively updated beyond the checkpoint in order to enhance performance of recovering a microprocessor from failing. The sequence depicted by FIG. 4 is actually processed within step 306 from FIG. 3 when enabled by a configuration latch set at processor initialization time. These steps of the present invention can be implemented using specific components of a processor system, such as those depicted in FIG. 2, including store queue 246 in load/store unit 228, checkpointed state 242 in recovery unit 240, and the caches, such as L1 data cache 216, L2 cache 217, and L1 data cache directory 244. [0059] The store queue (246 from FIG. 2) maintains an instruction tag for each entry which is used to identify whether the corresponding instruction was checkpointed or not. In order to reduce the required number of entries in the store queue and the number of separate store commands to the L2 cache, two different stores to the same line can be “chained” together and share a store queue entry. Therefore an instruction tag must be kept for both stores when chained together in the same queue entry. [0060] After a mini-refresh trigger is presented (step 302 from FIG. 3) and the checkpoint locked (step 304 from FIG. 3), the recovery unit signals the LSU to drain completed stores to the L2 cache and drop stores which have not checkpointed yet (step 306 from FIG. 3), which begins the sequence of FIG. 4. The store queue in the LSU is then processed one entry at a time. Chained stores are separated into separate individual stores (step 404) and the older of the separate stores then processed first. If the individual store has already passed the checkpoint (yes branch from decision step 406) then the store is sent to the L2 cache (step 410). If the individual store has not yet passed the checkpoint (no branch from decision step 406) then the L1 data cache entry corresponding to the store address is invalidated and the store is not sent to the L2 cache (step 408). Remaining individual stores separated from a chained store (yes branch of decision step 412) are processed in the same manner returning to decision step 406. If no more individual stores remain for a store queue entry (no branch of decision step 412) then the store queue is advanced to the next entry (step 414). If the store queue is empty (yes branch of decision step 416) the sequence ends. Otherwise (no branch of decision step 416) then the sequence is started from the beginning (step 404) for the next entry. [0061] Note that all store queue entries must continue to be processed even once entries are encountered where the stores have not yet passed the checkpoint. Because multiple processing threads share the store queue, it is possible that checkpointed stores from one thread are “behind” non-checkpointed stores from another thread. Also, the separated individual stores of a chained store entry may span a checkpoint boundary, and also span stores from other queue entries. The LSU indicates to the mini-refresh sequencing logic that all entries have been processed from the store queue according to FIG. 4, so the sequence in FIG. 3 advances to step 308. [0062] The present invention provides a more robust method to recover the processor from failing due to a logic bug in the design, a recovery that has less performance impact than a full processor instruction retry recovery. The present invention also provides two options to address the possibility of broken coherency between the L1 Data cache and the L2 cache which avoid the need to invalidate the entire L1 data cache. [0063] It is important to note that while the present invention has been described in the context of a fully functioning data processing system, those of ordinary skill in the art will appreciate that the processes of the present invention are capable of being distributed in the form of a computer readable medium of instructions and a variety of forms and that the present invention applies equally regardless of the particular type of signal bearing media actually used to carry out the distribution. Examples of computer readable media include recordable-type media, such as a floppy disk, a hard disk drive, a RAM, CD-ROMs, DVD-ROMs, and transmission-type media, such as digital and analog communications links, wired or wireless communications links using transmission forms, such as, for example, radio frequency and light wave transmissions. The computer readable media may take the form of coded formats that are decoded for actual use in a particular data processing system. [0064] The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4594710 *Dec 15, 1983Jun 10, 1986Fujitsu LimitedData processing system for preventing machine stoppage due to an error in a copy registerUS4912707 *Aug 23, 1988Mar 27, 1990International Business Machines CorporationCheckpoint retry mechanismUS5040107 *Jul 3, 1989Aug 13, 1991International Computers LimitedPipelined processor with look-ahead mode of operationUS5241636 *Feb 14, 1990Aug 31, 1993Intel CorporationMethod for parallel instruction execution in a computerUS5345583 *Apr 5, 1993Sep 6, 1994Scientific-Atlanta, Inc.Method and apparatus for momentarily interrupting power to a microprocessor to clear a fault stateUS5361267 *Apr 24, 1992Nov 1, 1994Digital Equipment CorporationScheme for error handling in a computer systemUS5418916 *Oct 4, 1990May 23, 1995International Business MachinesCentral processing unit checkpoint retry for store-in and store-through cache systemsUS5423026 *Sep 5, 1991Jun 6, 1995International Business Machines CorporationMethod and apparatus for performing control unit level recovery operationsUS5446851 *Jun 8, 1994Aug 29, 1995Matsushita Electric Industrial Co., Ltd.Instruction supplier for a microprocessor capable of preventing a functional error operationUS5452437 *Nov 18, 1991Sep 19, 1995Motorola, Inc.Methods of debugging multiprocessor systemUS5478873 *Aug 31, 1994Dec 26, 1995Sumitomo Chemical Company, LimitedThermoplastic resin compositionUS5495587 *Jun 21, 1994Feb 27, 1996International Business Machines CorporationMethod for processing checkpoint instructions to allow concurrent execution of overlapping instructionsUS5551043 *Sep 7, 1994Aug 27, 1996International Business Machines CorporationStandby checkpoint to prevent data lossUS5590277 *Jun 22, 1994Dec 31, 1996Lucent Technologies Inc.Progressive retry method and apparatus for software failure recovery in multi-process message-passing applicationsUS5630075 *May 25, 1995May 13, 1997Intel CorporationWrite combining buffer for sequentially addressed partial line operations originating from a single instructionUS5664137 *Sep 7, 1995Sep 2, 1997Intel CorporationMethod and apparatus for executing and dispatching store operations in a computer systemUS5692121 *Apr 30, 1996Nov 25, 1997International Business Machines CorporationRecovery unit for mirrored processorsUS5737604 *Sep 30, 1996Apr 7, 1998Compaq Computer CorporationMethod and apparatus for independently resetting processors and cache controllers in multiple processor systemsUS5748873 *Jul 26, 1996May 5, 1998Hitachi,Ltd.Fault recovering system provided in highly reliable computer system having duplicated processorsUS5812757 *Jul 5, 1996Sep 22, 1998Mitsubishi Denki Kabushiki KaishaProcessing board, a computer, and a fault recovery method for the computerUS5867444 *Sep 25, 1997Feb 2, 1999Compaq Computer CorporationProgrammable memory device that supports multiple operational modesUS5872948 *Mar 15, 1996Feb 16, 1999International Business Machines CorporationProcessor and method for out-of-order execution of instructions based upon an instruction parameterUS5892978 *Jul 24, 1996Apr 6, 1999Vlsi Technology, Inc.Combined consective byte update bufferUS5923832 *Mar 14, 1997Jul 13, 1999Kabushiki Kaisha ToshibaMethod and apparatus for checkpointing in computer systemUS5996083 *Aug 11, 1995Nov 30, 1999Hewlett-Packard CompanyMicroprocessor having software controllable power consumptionUS6289428 *Aug 3, 1999Sep 11, 2001International Business Machines CorporationSuperscaler processor and method for efficiently recovering from misaligned data addressesUS6360333 *Nov 19, 1998Mar 19, 2002Compaq Computer CorporationMethod and apparatus for determining a processor failure in a multiprocessor computerUS6393582 *Dec 10, 1998May 21, 2002Compaq Computer CorporationError self-checking and recovery using lock-step processor pair architectureUS6438709 *Dec 29, 1997Aug 20, 2002Intel CorporationMethod for recovering from computer system lockup conditionUS6543002 *Nov 4, 1999Apr 1, 2003International Business Machines CorporationRecovery from hang condition in a microprocessorUS6571324 *Jun 26, 1997May 27, 2003Hewlett-Packard Development Company, L.P.Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache systemUS6625749 *Dec 21, 1999Sep 23, 2003Intel CorporationFirmware mechanism for correcting soft errorsUS6640313 *Dec 21, 1999Oct 28, 2003Intel CorporationMicroprocessor with high-reliability operating modeUS6718483 *Jul 21, 2000Apr 6, 2004Nec CorporationFault tolerant circuit and autonomous recovering methodUS6751756 *Dec 1, 2000Jun 15, 2004Unisys CorporationFirst level cache parity error injectUS6834358 *Mar 28, 2001Dec 21, 2004Ncr CorporationRestartable database loads using parallel data streamsUS6948092 *Jan 31, 2002Sep 20, 2005Hewlett-Packard Development Company, L.P.System recovery from errors for processor and associated componentsUS7055060 *Dec 19, 2002May 30, 2006Intel CorporationOn-die mechanism for high-reliability processorUS7096322 *Oct 10, 2003Aug 22, 2006Unisys CorporationInstruction processor write buffer emulation using embedded emulation control instructionsUS7124224 *Dec 22, 2000Oct 17, 2006Intel CorporationMethod and apparatus for shared resource management in a multiprocessing systemUS20010042198 *Dec 29, 1997Nov 15, 2001David I. PoisnerMethod for recovering from computer system lockup conditionUS20030014736 *Jul 15, 2002Jan 16, 2003Nguyen Tai H.Debugger breakpoint management in a multicore DSP device having shared program memoryUS20030061535 *Sep 21, 2001Mar 27, 2003Bickel Robert E.Fault tolerant processing architectureUS20030208670 *Mar 28, 2002Nov 6, 2003International Business Machines Corp.System, method, and computer program product for effecting serialization in logical-partitioned systemsUS20050044311 *Aug 22, 2003Feb 24, 2005Oracle International CorporationReducing disk IO by full-cache write-mergingUS20050149769 *Dec 29, 2003Jul 7, 2005Intel CorporationMethods and apparatus to selectively power functional unitsUS20060020851 *Nov 10, 2004Jan 26, 2006Fujitsu LimitedInformation processing apparatus and error detecting methodUS20060047958 *Aug 25, 2004Mar 2, 2006Microsoft CorporationSystem and method for secure execution of program codeUS20060143509 *Dec 20, 2004Jun 29, 2006Sony Computer Entertainment Inc.Methods and apparatus for disabling error countermeasures in a processing systemUS20060156177 *Dec 29, 2004Jul 13, 2006Sailesh KottapalliMethod and apparatus for recovering from soft errors in register filesUSH1291 *Dec 20, 1990Feb 1, 1994Hinton Glenn JMicroprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7779305 *Aug 17, 2010Intel CorporationMethod and system for recovery from an error in a computing device by transferring control from a virtual machine monitor to separate firmware instructionsUS7827443Nov 2, 2010International Business Machines CorporationProcessor instruction retry recoveryUS7870369Oct 24, 2007Jan 11, 2011Oracle America, Inc.Abort prioritization in a trace-based processorUS7877630Jan 25, 2011Oracle America, Inc.Trace based rollback of a speculatively updated cacheUS7937564May 3, 2011Oracle America, Inc.Emit vector optimization of a traceUS7941607Jul 24, 2007May 10, 2011Oracle America, Inc.Method and system for promoting traces in an instruction processing circuitUS7949854May 24, 2011Oracle America, Inc.Trace unit with a trace builderUS7953961Jul 23, 2007May 31, 2011Oracle America, Inc.Trace unit with an op path from a decoder (bypass mode) and from a basic-block builderUS7966479Jul 23, 2007Jun 21, 2011Oracle America, Inc.Concurrent vs. low power branch predictionUS7987342Jul 23, 2007Jul 26, 2011Oracle America, Inc.Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencerUS8010745Aug 30, 2011Oracle America, Inc.Rolling back a speculative update of a non-modifiable cache lineUS8015359Sep 6, 2011Oracle America, Inc.Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuitUS8019944Sep 13, 2011Oracle America, Inc.Checking for a memory ordering violation after a speculative cache writeUS8024522Sep 20, 2011Oracle America, Inc.Memory ordering queue/versioning cache circuitUS8032710Oct 4, 2011Oracle America, Inc.System and method for ensuring coherency in trace executionUS8037285Oct 11, 2011Oracle America, Inc.Trace unitUS8037366 *Mar 24, 2009Oct 11, 2011International Business Machines CorporationIssuing instructions in-order in an out-of-order processor using false dependenciesUS8051247Nov 1, 2011Oracle America, Inc.Trace based deallocation of entries in a versioning cache circuitUS8112798 *Feb 7, 2012Microsoft CorporationHardware-aided software code measurementUS8166246 *Apr 24, 2012International Business Machines CorporationChaining multiple smaller store queue entries for more efficient store queue usageUS8370576Feb 5, 2013Oracle America, Inc.Cache rollback acceleration via a bank based versioning cache ciruitUS8370609Feb 5, 2013Oracle America, Inc.Data cache rollbacks for failed speculative traces with memory operationsUS8443227May 14, 2013International Business Machines CorporationProcessor and method for workaround trigger activated exceptionsUS8499293Nov 16, 2007Jul 30, 2013Oracle America, Inc.Symbolic renaming optimization of a traceUS8516303 *Dec 9, 2009Aug 20, 2013Fujitsu LimitedArithmetic device for concurrently processing a plurality of threadsUS8904118Jan 7, 2011Dec 2, 2014International Business Machines CorporationMechanisms for efficient intra-die/intra-chip collective messagingUS8930683 *Jun 3, 2008Jan 6, 2015Symantec Operating CorporationMemory order tester for multi-threaded programsUS8990514Sep 12, 2012Mar 24, 2015International Business Machines CorporationMechanisms for efficient intra-die/intra-chip collective messagingUS9015025 *Oct 31, 2011Apr 21, 2015International Business Machines CorporationVerifying processor-sparing functionality in a simulation environmentUS9043654Dec 7, 2012May 26, 2015International Business Machines CorporationAvoiding processing flaws in a computer processor triggered by a predetermined sequence of hardware eventsUS9098653Nov 14, 2013Aug 4, 2015International Business Machines CorporationVerifying processor-sparing functionality in a simulation environmentUS9195550Feb 3, 2011Nov 24, 2015International Business Machines CorporationMethod for guaranteeing program correctness using fine-grained hardware speculative executionUS9286067Sep 13, 2012Mar 15, 2016International Business Machines CorporationMethod and apparatus for a hierarchical synchronization barrier in a multi-node systemUS20070107056 *May 5, 2006May 10, 2007Microsoft CorporationHardware-aided software code measurementUS20090172471 *Dec 28, 2007Jul 2, 2009Zimmer Vincent JMethod and system for recovery from an error in a computing deviceUS20090198867 *Jan 31, 2008Aug 6, 2009Guy Lynn GuthrieMethod for chaining multiple smaller store queue entries for more efficient store queue usageUS20090210659 *Feb 15, 2008Aug 20, 2009International Business Machines CorporationProcessor and method for workaround trigger activated exceptionsUS20100088544 *Dec 9, 2009Apr 8, 2010Fujitsu LimitedArithmetic device for concurrently processing a plurality of threadsUS20100251016 *Sep 30, 2010International Business Machines CorporationIssuing Instructions In-Order in an Out-of-Order Processor Using False DependenciesUS20110271084 *Nov 3, 2011Fujitsu LimitedInformation processing system and information processing methodUS20120185672 *Jan 18, 2011Jul 19, 2012International Business Machines CorporationLocal-only synchronizing operationsUS20130110490 *May 2, 2013International Business Machines CorporationVerifying Processor-Sparing Functionality in a Simulation Environment* Cited by examinerClassifications U.S. Classification712/218, 714/E11.207, 712/E09.061International ClassificationG06F9/30Cooperative ClassificationG06F9/3851, G06F9/3863European ClassificationG06F9/38H2, G06F9/38E4Legal EventsDateCodeEventDescriptionMar 8, 2005ASAssignmentOwner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FLOYD, MICHAEL STEPHEN;LEITNER, LARRY SCOTT;LEVENSTEIN, SHELDON B.;AND OTHERS;REEL/FRAME:015853/0456Effective date: 20050210RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text: Translations German (26) Dutch (24) French (24) Italian (23) Spanish (23) Polish (21) Russian (20) Serbian (20) Chinese (18) Czech (18) Japanese (18) Swedish (18) Arabic (17) Brazilian Portuguese (17) Greek (17) License OSI-Approved Open Source (35) GNU General Public License version 2.0 (23) GNU General Public License version 3.0 (3) Academic Free License (2) GNU Library or Lesser General Public License version 2.0 (2) Affero GNU Public License (1) Apache License V2.0 (1) Apache Software License (1) BSD License (1) Common Development and Distribution License (1) Common Public License 1.0 (1) Computer Associates Trusted Open Source License 1.1 (1) Educational Community License, Version 2.0 (1) Mozilla Public License 1.1 (1) Python License (1) Sun Industry Standards Source License (1) Public Domain (3) Other License (2) Programming Language C (9) PHP (9) JavaScript (8) C++ (7) Java (7) Python (6) Perl (4) C# (2) Delphi/Kylix (2) PL/SQL (2) Ruby (2) Unix Shell (2) Visual Basic .NET (2) ASP.NET (1) ActionScript (1) Status 5 - Production/Stable (22) 1 - Planning (7) 6 - Mature (7) 4 - Beta (5) 2 - Pre-Alpha (3) 3 - Alpha (2) 7 - Inactive (1) OS Windows (32) Grouping and Descriptive Categories (28) All 32-bit MS Windows (12) All POSIX (12) OS Independent (11) All BSD Platforms (9) 32-bit MS Windows (8) 64-bit MS Windows (6) 32-bit MS Windows (3) OS Portable (2) Classic 8-bit Operating Systems (1) Project is an Operating System Distribution (1) Project is an Operating System Kernel (1) Linux (25) Mac (23) Modern (17) WinXP (9) Linux (8) OS X (5) Vista (4) Win2K (4) Windows 7 (3) FreeBSD (2) Solaris (2) Windows 8 (2) NetBSD (1) BSD (13) Other Operating Systems (8) Microsoft Windows Server 2003 (3) BeOS (1) MS-DOS (1) Other (1) SGI IRIX (1) Win98 (1) WinME (1) Emulation and API Compatibility (7) WINE (4) Cygwin (2) DOSEMU (1) Fink (1) MinGW/MSYS (1) Freshness Recently updated (11) Collection Enterprise (3) Top Apps

type: global

value: This website is a web service that offers software consumers a centralized online location to control and manage open-source software projects and research business software. It provides source code repository hosting, bug tracking, mirroring of downloads for load balancing, a wiki for documentation, developer and user mailing lists, user-support forums, user-written reviews and ratings, a news bulletin, micro-blog for publishing project updates, and other features.


text:
Metal handles can be attached to the rope to help grip.
Steeper, faster and longer rope tows require the use of a "nutcracker". The rider wears a harness around the hips.[7] To this is attached a clamp, much like the nutcracker from which it derives its name, which the rider attaches to the rope. This eliminates the need to hold on and allows the rope to be supported at waist height by pulleys. This system was used on many fields worldwide from the 1940s, and remains popular at 'club fields', especially in New Zealand.[8]
The first T-bar lift in the United States was installed in 1940 at the Pico Mountain ski area.[9] It was considered a great improvement over the rope tow. An earlier, potentially home-grown, T-bar was installed at Rib Mountain (now Granite Peak Ski Area), Wisconsin, in 1937.
Whereas many platter lifts are fairly similar to T-bars and J-bars with the stick attached to a spring box by a retractable cord, Pomas have a detachable grip to the tow cable with the button connected to the grip by a semi-rigid pole. Because they are detachable, most Pomas operate at speeds of around 4 metres (13 ft) per second, while platters and T-bars average 2.5 m/s (8.2 ft/s; 5.6 mph). When a Poma's grip attaches to the cable, the passenger's acceleration is lessened by the spring-loaded pole (however, on faster lifts, there can still be quite a jerk when the pole becomes fully extended). The 1,070-metre-long (3,510 ft) Summit Access / Howqua Poma at Mount Buller, Australia, operated at a swift 6.5 m/s (15 mph) when it was built in 1964.[10]
Some of the longest magic carpets are the 560-foot-long (170 m) installation at Stratton Mountain Resort[12] and the nearly 800-foot (240 m) carpet at Buck Hill in Burnsville, Minnesota, which has an overpass over a ski run.[13] Since 2014, the longest carpet lift, a Funbelt carpet lift, 1204-foot-long (367 m), is installed at Cauterets resort in France Pyrénées. It is covered by a protective gallery.
^ "Technical Information for lifts". SkiLifts.org. Archived from the original on 2007-02-06. Retrieved 2007-04-16. ^ Hochschwarzwald.de: 1. Skilift der Welt in Schollach entdecken (German)
^ Richards, Gordon. "HILLTOP WINTER SPORTS AREA HISTORY". Truckee Donner Historical Society, Inc. Retrieved 16 September 2015. ^ ISHA resources Timeline of Important Ski History Dates
^ Jeremy Davis. "The History of Vermont Skiing: One Hundred Years of Growth". Archived from the original on 2006-10-17. Retrieved 2006-11-16. ^ http://www.knowledgerush.com/kr/encyclopedia/Ski_tow/
^ Jeffries, Jane (Jun 5, 2015). "Canterbury: Fields of dreams". New Zealand Herald. Retrieved 4 April 2017. ^ SkiingHistory.org - accessed 25 May 2008
^ "Lift Features & Highlights". Rocky Mountain Conveyor & Equipment, Inc. Archived from the original on 2007-08-16. Retrieved 2008-02-06. ^ "America's Longest Magic Carpet Ski Lift and New Snowmaking Coming to Stratton". First Tracks! Online. 30 October 2007. Retrieved 2008-02-06. ^ Bill Hudson (January 1, 2009). "Magic Carpet Ride To The Top Of Buck Hill". WCCO-TV. Retrieved 2009-02-16. v
Retrieved from "https://en.wikipedia.org/w/index.php?title=Surface_lift&oldid=778834267"	Categories: Vertical transport devicesSurface liftsSki lift types	Navigation menu
ČeštinaEspañolNederlandsPolskiРусскийSvenskaTürkçe	Edit links	This page was last edited on 5 May 2017, at 13:39.

value: This website is the English-language edition of the free online encyclopedia Wikipedia. It was founded on 15 January 2001 as Wikipedia's first edition and, as of October 2021, has the most articles of any edition, at 6,412,521.


text:
Willa Carson Health Resource Center - Clearwater, FL | Groupon
All Deals 7495 Automotive 154 Beauty & Spas 1277 Food & Drink 438 Health & Fitness 939 Home Services 286
Meal Prep & Wine Delivery 71 Online Learning 72 Personal Services 1569 Personalized Items 1339 Retail 3079 Things To Do 789
1108 North Martin Luther King Junior Avenue, Clearwater, FL 33755 1108 North Martin Luther King Junior Avenue, Clearwater Directions
+17274679411
1108 North Martin Luther King Junior Avenue,
When you need something to do on your day off, visit Clearwater's Willa Carson Health Resource Center, FL and indulge in a day filled with fun and adventure. Head to this place for some fun, laughs, and a great experience.
Willa Carson Health Resource Center in Clearwater is a caring charity that's helping plant the seeds for change in a big way.
Glenwood (1.9 mi)
Orange Blossom Estates (4.1 mi)
Countryside Estates (4.4 mi)
Groupon has verified that the customer actually visited Willa Carson Health Resource Center.

value: This website is an American global e-commerce marketplace connecting subscribers with local merchants by offering activities, travel, goods and services in 15 countries. Based in Chicago, Groupon was launched there in November 2008, launching soon after in Boston, New York City and Toronto.


text:
LINC00472 long intergenic non-protein coding RNA 472 [Homo sapiens (human)] - Gene - NCBI
LINC00472 long intergenic non-protein coding RNA 472 [ Homo sapiens (human) ]
Gene ID: 79940, updated on 11-Sep-2019
LINC00472provided by HGNC
long intergenic non-protein coding RNA 472provided by HGNC
HGNC:HGNC:21380
Ensembl:ENSG00000233237
P53RRA; C6orf155
Broad expression in kidney (RPKM 3.8), thyroid (RPKM 2.0) and 20 other tissues See more
See LINC00472 in Genome Data Viewer
109.20190905 current GRCh38.p13 (GCF_000001405.39) 6 NC_000006.12 (71407864..71420745, complement)
105 previous assembly GRCh37.p13 (GCF_000001405.25) 6 NC_000006.11 (72120876..72130523, complement)
LINC00472 expression is regulated by promoter methylation and associated with disease-free survival in patients with grade 2 breast cancer. Shen Y, et al. Breast Cancer Res Treat, 2015 Dec. PMID 26564482, Free PMC Article
Prognostic and predictive values of long non-coding RNA LINC00472 in breast cancer. Shen Y, et al. Oncotarget, 2015 Apr 20. PMID 25865225, Free PMC Article
Long Noncoding RNA LINC00472 Inhibits Proliferation and Promotes Apoptosis of Lung Adenocarcinoma Cells via Regulating miR-24-3p/ DEDD. Su C, et al. Technol Cancer Res Treat, 2018 Jan 1. PMID 30175664, Free PMC Article
A G3BP1-Interacting lncRNA Promotes Ferroptosis and Apoptosis in Cancer via Nuclear Sequestration of p53. Mao C, et al. Cancer Res, 2018 Jul 1. PMID 29588351
LINC00472 is functionally a tumor suppressor.LINC00472 expression is regulated by promoter methylation and associated with disease-free survival in patients with grade 2 breast cancer.
Title: LINC00472 expression is regulated by promoter methylation and associated with disease-free survival in patients with grade 2 breast cancer.
Patients with high LINC00472 had significantly reduced risk of relapse and death, and they also had more favorable subtypes and better responses to adjuvant chemo- or hormonal therapy.
Title: Prognostic and predictive values of long non-coding RNA LINC00472 in breast cancer.
G66871 (e-PCR)
UniSTS:166728
UniSTS:484748
p53 related lncRNA
FLJ13189
NR_026807.2 RNA Sequence
Transcript Variant: This variant (2) uses an alternate splice site at an internal exon, resulting in a shorter transcript, compared to variant 1.
AI808466, AK023251, AL035467, AW274058
ENST00000651660.1
NR_121612.1 RNA Sequence
AI985403, AK023251, AL035467
NR_121613.1 RNA Sequence
Transcript Variant: This variant (3) lacks an alternate internal exon, resulting in a shorter transcript, compared to variant 1.
AK023251, AL035467, CD674415
NR_121614.1 RNA Sequence
Transcript Variant: This variant (4) lacks an alternate internal exon and uses an alternate splice site, resulting in a shorter transcript, compared to variant 1.
AI498652, AK023251, AL035467
71407864..71420745 complement
Q9H8W2.2 GenPept UniProtKB/Swiss-Prot:Q9H8W2
LINC00472 products
CTD: Comparative Toxicogenomics Database - LINC00472
Transcriptomine: regulation of the LINC00472 gene by nuclear receptor signaling pathways
GeneCard for LINC00472
Human cDNA clones used in NEDO Project / AK023251
Order LINC00472 cDNA clone/Protein/Antibody/RNAi
Order C6orf155 cDNA clone/Protein/Antibody/RNAi

value: This website is part of the United States National Library of Medicine , a branch of the National Institutes of Health . It is approved and funded by the government of the United States.


text:
sylvia4567 on eBaySkip to main contenteBayShop by categoryEnter your search keywordAll CategoriesAdvanced or register':' style="margin-right:3px">Hello -User-.'.replace(/-User-/,escape(a)))+"")}catch(b){document.write("")}})();Hello (Sign in to bid or buy)Daily DealsSellHelp & ContactMy eBayExpand My eBaySummaryBids/OffersWatch ListWish ListAll ListsPurchase HistorySellingMy CollectionsFollowed SearchesMessagesCollect & Spend Learn moreNotificationsylvia4567's profile Change photoRemovePlease sign in to make changes.That file isn't supported. Please only use JPG, GIF, PNG or TIF files.Image file is corrupted. Please try again.That image is too big.That image is too small.There was an unexpected service failure. Please try again.OKAre you sure you want to remove this photo?CancelOK
User ID sylvia4567 (Feedback score 486)
Based in United Kingdom, sylvia4567 has been an eBay member since 09 Jul, 2010Use this space to tell other eBay members about yourself and what you’re passionate about. Give people more reasons to follow you.Please save or cancel your changes.There was an unexpected service failure. Please try again.Please sign in to make changes.OKSaveCancel
Brilliant buyer A+27 Sep, 2016Hope to deal with you again. Thank you.23 Sep, 2016Instant payment thank you19 Sep, 2016many thanks for quick payment15 Sep, 2016Hope to deal with you again. Thank you.12 Sep, 2016
|||||Member since: 09 Jul, 2010|United KingdomFollowingMembersrevivalbooks0 collections . 3,173 followerszavvi_outlet1 collection . 3,091 followershemingwaysuk0 collections . 575 followersmusicmagpie29 collections . 52,088 followersshopto_outlet0 collections . 7,708 followers
18 May, 2016described as fitting a radiator - does not fit a double radiator with a grill on top, although it was good quality I had to return it at my expense and was advised that 20% would be deducted from purchase price - unfair as they described it as fitting a radiator.

value: This website is an American multinational e-commerce corporation based in San Jose, California, that facilitates consumer-to-consumer and business-to-consumer sales through its website.


text:
Breast Champions | eBay
Refine your search for Breast Champions
Unisex Clothing, Shoes & Accs (120)
results for Breast Champions
Follow Breast Champions to get e-mail alerts and updates on your eBay Feed.
Unfollow Breast Champions to stop getting updates on your eBay Feed.
Yay! You're now following Breast Champions in your eBay Feed.Email me new items that match this interest
Breast Champions: Items in search results
Breast Collar Very Heavy "Champion Team Roper" Heavy Hardware for Pulling
By Booger Barter
JEGS 2013 Champion Avenger Pro Stock Pink Breast Cancer Slixx #7189 Decals
Champion Turf medium leather, silver, show bridal, reins and breast collar set
Champion Gloves Receivers Gloves (Breast Cancer Awareness) Palm Logo
2013 Goodwin Champions Chestnut-Breasted Malkoha Animal Kingdom Patch AK-232!
Newly ListedIowa State Cyclones Champion Womens Breast Cancer Awareness Pink T-Shirt (M)
Newly ListedIowa State Cyclones Champion Womens V-Neck Breast Cancer Gray T-Shirt (M)
Newly ListedJ932R Pink Ribbon Breast Cancer Believe Sport Game Champion Star light Sign
Champion Coin Operated Horse Bridle and Breast Collar
Pueraria Mirifica Oil Natural No Side Effect Female Breast Enhancer Champion Her
Newly ListedP592R Pink Ribbon Breast Cancer Bar Pub Beer Sport Game Champion Star Light Sign
WORLD SERIES LEAGUE CHAMPIONS 2007 RARE NEW ERA WHITE PINK BLACK BREAST CANCER
Champion Gloves Lineman Gloves (Breast Cancer Awareness) Palm Logo Small or Med
Vtg 90s Champion Houston Rockets Breast Cancer BLANK Basketball Jersey sz 52
2012 UPPER DECK GOODWIN CHAMPIONS ANIMAL KINGDOM LILAC-BREASTED ROLLER AK-137
A Champion's Guide: To Thriving Beyond Breast Cancer (Faith) by Mueller, Janet
Luke 1977 Mens Champion Double Breasted Knited Cardigan
2012 Goodwin Champions Animal Kingdom Card - Lilac Breasted Roller AK-137
Iowa State Cyclones Champion Women Pink Breast Cancer Half-Zip Sweatshirt (M)
Reinsman Clay Tryan Champion Series - 2" Shaped Tooled Breast Collar - Chestnut
2013 Goodwin Champions Animal Kingdom Card - Chestnut Breasted Malkoha AK-232
CHAMPION DOUBLE DRY WOMENS MEDIUM WHITE BREAST CANCER HEART SHIRT TOP
Champion womens pink black BREAST CANCER sports bra lined Double Dry sz Medium
NEW BREAST CANCER AWARENESS 3 DAYS WALK "EVERY PRINCESS HAPPILY" T-SHIRT TEE
Breast Cancer Survivor Ladies' Champion Double Dry® V-neck Shirt WOW PINK ***NEW
$25.00to $27.00
Lilac Breasted Roller: 2012 Goodwin Champions Animal Kingdom Patch / #AK137 - NM
BRAND NEW WITH TAG World Champion Breast Stroker Blue Mens T-Shirt Small
Breast Cancer Sock Monkey Women's Gray Running Singlet
BRAND NEW WITH TAG World Champion Breast Stroker Blue Mens T-Shirt XL
I Married A Champion Fighter Pink Ribbon Breast Cancer TShirt All Colors & Sizes
Personalised RACE FOR LIFE Wooden Plaque CHAMPION Breast Cancer Charity Donation


text:
Words that end in dyspermatism | Words ending in dyspermatism
http://www.thefreedictionary.com/words-that-end-in-dyspermatism
Dictionary, Encyclopedia and Thesaurus - The Free Dictionary 10,519,588,457 visitors served
Words that end in dyspermatism
Found 1 words that end in dyspermatism. Browse our Scrabble Word Finder, Words With Friends cheat dictionary, and WordHub word solver to find words that end with dyspermatism. Or use our Unscramble word solver to find your best possible play! Related: Words containing dyspermatism
15-letter words that end in dyspermatismSee also
15-letter words that end in dyspermatism

value: This website is an American online dictionary and encyclopedia that aggregates information from various sources.


text:
Schumacher's Family Tree Nursery - Marathon City, WI | Groupon
3759 Wisconsin 107, Marathon City, WI 54448 3759 Wisconsin 107, Marathon City Directions
+17154433777
3759 Wisconsin 107,
Family Tree Nursery in Marathon City is ready to help. Whether it's just a mow or proper detailing of your garden and lawn, Family Tree Nursery lets you rest assured the job was done right. No matter your yard's needs, Family Tree Nursery can promise you a first-rate landscaping.
When you need repairs done around your home, get expert help from the friendly service providers at Family Tree Nursery.
Groupon has verified that the customer actually visited Schumacher's Family Tree Nursery.


text:
Signature Word 2007 05(2)
ScribdBrowseInterestsCareer & MoneyPersonal GrowthPolitics & Current AffairsScience & TechHealth & FitnessLifestyleEntertainmentBiographies & HistoryFictionBrowse byBooksAudiobooksNews & MagazinesSheet MusicBrowse allUploadSign inJoinSignature Word 2007 05(2)Uploaded by librarynanSpellingTextHuman CommunicationComputingWriting5.0 (2)DownloadEmbedView MoreCopyright: Attribution Non-Commercial (BY-NC)Download as PPT, PDF, TXT or read online from ScribdFlag for inappropriate content1Chapter 5
Word’s Proofing Tools
• Word’s proofing tools help you create thoughtful, wellwritten documents. • Word offers a spell checker, grammar checker, and Thesaurus. • You can get information about a document’s readability, translate text, and research specific topics.
• Word’s spell checker finds misspelled words, duplicate words, and irregular capitalizations. • The spell checker compares the words in the document to words in the dictionary. • If it does not find a match, spell checker stops so you can make a correction. • The grammar checker runs with the spell checker and checks for errors in grammar, punctuation, and word usage. 4
• Save the document before starting the spelling and grammar check. • If you want to check a selection rather than the whole document, select the text to check. • Click the Spelling & Grammar button in the Proofing group of the Review tab of the Ribbon or press F7 to start the check. • The spell or grammar checker highlights any suspected error and presents a suggestion for a change. 5
Found Spelling Error
Spell checker stops at the misspelled word
Found Grammar Error
Grammar checker stops at the sentence with an error
Common Correction Choices
• Ignore Once skips the current occurrence, leaving it unchanged. • Ignore All skips all occurrences. • Ignore rule skips the occurrence and ignores the grammar rule for the rest of the check. • Add to Dictionary adds the selection as a word in the main dictionary . • Change replaces the selection with the selected item in the Suggestions list. 8
• Change replaces the selection with the selected item in the Suggestions list. • Change All replaces all occurrences with the selected Suggestion item. • AutoCorrect inserts selected word and its correct spelling the AutoCorrect dialog box. • Explain displays grammar rule information about the selection. 9
Spell Check Only
• By default, Word checks both spelling and grammar. • To turn off the grammar check, click the Check grammar check box in the lower left corner of the Spelling and Grammar dialog box to clear the check box. 10
Editing While Spell Checking
• If the Spelling and Grammar dialog box does not suggest an appropriate correction, you can leave the Spelling and Grammar dialog box to make edits by clicking in the document. • To resume the check, click the Resume button that appears in the Spelling and Grammar dialog box. 11
Changing Spelling Options
• Click the Options button in the Spelling and Grammar dialog box to open the Word Options dialog box with the Proofing settings displayed. • You also can click the Office button, click Word options, and then click Proofing in the left panel. • Use the options to specify how you want the spell checker behave, such as ignoring words in UPPERCASE.
Spelling (Proofing) Options
• What purpose does the dictionary serve for the spell checker? • How do you start a spell check? • How do you correct an error found using the Spelling and Grammar dialog box? • How do you skip all instances of a proper name? • How do you make document edits when the Spelling and Grammar dialog box is open?
• Start a grammar check just as you would a spell check. Click the Spelling & Grammar button in the Proofing group of the Review tab of the Ribbon or press F7 to start the check. • The grammar checker checks the document for variety of grammar and style errors. Click the Ignore Rule button to tell the grammar checker to ignore the rule for he rest of the check. • Click the Next Sentence button to skip a sentence that the grammar checker stopped at. 15
Changing Grammar Checking Options
• To view options for the grammar checker, click the Options button in the Spelling and Grammar dialog box. Or click the Office button, click Word Options, and click Proofing in the left panel. • The key grammar checking options are in the When correcting spelling and grammar in Word section.
• Readability statistics provide useful information about the level of writing in a document, such as the average number of sentences per paragraph and words per sentence. • The Flesch Reading Ease score is based on the average number of syllables per word and the average number of words per sentence. The higher the score, the more readable the document. • The FleschKincaid Grade Level score indicates a grade reading level.
• You must turn on a Word option to have the Readability Statistics dialog box appear after a spell check. • Click Options in the Spelling and Grammar dialog box. Or click the Options button, click Word Options, and click Proofing in the left panel. • Check Show readability statistics in the When Correcting spelling and grammar section to check it.
• Word uses its default CUSTOM.DIC dictionary for spell checks. • If you want, you can create and use your own dictionary rather than adding and removing words in CUSTOM.DIC. • Click the Custom Dictionaries button in Word’s Proofing options to open the Custom Dictionaries dialog box. 20
• Click the New button to start the process for creating a custom dictionary. • Click the Edit Word List button to add words to a custom dictionary. 21
• Click the check box beside a dictionary in the Dictionary List in the Custom Dictionaries dialog box to determine whether spell check uses it. Checked dictionaries are in use. • To change the default dictionary, click the desired dictionary in the Dictionary List of the Custom Dictionaries dialog box, and then click the Change Default button. • To remove a dictionary, click the desired dictionary in the Dictionary List of the Custom Dictionaries dialog box, and then click the Remove button.
Displaying Word Count
• The Status bar displays the document word count. • You also can display a Word Count dialog box with additional statistics. • Either click the word count in the status bar, or click the Word Count button in the Proofing group of the Review tab to open the dialog box. 23
• When you finish reviewing the statistics, click Close.
• How do you start a grammar check? • What button skips a sentence during a grammar check? • Do readability statistics always appear after a spelling and grammar check? • What is a custom dictionary, and why might you want to use one? • How do you create and select a custom dictionary? • How do you display the Word Count dialog box?
• The Thesaurus can find synonyms, antonyms, and related words for a particular word. • To open the Thesaurus, click the Thesaurus button n the Proofing group of the Review tab or press Shift + F7. • The Thesaurus appears in the Research task pane at right. 26
• Click in the Search for text box, type the word for which you want to find a synonym, and press Enter. • A list of synonyms and antonyms appears in the pane. • To insert one of the words from the list, move the mouse pointer over it, click the downpointing arrow that appears, and click Insert. 27
Choosing a Synonym with the Mouse
• You can use the mouse to select a synonym from a shortcut menu. • Rightclick the word for which you want to find a synonym, point to Synonyms in the shortcut menu, and then click the synonym to use. • The synonym replaces the word on which you rightclicked. 28
• If the translation feature is installed, you can use the Research task pane to translate words from one language to another. • Click the Translate button in the Proofing group of the Review tab to open the Research task pane with the translation feature active.
• Type the word to translate in the Search for text box. • Select the language for the translation from the to drop down list. • The translation appears in the task pane. 30
• To turn on Translation ScreenTips, click the Translation ScreenTip button in the Proofing group of the Review tab, and click the desired language. • When the feature is active, you can move the mouse pointer over a word to display a ScreenTip with the translation for the word. 31
• The Research task pane also enables you to search for information from online sources. • Click the Translate button in the Proofing group of the Review tab to open the Research task pane with the research feature active. • Type the term to research in the Search for text box, and then select a research source from the dropdown list below it. • The results will appear in the pane. 32
Inserting Research Information
• You can copy and paste most information from the Research task pane into the document. • When searching for some types of information, an insert button appears. • Click the insert button to add the information to the document. 33
• What feature enables you to find synonyms and antonyms for a word? • How do you find and insert a synonym with the mouse? • Where can you translate text? • How do you turn on the Translation ScreenTips feature? • How do you search for online research information?
• • • Word can check both the spelling and grammar for any document. Spell checking finds misspellings, irregular capitalizations, and duplicated words. When the Spelling and Grammar dialog box finds a suspected error, it stops and offers options for changing or ignoring the error. When the Spelling and Grammar dialog box is open, you can click in the text to edit it, and then click Resume to return to the check. Click Proofing in the left panel of the Word Options dialog box to display spelling and grammar check options.
Grammar checking finds errors in grammar, style, and punctuation. You can enable a feature that displays readability statistics after a spelling and grammar check. You can create and use a custom dictionary for spelling checks. You can display the word count for the document. The Research task pane enables you to find synonyms with the Thesaurus, translate text, and find online research about a topic.
Documents Similar To Signature Word 2007 05(2)Skip carouselCS4642 Programming AssignmentWriting Skills Are an Important Part of CommunicationEDRL 461-FamilyLetterEnglish LESSON PLAN10 Tips to Make PresentationKs 2 Sample TestLP writing (28:1) 5G Watchline Vol III No 24en6Nounslesson plan template - success6th Grade Unit 3 Product AHomonymsHomonymShortcutItalian Spelling and Pronunciation27Dictionary of a via 00 Pier RichA3 Chris Fraser Threads Aspects of Writing K-6Trial Sbp Spm English 2010Body Language eFirst Day ActivitiesDsp Form 1 ChecklistBasic 1 Exam PracticeDummySli StutteringscaleMaking Oral Presentation-35 Speaking TechniquesOur own classroomDocuments About SpellingSkip carouselHow to Teach Phonics by Williams, Lida M.The Dyslexic Reader 2005 - Issue 40Division of Words
Rules for the Division of Words at the Ends of Lines, with Remarks on Spelling, Syllabication and Pronunciation by Hamilton, Frederick W. (Frederick William), 1860-1940The Art Of Writing & Speaking The English LanguageWord-Study and Composition & Rhetoric by Cody, SherwinThe Abington Journal 03-14-2012The Dyslexic Reader 2012 - Issue 61Magazine, or Animadversions on the English Spelling (1703) by G. W.Times Leader 03-12-2012Journalism for Women
A Practical Guide by Bennett, Arnold, 1867-1931Mike Flannery On Duty and Off by Butler, Ellis Parker, 1869-1937Poetical Works by Milton, John, 1608-1674Society for Pure English, Tract 03 (1920)A Few Practical Suggestions by Smith, Logan Pearsall, 1865-1949How Doth the Simple Spelling Bee by Wister, Owen, 1860-1938The Abington Journal 02-01-2012Times Leader 05-28-2012Nm Spelling Bee Tri FoldtmpF728The Dyslexic Reader 2014 Issue 66J5723 ODocuments About Human CommunicationSkip carousel50876_1935-1939tmp9A09.tmpMichif Language MMF Southwest RegionTexas Instruments Sample Verbal Placement Paper Level143958_1925-192948910_1925-1929tmpF412.tmp

value: This website is an American e-book and audiobook subscription service that includes one million titles.


text:
SEASALT Cotton Blouse/Shirt Blue Large White Polka Dot Rushmaker Top | eBay
SEASALT Ladies Multi colour Polka dot Shirt Blouse Top Organic Cotton RRP £35
+ AU $27.42 Postage
SEASALT Citron Rushmaker Shirt Top Vintage Floral Blouse Organic Cotton rp£37.95
racingants (26693 )
Details about SEASALT Cotton Blouse/Shirt Blue Large White Polka Dot Rushmaker Top
“Ex SEASALT, Brand new and excellent quality, however all tags and labels have been removed or ”
-Select- 10 12 16 22 26
Seasalt ~ Long Sleeve Blue Cotton Top ~ Size 18
Postage: + AU $26.82 Postage
223698906669
Last updated on 10 Nov, 2019 02:47:14 AEDST View all revisions
“Ex SEASALT, Brand new and excellent quality, however all tags and labels have been removed or defaced to comply with reseller laws and to prevent un-authorised store returns. No original packaging provided”
Colour: Blue Material: Organic Cotton
Department: Women Theme: Dots
Neckline: Collar Neck Featured Graphics: Polka Dot
Zara Polka Dot Tops & Blouses for Women,
Polyester Polka Dot Tops & Blouses for Women,
Zara Polka Dot Blouse Tops for Women,
Polka Dot Long Sleeve Casual Shirts for Men


text:
Unbranded Multi-Coloured Tibetan Silver Costume Jewellery | eBay
Unbranded Multi-Coloured Tibetan Silver Costume Jewellery
Rose Feather Leaf Flower Tibetan Silver Pearl Rhinestone Brooch Pin Jewellery
10mm Natural Red Stripe Agate Onyx Gems Necklace 18" Tibetan silver love clasps
TIBETAN ENAMEL BETTY BOOP RED SPOTS DRESS PENDANT 22" HOLLOW SLV/PLT NECKLACE
Multi Coloured Tibetan Silver Amber Bracelet, Pendant & Earrings Set
Lovely simulated amber bracelet set supplied with organza gift bag
TIBETAN ENAMEL BETTY BOOP RED FLOWER DRESS PENDANT 22" HOLLOW SLV/PLT NECKLACE
Ending Thursday at 9:10PM BST3d 16hTop Rated PlusClick & Collect
TIBETAN ENAMEL BETTY BOOP YELLOW DRESS PENDANT 22" HOLLOW SLV/PLT NECKLACE
Tibet silver is an alloy containing silver. The pattern of the Pearl is slightly different in every stone. the ring rail is back open, so that the size is adjustable. Due to the lighting for product photography and different screen settings it may cause that the color of the product is not authentically reproduced.
TIBETAN ENAMEL BETTY BOOP RED+HEART DRESS PENDANT 22" HOLLOW SLV/PLT NECKLACE
Ending Tuesday at 4:13PM BST1d 11h
Ladies Bangle Tibetan Silver Asian Elephant Crystal Bead Bracelet Jewelry
Ending Tuesday at 8:09PM BST1d 15hFrom China
TIBETAN ENAMEL BETTY V.TY. BOOP BLUE DRESS PENDANT 22" HOLLOW SLV/PLT NECKLACE
Silver Tone Pink Scroll Clear Crystal Charm Beads Snake European Bracelet 3
Brand New Crystal Glass Bead Charms X3 Will fit European and Snake Charm Bracelets
Ring Vintage Style Shell Black U Natural farbigtibet Silver Intertwined Form
The ring rail is back open, so that the size is adjustable. Tibet silver is an alloy containing silver. Due to the lighting conditions in product photography and different screen settings it may happen that the color of the product is not reproduced authentically.
TIBETAN ENAMEL BETTY BOOP PARTY HAT+ DRESS PENDANT 22" HOLLOW SLV/PLT NECKLACE
Beautiful Pandas Themed Necklace & Earrings Jewellery Set
(charm height = 23 mm) (total height of earrings = 38 mm). The necklace features a Panda (charm height = approx. ).
EQUALITY/ LGBT awareness bracelet (Breast Cancer Charity fundraiser )💕
EQUALITY/ LGBT awareness bracelet.
S925 Santas house silver charm pendant bead For European bracelet bangle
Ending Wednesday at 10:20PM BST2d 17hFrom China
Holiday Beach tree S925 silver charm pendant bead For European bracelet bangle
Ending Wednesday at 4:55PM BST2d 11hFrom China
European 925 sterling solid silver charms Space charm bead For bracelet chain ks
NEW! Pretty BEADED BRACELET, Tibetan Silver, multi-coloured, UK SELLER! :o) 2a
And it is made from Tibetan silver, and multi-coloured beads. It has a wrap-around style with an extender chain which joins the two ends, and it will fit most wrists. It fits on my wrist and I am a larger lady!
NEW! Pretty BEADED BRACELET, Tibetan Silver, multi-coloured, UK SELLER! :o) 1a
Silver Tone Pink Blue Clear Crystal Stone Charm Beads Snake European Bracelet x3
Crystal Glass Bead Charms. Blue Pink & Clear.
Dream miky S925 round silver charm pendant bead For European bracelet bangle
Ending Wednesday at 6:43PM BST2d 13hFrom China
New listingLadies Jewelry Tibet Silver Elephant Rose Multicolor Crystal Beads Bracelet
Ending Sunday at 10:04PM BST6d 16hFrom China
New Fashion jewelry Tibet Tibetan silver bracelet ladies Lucky beads bangle
Tibetan Silver Heart Beaded Bracelet
Tibetan silver jewelry Colorful beaded bracelet bangle


text:
Barneys Co-op Is Leading High-End Stores to Brooklyn - The New York Times
Commercial Real Estate|High-End Retailers Are Scouting Sites in Brooklyn
High-End Retailers Are Scouting Sites in Brooklyn
By JULIE SATOW MAY 18, 2010
A Barneys Co-op will open at 194 Atlantic, building at right, adjacent to Trader Joe’s and close to Urban Outfitters. Credit Todd Heisler/The New York Times
Brooklyn, the new bastion of cool for many New Yorkers, is poised to go mainstream chic. The announcement that Barneys Co-op will open its first store in Cobble Hill has cleared the way for other nationally recognized high-end retailers to make a similar move across the bridge, according to brokers who specialize in representing luxury clothiers.
With the news in March that the Co-op, Barneys New York’s younger, more accessible line, would lease 10,465 square feet on two floors at 194 Atlantic Avenue in Cobble Hill, a number of other retailers who in the past have been more at home in SoHo or on Madison Avenue have begun touring Brooklyn. These include the jewelers Swarovski Crystal, and the clothiers Anthropologie and North Face.
“Someone needed to be first, and now that Barneys Co-op has done it, others will follow,” said Karen Bellantoni, an executive vice president for the retail brokerage firm Robert K. Futterman & Associates. Ms. Bellantoni said that after the Barneys announcement, a boutique based in Manhattan and a national clothing chain, neither of which she would name, hired her to look for space in Brooklyn.
While it isn’t unusual for national retailers to open Manhattan outposts and then expand to Brooklyn — American Apparel and Urban Outfitters, for example, have been in the borough for several years — the $200 T-shirts and $300 jeans at the Co-op are aimed at wealthier shoppers.
“Brooklyn has the demographics to support this kind of retail, but until now, no national store was willing to take the chance,” said Joanne Podell, the executive director of retail services at Cushman & Wakefield.
One reason for the moves is that the retail industry may be on the mend. Retail sales surged 8.8 percent nationally in April compared with April 2009, according to the Commerce Department. Meanwhile, consumer confidence rose to 57.9 in April, its highest level since September 2008, according to the Conference Board.
Retail rents have remained relatively low, too, creating the perfect climate for expansion, say analysts. “Retailers with better balance sheets will expand in this market because they are seeing sales strengthen,” said Suzanne Mulvee, a real estate strategist for the research firm CoStar Group, “while at the same time rental rates are still incredibly low, allowing them to steal market share from competitors who are being more conservative.”
Because of its strong demographics and heavy foot traffic, the Cobble Hill area is the most likely target for upscale retailers. “The economics of Cobble Hill are as good as the Upper East Side or Upper West Side,” said Noel Caban, a vice president for retail at CB Richard Ellis who, with Richard Hodos, an executive vice president there, represented Barneys in the transaction. Stephen J. Bartha of S. J. Bartha Consulting Group also represented Barneys.
Cobble Hill is in the heart of brownstone Brooklyn, where apartment prices regularly top $1 million and the average household income is more than $109,000, according to the Census Bureau’s 2008 American Community Survey. In comparison, the average household incomes on the Upper West Side and SoHo — where two of the three Barneys Co-ops in New York are located — are $177,000 and $181,000, respectively. The other is in Chelsea.
National retailers are seeking space in an area that is already home to highend boutique stores, like Michelle New York and Jonathan Adler. Credit Todd Heisler/The New York Times
Cobble Hill is close to downtown Brooklyn and the thousands of office workers there. More than 100,000 people live within a mile of the new Barneys Co-op, and numerous subway lines converge there. It is also near the Fulton Street Mall, which is visited by 100,000 shoppers daily and where a hotly anticipated H&M clothing store is expected to open next year.
As for Barneys New York, it seems to be riding the wave of an improving industry. The company said its sales grew 20 percent in March, after smaller gains in January and February. In addition to the Brooklyn site, it plans to open another Co-op in Santa Monica, Calif.
It chose Brooklyn because, after analyzing its customer database, it discovered that many of its customers already lived in the area. It also helped that several Barneys executives were residents of the borough. Company officials say they chose Atlantic Avenue after roughly one year of looking at its demographics, its proximity to the busy retail corridor on Smith Street, and its location on the same block as Trader Joe’s and Urban Outfitters.
“We are opening the Brooklyn store for the same reason we opened our location on the Upper West Side: it’s where our customers are living, and they appreciate us coming to their neighborhoods,” said Dawn Brown, the vice president of publicity for the retailer.
The asking rents in Cobble Hill are roughly 20 to 25 percent of what is available in prime Manhattan spots like SoHo. Two Trees Management, the landlord at 194 Atlantic Avenue, was initially asking $85 a square foot for the 10-year lease but “the space was a little off of center and they weren’t on a corner, so Barneys ended up with a nice value,” said Mr. Caban of CB Richard Ellis, who declined to give the specific taking rent. Caroline Pardo, director of leasing for Two Trees, represented the landlord.
Sandra Dowling, the owner of Brooklyn Heights Real Estate, said she welcomed the store. “We are developing more and more residential space on Atlantic, bringing a significant high-end customer to the neighborhood,” she said, “and there just isn’t enough retail shopping for them.”
But while brokers say there is increased interest in Cobble Hill as a high-end retail destination, there are still stumbling blocks. Most notable is the paucity of spaces big enough for national retailers. There are few options on Atlantic Avenue, and Smith Street, while desirable, has mostly stores in the 1,000-square-foot range. Williamsburg, which offers roomier retail options, is less appealing because of its lack of density and access to mass transportation.
Among the potential Brooklyn tenants that haven’t yet made the move, Apple may be the most famous. It has looked “for years,” said Marty Markowitz, the borough president, who has been trying to lure the retailer.
In his most recent effort, he created a video last month on his iPad to promote the combined forces of the borough and the store, sending the results to Apple’s chief executive, Steven P. Jobs. “I must not have won any acting awards, since I’ve yet to get any response,” Mr. Markowitz said. He said he was considering traveling to Cupertino, Calif., where Apple is based, “and hanging out outside until Mr. Jobs agrees to see me.”
Amy Barney, a spokeswoman for Apple, said, “We have made no announcement about a store in Brooklyn.” Still, while there may be some challenges getting a critical mass of exclusive retailers into the borough, there is certainly a surge in interest. “There is an aggregating affect taking place in the area, with H&M at one end and Barneys Co-op at the other,” said Joe Chan, the president of the Downtown Brooklyn Partnership. “Atlantic Avenue may not turn into Madison Avenue, but will other high-end retailers come here? Most definitely.”
A version of this article appears in print on May 19, 2010, on Page B8 of the New York edition with the headline: High-End Retailers Are Scouting Sites in Brooklyn. Order Reprints| Today's Paper|Subscribe
Baltimore Puts Hope for West Side on Arts District MAY 18, 2010

value: This website is an American daily newspaper based in New York City with a worldwide readership. Founded in 1851, the Times has since won 132 Pulitzer Prizes, the most of any newspaper, and has long been regarded within the industry as a national "newspaper of record".


text:
8gb ddr3 1600mhz | eBay
Related: ddr3 16gb 1600mhz 8gb 1600mhz ddr3 sodimm ddr3 1600mhz 4gb 8gb ddr3 1600mhz dimm 8gb ddr3 1600mhz desktop 1600 mhz ddr3 8gb macbook 1600 mhz ddr3 8gb mac
7,625 results for 8gb ddr3 1600mhz
Save 8gb ddr3 1600mhz to get e-mail alerts and updates on your eBay Feed.
Unfollow 8gb ddr3 1600mhz to stop getting updates on your eBay feed.
8gb ddr3 1600mhz:
Did you mean: 8 gb ddr 3 1600mhz (5,701 items)?
Desktop Memory Ram DDR3 1600mhz PC3-12800U DIMM 240Pin Unbuffered CL11 4gb 8gb
1.35v EXCELLENT WORKING CONDITION, NEXT DAY DELIVERY.
Laptop Memory RAM DDR3 PC3 12800S 1600MHz 204 pin SODIMM 2 x GB 4GB 8GB Lot
£15.00 to £57.00
8GB (1x8GB)DDR3 PC3L-12800S 1600 MHz Laptop SODIMM RAM Memory Upgrade 204-Pin
See more like this8GB (1x8GB)DDR3 PC3L-12800S 1600 MHz Laptop SODIMM RAM Memory Upgrade 204-Pin
QUMOX 16GB(2x 8GB) DDR3 1600MHz PC3-12800 (204 PIN) SO-DIMM MEMORY 2 pices
1X 2X 4 8 16 GB DDR3 1600 MHz PC3 12800 Non-ECC desktop PC Memory RAM UK LOT
£5.49 to £74.94
Laptop Notebook Memory Ram DDR3 1600 mhz PC3-12800 204PIN soDIMM CL11 LOT 4gb8gb
Laptop Memory RAM DDR3L PC3L 12800S 1600MHz 204 pin SODIMM 2 x GB 4GB 8GB Lot
£7.50 to £57.00
Qumox 8GB 1600MHz DDR3 DDR3L PC3-12800 /PC-12800 (204 PIN) SO-DIMM MEMORY 1.35v
1X 2x 2 4GB 8GB DDR3-1600MHz PC3-12800 Non-ECC Desktop Memory RAM UK LOT
New listing Crucial 8GB 2Rx8 PC3-12800S SODIMM RAM Laptop Memory Intel DDR3 1600Mhz RAM
Memory RAM Gaming Desktop 8GB 2x4GB DDR3 1600 MHz PC3 12800 Non ECC DIMM
See more like thisMemory RAM Gaming Desktop 8GB 2x4GB DDR3 1600 MHz PC3 12800 Non ECC DIMM
SKhynix 8GB 2x4GB HMT451U6BFR8A PC3-12800U DDR3 1600Mhz Desktop RAM PC 240PIN
Corsair XMS3 ddr3 1600mhz 8gb (2x4GB) - cas9
8GB (2x4GB) Corsair XMS3 PC3-12800 DDR3-1600 DDR3 RAM 1600 MHz 11,11,11,30 1.5V
Micron 8GB PC3-12800R (DDR3-1600Mhz, 2RX4) ECC Registered RAM
See more like thisMicron 8GB PC3-12800R (DDR3-1600Mhz, 2RX4) ECC Registered RAM
DDR3 Desktop Memory RAM 2GB/ 4GB / 8GB DDR3 1600mhz PC3-12800 DIMM Gaming
Used Micron 8GB DDR3 PC3-12800 1600 MHz 204pin SODIMM Laptop RAM
Corsair Vengeance Low Profile DDR3 16Gb Kit, CL9 1600MHz RAM, CML8GX3M2A1600C9
See more like thisCorsair Vengeance Low Profile DDR3 16Gb Kit, CL9 1600MHz RAM, CML8GX3M2A1600C9
8GB (2x4GB) CORSAIR VEGEANCE 1600MHz DDR3 204-PIN LAPTOP RAM MEMORY (RN480)
4gb 8GB 16GB Laptop Notebook Memory Ram DDR3L 1600mhz PC3-12800S soDIMM
£13.40 to £35.40
Memory Ram 4 Laptop DDR3 PC3 12800 1600 MHz 204 pin SODIMM Low Non ECC GB 2x Lot
£14.91 to £261.44
8GB (1x8GB)DDR3 PC3-12800S 1600 MHz Laptop SODIMM RAM Memory Upgrade 204-Pin
New listing 8GB DDR3 1600Mhz RAM
Hyperx 8gb ddr3 1600mhz
Corsair Dominator 8GB (4x2GB) DDR3 1600MHz
Corsair XMS3 8GB(2x4GB) DDR3 1600MHz RAM
Corsair ValueSelect 8GB (1x 8GB) 1600MHz DDR3 RAM - FREE DELIVERY
New listing Corsair DDR3 8GB RAM 1600 MHz
New 8GB (2x4GB) DDR3-1600MHz PC Desktop Memory For Hyperx Ram PC3-12800 DIMM RAM
16GB(2×8gb) DDR3-12800-1600MHz Laptop RAM
New listing Integral 8GB DDR3 1600MHz SODIMM - IN3V8GNAJKXLV 1.35v Laptop memory RAM
See more like thisIntegral 8GB DDR3 1600MHz SODIMM - IN3V8GNAJKXLV 1.35v Laptop memory RAM
RAM SAMSUNG DDR3 8GB - 2X4GB 12800U 1600MHZ
New listing Hynix HMT351U6CFR8CPB (8GB, PC3-12800 (DDR3-1600), DDR3 SDRAM, 1600 MHz,...
Crucial 8GB Kit (2 x 4GB sticks) DDR3 1600MHz Desktop Memory PC RAM
Corsair (8 GB (4GBx2), (DDR3-1600), DDR3 RAM, 1600 MHz)
New listing Hyperx fury 8gb 1600MHz DDR3 Ram
Kingston HyperX Fury HX316C10F/8 (8 GB) , DDR3 SDRAM, 1600 MHz,
8GB 2Rx8 PC3-12800 DDR3 1600Mhz Memory Ram for MacBook Pro Mid-2012 13" A1278 #E
Corsair CMX8GX3M2A1600C9 (8 GB, PC3-12800 (DDR3-1600), DDR3 SDRAM, 1600 MHz, DIM
See more like this8GB DDR3 1600MHz PC3-12800U CL11 PC3-1600 DIMM RAM memory Only AMD Chipset AM3 @
New listing Ballistix Sport VLP 16GB Kit 8GBx2 DDR3 1600 Mhz PC3-12800 UDIMM 240-Pin Memory
100% New 8GB 2x 4GB DDR3 PC3-12800 1600MHZ CL11 DIMM 240PIN AMD Desktop Memory
New listing SK HYNIX 8GB 2X4GB DDR3 PC3L-12800 1600 Mhz SODIMM Laptop Memory RAM
Ram Crucial CT2K51264BD160B 8GB - 2x4GB DDR3 1600MHz DIMM 240-pin Memory Kit
New listing Patriot PSD38G1600K 8GB (2 x 4GB) DDR3 PC3-12800 (1600MHZ) DIMM Kit
See more like thisPatriot PSD38G1600K 8GB (2 x 4GB) DDR3 PC3-12800 (1600MHZ) DIMM Kit
Crucial Ballistix 8GB, (2x4GB) DDR3-1600MHz
Crucial 16 GB 2x8gb (DDR3-1600), DDR3 RAM, 1600 MHz
See more like thisCrucial 16 GB 2x8gb (DDR3-1600), DDR3 RAM, 1600 MHz
8GB Samsung (1x) DDR3L 12800S PC3L 1600 Mhz SODIMM Memory module -Mac/Laptop
8GB(2X4GB) DDR3 Desktop PC PC3 12800U 1600MHz Non ECC Unbuffered -sp
Computers/Tablets & Networking (7,956)
Computer Components & Parts (7,663)
Memory (RAM) (7,626)
Other Components & Parts (52)
Laptop Replacement Parts (20)
8 GB (6,593)
DIMM (2,585)
SO-DIMM (4,159)
1 (4,547)
2 (982)
16 GB (253)
8 GB (6,658)
2 GB (253)
Corsair (314)
Crucial (248)
G. SKILL (60)
Hynix (146)
Unbranded (1,425)
204 (659)
240 (1,069)
DDR3 SDRAM (7,509)
PC2-5300 (DDR2-667) (22)
PC2-6400 (DDR2-800) (13)
PC3-10600 (DDR3-1333) (108)
PC3-12800 (DDR3-1600) (4,665)
PC3-8500 (DDR3-1066) (5)
Seller refurbished (182)
This page was last updated: 17-Jan 16:10. Number of bids and bid amounts may be slightly out of date. See each listing for international postage options and costs.