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Patent US7511588 - Flux linked LC tank circuits forming distributed clock networks - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsCMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense....http://www.google.com/patents/US7511588?utm_source=gb-gplus-sharePatent US7511588 - Flux linked LC tank circuits forming distributed clock networksAdvanced Patent SearchPublication numberUS7511588 B2Publication typeGrantApplication numberUS 11/185,001Publication dateMar 31, 2009Filing dateJul 19, 2005Priority dateJul 19, 2005Fee statusPaidAlso published asUS20070018740, US20080007358, US20080074202Publication number11185001, 185001, US 7511588 B2, US 7511588B2, US-B2-7511588, US7511588 B2, US7511588B2InventorsThaddeus John GabaraOriginal AssigneeLctank LlcExport CitationBiBTeX, EndNote, RefManPatent Citations (29), Non-Patent Citations (6), Referenced by (22), Classifications (12), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetFlux linked LC tank circuits forming distributed clock networks
US 7511588 B2Abstract
CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. In one example, the distribution of a 45� separated multi-phase balanced oscillations over the surface of die 1.6 cm�1.6 cm at 10 GHz is expected to dissipate under 10 W and offers a potential to significantly reduce the road map predictions of 100 W. Simulations of several CMOS tank circuits indicate that the power dissipation can be reduced an order of magnitude when compared to conventional techniques. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of an oscillator are described.
1. An oscillator network comprising:
at least one oscillator network output;
a first tank circuit;
at least one additional tank circuit; wherein
each tank circuit comprises
a plurality of coils each having a first and second lead,
at least one coil encompassing a first surface different from a second surface encompassed by the remaining coils,
at least two transistors of one conductivity type cross coupled to each other, and
at least one coil in the first tank circuit having a flux linkage to at least one coil in the additional tank circuit, wherein
at least one of the coils in the first tank circuit overlaps and shares a common encompassed surface on a first substrate with at least one of the coils in one of the additional tank circuits.
at least one of the plurality of coils in each tank circuit is located on the first substrate and the remaining coils are located on a different substrate.
3. The network of claim 1 further comprising;
at least one adjustable capacitor.
4. The network of claim 2, wherein
the coil from the first substrate is juxtaposed to one of the remaining coils located on the different substrate.
5. A method of synchronizing a clock network formed on a substrate comprising the steps of:
placing a plurality of tank circuits on the substrate; whereby
at least one tank circuit comprises
the first and second leads of the plurality of coils directly connected respectively to the first and second outputs, and
at least one coil encompassing a first surface different from a second surface encompassed by the remaining coils;
linking the flux of at least one coil in a first tank circuit selected from the plurality of tank circuits to the flux of at least one coil in a second tank circuit selected from the plurality of tank circuits to exchange information;
overlapping and sharing a common encompassed surface between at least one of the coils in the first tank circuit and at least one of the coils in the second tank circuit; and
utilizing the exchanged information to automatically self-align a clock signal generated by the plurality of tank circuits; thereby
synchronizing the clock network.
the exchanged information is continuously updated to maintain synchronization.
the tank circuits further comprises;
a means for regeneration.
the clock network is synchronized on the substrate.
the clock network generates at least two different phases of the clock signal.
the plurality of tank circuits are substantially the same.
a startup circuit provides an initial energy to the network
12. A clock generating system comprising:
a regenerative circuit; and
an interconnection network that couples the two or more tank circuits together, wherein
at least one coil from the first tank circuit overlaps and shares a common surface of a substrate with at least one coil from the additional tank circuit.
the interconnection network comprises:
a flux-linked network that couples a flux associated with a coil in the first tank circuit to the flux associated with a coil in the additional tank circuit.
14. The system of claim 12 where the tank circuit further comprises:
15. An apparatus for generating a synchronized clock signal on a surface of a substrate comprising:
a plurality of tank circuits; wherein
a regenerative circuit,
a means of connecting the regenerative circuit, coils and capacitor together to form the tank circuit;
at least one of the coils from a first tank circuit overlaps and shares a common surface with at least one coil from a second tank circuit, and
a means of coupling together the plurality of tank circuits placed on the surface of the substrate to generate the synchronized clock signal.
16. An oscillator network comprising:
each of the plurality of tank circuits comprises a first and second lead of a first coil respectively coupled to a first and second lead of at least one additional coil,
at least one coil encompassing a first surface different from a second surface encompassed by the remaining coils, and
the first and the at least one additional coils are directly connected respectively to a first and second output terminal;
at least one coil from each of the plurality of tank circuits has a flux linkage coupling formed to at least one coil in at least one of the remaining tank circuits;
at least one coil from each of the plurality of tank circuits overlaps and shares a common surface with at least one coil in at least one of the remaining tank circuits; and
at least one continuous path formed through all the tank circuits; wherein
the path comprises a flux linkage coupling between the coils of two different tank circuits.
17. A multi-phase magnetically linked oscillator network comprising:
a plurality of multi-phase oscillator circuits;
each multi-phase oscillator circuit comprises
a plurality of balanced outputs, and
a plurality of tank circuits coupled in series to form a closed loop structure; at least one of the tank circuits comprises
a first and second output, and
a plurality of coils each having a first and second lead directly connected respectively to the first and second outputs;
a flux linkage formed between a coil selected from a first multi-phase oscillator circuit and a coil selected from a second multi-phase oscillator circuit;
at least one of the coils in the tank circuit from the first multi-phase oscillator circuit has an encompassed surface on a first substrate different from at least one of the remaining coils in the tank circuit in the first multi-phase oscillator circuit; and
at least one of the coils in a tank circuit from the first multi-phase oscillator circuit overlaps and shares a common encompassed surface on the first substrate with at least one of the coils in a tank circuit in one of the remaining multi-phase oscillator circuits.
the coils on the periphery of the surface of a substrate are modified from the initial value of inductance by a multiplication factor of (1+k) to satisfy the boundary condition of the apparatus.
20. The network of claim 17, wherein
at least one of the multi-phase outputs from the first multi-phase oscillator circuit is synchronized to one of the multi-phase outputs from the second multi-phase oscillator circuit.
21. A multi-phase magnetic field coupled oscillator network comprising:
a first multi-phase oscillator circuit comprising
a first plurality of tank circuits coupled in series to form a first closed loop structure,
a first and a second output coupled to one of the first plurality of tank circuits, and
a first plurality of coils each having a first and a second lead directly connected respectively to the first and second outputs;
a second multi-phase oscillator circuit comprising
a second plurality of tank circuits coupled in series to form a second closed loop structure,
a third and a fourth output coupled to one of the second plurality of tank circuits, and a
second plurality of coils each having a first and a second lead directly connected respectively to the third and fourth outputs; and
at least one coil from the first plurality of coils having a magnetic field coupling to at least one coil from the second plurality of coils;
at least one coil from a tank circuit in the first multi-phase oscillator circuit has an encompassed surface on the substrate different from at least one of the remaining coils from the tank circuit in the first multi-phase oscillator circuit; and
at least one coil from the tank circuit from the first multi-phase oscillator circuit overlaps and shares a common encompassed surface on a substrate with at least one of the coils from a tank circuit in the second multi-phase oscillator circuit.
22. The network of claim 21, wherein
the magnetic field coupling synchronizes the network.
23. An oscillator network comprising:
a plurality of tank circuits;
a first tank circuit selected from the plurality of tank circuits comprising
a first plurality of coils each having a first and second lead directly connected respectively to a first and second output of the first tank circuit, and
at least one coil from the first plurality of coils encompassing a first surface different from a second surface encompassed by the remaining coils from the first plurality of coils;
a second tank circuit selected from the plurality of tank circuits comprising
a second plurality of coils each having a first and second lead directly connected respectively to a first and second output of the second tank circuit; and
an interconnect network that couples a coil from the first plurality of coils to at least one coil from the second plurality of coils; and
at least one of the coils from the first tank circuit overlaps and shares a common encompassed surface on a substrate with at least one of the coils in the second tank circuit.
24. The oscillator network of claim 23, wherein
the interconnect network comprises at least one flux linkage between two coils.
25. The oscillator network of claim 23, wherein
the interconnect network synchronizes the oscillator network.
26. The oscillator network of claim 23, wherein
the plurality of tank circuits are distributed over the surface of the substrate and are magnetically coupled together to generate a synchronized clock signal.
27. An oscillator network comprising:
a plurality of coils where each of the coils has a first and second lead;
a plurality of tank circuits where each of the tank circuits has a first and second output;
the first and second outputs of a first tank circuit selected from the plurality of tank circuits are directly connected respectively to the first and second leads of at least one or more coils selected from the plurality of coils;
the first and second outputs of each additional tank circuit selected from the plurality of tank circuits are directly connected respectively to the first and second leads of at least two or more coils selected from the remaining plurality of coils, and
at least one coil from the first tank circuit encompassing a first surface different from a second surface encompassed by the remaining coils from the first tank circuit;
at least one coil from first tank circuit overlaps and shares a common encompassed surface on a substrate with at least one coil from one of the remaining tank circuits; and
at least one coil from each of the plurality of tank circuits has a flux linkage coupling formed to at least one coil in at least one of the remaining tank circuits.
28. The oscillator network of claim 27, wherein
at least one continuous path can be traced through all the tank circuits and the flux linkage coupling formed between the coils of the oscillator network.
29. The oscillator network of claim 27, wherein
the flux linkage coupling synchronizes the oscillator network. Description
The present application is related to the co-filed U.S. applications Ser. Nos. 11/184,768, 11/184,767 and 11/184,428 filed on Jul. 19, 2005, which are invented by the same inventor as the present application and incorporated herein by reference in their entireties.
Electronic consumer products are pushing both the bounds of computation complexity and high clocking frequencies. The systems that are experiencing these problems include: VLSI (Very Large Scale Integration), microprocessors, ASIC's (Application Specific Integrated Circuit), SOC (System On a Chip) and FPGA's (Field Programmable Gate Arrays). All of these systems operate at clock frequencies that increase dramatically each year. This higher clock frequency coupled with the increased size of the die creates some fundamental problems in heat removal from the die and clock distribution over the surface of the die.
P = 1 2 CV 2 f ( 1 ) which for a 1 pF load being clocked at a frequency of 10 GHz is 7.2 mW. Adiabatic techniques can reduce these power dissipation levels. It would be worthwhile to investigate if these techniques can be used advantageously to help solve these problems.
The calculation of the values of planar inductors are provided in a published paper, “Simple Accurate Expressions for Planar Spiral Inductances”, IEEE J. Solid-State Circuits, Vol. 34, No. 10, October 1999, by Mohan et al., hereafter referred to as the “Mohan” reference.
In 0'Mahony et al., a U.S. PGPUB. 2003/0001652 A1 published Jan. 2, 2003, they use a hierarchical clock distribution. The clock is sent to a plurality of clock grids by way of transmissions lines, and then each grid distributes the clock to the load. They use salphasic clocking which takes advantage of standing waves along a transmission line. The position of the receiver points must conform to positions that are multiple of one-half wavelength from one another dependant on the clock frequency. This will lock the frequency of the die into a range dependant on the half-wavelength. The loads however do not have to obey this constraint.
In Galton et al., “Clock Distribution Using Coupled Oscillators”, Proceeding of the 1996 IEEE Inter. Symp. On Circuits and Systems, May 12-15, Vol. 3, pp. 217-220, they suggest using strongly coupled RC oscillators to distribute a clock signal over the die. Their technique uses transmission line that can be less than a quarter of a wavelength long. In addition, the transmission line can be lossy to couple the RC oscillators. Injection locking is used to lock all the oscillators in frequency.
In Hall et al., “Clock Distribution Using Cooperative Ring Oscillators”, Proc. IEEE 17th Conf. Advanced Research in VLSI, 1997, pp. 62-75, a cooperative ring oscillator is used to distribute a clock signal within the die. They also provide multiple clock phases in the distribution. Their circuit expands the ring oscillator from a simple ring to an N-dimensional mesh. This array does not have to be regular. One of the concerns is aggregation that is the non-ideal characteristic variations of the VLSI interconnect. This is a concern since interconnect that is used to connect the inverters of the ring oscillators. This factor dissipates power and introduces skew into the network.
In Wood et al., “Rotary Travelling-Wave Oscillator Arrays: A New Clock Technology”, IEEE J. Solid-State Circuits, Vol. 36, No. 11, November 2001, a rotary traveling wave oscillator array is presented. It consists of a balanced set of transmission lines with distributed CMOS latches to power the oscillation and ensure rotation lock. A waveform propagates along the balanced transmission line that is looped at its ends so that the wave continues to propagate. In their design it is important that careful attention is required to guard against magnetic field coupling between the clock conductors since it will affect the potential performance of their oscillators.
Clock networks and clock generation in VLSI chips is a critical issue to high performance circuit operation. The distribution and minimization of power dissipation of the clock network is an important consideration when designing VLSI circuits. The adiabatic behavior of resonant circuits can be utilized to help resolve both of these designs considerations. Inductors and capacitors play a key role in energy recycling and distribution. The CMOS tank circuit or oscillator serves as the fundamental building block to create, distribute and maintain high frequency behavior in VLSI designs at low power dissipation levels.
The basic invention is connect many CMOS tank circuits together and use the electrical and flux linkage of the resonant circuits to achieve a unified circuit behavior that is beneficial to the generation and propagation of clock signals over a surface region of the VLSI die. Thus, this network will distribute and synchronize a clock signal over the surface of a die.
One aspect of this invention is to connect several tank circuits together to create multi-phase signal generation. Such a circuit configuration is useful to control the operation of a state machine or operate on the I and Q signals within RF (Radio Frequency) circuits. In particular, it would be desirable to also have these signals and their compliments. The connection of these tank circuits is formed in a loop thereby adding feedback to the circuit to preferentially obtain clock signals at different clock phase increments.
Another aspect of the invention is to utilize the flux linkage between the two inductors to synchronize the operation of tank circuits. The structure to obtain this behavior is known as the transformer. In its simplest form, the transformer consists of two inductors that have a mutual coupling coefficient k that can vary between 0 and 1. Lenz's law is utilized by using the flux linkage between the two coils to influence each other. Thus, when two inductors are placed near each other, the flux interaction can be used to force the synchronization of two or more LC tank circuits.
Yet another aspect of this invention is to adjust the frequency of an LC tank circuit using several different techniques. A Finite State Machine, a passive flux linkage circuit and a mechanical flux linkage circuits are described that can be used to adjust the frequency of a system of oscillators.
FIG. 12 b depicts the simulated waveforms of the balanced three-phase closed loop LC tank circuit in accordance with the present invention
The LC (inductor-capacitor) tank circuit has been a fundamental building block in many electrical system designs. This circuit is used in wireless, digital, and mixed-signal designs. The basic building elements of the LC tank circuit consist of at least one inductor and and at least one capacitor.
Finally, the tables listed in FIG. 1 e and FIG. 1 f displays the parameters of several inductors that were determined using the “Mohan” reference. The first column lists the values of the self-inductances Lequ. The second column indicates N which indicates the number of turns of the coil. The next column gives dout that is the outside dimension of the coil. The remaining dimensions of din and W are also indicated. Note that one difference between FIG. 1 e and FIG. 1 f is that the width of the conductive trace used to form the coil is 20 μm and 10 μm, respectively. The number of squares forming the conductive trace of each inductor is indicated in the sixth column. The next column provides the parasitic resistor assuming that the sheet resistance of 0.01Ω/□ is used. Finally, the last column gives the parasitic capacitance Cox of the inductors (see FIG. 1 d). Note that this capacitance value is one half of the total parasitic value of the inductor. These inductors provide an indication of the real estate used for several one-turn inductors. In addition, several of these inductors will be simulated in different tank circuits to help describe the invention.
FIG. 2 b illustrates a second version of the Colpitts oscillator 2-5 where the regenerative circuit 2-6 of type regen-1a has two additional inputs 2-7 and 2-8. These inputs can be used to introduce other clock signals into the oscillator to control its phase generation.
FIG. 4 illustrates several CMOS circuits configured in either regen-1, regen-1a or regen-2 type regenerative circuits. Similar circuits can be designed using BJT transistors as well. In FIG. 4 a, a regen-1 type circuit 4-1 is shown; here a p-channel 4-2 serves as a current source to the rest of the circuit. The two p-channel transistor 4-3 and 4-4 are cross coupled to each other; that is, the drain of 4-3 is connected to the gate of 4-4 and the drain of 4-4 is connected to the gate of 4-3. This forms a regenerative circuit, note that the two transistors have the same conductivity type. The two n-channel transistors 4-5 and 4-6 are configured in a similar manner. The drain of 4-6 is connected to the gate of 4-5 and the drain of 4-5 is connected to the gate of 4-6. This forms a second regenerative circuit. The tank circuitry is connected to the drains of the two cross coupled transistor circuits. In addition, the tank circuitry and the cross coupled transistors share the ground and power nodes. The output signal is provided at the two output nodes 4-7 and 4-8. The negative resistance of the circuit compensates for the resistive loss in the tank circuit and allows the oscillation created in the tank circuit to be maintained.
An equivalent representation of the circuit 4-9 is provided in FIG. 4 c. This regenerative circuit 4-10 consists of two inverters connected head to tail as shown. This is also the basic building block of a ram-cell that is used to store memory in integrated circuits (IC). The outputs of this circuit 4-10 are indicated as 4-7 and 4-8. This ram-cell has three states; outputs 4-7 and 4-8 are equal, output 4-7 is a logic “1” while output 4-8 is a logic “0”, and the case where output 4-7 is a logic “0” while output 4-8 is a logic “1”. The first state given is also know as the meta-stable state, where both outputs are equal. A slight bit of noise introduced into the circuit 4-10 under the meta-stable state condition will cause the circuit 4-10 to enter one of the remaining two states.
The last two circuits are type regen-1a circuits. FIG. 4 g shows a regenerative circuit 4-15 where a p-channel 4-16 serves as a current source to the rest of the circuit. The two p-channel transistors 4-17 and 4-18 allow external signals to be introduced into the regenerative circuit. A regenerative circuit consists of the two cross-coupled n-channels 4-21 and 4-22. The negative resistance of this circuit is provided to the LC tank circuit using the two outputs 4-19 and 4-20. The negative resistance of the circuit compensates for the resistive loss in the tank circuit and allows the oscillation created in the tank circuit to continue.
FIG. 4 h illustrates the second version 4-23 of the regen-1a circuit. This circuit is similar to the circuit in FIG. 4 g, except that the p-channel current source has been eliminated.
FIG. 5 b shows a LC tank circuit 5-6 where the regenerative circuit type regen-1a is used. Inputs 5-7 and 5-8 can be applied to the gates of the two p-channel transistors. This circuit generates two outputs 5-9 and 5-10. Similar to the previous circuit, this circuit contains both the constant capacitive load 5-12 and the adjustable capacitor 5-11.
FIG. 6 a shows the basic LC tank circuit 6-1 used to describe several different LC tank circuits, hereafter called the “basic LC tank circuit.” This circuit has two outputs 6-2 and 6-3. The circuit also contains (but not shown) the capacitor network of the adjustable and constant variety as mentioned in FIG. 5. FIG. 6 b illustrates an open series connection 6-5 of two basic LC tank circuits. This circuit 6-5 contains three outputs; 6-2, 6-3 and 6-4. FIG. 6 c depicts a closed loop connection 6-7 of the circuit illustrated in FIG. 6 b. Note that output 6-4 collapses and becomes the output 6-2.
FIG. 7 a illustrates three basic LC tank circuits configured in an open series connection 7-1. This circuit contains four outputs; 7-2, 7-3, 7-4 and 7-5. FIG. 7 b presents the simulation results of these four waveforms. Because of the open connection, every other output is similar. For example, waveforms 7-3 and 7-5 overlap each other, while waveforms 7-2 and 7-4 are generated 180� out of phase when compared to waveforms 7-3 and 7-5.
Note that when the closed loop contains an even number of LC tank circuits, the phase separation does not satisfy equation (4). This can be seen by comparing the arrows 8-8, 8-9, 8-10 and 8-11 in the circuit 8-1 against the plots of these outputs in the waveform simulation 8-12. When the time equals 19.92 nsec, the dotted line 8-6 is used to help determine the direction of the arrows in the circuit 8-1. During time 8-6, the output waveforms 8-2 and 8-4 are increasing which is indicated by the upwards arrows 8-8 and 8-10 in circuit 8-1. Similarly, the output waveforms 8-3 and 8-5 are decreasing as indicated by the downward arrows 8-9 and 8-11 in circuit 8-1. In effect, all of the arrows in circuit 8-1 are 180� out of phase with its adjacent neighbor. Note that at time 8-7, all the waveforms converge to a point 8-9. This corresponds to the case where all the transient outputs of the circuit 8-1 are equal. After the point 8-9, the arrows in the circuit 8-1 flip polarity.
FIG. 13 a illustrates two LC tank circuits 13-1 that are connected to each other. The outputs 13-2 and 13-3 of the upper LC tank circuit are cross connected to the gates of the two p-channels 13-7 and 13-8 in the lower LC tank circuit. In addition, the outputs of the lower LC tank circuit 13-4 and 13-5 are directly connected to the gates of the two p-channels 13-9 and 13-10 in the upper LC tank circuit. This circuit 13-1 generates a quadrature signal. Note that the circuit 13-1 uses the two sets of the regen-1a regenerative circuit.
A block diagram 14-1 that generates six balanced signals 14-2, 14-3, 14-4, 14-5, 14-6, and 14-7 are illustrated in FIG. 14 a. The circuit 14-1 was simulated and the waveforms are presented in FIG. 14 b. The three sets of balanced signals are; the 0� and 180� signals 14-4 and 14-5, the 60� and 240� signals 14-7 and 14-6, and the 120� and 300� signals 14-2 and 14-3.
1 L 1 + … + 1 L n = 1 L equ ( 6 ) or the equivalent inductance is determined as 0.633 nH by using equation (6). This value of inductance approaches that of the inductance given in the first row. As mentioned earlier, the encompassed area of a single 1.266 nH inductor increased the area by a factor of 4� compared to the 0.565 nH inductor. Furthermore, since there are two of these encompassed areas enclosed by the inductors 19-2 and 19-5. The overall encompassed area for this second basic cell using only one regenerative circuit is increased by 8� when compared to the prior basic cell consisting of a regenerative circuit connected to a single 0.565 nH inductor. Also note that the equivalent parasitic resistance of parallel-connected inductors is decreased as given by;
1 R 1 + … + 1 R n = 1 R equ ( 7 ) so the resistance presented to the regenerative circuit is 0.467Ω as determined by using equation (7). This is very similar to the parasitic resistance value of the first inductor in the first row. Thus, the parallel combination of larger inductances or coils in an IC offers benefits of increasing the encompassed area. In addition, the frequency of operation and the value of parasitic resistance can maintain their initial values. Furthermore, only one regenerative circuit is necessary to drive two inductors that offers the potential benefit of decreasing the power dissipation since one regenerative circuit has been eliminated. These are all advantages of the second aspect of his invention. Although the parasitic capacitance increases by a factor of two, the power dissipation of driving this capacitance is adiabatic (because of the tank circuit) and is lower than the power dissipation arrived at by using equation (1).
Each basic cell contains a regenerative circuit and as indicated earlier has a balanced output that drives a capacitive load consisting of parasitic and adjustable components. In this simulation, each output had an additional capacitive load of 0.5 pF connected to each output; part of which accounts for the two parallel-connected inductors that have a capacitive load of 0.35 pF. In addition, the gate and drain capacitance of the transistors within the regenerative circuit adds another 0.6 pF. The capacitance load that each output of the basic cell drives is approximately is 1.1 pF while the total capacitance each cell drives is 2.2 pF. However, since the transistor parasitics will not change significantly in a given technology, their contribution of “drivable” capacitive load will be subtracted from the 2.2 pF figure leaving about 1 pF of “drivable” load. The capacitive load of the inductor was not subtracted from this figure because it is possible that the inductor can be fabricated off-chip (MCM, for example) and may have a lower capacitance. Thus, the total “drivable” capacitance is 1 pF and the total “drivable” capacitance of the layout 21-1 would be 8 pF. The corresponding capacitive value for the μprocessor is 2048 pF as indicated in the table.
A feedback continuous flux linkage path is illustrated with FIG. 23 b which shows an additional cell added to the top metal layer. The fourth cell has its regenerative circuits in the region 23-9. Thus, 23-9 electrically drives the inductors 23-11 and 23-13. The inductor 23-11 is over inductor 23-10 driven by the regenerative circuit 23-8, while the inductor 23-13 is over the inductor 23-12 driven by the regenerative circuit 23-4. A feedback path would occur starting from the regenerative circuit 23-3, sending the electronic signal to the inductor 23-6, having a flux linkage path to the inductor 23-5 below it, sending the electronic signal to the regenerative circuit 23-4, passed electrically to the inductor 23-12, having a flux linkage path to the inductor 23-13 above it, sent electrically to the regenerative circuit 23-9, passed electrically to inductor 23-11, having a flux linkage path to the inductor 23-10 below it, sent electronically to the regenerative circuit 23-8, passed electrically to the inductor 23-2, having a flux linkage to the inductor 23-7 above it, and finally having the electrical signal ending at the regenerative circuit 23-3.
FIG. 26 d provides a table 26-6 indicating the simulation conditions when the circuit in FIG. 26 a representing the physical layout 26-1 was simulated in SPICE. The frequency of operation of the layout was targeted at 10 GHz and is an expected frequency of future VLSI and μprocessor chips. The process was a 0.13 μm CMOS technology having a core VDD of 1.2V. The transistor sizes in the regenerative circuit had a p-channel width of 20 μm and an n-channel width of 10 μm. Each basic cell generates 4 sets of balanced outputs and contains 4 regenerative circuits, one for each set of balanced outputs. The inductor was selected from the first row of the table given in FIG. 1 f. The inductance of each individual coil was 0.633 nH and had a parasitic resistance of 0.868Ω+0.24Ω for the extension leg providing a total of 1.108Ω, where a sheet resistance of 0.01Ω/□ was used for the coils. The parasitic capacitance Cox of the coil and extension leg is 0.225 pF. The k coupling coefficient value was set at 0.9.
Each basic cell contains four regenerative circuits and as indicated earlier has a balanced output that drives a capacitive load consisting of parasitic and adjustable components. In this simulation, each output had an additional capacitive load of 0.5 pF connected to each output; part of which accounts for the inductor that have a capacitive load of 0.2225 pF. Thus, the total “drivable” capacitance (discussed earlier) in each cell is 4 pF and the total “drivable” capacitance of the layout 26-1 would be 64 pF. The corresponding capacitive value for the μprocessor is 4096 pF as indicated in the table.
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Solid State, vol. 40, Issue 1, Jan. 2005, pp. 102-109.2Galton et al., Clock Distribution Using Coupled Oscillators, Proc. of the 1996 IEEE Inter. Symp. on Cir. and Systems, May 12-15, vol. 3, pp. 217-220.3Hall et al., Clock Distribution Using Cooperative Ring Oscillators, Proc. IEEE 17th Conf. Advanced Research in VLSI, 1997, pp. 62-75.4Mohan et al., Simple Accurate Expressions for Planar Sprial Inductances, IEEE J. of Solid-state Circurits, vol. 34, No. 10, Oct. 1999, pp. 1419-1424.5Rofougaran, et al, "A 900MHz CMOS LC-Oscillator with Quadrature Outputs", SP24.6, 1996 IEEE International Solid State Conference, pp. 392-393.6Wood et al., Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology, IEEE J. of Solid-state Circuits, vol. 36, No. 11, Nov. 2001, pp. 1654-1665.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7847650 *Dec 7, 2010Pentomics, IncLow phase-noise oscillatorUS8068004Feb 3, 2010Nov 29, 2011Xilinx, Inc.Embedded inductorUS8212155 *Jun 26, 2007Jul 3, 2012Wright Peter VIntegrated passive deviceUS8410858Apr 2, 2013Analog Devices, Inc.Electronic circuitryUS8487710Dec 12, 2011Jul 16, 2013Analog Devices, Inc.RTWO-based pulse width modulatorUS8581668Dec 20, 2011Nov 12, 2013Analog Devices, Inc.Oscillator regeneration deviceUS8610474Oct 9, 2010Dec 17, 2013Rambus Inc.Signal distribution networks and related methodsUS8633774Dec 5, 2011Jan 21, 2014Analog Devices, Inc.Electronic pulse generator and oscillatorUS8669818Apr 30, 2012Mar 11, 2014Analog Devices, Inc.Wave reversing system and method for a rotary traveling wave oscillatorUS8742857Dec 31, 2011Jun 3, 2014Analog Devices, Inc.Inductance enhanced rotary traveling wave oscillator circuit and methodUS8823133Mar 29, 2011Sep 2, 2014Xilinx, Inc.Interposer having an inductorUS8913978Apr 9, 2008Dec 16, 2014Analog Devices, Inc.RTWO-based down converterUS8947168Mar 19, 2013Feb 3, 2015Analog Devices, Inc.Electronic circuitryUS9065453Nov 25, 2013Jun 23, 2015Silicon Image, Inc.Signal distribution networks and related methodsUS9160346Feb 7, 2012Oct 13, 2015Rambus Inc.Area and power efficient clock generationUS9275784Aug 29, 2012Mar 1, 2016Rambus Inc.Electronic circuits using coupled multi-inductorsUS9330823Dec 19, 2011May 3, 2016Xilinx, Inc.Integrated circuit structure with inductor in silicon interposerUS9337138Mar 9, 2012May 10, 2016Xilinx, Inc.Capacitors within an interposer coupled to supply and ground planes of a substrateUS9368271 *Apr 22, 2015Jun 14, 2016Industrial Technology Research InstituteThree-dimension symmetrical vertical transformerUS20080143446 *Dec 17, 2007Jun 19, 2008Chih-Wei YaoLow Phase-Noise OscillatorUS20090045850 *Apr 9, 2008Feb 19, 2009Multigig, Inc.Rtwo-based down converterUS20160012958 *Apr 22, 2015Jan 14, 2016Industrial Technology Research InstituteThree-dimension symmetrical vertical transformer* Cited by examinerClassifications U.S. Classification331/117.0FE, 331/55, 331/181, 331/167International ClassificationH03B5/12Cooperative ClassificationH01L2224/16145, H03B5/1243, H03B5/1228, H03B5/1212, G06F1/10, H03B2200/0076European ClassificationG06F1/10Legal EventsDateCodeEventDescriptionApr 29, 2010ASAssignmentOwner name: LCTANK LLC,NEW JERSEYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GABARA, THADDEUS JOHN;REEL/FRAME:024311/0586Effective date: 20100429Owner name: LCTANK LLC, NEW JERSEYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GABARA, THADDEUS JOHN;REEL/FRAME:024311/0586Effective date: 20100429Nov 3, 2010ASAssignmentOwner name: LC TANK LLC, NEW JERSEYFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GABARA, THADDEUS JOHN;REEL/FRAME:025238/0243Effective date: 20101103Mar 11, 2011ASAssignmentOwner name: INTELLECTUAL VENTURES FUND 70 LLC, NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LC TANK LLC;REEL/FRAME:025941/0287Effective date: 20110104Mar 25, 2011ASAssignmentOwner name: INTELLECTUAL VENTURES FUND 70 LLC, NEVADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LC TANK LLC;REEL/FRAME:026022/0017Effective date: 20110104Aug 28, 2012FPAYFee paymentYear of fee payment: 4Jan 29, 2016ASAssignmentOwner name: INTELLECTUAL VENTURES HOLDING 81 LLC, NEVADAFree format text: MERGER;ASSIGNOR:INTELLECTUAL VENTURES FUND 70 LLC;REEL/FRAME:037625/0103Effective date: 20150827RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

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text: today. senators reid and mcconnell are discussing a potential agreement where we can get a bipartisan bill out of the senate over into the house and done in a timely fashion so that we met the december 31st deadline. given how things have been working in this town we have to actually wait and see until it actually happens. the one thing that the american people should not have to wait and see is some sort of action. so if we don't see an agreement between the two leaders in the senate, i expect a bill to go on the floor. and i have asked senator reid to do. this put a bill on the floor that makes sure that taxes on middle class families don't go up, that unemployment insurance is still available for 2 million people, and that lays the groundwork then for additional deficit reduction and economic growth steps that we can take in the new year. >> joining us now from capitol hill. south dakota republican senator john thune, a member of the budget committee. so, senator, what do you make of the president's plan? >> i'm just glad the president is engaged. you can't do big things in washing The O Reilly Factor

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Our Lady of Lourdes Shrine, Villianur - Wikipedia
11°54′41″N 79°45′38″E / 11.911262°N 79.760664°E / 11.911262; 79.760664Coordinates: 11°54′41″N 79°45′38″E / 11.911262°N 79.760664°E / 11.911262; 79.760664
www.villianurshrine.com
8 April 1877 (1877-04-08)
8, May 1886 - The statue was crowned in the name of Pope Leo XIII, and permanent plenary indulgence attached, declared as a Shrine.
Parish church and Marian shrine
Fr. Tarbes, M.E.P
Pondicherry and Cuddalore
Rev. Mgr. Antony Anandarayar
Fr. S. Richard
Our Lady of Lourdes Shrine is a famous Marian shrine located in Villianur Town, Puducherry. This Roman Catholic shrine is devoted to Our Lady of Lourdes.
1 History of the Shrine According to Catholic Sources
1.1 Miraculous Statue
1.2 Sacred Pond
1.4 The Stations of the Cross
1.5 The 125th Anniversary Celebrations
1.6 A new Church
2 Feasts and Other Celebrations
2.1 Annual Feast of the Shrine
2.2 The Holy Water from Lourdes
2.3 Pilgrimage on foot
History of the Shrine According to Catholic Sources[edit]
A rare old picture of the shrine
In 1867, the MEP missionaries in Puducherry wished to build a Chapel at Villianur which is 13 kilometers from Pondicherry, on the road to Villupuram. Hence they bought a piece of land at Villianur and Rev.Fr.Gou, then procurator of the Puducherry mission after a long negotiation with the Hindu temple authorities of Thirukameswarer Gogilambigai Temple started to build a Chapel at Kanuvapet on the outskirts of Villianur. It is said that the building of the church was sponsored by the thanksgiving offering of Dr.Lephine's family for the miraculous cure of his daughter.
It took 10 years to complete the Chapel. And Rev.Fr.Tarbes a cousin brother of St. Bernadette, the visionary of Lourdes, was appointed as the Parish Priest of Villianur mission. Since he had a direct report of the apparitions of Our Lady of Lourdes, this chapel is the first in the world to be named after Our Lady of Lourdes outside Lourdes, France.
Miraculous Statue[edit]
Central Altar with the Miraculous Statue
A parishioner of Our Lady of Lourdes commissioned a six foot tall statue for the site, which arrived in Puducherry on 4 April 1877. The box containing the statue was dropped three times on the way to the Cathedral, but arrived intact, and was sent on to Villianur.
The statue was claimed to be associated with a number of miracles in the late nineteenth century. In 1885 the archbishop Laouënan went to Rome and provided a report of the alleged miracles that took place at the shrine to Pope Leo XIII. The archbishop received permission on 21 February 1886 to declare the site an official Shrine of Our Lady of Lourdes, and to canonically crown the statue.
On the archbishop's return from Rome on 8 May 1886, a pontifical high mass was held, with the celebration being witnessed by around 40,000 people. At the mass, the archbishop crowned the statue in the name of the pope, and declared the church as the Shrine of Our Lady of Lourdes, Villianur, attaching permanent plenary indulgences to the shrine.
There was a natural pond in front of the chapel. it was once used as the water reservoir for the irrigation of the lands around and water came from the big Ousteri Lake which is 10 km away from here. And this pond was constructed by Fr. Lesbond, the Parish Priest, with donations from Zigon organized by Mr. Lesage. Mr. Larocgue from the people in Zigon got a statue from Lourdes and in 1924 and a solemn ceremony took place to install the statue in the middle of the sacred pond after the due consecration of the statue and the pond.
It is believed by the people here that the pond water is miracles and has the ability to cure the sick and bring good fortune. This is the only Catholic church in Asia having a sacred pond in front of the church.
19 years after Lourdes apparitions, the first church and grotto for Our Lady of Lourdes was constructed in 1877. The centenary celebrations was celebrated on 10 September 1977. As a remembrance of the centenary celebrations, Rev.Fr.Duissen built a big grotto in the garden of the church, which was consecrated by bishop Venmani S. Selvanather on 10 October 1978. The grotto which was inside the church was modified according as per the instruction of the Second Vatican Council.
The Stations of the Cross[edit]
In 2009, The Stations of the Cross were constructed around the 'Sacred Pond'.
The 125th Anniversary Celebrations[edit]
In 08, October 2011, on the 125th anniversary of the crowning of the statue by the Pope, Archbishop Rev. Mgr. Antony Anandarayar crowned the Statue again with a diamond crown.
A new Church[edit]
As the existing Church could not accommodate the growing number of pilgrims, a new Church is planned with the approval of Archbishop Most. Rev.Dr.Antony Anandarayar. It is expected to be finished by 2014-2015. On 10 September 2011, Rev. Fr. A. Arulanandam, the Vicar General of Archdiocese blessed and officially commenced the construction work for the church. Rev. Fr. C. Joseph Arumaiselvam, the procurator and many other priests were present at the event.
Feasts and Other Celebrations[edit]
Annual Feast of the Shrine[edit]
Annual feast of Our Lady of Lourdes shrine commence with the nine days of Novena and flag hoisting on the 6th day after Easter Sunday. The car procession is done during these days. The feast day is on the 15th day after Easter. This is a Puducherry state Christian festival.
The Holy Water from Lourdes[edit]
Every first Saturday in the month of August, The Holy Water from Lourdes Church, France is poured into the 'Sacred Pond' at Villianur Shrine. This event is attended by thousands of devotees every year.
Pilgrimage on foot[edit]
As a sign of gratitude to Our Lady, for saving the city from a cyclone, the first pilgrimage on foot took place on 10 October 1977 from Pondicherry and this tradition is still continued on the second Saturday in the month of October. It starts from Immaculate Conception Cathedral, Pondicherry and ends in the shrine covering approximately 12 km.
Church flagpole, renovated in 2014
Benediction sermon by Card. Oswald Gracias
CatholicChurches.in Directory
http://www.pondicherryarchdiocese.org/PARKEDDOMAINS/villianur.org/
Wikimedia Commons has media related to Our Lady of Lourdes Shrine, Villianur.
Retrieved from "https://en.wikipedia.org/w/index.php?title=Our_Lady_of_Lourdes_Shrine,_Villianur&oldid=714300574"	Categories: Roman Catholic churches in PuducherryMarian shrinesRoman Catholic churches completed in 1877Archdiocese of Pondicherry and CuddaloreHidden categories: Use Indian English from January 2015All Wikipedia articles written in Indian EnglishUse dmy dates from January 2015Coordinates on WikidataCommons category with local link same as on Wikidata	Navigation menu
Español	Edit links	This page was last modified on 8 April 2016, at 21:59.

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text:
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Patent US20090007265 - Defending Against Denial Of Service Attacks - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn various embodiments, a server may be provided. The server may respond to a request for a service, from a processing device, with a challenge. The challenge may include a partial key for a memory-intensive operation, a number of iterations of the memory-intensive operation to perform, and a result...http://www.google.com/patents/US20090007265?utm_source=gb-gplus-sharePatent US20090007265 - Defending Against Denial Of Service AttacksAdvanced Patent SearchPublication numberUS20090007265 A1Publication typeApplicationApplication numberUS 11/771,034Publication dateJan 1, 2009Filing dateJun 29, 2007Priority dateJun 29, 2007Also published asUS7937586Publication number11771034, 771034, US 2009/0007265 A1, US 2009/007265 A1, US 20090007265 A1, US 20090007265A1, US 2009007265 A1, US 2009007265A1, US-A1-20090007265, US-A1-2009007265, US2009/0007265A1, US2009/007265A1, US20090007265 A1, US20090007265A1, US2009007265 A1, US2009007265A1InventorsDouglas Robert de la TORRE, Aidan Thomas Joseph HUGHES, Josh BenalohOriginal AssigneeMicrosoft CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (3), Classifications (10), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetDefending Against Denial Of Service AttacksUS 20090007265 A1Abstract In various embodiments, a server may be provided. The server may respond to a request for a service, from a processing device, with a challenge. The challenge may include a partial key for a memory-intensive operation, a number of iterations of the memory-intensive operation to perform, and a result of performing the number of iterations of the memory-intensive operation. Upon receiving the challenge, the processing device may choose a complete key consistent with the partial key and may produce a proposed result by performing the memory-intensive operation for the number of iterations. When the proposed result matches the result included in the challenge, the processing device may send a challenge answer, including the chosen complete key, to the server. Upon receiving a correct challenge answer from the processing device, the server may access the requested service and may return a result of the access to the processing device.
1. A machine-implemented method for defending against a denial of service attack, the method comprising:
receiving a request from a client for access to a web service; responding to the client with a challenge including a partial key for a memory intensive operation to be performed by the client; receiving a response to the challenge from the client; determining whether the response to the challenge includes a correct challenge answer; and returning to the client a result of accessing the web service when the response to the challenge is determined to include the correct challenge answer. 2. The machine-implemented method of claim 1, wherein the returning to the client a result of accessing the web service is performed only when the response to the challenge is determined to include the correct challenge answer.
writing values to a block of memory; and using a stream cipher operation over the block of memory to generate a challenge answer for the response to the challenge. 4. The machine-implemented method of claim 1, further comprising:
determining, after the receiving of the request from the client, an amount of the partial key to reveal to the client when responding to the client with the challenge, the amount of the partial key being based on a determined level of busyness, wherein: the amount of the partial key to be revealed to the client is smaller when the determined level of busyness is high and the amount of the partial key to be revealed to the client is larger when the determined level of busyness is low. 5. The machine-implemented method of claim 1, wherein:
the responding to the client with a challenge further comprises including with the challenge a digital signature calculated over the challenge, and the machine-implemented method further comprises:
the responding to the client with a challenge further comprises including a timestamp with the challenge, and the timestamp is included in the response to the challenge, the machine-implemented method further comprises:
the timestamp is included in the response to the challenge, and
at least one processor; and a memory connected to the at least one processor, the memory further comprising: instructions for creating and sending a challenge to a client in response to receiving a request from the client for access to the service, the challenge including a partial key for a stream cipher operation, a specified number of iterations with respect to the stream cipher operation, and a result of performing the stream cipher operation using a complete key corresponding to the partial key for the specified number of iterations of the stream cipher operation, instructions for determining whether a challenge answer from the client, responsive to sending the challenge, includes the complete key, and instructions for permitting the access to the service and returning a result of the access to the client when the challenge answer from the client includes the complete key. 9. The at least one server of claim 8, wherein the memory further comprises:
instructions for determining a level of busyness of a respective one of the at least one server; and instructions for determining a number of bits of the complete key to hide when forming the partial key based, at least in part, on the level of busyness of the respective one of the at least one server. 10. The at least one server of claim 8, wherein the memory further comprises:
instructions for determining a level of busyness of a respective one of the at least one server; and instructions for determining a number of bits of the complete key to hide when forming the partial key based, at least in part, on the level of busyness of the respective one of the at least one server, wherein the level of busyness is based on at least one of a utilization amount of the at least one processor or a number of items in at least one queue. 11. The at least one server of claim 8, wherein the memory further comprises:
instructions for determining a level of busyness of a respective one of the at least one server; and instructions for creating and sending a second challenge to the client in response to receiving the client answer when the determined level of busyness of the respective one of the at least one server is greater than a predetermined level. 12. The at least one server of claim 8, wherein the memory further comprises:
instructions for determining whether a challenge answer from the client is received within a predetermined time window measured from a time the challenge is created, wherein the instructions for permitting the access to the service and returning a result of the access to the client when the challenge answer from the client includes the complete key further only permit access to the service when the challenge answer is received within the predetermined time window. 13. The at least one server of claim 8, wherein the instructions for creating and sending a challenge to the client in response to receiving a request from the client for access to the service further comprise:
instructions for calculating a valid digital signature over the challenge and including the valid digital signature with the challenge, instructions for discarding a received challenge answer from the client when the received challenge answer fails to include the valid digital signature, instructions for determining whether the received challenge answer is already in a cache of recently received challenge answers, and instructions for discarding the received challenge answer when the received challenge answer is already in the cache of recently received challenge answers. 14. The at least one server of claim 8, wherein the instructions for creating and sending a challenge to the client in response to receiving a request from the client for access to the service further comprise:
instructions for including a timestamp with the challenge, instructions for calculating a valid digital signature over the challenge and the timestamp and including the valid digital signature with the challenge, and instructions for discarding a received challenge answer from the client when the received challenge answer fails to include the valid digital signature or when the challenge answer is received outside of a predetermined time window measured from a time as indicated in a copy of the timestamp included with the challenge answer. 15. A processing device comprising:
at least one processor; and a memory connected to the at least one processor, the memory further comprising: instructions for receiving a challenge in response to sending a request for accessing a service, the challenge including a partial key for a memory intensive operation and a result of the memory intensive operation, instructions for choosing a first complete key based on the partial key, instructions for performing the memory intensive operation, using the first complete key, to produce a proposed result, instructions for comparing the result of the memory intensive operation with the proposed result to determine whether the proposed result equals the result of the memory intensive operation, and instructions for preparing and transmitting a challenge answer including the first complete key when the proposed result is determined to equal the result of the memory intensive operation. 16. The processing device of claim 15, wherein the memory further comprises:
instructions for choosing a next complete key based on the partial key when the proposed result is not equal to the result of the memory intensive operation, and instructions for performing the memory intensive operation, using a next complete key, to produce a next proposed result when the proposed result is determined to not equal the result of the memory intensive operation. 17. The processing device of claim 15, wherein:
the challenge further includes a timestamp and a hashed message authentication code calculated over the timestamp, and the instructions for preparing and transmitting a challenge answer further include instructions for including the timestamp and the hashed message authentication code in the challenge answer. 18. The processing device of claim 15, wherein the memory intensive operation includes a stream cipher operation.
the memory intensive operation includes a stream cipher operation, and the challenge includes a number corresponding to a specific number of operations of the stream cipher operation, and the memory further comprises:
instructions for performing the stream cipher operation for the specific number of operations to produce the proposed result.
20. The processing device of claim 15, further comprising:
instructions for receiving a result of performing the service in response to preparing and transmitting a challenge answer. Description
BACKGROUND Software vendors may deploy services on servers connected to a network, such as, for example, the Internet, or other networks. When the services are provided on the Internet, the services may be called web services. Third parties may use the deployed services by accessing the servers. If a server, which provides a particular service, is not operational, then the particular service is not available and a software vendor who provides the particular service may appear to be unreliable.
Services, such as, for example, publicly-provided web services, may be attacked by hackers. One type of attack that hackers may employ includes the use of botnets (multiple processing device working in tandem, typically, with a malicious purpose) to overload and effectively, disable a server. Such an attack is called a Denial of Service (DoS) attack.
Overview In embodiments consistent with the subject matter of this disclosure, a network-connected processing device, such as, for example, a client device, may send a request to access a service provided via the network. A processing device, such as, for example, a server, which provides the service, may receive the request and may respond by creating and transmitting a challenge to the client device. In some embodiments, the challenge may include a partial key for a memory-intensive operation, a number of iterations to perform, and a result of performing the memory-intensive operation for the number of iterations using a complete key corresponding to the partial key. In some embodiments, a number of bits of the partial key not provided may be determined based on a level of busyness of the server. The level of busyness may be determined based on processor utilization of the server and/or a length of a queue, such as, for example, a queue of requests for accessing the service. In other embodiments, the level of busyness may be determined based on one or more other factors.
Exemplary Operating Environment FIG. 1 illustrates an exemplary operating environment 100 for embodiments consistent with the subject matter of this disclosure. Operating environment 100 may include a network 102, a processing device 104, and one or more servers 106.
Exemplary Processing Device FIG. 2 is a functional block diagram that illustrates an exemplary processing device 200, which may be used to implement embodiments of processing device 104 and/or server 106 consistent with the subject matter of this disclosure.
Exemplary Server Processes FIG. 3 is a flowchart illustrating an exemplary process, which may be performed in embodiments of server 106 consistent with the subject matter of this disclosure. The process may begin with server 106 receiving a request for access to a service, such as, for example, a web service, or other service, from processing device 104, which may function as a client device (act 302). Next, server 106 may create a challenge in response to receiving the request for access to the service (act 304).
Exemplary Client Process FIG. 7 is a flowchart illustrating an exemplary process, which may be performed by processing device 104 acting as a client device. The process may begin with processing device 104 sending to server 106 a request to access a service (act 702). As a result of sending the request to access a service, processing device 104 may receive from server 106 a challenge, which may include a partial key for a memory-intensive operation, such as, for example, a stream cipher operation or another operation, a value for a number of iterations, and a provided result of performing the memory-intensive operation using a complete key, corresponding to the partial key, for the number of iterations (act 704).
Processing device 104 may perform the memory-intensive operation using the chosen complete key for the number of iterations to produce a proposed result (act 708). In some embodiments, processing device 104 may perform a stream cipher operation using the chosen key. Processing device 104 may then determine whether the proposed result of the memory-intensive operation matches the provided result included in the received challenge (act 710). If the proposed result does not match the provided result, then processing device 104 may choose a next complete key based on the partial key (act 712). As an example, suppose the partial key is 1XX7AF in a hexadecimal representation, where �X� represents hidden bits. Corresponding complete keys may include, for example, 1007AF, 1017AF, 1027AF, 1037AF, . . . , 1FD7AF, 1FE7AF, and 1FF7AF. Processing device 104 may then repeat acts 708-712.
Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8334755 *Nov 24, 2009Dec 18, 2012Electronics And Telecommunications Research InstituteMethod for recognizing radio frequency identification tag reader and apparatus thereofUS8533474 *Feb 27, 2008Sep 10, 2013Red Hat, Inc.Generating session keysUS20100141402 *Nov 24, 2009Jun 10, 2010Electronics And Telecommunications Research InstituteMethod for recognizing radio frequency identification tag reader and apparatus thereof* Cited by examinerClassifications U.S. Classification726/22International ClassificationG08B23/00Cooperative ClassificationG06F2221/2129, H04L63/1458, H04L2463/141, H04L63/12, G06F21/445European ClassificationH04L63/14D2, H04L63/12, G06F21/44ALegal EventsDateCodeEventDescriptionJul 19, 2011CCCertificate of correctionSep 21, 2007ASAssignmentOwner name: MICROSOFT CORPORATION, WASHINGTONFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TORRE, DOUGLAS ROBERT DE LA;HUGHES, AIDAN THOMAS JOSEPH;BENALOH, JOSH;REEL/FRAME:019861/0801;SIGNING DATES FROM 20070817 TO 20070828Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TORRE, DOUGLAS ROBERT DE LA;HUGHES, AIDAN THOMAS JOSEPH;BENALOH, JOSH;SIGNING DATES FROM 20070817 TO 20070828;REEL/FRAME:019861/0801RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


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Beast and man in India ; a popular sketch of Indian animals in their relations with the people by John Lockwood Kipling | 2940015298932 | NOOK Book (eBook) | Barnes & Noble
A keeper. Illustrations are small, but worthy. Scan is OK. Visit Your Local StoreFind Author and Storytime Events Find a Store > Gift CardsAlways the Perfect Gift Shop Now > Barnes & Noble CaféRelax and Refuel Visit BN Café > B&N MembershipDon't Miss Out on Savings Learn More > B&N ServicesAdvertisePublisher & Author GuidelinesSelf-Publish with NOOK PressBulk Order DiscountsB&N MembershipB&N MasterCardB&N Kids' ClubB&N EducatorsB&N BookfairsCareers at B&NShipping & DeliveryAbout Free ShippingAbout ShippingShipping RatesNOOKNOOK Tablets & eReaders NOOK Mobile Apps Special OffersNOOK on FacebookNOOK on TwitterQuick HelpCustomer ServiceOrder StatusEasy ReturnsProduct RecallsAbout UsAbout B&NInvestor RelationsBarnes & Noble, Inc.Store & Events Author Events, FREE Wi-Fi, and more Store Locator Be in the KnowSign up for savings, news, updates Email FacebookTwitterPinterestTerms of Use Copyright & TrademarkPrivacy PolicySitemapAccessibility© 1997-2016 Barnes & Noble Booksellers, Inc. 122 Fifth Avenue, New York, NY 10011.

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Amazon.com: Paralyzed Without Fear: A Family of Their Own eBook: Jacqueline Dunkle, Erik Fugunt, Jennifer Fugunt: Kindle Store
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Patent US6549111 - Inductive element - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA description is given of a method of manufacturing an inductive element for SMD applications. This method comprises the following steps: a) providing a number of predominantly parallel electroconductive wires in the mould of an injection-molding device, b) circumferentially providing a part of the wires...http://www.google.com/patents/US6549111?utm_source=gb-gplus-sharePatent US6549111 - Inductive elementAdvanced Patent SearchPublication numberUS6549111 B1Publication typeGrantApplication numberUS 09/858,725Publication dateApr 15, 2003Filing dateMay 16, 2001Priority dateMay 8, 1998Fee statusLapsedAlso published asDE69911839D1, US6259345Publication number09858725, 858725, US 6549111 B1, US 6549111B1, US-B1-6549111, US6549111 B1, US6549111B1InventorsMartinus J. M. de Graaf, Eelco G. VisserOriginal AssigneeKoninklijke Philips Electronics N.V.Export CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (26), Classifications (16), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetInductive elementUS 6549111 B1Abstract A description is given of a method of manufacturing an inductive element for SMD applications. This method comprises the following steps: a) providing a number of predominantly parallel electroconductive wires in the mould of an injection-molding device, b) circumferentially providing a part of the wires with a synthetic resin by injection molding, in such a manner that the ends of the wires remain free, c) providing an envelope of a soft-magnetic material around the circumferentially injection molded part of the wires, and d) reshaping the ends of the wires. In accordance with the invention, the method is characterized in that the parts of the wires to be circumferentially injection molded are fixed inside the mold during the injection molding process. It has been found that inductive elements of the type manufactured in accordance with the inventive method generate, in operation, optimally homogeneous magnetic fields. Also the risk of electric short-circuits proves to be small.
What is claimed is: 1. An inductive element comprising a number of predominantly parallel electroconductive wires which are partly circumferentially provided with a synthetic resin by injection moulding, said injection-moulded part of said wires being accommodated in a block-shaped, undivided core of a soft-magnetic material.
2. The inductive element of claim 1, wherein said core is predominantly composed of a soft-magnetic ferrite material.
This application is a continuation of Ser. No. 09/307,158 filed May 7, 1999 now U.S. Pat. No. 6,259,345.
The invention relates to a method of manufacturing an inductive element for SMD applications, which method includes the following steps:
BACKGROUND OF THE INVENTION It has been found that in practice the inductive elements manufactured in accordance with the above-mentioned method give rise to problems. For example, in the case of mass-produced inductive elements, the electrical and magnetic properties of the elements vary to an undesirable extent. It has been found that the magnetic fields, which are generated during operation of these elements, are not optimally homogeneous. It has also been found that sometimes an electric short-circuit occurs in these elements. These drawbacks increase as the thickness or diameter of the wires is chosen to be smaller.
SUMMARY OF THE INVENTION It is an object of the invention to obviate the above-mentioned drawbacks. The invention more particularly aims at providing a method which enables inductive elements having improved electrical and magnetic properties to be manufactured. The invention also aims at providing an improved inductive element.
These and other objects of the invention are achieved by a method of the type mentioned in the opening paragraph, which is characterized in that the parts of the wires to be circumferentially injection moulded are secured in the mould during said injection moulding operation.
The invention is based on the experimentally gained insight that deformation of the wire during the injection-moulding process is responsible for said drawbacks. This deformation is caused by the force with which the synthetic resin is squirted into the mould. Said undesirable deformation is substantially reduced, and sometimes even precluded, by securing the wires in the mould during the injection-moulding process.
A preferred embodiment of the invention is characterized in that the injection-moulding device is provided with means for securing the wires in the mould. It is noted that, in principle it is also possible to connect the wires to each other, for example by means of a piece of adhesive tape. However, this possibility requires an additional process step, namely the provision of the adhesive tape. In addition, it has been found that this solution is less satisfactory when synthetic resins are used which are squirted into the mould at a high temperature.
A further preferred embodiment is characterized in that the means comprise at least one pair of elongated parts, which are provided in the mould and between which the wires are clamped. These parts may, for example, be embodied so as to be in the form of knives which, when the mould portions are closed, rest on the wires in a clamping manner. If one pair of this type of knives is used, the knives are preferably arranged in the mould in such a manner that approximately the center of the part of the wires to be circumferentially injection moulded is engaged in a clamping manner.
A more refined modification of the last-mentioned embodiment of the method is characterized in accordance with the invention in that the means comprise at least two pairs of elongated parts, which are provided with teeth between which the wires are held, which teeth are distributed over said parts in such a manner that adjoining wires are not held by the same pair of parts. As a result of this measure, the creepage distance between adjoining wires is larger than in the last-mentioned embodiment. Consequently, the risk of problems caused by a short-circuit due to moisture is reduced.
Another interesting embodiment of the method is characterized in that the wires form part of a lead frame whose transport strips are removed. The use of lead frames simplifies the positioning of the wires in the mould of the injection-moulding device. Preferably, the wires are also connected to the adjoining wire or wires at the location where the parts of the injection-moulding device rest on the wires during the injection-moulding process. This precludes injection-moulding material from being squeezed out. These connections (also referred to as �dam bars�) must be interrupted after the synthetic resin has been provided.
Another favorable embodiment of the method in accordance with the invention is characterized in that a thermoplastic synthetic resin is circumferentially provided on the wires by injection moulding. It is noted that, in principle, a thermo-curing synthetic resin may alternatively be used. However, due to the necessary, relatively long curing times of customary thermo-curing synthetic resins, they are less attractive for use in mass-production. Preferably, use is made of a thermoplastic synthetic resin based on liquid-crystalline polymers. Said polymers can be readily injection moulded and have relatively good flame-extinguishing properties.
FIG. 1 is an elevational view of an inductive element in accordance with the invention,
DETAILED DESCRIPTION OF THE PRIMARY EMBODIMENT FIG. 1 shows an elevational view of an inductive element in the form of an inductor. This inductive element comprises a block-shaped, undivided core (1) of a soft-magnetic ferrite material, which in this case consists of MnZn-ferrite. Said core 1 comprises a through-hole (2) through which ten wires (3) of tin-plated copper are passed. These wires are bent at their end portions (4) in such a manner that the inductive element can be soldered as an SMD-component onto a printed circuit board (PCB). By means of an injection-moulding process, the wires are partly circumferentially covered with an electrically insulating synthetic resin, which in this case consists of a thermoplastic synthetic resin on the basis of liquid-crystalline polymers.
The substantially parallel wires (3) are subsequently introduced into the mould of an injection-moulding device (not shown). The part of the wires to be circumferentially injection moulded is bounded by said �dam bars� (8). By virtue of the presence of these dam bars, the injection-moulding material is not extruded between the wires.
Subsequently, the �dam bars� (8) and the transport strips are removed from the lead frame. After the provision of a small amount of adhesive on one or both main surfaces of the circumferentially injection moulded synthetic resin material, an undivided, block-shaped envelope of a soft-magnetic ferrite material (MnZn-ferrite) is slid over the circumferentially injection moulded wires. Finally, the free ends of the wires are bent in such a manner that a so-called gulf-wing is formed, which renders the resultant inductive element suitable for use as an SMD-element.
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2010Volterra Semiconductor CorporationMethod for making magnetic components with N-phase coupling, and related inductor structuresUS7772955Sep 7, 2007Aug 10, 2010Volterra Semiconductor CorporationMethod for making magnetic components with N-phase coupling, and related inductor structuresUS7864016Sep 7, 2007Jan 4, 2011Volterra Semiconductor CorporationMethod for making magnetic components with N-phase coupling, and related inductor structuresUS7893806Dec 24, 2008Feb 22, 2011Volterra Semiconductor CorporationMethod for making magnetic components with N-phase coupling, and related inductor structuresUS7898379Feb 25, 2009Mar 1, 2011Volterra Semiconductor CorporationMethod for making magnetic components with N-phase coupling, and related inductor structuresUS7965165Nov 14, 2008Jun 21, 2011Volterra Semiconductor CorporationMethod for making magnetic components with M-phase coupling, and related inductor structuresUS7994888Dec 21, 2009Aug 9, 2011Volterra Semiconductor CorporationMulti-turn inductorsUS8040212Jul 22, 2009Oct 18, 2011Volterra Semiconductor CorporationLow profile inductors for high density circuit boardsUS8102233Aug 10, 2009Jan 24, 2012Volterra Semiconductor CorporationCoupled inductor with improved leakage inductance controlUS8174348May 24, 2010May 8, 2012Volterra Semiconductor CorporationTwo-phase coupled inductors which promote improved printed circuit board layoutUS8237530Jul 6, 2010Aug 7, 2012Volterra Semiconductor CorporationCoupled inductor with improved leakage inductance controlUS8299882Nov 5, 2010Oct 30, 2012Volterra Semiconductor CorporationLow profile inductors for high density circuit boardsUS8299885May 13, 2011Oct 30, 2012Volterra Semiconductor CorporationMethod for making magnetic components with M-phase coupling, and related inductor structuresUS8350658Jan 10, 2011Jan 8, 2013Volterra Semiconductor CorporationMethod for making magnetic components with N-phase coupling, and related inductor structuresUS8362867Jul 1, 2011Jan 29, 2013Volterra Semicanductor CorporationMulti-turn inductorsUS8416043Feb 9, 2011Apr 9, 2013Volterra Semiconductor CorporationPowder core material coupled inductors and associated methodsUS8638187Nov 15, 2011Jan 28, 2014Volterra Semiconductor CorporationLow profile inductors for high density circuit boardsUS8674798Jan 6, 2012Mar 18, 2014Volterra Semiconductor CorporationLow profile inductors for high density circuit boardsUS8674802Oct 7, 2011Mar 18, 2014Volterra Semiconductor CorporationMulti-turn inductorsUS8779885Mar 10, 2013Jul 15, 2014Volterra Semiconductor CorporationMethod for making magnetic components with M-phase coupling, and related inductor structuresUS8786395Mar 10, 2013Jul 22, 2014Volterra Semiconductor CorporationMethod for making magnetic components with M-phase coupling, and related inductor structuresUS8836461 *Mar 10, 2013Sep 16, 2014Volterra Semiconductor CorporationMethod for making magnetic components with M-phase coupling, and related inductor structuresUS8836463Mar 16, 2009Sep 16, 2014Volterra Semiconductor CorporationVoltage converter inductor having a nonlinear inductance valueUS20130229249 *Mar 10, 2013Sep 5, 2013Volterra Semiconductor CorporationMethod For Making Magnetic Components With M-Phase Coupling, And Related Inductor Structures* Cited by examinerClassifications U.S. Classification336/192, 336/83, 336/90, 336/96International ClassificationH01F41/12, B29C45/14, H01F17/00, H01F41/04Cooperative ClassificationB29C45/14639, H01F41/12, H01F41/046, H01F17/0033European ClassificationB29C45/14M, H01F41/04A8, H01F17/00A4, H01F41/12Legal EventsDateCodeEventDescriptionJun 7, 2011FPExpired due to failure to pay maintenance feeEffective date: 20110415Apr 15, 2011LAPSLapse for failure to pay maintenance feesNov 22, 2010REMIMaintenance fee reminder mailedSep 20, 2006FPAYFee paymentYear of fee payment: 4Mar 5, 2003ASAssignmentOwner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., NETHERLANDSFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:U.S PHILIPS CORPORATION;REEL/FRAME:013811/0346Effective date: 20030115Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V. GROENEWOUDSEWRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


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3 bedroom house for sale in Brittany, Morbihan, Guilliers, France
OFFERS ARE INVITED ON THIS PROPERTY Which is deceptive in size. This large three bed property with garden situated in a hamlet near to Guilliers and Medieval Josselin.
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Leggett ref: 74603BVS56
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Amazon.com: Ashley Eckler's review of Carhartt Women's Snow Flake Sherpa Cuff Gr...
I like these socks!, December 21, 2013
By Ashley Eckler
Nice and warm, fits great! I like the style too. Always nice to find good wool socks in the winter.
Top Reviewer Ranking: 8,586,537