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Trou aux Biches Resort & Spa (Trou Aux Biches, Mauritius) | Expedia
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Lie back and work on your tan with relaxing beach amenities like umbrellas and sun loungers. At Trou aux Biches Resort & Spa you can cool off in one of the 7 outdoor swimming pools and indulge in a pampering afternoon at the full-service spa. A complimentary manager's reception is offered on select days. Dining is available at one of the hotel's 6 restaurants. Guests can unwind with a drink at one of the hotel's bars, which include 2 bars/lounges, a beach bar, and a poolside bar. High-speed wireless Internet access is complimentary. This luxury hotel also offers a complimentary children's club, a children's pool, and outdoor tennis courts. Complimentary self parking is available on site. Trou aux Biches Resort & Spa has designated areas for smoking. 24-hour front desk Airport transportation (surcharge) Babysitting or childcare (surcharge) Beach bar Beach sun loungers Beach towels Beach umbrellas Business center Children's club (free) Children's pool Free reception Concierge services Conference space size (feet) - 2044 Conference space size (meters) - 190 Designated smoking areas Dry cleaning/laundry service Fitness facilities Free self parking Free WiFi Full-service spa Garden Gift shops or newsstand Hair salon Laundry facilities Limo or Town Car service available Luggage storage Number of bars/lounges - 2 Number of outdoor pools - 7 Number of restaurants - 6 One meeting room Outdoor tennis courts 6 Poolside bar Porter/bellhop Shopping on site Spa treatment room(s) Supervised childcare/activities (free) Tennis on site Total number of rooms - 333 Tours/ticket assistance Turkish bath/Hammam Wedding services Show all hotel amenities Family Friendly Amenities
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Patent US20060187097 - Sigma delta converter with flying capacitor input - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA sigma delta analog to digital converter of the type adapted to be connected to a capacitive current input device, comprises: a sigma delta modulator having an input; and a flying capacitor constructed so as to be connected between the input of the sigma delta modulator and the capacitive current input...http://www.google.com/patents/US20060187097?utm_source=gb-gplus-sharePatent US20060187097 - Sigma delta converter with flying capacitor inputAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20060187097 A1Publication typeApplicationApplication numberUS 11/064,161Publication dateAug 24, 2006Filing dateFeb 23, 2005Priority dateFeb 23, 2005Also published asUS7230555Publication number064161, 11064161, US 2006/0187097 A1, US 2006/187097 A1, US 20060187097 A1, US 20060187097A1, US 2006187097 A1, US 2006187097A1, US-A1-20060187097, US-A1-2006187097, US2006/0187097A1, US2006/187097A1, US20060187097 A1, US20060187097A1, US2006187097 A1, US2006187097A1InventorsEnrico Dolazza, Hans WeedonOriginal AssigneeEnrico Dolazza, Hans WeedonExport CitationBiBTeX, EndNote, RefManPatent Citations (15), Referenced by (6), Classifications (4), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSigma delta converter with flying capacitor input
US 20060187097 A1Abstract
A sigma delta analog to digital converter of the type adapted to be connected to a capacitive current input device, comprises: a sigma delta modulator having an input; and a flying capacitor constructed so as to be connected between the input of the sigma delta modulator and the capacitive current input device. In a preferred embodiment, the converter includes an input stage having an input coupled to the flying capacitor; a feedback path; a digital to analog converter (DAC) disposed in the feedback path and having a DAC output; and a DAC output capacitor and a second switch for alternately switching the DAC output capacitor between a first connection so as to transfer a signal from the output of the digital to analog converter to the DAC output capacitor and a second connection so as to transfer a signal from the DAC output capacitor to the input of the sigma delta modulator. The flying capacitor includes a charging capacitor and a flying capacitor switch, the flying capacitor being constructed so as to be alternately switched between a first connection so as to transfer a signal from the capacitive current input device to the charging capacitor and a second connection so as to transfer a signal from the charging capacitor to the input of the sigma delta modulator. The switching frequency of both switches is preferably operated at the same frequency fs so as to define a common switching cycle for both the flying capacitor switch and the second switch, and synchronized so that the flying capacitor switch and the second switch are each switched to the first connection during one phase of the switching cycle and switched to the second connection during a second phase of the switching cycle. The converter has particular utility for any device having capacitive current input devices, such as CAT scanner detectors and electret microphones. The disclosure also describes and claims a method of converting a current provided by a capacitive current input device to a digital signal using a sigma delta analog to digital converter. Images(6) Claims(18)
FIELD [0001] The disclosure relates generally to analog to digital (A/D) converters, and more particularly to Sigma Delta (ΣΔ) Analog-to-Digital (A/D) converters of the type having capacitive current inputs. BACKGROUND [0002] ΣΔ A/D converters with capacitive current inputs are converters that digitize the output current of devices having significant output capacitance to ground. The equivalent circuit of such capacitive current generating devices 12 is shown in FIG. 1. Examples of such devices include, but are not limited to, photodiodes like those used in x-ray detectors of CAT scanners (in which case the output capacitance may of the order of 50 pF, including the layout capacitance) and electret microphones (normally referred to as electrostatic microphones). [0003] In most cases, such devices have output voltage compliance limitations. Specifically, the voltages applied at their outputs should be kept within certain limits, although such a requirement becomes somewhat less stringent as the output current of such devices increases. For instance, zero-biased photodiodes used in CAT scanner detectors have typical output voltage compliance requirements of about 0±5 mV when the output current is around zero, and of about 0±25 mV when the output current is near full scale. [0004] Various techniques of connecting the output of a capacitive current generator device to a ΣΔ A/D converter exist in prior art. Most, if not all, of them fall into one of the following three categories. [0005] In a first connection category, an example of which is illustrated in FIG. 2, the output of the capacitive current generating device 22 is connected to an intermediate filter stage 24 that converts the analog input current to a voltage. The voltage signal is then sampled, held, and digitized by the ΣΔ converter 26. In this case, the converter 26 operates as a voltage input digitizer. This connection category is very frequently used in CAT scanner data acquisition systems (DAS), in which the intermediate filter stage 24 is most frequently implemented as a reset integrator, like that one shown in FIG. 2. [0006] Whereas the type of connection illustrated in FIG. 2 can be designed to insure the voltage compliance requirements of the current generating device, it has substantial limitations: 1) the intermediate filter stage 24 adds circuitry complexity, and therefore adds cost power dissipation and reduces the overall reliability of the DAS channel; 2) the noise generated by the intermediate filter stage 24 must be kept very low; something that may be difficult when the output capacitance of the current source is significant as that of detector photodiodes; 3) the intermediate filter stage 24 pre-defines the frequency response of the converter output, thus eliminating the possibility of optimizing the frequency response of the DAS output for different applications and/or procedures. [0007] In a second connection category, as illustrated in FIG. 3, the output of the capacitive current generating device 32 is connected to the input of the ΣΔ A/D converter 36 via an intermediate trans-impedance stage 34. This latter stage transforms the analog input current signal to an analog voltage signal. This analog voltage signal represents the input of the converter, which, also in this case, operates as a voltage input digitizer. [0008] Like the first category of connection, this second one results in added circuit complexity, which means added costs and power dissipation as well as lower reliability of the DAS channels. The same considerations apply to the noise introduced by this intermediate stage 34. This second connection category, however, performs differently from the first one from two points of view: 1) the intermediate trans-impedance stage 34 does not pre-define the frequency response of the converter output of converter 36, which now can be optimized for the application by properly programming the digital filter/decimator of the ΣΔ converter 36; 2) the value of the resistor 38 in the trans-impedance stage 34 must be tuned to the value of the full scale input current to keep a reasonable stage gain so as to maintain voltage compliance requirements. Therefore, when different applications call for different values of the full scale input current, the stage 34 should feature selectable resistor values, thus further increasing the circuit complexity. [0009] In a third category of connection, schematically illustrated in FIG. 4, the output of the capacitive current generating device 42 is coupled to the input of the ΣΔ A/D converter 44, the converter operating as a current input digitizer, converting the current input from capacitive current generating device 42 to a digitized value. U.S. Pat. No. 6,657,571, assigned to the present assignee, covers this type of connection in CAT scanner DAS applications. [0010] The directly coupled input of the type shown in FIG. 4 removes all cost and noise disadvantages related to the introduction of an intermediate stage and, at the same time, insures the input voltage compliance requirements and preserves the possibility of optimizing the frequency response of the converter as a function of the application. Therefore, ΣΔ converters directly coupled to detector photodiodes (as illustrated in FIG. 4) provide an excellent solution for single or dual ring CAT scanner DAS's, which typically feature a number of channels of the order of 1000. [0011] However, the type of connection shown in FIG. 4 presents limitations when power dissipation and operational speed requirements become severe. DAS's of multi-ring, high speed CAT scanners offer a pertinent example . Such scanners provide a dramatic increase in the number of channels (in excess of 50,000 for 64 rings), which in turn poses a stringent upper limit to the channel power dissipation, which for most applications should be kept substantially below 4 mW. However, such scanners, having higher rotational speeds, call for higher power of the X-ray tube, so that a sufficient x-ray flux is radiated in a shorter time. Higher x-ray flux, in turn, results in higher current per unit area of the photodiode that can reach hundreds of nanoamperes per square millimeter. [0012] As illustrated in FIG. 5, the capacitive current generating device 52, having an output capacitance CD, indicated as 54, is connected directly to the input of the ΣΔ modulator or converter 56. The converter 56 is shown as including the first integrator stage 58, also designated A1, comprising an integrating amplifier. As previously described, the inverting input of the integrating amplifier is directly coupled to the capacitive current generating device 52. Assume that the integrator stage 58 is implemented so that the integrating amplifier operates as a voltage output operational amplifier, having a gain-bandwidth product f0 and a feedback capacitance CF. The input impedance to ground of the voltage output operational amplifier of stage 58 is given, in first approximation, by the capacitance of CD in parallel with an equivalent resistor that has an approximate value of 1/27πf0CF. As a result, any time the DAC 68 of the ΣΔ converter feeds back a charge at the input of the first integrator stage, this input will settle with a time constant τ approximately equal to CD/27πf0CF. The DAC 68 of the converter feeds back a charge at the over-sampling frequency fS, and therefore the first stage input must settle with very high precision, in the time 1/fS. In practice one can quantify the required precision stating that the time 1/fS must be of the order of 10 times the constants τ. As a result one can derive a first cut estimate of the required amplifier gain-bandwidth product as follows: f 0=˜10 f S C D/2πC F (1) [0013] Returning to the example of a DAS for a multi-ring, high speed CAT scanner considered above, when the DAS is implemented with ΣΔ converters integrated in silicon, typical values of CF are of the order of few tenths of a picofarad; and the over-sampling frequency fS must be as high as several megahertz, to handle full-scale input currents like those considered above. As indicated above, typical values of CD are in the range of 50 pF. As a result, the gain-bandwidth product of the operational amplifier of the first integrator stage 58 should be of the order of several gigahertz. Operational amplifiers with such a high gain-bandwidth product are not economically feasible and, in any event, will dissipate power well in excess of the total power budget allocated to the entire channel, since the power dissipation of an operational amplifier is more than proportional to its gain-bandwidth product. [0014] The present disclosure provides an approach for realizing the direct coupling of a capacitive current input device to a ΣΔ A/D converter that can be implemented with current IC mixed signal technologies and that meets all stated speed and power performance requirements. SUMMARY [0015] A sigma delta analog to digital converter of the type adapted to be connected a capacitive current input device, comprises a sigma delta modulator having an input; and a flying capacitor constructed to be connected between the input of the sigma delta modulator and the capacitive current input device. In a preferred embodiment, the converter includes an input stage having an input coupled to the flying capacitor; a feedback path; a digital to analog converter (DAC) disposed in the feedback path and having a DAC output; and a DAC output capacitor and a second switch for alternately switching the DAC output capacitor between a first connection so as to transfer a signal from the output of the digital to analog converter to the DAC output capacitor and a second connection so as to transfer a signal from the DAC output capacitor to the input of the sigma delta modulator. The flying capacitor includes a charging capacitor and a flying capacitor switch, the flying capacitor being constructed so as to be alternately switched between a first connection so as to transfer a signal from the capacitive current input device to the charging capacitor and a second connection so as to transfer a signal from the charging capacitor to the input of the sigma delta modulator. The switching frequency of both switches is preferably operated at the same frequency fs so as to define a common switching cycle for both the flying capacitor switch and the second switch, and synchronized so that the flying capacitor switch and the second switch are each simultaneously switched to the first connection during one phase of the switching cycle, and simultaneously switched to the second connection during a second phase of the switching cycle. The converter has particular utility for any device having capacitive current input devices, such as CAT scanner detectors and electret microphones. The disclosure also describes and claims a method of converting a current provided by a capacitive current input device to a digital signal using a sigma delta analog to digital converter. [0016] Additional aspects and advantages of the present disclosure will become readily apparent to those skilled in this art from the following detailed description, wherein exemplary embodiments of the present disclosure are shown and described, simply by way of illustration of the best modes contemplated for carrying out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
GENERAL DESCRIPTION OF THE DRAWINGS [0017] Reference is made to the attached drawings, wherein: [0018] FIG. 1 is an equivalent circuit of a capacitive current generating device; [0019] FIG. 2 is a circuit schematic illustrating a first category of prior art technique of connecting the output of a capacitive current generator device to a ΣΔ A/D converter. [0020] FIG. 3 is a circuit schematic illustrating a second category of prior art technique of connecting the output of a capacitive current generator device to a ΣΔ A/D converter. [0021] FIG. 4 is a circuit schematic illustrating a third category of prior art technique of connecting the output of a capacitive current generator device to a ΣΔ A/D converter. [0022] FIG. 5 is a circuit schematic illustrating a prior art ΣΔ converter of the type described in U.S. Pat. No. 6,657,571, and including a first integrator stage directly coupled to the capacitive current generating device having an output capacitance. [0023] FIG. 6.1 is a circuit schematic illustrating a ΣΔ converter modified in accordance with teachings of the present disclosure. [0024] FIG. 6.2 is a partial schematic illustrating one phase of operation of the ΣΔ converter of FIG. 6.1. [0025] FIG. 6.3 is a partial schematic illustrating a second phase of operation of the ΣΔ converter of FIG. 6.1.
DETAILED DESCRIPTION OF THE DRAWINGS [0026] According to the disclosure the input of the operational amplifier 84 of the first integrator stage of the ΣΔ A/D converter 90 is modified so as to further comprise a series flying or switching capacitor CI comprising the switch SW1, indicated at 86, and the capacitor 88, connected so as to transfer charge from the capacitive current generating device 82 to the input of the amplifier 84 of the input stage. The capacitive output of the DAC 94 is designated as CDAC and for purposes of illustration is shown as a switching capacitor 92 having a switch SW2. During each over-sampling cycle of duration 1/fS, the flying capacitor CI switches generally synchronously with the capacitor CDAC that feeds back a charge proportional to the output voltage of the DAC 94. In a preferred implementation, for a short part of the cycle time (phase α) shown in FIG. 6.2, CI is connected to the capacitive current generating device 82 , while CDAC is connected to the voltage output of the DAC; during all the remaining cycle time (phase β), both CI and CDAC are connected to the input of the operational amplifier 84. FIG. 6.1, 6.2, and 6.3 show the input of the ΣΔ converter, modified according to this invention, and the configuration of CI and CDAC during the two phases of the cycle of the suggested timing. [0027] The flying input capacitor CI provides a main benefit of buffering the input of the operational amplifier 84 of the first integrator stage from the output capacitance CD of the current generating device 82. In fact, the operational amplifier 84 sees at its input only the capacitive load of CI (ignoring other negligible capacitive loads like that of CDAC) during its settling time, i.e. during phase β, whose duration can be a major fraction of the entire cycle time 1/f0. Therefore, equation (1) now can be rewritten as follows: f 0*=˜10 f S C I/2π C F (2) [0028] In general, CI can be made substantially smaller than CD, without violating input voltage compliance requirements, and at the expense of an additional thermal noise term that can be shown to be negligible with respect to the KTC noise of the input stage. As a result, the new required value of the gain-bandwidth product, f0*, of the operational amplifier 84 of the first integrator stage is substantially lower than the value of originally stated, so that the amplifier can be implemented using current IC mixed signal technologies and its power dissipation will be reduced by an amount more than proportional to the ratio CD/CI. [0029] Consider the voltage compliance requirement at the input of the converter. The current input signal has a full-scale value IFS, which may vary as a function of the application. Typically, a current input ΣΔ A/D converter can handle a wide range of full-scale values of the input current, by proper adaptation of its over-digitization frequency fS. In this way the converter circuitry can be designed based on single full-scale input charge, qFS, per over-sampling cycle. The value of this charge is typically in the range 0.10-0.15 pC for ΣΔ converters implemented in silicon. The maximum voltage VD,FS applied to the output of the current generator device will be given, in first approximation, by the following equation: V D,FS ≈V D,0 +q FS /C I (3) The first term of equation (3) represents the value of the voltage in absence of input current (i.e. the input offset voltage of the first converter stage) and the second term represents its increase due to the full-scale input current. [0030] As seen, the typical voltage compliance requirement of a 0-biased photodiode is about ±5 mV and ±25 mV at zero and full-scale current output, respectively. In CAT scanner applications, therefore, the voltage compliance requirement sets a lower limit to the value of the capacitance of CI at about qFS/20 mV, i.e. around 5.0-7.5 pF. As a result, the capacitance of CI may be about ten times smaller than that of CD, without violating voltage compliance requirements typical of this application. [0031] Examining the additional thermal noise introduced by the flying capacitance CI, any time the flying capacitor CI disconnects from the capacitive input device, i.e. at the end of phase α of each cycle, a random charge +q remains stored on CI and an equal and opposite charge −q remains stored on CD. During the following phase β the charge +q is transferred to the feed-back capacitor CF of the first integrator stage of the converter. When, at the end of phase β, CI disconnects from the first integrator stage, a new random charge +q′ remains stored on CI and an equal and opposite charge −q′ remains stored on the feedback capacitor CF. Therefore, at each cycle, a random noise charge, (+q)+(−q′), is injected at the converter input. Both random charges belong to a distribution whose variance is approximately equal to KTCI, so that the variance of the noise injected at the converter input at each cycle is approximately equal to 2KTCI. The opposite random charges stored on CI and on CD at the end of the cycle, however, do not dissipate to ground, because there is no path through which they can flow. Rather, during the successive cycles, they redistribute between CD, CI and CF and eventually they wind up entirely on CF and fully compensate the noise charge originally stored on it. This compensation process takes place exponentially, with a time constant that is a function of CD and CI. In this way, the switching of the flying capacitor CI generates a noise that disappears in time, i.e. a noise that does not have a DC component or, in other terms, a noise whose spectral density is equal to zero at f=0. An analytical evaluation of the spectral density of the noise power per cycle, NCl(f), due to the switching of CI can be generated. It is: N Cl(f)=(2KTC I /f S)[μ−1−(μ−1−1) Σk μk cos (2π kf/f S)] (4) [0032] In equation (4), μ=CD/(CI+CD) and the summation variable k spans from 0 to ∞. It is easy to verify that NCI is equal to zero for f=0. In fact it is: N Cl(0)=(2KTC I /f S)[μ−1−(μ−131 1)/(1−μ)]=0 [0033] One can also evaluate the first derivative of NCI(f) and verify that it also is equal to zero for f=0 and, therefore, that the power density of this noise mechanism has a double zero at DC. [0000] For |f|<<|fS| equation (4) is well approximated by the following simpler equation: N CI(f)≈(4π2 KTC D /f S)(3+2C D /C I)(f/fS)2 (5) [0034] Equation (5) shows that the spectral density of the noise power per cycle due to the switching of CI, has a parabolic behavior in the frequency region in which |f|<<|fS|. The low pass filter of the ΣΔ A/D converter passes the frequency components of the band of interest practically unchanged, and drastically attenuates the frequency components that are between the “band of interest” and ±fS/2. Defining the “band of interest” as the frequency band defined by |f|≦|fS/2ξ|, where ξ is the over-digitization factor, i.e. the ratio between the converter sampling frequency, fS, and the frequency at which the band of interest is sampled. For sake of simplicity, but without loss of generality, assume that the converter filter has a gain of 1 in the band of interest, i.e. in the frequency interval |f|≦|fS/2ξ|, and has a gain of 0 in the frequency interval |fS/2ξ|<|f|≦|fS/2|. The power per cycle of this noise mechanism, transferred to the converter output, σCI 2, will be the integral of the noise power density NCI(f) in the band of interest defined above. It results: σCI 2≈(π2 KTC D/3)(3+2C D /C I)/ξ3 (6) [0035] It is convenient to compare the output noise power related to the switching of CI to the output noise power per cycle, σDAC 2, related to the switching of the DAC capacitor CDAC at the input of the converter. In fact, σDAC 2 should be the dominant noise source in a well designed ΣΔ A/D converter. Under the same assumption of the behavior of the filter of the converter, it results in: σDAC 2=2KTC DAC/ξ (7) [0036] Quantifying the comparison in the specific case of a ΣΔ converter implemented in silicon, which digitized the current output of a detector of a multi-ring CAT scanner. Reasonable capacitor values for this application are as follows: CD=50 pF, CI=7.5 pF, CDAC=0.1 pF. [0037] This results in: σCI 2≈1.2 10−29/ξ3 [C2] and σDAC 2≈9.0 10−34 /ξ[C 2]. These values show that the two noise mechanisms contribute to an equal output noise power at an over-digitization of about 115. At over-digitization values in excess of about 250, which is a lower limit for all practical applications, the output noise power due to the switching of the input flying capacitor is substantially smaller than that related to the switching of the DAC capacitor CDAC of the input stage of the converter. [0038] As shown in FIG. 6.1, the ΣΔ A/D converter can be used in various systems, such as but not limited to a CAT scanner and an electret microphone, indicated generally at 100. Other applications will be self evident to those skilled in the art. [0039] Thus, a new and improved ΣΔ A/D converter constructed in accordance with the present disclosure, and some applications for the converter, have been described. The exemplary embodiment described in this specification have been presented by way of illustration rather than limitation, and various modifications, combinations and substitutions may be effected by those skilled in the art without departure either in spirit or scope from this disclosure in its broader aspects and as set forth in the appended claims. [0040] The ΣΔ A/D converter of the present disclosure as disclosed herein, and all elements thereof, are contained within the scope of at least one of the following claims. No elements of the presently disclosed ΣΔ A/D converter are meant to be disclaimed, nor are they intended to necessarily restrict the interpretation of the claims. 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Patent US7439717 - Secondary side post regulators - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA synchronously switched buck post regulator is revealed for multi-output forward converters. The synchronously switched buck post regulator accomplishes precise independent load regulation for each output and reduced magnetics volume by using a coupled inductor with a common core for all outputs plus...http://www.google.com/patents/US7439717?utm_source=gb-gplus-sharePatent US7439717 - Secondary side post regulatorsAdvanced Patent SearchPublication numberUS7439717 B1Publication typeGrantApplication numberUS 11/684,743Publication dateOct 21, 2008Filing dateMar 12, 2007Priority dateSep 18, 2004Fee statusLapsedAlso published asUS7589571, US20060062026Publication number11684743, 684743, US 7439717 B1, US 7439717B1, US-B1-7439717, US7439717 B1, US7439717B1InventorsErnest Henry Wittenbreder, Jr.Original AssigneeErnest H. Wittenbreder, Jr.Export CitationBiBTeX, EndNote, RefManPatent Citations (12), Classifications (12), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSecondary side post regulatorsUS 7439717 B1Abstract A synchronously switched buck post regulator is revealed for multi-output forward converters. The synchronously switched buck post regulator accomplishes precise independent load regulation for each output and reduced magnetics volume by using a coupled inductor with a common core for all outputs plus a second smaller inductor for each output except the highest voltage output.
1. A secondary side buck post regulator for a second output of a multi-output forward converter comprising,
a first coupled inductor having a first winding and a second winding with an undotted terminal of said first winding connected to a first output of said multi-output forward converter and with said second winding connected in series with said second output of said multi-output forward converter,
a second inductor connected in series with said second winding of said first coupled inductor,
first switch means having a drain terminal connected to a dotted terminal of said first winding of said first coupled inductor,
second switch means, operable substantially in anti-synchronization to said first switch means, having a source terminal connected to an output terminal, which is common to said first output and to said second output of said multi-output forward converter and having a drain terminal connected to a source terminal of said first switch means and connected to a series winding network comprising said second inductor and said second winding of said first coupled inductor,
whereby said secondary side buck post regulator provides a second precisely regulated output with reduced magnetics volume and cost.
CROSS-REFERENCE TO RELATED APPLICATION This is a division of application Ser. No. 10/944,588, filed 2004 Sep. 18, now abandoned.
The subject invention generally pertains to electronic power conversion circuits, and more specifically to high frequency, switched mode electronic power converters. Some of the subject matter of this application was first revealed in Disclosure Document Number 527396.
Many electronic circuits require power at more than one voltage, so power supply manufacturers offer power supplies with multiple regulated outputs. This was often an application for magnetic amplifiers, but magnetic amplifiers have become less popular as switching frequencies have risen and silicon semiconductor prices have fallen. One common way of providing additional regulated outputs in current use is illustrated in FIG. 1. Operational wave forms for the FIG. 1 circuit are illustrated in FIG. 2. In FIG. 1 a second regulated output is provided by a synchronously switched buck post regulator, which is a sort of semiconductor magnetic amplifier. In the FIG. 1 circuit an output choke L1 is provided for the main output and a second output choke L2 is provided for the second output. In general the first output voltage is fed back to control the primary switch and the second output is regulated with a local feedback loop which controls the delay in the turn on time of MS2A with respect to the turn on time of MS1A. This is leading edge modulation which is similar to that used in a magnetic amplifier. In most of these power converters there is a maximum power level which is the sum of the powers of the two outputs, but either of the two outputs can be operated at or near the maximum power level. This requires two output chokes each of which must be sized for the converter's maximum power level. An alternate method is illustrated in FIG. 3. The FIG. 3 circuit uses a coupled output choke to obviate two separate magnetic circuit elements sized for maximum power. In the coupled inductor the single core must be sized for maximum power and the window area must be sized to accommodate two windings each of which must be capable of accommodating the maximum output power. This is an improvement which results in a smaller and cheaper output choke, compared to the FIG. 1 circuit. The disadvantage of the FIG. 3 circuit is that the second output is not independently regulated and two secondary windings are required on the main transformer. What is needed is a circuit that achieves the performance of the FIG. 1 circuit but with lower total output choke volume.
OBJECTS AND ADVANTAGES An object of the subject invention is to reveal a technique for achieving multiple independently regulated output voltages with reduced total magnetics volume.
These and other objects of the invention are provided by new circuit structures for achieving independently regulated outputs in a multi-output power supply with reduced magnetics volume. Also revealed is a simple capacitor coupled floating drive circuit that is tolerant of voltage variations at the terminals of the high side switch.
FIG. 1 illustrates a forward converter with two independently regulated outputs according to the prior art.
FIG. 2( a) illustrates the timing wave form for the MPRI and MS1A switches of FIG. 1.
FIG. 2( b) illustrates the timing wave form for the MS1B switch of FIG. 1.
FIG. 2( c) illustrates the timing wave form for the MS2A switch of FIG. 1.
FIG. 2( d) illustrates the timing wave form for the MS2B switch of FIG. 1.
FIG. 2( e) illustrates the current wave form for the L1 inductor of FIG. 1.
FIG. 2( f) illustrates the current wave form for the L2 inductor of FIG. 1.
FIG. 3 illustrates a forward converter with two outputs utilizing a single coupled output choke according to the prior art.
FIG. 4 illustrates a forward converter with two independently regulated outputs using a coupled output choke according to the subject invention.
FIG. 5( a) illustrates the timing wave form for the MPRI and MS1A switches of FIG. 4 according to the subject invention.
FIG. 5( b) illustrates the timing wave form for the MS1B switch of FIG. 4 according to the subject invention.
FIG. 5( c) illustrates the timing wave form for the MS2A switch of FIG. 4 according to the subject invention.
FIG. 5( d) illustrates the timing wave form for the MS2B switch of FIG. 4 according to the subject invention.
FIG. 5( e) illustrates the current wave form for the L1A inductor of FIG. 4 according to the subject invention.
FIG. 5( f) illustrates the current wave form for the L2 and L1B inductors of FIG. 4 according to the subject invention.
FIG. 6 illustrates a forward converter with two independently regulated outputs using a coupled output choke with low magnetic coupling according to the subject invention.
FIG. 7 illustrates a current doubler rectifier forward converter with a quarter bridge primary network and two independently regulated outputs using coupled output chokes according to the subject invention.
SUMMARY The subject invention reveals a circuit that can achieve multiple independently regulated outputs in a forward converter with lower overall magnetic circuit volume and cost.
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 illustrates a single-ended forward converter with two outputs that can be independently regulated. The first output relies on modulation of the primary switch to achieve its regulation. The second output relies upon a second local control loop (not shown) to accomplish its regulation. The second output is a synchronously switched buck converter which is also referred to as a semiconductor magnetic amplifier since the switch control is similar to that of a magnetic amplifier. The main switch, MS2A, of the second output's buck converter is turned off in synchronization with the first output in each switching cycle and turned on after the switch MS1A during each switching cycle. Wave forms of the switch timing and output choke currents are illustrated in FIGS. 2( a) through 2(f). In commercial multi-output power supplies the designer's goal is to provide two independently regulated outputs, each of which can handle the converter's full output power rating in order to accommodate the broadest range of customers. In the FIG. 1 circuit each of the two output chokes must be sized to accommodate the full output load. FIG. 3 illustrates another prior art example that has been used for multi-output power supplies. In the FIG. 3 circuit there is a single output choke that accommodates both outputs, but the two outputs cannot be independently regulated in the FIG. 3 circuit. Different voltage levels can be set by adjusting the turns ratios for the two outputs. The turns ratio for the secondary windings should match the turns ratio for the coupled inductor windings in order for the output currents to be non-pulsating. The FIG. 3 circuit has the advantage of smaller magnetics over the FIG. 2 circuit, since the two outputs share a common magnetic core, but the two outputs are not independently regulated. The common magnetic core of the two outputs of the FIG. 3 circuit need only be large enough to handle the full power of the power supply.
FIG. 4 illustrates a two output power supply with independently regulated outputs that uses a common magnetic core for the two outputs, thereby saving the space of another large core sized to handle the full output power, plus a second much smaller core, L2, with a much smaller inductance that adds the ability to independently regulate the second output in a synchronously switched buck converter. In the FIG. 4 circuit the first output is controlled by controlling the duty cycle of the primary switch MPRI. The switch MS1A is operated in full synchronization with MPRI and the switch MS1B is operated in anti-synchronization to MPRI. A wave form illustrating the switch timing for MPRI and MS1A is illustrated in FIG. 5( a). A wave form illustrating the timing for the MS1B switch is illustrated in FIG. 5( b). The output voltage for the first output is determined by the duty cycle of MPRI and the turns ratio of the transformer T. For the second output the switch MS2A is turned off in synchronization with MPRI, but MS2A is turned on after MPRI so that there is a delay between the time MPRI is turned on and the time at which MS2A is turned on, as illustrated in FIG. 5( c). Switch MS2B turns on in synchronization with switch MS1B when MPRI is turned off, but MS2B turns off after MS1B is turned off due to the delay in the turn on of MS2A. MS2B operates in anti-synchronization to MS2A, as illustrated in FIG. 5( d). Because MS2A is delayed with respect to MPRI and MS1A the duty cycle for the second output will be less than the duty cycle for the first output and the voltage at the second output will be less than the voltage at the first output. The inductor L2 forces the output current for the second output to be non-pulsating since an infinite voltage would be required to create a step change in current in L2. The current in L1A is also non-pulsating, since there is no mechanism in the circuit to instantly interrupt current flow in either L1A or L1B. Current in L1A is provided through MS1A and the transformer secondary winding when MPRI is on or through MS1B when MPRI is off, although L1A could still be pulsating despite this fact, but only if the current in L1B is interrupted. L2 forces the current in L1B to be continuous. The currents in L1A and L1B will both be continuous, but they will not, in general, be simple triangular wave forms. A current wave form for L1A is illustrated in FIG. 5( e) and a corresponding wave form for L1B current is illustrated in FIG. 5( f). The current in L1B must be equal to the current in L2, since the two windings are in series. The slope of the current in L2 will depend on the value of L2 and the voltage applied to L2. During the course of one switching cycle there are three different values of applied voltage for L2. When MPRI is off MS1B and MS2B are on and the voltage at the node A is zero. While MPRI is off the dotted terminal of L2 is at ground and the undotted terminal of L2 is at a voltage V1, where
V 1 = V OUT2 - N 2 N 1 * V OUT1 , VOUT2 is the output voltage of the second output, VOUT1 is the output voltage of the first output, N2 is the number of turns of L1B, and N1 is the number of turns of L1A. Depending on the turns ratio,
N 2 N 1 , the current slope of L2 during the time that MPRI is off can be positive, negative, or zero. In the example illustrated the current slope of L2 is near zero during the off time of MPRI, as illustrated in FIG. 5( f). When MPRI turns on, MS1A also turns on, and the voltage at the node A becomes positive, such that
V A = N SEC N PRI * V INPUT , where VINPUT is the voltage of the input source, NPRI is the number of primary turns of transformer T, and NSEC is the number of secondary turns of transformer T. While MS1A is on and MS2B remains on, the voltage at the undotted terminal of L2 is V2, where
V 2 = V OUT2 + N 2 N 1 * ( V A - V OUT1 ) , so that the undotted terminal of L2 is higher in voltage than the dotted terminal of L2 and the current in L2 must be decreasing. In the example illustrated the rate of decreasing current is relatively large for this example while MPRI is on and MS2A is off, as illustrated in FIG. 5( f). When MS2B turns off and MS2A turns on, while MPRI and MS1A remain on, the voltage at the dotted terminal of L2 is VA and the voltage at the undotted terminal of L2 is V2 and the voltage applied to L2 is V3, where V3=VA−V2. During the on time of MS2A, the current slope in L2 can be positive, negative, or zero depending on the turns ratio,
N 2 N 1 , and the values of VA, VOUT1, and VOUT2. In the example illustrated the current slope in L2 is positive, as illustrated in FIG. 5( f). In a practical application the current slope of L2 during the on time of MS2A will, in general, be positive. Since L2 is connected in series with L1B the current in L1B will always be equal to the current in L2. The current slope in L1A will depend on the voltage applied to L1A and on the current slope of L1B and L2. The relationship between the voltage applied to L1A and its current slope is
V L1A = L 1  A * dI L1A dt + M 12 * dI L1B dt = L 1  A * dI L1A dt + M 12 * dI L2 dt , ( 1 ) where VL1A is the L1A applied voltage, IL1A is the current in L1A, IL1B is the L1B current, M12 is the L1AL1B mutual inductance, and IL2 is the L2 current. From equation (1) we can solve for the L1A current slope so that
dI L1A dt = V L1A L 1  A - M 12 L 1  A * dI L2 dt . ( 2 ) From equation (2) we see how the L1A current slope depends on both the voltage applied to the L1A winding and the current slope in the L1B winding. The turns ratio,
N 2 N 1 , should be set to provide a minimum average applied voltage for L2 in order to minimize the current slopes and output ripple currents, which serves to minimize the size of L2. The primary benefit of the subject invention is a reduction in total magnetics volume combined with independent regulation of both outputs. The reduction of magnetics volume is accomplished by using a common core for the L1A and L1B windings so that only one large core capable of handling the full output power is required. A second smaller inductor, L2, is required to provide independent regulation for both outputs.
FIG. 5 illustrates the subject invention with series inductances l1A and l1B, which represent the leakage inductances or uncoupled inductances in each winding of L1. In general, it is preferable to loosely couple the windings in a coupled inductor forward converter application, thereby increasing the leakage inductances, since the main advantage of using the common core for both outputs is a size and cost reduction, not a performance improvement. The effect of the leakage inductance here is to improve the overall ripple performance. The relatively large leakage inductances, in comparison to a tightly coupled L1, provide additional current smoothing without an additional magnetic circuit element.
FIG. 7 illustrates a multi-output current doubler rectifier forward converter with a quarter bridge primary switching network and independently regulated outputs according to the subject invention. In the FIG. 7 circuit planar magnetics become more practical because of the reduction of primary winding voltage stress. In the current doubler configuration two chokes are required for each output. In the FIG. 7 circuit two independently regulated outputs are achieved using two large chokes and two small chokes.
CONCLUSION, RAMIFICATIONS, AND SCOPE OF INVENTION Thus the reader will also see that a multi-output power supply using a secondary side synchronously switched post buck regulator can be improved by combining the output chokes onto a single core capable of handling the converter's full power and adding a small choke for the second output to provide fully independent regulation of the outputs.
While my above description contains many specificities, these should not be construed as limitations on the scope of the invention, but rather, as exemplifications or preferred embodiments thereof. Many other variations are possible. For example, power converters with more than two independently regulated outputs using a single large output coupled inductor plus much smaller chokes for the second and successive outputs are possible using the techniques revealed here.
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Patent US6888739 - Nanocrystal write once read only memory for archival storage - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsStructures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel...http://www.google.com/patents/US6888739?utm_source=gb-gplus-sharePatent US6888739 - Nanocrystal write once read only memory for archival storageAdvanced Patent SearchPublication numberUS6888739 B2Publication typeGrantApplication numberUS 10/177,214Publication dateMay 3, 2005Filing dateJun 21, 2002Priority dateJun 21, 2002Fee statusPaidAlso published asUS7154778, US7257022, US7639528, US20030235081, US20050199947, US20070091661, US20080062757, WO2004017362A2, WO2004017362A3Publication number10177214, 177214, US 6888739 B2, US 6888739B2, US-B2-6888739, US6888739 B2, US6888739B2InventorsLeonard ForbesOriginal AssigneeMicron Technology Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (58), Referenced by (32), Classifications (21), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetNanocrystal write once read only memory for archival storageUS 6888739 B2Abstract Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.
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G11C2216/06, G11C17/146, H01L29/42332, H01L29/7885, G11C17/08, H01L21/28273, G11C16/0416, G11C17/12European ClassificationB82Y10/00, G11C17/12, H01L21/28F, H01L29/788B6B, H01L29/423D2B2C, G11C17/14W, G11C16/04F1Legal EventsDateCodeEventDescriptionSep 28, 2012FPAYFee paymentYear of fee payment: 8Sep 30, 2008FPAYFee paymentYear of fee payment: 4Jul 19, 2005CCCertificate of correctionJun 21, 2002ASAssignmentOwner name: MICRON TECHNOLOGY, INC., IDAHOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FORBES, LEONARD;REEL/FRAME:013043/0871Effective date: 20020424Owner name: MICRON TECHNOLOGY, INC. 8000 SOUTH FEDERAL WAYBOISFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FORBES, LEONARD /AR;REEL/FRAME:013043/0871RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


text: SnapshotPeople OverviewBoard MembersCommittees	BOARD MEMBERS AFFILIATED WITH Bernie Dorval *Bernie Dorval Return to CHINA RESOURCES JINHUA CO-AGroup Head of Insurance and Global Development and Co-Chairman of TD Canada Trust1111AgeTotal Annual Compensation---- Thomas J. MullinConstellation Brands Inc.Board AffiliationsTD Bank US Holding CompanyWilliam E. BennettWest Penn Power CompanyBoard AffiliationsTD Bank US Holding Company P. Kevin CondronThe Hanover Insurance Group, Inc.Board AffiliationsTD Bank US Holding CompanyBharat B. MasraniThe Toronto-Dominion BankBoard AffiliationsTD Bank US Holding Company Brian Michael LevittART Advanced Research Technologies Inc.Board AffiliationsTD Bank US Holding CompanyDana S. LevensonTD Bank US Holding CompanyBoard AffiliationsTD Bank US Holding Company Stanley E. GraysonPrudential Equity Group, LLCBoard AffiliationsTD Bank US Holding CompanyFrank J. McKennaThe Toronto-Dominion BankBoard AffiliationsTD Bank US Holding Company Natica von AlthannPPL CorporationBoard AffiliationsTD Bank US Holding CompanyRobert E. DorranceThe Toronto-Dominion BankBoard AffiliationsTD Bank US Holding Company Peter G. VigueThe Cianbro CompaniesBoard AffiliationsTD Bank US Holding Company

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