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Patent US20070264774 - Method of Manufacturing a Flash Memory Device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses....http://www.google.com/patents/US20070264774?utm_source=gb-gplus-sharePatent US20070264774 - Method of Manufacturing a Flash Memory DeviceAdvanced Patent SearchPublication numberUS20070264774 A1Publication typeApplicationApplication numberUS 11/383,073Publication dateNov 15, 2007Filing dateMay 12, 2006Priority dateMay 12, 2006Also published asCN100524699C, CN101071792A, US8129242Publication number11383073, 383073, US 2007/0264774 A1, US 2007/264774 A1, US 20070264774 A1, US 20070264774A1, US 2007264774 A1, US 2007264774A1, US-A1-20070264774, US-A1-2007264774, US2007/0264774A1, US2007/264774A1, US20070264774 A1, US20070264774A1, US2007264774 A1, US2007264774A1InventorsTian-Shuan Luo, Chun-Pei WuOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (1), Classifications (12), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetMethod of Manufacturing a Flash Memory Device
US 20070264774 A1Abstract
A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device. Images(19) Claims(31)
1. A method of manufacturing a flash memory device including a semiconductor spacer layer in operable contact with a first semiconductor layer to form a floating gate, the method comprising: forming the first semiconductor layer; forming the semiconductor spacer layer, including a plurality of recesses, on top of the first semiconductor layer; forming an oxide layer on top of the semiconductor spacer layer; and removing the oxide layer to form a semiconductor spacer structure and to expose an interior surface of each of the recesses. 2. A flash memory device formed by the method of claim 1. 3. A method of manufacturing a flash memory device comprising providing a plate line in operable contact with a first semiconductor layer to form a floating gate, the plate line having a plurality of recesses, wherein the plate line is fabricated using a wet etching process. 4. A flash memory device formed by the method of claim 3. 5. A method of manufacturing a flash memory device, the method comprising: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming a first semiconductor layer on the dielectric layer; forming an insulating layer on the first semiconductor layer; forming a plurality of buried drains in the substrate; providing a buried drain oxide layer forming a plurality of mesas, each mesa positioned on top of one of the buried drains, and each mesa having an upper surface extending above an upper surface of a remaining portion of the first semiconductor layer; removing the insulating layer to expose an upper surface of the remaining portion of the first semiconductor layer; forming a semiconductor spacer layer having a generally uniform thickness on top of the upper surfaces of the buried drain oxide layer mesas and the remaining portion of the first semiconductor layer, forming a plurality of recesses above the remaining portion of the first semiconductor layer; forming an oxide layer on top of the semiconductor spacer layer of sufficient thickness to fill in each of the plurality of recesses; removing a portion of the oxide layer formed on top of the semiconductor spacer layer to expose a portion of the semiconductor spacer layer, but leaving a remaining portion of the oxide layer within the plurality of recesses; removing a portion of the semiconductor spacer layer to expose the upper surfaces of the buried drain oxide layer mesas; and removing the remainder of the oxide layer formed on top of the semiconductor spacer layer and a portion of the buried drain oxide layer to expose a remainder of the semiconductor spacer layer, including an interior surface of each of the plurality of recesses, and a portion of the first semiconductor layer. 6. The method of manufacturing a flash memory device of claim 5, further comprising forming an insulating stacked structure on the exposed portions of the buried drain oxide layer, the first semiconductor layer, and the semiconductor spacer layer; and forming a second semiconductor layer on top of the insulating stacked structure. 7. The method of manufacturing a flash memory device of claim 6, wherein the second semiconductor layer forms a control gate. 8. The method of manufacturing a flash memory device of claim 6, wherein the first semiconductor layer, the semiconductor spacer layer, and the second semiconductor layer are each formed from polysilicon. 9. The method of manufacturing a flash memory device of claim 6, wherein the insulating stacked structure is an oxide-nitride-oxide structure. 10. The method of manufacturing a flash memory device of claim 5, further comprising a step of removing an exterior portion of each of the buried drain oxide layer mesas prior to the step of forming the semiconductor spacer layer on top of the buried drain oxide layer mesas. 11. The method of manufacturing a flash memory device of claim 10, wherein the step of removing an exterior portion of each of the plurality of buried drain oxide layer mesas is performed using a cleaning process. 12. The method of manufacturing a flash memory device of claim 5, wherein the step of removing a portion of the oxide layer formed on top of the semiconductor spacer layer to expose a portion of the semiconductor spacer layer is performed using a polishing process. 13. The method of manufacturing a flash memory device of claim 12, wherein the polishing process removes the oxide layer down to the semiconductor spacer layer, but does not substantially remove the semiconductor spacer layer. 14. The method of manufacturing a flash memory device of claim 5, wherein the insulating layer is formed from silicon-nitride. 15. The method of manufacturing a flash memory device of claim 5, wherein the dielectric layer is formed from silicon dioxide. 16. The method of manufacturing a flash memory device of claim 5, further comprising: removing a portion of the first semiconductor layer to expose a portion of the dielectric layer by using an etching process. 17. The method of manufacturing a flash memory device of claim 5, wherein the step of removing a portion of the semiconductor spacer layer is performed using an etching process. 18. The method of manufacturing a flash memory device of claim 5, wherein the step of removing a portion of the oxide layer formed on top of the semiconductor spacer layer to expose a portion of the semiconductor spacer layer and the step of removing a portion of the semiconductor spacer layer to expose the upper surfaces of the buried drain oxide layer mesas are each performed using an etching process. 19. The method of manufacturing a flash memory device of claim 5, wherein the step of removing a portion of the oxide layer formed on top of the semiconductor spacer layer to expose a portion of the semiconductor spacer layer and the step of removing a portion of the semiconductor spacer layer to expose the upper surfaces of the buried drain oxide layer are each performed using a polishing process. 20. The method of manufacturing a flash memory device of claim 5, wherein the step of removing the remainder of the oxide layer formed on top of the semiconductor spacer layer and a portion of the buried drain oxide layer is controlled to remove a predetermined amount of the oxide layers to a predetermined depth to obtain a predetermined gate coupling ratio. 21. The method of manufacturing a flash memory device of claim 5, wherein the first semiconductor layer and the semiconductor spacer together form a floating gate. 22. The method of manufacturing a flash memory device of claim 5, further comprising: removing a portion of the insulating layer including: forming a photo resist layer on top of the insulating layer; patterning the photo resist layer; and using the patterned photo resist layer as an etch mask for an etching process to remove the portion of the insulating layer. 23. The method of manufacturing a flash memory device of claim 5, wherein the step of forming buried drain oxide layer is performed using a deposition process. 24. The method of manufacturing a flash memory device of claim 5, further comprising: polishing the upper surfaces of the buried drain oxide layer mesas and the insulating layer using a chemical-mechanical-polishing planarization technique. 25. A flash memory device formed by the method of claim 5. 26. A method of manufacturing a flash memory device, the method comprising: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming a first semiconductor layer on the dielectric layer; forming an insulating layer on the first semiconductor layer; forming a plurality of buried drains in the substrate; forming a plurality of buried drain oxide layer mesas, one mesa on top of each of the buried drains, each of the plurality of buried drain oxide layer mesas having an upper surface extending above an upper surface of a remaining portion of the first semiconductor layer; removing the insulating layer to expose an upper surface of the remaining portion of the first semiconductor layer; forming a semiconductor spacer layer having a generally uniform thickness on top of the upper surfaces of the buried drain oxide layer mesas and the remaining portion of the first semiconductor layer, forming a plurality of recesses above the remaining portion of the first semiconductor layer, each recess including an exposed interior surface; removing a portion of the semiconductor spacer layer to expose the upper surfaces of the plurality of buried drain oxide layer mesas and at least a portion of the upper surfaces of the first semiconductor layer; and removing a portion of the buried drain oxide layer to expose a remainder of the semiconductor spacer layer. 27. The method according to claim 26, further comprising: forming an insulating stacked structure on the exposed portions of the buried drain oxide layer, the first semiconductor layer, and the semiconductor spacer layer; and forming a second semiconductor layer on top of the insulating stacked structure. 28. The method of manufacturing a flash memory device of claim 26, wherein in the step of removing a portion of the buried drain oxide layer, a sufficient amount of the buried drain oxide layer is removed to expose a portion of the first semiconductor layer. 29. The method of manufacturing a flash memory device of claim 26, wherein the step of removing the portion of the semiconductor spacer layer is performed using an etching process. 30. The method of manufacturing a flash memory device of claim 26, wherein the step of removing the portion of the semiconductor spacer layer is performed using a polishing process. 31. A flash memory device formed by the method of claim 26. Description
BACKGROUND OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to flash memory devices having an enhanced gate coupling ratio. Flash memory devices are known in the art. For example, U.S. Pat. No. 6,897,116 (Lee et al., “the '116 patent”) discloses an embodiment of a flash memory device having an enhanced gate coupling ratio (GCR). The concept of gate coupling ratio is discussed in the '116 patent, and that discussion is incorporated herein by reference. A method of manufacturing a flash memory device having an enhanced gate coupling ratio which 1) provides greater flexibility of the manufacturing process and 2) does not require reduction of buried drain semiconductor space would be desirable. BRIEF SUMMARY OF THE INVENTION Briefly stated, in a first aspect, the present invention is directed to a method of manufacturing a flash memory device including a semiconductor spacer layer in operable contact with a first semiconductor layer to form a floating gate. The method comprises a step of forming the first semiconductor layer. The semiconductor spacer layer is formed, including a plurality of recesses, on top of the first semiconductor layer. An oxide layer is formed on top of the semiconductor spacer layer. The oxide layer is removed to form a semiconductor spacer layer and to expose an interior surface of each of the recesses. In a second aspect, the present invention is a method of manufacturing a flash memory device comprising a step of providing a plate line in operable contact with a first semiconductor layer to form a floating gate, the plate line having a plurality of recesses, wherein the plate line is fabricated using a wet etching process. In a third aspect, the present invention is a method of manufacturing a flash memory device comprising a step of providing a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate. A first semiconductor layer is formed on the gate oxide layer. An insulating layer is formed on the first semiconductor layer. A portion of the insulating layer is removed to expose a portion of the first semiconductor layer. A portion of the first semiconductor layer is removed to expose a portion of the gate oxide layer. Ions are implanted in the substrate to form a plurality of buried drains. A buried drain oxide layer forming a plurality of mesas is provided, each mesa positioned on top of one of the buried drains, and each mesa having an upper surface extending above an upper surface of a remaining portion of the first semiconductor layer. The upper surfaces of the buried drain oxide layer mesas and the insulating layer are polished to form a substantially planar surface. A remainder of the insulating layer is removed to expose an upper surface of the remaining portion of the first semiconductor layer. A semiconductor spacer layer having a generally uniform thickness is formed on top of the upper surfaces of the buried drain oxide layer mesas and the remaining portion of the first semiconductor layer. A plurality of recesses are thus formed above the remaining portion of the first semiconductor layer. An oxide layer is formed on top of the semiconductor spacer layer of sufficient thickness to fill in each of the plurality of recesses. A portion of the oxide layer formed on top of the semiconductor spacer layer is removed to expose a portion of the semiconductor spacer layer, but leaving a remaining portion of the oxide layer within the plurality of recesses. A portion of the semiconductor spacer layer is removed to expose the upper surfaces of the buried drain oxide layer mesas. The remainder of the oxide layer formed on top of the semiconductor spacer layer and a portion of the buried drain oxide layer are removed to expose a remainder of the semiconductor spacer layer, including an interior surface of each of the plurality of recesses, and a portion of the first semiconductor layer. An insulating stacked structure is formed on exposed portions of the buried drain oxide layer, the first semiconductor layer, and the semiconductor spacer layer. A second semiconductor layer is formed on top of the insulating stacked structure. In a fourth aspect, the invention is a method of manufacturing a flash memory device comprising a step of providing a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate. A first semiconductor layer is formed on the gate oxide layer. An insulating layer is formed on the first semiconductor layer. A portion of the insulating layer is removed to expose a portion of the first semiconductor layer. A portion of the first semiconductor layer is removed to expose a portion of the gate oxide layer. Ions are implanted in the substrate to form a plurality of buried drains. A plurality of buried drain oxide layer mesas are formed, one mesa on top of each of the buried drains. Each of the plurality of buried drain oxide layer mesas has an upper surface extending above an upper surface of a remaining portion of the first semiconductor layer. The upper surfaces of the buried drain oxide layer mesas and the insulating layer are polished to form a substantially planar surface. A remainder of the insulating layer is removed to expose an upper surface of the remaining portion of the first semiconductor layer. A semiconductor spacer layer having a generally uniform thickness is formed on top of the upper surfaces of the buried drain oxide layer mesas and the remaining portion of the first semiconductor layer, forming a plurality of recesses above the remaining portion of the first semiconductor layer, each recess including an exposed interior surface. A portion of the semiconductor spacer layer is removed to expose the upper surfaces of the plurality of buried drain oxide layer mesas and at least a portion of upper surfaces of the first semiconductor layer. A portion of the buried drain oxide layer is removed to expose a remainder of the semiconductor spacer layer. An insulating stacked structure is formed on the exposed portions of the buried drain oxide layer, the first semiconductor layer, and the semiconductor spacer layer. A second semiconductor layer is formed on top of the insulating stacked structure.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS The foregoing summary as well as the following detailed description of preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It is understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. In the drawings: FIGS. 1A-1D are a flow diagram of steps of multiple variations of a method for producing a flash memory device; FIGS. 2-13 are schematic cross-sectional views of a flash memory device undergoing a series of progressive manufacturing steps in accordance with a first variation of the method of FIG. 1; FIGS. 14-16 are schematic cross-sectional views of a flash memory device undergoing a series of progressive manufacturing steps in accordance with a second variation of the method of FIG. 1; FIGS. 17 and 18 are schematic cross-sectional views of a flash memory device undergoing a series of progressive manufacturing steps in accordance with a third variation of the method of FIG. 1: FIG. 19 is a schematic cross-sectional view of a flash memory device undergoing a manufacturing step in accordance with a fourth variation of the method of FIG. 1; FIGS. 20-25 are schematic cross-sectional views of a flash memory device undergoing a series of progressive manufacturing steps in accordance with a fifth variation of the method of FIG. 1; and FIG. 26 is a table summarizing the manufacturing steps associated with each of the multiple variations of the method of FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION Certain terminology is used in the following description for convenience only and is not limiting. The words, “right,” “left,” “lower” and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer to directions toward and away from, respectively, the geometric center of the electrical device power cord storage module and designated parts thereof. The terminology includes the words above specifically mentioned, derivatives thereof and words of similar import. Additionally, the word “a”, as used in the specification, means at least one. Referring to the drawings in detail, wherein like numerals indicate like elements throughout, there is shown in FIGS. 1-26 first through fifth variations 10 a through 10 e of a method 10 of manufacturing a flash memory device 300 having an enhanced gate coupling ratio. FIGS. 2-25 are shown at a scale greatly enlarged from the actual dimensions of the physical embodiment of the flash memory device illustrated. The relative proportions illustrated in FIGS. 2-25 of the various elements is not necessarily representative of the physical proportions of the elements. With reference to FIGS. 1A-1D, 2-13, and 26, first variation 10 a of the method 10 is illustrated. Steps of the method 10 are designated as “first”, “second”, etc. only for convenience in identifying the steps, and such nomenclature is not necessarily indicative of the order in which the steps are performed. With particular reference to FIGS. 1A and 2, the first variation 10 a of method 10 comprises a first step 20 of providing a semiconductor substrate 320. The substrate 320 may be formed in any number of known, conventional methods, such as float zone monocrystalline growth techniques or Czochralski (CZ) crystal growth techniques. In a second step 30, a tunnel oxide or gate oxide layer 330, is formed on the substrate 320. In a third step 40, a first semiconductor layer 340, preferably polysilicon, is formed on the gate oxide layer 330. Portions of first semiconductor layer 340 ultimately form the floating gate portion of the flash memory device. In a fourth step 50, an insulating layer 350, preferably Silicon Nitride, is formed on the first semiconductor layer 340. Known, conventional materials and methods may be used to form the gate oxide layer 330, the first semiconductor layer 340, and the insulating layer 350. With particular reference to FIGS. 1A and 3, in a fifth step 60, a portion of the insulating layer 350 is removed to expose a portion of an upper surface 342 of the first semiconductor layer 340. Preferably, the insulating layer 350 is removed by a conventional etching process, using a patterned photo resist layer 360, which forms an etch mask. After the portion of the insulating layer 350 has been removed in fifth step 60, the photo resist layer 360 is removed. Once etched, the remaining portion of the insulating layer 350 also forms an etch mask. With reference to FIG. 4, as well as continued reference to FIG. 1A, in a sixth step 70, a portion of the first semiconductor layer 340 is removed to expose a portion of the gate oxide layer 330. Preferably, the portion of the first semiconductor layer 340 is removed using conventional etching techniques well-known to persons of ordinary skill in the art of semiconductor manufacturing processes. With reference now to FIGS. 1B and 5, in a seventh step 80, using conventional techniques, ions are implanted in the substrate 320 to form at least one, and preferably a plurality of buried drains 370. With reference to FIGS. 1B, 5A, 6, and 7, in an eighth step 90, a buried drain oxide layer 380 is formed on top of the buried drains 370. Preferably, the buried drain oxide layer 380 is formed using conventional techniques such as high density plasma chemical vapor deposition. Following deposition, the buried drain oxide layer 380 covers both the buried drains 370 as well as remaining portions of the first semiconductor layer 340 and the insulating layer 350 (see FIG. 5A). With particular reference to FIG. 6, an upper portion of the buried drain oxide layer 380 is removed, preferably using conventional Chemical-Mechanical Polishing (CMP) techniques or etching back process, to form the buried drain oxide layer 380 into a set of discrete mesas, one mesa formed over each buried drain 370. Preferably, the CMP process removes the upper portion of the buried drain oxide layer 380 to a depth corresponding to an upper surface 352 of the insulating layer. The buried drain oxide layer 380 thus formed has an upper surface or top 382 extending above upper surface or top 342 of a remaining portion of the first semiconductor layer 340. In a preferred ninth step 100, the upper surface of the buried drain oxide layer 380 and the upper surface of a remainder of the insulating layer 350 are polished using conventional techniques, such as conventional CMP techniques to form a substantially planar surface. In a tenth step 110, the remainder of the insulating layer 350 is removed, preferably using conventional etching techniques, to expose the tops 342 of the remaining portion of the first semiconductor layer 340. Following tenth step 110, the first variation 10 a of the method 10 follows path 111 (see FIGS. 1B and 1C) to an eleventh step 130. With reference to FIGS. 1C and FIG. 8, in eleventh step 130, a semiconductor spacer layer 390 is formed. The semiconductor spacer layer 390 has a generally uniform thickness, and extends both on tops 382 and exposed sides of the buried drain oxide layer 380 and the tops 342 of the remaining portion of the first semiconductor layer 340. The semiconductor spacer layer 390 has an upper surface 394. Given the height differential between the tops 382 and the tops 342, and given the at least substantially uniform thickness of the semiconductor spacer layer 390, a plurality of recesses 392 are formed above the tops 342 of the remaining portion of the first semiconductor layer 340. Each recess 392 has a width W1 substantially equal to the spacing between adjacent buried drains 370 and also substantially equal to spacing between adjacent mesas of the buried drain oxide layer 380. With reference to FIG. 9 and continued reference to FIG. 1C, in a twelfth step 140, an oxide layer 400 is formed on top of the semiconductor spacer layer 390. The oxide layer 400 is provided with a thickness at least sufficient to fill each of the plurality of recesses 392. With reference to FIG. 10, in a thirteenth step 150, a portion of the oxide layer 400 formed on top of the semiconductor spacer layer 390 is removed to expose a portion (preferably upper surface 394) of the semiconductor spacer layer, but leaving a remaining portion 402 of the oxide layer within the plurality of recesses 392. The removal may be accomplished by various methods. In a preferred process incorporated into the first variation 10 a of the method 10, the step of removing of a portion of oxide layer 400 is accomplished using a conventional etching process 152. With reference to FIG. 11, in a fourteenth step 160, a portion of the semiconductor spacer layer 390 is removed to expose tops 382 of the buried drain oxide layer 380. A semiconductor spacer structure 398 a is thus formed, which acts as a conductive extension of the first semiconductor layer 340. Fourteenth step 160 may be performed using either a conventional wet etching process, or a conventional dry etching process. With reference to FIGS. 1C, 1D, and 12, subsequent to fourteenth step 160, the first variation 10 a of method 10 proceeds along path 161 to a fifteenth step 190. In this fifteenth step 190, the remainder of the oxide layer 400 and a portion of the buried drain oxide layer 380 are removed to expose a remainder of the semiconductor spacer layer 390 (semiconductor spacer structure 398 a) including an interior surface 396 of each of the plurality of recesses 392. In a preferred variation 190 a of fifteenth step 190, upper portions of the buried drain oxide layers 380 are removed to a depth sufficient to expose a portion of the first semiconductor layer 340. The gate coupling ratio obtained may be controlled by controlling the depth to which the buried drain oxide layer 380 is etched. That is, as more of the buried drain oxide layer is removed below the top 342 of the first semiconductor layer, more of the first semiconductor is exposed, increasing the contact area between the floating gate and the control gate, and thus increasing the gate coupling ratio. With continued reference to FIG. 1D and with reference also to FIG. 13, in a sixteenth step 200, an insulating stacked structure 410 is formed on the semiconductor spacer structure 398 a, exposed surfaces of the buried drain oxide layer 380, and exposed portions of first semiconductor layer 340. The insulating stacked structure 410 is preferably a structure conventionally known in the art as an “ONO” layer. The insulating stacked structure 410 is preferably formed using conventional materials and using conventional techniques well known in the art, and as the insulating stacked structure 410 is conventional, further description is unnecessary and is omitted for brevity. With continued reference to FIG. 13, in a seventeenth step 210, a second semiconductor layer 420 is formed on top of the insulating stacked structure 410. The second semiconductor layer 420 forms a control gate of the flash memory device 300. With continued reference to FIG. 13, the semiconductor spacer structure 398 a significantly increases the effective area in electrical communication between the floating gate (first semiconductor layer 340) and the control gate (second semiconductor layer 420), thus increasing the gate coupling ratio. With reference now to FIGS. 1A-1D, 14-16, and 26, a second variation 10 b of the method 10 includes first through eleventh steps 20-130 of the first variation 10 a. However, in the second variation 10 b, the eleventh step 130 follows path 131 to an eighteenth step 170. In eighteenth step 170, a dry, anisotropic etch process is used to remove a portion of the semiconductor spacer layer 390. As the process is anisotropic, as illustrated in FIG. 14, both tops 382 of the buried drain oxide layer 380 are exposed, as well as tops 342 of the first semiconductor layer 340. With reference to FIG. 15, in a nineteenth step 180, an upper portion of the buried drain oxide layer is removed, preferably to a depth sufficient to expose a portion of the first semiconductor layer 340. A semiconductor spacer structure 398 b comprising two sides but no base connecting the sides (in contrast to semiconductor spacer layer 398 a) is thus formed. As in fifteenth step 190, the gate coupling ratio may be controlled in part by controlling the depth to which the buried drain oxide layer 380 is etched. Finally, with reference to FIGS. 1D and 16, from nineteenth step 180, the process of the second variation 10 b proceeds along path 181 to the sixteenth and seventeenth steps 200, 210 of the first variation 10 a, thus producing a flash memory device 300 having an enhanced gate coupling ratio. With reference now to FIGS. 1A-1D, 17, 18, and 26, a third variation 10 c of the method 10 includes first through seventeenth steps 20-210 of the first variation 10 a. However, in the third variation 10 c, the thirteenth step 150 is performed using a conventional polishing process 154 to remove the portion of the oxide layer 400 formed on top of the semiconductor spacer layer 390 to a depth corresponding substantially to the top 394 of the semiconductor spacer layer 390, and leaving the remaining portion 402 of the oxide layer within the plurality of recesses 392. Subsequent to step 150 and process 154, the process of the third variation 10 c follows path 151 to step 160. Steps of the third variation 10 c subsequent to process 154 are the same as the fourteenth through seventeenth steps 160-210 of the first variation 10 a (including step 160 illustrated in FIG. 18). With reference now to FIGS. 1A-1D, 19, and 26, a fourth variation 10 d of the method 10 like the third variation 10 c also includes first through seventeenth steps 20-210 of the first variation 10 a. Similar to the third variation 10 c, in the fourth variation 10 d, the thirteenth step 150 is performed using a conventional polishing process 156 to remove the semiconductor spacer layer 390. However, the polishing process 156 is performed to a depth corresponding substantially to the tops 382 of the buried drain oxide layer 380. Subsequent to step 150 and process 156, the process of fourth variation 10 d follows path 158 to step 190. Steps of the fourth variation 10 d subsequent to process 156 are the same as the fifteenth through seventeenth steps 190-210 of the first variation 10 a. With reference now to FIGS. 1A-1D and 20-26, a fifth variation lOe of the method 10 includes first through tenth steps 20-110 of the first variation 10 a. However, the process of the fifth variation 10 e follows path 112 to a twentieth step 120. In twentieth step 120, an exterior surface of each of the mesas of the buried drain oxide layers 380 is removed, preferably by a native oxide removal process. The twentieth step 120 is followed by eleventh through seventeenth steps 130-210 to form the flash memory device 300, and FIGS. 21 through 25 reflect steps 140 (FIG. 21), 150 (FIG. 22, using process 152), 160 (FIG. 23), 190 (FIG. 24, using process 190 b), and steps 200 and 210 (FIG. 25). With particular reference to FIG. 23, following fourteenth step 160, the resulting semiconductor spacer structures 398 e each have a width W2. The width W2 is larger than the width W1 associated with first through fourth variations 10 a-10 d. A resulting spacer structure 398 e is larger, and has more surface area, than the spacer structure 398 a-398 d associated with the first through fourth variations 10 a-10 d, respectively. Owing to the twentieth step 120, the width W2 is larger than a width of the buried drain oxide layer mesa, and also larger than a spacing between adjacent buried drains 370. Thus, the semiconductor spacer structure 398 e is made wider (and the contact area between the semiconductor spacer structure 398 e (part of the floating gate) and the second semiconductor layer 420 (the control gate) is increased) without affecting spacing between adjacent buried drains 370. In the fifth variation 10 e, removal of the buried drain oxide layers in fifteenth step 190 is preferably performed using process 190 b, to etch the buried drain oxide layers to a depth less than upper surfaces 342 of the first semiconductor layer 340. FIG. 26 is provided to assist the reader in understanding the relationship among the variations 10 a-10 e of the method 10. A method of manufacturing a flash memory device is thus disclosed. The method of providing flash memory devices having enhanced gate coupling ratios providing greater processing flexibility and without requiring reduction of buried drain semiconductor space. It will be appreciated by those skilled in the art that changes could be made to the embodiment described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiment disclosed, but it is intended to cover modifications within the spirit and scope of the present invention. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8154071 *May 18, 2009Apr 10, 2012Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device and method for fabricating nonvolatile semiconductor memory device* Cited by examinerClassifications U.S. Classification438/257, 257/E21.682, 257/E21.209, 257/E27.103, 257/E29.3International ClassificationH01L21/336Cooperative ClassificationH01L27/11521, H01L27/115, H01L21/28273European ClassificationH01L21/28F, H01L27/115, H01L27/115F4Legal EventsDateCodeEventDescriptionMay 12, 2006ASAssignmentOwner name: MACRONIX INTERNATIONAL CO., LTD, TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, CHUN-PEI;LUO, TIAN-SHUAN;REEL/FRAME:017611/0588Effective date: 20060314Jun 26, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

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HHA Archery Optimizer Lite Ultra Ds-5019 Bow Sight RH DS-5019 716415990002 | eBay
See more HHA Sports Optimizer Lite Ultra 5000 .019 RH 3...
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Details about HHA Archery Optimizer Lite Ultra Ds-5019 Bow Sight RH DS-5019
HHA Archery Optimizer Lite Ultra Ds-5019 Bow Sight RH DS-5019
$54.91 (23% off)
HHA Archery Optimizer Lite Ultra Ds-Xl5019 Bow Sight RH DS-XL5019
HHA Archery Optimizer Lite Xl-5019 Bow Sight RH XL-5019
HHA Archery Optimizer Lite Ol-5510 Bow Sight RH OL-5510
HHA Archery Optimizer Lite Ol-5500 Bow Sight RH OL-5500
HHA Archery Optimizer Lite Xl-5510 Bow Sight RH XL-5510
HHA Archery Optimizer Lite Xl-5519 Bow Sight RH XL-5519
HHA Optimizer Lite King Pin 5519 RH Bow Sight .019 KP-5519
HHA Archery Optimizer Lite Speed Dial Cross Bow Sight Mount OL-SD
182508756189
Last updated on Feb 27, 2020 16:18:00 PST View all revisions
716415990002
Excellent transaction! Fast shipping thanks!
I ordered this rest to Okinawa Japan, got here faster than amazon prime
Great Bow, & very fast shipping Thanks !!
Exactly as described, great price, fast shipping, A+++++
A great item at a greater price fast shipping thank you. Rated AAA+++.
As advertised, shipping was a little slow
Definitely a Attt seller Thought the sight came with a harmonic damper but didnt
by foulk_chri Jan 16, 2019
Awesome single pin sight.
Excellent sight period! I sighted in at 20/40 yds and used the provided instructions to select the correct tape, lined it up and have been shooting arrows without flaw from 20 to 70 yds. I move around and range find the target, dial it in, and don't have to guess which "blurry" pin to use. At age 51 with my eyes not working like they did 20 years ago, the .019 pin is plenty visible. Now i have to pick different spots so i'm not busting the nocks off. built to last. Love it.
by wil_703632 Dec 10, 2019
Works great but lacks mounting instructions
The sight itself is great and works very well once it is dialed in. I like it much more than my old multi pin site. The only downside is there are minimal instructions that come with this sight and my old quiver did not work with this site and it seems that a special bracket is needed for any quiver to work. In my opinion, the bracket should come with the sight.
by pbrill7415 Aug 29, 2019
The sight is well made. Still working on sighting the bow in but excellent addition.
by learbear67 Sep 25, 2016
Very fast shipping,good quality bow sight
by bossdog359 Oct 11, 2017
love it works great and is easy to set up and use.
Verified purchase: Yes | Condition: new | Sold by: comerlend2017
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Nine Plays by EURIPIDES,: The Franklin Library Hardcover - AbeBooks.com
Home EURIPIDES, Nine Plays
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Quarto. full green leather pictorially decorated and lettered in gilt, spine with raised bands and gilt, all edges gilt, silk bookmark bound in, dark blue silk endpapers. Illustrated. Bookseller Inventory #
Book Condition: Fine. Like new
1. Nine Plays
Euripides (translators include Rex Warner, Richard Lattimore & others)
Published by Franklin Center: The Franklin Library (1976)
Book Description Franklin Center: The Franklin Library, 1976. Hardcover. Condition: Fine. No Jacket. Special Edition. Plays in this collection are: -Medea. -The Trojan Women. -Orestes. -Electra. -Iphigenia in Tauris. -The Bacchae. -Alcestis. -Hippolytus. -Heracles. Octavo bound in green, full leather with gilt lettering, borders & decorations; all edges gilt. 653 pages. Seller Inventory # 305344
2. Nine Plays
Book Description The Franklin Library, 1976. Leather Bound. Condition: Very Good. No Jacket. Limited Edition. Very Good condition, no DJ. Limited edition. No markings to the text block. No marks of personal identification or prior ownership. Ribbon marker present. All edges gilt but marred by spotting (common problem with lightly applied gilt). Otherwise this book could be classified as NEAR FINE (book never read, ribbon marker in original position). Seller Inventory # 43900
3. Nine Plays - Euripides - The Franklin Library - Quentin Fiore Illustrations - Limited Edition
Book Description Franklin Library. Hardcover. Condition: Very Good. A copy that has been read, but remains in excellent condition. Pages are intact and are not marred by notes or highlighting, but may contain a neat previous owner name. The spine remains undamaged. At ThriftBooks, our motto is: Read More, Spend Less. Seller Inventory # GB00EC8G3IYI4N00
4. Nine Plays - Euripides - The Franklin Library - Quentin Fiore Illustrations - Limited Edition
5. Nine Plays
Book Description The Franklin Library, Franklin Center, PA, 1976. Full-Leather. Condition: As New. Limited. No Dust Jacket, As Issued. 653 pp, Media; The Trojan Women; Orestes; Electra; Iphigenia in Tauris; The Bacchae; Alcestis; Hippolytus; Heracles. From the Complete Greek Tragedies, edited by Richmond Lattimore and David Greene. The 100 Greatest of All Time: Limited Edition, 1976. No Book Plate. Pristine, no wear. Clean, tight and strong binding with no other underlining, highlighting or marginalia. Green leather with gilt embossed decorative boards, raised bands on spine, gilt lettering to spine, gilt text block edges, black silk moire endpapers, and a black satin ribbon. Size: Large 8vo. Seller Inventory # 004256
6. Euripides Nine Plays
Book Description The Franklin Library, Franklin Center, Pa, 1976. Full-Leather. Condition: Fine. Book. Seller Inventory # 025181
7. Nine Plays
Book Description The Franklin Library, 1976. Hardcover. Condition: Near Fine. No Jacket. Limited Edition. Bound in premium full leather. Accented in 22kt gold. Gilt title and raised bands to spine with all page edges gilt. High-quality paper with gilded edges, ribbon marker, and silk moire endpapers. Limited Edition as stated on title page. Dent on top two raised bands on spine. Seller Inventory # 1507039
8. Nine Plays
Book Description Franklin Library, Franklin Center, Pennsylvania, 1976. Hardcover. Condition: Fine. Quentin Fiore (illustrator). Published exclusively for subscribers to the Franklin Library collection : The 100 Greatest Books of All Time. Bound in the publisher's original green composition leather, spine stamped in gilt. Four raised bands on the spine. Decorations stamped in gilt on the covers and spine. Silk moire end papers. Previous owners bookplate. Illustrated by Quentin Fiore. Seller Inventory # 9016518
9. Nine Plays - Euripides - The Franklin Library - Quentin Fiore Illustrations - Limited Edition
Book Description Franklin Library. Hardcover. Condition: New. B00EC8G3IY New book. Seller Inventory # V1-204
10. Euripides Nine Plays
Book Description The Franklin Library, Franklin Center, PA, 1976. Hardcover. Condition: VG. Quentin Fiore (illustrator). Limited. The book is green leather with gilt decorations and title. Complete with ribbon marker. Only defect to note is spotting along the edges of the end pages. Black and white illustrations. Greek tragedies translated by various persons. Seller Inventory # 008605

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Case management in aftercare of involuntarily committed patients with substance abuse. A randomized trial. - PubMed - NCBI
1 selected item: 22853707
Lindahl ML1, Berglund M, Tönnesen H.
Department of Health Sciences, Lund University, Lund, Sweden. marianne.larsson_lindahl@med.lu.se
Court-ordered patients with substance abuse ( n = 36) were randomly assigned to either strengths based case management or treatment-as-usual during 6 months in aftercare. Data was collected at intake, at conclusion of intervention and at 6 month's follow-up with a follow-up rate of 94%.
Case management may be useful in order to retain abstinence in aftercare following court-ordered treatment. The social welfare and hospital care systems seem to provide care irrespective of case manager intervention. The study design, interventions and assessments instruments were well received by patients but needs to be replicated with a larger population.
The 100% retention in the case management support group indicates that patients were satisfied with this type of intervention and the methodology seems to be useful in order to retain abstinence.

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text: Loading...SPOKANE, WA - JANUARY 10: Matthew Dellavedova #4 of the Saint Mary's Gaels drives against Kelly Olynyk #13 of the Gonzaga Bulldogs during the second half of the game at McCarthey Athletic Center on January 10, 2013 in Spokane, Washington. (Photo by William Mancebo/Getty Images)Back to galleryPhoto 16 of 18Previous | Next

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Avalanche (EP) - Wikipedia
EP by Echo & the Bunnymen
Ian McCulloch, Will Sergeant
(1999)Get in the Car1999
(2001)It's Alright2001
Avalanche is an EP that was released in October 2000 by Echo & the Bunnymen. The EP was released on CD by Gimme Music and was only available to buy on the internet.[1]
2.2 2003 reissue
The first track on the original EP is a cover version of American folk musician Tim Hardin's song "How Can We Hang On to a Dream?", with the title changed to "Hang on to a Dream". The second track, "Avalanche", was a new song by the band. The next three tracks ("All My Colours (Zimbo)", "Silver" and "Angels and Devils") are re-recordings of songs previously released by the band. The final track of the original EP is a cover of the Bob Dylan song "It's All Over Now, Baby Blue" with the title listed as "It's All Over Now".
In 2003 the EP was re-released with two bonus tracks: the first being the Electrafixion version of "Baseball Bill" and the second being a remixed version called "Baseball Bill (Sgt Fuzz Remix)".
"Hang on to a Dream" (Tim Hardin) – 2:26
"Avalanche" (Will Sergeant, Ian McCulloch) – 3:27
"All My Colours (Zimbo)" (Sergeant, McCulloch, Les Pattinson, Pete de Freitas) – 4:12
"Silver" (Sergeant, McCulloch, Pattinson, de Freitas) – 3:18
"Angels and Devils" (Sergeant, McCulloch, Pattinson, de Freitas) – 3:31
"It's All Over Now (Baby Blue)" (Bob Dylan) – 3:35
2003 reissue[edit]
"Baseball Bill (Electrafixion Version)" (Sergeant, McCulloch) – 4:43
"Baseball Bill (Sgt Fuzz Remix)" (Sergeant, McCulloch) – 4:35
Alex Gleave – bass
Vinnie Jamieson – drums
Tim Speed – engineer
Nick Allen – sleeve artwork
^ "The Ultimate Echo and the Bunnymen Discography". Villiers Terrace.com. Archived from the original on 15 May 2008. Retrieved 12 May 2008. "Echo & The Bunnymen – World Tour E.P.". Discogs.com. Retrieved 11 May 2008. v
Retrieved from "https://en.wikipedia.org/w/index.php?title=Avalanche_(EP)&oldid=789624014"	Categories: 2000 EPsEcho & the Bunnymen EPsHidden categories: Articles needing additional references from March 2016All articles needing additional referencesEngvarB from May 2014Use dmy dates from May 2014Articles with hAudio microformatsMusic infoboxes with deprecated parameters	Navigation menu
EspañolУкраїнська	Edit links	This page was last edited on 8 July 2017, at 13:45.

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In addition to an outdoor pool, Aliante Casino & Hotel provides a spa tub and a fitness center. Dining is available at one of the resort's 5 restaurants and guests can grab coffee at the coffee shop/café. A 24-hour business center is on site at this 4-star property. A computer station is located on site and high-speed wireless Internet access is complimentary. Event facilities measuring 14000 square feet (1260 square meters) include a conference center and conference space. This family-friendly resort also offers a casino, a nightclub, and an arcade/game room. Complimentary self parking and valet parking are available on site. Conference space size (meters) - 1260 Conference center Free valet parking Computer station Luggage storage 24-hour business center Conference space size (feet) - 14000 Coffee shop or café Free newspapers in lobby Arcade/game room Total number of rooms - 202 Number of floors - 9 ATM/banking Breakfast available (surcharge) Casino Conference space Dry cleaning/laundry service Elevator/lift Express check-in Express check-out Fitness facilities Gift shops or newsstand Free WiFi Multilingual staff Nightclub Porter/bellhop Number of restaurants - 5 Free self parking Shopping on site Spa tub Outdoor pool Wedding services Show all hotel amenities Family Friendly Amenities
An outdoor pool and a spa tub are on site. Other recreational amenities include a fitness center. The recreational activities listed below are available either on site or nearby; fees may apply. Golfing nearby Kayaking nearby Sailing nearby Water skiing nearby Rafting nearby Hiking/biking trails nearby Scooter/moped rentals nearby Mountain biking nearby Skydiving nearby Ecotours nearby Golf lessons available nearby Personal motorized watercraft on site Show recreation options Accessibility

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Landidyll Hotel Zum Alten Schloss, Kirchensittenbach - Restaurant Reviews, Phone Number & Photos - TripAdvisor
Landidyll Hotel Zum Alten Schloss, Kirchensittenbach
Europe Germany Bavaria Franconia Middle Franconia Kirchensittenbach Kirchensittenbach Restaurants Landidyll Hotel Zum Alten Schloss
#1 of 2 Restaurants in Kirchensittenbach $$ - $$$
Kleedorf 5, 91241 Kirchensittenbach, Bavaria, Germany+49 9151 8600Website
Also show MapSatellite Map updates are paused. Zoom in to see updated info. Reset zoom Updating Map... Return to Map Overview 4.5 12 reviewsExcellent51%Very good33%Average16%Poor0%Terrible0%Mar 22, 2016“Nice place with good food.”Apr 5, 2017“feine fränkische Küche!!!”Restaurant Hours + Add hoursPRICE $$ - $$$RATINGS ServiceFoodValueAtmosphereLOCATION Kleedorf 5, 91241 Kirchensittenbach, Bavaria, GermanyAll Details Improve This ListingIs this restaurant appropriate for Kids?Yes No Unsure Can a vegetarian person get a good meal at this restaurant?Yes No Unsure Are the prices at this restaurant mid-range / moderate?Yes No Unsure Is this restaurant good for brunch?Yes No Unsure Is this restaurant wheelchair accessible?Yes No Unsure Is this restaurant family-friendly?Yes No Unsure Can a gluten free person get a good meal at this restaurant?Yes No Unsure Is this restaurant good for breakfast?Yes No Unsure Can a vegan person get a good meal at this restaurant?Yes No Unsure Does this restaurant offer takeout or food to go?Yes No Unsure Thanks for helping! Share another experience before you go. Write a Review
Traveler rating Excellent6Very good4Average2Poor0Terrible0Traveler typeFamiliesCouplesSoloBusinessFriendsTime of year Mar-MayJun-AugSep-NovDec-FebLanguage All languages English (1)German (11)Language English (1)German (11)
Agnieszka B568Reviewed March 22, 2016 Nice place with good food.I was here together with my mom for Heilig Drei Konige Brunch. We eat here from 10 a.m. until 2 p.m., finishing with tasty dessert. As a welcome drink we get a glass of champagne, it was delicious. First round it was breakfast, swedish table...MoreThank Agnieszka B Wolfgang BWien, Österreich21248Reviewed April 5, 2017 feine fränkische Küche!!!Google Translation MoreThank Wolfgang B RB-135711Neuhaus an der Pegnitz, Germany5115Reviewed August 4, 2016 Gutes RestaurantGoogle Translation Thank RB-135711 Michael BRoßtal9647Reviewed June 4, 2016 Für große Gruppen sehr gut geeignetGoogle Translation MoreThank Michael B Wolfgang KMunich, Germany1615Reviewed April 18, 2016 Sehr gute KücheGoogle Translation Thank Wolfgang K Achim SSchwabach, Germany2712Reviewed March 28, 2016 Brunch - Essen gut, oft zu wenig, dauerte viel zu langeGoogle Translation More1 Thank Achim S RomanRoettingBad Bentheim, Germany271Reviewed February 25, 2016 Lecker essen zu fairem PreisGoogle Translation Thank RomanRoetting YvaggaWinnenden, Baden-Württemberg, Germany7222Reviewed February 14, 2016 A la carte Essen einfach nur klasseGoogle Translation More1 Thank Yvagga MBenzmuellerMulheim an der Mosel, Germany9836Reviewed October 9, 2015 Saisonal-Regional-PreiswertGoogle Translation MoreThank MBenzmueller brodbeckNuremberg, Germany401224Reviewed May 5, 2012 Nettes Ausflugslokal vor HersbruckGoogle Translation MoreThank brodbeck Previous
Updating list... Nearby Nearby RestaurantsGruner Schwan6 reviews 2.16 miles away Na Und!7 reviews 2.06 miles away Giacomucci Francesco18 reviews 2.06 miles away Nearby AttractionsFackelmann Therme Hersbruck34 reviews 1.76 miles away Industriemuseum Lauf8 reviews 7.73 miles away Burg Veldenstein7 reviews 7.95 miles away Frankisches Wunderland19 reviews 8.38 miles away Questions & AnswersGet quick answers from Landidyll Hotel Zum Alten Schloss staff and past visitors.Note: your question will be posted publicly on the Questions & Answers page.Posting guidelinesSubmitVerification: Improve this listing
Kleedorf 5, 91241 Kirchensittenbach, Bavaria, Germany Location:
> Kirchensittenbach
+49 9151 8600
E-mail This restaurant is at Landidyll Hotel Zum Alten Schloss

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text:
The present invention is generally directed to adhesive compositions comprising selected ratios of crystalline and amorphous polymers. In some versions of the invention, polymers capable of existing in different configurations (e.g., a polymer such as polypropylene which can exist in an atactic, syndiotactic....http://www.google.com/patents/US7786032?utm_source=gb-gplus-sharePatent US7786032 - Hot-melt adhesive based on blend of amorphous and crystalline polymers for multilayer bonding
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text:
Patent US5961344 - Cam-actuated terminal connector - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA connector for removably joining a plurality of electrical terminals to a flat cable. The connector has a housing containing two eccentric cams mounted on separate, parallel axes. The cams are spring biased to a closed position wherein the adjacent surfaces are relatively close together and are rotatable...http://www.google.com/patents/US5961344?utm_source=gb-gplus-sharePatent US5961344 - Cam-actuated terminal connectorAdvanced Patent SearchPublication numberUS5961344 APublication typeGrantApplication numberUS 08/920,016Publication dateOct 5, 1999Filing dateAug 26, 1997Priority dateAug 26, 1997Fee statusLapsedPublication number08920016, 920016, US 5961344 A, US 5961344A, US-A-5961344, US5961344 A, US5961344AInventorsMark Steven Rosales, William GronowiczOriginal AssigneeYazaki CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (13), Classifications (11), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetCam-actuated terminal connector
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3070771 *Aug 4, 1959Dec 25, 1962Gorn Electric Company IncPrinted tape cable connectorUS3576518 *Nov 7, 1968Apr 27, 1971Minnesota Mining & MfgSolderless connector for insulated wiresUS3579283 *Oct 4, 1968May 18, 1971Amp IncCam grip flat conductor connectorUS3824529 *Nov 28, 1972Jul 16, 1974Bunker RamoFlat cable connectorUS4743080 *Sep 25, 1986May 10, 1988G & H Technology, Inc.Flat cable connectorUS5470238 *Feb 9, 1994Nov 28, 1995Intercon Systems, Inc.Shielded ribbon cable electrical connector assembly and methodUS5735709 *Oct 2, 1995Apr 7, 1998Japan Aviation Electronics Industry LimitedZero insertion force connector for flexible circuit boards* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6079998 *Dec 29, 1998Jun 27, 2000Yazaki North America, Inc.Low insertion force connector with gear driven camsUS6210210 *Feb 17, 2000Apr 3, 2001Methode Electronics, Inc.Flat conductor termination deviceUS6312280 *Oct 10, 2000Nov 6, 2001General Motors CorporationFlexible circuit board connector having insulation removal mechanismUS6561554 *Jul 2, 2001May 13, 2003International Business Machines CorporationSimplified latch and associated assembly methodUS6733309Feb 27, 2003May 11, 2004Hirschmann Austria GmbhDevice for connecting electrical conductorsUS6976852 *Jul 13, 2004Dec 20, 2005Enplas CorporationSocket for electrical partsUS7081026Apr 2, 2004Jul 25, 2006Nicolay Verwaltungs-GmbhElectrical device connecting a line to an electrodeUS7150659 *Nov 12, 2004Dec 19, 2006Abb Research LtdMethod for electrically contacting a cable, cable connector and connector terminal blockUS7160293Aug 16, 2004Jan 9, 2007Sherwood Services AgMultiple RF return pad contact detection systemDE10028184A1 *Jun 9, 2000Mar 7, 2002Hirschmann Austria Gmbh RankweVorrichtung zum Verbindung von elektrischen LeiternDE10317286B3 *Apr 9, 2003Oct 7, 2004Nicolay Verwaltungs-GmbhVorrichtung zum elektrischen Verbinden einer Anschlu�leitung mit einer Elektrode, insbesondere einer medizintechnischen HautelektrodeEP1647234A1 *Oct 13, 2005Apr 19, 2006Sherwood Services AGUniversal contact port for an electrosurgical generatorWO2001061791A1 *Jan 12, 2001Aug 23, 2001Methode Electronics IncFlat conductor termination device* Cited by examinerClassifications U.S. Classification439/495International ClassificationH01R12/77, H01R12/61, H01R4/50, H01R13/585Cooperative ClassificationH01R13/585, H01R4/5008, H01R12/61, H01R12/774European ClassificationH01R12/61, H01R12/77D4Legal EventsDateCodeEventDescriptionNov 22, 2011FPExpired due to failure to pay maintenance feeEffective date: 20111005Oct 5, 2011LAPSLapse for failure to pay maintenance feesMay 9, 2011REMIMaintenance fee reminder mailedApr 4, 2007FPAYFee paymentYear of fee payment: 8Mar 12, 2003FPAYFee paymentYear of fee payment: 4Aug 26, 1997ASAssignmentOwner name: YAZAKI CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROSALES, MARK STEVEN;GRONOWICZ, WILLIAM;REEL/FRAME:008777/0897Effective date: 19970821RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text:
Amazon.co.uk: John Bradshaw - In Stock Only / Behaviour / Animal Sciences: Books Amazon Try Prime Your Amazon.co.uk Today's Deals Gift Cards Sell Help Shop by Department Hello. Sign in Your Account Try Prime Basket Wish List Search Animal Behaviour Science Animal Behaviour Science All Departments Amazon Instant Video Apps & Games Baby Beauty Books Car & Motorbike CDs & Vinyl Classical Clothing Computers & Accessories Digital Music DIY & Tools DVD & Blu-ray Electronics & Photo Garden & Outdoors Gift Cards Grocery Health & Personal Care Jewellery Kindle Store Kitchen & Home Large Appliances Lighting LOVEFiLM by Post Luggage Musical Instruments & DJ PC & Video Games Pet Supplies Shoes & Bags Software Sports & Outdoors Stationery & Office Supplies Toys & Games VHS Watches Books
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9780967460246: In the Shadow of the Mammoth - AbeBooks - Patricia Nikolina Clark: 0967460247
Patricia Nikolina Clark In the Shadow of the Mammoth
ISBN 13: 9780967460246
ISBN 10: 0967460247 ISBN 13: 9780967460246
Publisher: Blue Marlin Pubns, 2003
At eleven summers, Zol approaches manhood in his clan of Ice Age Hunters. He should be eager for his first mammoth hunt, but shameful fear gnaws at his insides like a hungry rat.
Fear of disgracing his brave father’s memory drives Zol to prove himself worthy of the Star Dancer clan. In his quest for courage, Zol barely escapes death in a raging river, stands face-to-face with a young mammoth, and survives two attacks by a long-toothed cat. Zol gains confidence from these encounters. But will his new-found courage stand the test of the mammoth hunt?
Patricia Nikolina Clark lives in Washington State with her husband, their energetic dog, and a cat named Stump.
Her passion for prehistory leads her to volunteer in archaeological excavations whenever possible. The idea for this book came during her participation in a dig that uncovered a cache of stone points dated to the Clovis period. She held in her hands a stone point once held by a Clovis hunter— 12,000 years ago! It was then that Zol tapped her on her shoulder and began whispering his story in her ear.
Patricia’s stories and articles have appeared in children’s magazines for many years Her easy-reader, Goodbye, Goose, was published in 2000. This is her first novel for children.
Grade 4-6-A tribe of people called the Star Dancers survive as hunters and gatherers in this novel set approximately 12,000 years ago. At 11 summers old, Zol lives in a small village with his mother, younger sister, and grandmother. Bad dreams and fears have plagued him ever since his father was killed while hunting mammoth several years earlier. He has been allowed to pursue his own interests, such as flint knapping, which is considered women's work, while other boys learn hunting skills. His troubles only increase when he rescues an injured baby crow and raises it as a pet. His grandmother believes that crows are evil and Zol's insistence on keeping it causes many arguments. Now, the age of manhood is fast approaching and Zol is expected to join the men on their next hunt. Although he almost drowns, has dangerous encounters with wild animals, and invents a new hunting tool, the plot moves along at a snail's pace and has no intensity. While Clark's research is meticulous and the setting and characterization are historically sound, the writing is dry, resulting in a mediocre read at best.
Karen T. Bilton, Somerset County Library, Bridgewater, NJ
ISBN 10: 096746028X ISBN 13: 9780967460284
Publisher: Blue Marlin Pubns, 2005
1. In the Shadow of the Mammoth (Paperback)
Book Description Blue Marlin Pubns, 2003. Paperback. Book Condition: New. Anthony Alex Letourneau (illustrator). Language: English . Brand New Book. Zol wants to be a great hunter like his father, who was killed on a mammoth hunt many years before, but is haunted by his belief that animals feel fear and pain, especially after he rescues and tames a young crow. Bookseller Inventory # FLT9780967460246
2. In the Shadow of the Mammoth (Paperback)
3. In the Shadow of the Mammoth
Book Description Blue Marlin Pubns, 2003. Paperback. Book Condition: New. Anthony Alex Letourneau (illustrator). book. Bookseller Inventory # M0967460247
4. In the Shadow of the Mammoth
Clark, Patricia Nikolina/ Letourneau, Anthony Alex (Illustrator)
Book Description Blue Marlin Pubns, 2003. Paperback. Book Condition: Brand New. 1st edition. 171 pages. 7.75x5.50x0.50 inches. In Stock. Bookseller Inventory # 0967460247
5. In the Shadow of the Mammoth
Book Description Blue Marlin Pubns, 2003. Paperback. Book Condition: New. Never used!. Bookseller Inventory # P110967460247
6. In the Shadow of the Mammoth
Book Description Blue Marlin Pubns. PAPERBACK. Book Condition: New. 0967460247 New Condition. Bookseller Inventory # NEW7.1491470


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Overall(304)Performance(263)Story(255)
Overall(1869)Performance(1737)Story(1738)
Overall(1082)Performance(1004)Story(998)
Over the decades, the reputation of the samurai has grown to mythical proportions, owing to such films as Akira Kurosawa's Seven Samurai and Yojimbo, as well as works such as James Clavell's epic Shogun. In Legends of the Samurai, Hiroaki Sato confronts both the history and the legend of the samurai, untangling the two to present an authentic picture of these legendary warriors. Through his masterful translations of original samurai tales, laws, dicta, reports, and arguments accompanied by insightful commentary, Sato chronicles the changing ethos of the Japanese warrior from the samurai's historical origins to his rise to political power. A fascinating look at Japanese history as seen through the evolution of the samurai, Legends of the Samurai stands as the ultimate authority on its subject. ©1995 Hiroaki Sato (P)2016 Gildan Media LLC

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Patent US4601699 - Implant device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA low cost implant device suitable for manufacture by high speed injection molding techniques is described. The implant device can be fabricated and assembled using only two parts, a plunger assembly and a plunger assembly housing. The plunger assembly housing is provided with a socket-like chamber for...http://www.google.com/patents/US4601699?utm_source=gb-gplus-sharePatent US4601699 - Implant deviceAdvanced Patent SearchPublication numberUS4601699 APublication typeGrantApplication numberUS 06/677,419Publication dateJul 22, 1986Filing dateDec 3, 1984Priority dateDec 3, 1984Fee statusPaidPublication number06677419, 677419, US 4601699 A, US 4601699A, US-A-4601699, US4601699 A, US4601699AInventorsKenny K. CrainOriginal AssigneeInternational Minerals & Chemical Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (15), Classifications (5), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetImplant deviceUS 4601699 AAbstract A low cost implant device suitable for manufacture by high speed injection molding techniques is described. The implant device can be fabricated and assembled using only two parts, a plunger assembly and a plunger assembly housing. The plunger assembly housing is provided with a socket-like chamber for receiving a disposable flanged cartridge containing a solid medicament in pellet form. The cartridge also can be made by injection molding. The device is used for subcutaneously implanting the solid pellet medicament in an animal.
I claim: 1. A device for subcutaneously implanting a solid pellet in an animal comprising in combination(1) a molded plunger assembly housing of unitary construction, said housing including(a) a first tubular section with an enlarged bore having(i) a user-proximal rear end opening with substantially the same cross section as said enlarged bore and (ii) an ejector rod guide positioned near the user-distal front end, and (b) a second tubular section with a reduced bore coupled to the user-distal front end of said first tubular section; (2) a hollow needle embedded permanently in said second tubular section; (3) a plunger assembly axially slideable in said housing, said assembly including(a) a molded user-actuated plunger of unitary construction dimensioned for slideable movement in said enlarged bore, extending through the opening at the user-proximal rear end of said first tubular section, and (b) an ejector rod dimensioned for slideable movement in said hollow needle and embedded permanently in the user-distal front end of said plunger, said ejector rod having a length sufficient to extend into the ejector rod guide when the plunger assembly is in its rear-most position and to extend through the hollow needle when the plunger assembly is in its forward-most position, and (4) a socket-like cartridge receiving chamber positioned at the user-distal front end of said first tubular section and extending into said second tubular section having a flange receiving portion and a tubular receiving portion for retaining a flanged, solid pellet-containing cartridge. 2. A flanged, solid pellet-containing cartridge comprising a planar section with a substantially perpendicularly aligned tubular section extending outwardly therefrom, said tubular section having a sufficient cross-section to contain a solid pellet medicament, said planar section having an opening through which a pellet can be inserted into the tubular section and means for sealing said opening, the planar section constituting a flange for said tubular section and having a taper which terminates with a locking means, said taper facilitating insertion of the cartridge into an implant device of the type including(1) a molded plunger assembly housing of unitary construction, said housing including(a) a first tubular section with an enlarged bore having(i) a user-proximal rear end opening with substantially the same cross section as said enlarged bore and (ii) an ejector rod guide positioned near the user-distal front end, and (b) a second tubular section with a reduced bore coupled to the user-distal front end of said first tubular section; (2) a hollow needle embedded permanently in said second tubular section; (3) a plunger assembly axially slideable in said housing, said assembly including(a) a molded user-actuated plunger of unitary construction dimensioned for slideable movement in said enlarged bore, extending through the opening at the user-proximal rear end of said first tubular section, and (b) an ejector rod dimensioned for slideable movement in said hollow needle and embedded permannently in the user-distal front end of said plunger, said ejector rod having a length sufficient to extend into the ejector rod guide when the plunger assembly is in its rear-most position and to extend through the hollow needle when the plunger assembly is in its forward-most position, and (4) a socket-like cartridge receiving chamber positioned at the user-distal front end of said first tubular section and extending into said second tubular section having a flange receiving portion and a tubular receiving portion. 3. The device of claim 1 wherein said molded housing is fabricated from a plastic material selected from the group consisting of nylon, polycarbonate, polyethylene, and polypropylene.
SUMMARY OF THE INVENTION The present invention pertains to a device for subcutaneously implanting a solid pellet in an animal comprising in combination
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of the present invention showing the plunger assembly housing.
DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a device resembling a hypodermic syringe for subcutaneously implanting a solid pellet medicament, such as an anabolic agent, a hormone, an antibiotic and the like in an animal. In accordance with this invention, the solid pellet is contained in a disposable, flanged cartridge. If desired the cartridge can be made resistant to tampering. This cartridge is inserted into an appropriately shaped socket-like chamber in the implant device and the pellet is ejected from the device by manipulating an appropriately configured plunger assembly.
In use, a flanged, solid pellet-containing cartridge having the illustrated design is inserted into the socket-like cartridge receiving chamber 27 and locked into position by forcing fingers 55 and 56 through the opening 26 in the connecting web 22 of collar 18. The cartridge contains a single dose of a solid, pelleted medicament such as RALGRO�, zeranol anabolic agent available from International Minerals and Chemical Corp. Upon placing the index finger and second finger about the handle 30 and the thumb on the plate 42 of plunger assembly 35, the needle 19 is inserted beneath the animal's skin and the user may manipulate the ejector rod 41 with the thumb so as to pierce the foil membrane of the cartridge and force the solid pellet through the hollow needle 19 and into the tissue of the animal.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS2502909 *Mar 12, 1947Apr 4, 1950Edward D CampbellPellet injectorUS2601852 *May 19, 1950Jul 1, 1952Wendt Delbert ODevice for dispensing tablets and the likeUS3016895 *Aug 1, 1958Jan 16, 1962Pan American Lab IncInjector for subcutaneous implantation of solidsUS3744493 *Jan 10, 1972Jul 10, 1973Syntex CorpImplanter having an improved cartridge ejectorUS4086914 *Feb 11, 1977May 2, 1978Edwin Bailey MooreImplant injectorUS4473369 *Jan 11, 1982Sep 25, 1984Baxter Travenol Laboratories, Inc.Continuous ambulatory peritoneal dialysis clamping systemUS4531938 *Jul 6, 1983Jul 30, 1985Ivy-Gene Co., Inc.Medicament implant applicator* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4941874 *Aug 9, 1988Jul 17, 1990Hoechst AktiengesellschaftDevice for the administration of implantsUS4954124 *Jan 30, 1989Sep 4, 1990The Dow Chemical CompanyStand-up plastic bag and method of making sameUS5484403 *Apr 5, 1994Jan 16, 1996Avid Marketing, Inc.Hypodermic syringe for implanting solid objectsUS5558637 *Sep 20, 1994Sep 24, 1996Leiras OyImplant injection deviceUS5827293 *May 13, 1996Oct 27, 1998Elliott; James B.Subcutaneous insertion deviceUS5908404 *Mar 3, 1998Jun 1, 1999Elliott; James B.Methods for inserting an implantUS6458070 *Dec 21, 1999Oct 1, 2002Novoste CorporationMethod and apparatus for treating a desired area in the vascular system of a patientUS6530896Jul 24, 2000Mar 11, 2003James B. ElliottApparatus and method for introducing an implantUS6648849Jun 27, 2001Nov 18, 2003Ethicon, Inc.Medicinal implant and device and method for loading and delivering implants containing drugs and cellsUS7066872Apr 11, 2003Jun 27, 2006Best Vascular, Inc.Method and apparatus for treating a desired area in the vascular system of a patientUS7160238Dec 21, 1999Jan 9, 2007Best Vascular, Inc.Method and apparatus for treating a desired area in the vascular system of a patientEP1281416A2 *Jun 26, 2002Feb 5, 2003Ethicon, Inc.Medicinal implant, device and method for loading and delivering implants containing drugs and cellsEP2525909A1 *Jan 21, 2011Nov 28, 2012Promega CorporationConsumable analytical plasticware comprising high-solubility plasticsWO1995010314A1 *Sep 16, 1994Apr 20, 1995Hannu AllonenImplant injection deviceWO2013148447A1 *Mar 21, 2013Oct 3, 2013Warsaw Orthopedic, Inc.Drug delivery system* Cited by examinerClassifications U.S. Classification604/64, 604/60International ClassificationA61M31/00Cooperative ClassificationA61M37/0069European ClassificationA61M37/00PLegal EventsDateCodeEventDescriptionJan 21, 1998FPAYFee paymentYear of fee payment: 12Jan 12, 1998ASAssignmentOwner name: SCHERING-PLOUGH ANIMAL HEALTH CORPORATION, NEW JERFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MALLINCKRODT, INC.;REEL/FRAME:008886/0806Effective date: 19970629Jan 14, 1994FPAYFee paymentYear of fee payment: 8Nov 3, 1989FPAYFee paymentYear of fee payment: 4Apr 28, 1987CCCertificate of correctionDec 3, 1984ASAssignmentOwner name: INTERNATIONAL MINERALS & CHEMICAL CORPORATION, AFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:CRAIN, KENNY K.;REEL/FRAME:004341/0139Effective date: 19841129RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


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