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Patent US6708256 - Memory-to-memory copy and compare/exchange instructions to support non ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not...http://www.google.com/patents/US6708256?utm_source=gb-gplus-sharePatent US6708256 - Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemesAdvanced Patent SearchPublication numberUS6708256 B2Publication typeGrantApplication numberUS 10/230,288Publication dateMar 16, 2004Filing dateAug 29, 2002Priority dateDec 15, 2000Fee statusPaidAlso published asUS6502170, US6665783, US20020078307, US20030009636, US20030182515Publication number10230288, 230288, US 6708256 B2, US 6708256B2, US-B2-6708256, US6708256 B2, US6708256B2InventorsAchmed Rumi ZahirOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (3), Non-Patent Citations (8), Referenced by (3), Classifications (13), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMemory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemesUS 6708256 B2Abstract A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location. Subsequently, the thread may read atomically a current copy of a version stamp from a target address, compare it to a version of the same version stamp obtained earlier, and, if the two version stamps agree, write the source data to the target address.
We claim: 1. A method of implementing an atomic memory-to-memory copy of data, comprising:
atomically reading data to a thread from a source location, and atomically writing the data from a thread to a target location, wherein cache coherent operations may occur between the reading and the writing. 2. The method of claim 1, wherein the reading and writing respectively transfer a quantity of data larger than an internal register of the thread.
3. The method of claim 1, wherein the reading and writing respectively transfer a quantity of data up to a cache line of a computer system in which the thread is located.
4. The method of claim 1, wherein the reading is directed to a predetermined address in a system memory, a first portion of the address representing a cache line from which the data is to be read and a second portion of the address representing a location within the cache line where a version stamp is located.
5. The method of claim 4, wherein, in a system having aligned cache lines of L bytes in length, the second address portion is log2(L) in length.
6. The method of claim 4, wherein a length of the version stamp is defined by an instruction used by software to invoke the method.
7. The method of claim 1, wherein the atomic reading operation and the atomic writing operation are performed pursuant to execution of a single memory-to-memory copy instruction.
prior to the reading, storing a first version stamp associated with the data, subsequent to the reading, determining a second version stamp associated with the data, and comparing the first and second version stamps, and if the version stamps do not match, repeating the method. 9. A method of implementing an atomic memory-to-memory copy of data, comprising:
atomically reading data from a source location to a thread, and atomically: acquiring exclusive ownership of a target location, and writing the data to the target location, wherein the atomic reading operation and the atomic acquisition-and-writing operation may be interrupted by cache coherent operations. 10. The method of claim 9, wherein the reading and writing respectively transfer a quantity of data larger than an internal register of the thread.
11. The method of claim 9, wherein the reading and writing respectively transfer a quantity of data up to a cache line of a computer system in which the thread is located.
12. The method of claim 9, wherein the reading is directed to a predetermined address in a system memory, a first portion of the address representing a cache line from which the data is to be read and a second portion of the address representing a location within the cache line where a version stamp is located.
13. The method of claim 12, wherein a length of the version stamp is defined by an instruction used by software to invoke the method.
14. The method of claim 12, wherein, in a system having aligned cache lines of L bytes in length, the second portion is log2(L) in length.
15. The method of claim 9, wherein the atomic reading operation and the atomic acquisition-and-writing operation are performed pursuant to execution of a single memory-to-memory copy instruction.
16. The method of claim 15, further comprising, upon conclusion of the instruction, determining a version number of the data.
17. The method of claim 9, wherein the atomic reading operation and the atomic acquisition-and-writing operation respectively read the data to and write the data from a processor.
prior to the reading, storing a first version stamp associated with the data, subsequent to the reading, determining a second version stamp associated with the data, and comparing the first and second version stamps, and if the version stamps do not match, repeating the method. 19. The method of claim 9, further comprising:
prior to the reading, storing a first version stamp associated with the data, subsequent to the reading, determining a second version stamp associated with the data, and comparing the first and second version stamps, and if the version stamps do not match, incrementing a counter, and if the counter exceeds a predetermined value, locking the source location and copying the data from the source location to the target location while the source location is continuously locked. 20. A data transfer method, comprising:
copying an array of data from a first space in a memory to a second space in a memory, the copying comprising, for each location in the first space: locking the location in the first space, reading a data unit from the location in the first space to a thread, releasing the lock when the reading concludes, and writing the data unit to a location in the second space; wherein, for each location in the first space, other threads are permitted access to the location between the respective reading and writing operations performed on the data unit associated therewith. 21. The data transfer method of claim 20, further comprising:
prior to each reading, storing a first version stamp associated with the data unit corresponding thereto, subsequent to the reading, determining a second version stamp associated with the corresponding data unit, and comparing the first and second version stamps, and if the version stamps do not match, repeating the copying with respect to the corresponding data unit. 22. The data transfer method of claim 21, wherein the array includes a single version stamp.
23. The data transfer method of claim 21, wherein each data unit includes a version stamp.
IN RELATED APPLICATIONS This patent application is a divisional application of U.S. application Ser. No. 09/736,433, filed Dec. 15, 2000, U.S. Pat. No. 6,502,170 is incorporated herein by reference and may benefit from the priority thereof.
BACKGROUND The present invention relates to instruction support for memory-to-memory atomic copy and memory-to-memory compare/exchange instructions in a multiprocessor computer system. More particularly, for threads employing non-blocking synchronization schemes, the instruction support reduces the time in which processors (and hence applications) are subject to memory access lockouts (spin-locks).
The Pentium Pro� processor, commercially available from Intel Corporation of Santa Clara, Calif., provides support for several register-to-memory instructions: loads, stores and compare-and-exchange. The load and store instructions transfer data from registers within the processor to a public memory location or vice versa. The compare and exchange operation compares a value stored in a target address with a value stored in a predetermined pair of registers and, if they are equal, writes the value from a second register pair to the target address. In the Pentium Pro� processor, registers are 32 bits wide; the largest increment of data to be transferred atomically according to these instructions is 64-bits (using the double-word compare-exchange instruction).
The copy (load/store) and compare-and-exchange instructions provide tools for software designers to manage data structures. Of course, software designers routinely manage data structures that are much greater than the size of a single 32-bit register or even a collection of registers. To extend the set of atomic instructions to data sizes that are much larger than a register width, that approach the size of a processor's cache line, the instructions become memory-to-memory data transfers rather than register-to-memory transfers. An instruction requires access to a source address in memory and to a target address in memory. By gaining access to two addresses during the course of program execution, particularly in multi-threaded environments, extension of the copy and compare-and-exchange instruction raises a risk that blocking may occur among parallel threads.
A multi-processor computer system (even a uniprocessor computer system) may include a plurality of �threads,� each of which executes program instructions independently from other threads in the system. Multiple agents in a system each are independent threads in the system. Additionally, as is known, resources of a single processor may be shared among several execution processes that are independent from each other. Although the processes execute on a single processor, they may be considered separate threads because their execution is independent from each other much in the same way that execution among two or more processors may be independent from each other. Herein, we use the term �thread� to refer to any logically independent processing agent, regardless of whether the threads are distributed over a single processor (time-multiplexed threading) or multiple processors (space-multiplexed threading) in a computing system.
Blocking may occur when two or more threads attempt to gain ownership of a single data element. Typically, threads engage in administrative protocols to synchronize with each other and to ensure that they use the most current copy of data available to the system. One coherency technique involves locks that are applied to data by a thread while the thread uses the data. If a thread were required to update a data structure, for example, the thread typically must acquire a lock, perform the data update and then release the acquired lock. Other threads that required access to the same data structure would be denied access so long as the lock were applied. The lock renders the first thread's data update operations �atomic� because no other thread can gain access to the locked data until the data structure is completely updated. These locks can lead to significant performance bottlenecks because (1) threads waiting for access to the locked data structure waste CPU cycles until the lock becomes available, and, more importantly (2) threads holding a lock can be interrupted by other processes by a long-latency operation (e.g. due to a page fault or a interval-timer interrupt�often in the millisecond range). In this circumstance, a first thread that acquired a lock would not make forward progress because it was interrupted and another thread requiring access to the locked data structure also could not make forward progress because it was denied access (because the interrupted thread holds the sought after lock). Both threads, the one holding the lock and the one seeking the lock, fail to make progress even though the data structure is not actively being used.
Non-blocking synchronization (�NBS�) programming techniques also provide data coherency guarantees but they permit multiple threads to read and update data simultaneously. NBS techniques assign version stamps to data elements. When a thread operates on data, the thread may read a new version stamp from memory and compare it to an older copy of the version stamp that the thread read prior to its data operation. If the two version stamps are identical, the thread can confirm that the results of its data operation are valid. If not, the data element is assumed to have been updated while the data operations were in progress; the thread typically re-reads the data, the version stamps and retries the data operation.
No known processor provides atomic copy or compare-and-exchange instruction support for larger-than-register-size memory-to-memory transfers. No known processor provides such instruction support in the context of an NBS scheme. Accordingly, there is a need in the art for instruction support for memory-to-memory copy and compare-and-exchange instructions that operate on data sizes that approach a cache line size in a processor.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a multiprocessor computer system suitable for use with embodiments of the present invention.
FIG. 2 is a simplified block diagram of a processor suitable for use with the present invention.
FIG. 3 illustrates a method of operation for a memory-to-memory copy instruction according to an embodiment of the present invention.
FIG. 4 illustrates a method of operation for a memory-to-memory compare and exchange instruction according to an embodiment of the present invention.
FIG. 5 illustrates a usage model for the memory-to-memory copy instruction of FIG. 3 according to an embodiment of the present invention.
FIG. 6 illustrates a usage model for the memory-to-memory compare and exchange instruction of FIG. 4 according to an embodiment of the present invention.
DETAILED DESCRIPTION Embodiments of the present invention provide a coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. In a copy instruction, reads and writes are each atomic but the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread copies data pursuant, it may permit other threads to access or update the data. The data may include a version stamp. After the first thread operates on the copy of the data, it must re-read in the version stamp a second time to validate that the result computed based on the copy of the data is still meaningful. If the two version stamps agree, the results of the thread's operation may be considered valid.
For a compare and exchange operation, a thread may read data and operate upon it. Subsequently, the thread may atomically (1) read a current copy of a version stamp from a target address, (2) compare it to an older version of the same version stamp, and, (3) if the two version stamps agree, write new data to the target address.
FIG. 1 is a block diagram of a multiprocessor computer system 100 suitable for use with embodiments of the present invention. The system may include a plurality of agents 110-160 interconnected via a common communication bus 170. An �agent� includes any processing entity that communicates via the bus 170; agents may include processors 110-140, memories and memory controllers (collectively shown as �memory�) 150, bridge interfaces 160, digital signal processors or application-specific integrated circuits (not shown). As described above, the agents may be divided logically into a plurality of threads. A modern computer system 100 may include several clusters 180, 280 of processors interconnected via a network fabric 190. FIG. 1 illustrates two exemplary clusters 180, 280; there may be more. The second cluster 280 is shown as including a plurality of processors 210-240, a system memory 250 and a bridge interface 260 interconnected via a common communication bus 270. This architecture also is merely illustrative; clusters 180, 280 need not be provisioned identically to one another in a distributed processing system.
In such a system, the system memories 150, 250 of the system 100 define a universal, shared cache-coherent memory space. It is possible that, during operation, an agent 110 from one cluster 180 will operate upon data stored in the memory 250 of another cluster 280. Of course, read and write operations from one agent (say, 110) to memory 250 in another cluster 280 may traverse the network fabric 190 which may impose a much longer (and possibly unpredictable) latency to the operation than would a similar operation directed to local memory 150. For the purposes of this discussion, the operation of the various clusters and threads is not material to the operation of the present embodiments. It is sufficient to note that the system 100 defines a shared, coherent memory space in which data is stored for use by all the threads. In this regard, the operation of the system 100 is well known.
According to an embodiment, a thread may have access to a private memory space. The private memory space may be provided in the thread's internal cache hierarchy (not shown in FIG. 1). Alternatively, it may be provided by a portion of the universal memory space 150, 250 that is not used by the other threads. Such segregation of the universal memory space may be established as a conventional software-controllable parameter of system operation.
FIG. 2 is a simplified block diagram of functional units within an agent 300 suitable for use with the embodiments described herein. The agent 300 may include a processor core 310, a cache hierarchy 320 and a bus interface unit 330. These entities may overlap to a degree; in the example shown in FIG. 2, an L0 cache 390 is shown as a member both of the core 310 and the cache hierarchy 320. The core 310 may include the L0 cache 340 and a core execution unit 350. One or more registers 360 may be provided within the core execution unit 350. These registers may have a predetermined width W, for example, 16, 32 or 64 bits.
The cache hierarchy 320 may include one or more layers of cache. In the example shown in FIG. 2, three layers of cache are shown, the L0 cache 340, an L1 cache 370 and an L2 cache 380. Typically, lower level caches such as the L0 cache are smaller and faster than the caches at the higher levels, such as the L2 cache. In the higher level caches, such as the L2, cache lines may have a width L that relates to the largest increment of data that may be transferred pursuant to a single transaction on the external bus. For example, cache lines in the Pentium Pro� processor are 64 bytes while the register widths are 32 bits. The middle level and lower level caches (L0 and L1) may but need not be organized into cache line sized entries.
The bus interface unit 340 interfaces the other functional units with the external bus 390. In this regard, the structure and operation of an agent is well known.
FIG. 3 illustrates a method of operation 1000 for a memory-to-memory copy instruction according to an embodiment of the present invention, to copy a value from a source address in the shared memory to a target address in the shared memory. The method may begin by atomically reading data from the source address to a non-snooped buffer of the thread (box 1010). It concludes by atomically writing the data from the non-snooped buffer to the target address (box 1020). The read and write operations are both atomic individually, Indeed, between the atomic read and atomic write operations, automatically need not be maintained throughout the entirety of the method 1000. Other threads may perform cache coherent operations to data either at the source address or at the target address (represented by box 1030). Optionally, at the conclusion of the atomic write 1020, the thread may return a version stamp of the source data to the software level (box 1040).
The method of FIG. 3 is useful because it avoids certain deadlock events that can occur in multiprocessor systems if the memory-to-memory COPY operation were to require ownership of both the source and the target cache lines. One such deadlock event can occur when a first thread attempts to perform an operation COPY [B]=[A] while a second thread attempts to perform a COPY [A]=[B] and both instructions are atomic. In this situation, a first thread reads the source address B and acquires its ownership. The second thread acquires ownership of the source address A before the first thread can access it. Having read the source addresses, the two threads attempt to gain exclusive ownership of their respective target addresses (to write to the target addresses). However, because each thread locked the other thread's target and because each thread's instructions are atomic, neither thread can complete its operation. They deadlock.
If the same event were to occur in a system operating in accordance with the present embodiments, no such deadlock would occur. For the COPY [B]=[A] instruction, the first thread (say, 110) would read the data atomically from address A in the shared memory to a non-snooped buffer. The read portion of the COPY operation is atomic; ownership of address A cannot be released until the read completes. Once the atomic read portion of the COPY operation completes, however, the ownership of address A is released. At the same time, the second thread (say, 120) may read the data from address B in the shared memory to its own non-snooped buffer. Again, the operation is atomic; until the second thread completes the read of address B, no other thread can acquire ownership of address B. When each thread attempts to write to the target addresses, the target addresses are only owned exclusively for the duration of the write portion of the COPY operation (that stores data from the non-snooped buffer to the target address). The threads can complete their write operations. No deadlock occurs.
FIG. 4 illustrates a method of operation 1100 for a memory-to-memory compare-and-exchange instruction according to an embodiment of the present invention. Before the operation begins, an �old� version stamp may be stored internally within a register of a thread. The version stamp may have been obtained by the thread during operation of prior instructions; it is an �old version stamp.� Also, prior to operation of the instruction a private source address stores data to be written to the target address. The source address also stores a new version stamp to be written to the target address.
Operation for the compare-and-exchange instruction may begin with an atomic read of data from the source address to a non-snooped buffer of the thread (box 1110). Thereafter, the thread may read a copy of the version stamp currently stored at the target address (the �current version stamp�) (box 1120). The thread may compare the old version and determine whether they agree (boxes 1130-1140). If so, the thread may write the non-snooped buffer (which holds the source data) to the target address (box 1150). Both the data and the new version stamp may be stored at the target address. Thereafter, or if the version stamps do not agree, the thread may return the current version stamp to the software level (box 1160).
In an embodiment, the sequence of operations represented by boxes 1120-1160 may be atomic. They cannot be interrupted by other cache coherent operations to the target address performed by another thread. Of course, cache coherent operations from other threads (represented by box 1170) are permissible between the atomic read of the source data, box 1110, and the atomic sequence of boxes 1120-1160. Thus, exclusive ownership of the target address is ensured. No other thread may gain access to the target address until the conditional update portion of the memory-to-memory compare-and-exchange instruction is completed (or aborted if the version numbers mismatch).
Because the compare and exchange operation 1100 may be performed as a pair of discrete atomic operations rather a single atomic sequence of operations, the operation 1000 avoids the deadlock events that plague other schemes. While the read of data (box 1110) may cause the source address to be owned by a single thread, the thread's ownership may be released once the read completes. Similarly, the operations of boxes 1120-1160 may cause a target address to be exclusively owned by a single thread but only until the write, if one occurs, is completed. The method of FIG. 4 prevents deadlock from occurring because the source address and target address are not required to be owned concurrently by the thread executing the instruction. This significantly simplifies use, silicon design and validation of these operations.
According to an embodiment, rather than passing the current version stamp back to the software at box 1160, the thread simply may generate a flag indicating whether the version stamps agreed at box 1140 or not.
Because the foregoing embodiments are memory-to-memory operations, the data transfers caused by the copy and the compare-and-exchange operations may exceed size restrictions that otherwise would exist if the instructions were register-to-memory operations. Accordingly, the instructions may cause a much larger data transfer to atomically occur in single instruction. In an embodiment, the instructions may operate on any element of data up to the size of a cache line. Cache lines in the Pentium Pro� processor are 64 bytes. Thus, the foregoing embodiments, if applied to the Pentium Pro� processor, could yield an eight-fold increase over instructions presently used. Of course, the principles of the foregoing embodiments may be applied to other processors having larger cache line sizes (e.g., 128, 256 or more bytes). According to an embodiment, the version stamp may be provided in an arbitrary location within each cache line. The location of the version stamps within a cache line may be determined by software developers (those who use the instructions), and identified as a software controllable parameter to the instruction itself. As is known, system memories 150, 250 may be organized as a regular array of cache lines of data. However, memory addresses typically identify data locations at granularities smaller than a cache line. Thus a memory address may be considered to include two fields: a cache-line address, typically represented by the most significant bits of the address, and an offset into the cache line, represented by lesser significant bits of the address. Although embodiments of the memory-to-memory copy and the memory-to-memory compare-and-exchange instructions may deal in cache-line sized reads or writes of data, the offset field may be used advantageously to identify a location of the version stamp within the cache line. The thread may interpret the offset field to identify a location of data to use as the version stamp.
According to an embodiment, addressing may be applied to a system having any predetermined cache line length. As described above, the Pentium Pro� processor operates using a cache line length of 64 bytes; other systems may operate on cache lines of a different length. Typically, addresses used for shared memory transactions are aligned to the cache line lengths (to avoid false sharing). In a system having a cache line length of L bytes, then the lower log2(L) bits of an address have no bearing on which cache line is addressed. These lower log2(L) may be used as the offset field to determine the location of the version stamp within the addressed cache line. According to an embodiment, a version stamp may be sized to be a one, two, four or eight bytes, or any size up to the size W of the thread's internal registers.
According to an embodiment, a version stamp may have a predetermined length (in bytes). Alternatively, the length of a version stamp may vary as a software controllable parameter. Syntax may be provided for the copy and compare-and-exchange instructions to define a length of the version stamp. In such an embodiment, data manipulations (transfers, comparisons) directed to a version stamp may be made in data sizes defined by the version stamp length parameter of the instruction.
The instructions presented in the foregoing embodiments may find application for data sizes on the order of a system's cache line. They, however, may contribute to data management operations for data structures of larger sizes. FIG. 5 illustrates a usage model 1200 for an atomic lookup operation for a data structure according to an embodiment of the present invention. The usage model shown in FIG. 5 may operate at a software level whereas the copy instruction on which it is based may operate at the hardware level of the thread.
According to the embodiment, a thread may atomically copy a version stamp and a data element of the data structure (box 1210); this first copy of the version stamp is the �old� version. The element may be copied in conjunction with the version stamp. The thread may perform any operations as dictated by software that may be required by the lookup operation (box 1220). When the lookup data operations are complete, the thread may atomically read another copy of version stamp, called the �current version stamp� (box 1230). The thread may compare the old and current version stamps to determine whether they agree (box 1240). If they agree, then the results of the data operations are valid (box 1250); the software may propagate the results computed by box 1230 to other stages.
If the version stamps do not agree, it could indicate that the data structure was altered by another thread while the first thread performed the data operations in box 1220. The results obtained from those data operations could be invalid. Accordingly, if the version stamps do not agree, the thread may retry the method 1200 by returning to box 1210.
In an alternate embodiment, shown in FIG. 5 in phantom, the thread may maintain a counter of the number of unsuccessful retry attempts. If the old and current version stamps repeatedly do not agree at box 1250, the thread may increment a counter and determine whether the counter exceeds a predetermined threshold (boxes 1260-1270). If the threshold is exceeded, the thread may retry the data operations using a traditional lock variable (semaphore) that remains asserted throughout the data operations' duration (box 1280). Otherwise, if the threshold is not exceeded, the thread may reiterate the operations of boxes 1210-1240.
In another embodiment, rather than advance to static lock at box 1290, the software may impose a random or exponentially increasing back-off delay before re-attempting the procedure starting at box 1210. Thus, if two threads repeatedly engage in competition to a shared resource, the random or exponentially increasing back-off delay can prevent repeated races between them.
The usage model described in FIG. 5 finds application with data structures of all sizes. At one extreme, a single version stamp may be provided for the entire data structure. Data structures conventionally may be quite large relative to cache line sizes. For example, they may be large (e.g. hundreds of kilobytes), dynamically-allocated data structures that are distributed across multiple virtual memory locations. In this embodiment, a modification to any part of the data structure by one thread may cause the version stamp to be updated and may cause another thread operating pursuant to FIG. 5 to reiterate the operation several times over.
Another extreme may be presented when a version stamp is provided at each cache line in the data structure. In this case, one thread's modification of a cache line of the data structure may cause reiteration of another thread's operation of FIG. 5 only if the other thread is operating upon the same cache line. In this embodiment, the likelihood of reiteration may be substantially reduced when compared to the foregoing embodiment. This second embodiment, of course, expands the memory consumed by the data structure; not only must the substantive data of the structure be stored in memory but version stamps must be stored at addresses as well. In implementation, it is expected that software designers will determine how to construct their data structures and how to distribute version stamps throughout it. For the purposes of this discussion, it is sufficient to note that the operation of FIG. 5 finds application with implementations at either extreme or anywhere in between.
FIG. 6 illustrates a usage model data update method 1300 according to an embodiment that may employ the compare and exchange operation of FIG. 4. This usage model may be executed by the thread at the software level. The method 1300 may find application with data structures having only a single version number for the entire structure, data structures having version numbers for each cache line in the structure or embodiments in between these two extremes.
The method 1300 may begin when the thread atomically copies an �old� version stamp and data element from the data structure (box 1310). Thereafter, the thread may operate on its private copy of the data element as may dictated by software (box 1320). To distinguish the updated data element from prior versions of the same element, the updating thread may create a �new� version number within the private copy of the data element. When the data update operations are complete, the thread may load the �old� version number into a predetermined register for access by the compare-and-exchange instruction (box 1330). The thread then executes the compare-and-exchange instruction (box 1340). As described in FIG. 3, the compare and exchange instruction may compare old and current version numbers at the hardware level and, if they agree, write data from a source location to a target location.
After the compare-and-exchange operation completes, the thread may compare the old and current versions stamps at the software level (box 1350). If so, then the update was successful and the software may advance to other stages of processing (box 1360).
If the compare and exchange was not successful, the method 1300 may be retried. As with the operation of FIG. 5, several embodiments are available. In a first embodiment, the thread may return to box 1310 and retry the entire method 1300. Alternatively, the software may maintain a counter of unsuccessful iterations and, if the counter exceeds a predetermined threshold, the software may attempt to accomplish the data operations using a permanent lock (boxes 1370-1390). And, as with the other embodiment, random delays or exponentially increasing delays may be introduced before retries to avoid race conditions.
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Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982. (eBook, 1982) [WorldCat.org]
I thought you might be interested in this item at http://www.worldcat.org/oclc/681907110 Title: Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982. Publisher: Washington : U.S. G.P.O., 1982. OCLC:681907110
Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982.
Federal Meat Inspection Act amendments.
(DLC) 83601304
(OCoLC)9159869
681907110
Add tags for "Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982.". Be the first.
<http://www.worldcat.org/oclc/681907110> # Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982.
library:oclcnum "681907110" ;
library:placeOfPublication <http://experiment.worldcat.org/entity/work/data/22306819#Place/washington> ; # Washington
schema:exampleOfWork <http://worldcat.org/entity/work/id/22306819> ;
schema:isSimilarTo <http://www.worldcat.org/oclc/9159869> ;
schema:name "Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982."@en ;
schema:productID "681907110" ;
schema:publication <http://www.worldcat.org/title/-/oclc/681907110#PublicationEvent/washington_u_s_g_p_o_1982> ;
schema:publisher <http://experiment.worldcat.org/entity/work/data/22306819#Agent/u_s_g_p_o> ; # U.S. G.P.O.
schema:url <http://catalog.hathitrust.org/api/volumes/oclc/45887269.html> ;
schema:url <http://books.google.com/books?id=ETTWAAAAMAAJ> ;
schema:url <http://catalog.hathitrust.org/api/volumes/oclc/9159869.html> ;
wdrs:describedby <http://www.worldcat.org/title/-/oclc/681907110> ;
<http://experiment.worldcat.org/entity/work/data/22306819#Agent/u_s_g_p_o> # U.S. G.P.O.
<http://experiment.worldcat.org/entity/work/data/22306819#Place/washington> # Washington
<http://www.worldcat.org/oclc/9159869>
rdfs:label "Federal Meat Inspection Act amendments." ;
schema:isSimilarTo <http://www.worldcat.org/oclc/681907110> ; # Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982.
<http://www.worldcat.org/title/-/oclc/681907110>
schema:about <http://www.worldcat.org/oclc/681907110> ; # Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982.
<http://www.worldcat.org/title/-/oclc/681907110#PublicationEvent/washington_u_s_g_p_o_1982>
schema:location <http://experiment.worldcat.org/entity/work/data/22306819#Place/washington> ; # Washington
schema:organizer <http://experiment.worldcat.org/entity/work/data/22306819#Agent/u_s_g_p_o> ; # U.S. G.P.O.
Federal Meat Inspection Act amendments : hearing before the Subcommittee on Livestock, Dairy, and Poultry of the Committee on Agriculture, House of Representatives, Ninety-seventh Congress, second session, on H.R. 5268, September 29, 1982./United States. Congress. House. Committee on Agriculture. Subcommittee on Livestock, Dairy, and Poultry.; Washington : U.S. G.P.O., 1982.

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text:
De 10 bästa hotellen nära Karting Almancil, Almancil, POR – Booking.com
Hotell och boenden nära Karting Almancil i Almancil (Portugal)
Letar du efter boende i närheten av Karting Almancil?
Hotell nära Karting Almancil
Quarteira (5 km från Karting Almancil)
Beskrivning Parque Atlântico is set in Quarteira, 3.6 km from Aquashow Water Park, and an outdoor swimming pool and a tennis court are available in-house.
Vila Limao Det här boendet är med i vårt program för rekommenderade boenden. Boendet gör allt för att ge sina gäster en bra upplevelse tack vare dess utmärkta service och bra priser. Boendet betalar eventuellt Booking.com lite mer för att vara med i programmet.
Almancil (2,7 km från Karting Almancil)
Beskrivning Located in Almancil, Vila Limão offers a private swimming pool and is surrounded by lush gardens.
Quarteira (4,7 km från Karting Almancil)
Beskrivning Situated in Quarteira, just 3.2 km from Aquashow Water Park, Carteira, 2 Bedrooms By Vilamoura Sun features accommodation with free WiFi.
Quarteira (4,9 km från Karting Almancil)
Beskrivning Situated just 3.5 km from Aquashow Water Park, Varandas de Carteia features accommodation in Quarteira with access to a casino, an outdoor swimming pool, as well as valet parking.
Quarteira (4,5 km från Karting Almancil)
Beskrivning Offering free WiFi and garden views, Quinta Shiamar is an accommodation situated in Quarteira. Guests staying at this holiday home have access to a fully equipped kitchen and a terrace.
Algarvila Det här boendet är med i vårt program för rekommenderade boenden. Boendet gör allt för att ge sina gäster en bra upplevelse tack vare dess utmärkta service och bra priser. Boendet betalar eventuellt Booking.com lite mer för att vara med i programmet.
Vilamoura (5 km från Karting Almancil)
Beskrivning Algarvila, boasting free bikes, is located in Vilamoura, 2.2 km from Vilamoura Marina and 6 km from Falesia Beach. The Água Moments is within 2.5 km of the holiday home, and free WiFi is provided.
Farm of Dreams Det här boendet är med i vårt program för rekommenderade boenden. Boendet gör allt för att ge sina gäster en bra upplevelse tack vare dess utmärkta service och bra priser. Boendet betalar eventuellt Booking.com lite mer för att vara med i programmet.
Almancil (0,8 km från Karting Almancil)
Beskrivning Farm of Dreams ligger i Almancil och har en uppvärmd utomhuspool. Boendet ligger 15 km från Faro och 11 km från Vilamoura. På anläggningen erbjuds boende i semesterhus med 1, 2 eller 3 sovrum.
"The accommodation was beautiful and spotless within gorgeous surroundings. The pool was perfect for the children; they also enjoyed the trampoline and the mini golf. We had a wonderful holiday."
Farm of Dreams ligger i Almancil och har en uppvärmd utomhuspool. Boendet ligger 15 km från Faro och 11 km från Vilamoura. På anläggningen erbjuds boende i semesterhus med 1, 2 eller 3 sovrum.
Vale do Lobo (4,7 km från Karting Almancil)
Beskrivning Located in Vale do Lobo, Vale do Lobo Beach Villa features a private pool. With sea views, this accommodation offers a terrace. The villa has a cable flat-screen TV.
Vilamoura (4,9 km från Karting Almancil)
Beskrivning Villa Sunset is situated in Vilamoura. Providing free WiFi, the property also has free bikes and an outdoor swimming pool.
"We absolutely loved our stay here and only wished we could have stayed longer. It was so relaxing, quiet and so picturesque. After recently having a baby, all I wanted was to spend time with the family..."
Ceri. Storbritannien
Villa Sunset is situated in Vilamoura. Providing free WiFi, the property also has free bikes and an outdoor swimming pool.
VIVENDA L'OLIVIER Det här boendet är med i vårt program för rekommenderade boenden. Boendet gör allt för att ge sina gäster en bra upplevelse tack vare dess utmärkta service och bra priser. Boendet betalar eventuellt Booking.com lite mer för att vara med i programmet.
Quarteira (4,3 km från Karting Almancil)
Beskrivning Located in Quarteira, 2.7 km from Aquashow Water Park, VIVENDA L'OLIVIER provides accommodation with free WiFi and a garden.
"Fantastic ! French couple, very good hosts, lovely property. Highly recomended."
Located in Quarteira, 2.7 km from Aquashow Water Park, VIVENDA L'OLIVIER provides accommodation with free WiFi and a garden.
Visa fler boenden nära Karting Almancil
De mest bokade hotellen i närheten av Karting Almancil den senaste månaden
Zodiaco 3 stjärnor
Det här hotellet i Almancil bokades 235 gånger
Hotel Pinhal do Sol 3 stjärnor
Det här hotellet i Almancil bokades 137 gånger
Aquashow Park Hotel 4 stjärnor
Det här hotellet i Almancil bokades 190 gånger
Pestana Vila Sol Golf & Resort Hotel 5 stjärnor
Det här hotellet i Almancil bokades 178 gånger
Conrad Algarve 5 stjärnor
Det här hotellet i Almancil bokades 100 gånger
Det här hotellet i Almancil bokades 125 gånger
Solgarve 3 stjärnor
Det här hotellet i Almancil bokades 135 gånger
Det här hotellet i Almancil bokades 132 gånger
Andra sevärdheter nära Karting Almancil
Populära hotell nära Karting Almancil
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text:
Official Campaign Web Site - Robert J. Johnson | Library of Congress
Archived Web Site Official Campaign Web Site - Robert J. Johnson
Official Campaign Web Site - Robert J. Johnson
- Johnson, Robert J.
http://johnsonforcongress.org/
Johnson, Robert J. Official Campaign Web Site - Robert J. Johnson . 2004. Archived Web Site. https://www.loc.gov/item/lcwaN0001153/.
Johnson, R. J. (2004) Official Campaign Web Site - Robert J. Johnson . [Archived Web Site] Retrieved from the Library of Congress, https://www.loc.gov/item/lcwaN0001153/.
Johnson, Robert J. Official Campaign Web Site - Robert J. Johnson . 2004. Archived Web Site. Retrieved from the Library of Congress, <www.loc.gov/item/lcwaN0001153/>.

value: This website is the research library that officially serves the United States Congress and is the de facto national library of the United States. It is the oldest federal cultural institution in the United States.


text:
Robert Burgess (sociologist) - Wikipedia
Robert Burgess (sociologist)
(Redirected from Robert Burgess (professor))
Burgess at Thomas Erlebach's inaugural lecture on 2 December 2008
Robert George Burgess
(1947-04-23) 23 April 1947 (age 70)
University of Warwick (PhD, 1981)
University of Durham, (BA, 1971)
Hilary Joyce (m. 1974)
Sir Robert Burgess DL, FAcSS (born 23 April 1947) is a British sociologist and academic. He was appointed Vice-Chancellor of the University of Leicester in 1999, succeeding Ken Edwards. He was President of the British Sociological Association 1989-1991.[2] He is currently chair of the board of GSM London.[3]
Burgess received his BA degree from the University of Durham in 1971 and his PhD degree from the University of Warwick in 1981. He remained at Warwick as a lecturer and became Professor of Sociology in 1987. He then rose through the ranks, serving as Senior Pro-Vice-Chancellor 1995–99.[1] Burgess then moved to the University of Leicester as Vice-Chancellor, introducing sweeping changes that enhanced the university's reputation and saw it enter the top-20 institutions in many league tables.[4]
Burgess is chair of the Universities and Colleges Admissions Service (UCAS), the Research Information Network,[5] and the UUK/Guild HE Teacher Education Advisory Group.[6] In 2007, Burgess chaired the steering group that produced the Burgess Report, calling for sweeping changes in university degree classification that would replace the established system of first- and second class degrees.[7][8][9]
Burgess was knighted in the 2010 New Year Honours.[10] He became an Academician of the Social Sciences in 2000. He received an Honorary DLitt degree from the University of Staffordshire in 1998 and a DUniv degree from the University of Northampton in 2007.[1]
He married Hilary Margaret Mary Joyce in 1974 and lists his recreations as walking, music and "some gardening".[1] Sir Bob and Lady Burgess live at Knighton Hall, the University of Leicester's traditional vice-chancellor's residence in Knighton, Leicester. Burgess's record in building both the university's academic reputation and its campus buildings have earned him the nickname Bob the Builder among his university colleagues.[11]
Burgess retired from the post of Vice-Chancellor in September 2014, at age 67.[12] He was succeeded by Professor Paul Boyle.[2]
^ a b c d BURGESS, Prof. Robert George’, Who's Who 2010, A & C Black, 2010; online edn, Oxford University Press, Dec 2009 ; online edn, Nov 2009 accessed 31 Dec 2009
^ a b "University welcomes new President and Vice-Chancellor". University of Leicester. Retrieved 2014-10-08. ^ GSM London (April 2015). "Professor Sir Bob Burgess joins GSM London as chair of board". GSM London. Retrieved 2 July 2015. ^ Services to education prominent in New Year honours list The Guardian, 31 December 2009
^ Advisory Board – Research Information Network
^ Teacher education - Policy areas - Policy and research - Universities UK
^ Report outlines future reforms for degree classification, University of Leicester, 16 October 2007
^ Burgess report on degrees will help employers, University of Bedfordshire, 18 October 2007
^ Bob Burgess: I hope student records make degree classes obsolete, The Independent, 5 November 2009
^ "No. 59282". The London Gazette (Supplement). 31 December 2009. p. 1. ^ "Bye bye Bob". The Tab. 23 September 2013. Retrieved 20 December 2013. ^ Dryden, Fiona (9 August 2014). "Retiring Professor Sir Robert Burgess reflects on his career at the University of Leicester". Academic offices
Vice-Chancellor of the University of Leicester
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Add links	This page was last edited on 17 December 2016, at 14:51.

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text:
Authentic - Review of Achilleus, Vienna, Austria - TripAdvisor
Authentic - Achilleus
Ranked #1,685 of 4,308 Restaurants in Vienna
Great Greek fare nearly as good as mama makes! A real authentic eating experience outside of Greece. Friendly and attentive service and terrific ambience.
Ask John G about Achilleus
There are newer reviews for Achilleus
All reviews moussaka greek restaurant great greek food generous portion small restaurant
Touristma
Bad food, no taste, no flavour, money waste. Don't go there.
The food is salty, no taste at all, no flavour except of overfried oil. The worst food I had in Vienna. There is nothing greek, except for names and wines. Horrible beer. They shamelessly ask for tip although they charge 1.5 euros per person for " the cover". The worst choice we made while staying in Vienna.
Ask Touristma about Achilleus
1 Thank Touristma
Our fault too as we arrived fairly late in the evening. Service ok but we were more or less the only people there. But the food was uninspiring. Some fair, some appalling. Over cooked and not tasty at all. A bad reflection on Greek cooking.
Ask gummington about Achilleus
1 Thank gummington
Seal of approval from a Greek
My husband is Greek, and I lived there for 15 years, and we loved this restaurant! I am really surprised by the negative comments below. I can only guess that they were looking for a stereotypical cheaper mid-category Greek restaurant (ie American Greek restaurant style with souvlaki on a stick served with rice and potatoes), and Achilleus should not be compared to that band of dining.
In fact, since we can not find good Greek food where we currently live, we ate at Achilleus three times during our trip to Vienna, including celebrating Greek Easter. The owner, chef and staff are all Greek, which adds to the authenticity of the restaurant, and they are very warm and friendly.
We highly recommend the lamb chops, grilled octopus and sole - all which are brought from Greece. The kotsi melted off the bone and my daughters loved the giouvetsi. They have a white wine which is one of the best Greek wines in our well-researched opinion, Alpha Estates Axia. So good! You MUST save room to try the galaktobouriko and the karidopita... both of which rival any restaurants in Greece.
Ask MLV_Greece about Achilleus
I was there with some friends(we were 3 in total), had a greek coffee at first(average), then ordered a drink and a portion o gyros(typical greek way to share food with friends). We had to pay 40€, which included the waiter's tip, for 3 coffees, 4 drinks and a rather small portion of gyros. Bread was also charged without us being informed. FYI: waiter was rude and we didn't want to give him a tip... I guess he demanded it.
Definitely a tourist trap, wouldn't recommend it to anyone.
Important: I'm a Greek living in Vienna. However I would never go there again, not even to support my own people. Pity their attitude is so unprofessional
Ask fotis9990 about Achilleus
1 Thank fotis9990

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text:
Mystery of the underwater 'fairy rings' solved: Bizarre grass circles are the result of sulphurous toxins in the sea | Daily Mail Online
Biologists said the ring shapes are created because of the circular pattern in which the grass grows - and dies when it is exposed to toxins
Published: 06:31 EDT, 4 February 2014 | Updated: 06:55 EDT, 4 February 2014
Strange underwater rings spied in shallow water off the coast of Denmark are caused by poison – and not aliens or fairies, biologists have said.
A holidaying journalist took a photo of the mysterious 'fairy rings' in the clear water off the Isle of Møn, leading people to speculate about the cause of the underwater fairy rings.
The rings are formed of vivid green eelgrass and measure up to 49ft (15m) wide and their shape is created by toxins in the water.
Strange underwater rings (pictured) spied in shallow water off the coast of Denmark are caused by poison and not aliens or fairies, biologists have said. The rings are formed of eelgrass and measure up to 49ft (15m) wide
WHAT MADE THE RINGS?
The rings are eelgrass and measure up to 49ft (15m) wide.
Studying the mud surrounding the bizarre rings, Danish biologists discovered high levels of sulphide, which is poisonous to the grass.
The plants trap the toxic soil so that there is a high concentration around them.
The rings form because of the circular pattern in which eelgrass naturally grows and the toxin killing off older, weaker plants.
Younger eelgrass plants seem to be better at withstanding the toxin than the older plants at the centre of a circular colony, which die and leave a ‘hole’ so that the plants look like rings.
The result is an exceptional circular shape, where only the rim of the circle survives.
Danish biologists have confirmed that the circles have ‘nothing to do with either bomb craters or landing marks for aliens’.
Marianne Holmer from the University of Southern Denmark and Jens Borum from the University of Copenhagen also ruled out fairies, ‘who in the old days got the blame for similar phenomena on land,’ they said.
Mysterious plague causes starfish to rip off their arms -... Want your children to grow up confident and kind? Get them a...
Instead, they believe the rings form because of the circular pattern in which eelgrass naturally grows and the toxin killing off older, weaker plants, according to the journal Marine Biology.
Studying the mud surrounding the bizarre rings, they discovered high levels of sulphide, which is poisonous to the grass and can gradually build up on a chalky seabed, just like Møn’s.
Scientists believe that the rings form because of the circular pattern in which vivid green eelgrass (pictured) naturally grows and the toxin killing off older, weaker plants
‘Most mud gets washed away from the barren, chalky seabed, but like trees trap soil on an exposed hillside, eelgrass plants trap the mud and therefore there will be a high concentration of sulphide-rich mud among the eelgrass plants,’ the biologists said.
While the grass might look a little like some types of seaweed, it is a flowering plant that expands outwards to create circular colonies when it grows.
Younger eelgrass plants seem to be better at withstanding the toxin than the older plants at the centre of a circular colony, which die and leave a hole so that the plants look like rings.
Holmer and Borum said: ‘The result is an exceptional circular shape, where only the rim of the circle survives - like fairy rings in a lawn.’
Some fairy rings on land have been blamed on fungus, but others have baffled scientists, such as those found in the grasslands of Nambia.
Hungry ants, seeping gas and competition for resources have all been blamed for the markings there.

value: This website is the website of the Daily Mail, a newspaper in the United Kingdom, and of its sister paper The Mail on Sunday. MailOnline is a division of dmg media, which is owned by Daily Mail and General Trust plc.


text:
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2.2.5 Additional Projects
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The Seeker's Storm by Lea Carter, Paperback | Barnes & Noble® B&N Top 100 NY Times Bestsellers
9780998967806
Silver Sagas , #6
The Seeker's Storm 4 out of 5 based on 0 ratings. 1 reviews.
PearlsReviews More than 1 year ago
There is no mention on the cover or in the synopsis that this is a part of a series. Online, the title includes "Silver Sagas Book" but I wasn't aware of that when I started reading it. And although I could feel elements of the story were referring to past books, it was still able to stand on its own two feet. It actually made me more curious to read the previous books. I was surprised to discover that there were multiple books prior to this one. I only felt like there was one, maybe two books I had missed. I never would have guessed five. Because this is my first book by this author, and having jumped into the middle of a series, I did miss out on really knowing these characters. They had so much history that I missed out on. Yet, I was fascinated by their relationships and friendships. Sometimes I like just being thrown into a story. I loved reading the climax on both storylines. They really drew me in. I am ready to learn more about the characters and the events. I will definitely look into the previous books and wait for the next books.

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text: -class families from the fiscal cliff that they're facing by freezing the tax rates for the first $250,000 of all americans' income. letting the rates go up to the same level they were during the clinton administration. republicans know where we stand. we've said it. we've said it. we've said it so many times. the president said the same thing. it's been weeks, at least two weeks, since we met at the white house. we're still waiting for a serious offer from the republicans. really, now is the time for the republicans to move past this happy talk about revenues, ill-defined, of course, and put specifics on the table. the president has made his proposal. we need a proposal from them. i'm glad to see there are some reasonable republicans breaking from the pack. veteran representative cole and a new member, scott from south carolina, have said basically the same thing. and that is, they should bring to the floor of the house the bill that's passed over here. it would pass overwhelmingly, as scott said in the press today. our bill would pass in a matter of minutes if the house republicans simply allow ×

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text: Translations English (46) German (15) Spanish (15) French (13) Polish (12) Russian (11) Czech (10) Italian (10) Danish (9) Dutch (9) Japanese (9) Brazilian Portuguese (8) Chinese (Simplified) (8) Hungarian (8) Finnish (7) License OSI-Approved Open Source (64) Academic Free License (4) Adaptive Public License (1) Affero GNU Public License (2) Apache License V2.0 (1) Artistic License (3) Attribution Assurance License (1) BSD License (8) Boost Software License (1) Computer Associates Trusted Open Source License 1.1 (1) Eclipse Public License (1) GNU General Public License version 2.0 (34) GNU General Public License version 3.0 (16) GNU Library or Lesser General Public License version 2.0 (6) GNU Library or Lesser General Public License version 3.0 (1) MIT License (5) Creative Commons Attribution License (4) Creative Commons Attribution Non-Commercial License V2.0 (1) Creative Commons Attribution ShareAlike License V2.0 (2) Creative Commons Attribution ShareAlike License V3.0 (2) Other License (4) Programming Language C++ (34) C (13) Java (7) Python (7) C# (6) Delphi/Kylix (5) ALGOL 68 (3) JavaScript (3) Perl (3) APL (2) ASP (2) ActionScript (2) Free Pascal (2) Lazarus (2) Lua (2) Status Beta (13) Planning (5) Alpha (4) Mature (4) Pre-Alpha (3) Inactive (1) OS Modern (68) FreeBSD (12) Linux (52) NetBSD (5) OS X (38) OpenBSD (7) Solaris (11) Win2K (24) WinXP (56) Windows 7 (52) Windows 8 (12) Windows (68) Linux (57) Grouping and Descriptive Categories (43) 32-bit MS Windows (95/98) (1) 32-bit MS Windows (NT/2000/XP) (22) 64-bit MS Windows (22) All 32-bit MS Windows (10) All BSD Platforms (9) All POSIX (24) Classic 8-bit Operating Systems (1) OS Independent (2) OS Portable (17) Project is OS Distribution-Specific (3) Project is an Operating System Distribution (4) Project is an Operating System Kernel (2) Mac (42) BSD (30) Freshness Recently updated (27) Collection Enterprise (2) Top Apps

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internationalization - Cakephp i18n get translation locales - Stack Overflow
I must say that cakephp (using the 1.3 version because project was set up with that) has a strange concept of i18n.
I did translate the static strings with success, but the dynamic ones.. cake's ideas how to manage multilingual content seems a bit, let's say, akward to me.
I did set up the i18n table (will split that up in several tables later when i got it working) and attached the translate behaviour to the desired models.
So far so good, then, in the add-actions i added a select field containing the locales (en_us, de_de...) so that the user can decide wich one to save.
Bevore saving the records, i did a $this->Modelname->locale = $locale; to tell the model wich locale to use.
The record gets saved successfully, buttttt, here come the problems:
- I have an index-action with a lot of records, i want the user to have the possibility to have different translations for each item (let's say: one item is translated into english(us) and german, another is translated into english(us), italian and french, how can i give the user the possibility to edit/delete single translations?
- I did use the $this->Modelname->bindTranslation(...) inside actions where i needed to get the locale names (wich translations existed) so that the user can decide wich one to edit, is there another, more elegant way to accomplish this? Also, when i do this: $this->Modelname->bindTranslation(...); and then instead of using the find() method, i use the paginate(), it does not return any translations... =/
I hope someone understood my a bit overcomplicated text and can maybe help me ;-)
cakephp internationalization cakephp-1.3 share|improve this question asked Mar 7 '12 at 22:09
1 Complex questions like this work better with the following: 1- more formatting in the question instead of a single long paragraph. 2- Code samples to help demonstrate what your are doing so the helper doesn't have to visualize everything or try to recreate it from a description.
Ok, let's try it in a more simpler way: First of all, i have records with multiple translations, i want to get the existing language/locale names that exist for each row. For instance: I have 4 rows of data, for each row there can be translations in different languages, i want to know wich languages exist for each row.
– AlexFr.
Mar 8 '12 at 7:29
I have a solution for Cakephp2.0 which maybe works with Cakephp1.3, too, also i've never tested. You have to rename stuff and edit some things, but it may work.
In case: i recommend you to update to Cakephp2.0 as long as you are in early state of your project. 1.3 is deprecated ever since Cakephp2.1 was finally released.
I went through that update process about two or three times and it's a day of work, maybe two. In my case is restarted the project from scratch. I do not really trust that updated shell although it is doing really great work.
My method includes overwriting the existing TranslateBehavior, added a new TranslationBehavior, a helper and a component.
Here's the zip with the files.
http://www.func0der.de/cakephp/MultiLanguageForms.zip
As soon as I figured out how to use GIT properly, i will pull request it to them.
Ticket with files is already in: http://cakephp.lighthouseapp.com/projects/42648/tickets/2463-multi-language-forms#ticket-2463-4 ;)
In the Controller you include the component and the helper. The models gets the Translation AND the Translate behavior. The Translatio goes first because of a callback matter. But the script will throw exception else anyway.
The component will find all languages existing in the "Locale" folder by it self and safe them in into the Configure class.
In the view you use $this->Translation->inputs('Modelname.field');. The model name is important, cause i haven't figured out a way yet, to determine that automatically, because i am not sure if the FormHelper instance in my helper is the same as in the View. And i have a leak of time. ^^
The TranslationBehavior will validate EACH! of the language fields based on the field name.
If there are any questions: Ask ^^
Through i am not here very often, i will try to have a look over this question ;)
share|improve this answer answered Mar 24 '12 at 18:27
Not the answer you're looking for?	Browse other questions tagged cakephp internationalization cakephp-1.3 or ask your own question.	asked
Routing for CakePHP i18n
CakePHP TranslateBehavior saving to both i18n table and model table

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Sirt3 mediates reduction of oxidative damage and prevention of age-related hearing loss under caloric restriction. - PubMed - NCBI
1 selected item: 21094524
Cell. 2010 Nov 24;143(5):802-12. doi: 10.1016/j.cell.2010.10.002.
Someya S1, Yu W, Hallows WC, Xu J, Vann JM, Leeuwenburgh C, Tanokura M, Denu JM, Prolla TA.
Departments of Genetics and Medical Genetics, University of Wisconsin, Madison, 53706, USA.
Caloric restriction (CR) extends the life span and health span of a variety of species and slows the progression of age-related hearing loss (AHL), a common age-related disorder associated with oxidative stress. Here, we report that CR reduces oxidative DNA damage in multiple tissues and prevents AHL in wild-type mice but fails to modify these phenotypes in mice lacking the mitochondrial deacetylase Sirt3, a member of the sirtuin family. In response to CR, Sirt3 directly deacetylates and activates mitochondrial isocitrate dehydrogenase 2 (Idh2), leading to increased NADPH levels and an increased ratio of reduced-to-oxidized glutathione in mitochondria. In cultured cells, overexpression of Sirt3 and/or Idh2 increases NADPH levels and protects from oxidative stress-induced cell death. Therefore, our findings identify Sirt3 as an essential player in enhancing the mitochondrial glutathione antioxidant defense system during CR and suggest that Sirt3-dependent mitochondrial adaptations may be a central mechanism of aging retardation in mammals.
Sirtuins and calorie restriction. [Nat Rev Mol Cell Biol. 2012]
SIRT3 in calorie restriction: can you hear me now? [Cell. 2010]
PMC3018849
10.1016/j.cell.2010.10.002
CR Prevents AHL and Protect Cochlear Neurons in WT Mice, But not in Sirt3−/− Mice
(A) ABR hearing thresholds were measured at 32, 16, and 8 kHz from control diet and/or calorie restricted WT (left) and Sirt3−/− (right) mice at 2 and 12 months of age (n = 9–12). *Significantly different from 2-month-old WT or Sirt3−/− mice (P < 0.05), **significantly different from 12-month-old WT mice (P < 0.05). CD = control diet, CR = calorie restricted diet.
(B–M) Neurons in the basal cochlear regions from WT mice in control diet at 2 (B and C) and 12 (F and G) months of age, and calorie restricted diet at 12 months of age (J and K). Neurons from control diet Sirt3−/− mice at 2 (D and E) and 12 (H and I) months of age, and calorie restricted Sirt3−/− mice at 12 months of age (L and M)(n = 5). Arrows in the lower magnification photos indicate neuron regions. Scale bar = 100 µm (B, F, J, D, H, and L), 20 µm (C, G, J, E, I, and M). Data are means ± SEM. See also .
Cell. ;143(5):802-812.
CR Reduces Oxidative DNA Damage and Increases Cell Survival in the Cochleae from WT Mice, But not from Sirt3−/− Mice
(A) Oxidative damage to DNA (apurinic/apyrimidinic sites) was measured in the cochlea and neocortex from control diet and calorie restricted WT and Sirt3−/− mice at 12 months of age (n = 4–5). AP sites= apurinic/apyrimidinic sites. *Significantly different from 12-month-old WT mice (P < 0.05).
(B) Oxidative damage to DNA (8-oxodGuo) was measured in the liver from control diet and calorie restricted WT and Sirt3−/− mice at 12 months of age (n = 4–5).
(C) Neuron survival (neuron density) of basal, middle, and apical cochlear regions was measured from control diet and calorie restricted WT and Sirt3−/− mice at 12 months of age (n = 4–5).
(D) OH (outer hair) cell survival (%) of basal, middle, and apical cochlear regions was measured from control diet and calorie restricted WT and Sirt3−/− mice at 12 months of age (n = 4–5).
(E) IH (inner hair) cell survival (%) of basal, middle, and apical cochlear regions was measured from control diet and calorie restricted WT and Sirt3−/− mice at 12 months of age (n = 4–5). Data are means ± SEM. See also .
Sirt3 Increases the Ratios Of GSH:GSSG in Mitochondria During CR
(A–C) Ratios of GSH:GSSG (A), GSSG (B), and GSH (C) were measured in the inner ear, brain (neocortex), and liver from control diet and calorie restricted WT and Sirt3−/− mice at 5 months of age (n = 4–5). *Significantly different from 12- or 5-month-old WT mice (P < 0.05). Data are means ± SEM.
Sirt3 Increases Idh2 Activity and NADPH Levels in Mitochondria by Decreasing the Acetylation State of Idh2 During CR
(A) Top panels: Western blot analysis of Sirt3 and Idh2 levels in the liver from 5-month-old WT or Sirt3−/− fed either control or calorie restricted diet. Lower panels: Endogenous acetylated Idh2 was isolated by immunoprecipitation with anti-Idh2 antibody followed by western blotting with anti-acetyl-lysine antibody (n = 3).
(B–C) Quantification of the amounts of total Idh2 acetylation (B) and Sirt3 protein (C) from (A). Western blot was normalized with Idh2 levels or Sirt3 levels quantified and analyzed by Image software (n = 3).
(D) Idh2 activities were measured in the liver, inner ear (cochlea), and brain (neocortex) from control diet and calorie restricted WT and Sirt3−/− mice at 5 months of age (n = 3–5).
(E) Ratios of NADPH:total NADP (NADP+ + NADPH) were measured in the liver, inner ear, and brain (neocortex) from control diet and caloric restricted WT and Sirt3−/− mice at 5 months of age (n = 3–5). *Significantly different from control diet fed WT mice (P < 0.05). Data are means ± SEM.
Sirt3 Directly Deacetylates Idh2 and Stimulates Activity
(A–B) Sirt3 interacts with Idh2. Idh2 or Sirt3 were immunoprecipitated from HEK293 cell lysates with IgG antibody or FLAG beads. Precipitated Idh2-FLAG was detected by anti-FLAG antibody and co-IP Sirt3-HA was detected by anti-HA as indicated (A). Precipitated Sirt3-FLAG was detected by anti-FLAG antibody and co-IP Idh2-MYC was detected by anti-MYC as indicated (B) (n = 3).
(C) Sirt3 deacetylates Idh2 in HEK293 cells. Idh2 was cotransfected with or without Sirt3, isolated by immunoprecipitation with anti-MYC antibody followed by western blotting with anti-acetyl-lysine antibody (n = 3).
(D) Sirt3, but not Sirt5, deacetylates Idh2 in vitro. Acetylated Idh2 was prepared as outlined in Experimental Procedure, and was incubated with purified recombinant Sirt3 or Sirt5 with or without NAD+ at 37 °C for 1 hour. Acetylation status was assessed by western blotting with anti-acetyl-lysine antibody (n = 3). An anti-FLAG western shows equivalent Idh2 protein levels were used and coomassie staining shows purified Sirt3 and Sirt5.
(E) In vitro deacetylation of Idh2 by Sirt3, but not Sirt5, stimulates Idh2 activity. Acetylated Idh2 in buffer (Tris (pH 7.5), with or without 1 mM NAD, and 1 mM DTT) was incubated with purified 50 nM Sirt3 or Sirt5 () at 37°C for 1 hour, followed by Idh2 activity assay (n = 3). *Significantly different from Idh2 alone (P < 0.05). Data are means ± SEM. See also .
Overexpression of Sirt3 and/or Idh2 Is Sufficient to Increase NADPH Levels and Protects HEK293 Cells from Oxidative Stress
(A–B) NADPH concentrations were significantly increased when either Idh2 or Sirt3 or both were stably overexpressed in HEK293 cells. Measurements with errors are shown for the four different stable cell populations from each type of transfection (vector alone, Sirt3, Idh2 and Sirt3 with Idh2) (n = 3). *Significantly different from vector alone (P < 0.05), **Significantly different from Idh2 or Sirt3 (P < 0.05), (B) Western blotting confirms Idh2 and Sirt3 stable expression.
(C–D) Sirt3 and/or Idh2 overexpression is sufficient to protect HEK293 cells from the exogenous oxidants hydrogen peroxide (H2O2)(C) and menadione (D). The four different stable cells were transiently exposed to either 1 mM H2O2 or 25 µM menadione (n = 16). Data are means ± SEM.
A Model for the CR-mediated Prevention of AHL in Mammals
In response to CR, SIRT3 activates Idh2, thereby increasing NADPH levels in mitochondria. This in turn leads to an increased ratio of GSH:GSSG and decreased levels of ROS, thereby resulting in protection from oxidative stress and prevention of AHL in mammals.
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Amazon.co.uk: A Customer's review of The Great Gatsby: The Authorised text
Gasby is the best summary of the Roaring 20s around today., 29 May 1998
I am a senior in high school and was assigned The Great Gatsy to read for english class. There was nothing quite like sitting down and thinking about what the true meanings in this book really are. There are stories of triumph, sacrifice; love and hate; rich and poor, and many others. Each character has their own story, and each intertwines with another. The Great Gatsby is an amazing work of art with incredible stories clashing different types of people to give the essence of a great era in our history. I highly recommend it to anyone.
The Great Gatsby: The Authorised text 0684801523

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Words that start with sphincto | Words starting with sphincto
https://www.thefreedictionary.com/words-that-start-with-sphincto
Dictionary, Encyclopedia and Thesaurus - The Free Dictionary 10,935,714,108 visitors served
Words that start with sphincto
Found 2 words that start with sphincto. Browse our Scrabble Word Finder, Words With Friends cheat dictionary, and WordHub word solver to find words starting with sphincto. Or use our Unscramble word solver to find your best possible play! Related: Words containing sphincto
11-letter words that start with sphincto10-letter words that start with sphinctoSee also
11-letter words that start with sphincto
10-letter words that start with sphincto
Words that start with sphinctou
Words that start with sphinctoz

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text:
Meetup.com walk on Monday May 28 cancelled - South Sound Walkers Meetup Group (Puyallup, WA) | Meetup
Meetup.com walk on Monday May 28 cancelled
Sent on: Monday, May 21, 2012 3:19 PM
We have cancelled the Friends of the Riverwalk meetup walk in Puyallup on Memorial Day, May 28.
Enjoy your day and we will catch up with you on the following Monday.
3,429 Riders

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