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BRAND NEW 17PC BUSHING BEARING DRIVER KIT CASE | eBay
Item 140456854994 is no longer available.50 items found similar to 'BRAND NEW 17PC BUSHING BEARING DRIVER KIT CASE'Learn more about searching:General Search tipsAdvanced search commandsView as:Price Postage to UKTime Left BRAND NEW 17PC BUSHING & BEARING DRIVER KIT IN CASEExpress delivery available £18.99FreeTime left:14d 13h 45m BRAND NEW 17PC BUSHING & BEARING DRIVER KIT IN CASE - F...Express delivery available £18.99FreeTime left:14d 13h 46m 17pc Bushing Bearing Install Driver Set Kit Metric 10mm... From United States£19.30+£13.18Time left:10d 21h 36m 17 pc Bearing Bushing Race Seal Driver Set Kit Metric T...Express delivery available £18.22FreeTime left:4d 2h 24m 17 pc Bearing Bushing Race Seal Driver Set Kit Metric T... From Germany£18.22FreeTime left:4d 2h 25m Bushing Bearing Install Driver Set Kit Metric 17pc 10mm... From United States£10.85+£27.36Time left:19d 7h 13m BRAND NEW 17 PIECE AUTOMOTIVE BUSHING & BEARING DRIVER ...Express delivery available £17.99FreeTime left:14d 13h 52m Bushing And Bearing Driver Set 17pc - 3 Driver Handle £17.36FreeTime left:20d 0h 59m Bushing And Bearing Driver Set 17pc - 3 Driver Handle W... £18.06FreeTime left:6d 2h 32m 17pc Bushing and Bearing Driver Set £15.99+£3.80Time left:8d 9h 0m Bushing Bearing Driver Set English Standard 17pc 3/8" t... From United States£9.65+£24.76Time left:28d 22h 8m Bushing Bearing Driver Set SAE English 17pc 3/8" to 1-... From United States£9.65+£24.76Time left:15d 12h 45m 17PCS Automotive Bushing Replacement Tool Bearing Drive... From Netherlands£336.99FreeTime left:6d 0h 34m 17PCS BUSHING BEARING DRIVER SET TOOLS KIT (METRIC) From Netherlands£290.99FreeTime left:12d 2h 5m BUSHING BEARING DRIVER SET 23 PC KIT ATV SMALL ENGINE A... From United States£24.12+£43.58Time left:22d 11h 19m 10pc Bushing Bearing Race and Seal Install Driver Set K... From United States£12.66+£39.63Time left:29d 12h 8m DRIVER SET BUSHING BEARING 23 PC KIT ATV SMALL ENGINE A... From United States£24.12+£10.61Time left:23d 15h 38m 17 Piece Metric Bushing Driver Kit OTC4407 BRAND NEW! From United States£44.88+£28.62Time left:14d 11h 30m Bergen BER6106 17PC ALUMINIUM WHEEL BEARING RACE & SEAL...Express delivery available £15.99FreeTime left:2h 6m Professional 17Pc Aluminium Wheel Bearing Race & Seal B...Express delivery available £16.00FreeTime left:17d 5h 3m 17PC HOME WORKSHOP METRIC BUSH BEARING SEAL DRIVER CAR ...Express delivery available £21.99FreeTime left:5d 10h 46m NEW PRO QUALITY 17PC ALUMINIUM WHEEL BEARING RACE SEAL ...Express delivery available RRP£36.99£15.80FreeTime left:1d 3h 20m 450843 17PC Aluminum Wheel Bearing Race Seal Bush Drive...Express delivery available £14.99FreeTime left:2h 11m Bergen tools Bearing race seal bush driver set / tool /...Express delivery available £19.95FreeTime left:16d 7h 22m DEMO - PRO 17PC ALUMINIUM WHEEL BEARING RACE & SEAL BUS...Express delivery available RRP£39.99£11.99FreeTime left:27d 7h 42m 10 pc. Bearing Race and Seal Driver Kit LIS-12980 BRAND... From United States£47.58+£33.39Time left:6d 21h 26m NEW XXR TOOLS 17PC METRIC BUSH BEARING SEAL DRIVER CAR ...BEST QUALITY ON EBAY - GUARANTEED! FAST DELIVERY!Express delivery available £19.99FreeTime left:16d 14h 10m PROFESSIONAL 17PC ALUMINIUM WHEEL BEARING RACE & SEAL B...Express delivery available RRP£39.99£14.99FreeTime left:2d 8h 37m PRO QUALITY 17PC ALUMINIUM WHEEL BEARING RACE & SEAL BU...Express delivery available RRP£36.99£15.84FreeTime left:2d 8h 42m 7 pc. Bearing Race and Seal Driver Kit LIS-12600 BRAND ... From United States£26.77+£28.62Time left:6d 21h 26m 10pc Axle Bushing Bearing Race & Seal Install Driver Ma... From United States£19.99+£13.18Time left:9d 17h 21m 9pc Master Auto Axle Bushing Bearing Race & Seal Instal... From United States£22.04+£11.34Time left:11d 15h 25m Car Truck SUV Van 17 Piece Bearing Race & Bushing Seal ...Express delivery available £15.99FreeTime left:28d 16h 14m 17 PIECE BUSHING & BEARING DRIVER SET REMOVAL BUSH'S CA...Express delivery available £14.99FreeTime left:11h 17m 19pc Bushing Driver Set Auto Shop Tools Automotive Serv... From United States£20.03+£33.39Time left:29d 11h 31m 17pcs Metric Bushing Bearing Race Seal Driver Car Motor... From Netherlands£135.99FreeTime left:7d 3h 28m Bushing Bearing Driver Tool Set Metric Steel 19pc 10.5m... From United States£8.44+£24.76Time left:3d 5h 12m 17 PIECE METRIC BUSHING BEARING RACE SEAL DRIVER CAR MO...BEST QUALITY ON EBAY! FAST DELI VERY - GUARANTEED!Express delivery available £19.99FreeTime left:1d 9h 25m Bushing, Bearing and Seal Driver Starter Set OTC-27793 ... From United States£107.63+£35.77Time left:6d 22h 17m BALL BEARING INSTALLER REMOVER DRIVER BUSHING INSTALLAT... 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From Netherlands£136.99FreeTime left:13d 2h 46m Nissan Terrano & Ford Maverick - 3 PC Clutch Kit With B... 4 Bids£21.89+£7.28Time left:4d 13h 49m Professional 17PCS Auminum Metric Bushing Adapters Bush... From Netherlands£136.99FreeTime left:12d 4h 22mItems per page:25 | 50 | 100 | 200Picture size: Page 1 of 1Previous1|2|3|4|5|6|7NextGo to pageAlternatives searches close to what you're looking forAmounts shown in italicised text are for items listed in currency other than Pounds Sterling and are approximate conversions to Pounds Sterling based upon Bloomberg's conversion rates. For more recent exchange rates, please use the Universal Currency Converter.This page was last updated: 28-Aug 07:59. FINDING_TREATMENT_76Number of bids and bid amounts may be slightly out of date. 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Files - Read, Chat, Craft! (Mount Dora, FL)
Our group meets throughout the month for various fun activities. We started as a book club, reading Chic Lit, but found we had a variety of reading interests. So we also have a Mystery book club as well. We meet at restaurants around the Mount Dora and Lake county area for a Monthly lunch, Weekly Cupcakes and the book clubs. We also have a Monthly Craft night! We love to see new members and welcome newcomers and winter residents to our group. Our Sponsors
740 Adventure Lovers
527 Explorer Ladies
342 Blessed Friends

type: global

value: This website is a service used to organize online groups that host in-person and virtual events for people with similar interests. It was founded in 2002 by Chairman Scott Heiferman and four co-founders.


text:
Joëlle De Caluwé - Semantic Scholar
Joëlle De Caluwé
J Chory5
David E Somers5
C M Sullivan5
Aurora Piñas Fernández5
Sheen X Lu5
2Didier Gonze
2Christian Hermans
2Jean-Christophe Leloup
2Nathalie Verbruggen
1Ahmed A. Moustafa
The progression towards Alzheimer's disease described as a bistable switch arising from the positive loop between amyloids and Ca(2+).
Joëlle De Caluwé, Geneviève Dupont
Alzheimer's disease is a progressive neurodegenerative disorder affecting millions of people. It is characterized by the slow deposition of cerebral amyloid-β peptides in the brain and by dysregulations in neuronal Ca(2+) homeostasis. Numerous experimental studies have revealed the existence of a feed-forward loop wherein amyloids-β disturb neuronal Ca(2+)… (More)
A Compact Model for the Complex Plant Circadian Clock
Joëlle De Caluwé, Qiying Xiao, Christian Hermans, Nathalie Verbruggen, Jean-Christophe Leloup, Didier Gonze
The circadian clock is an endogenous timekeeper that allows organisms to anticipate and adapt to the daily variations of their environment. The plant clock is an intricate network of interlocked feedback loops, in which transcription factors regulate each other to generate oscillations with expression peaks at specific times of the day. Over the last… (More)
Modeling the photoperiodic entrainment of the plant circadian clock.
Joëlle De Caluwé, José Romário Fernandes de Melo, +4 authors Didier Gonze
The circadian clock is an endogenous 24 hour rhythm that helps organisms anticipate and adapt to daily and seasonal variations in environment, such as the day/night cycle or changing temperatures. The plant clock is a complex network of transcription factors that regulate each other, forming interlocked feedback loops. Most of its components are… (More)

value: This website is an artificial-intelligence backed search engine for academic publications developed at the Allen Institute for AI and publicly released in November 2015. It uses advances in natural language processing to provide summaries for scholarly papers.


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Mog's Christmas eBook: Judith Kerr: Amazon.co.uk: Kindle Store
See larger image Mog's Christmas [Kindle Edition]
Praise for Mog the Forgetful Cat:‘Grandparents are likely to get as much fun out of seeing it again as the new generation of fans just learning to read!’ Choice Magazine‘A lovely book for all Mog-fanciers’ The ObserverPraise for Goodbye Mog:‘Kerr’s warmth, humour and honesty make this an engaging introduction to a difficult topic’ Financial Times‘Believable, amusing and moving’ Nursery World‘A supremely sensitive story’ The Times‘The best, most consoling book for children on the subject of bereavement…a joy to read’ The Independent on SundayPraise for the Mog series:‘Since her debut in 1970, Mog has become… a national hero.’ Junior‘Delightful stories about the family cat with attitude.’ The Guardian

value: This website is an American multinational technology company which focuses on e-commerce, cloud computing, digital streaming, and artificial intelligence.


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4 bedroom detached house for sale in Church Lane, Elvington, York, YO41 4AD, YO41
www.rightmove.co.uk/property/57045076
FULORD COMPREHENSIVE SCHOOL CATCHMENT
OPEN VIEWS, to the front of this spacious four bedroom detached house which was built and designed by Burns builders approximately 28 years ago. The property is situated in the beautiful village of Elvington which is located eight miles South East of York, the village has a good range of amenities to include doctors, local shop, public house, primary school and is within the catchment area of the highly regarded Fulford comprehensive school. Ideal for commuting to Leeds and West Yorkshire the property would make an ideal family home. Benefiting from double glazing and gas radiator central heating the property briefly comprises of an: entrance hall, downstairs w/c, utility, study, lounge, dining room. To the first floor master bedroom en-suite guest bedroom, bedroom three, bedroom four and the house bathroom. Outside we have gardens to four sides with a gravelled driveway leading to a double garage. The house has some lovely views over open fields as you look out of the front of the property.
A paved pathway to the front door, a garden area mainly set to lawn which leads round to the side of the house where there is a gravelled drive leading to a:
Oak floor, brick fireplace with york stone hearth, french window to the side garden.
Oak floor, french window to the front elevation.
Range of wall and base units, with matching preparation surfaces. integral bosch dishwasher, space for a fridge and a gas cooker point. Belfast sink with a waste disposal unit.
Oak floor leading through the ground floor, stairs leading to the first floor and doors leading to:
Stainless steel sink unit, with the boiler and plumbing for washing machine.
Loft access and a window overlooking the fields to the front.
Television point and window to rear elevation.
Shower cubicle. low level w/c and a wash hand basin.
Corner bath, low level w/c, wash hand basin and a window to the rear elevation.
Double garage contains power and light.
To the rear is a gravelled area for easy maintenance.
To view this media, please visit the on-line version of this page at www.rightmove.co.uk/property-for-sale/property-57045076.html?premiumA=true
Disclaimer - Property reference YRKSP99256695. The information displayed about this property comprises a property advertisement. Rightmove.co.uk makes no warranty as to the accuracy or completeness of the advertisement or any linked or associated information, and Rightmove has no control over the content. This property advertisement does not constitute property particulars. The information is provided and maintained by Hunters, York. Please contact the selling agent or developer directly to obtain any information which may be available under the terms of The Energy Performance of Buildings (Certificates and Inspections) (England and Wales) Regulations 2007 or the Home Report if in relation to a residential property in Scotland.

value: This website is a UK-based company that runs rightmove.co.uk, the UK's largest online real estate portal and property website. It is listed on the London Stock Exchange and is a constituent of the FTSE 100 Index.


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Americana Decor, Primitive Patriotic Decor, Patriotic Wall Basket, Primitive Long John Wall Basket
Retro Gold Coasters - Set of 4
Rustic Patriotic Wooden Flag
CallofValhallaDesign
Americana Ticking Pillow Cover, Americana Decor, Stars and Stripes, 4th of July
Primitive red, white, and blue patriotic hearts on vintage spindles, Americana decor, Fourth of July
Patriotic primitive Uncle Sam shelf sitter, Patriotic decor, Americana decor, Primitive decor, Fourth of July
Patriotic Decor, Americana Decor, Uncle Sam Top Hat Shelf Sitter. Uncle Sam Ornie, July 4th Ornie, Americana Ornie, Patriotic Shelf Sitter
Earthenware Coasters Set of 4
Patriotic Decor,Liberty,Americana,Wooden Art Sign,18x6,Robin-Lee Vieira
Vintage Silver Salt & Pepper Shakers, 1881 Rogers Oneida Silver Plated Salt and Pepper Shakers, Vintage Americana Decor
todwellandgather
Set of five vintage coasters
TheLondonWreathShop
Box of 6 french vintage coasters
Rustic American Flag, Patriotic Decor, USA, Farmhouse, Farmhouse decor, Rustic home decor
Rustic American Flag, Flag, American Flag Decor, Americana decor, Cabin decor, Country decor, Farmhouse decor, reclaimed wood, wall decor
USA blocks, vertical & horizontal
Rustic Patriotic Wreath with Star - Mesh and Burlap - Americana
CreationsbySaraJane
10% off order* $18.14
Let Freedom Ring.. Solid Wood Sign
5 Vintage France coasters
Made In the USA Sign, Rustic Patriotic Sign, Farmhouse Sign, 11"W x 12.5"H
Vintage Americana Burlap Wreath Bow Rustic Patriotic Burlap Bow July 4th Party Decor Fourth of July Decor Independence Wreath Bow Gift Bow
Fourth of July Pillow Cover Set July 4th Pillows Stars and Stripes Rustic Patriotic Decor Rustic Nautical Decor Rustic July Fourth American
Primitive Flower Arrangement~Americana Decor~Fabric Flowers~Yo Yo Flowers~Primitive Home Decor~Primitive Tablesitter
Set of bald eagle coasters
Vintage Deco No. 2 Darts
Wood Americana Plaque Bee Hive
Patriotic Placemats, Americana Placemats, Rustic Placemats, American Flag Placemats, Ragged Placemats, Americana Decor, Country Decor
American Flag Bunting by Lillypaul Designs
Vintage coasters, shaped like dresses on a hanger, 1960's
RavelingsCoolThings
Set of 6 Vintage Bill O'Shea Western Themed Coasters
Red, White, And Blue Horseshoe, Patriotic Horseshoe, Flag Horseshoe

value: This website is an American e-commerce company focused on handmade or vintage items and craft supplies.


text:
Lees AQ2 Aquarium Divider 10 gallon fish tanks | eBay
View: Gallery view Lees AQ2 Aquarium Divider 10 gallon fish tanks: Lees AQ2 Aquarium Divider 10 gallon fish tanks0 results. You may also like
+C $7.86 shipping	Lees AQ2 Aquarium Divider System For 29/55-Gallon Tanks Pet Supplies Fish & Aqu
+C $8.03 shipping	Lees Aq2 Aquarium Divider System For 29/55-Gallon Tanks Pet Supplies Fish & Aqu
+C $7.86 shipping	Lee's Fish Aquarium AQ2 Divider System 10 Gallon #10600
+C $5.27 shipping	Lee S Aq2 Aquarium Divider System For 15/20L-Gallon Tanks Pet Supplies Fish &
+C $6.43 shipping	Lee's Fish Aquarium AQ2 Divider System 20H Gallon #10610
+C $6.58 shipping	NEW Lees AQ2 Aquarium Divider System for 29 55 Gallon Tanks FREE SHIPPING
Lee's Aquarium AQ2 Divider System 29/55 Gallon #10615
+C $9.22 shipping	Lee's AQ2 Aquarium Divider System for 15/20L-Gallon Tanks New
Lee's AQ2 Aquarium Divider System for 40/60-Gallon Tanks New
Lee's AQ2 Aquarium Divider System for 15/20L-Gallon Tanks LEE10615
+C $7.84 shipping	Tank Divider - 10 Gallon - TDMBX - Penn Plax
+C $4.50 shipping	Aquarium Divider System in Black
API AquaWave Aquarium Kit with LED Lighting and Internal Filter 2-1/2-Gallon New
Lees Protein Skimmer Counter Current Small for aquarium reef tanks
+C $14.68 shipping	Tank Divider - 20 Gallon High - TDELBX - Penn Plax
+C $4.74 shipping	75Gallon Aquarium Acrylic Divider With Holes 4 Suction Cup Seperate Fish 17"x17"
Aquarium Divider System in Black 25 FEET
+C $13.16 shipping	20 Gallon Aquarium Starter Kit with LED Lighting Tanks Fish Internal Filter New
C $11.83 to C $29.60
10 Gallon 9.8"x11" Tank Aquarium Acrylic Divider With Holes 4 Suction Clips
Hawkeye Starter Aquarium Fish Tank Easy Install Kit LED Lights, 5 Gallons
NEW: Tetra Whisper 10i Internal Aquarium Filter for 2-10 Gallon Tanks
+C $12.44 shipping	Cascade Quality Hang-on Power Aquarium Filter. Up to 100 Gallon Fish Tanks, New
Aquarium Air Pump for 60 to 100 Gallon Fish tanks
+C $13.50 shipping	Fish Aquarium Tank Tropical Aquarius 2.5 Gallon LED Kit Sturdy Acrylic LED Light

value: This website is an American multinational e-commerce corporation based in San Jose, California, that facilitates consumer-to-consumer and business-to-consumer sales through its website.


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Leather bracelet cow leather Brown leather Designer toggle
This listing is for a brown leather/suede bracelet that is 8 inches long including toggle. It has a silver plated designer toggle and all other silver is also silver plated. It is a statement piece and will go with almost anything.
Bracelet 10mm cow leather for men. 925 sterling silver Claps. Light beige
Southwestern Style Leather Bracelet with Cow Skull
Brown leather wrap bracelet for women, charm bracelet, turquoise boho bracelet, stack bracelet, hipster bracelet, cow leather bracelet.
Designer Toggle Clasp -Sterling Silver (#5087)


text:
Patent US20020006171 - Low phase noise frequency converter - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsOne aspect of the present invention is a frequency conversion circuit having a pair of local oscillators. The local oscillators are frequency synthesizers based on an external frequency reference. The frequency conversion circuit is configured to perform a frequency conversion to an input signal equal...http://www.google.com/patents/US20020006171?utm_source=gb-gplus-sharePatent US20020006171 - Low phase noise frequency converterAdvanced Patent SearchPublication numberUS20020006171 A1Publication typeApplicationApplication numberUS 09/899,430Publication dateJan 17, 2002Filing dateJul 5, 2001Priority dateJul 6, 2000Also published asCA2352398A1, CA2352398C, DE60128518D1, DE60128518T2, EP1175008A2, EP1175008A3, EP1175008B1, US6968017Publication number09899430, 899430, US 2002/0006171 A1, US 2002/006171 A1, US 20020006171 A1, US 20020006171A1, US 2002006171 A1, US 2002006171A1, US-A1-20020006171, US-A1-2002006171, US2002/0006171A1, US2002/006171A1, US20020006171 A1, US20020006171A1, US2002006171 A1, US2002006171A1InventorsGert NielsenOriginal AssigneeNielsen Gert LyngeExport CitationBiBTeX, EndNote, RefManReferenced by (17), Classifications (25), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetLow phase noise frequency converterUS 20020006171 A1Abstract One aspect of the present invention is a frequency conversion circuit having a pair of local oscillators. The local oscillators are frequency synthesizers based on an external frequency reference. The frequency conversion circuit is configured to perform a frequency conversion to an input signal equal to a frequency difference of signals from the pair of local oscillators; to generate an oscillator frequency difference signal; to generate an error signal using the oscillator frequency difference signal and an internal reference signal derived from the external frequency reference; and to adjust a phase of one of the pair of oscillators using the error signal. The above-described frequency conversion circuit embodiment essentially eliminates divider phase noise such as that generated by traditional prescalers. In addition, the use of two local oscillators provides a frequency conversion circuit capable of wide-range frequency conversion and high resolution. This frequency conversion circuit embodiment is suitable for receivers as well as transmitters, and is particularly suitable for digital television systems. Images(8) Claims(20)
[0024] In one embodiment, the shortened RS code is implemented by adding 51 bytes, all set to zero, before information bytes input to a (255, 239, t=8) encoder. After encoding, the null bytes are discarded. Outer interleaving follows with depth I=12, and packets are delimited by inverted or non-inverted MPEG-2 sync bytes, preserving the periodicity of 204 bytes. Inner coding using a range of punctured convolutional codes is provided to allow selection of an appropriate level of error correction. An inner interleaver provides bit-wise interleaving followed by symbol interleaving. [0025] The mapped data from mapper 58 is applied to a frame adapter 60, which adapts the data to either 2K or 8K frames, as appropriate. Each frame is 68-OFDM simple, where �OFDM simple� is 204 bytes. Pilot or transmission parameter signaling (TPS) is applied by Pilot/TPS unit 62. The output of frame adapter 60 is provided as the input of IFFT (Digital OFDM) modulator 64. IFFT 64 calculates an envelope of the input signal, converting its time-domain input into the frequency domain. IFFT 64 thus determines which information from its input will be carried on which carrier frequency. Guard interval inserter 66 provides information to IFFT 64 concerning the required guard intervals, as well as the modulation type and code rate. [0026] The output of IFFT 64 is input to limiter/precorrector 68, which checks the digital values output by IFFT 64 to prevent overload of DAC (Digital to Analog Converter) 70 and subsequent components in modulator 12. Limiter/precorrector 68 applies clipping as necessary to prevent overload. DAC 70 produces a base band (or first IF signal) 72 that is either a 9.1428571 MHz signal (corresponding to an 8 MHz bandwidth UHF channel) or an 8 MHz signal (corresponding to a 7 MHz VHF channel). In other embodiments, base band signals having different characteristics are produced to correspond with different standards. [0027] In the embodiment exemplified by FIG. 2, a base band signal output by DAC 70 is upconverted by IF converter 74. For example, an IF frequency of 36.0 MHz is used. The output of IF converter 74 is filtered with a band pass filter 76 and amplified by output IF amplifier 78. The IF signal is converted to a suitable RF signal 82 by RF converter 84. RF signal 82 can be further amplified or processed, depending upon the application in which modulator 12 is used. [0028] In one embodiment and referring to FIG. 3, DTV modulator 12 comprises a microprocessor 86 and associated memory 88, an application specific integrated circuit (ASIC) 90, a digital to analog converter (DAC) 70, and analog circuitry 92. The architecture of modulator 12 in this embodiment provides an advantage of allowing instruction set changes without hardware redesign. In particular, functions of blocks 40, 42, 44, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, and/or 68 are divided between ASIC 90 and microprocessor 86 (and its associated memory 88). For example, in one embodiment, ASIC 90 performs the functions of IFFT 64 and limiter/precorrector 68, while microprocessor 86 performs the functions of guard interval inserter 66 and blocks preceding block 64 in the processing chain. Analog circuit 92 performs the functions of IF converter 74, band pass filter 76, output IF amplifier 78 and RF converter 84. [0029] In one embodiment IFFT 64 is embodied in ASIC 90 and comprises a plurality of signal processors to generate carriers with excellent resolution to provide the high speed operation that is necessary for handling high speed data streams. For example, ten signal processors are provided, each with sixteen-bit accuracy to provide improved resolution. [0030] More particularly, in one embodiment, 6,817 carriers are used in an 8 MHz band to provide high speed. The 8 MHz bandwidth is achieved by using the large number of equally spaced carriers. In another embodiment, approximately 8,000 carriers are available for data modulation, and error correction and interleaving techniques are used so that signals can be recovered even if a number of these carriers are lost. A guard interval is provided to freeze a signal so that the receiver has time to detect a television signal. Once the signal is stable for a period of time, the receiver can then start displaying the demodulated signal. [0031] In one embodiment and referring to FIG. 4, COFDM (Coded Orthogonal Frequency Division Multiplexing) modulator 93 calculates the envelope of the signal and converts signals from the time domain into the frequency domain. COFDM coder module 93 replaces components having common reference designations between FIGS. 2 and 4. These components have similar functions in these two figures. However, hierarchical mode uses two identical channels as indicated by the duplication of blocks 40, 42, 48, and 50 in FIG. 4. In addition, some of the blocks in FIG. 4 have additional functions that are described below. In the embodiment represented in FIG. 4, each block is connected to a clock (N*Fsys) 94 and to control 96. Data input and output is synchronous to N*Fsys. [0032] The basic requirements for SFN timing is to (1) find MIP (Megaframe Information Package) that holds information about Megaframe ID and time; (2) identify a Megaframe in a signal; and (3) assure that the megaframe after all the processing is output at a specified time. An SFN delay module supplies all of the required delay and identifies the megaframe by supplying a �megaframe sync� following the first data item in a megaframe. The delay module creates a feed-forward signal used to open the output stream when synchronized to an SFN signal. (This function is initialization of the SFN operation.) When initialized, the feed-forward signal and the megasync output signal continue to be aligned because the total SFN system is fully synchronous. [0033] Because of strict timing requirements for SFN, a system designed for SFN operation can use the same timing for most circuits in MFN timing. More particularly, except for timing requirements, blocks from a sync inverter and the rest of the instrument have no special SFN/MFN requirements. In one embodiment, MFN timing attempts to simulate an SFN system at the input of the sync inverter, thereby making the most of the blocks independent of MFN/SFN mode. [0034] COFDM coder module 93 includes an input adapter 40. Input adapter 40 accepts inputs of eight data lines, a clock line, a data valid line, and a sync line, although the use of sync line is optional. Outputs of input adapter 40 include eight data lines, a clock line, a data valid line, and a sync line. Input adapter 40 also provides information to a controller, including a sync locked indicator and a indicator of packet size (i.e., whether the received packet size is 188 or 204 bytes), which is detected by automatic synchronizing with the input data. Input adapter 40 provides a flexible input to enable different electrical interfaces, and accepts jitter from transmission including ASI in burst mode. Output data rates for COFDM coder module 93 range from 450 kbytes/sec to 4.5 MB/sec. Data output from input adapter 40 is a predefined function when no data is input and, in this embodiment, is always converted to 204 byte packets at the output regardless of the received packet size. [0035] Transport stream inputs can have clock jitter from different parts of the distribution network, and is attenuated when it is above a predetermined frequency to assure proper operation of the TSA network. [0036] Transport stream adapter 42 of FIG. 4 includes a rate adaptation module (not separately illustrated) that accepts outputs of input adapter 40 as inputs. In addition, there is a reference input 94 having a frequency of N�Fsys, where Fsys is the system clock frequency. The rate adaptation module provides eight data lines of output, one data enable line, one sync line, and one �megasync� line 98. The output, in one embodiment, has a packet size of 204 bytes (which includes 16 dummy bytes when Reed-Solomon coding is not used). The sync output follows the first data byte in a packet, whereas megasync output 98 follows the first data byte in each �megaframe.� In one embodiment (MFN, or Multiple Frequency Network), the first megaframe is selected at random, and is used only to simulate the same output as SFN uses at this interface. The actual output rate is controlled by an �enable� input from a data receiver. The number of packets in a megaframe is used for megasync generation, and to force the insert of stuffing into the data stream. [0037] In one embodiment, the rate adaptation module of transport stream adapter 42 calculates a data rate from the mode, where there is a different rate for 6, 7, and 8 MHz. Also in one embodiment, stuffing packets that are received are deleted, and stuffing packets are delivered when no input packets are ready. Thus, the rate adaptation module is functional even if its input rate is zero. When the data rate is changed in a transport stream, the PCR (Program Clock Reference) packets are restamped according to their packet position in the stream. [0038] The output of the rate adaptation module is input to an SFN delay module (which, in one embodiment, is bypassed in MFN). (The SFN delay module is part of transport stream adapter 42 and is not separately shown in FIG. 4.) The input is arranged as 204 byte packets, with 16 dummy bytes when RS encoding is not used. A reference input 94 is also provided at a frequency of N�Fsys, as a system clock. In one embodiment, all SFN timing is in 100 nsec resolution with reference to this signal. A 1 pps (pulse per second) reference signal 22 is also provided for megaframe output timing. The output of the SFN delay module includes eight data lines, one data enable line, one sync line, and one megasync line 98. The output is arranged in 204 byte packets with RS encoded bytes, with a sync output following the first data byte in a packet. In addition, a megasync output follows the first data byte in each megaframe. An addition �mega request� output 98 is provided as a feed-forward signal to enable/synchronize megaframe output with exact timing. [0039] The number of packets in a megaframe can be used for acceptance of a single missing MIP. A time offset (i.e., a programmable offset from MIP defined) is used to compensate for transmitter delay. In one embodiment, SFN delay module is forced to insert stuffing bytes under conditions of no input, and information fields are output from MIP frames. [0040] The SFN delay module operates as a FIFO (first in, first out register), providing up to 1 second of delay. The SFN delay module also extracts timing information to generate megarequest signal 98. [0041] The output of SFN delay module is provided to a sync inverter module (not separately shown in FIG. 4, but which is a part of scrambler 48 in the embodiment represented therein). The Sync inverter module inverts all of the bits in every eighth packet, and passes this data to a scrambler module (also not separately shown, but part of scrambler 48). The scrambler module synchronizes to the eight packet sequence produced by sync the inverter module and adds a PRBS (Pseudo-Random Binary Sequence) to the signal. [0042] The output of scrambler 48 is arranged as 204 byte packets including 188 data bytes and 16 dummy bytes. This input is provided to a Reed Solomon encoder 50, which replaces the 16 dummy bytes with a Reed-Solomon checksum. An outer interleaver (not separately shown, but part of Reed Solomon encoder 50 in the embodiment of FIG. 4) operates on the Reed-Solomon encoded packets to produce interleaved output. A megasync output follows the first data byte in each megaframe as data leaves the outer interleaver, and interleaving is provided. An inner coder module (not shown, but part of Reed Solomon encoder 50 in the embodiment of FIG. 4) has eight lines of input data, one data enable input, and one megasync indicator line, and produces output data on two, four, or six data output lines. The number of lines used for data output is dependent upon a selected mode of operation. A data enable line and a megasync line are also output. A megasync output follows the first data in each megaframe. In hierarchical mode, the megasync output is the last part of the two independent input channels. A code rate control and a mode control (to select two, four, or six bit mode) are also input to the inner coder module, which implements a punctured convolutional coder initialized using a signal on megasync line. [0043] The six data lines, data enable line, and two megasync lines from code rate control are input to a bit interleaver module (not separately shown, but part of Reed-Solomon encoder 50 in the embodiment of FIG. 4). The data input to the bit interleaver module depends upon the data constellation and the hierarchical mode. For example, depending upon which non-hierarchical mode is operational, either two, four, or six data lines are active and input from an HP (High Priority) bit stream channel. In a hierarchical mode, there is only one megasync from each channel, and input data is two bits from one channel and either two or four bits from the other channel. The bit interleaver module provides outputs on two, four, or six data lines, depending upon mode. Bit interleaver module also provides one data enable line and one megasync line. Bit interleaver module operates as up to as many as six independent interleavers. By taking input from two channels, this module also serves as a combining point for hierarchical mode. An interleaving depth of 126 bits is provided in one embodiment. [0044] A byte interleaver module (not separately shown, but part of Reed Solomon encoder 50 in the embodiment of FIG. 4) operates on the output of the bit interleaver module. More specifically, six data lines, one enable line, and one megasync line provide inputs for the byte interleaver module, although only two or four of the six data lines are active in some modes. Correspondingly, the same number of the six data line outputs are active. The byte interleaver module also provides a data enable line output, a sync output, and a megasync output line. The byte interleaver module generates blocks of data, where one block fits into one IFFT block, by interleaving in a block size equal to the data capacity of one IFFT symbol. In one embodiment, the byte interleaver module operates by writing data in an address pattern, and then reading linearly, so that interleaving is done in one symbol. The next symbol works in the opposite direction so that the reading address of one symbol is used as the writing address of the next symbol in the same memory. The memory of byte the interleaver module in one embodiment is 6048 six-bit words. [0045] Pilot inserter module 62 receives six data lines from the byte interleaver module of Reed-Solomon encoder 50, a data enable line, a sync line, and a megasync line. (In some modes, only two or four of the six data lines are active.) In addition, for TPS (Transmission Parameter Signaling) modulation, pilot inserter module 62 receives control information 96 to determine a mode of operation. The output of pilot inserter module 62 is a stream of complex data represented as constellation indices. More particularly, in one embodiment, two four-bit data lines are output. A data enable line is also provided as output, as is a sync line and a megasync line. These outputs of pilot inserter module 62 are provided as inputs to mapper module 100. Mapper module 100 receives the stream of complex data represented by constellation indices and converts this stream into a stream of complex data represented as two words, which, in one embodiment, are sixteen bits each. A control input 96 of mapper module 100 determines a type of constellation. In one embodiment, selectable constellation types are QPSK (Quaternary Phase Shift Keyed), 16-QAM (Quadrature Amplitude Modulated) non-hierarchical (or hierarchical and α=1), 64-QAM non-hierarchical (or hierarchical and α=1), 16-QAM hierarchical α=2, 16-QAM hierarchical α=4, 64-QAM hierarchical α=2, and 64-QAM hierarchical α=4. Mapper module 100 translates each input from index to actual modulation amplitude. In one embodiment in which the mapper function is implemented in an IFFT chip, an optional bypass control is provided for mapper module 100. [0046] IFFT module 64, which in one embodiment is a single chip module, inputs blocks of 8K or 2K complex data through a 16-bit parallel interface from mapper module 100. IFFT module 64 produces corresponding blocks of 8K or 2K complex data at 16-bit interface. The input and output are both 16-bit parallel interfaces in the same format. IFFT 64 also has control inputs including an FFT (Fast Fourier Transform) size selection, an IFFT/FFT selection, and a scale control. In one embodiment, support is provided for 4K (Japanese OFDM), and 1K, 512, 256, and 64 (Wireless LAN) blocks of complex data. [0047] Guard interval insertion module 66 receives blocks of 8K or 2K complex data from IFFT module 64 through a 16-bit parallel interface. Guard interval insertion module 66 processes this data and outputs blocks of 8K or 2K complex data (depending upon which is input) plus a guard interval length. A sync signal is active during the guard interval. The guard interval is selectable from a plurality of values depending upon a state of control 96. In one embodiment, for example, the guard intervals are selected from �, ⅛, {fraction (1/16)} and {fraction (1/32)}. The guard interval is a copy of the last part of the IFFT-result, and is inserted before the main part. The output of guard interval insertion module 66 is applied to an output enable switch 102, which is used to create an exact timed output condition when starting an SFN transmission. Output enable switch 102 receives a continuous I & Q base band stream sampled at Fsys. A resync signal is also input. This signal causes output enable switch 102 to restart an SFN synchronization sequence by outputting data until a megasync is received, and stopping output until a megasync out request is received. Output enable switch 102 produces I & Q base band outputs 72, a symbol sync output 104, a delayed sync output, and a request data output. Symbol sync output 104 is active during guard band data, and inactive during non-guard band data. The delayed sync output is presented to an external connector for measurement purposes. Two bits are provided, one of which is a symbol sync, which is active during a guard interval, and the other is a megasync, which is active during a guard interval of a first symbol in a megaframe. In one embodiment, the outputs of output enable switch 102 are delayed by a programmable amount to compensate for other instrument delays. The request data output is used to indicate a data request to a preceding functional block. [0048] Functionally, modulator 93 is a single-board Dvb-T modulator that can be used in a variety of applications. For example, it can be used in a unit having a U base cabinet with reference design and IF/UHF circuits, or it can be customized for specific transmitters. One embodiment of modulator 92 is in VHDL (VHSIC [very high speed integrated circuit] Hardware Description Language), so that it can be programmed into a single FPGA (Field Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit). Depending upon the embodiment, some external memory may be required. [0049] In operation, one embodiment of the present invention includes instrument control via a front panel, a remote control, and via an MIP frame in an SFN transport stream. An additional remote interface is also provided for precorrector on-line correction, and control from transport stream disconnect is possible. Also provided is a front panel setting menus lock, automatic memory for restart with correct settings after power off, three or more memories for instrument settings, and separate memories for precorrector settings. A clock reference input and a time reference input are provided. An input indicator provides indications of data present, clock recovered (for serial input), input data overflow/underflow, sync 188 byte present, sync 204 byte present, MIP present (for SFN signals) and input data rate. Supported modes are 2K or 8K IFFT, guard intervals of �, ⅛, {fraction (1/16)}, {fraction (1/32)}, and code rates of �, ⅔, �, ⅚, and ⅞ (independent for LP and HP). Constellations provided are QPSK, 16-QAM, and 64-QAM. Mapping is uniform (alpha=1), alpha=2, and alpha=4. Full support is provided for hierarchical mode. All SFN input bit rates are supported, as well as MFN bit rates according to selected mode, +0%/−20%. No input generates defined internal signal: zero-frames. Supported bandwidths are 8 MHz, 7 MHz, and 6 MHz. [0050] Signal delay is compatible with SFN, with a maximum delay up to 999 msec, and minimum delay of 50 msec (implementation delay). Full I & Q amplitude and phase correction is provided, and linearity precorrection is programmable. Three or more settings are stored in a nonvolatile memory. Transport stream is substituted by zero-frames if there is no input, and muting RF/IF output is selectable. Test signals provided are removed carriers (selectable position and width, to test IM noise, etc.), single carrier (center frequency) RMS level like normal signal (converter alignment, phase noise), an internal 223−1 PRBS, other PRBS sequences, three insertion points for PRBS, and zero-frames. [0051] In one embodiment and referring to FIG. 5, low phase noise and high frequency resolution is achieved by RF converter 84. The RF converter includes a first frequency synthesizer 206, a second frequency synthesizer 208, a first mixer 176, a second mixer 178, a difference mixer 142, a sampling mixer 154 and a pulse train generator 210. An IF signal 80 from the IF output amplifier 78 (FIG. 2) is input into signal path 170. The signal path 170 includes the first and second mixers 176, 178 and outputs the RF signal 82. The first mixer 176 receives a signal from the first frequency synthesizer 206 at frequency f1 and the second mixer 178 receives a signal from the second frequency synthesizer 208 at frequency f2. The signals from the first frequency synthesizer 206 and the second frequency synthesizer 208 are also input into the difference mixer 142. The output of the difference mixer 142 is connected to the sampling mixer 154. Also connected to the sampling mixer 154 is the pulse train generator 210. The output of the sampling mixer 154 is an error signal 156 that is provided to the second frequency synthesizer 208. The first frequency synthesizer 206, the second frequency synthesizer 208 and the pulse train generator 210 each receive a reference signal 152 as an input. [0052] In operation, the RF converter 84 shifts the frequency of the IF signal 80 to produce the RF signal 82. The shift in the frequency of the IF signal 80 occurs through the signal path 170 wherein the first mixer 176 causes the IF signal 80 to be shifted upwards by f1 and the second mixer 178 causes the signal from the first mixer 176 to be shifted downwards by f2. The RF signal 82 is therefore the IF signal 80 shifted in frequency by f1−f2. The signals f1 and f2 are created by the first frequency synthesizer 206 and the second frequency synthesizer 208, respectively. The frequency synthesizers 206, 208 are programmed such that the difference between their respective frequencies is the desired frequency shift in the IF signal 80. [0053] The accuracy of the frequency shift is maintained through a sampling circuit that measures the frequency shift and generates an error signal 156 that causes the second frequency synthesizer 208 to adjust its signal f2. The signals f1 and f2 are input into the difference mixer 142, which outputs a difference signal 148 at the frequency f2−f1. This signal is input into the sampling mixer 154. Also input into the sampling mixer 154 is a low-frequency reference signal 150 generated by the pulse train generator 210. The low-frequency reference signal 150 is a clean, synthesized low-frequency reference signal that has an Nth order harmonic at a frequency corresponding to the desired frequency shift in the IF signal 80. The low-frequency reference signal 150 is a train of delta pulses. [0054] The sampling mixer 154 receives the low-frequency reference signal 150 and the difference signal 148 and generates an error signal 156. The combination of the pulse train reference signal 150, having an Nth order harmonic at the desired frequency shift, and the difference signal 148 results, through aliasing, in an error signal 156 with a low frequency component representative of the difference between the desired frequency shift and the actual frequency shift. The error signal 156 is provided to the second frequency synthesizer 208, which adapts the frequency f2 accordingly to minimize the error signal. [0055] The comparison of the actual frequency shift with a reference signal using a harmonic of the reference signal and the aliasing effects of sampling results in less phase noise because it constitutes a purely mathematical operation, whereas a comparison of the frequency shift with a reference signal using a division circuit introduces significant phase noise due to the circuitry involved in the divider. By eliminating the divider phase noise, the overall performance of the circuit is improved. [0056]FIG. 6 shows in greater detail a block diagram of one embodiment of the RF converter 84. In the embodiment shown in FIG. 6, a direct digital synthesis (DDS) circuit 122 supplied with a clock signal 124 derived from a crystal oscillator is used to produce a clean, agile frequency reference. DDS circuit 122, for example, is a combination of a numerically controlled oscillator (NCO), a multiplier, a D/A converter and a comparator. DDS circuit 122 is a used for generation of a clock signal with a programmable frequency. In one embodiment, the operating frequency of DDS circuit 122 is programmed to be an integer fraction of the difference between the two local oscillators 130 and 132, i.e., (f2−f1)/N, where N is chosen so that DDS circuit 122 output frequency is the highest possible frequency below 20 MHz. [0057] The upward change in frequency between IF signal 126 and RF signal 82 is determined by the frequency difference between two synthesized local oscillators 130 and 132. In one embodiment, the frequency range of local oscillator 130 adapts different IF frequencies from 36 to 54 MHz to 1260 MHz bandpass filter 204. Also in one embodiment, the frequency range of local oscillator 132 is determined by a desired output frequency from −100 MHz to +1000 MHz, so that in the range 0-100 MHz, the converter is capable of delivering inverted and non-inverted spectrum output. [0058] Samples 134, 136 of the signals from oscillators 130 and 132 split off using splitters 138 and 140, respectively, are compared using mixer 142. (In one embodiment, mixer 142 is fed with different signal levels provided by amplifiers 198 and 200 because one signal is connected to an LO port of mixer 142 and the other to an RF port of mixer 142.) Output 144 of mixer 142 is low-pass filtered 146 to obtain a compared difference frequency signal 148 between oscillators 130 and 132. This difference frequency is compared with a harmonic of a clean, synthesized, harmonically generated low-frequency reference signal 150 derived from reference signal 152, which itself is used to as a reference for oscillators 130 and 132. The comparison between reference signal 152 and difference signal 148 utilizes a sample detector or mixer 154. Error signal 156 is amplified and applied as a correction to oscillator 132. [0059] A frequency setting is initiated by programming two ordinary frequency synthesizers 162, 164 to a frequency close to a desired frequency, within step size limitations. When lock is achieved, switches 190 and 192 are used to substitute synthesizer 164 with a control voltage from sample detector amplifier 198. Provided that the frequency difference between the first frequency setting and the final determined by DDS 122 is smaller than the lock-in range for the sample detector loop, oscillator 164 will adjust so that the frequency difference f2−f1=N*fDDS. Thus, the step sizes of frequency synthesizers 162 and 164 can be selected for practical reasons, as they have no influence on the final frequency resolution, which is determined solely by N times the DDS 122 step size. In one embodiment, this frequency resolution can be in the milli- or microHertz range. [0060] The relationship between synthesized reference signal 150 and low frequency reference ensures that the divider phase noise of traditional prescalers is essentially eliminated, while the use of an internal reference frequency generated by DDS122 provides enhanced frequency resolution as the DDS is capable of very fine frequency stepping. [0061] IF output 80 of IF amplifier 78 is mixed with the output frequency f1 of first oscillator 130, which in one embodiment is a frequency between 1206 and 1224 MHz that is adjustable in 25 kHz steps 162. Upconverted signal 202 centered at about 1260 MHz and is sent through a band pass filter 204 and a notch filter 158 to remove unwanted mixing products and to limit signal bandwidth. In one embodiment, the bandwidth of band pass filter 204, is 20 MHz to assure flat amplitude and group delay response within an OFDM channel bandwidth (8 MHz). Notch filter 158 is provided to suppress leakage from local oscillator 130. [0062] A further conversion takes place when filtered, upconverted signal 160 is mixed with output frequency f2 of second oscillator 132, which in one embodiment ranges between 1160 and 2260 MHz in 1 MHz steps 164. The resulting output signal 166 is passed through low pass filter 168 to remove unwanted mixing products and to produce an RF DTV signal 82 in the VHF or UHF band. [0063] More particularly, if IF output 80 is characterized by an IF frequency fIF, the frequency of RF DTV signal 82 is fRF=(f2−f1)−fIF. The use of small frequency steps for first oscillator 130 and larger frequency steps for second oscillator 132 achieves a wide output frequency range at high frequency resolution. Low phase noise is achieved because the frequency difference (f2−f1) is compared with a signal 150 derived from a clean version 152 of external reference 20 and the phase difference is used as feedback for the second oscillator 132. [0064] The choice of a smaller frequency range and step size for first oscillator 130 compared with that of second oscillator 132 makes it more convenient to design filters 204 and 158 for a specified IF frequency fIF, but these relationships are not required in all embodiments. Embodiments having different filtering configurations for signal path 170 can be designed so that the frequency of RF DTV signal 82 is fRF=|(f1−f2)−fIF| rather than fRF=|(f2−f1)−fIF|. However, the design choices illustrated in the embodiment of FIG. 9 simplify tuning of RF converter 84 and the design of signal path 170. [0065] Amplifiers and attenuators such as 172, 174 and others not specifically numbered are provided in RF converter 84 to optimize signal levels in the circuit in one embodiment. Such circuit optimizations are considered to be within the capability of one of ordinary skill in the art upon achieving an understanding of the present invention. [0066] In another embodiment of RF converter 84, phase difference error signal 156 is fed back to first oscillator 130 rather than second oscillator 132. Because the total frequency conversion is based on the frequency difference (f2−f1), this embodiment also achieves reduction of phase noise from RF output signal 82. [0067] In another embodiment, RF converter 84 is configured as a downconverter stage for a DTV receiver. In this case, signal 126 is or is derived from a received RF signal. IF amplifier 78 is eliminated or optionally replaced by a suitable RF amplifier. Filters in signal path 170 select mixing products from mixers 176 and 178 so that output 82 of signal path 170 is a baseband or an IF signal, where either fIF=|(f1−f2)−fRF| or f IF=|(f2−f1)−fRF|, depending upon a design choice implemented by the filtering. [0068] In one specific transmitter embodiment, RF converter 84 accepts an IF input signal 126 characterized by an IF frequency between 36 and 54 MHz. For example, let us assume IF input signal 126 is characterized by a 46 MHz IF frequency, first oscillator 130 is set by frequency synthesis to a frequency of 1210.025 MHz and second oscillator 132 is set by frequency synthesis to a frequency of 1950 MHz. The first mixing product 180 (which is selected by filtering) is the mixing product at 1256.025 MHz. The second mixing product 182 selected by low pass filter 168 is 693.975 MHz, which is the frequency of RF output signal 82. In this example, fRF=|(f2−f1)−fIF|, where fIF=46 MHz, f1=1210.025 MHz, and f2=1950 MHz. [0069] Other features of the embodiment illustrated in FIG. 6 include two D/A converters (shown as 184) controlling IF gain (A) and loop gain(B), a PC bus expander 186, which is an I2C bus device with 8 logic outputs, and EEPROM 188, which is a memory for calibration data, for example, gain and frequency dependency. Modules 78, 122, 162, 164, 184, 186, 188, 190, 192, 194, 196, and 198 are controllable via remote control. [0070] In one receiver embodiment, the input signal to signal path 170 is an RF signal rather than an IF signal, the output signal is an IF signal, and RF signal is first mixed with a wide-range, coarse tuning oscillator followed by a narrow-range, fine-tuning oscillator. (In other words, the positions of oscillators 130 and 132, as well as their synthesizer inputs 162, 164, and other associated components and correction inputs are exchanged.) An RF input signal at 693.975 MHz, for example, is first mixed with a 1950 MHz signal to obtain a mixing product at 1256.025 MHz, which is band-pass filtered. This product is then down-converted with a 1210.025 MHz local oscillator signal to product a 46 MHz IF signal. In this example, fRF=693.975 MHz, f1=1210.025 MHz, and f2 =1950 MHz., and fIF=|(f2−f1)−fRF|. [0071] Reference is now made to FIG. 7, which shows a block diagram of an RF converter 84′, which is an alternative embodiment of the RF converter 84 of FIG. 5. Like reference numerals in the Figures correspond to like components. The RF converter 84′ shown in FIG. 7 functions similar to that shown in FIG. 6 except for differences that will be apparent from the following description. It will be noted that the alphabetic control signal designations vary and are not identical between FIG. 6 and FIG. 7. [0072] In the RF converter of 84′, the first frequency synthesizer 206 includes a frequency synthesizer 162, a local oscillator 130, a splitter 138, a loop filter 131 and an amplifier 172. The reference signal 152 and control signal B are input into the frequency synthesizer 162. The output of the frequency synthesizer 162 is connected to the local oscillator 130 through the loop filter 131. The local oscillator 130 outputs a signal which passes through the splitter 138. The splitter 138 has three outputs. One of the outputs from the splitter 138 is connected to the frequency synthesizer 162 to establish a feed back loop. Another output of the splitter is connected to the difference mixer 142 through an amplifier 198. The third output from the splitter 138 is connected to the amplifier 172, which produces the signal f1 that is provided to the first mixer 176. [0073] The second frequency synthesizer 208 includes a frequency synthesizer 164, a local oscillator 132, a splitter 140, a loop filter 133, an amplifier 173 and a switch 190. The reference signal 152 and control signal D are input into the frequency synthesizer 164. The output of the frequency synthesizer 164 is connected to the local oscillator 132 through the switch 190 and the loop filter 133. The local oscillator 132 outputs a signal which passes through the splitter 140. In a similar fashion as to the first frequency synthesizer 206, the outputs of the splitter 140 are connected to the difference mixer 142, the frequency synthesizer 164 and to the second mixer 178. The switch 190 receives the error signal 156 and a control signal E. The switch 190 selects whether the local oscillator 132 receives a signal from the frequency synthesizer 164 or the error signal 156. [0074] The upward change in frequency between IF signal 126 and RF signal 82 is determined by the frequency difference between the two synthesized local oscillators 130 and 132. In one embodiment, the frequency range of local oscillator 130 adapts different IF frequencies from 36 to 44 MHz up to 1260 MHz. Also in one embodiment, the frequency range of local oscillator 132 is determined by a desired output frequency from 30 MHz to 1000 MHz. Accordingly, the frequency range of local oscillator 132 is 1290 MHz to 2260 MHz, which therefore adapts the 1260 MHz signal from the first mixer 176 to 30 MHz to 1000 MHz. [0075] Samples 134,136 of the signals from oscillators 130 and 132 split off using splitters 138 and 140, respectively, are compared using the difference mixer 142. (In one embodiment, the difference mixer 142 is fed with different signal levels provided by amplifiers 198 and 200 because one signal is connected to an LO port of the difference mixer 142 and the other to an RF port of the difference mixer 142.) An output 144 of the difference mixer 142 is low-pass filtered 146 to obtain the difference frequency signal 148 between the oscillators 130 and 132. This difference frequency signal 148 is compared with a harmonic of the clean, synthesized, low-frequency reference signal 150 derived from the reference signal 152, which itself is used to as a reference for the oscillators 130 and 132. The comparison between the low-frequency reference signal 150 and the difference signal 148 occurs using the sample mixer 154. Error signal 156 is amplified through an amplifier 196 and applied as a correction signal to oscillator 132. [0076] Referring still to FIG. 7, the pulse train generator 210 is implemented using a direct digital synthesis (DDS) circuit 122 supplied with a clock signal 124 to produce a clean, agile frequency reference. DDS circuit 122, for example, is a combination of a numerically controlled oscillator (NCO), a multiplier, a D/A converter and a comparator DDS circuit 122 is used for generation of a clock signal with a programmable frequency. In one embodiment, the operating frequency of DDS circuit 122 is programmed to be an integer fraction of the difference between the two local oscillators 130 and 132, i.e., (f2−f1)/N, where N is chosen so that DDS circuit 122 output frequency is the highest possible frequency below 30 MHz. In other words, the difference between the two local oscillators' 130, 132 frequencies corresponds to the Nth order harmonic of the operating frequency of the DDS circuit 122. [0077] The pulse train generator 210 is further implemented using a low pass filter 212, a comparator 214 and a comb generator 216. The low pass filter 212 filters out aliasing products from the DDS circuit 122 to create a clear sinusoidal signal. The comparator 214 clips the sinusoidal signal from the DDS circuit 122 to a square wave. The comb generator 216 then converts the square wave to a train of delta pulses synchronized to the leading edges of the square wave. The resulting low-frequency reference signal 150 is a clean, synthesized low-frequency pulse train reference signal that has an Nth order harmonic at a frequency corresponding to the desired frequency shift in the IF signal 80. [0078] The pulse train generator 210 is supplied with a clock signal 124 derived from an external 10 MHz reference signal 20. The external reference signal 20 is buffered 218 and then the buffered reference signal 152 is input into the frequency synthesizers 162, 164 and an 80 MHz PLL 220. The 80 MHz PLL 220 is an 80 MHz crystal locked to the 8th order harmonic of the 10 MHz reference. The loop bandwidth is very low, so phase noise from the external reference signal 20 is suppressed. The 80 MHz PLL 220 provides the 80 MHz clock signal 124 used by the DDS circuit 122. [0079] In operation, a frequency setting is initiated by programming the two frequency synthesizers 162, 164, using control signals C and D, to a frequency close to a desired frequency, within step size limitations. When lock is achieved, switch 190 is used to substitute synthesizer 164 with the error signal 156 from amplifier 198. Provided that the frequency difference between the first frequency setting and the final determined by DDS circuit 122 is smaller than the lock-in range for the sample detector loop, oscillator 132 will adjust so that the frequency difference f2−f1=N*fDDS. Thus, the step sizes of frequency synthesizers 162 and 164 can be selected for practical reasons, as they have no influence on the final frequency resolution, which is determined solely by N times the DDS circuit 122 step size. In one embodiment, this frequency resolution can be in the milli- or microHertz range. [0080] Referring still to FIG. 7, the signal path 170 includes the first and second mixers 176, 178, the IF amplifier 78, a bandpass filter 204, a notch filter 158, a low pass filter 168 and various amplifiers and attenuators, as required. The IF output 80 of the IF amplifier 78 is mixed with the output signal f1 of the first local oscillator 130, which in one embodiment is a frequency between 1216 and 1224 MHz that is adjustable in 25 kHz steps 162. Upconverted signal 202 centered at about 1260 MHz is sent through the band pass filter 204 and the notch filter 158 to remove unwanted mixing products and to limit signal bandwidth. In one embodiment, the bandwidth of band pass filter 204, is 20 MHz to assure flat amplitude and group delay response within an OFDM channel bandwidth (8 MHz). Notch filter 158 is provided to prevent leakage from the first local oscillator 130. [0081] A further conversion takes place when filtered, upconverted signal 160 is mixed with output signal f2 of the second local oscillator 132, which in one embodiment ranges between 1290 and 2260 MHz in 1 MHz steps 164. The resulting output signal 166 is passed through low pass filter 168 to remove unwanted mixing products and to produce an RF DTV signal 82 in the VHF or UHF band. [0082] More particularly, if IF output 80 is characterized by an IF frequency fIF, the frequency of RF DTV signal 82 is fRF=(f2−f1)−fIF. The use of small frequency steps for first oscillator 130 and larger frequency steps for second oscillator 132 achieves a wide output frequency range at high frequency resolution. Low phase noise is achieved because the frequency difference (f2−f1) is compared with a low-frequency pulse train reference signal 150 derived from a clean reference signal 152 and the phase difference is used as feedback for the second oscillator 132. [0083] The choice of a smaller frequency range and step size for first oscillator 130 compared with that of second oscillator 132 makes it more convenient to design filters 204 and 158 for a specified IF frequency fIF, but these relationships are not required in all embodiments. Embodiments having different filtering configurations for signal path 170 can be designed so that the frequency of RF DTV signal 82 is fRF=|(f1−f2)−fIF| rather than fRF=|(f2−f1)−fIF|. However, the design choices illustrated in the embodiment of FIG. 7 simplify tuning of RF converter 84′ and the design of signal path 170. It will be understood that at least one of the oscillators 130, 132 is required to have a step size that allows the frequency difference to fall within the pulling range of the low-frequency reference signal 150. [0084] Amplifiers and attenuators such as 172, 174 and others not specifically numbered are provided in RF converter 84 (and RF converter 84′) to optimize signal levels in the circuit in one embodiment. Such circuit optimizations are considered to be within the capability of one of ordinary skill in the art upon achieving an understanding of the present invention. [0085] Low pass filters 168, 146 are controlled by a filter control 222 that receives a control signal F. The filter control 222 can select a bandwidth of 500 MHz or 1 GHz for the low pass filters 168, 146. When the RF signal 82 is a lower frequency signal, i.e., less than 500 MHz, the filter control 222 will select a 500 MHz bandwidth for the low pass filters 168, 146. [0086] In another embodiment of RF converter 84 (and RF converter 84′), phase difference error signal 156 is fed back to first oscillator 130 rather than second oscillator 132. Because the total frequency conversion is based on the frequency difference (f2−f1), this embodiment also achieves reduction of phase noise from RF output signal 82. [0087] In one specific transmitter embodiment, RF converter 84 (and RF converter 84′) accepts an IF input signal 126 characterized by an IF frequency between 36 and 54 MHz. For example, let us assume IF input signal 126 is characterized by a 46 MHz IF frequency, first oscillator 130 is set by frequency synthesis to a frequency of 1210.025 MHz and second oscillator 132 is set by frequency synthesis to a frequency of 1950 MHz. The first mixing product 180 (which is selected by filtering) is the mixing product at 1256.025 MHz. The second mixing product 182 selected by low pass filter 168 is 693.975 MHz, which is the frequency of RF output signal 82. In this example, fRF=|(f2−f1)−fIF|, where fIF=46 MHz, f1=1210.025 MHz, and f2=1950 MHz. [0088] Other features of the embodiment illustrated in FIG. 7 include two D/A converters 184 generating control signals A and B for controlling IF gain and loop gain, four A/D converters 185 receiving control signals K, L, M and N to supervise voltages in the oscillator loops and the 10V supply, a PC bus expander 186, which is an I2C bus device with 8 logic outputs, and EEPROM 188, which is a memory for calibration data, for example, gain and frequency dependency. Modules 78, 122, 131, 133, 162, 164, 184, 185, 186, 188, 190, 196 and 222 are controllable via remote control. [0089] In one receiver embodiment, the input signal to signal path 170 is an RF signal rather than an IF signal, the output signal is an IF signal, and RF signal is first mixed with a wide-range, coarse tuning oscillator followed by a narrow-range, fine-tuning oscillator. (In other words, the positions of oscillators 130 and 132, as well as their synthesizer inputs 162, 164, and other associated components and correction inputs are exchanged.) An RF input signal at 693.975 MHz, for example, is first mixed with a 1950 MHz signal to obtain a mixing product at 1256.025 MHz, which is band-pass filtered. This product is then down-converted with a 1210.025 MHz local oscillator signal to product a 46 MHz IF signal. In this example, fRF=693.975 MHz, f1=1210.025 MHz, and f2=1950 MHz., and fIF=|(f2−f1)−FRF|. [0090] In another embodiment, RF converter 84 (and RF converter 84′) is configured as a downconverter stage for a DTV receiver. In this case, signal 126 is or is derived from a received RF signal. IF amplifier 78 is eliminated or optionally replaced by a suitable RF amplifier. Filters in signal path 170 select mixing products from mixers 176 and 178 so that output 82 of signal path 170 is a baseband or an IF signal, where either fIF=|(f1−f2)−fRF| or fIF=|(f2−f1)−fRF|, depending upon a design choice implemented by the filtering. [0091] It will be apparent that the low phase noise, high resolution features of RF converter 84 (and RF converter 84′) do not depend upon its use in a digital television receiver or transmitter circuit. Therefore, in other embodiments, RF converter 84 (and RF converter 84′) is used in other devices in which low phase noise and high frequency resolution provide useful advantages. [0092] The components of the invention can be implemented using analog circuitry, digital logic circuitry, microprocessors, ASICs, software running on computer systems, or other comparable devices, or various combinations or subcombinations of these devices, as will be understood by those of ordinary skill in the art. [0093] While the invention has been described in terms of various specific embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the claims Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6920172 *Jan 2, 2001Jul 19, 20053Com CorporationDual purpose spread spectrum radio receivers with controlled frequency rejectionUS6934597 *Mar 26, 2002Aug 23, 2005Lsi Logic CorporationIntegrated circuit having integrated programmable gate array and method of operating the sameUS7171182 *May 1, 2002Jan 30, 2007Qualcomm IncorporatedFrequency synthesizers for supporting voice communication and wireless networking standardsUS7462956Jan 11, 2007Dec 9, 2008Northrop Grumman Space & Mission Systems Corp.High efficiency NLTL comb generator using time domain waveform synthesis techniqueUS7903538 *Aug 6, 2003Mar 8, 2011Intel CorporationTechnique to select transmission parametersUS7924886 *Jun 16, 2008Apr 12, 2011Screen Service Broadcasting Technologies S.P.A.Deterministic program clock reference re-stamping for synchronous bit rate adaptation based on mega-frame initialization packetUS7983303Jun 16, 2008Jul 19, 2011Screen Service Broadcasting Technologies S.P.A.Mega-frame initialization packet generation and synchronous re-generation with bit rate adaptation for single frequency networks with multiple modulation schemesUS8300113 *Oct 10, 2008Oct 30, 2012Los Alamos National Security, LlcHadamard multimode optical imaging transceiverUS8432882 *Nov 24, 2008Apr 30, 2013Cisco Technology, Inc.Multiple transport receiverUS8456245 *Oct 12, 2011Jun 4, 2013Texas Instruments IncorporatedTwo LO and two mixers generating high frequency LO signalUS8493853 *Dec 15, 2008Jul 23, 2013Arris Solutions, Inc.Flow control in a network deviceUS8779814Jul 22, 2013Jul 15, 2014Associated Universities, Inc.Synthesizer method utilizing variable frequency comb lines and frequency togglingUS20090168813 *Nov 24, 2008Jul 2, 2009Cisco Technology, Inc.Multiple Transport ReceiverUS20100091134 *Oct 10, 2008Apr 15, 2010The Regents Of The University Of CaliforniaHadamard multimode optical imaging transceiverUS20100111145 *Oct 23, 2009May 6, 2010Broadcom CorporationBaseband unit having bit repetitive encoded/decodingUS20120008949 *Mar 15, 2010Jan 12, 2012Nec CorporationCircuit, control system, control method, and computer-readable recording medium for recording programUS20130070821 *May 20, 2011Mar 21, 2013Stephen William LaiSystem and method for providing a wireless/power-line diversity communications channel* Cited by examinerClassifications U.S. Classification375/316, 348/E05.108, 348/E05.113, 375/E07.002International ClassificationH04L27/26, H03L7/22, H04N7/24, H04N5/455, H04N5/44, H03D7/16, H03L7/23Cooperative ClassificationH03D7/163, H04N21/2383, H04N5/455, H03L7/22, H04N5/4401, H04L27/2626, H04N21/4382, H03L7/23European ClassificationH04N21/438M, H04N21/2383, H04N5/455, H03D7/16B1, H03L7/22, H03L7/23Legal EventsDateCodeEventDescriptionJan 14, 2014FPExpired due to failure to pay maintenance feeEffective date: 20131122Nov 22, 2013LAPSLapse for failure to pay maintenance feesJul 8, 2013ASAssignmentEffective date: 20130626Free format text: SECURITY AGREEMENT;ASSIGNOR:UNIQUE BROADBAND SYSTEMS, LTD.;REEL/FRAME:030763/0752Owner name: BANK OF MONTREAL, CANADAFree format text: SECURITY AGREEMENT;ASSIGNOR:UBS-AXCERA, INC. (AS GUARANTOR);REEL/FRAME:030763/0736Jul 5, 2013REMIMaintenance fee reminder mailedMay 19, 2009FPAYFee paymentYear of fee payment: 4Oct 18, 2006ASAssignmentOwner name: UNIQUE BROADBAND SYSTEMS LTD., CANADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNIQUE BROADBAND SYSTEMS, INC.;REEL/FRAME:018398/0875Effective date: 20060918Jul 5, 2001ASAssignmentOwner name: UNIQUE BROADBAND SYSTEMS, INC., CANADAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NIELSEN, GERT LYNGE;REEL/FRAME:011973/0440Effective date: 20010628RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google

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Harutinator comments on Relationship advice, from a teenage girl.jump to contentmy subredditsannouncementsArtAskRedditaskscienceawwblogbookscreepydataisbeautifulDIYDocumentariesEarthPornexplainlikeimfiveFitnessfoodfunnyFuturologygadgetsgamingGetMotivatedgifshistoryIAmAInternetIsBeautifulJokesLifeProTipslistentothismildlyinterestingmoviesMusicnewsnosleepnottheonionOldSchoolCoolpersonalfinancephilosophyphotoshopbattlespicsscienceShowerthoughtsspacesportstelevisiontifutodayilearnedTwoXChromosomesUpliftingNewsvideosworldnewsWritingPromptsedit subscriptionsfront-all-random | InternetIsBeautiful-food-philosophy-photoshopbattles-Documentaries-news-WritingPrompts-Music-gadgets-movies-sports-Fitness-Showerthoughts-Jokes-personalfinance-pics-askscience-listentothis-dataisbeautiful-gaming-gifs-OldSchoolCool-television-DIY-AskReddit-explainlikeimfive-Art-tifu-history-videos-space-LifeProTips-nosleep-creepy-TwoXChromosomes-worldnews-nottheonion-science-GetMotivated-UpliftingNews-funny-aww-IAmA-mildlyinteresting-books-todayilearned-EarthPorn-Futurologymore » cringecommentsrelatedwant to join? login or register in seconds|Englishlimit my search to /r/cringeuse the following search parameters to narrow your results:subreddit:subredditfind submissions in "subreddit"author:usernamefind submissions by "username"site:example.comfind submissions from "example.com"url:textsearch for "text" in urlselftext:textsearch for "text" in self post contentsself:yes (or self:no)include (or exclude) self postsnsfw:yes (or nsfw:no)include (or exclude) results marked as NSFWe.g. subreddit:aww site:imgur.com dogsee the search faq for details.advanced search: by author, subreddit...this post was submitted on 19 Apr 2013212 points (88% upvoted)shortlink: remember mereset passwordloginSubmit cringe (no minors)Submit personal story/memorycringesubscribeunsubscribe283,104 readers668 users here now/r/cringe is the place for videos or personal stories involving an awkward or embarrassing situation for two or more people involved. View a list of all "Seal of Approval" posts!
created by [deleted]a community for 5 yearsmessage the moderatorsMODERATORSdrumcowskikeyboardcowsnowboardManWithoutModemstopscopiesmeIAmAN00bieAutoModeratorAddyctSlijhourdsmikimsFakeAudio...and 12 more »211212213Relationship advice, from a teenage girl. (youtube.com)submitted 1 year ago by Kentagious152 commentssharecancelsorry, this has been archived and can no longer be voted onloading...sorted by: bestbesttopnewhotcontroversialoldrandomyou are viewing a single comment's thread.view the rest of the comments →[–]Harutinator -1 points0 points1 point 1 year ago (0 children)sorry, this has been archived and can no longer be voted onBro don't you dare make fun of my mom's handjobs
username:try anotheravailable!account recovery email: (optional)we only send email at your requestpassword:verify password:remember mecreate accountis it really that easy? only one way to find out...loginalready have an account and just want to login?username:password:remember merecover passwordloginclose this windowinterface languageEnglish [en]العربية [ar]Беларуская мова [be]български език [bg]Bosanski [bs]català [ca]česky [cs]dansk [da]Deutsch [de]Ελληνικά [el]English (Australia) [en-au]English (Canadian) [en-ca]English (Great Britain) [en-gb]English [en-us]Esperanto [eo]español [es]español [es-ar]eesti keel [et]Euskara [eu]فارسی [fa]suomi [fi]français [fr]Gàidhlig [gd]עברית [he]मानक हिन्दी [hi]hrvatski [hr]Magyar [hu]Հայերեն լեզու [hy]Bahasa Indonesia [id]íslenska [is] (*)italiano (Italy) [it]日本語 [ja]ಕನ್ನಡ [kn_IN]한국어 [ko]Latin [la]1337 [leet]LOL [lol]lietuvių kalba [lt]latviešu valoda [lv]Nederlands [nl]Nynorsk [nn]Norsk [no]Arrrrrrrr! [pir]polski [pl]português [pt] (*)português [pt-pt]português brasileiro [pt_BR]română [ro]русский [ru]slovenčina [sk]slovenščina [sl]српски језик [sr]Srpski [sr-la]Svenska [sv]தமிழ் [ta]ภาษาไทย [th]Türkçe [tr]українська мова [uk]Tiếng Việt [vi]中文 [zh] (*) incomplete volunteer to translateπ Rendered by PID 875 on app-29 at 2014-10-24 16:25:01.234964+00:00 running 97727a2 country code: US.

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Audiobooks narrated by Harald Schwaiger | Audible.com
Showing results by narrator "Harald Schwaiger"
By: Markus Topf, Markus Duschek
Narrated by: Louis F. Thiele, Dagmar Bittner, Detlef Tams, and others
Narrated by: Louis F. Thiele, Dagmar Bittner, Detlef Tams, Harald Schwaiger, Sinikka Compart, Katja Brügger

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Amazon.com: Cactus Factory (9780974017341): Debbi Miller Gutierrez: Books
Cactus Factory has been added to your Cart
Cactus Factory Paperback – October 27, 2011
by Debbi Miller Gutierrez (Author)
No matter what Tansy Tuttletin faces, she never gives up. When Mrs. Tuttletin’s employer, the town’s yarn factory, faces closure, Tansy searches for odd jobs. When cabbage soup is all there is to eat, she wheels her wagon full of little red plant pots door to door. When a notorious burglar threatens to steal the silver sugar bowl Mr. Tuttletin left Tansy and her mother, she meets the danger head-on. Will her good spirits and can-do attitude pay off? Perhaps, with a little help from the “cactus factory”. Cactus Factory is sometimes funny, sometimes surprising, and all the time good reading fun for children 12 and under. With something for everyone, parents, grandparents, and teachers will enjoy reading this chapter book out loud to little ones, or reading along with early and middle grade readers.
Publisher: Prints By Mail (October 27, 2011)
This item: Cactus Factory


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