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Patent US4605124 - Disposable cover for surgical light handle - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA sterile cover for the handle on a surgical light is comprised of an integrally formed disposable plastic sheath generally in the shape of a unibody hollow cylinder with either a hollow inverse conical-shaped member or a dish shaped member at an open end of the cylinder. An alternative embodiment of...http://www.google.com/patents/US4605124?utm_source=gb-gplus-sharePatent US4605124 - Disposable cover for surgical light handleAdvanced Patent SearchPublication numberUS4605124 APublication typeGrantApplication numberUS 06/521,626Publication dateAug 12, 1986Filing dateAug 9, 1983Priority dateAug 9, 1983Fee statusPaidPublication number06521626, 521626, US 4605124 A, US 4605124A, US-A-4605124, US4605124 A, US4605124AInventorsDan Sandel, Michael HoftmanOriginal AssigneeDevon Industries, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (12), Referenced by (78), Classifications (20), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetDisposable cover for surgical light handleUS 4605124 AAbstract A sterile cover for the handle on a surgical light is comprised of an integrally formed disposable plastic sheath generally in the shape of a unibody hollow cylinder with either a hollow inverse conical-shaped member or a dish shaped member at an open end of the cylinder. An alternative embodiment of the invention relates to an adapter kit having an adapter bushing, an adapter handle for threaded or snap-on attachment to the stud on any of a variety of lighting fixtures and sterile covers to allow the covers to be used on light fixtures having different sizes of handle mounting studs.
What is claimed is: 1. A disposable cover for the handle of a surgical room light fixture which is normally positioned above the operating table and handled by the surgeon during operations, said handle having a generally cylindrical grip depending form a bell-shaped portion adjacent the light fixture, said cover comprising:a sterile, disposable thin walled impervious plastics or rubber like material body including a generally cylindrical and hollow grip portion and a flange, integral with said grip portion at an open end thereof, the opposite end of said grip being closed by an integral end wall, and wherein said flange is of a generally bell like configuration for mating engagement with said handle bell-shaped portion wherein said cover body may be fitted over said light fixture handle grip portion with said flange abutting and covering said bell-shaped portion of said handle adjacent said fixture, wherein an adhesive material is preapplied to the interior portions of said flange whereby said flange may be pressed into an adhering fit against adjacent portions of said handle and/or fixture. 2. A disposable cover for the handle of a surgical room light fixture which is normally positioned above the operating table and handled by the surgeon during operations, said handle having a generally cylindrical grip depending from a bell-shaped portion adjacent the light fixture, said cover comprising:a sterile, disposable thin walled impervious plastics or rubber like material body including a generally cylindrical and hollow grip portion and a flange integral with said grip portion at an open end thereof, the opposite end of said grip being closed by an integral end wall, and wherein said flange is of a generally bell-like configuration for mating engagement with said handle bell-shaped portion wherein said cover body may be fitted over said light fixture handle grip portion with said flange abutting and covering said bell-shaped portion of said handle adjacent said fixture, and reinforcing means including integral ribs are provided integrally of said grip portion and flange for giving said flange and grip portion a reinforced predetermined configuration for facilitating the fit thereof to said handle. 3. A disposable cover for the handle of a surgical room light fixture which is normally positioned above the operating table and handled by the surgeon during operations, said handle including a handle grip depending from a handle flange adjacent said fixture, said cover comprising:a sterile, disposable thin walled imperivous plastics or rubber like material body including a generally hollow grip portion and a flange integral with said grip portion at an open end thereof, whereby said cover body may be fitted over said light fixture handle, and wherein reinforcing means including a plurality of spaced ribs are provided integrally of said grip portion and flange for giving said flange and grip portion a reinforced and predetermined configuration for facilitating the fit thereof to said handle. 4. The disposable cover of claim 3 wherein said cylindrical grip is provided with a low coefficient of friction surface on its inside and a high coefficient of friction surface on its outside.
BACKGROUND OF THE INVENTION: The present invention relates in general to hospital surgery room equipment and specifically to a disposable cover for the handle of a surgical room light fixture which is normally positioned above the operating table and handled by the surgeon and or nurse during operations.
OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel sterile cover for the handle on a surgical light fixture. It is a further object to provide such a surgical light fixture handle cover that is both inexpensive and easy to manufacture and which may be disposable. A further object of the present invention is to provide an adapter kit so that the handle cover of the present invention may be used with various type or size of light fixture handle.
SUMMARY OF THE INVENTION Generally stated, the present invention comprises the provision of a disposable cover for the handle of the surgical room light fixture, which is normally positioned above the operating table and handled by the surgeon and or nurse during operations, the cover comprising a sterile, disposable thin walled impervious plastic or rubber like material body including a generally cylindrical or conical grip portion and a flange integral with said grip portion at an open end thereof, the opposite end of said grip being closed by an integral end wall whereby said cover body may be fit over said light fixture handle with said flange abutting portions of said fixture adjacent said handle.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a surgical lighting fixture and handle thereof equipped with an exemplary embodiment of the disposable cover of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1, a surgical lighting fixture 10 comprised of a body 14 and having a manual handle and cover assembly is shown at 16 which is meant to be used by a surgical attendant designated by the FIG. Z. The lighting structure is suspended over the head of the surgical attendant performing the surgical procedure. As can readily be seen in FIG. 1, the surgical attendant may make necessary adjustments to the lighting fixture orientation, including the angle of light incidence by use of the cover and handle assembly 16.
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LP;ASSIGNOR:KENDALL COMPANY LP, THE;REEL/FRAME:014491/0698Effective date: 19990326Owner name: THE KENDALL COMPANY LP 15 HAMPSHIRE STREETMANSFIELFree format text: CONTRIBUTION AGREEMENT;ASSIGNOR:GRAPHIC CONTROLS CORPORATION /AR;REEL/FRAME:014491/0660Owner name: TYCO HEALTHCARE GROUP LP 15 HAMSPHIRE STREETMANSFIFree format text: CERTIFICATE OF AMENDMENT TO THE CERTIFICATE OF LIMITED PARTNERSHIP OF THE KENDALL CO. LP;ASSIGNOR:KENDALL COMPANY LP, THE /AR;REEL/FRAME:014491/0698Jan 8, 1998FPAYFee paymentYear of fee payment: 12Apr 4, 1996ASAssignmentOwner name: CHEMICAL BANK (AS COLLATERAL AGENT), NEW YORKFree format text: SECURITY INTEREST;ASSIGNOR:DEVON INDUSTRIES, INC.;REEL/FRAME:007881/0730Effective date: 19960229Dec 6, 1993FPAYFee paymentYear of fee payment: 8Sep 25, 1989FPAYFee paymentYear of fee payment: 4Aug 9, 1983ASAssignmentOwner name: DEVON INDUSTRIES, INC., 21040 OSBORNE ST., CANOGAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:SANDEL, DAN;HOFTMAN, MICHAEL;REEL/FRAME:004162/0855Effective date: 19830801RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


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Patent US7119812 - Full-scene anti-aliasing method and system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a resulting image. A scene is rasterized at a first angle relative to a first coordinate system to generate a plurality of pixels, which are then...http://www.google.com/patents/US7119812?utm_source=gb-gplus-sharePatent US7119812 - Full-scene anti-aliasing method and systemAdvanced Patent SearchPublication numberUS7119812 B2Publication typeGrantApplication numberUS 10/837,234Publication dateOct 10, 2006Filing dateApr 30, 2004Priority dateAug 28, 2002Fee statusPaidAlso published asUS6922199, US7205996, US7369138, US8564609, US20040041817, US20040207634, US20040217973, US20060244760, US20080186329, US20130033514Publication number10837234, 837234, US 7119812 B2, US 7119812B2, US-B2-7119812, US7119812 B2, US7119812B2InventorsGregory M. HunterOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (26), Referenced by (5), Classifications (7), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetFull-scene anti-aliasing method and systemUS 7119812 B2Abstract A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a resulting image. A scene is rasterized at a first angle relative to a first coordinate system to generate a plurality of pixels, which are then applied to a polygon surface that is rendered at a second angle equal to the inverse of the first angle. Thus, the resulting image is re-oriented with respect to the first coordinate system.
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LlcFull-scene anti-aliasing method and systemUS8779469Nov 15, 2013Jul 15, 2014International Business Machines CorporationPost-gate shallow trench isolation structure formationUS8785291Oct 20, 2011Jul 22, 2014International Business Machines CorporationPost-gate shallow trench isolation structure formationClassifications U.S. Classification345/582, 345/611, 345/427International ClassificationG06T15/20, G09G5/00Cooperative ClassificationG06T15/04European ClassificationG06T15/04Legal EventsDateCodeEventDescriptionMar 12, 2014FPAYFee paymentYear of fee payment: 8Apr 8, 2010FPAYFee paymentYear of fee payment: 4Jan 4, 2010ASAssignmentOwner name: ROUND ROCK RESEARCH, LLC,NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;US-ASSIGNMENT DATABASE UPDATED:20100204;REEL/FRAME:23786/416Effective date: 20091223Owner name: ROUND ROCK RESEARCH, LLC,NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;US-ASSIGNMENT DATABASE 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https://nyti.ms/1OKCgu1
By CHRISTINE HAUSER JAN. 11, 2016
Elephants with the Ringling Bros. & Barnum and Bailey circus exercised near Madison Square Garden in 2003. Credit Richard Perry/The New York Times
A version of this article appears in print on January 12, 2016, on Page C3 of the New York edition with the headline: Ringling Speeds Up Elephants’ Retirement. Order Reprints| Today's Paper|Subscribe
Running Away With the Circus NOV. 19, 2015
Elephants to Retire From Ringling Brothers Stage MARCH 5, 2015

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A Potomac Swim May End in Court - The Washington Post
A Potomac Swim May End in Court
By Michael Specter By Michael Specter May 14, 1985
U.S. Attorney Elsie L. Munsell yesterday asked for a federal court order that would force anyone arrested entering the Potomac River from park land to appear in court.
Although the maximum penalty for the offense is a $500 fine and six months in jail, it is now treated much like a parking violation and people who choose not to contest the charge can pay a $25 fine by mail.
The order Munsell is seeking from the eight active U.S. District Court judges in the Eastern District of Virginia is designed to discourage swimmers from plunging into the particularly treacherous stretch of the Potomac from just above Great Falls to Chain Bridge.
"This is an offense that risks serious injury or death," Munsell said after filing the motion. "We are hoping this will help people see how dangerous it is."
J. Frederick Motz, the U.S. attorney for Maryland, said that later this week he will file a request similar to Munsell's for an order that would affect people who enter the river from the Maryland side.
Last year, at least 14 people drowned in the 11-mile stretch of river between Seneca and Chain Bridge. There have been five reported deaths so far this year. An average of seven people die annually in the waters that even experienced canoeists frequently describe as violent.
The river near Great Falls claimed its latest victim two weeks ago when Hai Van Huynh, a 19-year-old junior at Arlington's Wakefield High School.
The proposed tightening of the law was hailed by National Park Service officials, who for years have struggled to prevent the summertime Potomac drownings.
"We have tried everything," said Sandra Alley, a spokesman for the Park Service, "signs, patrols, education. But some people just don't care. Maybe this will help."
Despite ominous warning signs scattered throughout Great Falls Park, many people among the thousands who visit the park each weekend go there to leap the rocks and risk a dip in the water.
A spokesman for the Park Service said yesterday he did not know how many tickets have been issued during the past two years, but that the number, along with the frequency of rescues, has increased steadily.
In April, Reps. Frank R. Wolf (R-Va.) and Michael Barnes (D-Md.) urged Interior Secretary Donald P. Hodel to impose automatic $200 fines on those who enter the river illegally from national parkland.
Wolf said yesterday he thinks the move by Munsell "is a significant step in the right direction. The river looks calm but it is very dangerous and this is not to be treated like some minor violation. I strongly support it."
A $3.5 million plan to modify the Potomac's Little Falls Dam two miles upstream from Chain Bridge, known as "the drowning machine" because of the frequency of deaths in its swirling waters, has been approved by the Army Corps of Engineers and the District.
The dam's hydraulic characteristics will be altered by adding grout-filled bags.
Munsell said that U.S. District Judge Albert V. Bryan Jr. in Alexandria had agreed to circulate her request to the seven other judges.

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P. 1Internship Report of NBPInternship Report of NBPRatings: (0)|Views: 266|Likes: 7Published by ✬ SHANZA MALIK ✬More info:Published by: ✬ SHANZA MALIK ✬ on Jan 22, 2011Copyright:Attribution Non-commercialAvailability:Read on Scribd mobile: iPhone, iPad and Android.download as DOC, PDF, TXT or read online from ScribdFlag for inappropriate content|Add to collectionSee moreSee lesshttps://www.scribd.com/doc/47356660/Internship-Report-of-NBP11/15/2013pdftextoriginal INTERNSHIP CONCLUSIVE REPORT 2009Master of Business Administration ProgramInternee name: Mohammad NomanRegistration No: FA07-MBA-041Specialization: FinanceCOMSATS INSTITUTE OF INFORMATION TECHNOLOGY Company Name: NATIONAL BANK OFPAKISTANPostal address: NBP NIH BRANCH P/O NIH IBDSupervisor Name: Muhammad NAZIRTelephone Number: 03335646875Start Date for Internship: JULY 15, 2009
Muhammad NomanFA07-MBA-041
FA07-MBA-0411
NATIONAL BANK OF PAKISTANMasters in Business Administration
It is certified that the internship report and theworking contained in it conforms to all the standardsset by the institute for the evaluation of any suchwork
1. _______________________________________________________________________ _ 2._______________________________________________________________________ 3. _______________________________________________________________________ _ 4. _______________________________________________________________________ _ PREFACE FA07-MBA-0412
In order to be able to cope with the changing environment it is necessary to have some practical experience. As the students of Business Administration we have to pass througha series of various managerial techniques. During this practical course we are providedwith an opportunity to learn that how the theoretical knowledge can be implemented in practical grounds.I was selected to do my internship in National Bank of Pakistan NIH BranchIslamabad. I worked there for six weeks & it gave me a greater practical knowledge aboutthe operations of a bank.
I am highly grateful to almighty Allah who gave me the power to complete this report.I am also highly thankful to my honorable teachers for theirs guidance.FA07-MBA-0413
Activity (9)FiltersAdd to collectionReviewAdd NoteLikeShowingAllMost RecentReviewsAll NotesLikesYou've already reviewed this. Edit your review.Rating 0/5Post notePost reviewPost replyPost note and like1 thousand reads1 hundred readsshaan_ah liked thisYasir Babar liked thisFaan Shah liked thisehsanul1 liked thisirfankotlian liked thismuhammadirfanahmed liked thisAli Nawaz Chandio liked thisLoad more
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Submitted To: Instructor MISI 619 Submitted By: Muhammad Abuzar MC06040004...Previous|NextPage 1 of 8

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Patent US20040230752 - Bus protocol for a "switchless" distributed shared memory computer system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a...http://www.google.com/patents/US20040230752?utm_source=gb-gplus-sharePatent US20040230752 - Bus protocol for a "switchless" distributed shared memory computer systemAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20040230752 A1Publication typeApplicationApplication numberUS 10/435,878Publication dateNov 18, 2004Filing dateMay 12, 2003Priority dateMay 12, 2003Also published asUS6988173Publication number10435878, 435878, US 2004/0230752 A1, US 2004/230752 A1, US 20040230752 A1, US 20040230752A1, US 2004230752 A1, US 2004230752A1, US-A1-20040230752, US-A1-2004230752, US2004/0230752A1, US2004/230752A1, US20040230752 A1, US20040230752A1, US2004230752 A1, US2004230752A1InventorsMichael Blake, Steven German, Pak-Kin Mak, Adrian Seigler, Gary Van HubenOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (13), Referenced by (54), Classifications (7), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetBus protocol for a "switchless" distributed shared memory computer system
DETAILED DESCRIPTION [0042] Referring now to the Figures and in accordance with an exemplary embodiment of the present invention, a large shared-memory symmetrical multiprocessing computer system built from multiple building blocks, henceforth referred to as “nodes”, each of which contains some amount of memory and some number of processing units is illustrated. In accordance with an exemplary embodiment, the system structure comprises four nodes interconnected via a dual concentric ring topology for illustrative purposes. Of course, it is contemplated that systems comprising more or less than four nodes may be used with the embodiments disclosed herein. [0043] [0043]FIG. 1a depicts an example of four nodes (104) in a multi-nodal symmetric multiprocessing system. Each node (104) comprises a System Controller Element (103) which provides interconnections and communications with a plurality of central processors (100), I/O adapters (101), and main memory (102) of the node it is resident upon and the other nodes via other system controllers elements on the other nodes and a pair of rings for providing communication links between the nodes. [0044] The System Controller Element (103) contains top-level cache which serves as the central coherency point within that particular node. Both the top-level cache and the main memory are accessible by a central processor or I/O adapter within that node (104) or any of the remaining three nodes in the system. Data fetch and store requests are initiated by the central processors or I/O adapters, and are processed by the local controllers contained within the SCE (103). [0045] Fetch requests from a central processor which miss the top-level cache within a node will interrogate the top-level caches on the other nodes. If the fetch operation misses the top-level caches on all nodes, then the target node where the main memory address resides serves as the source for the data. For LRU Writeback operations resulting from aged out cache data, the data is transferred directly to the target node without the need for interrogation. [0046] The command/address portion of all ring operations destined for other nodes are launched onto both rings simultaneously. For matters of system level coherency, both operations must pass through each node and the results of the requested operations are merged to provide a final response to the requesting node. [0047] As the operation passes through each remote node, remote fetch controllers interrogate the top-level cache on that remote node and perform any necessary system coherency actions. In the event the desired data is located in one of the remote caches, the data fetch operation is handled by remote fetch controllers resident upon the node having the desired data. Finally, if the operation misses all the caches (local and remote) and targets memory on a remote node, the data fetch operation is handled by the remote fetch controller on the node in which the target memory resides. [0048] The system's main memory is distributed across the nodes. On each node there exists a set of hardware mapping registers which takes the address portion of the operation and determines if the main memory location exists on that node. [0049] For LRU Writeback operations passing thru each remote node, there exists a set of remote store controllers. On intermediate nodes (nodes which are neither the source or destination of data) the remote store controllers serve to propagate the operation to the next node. On the target memory node, the remote store controller no longer forwards the operation, but puts the data away in main memory and returns a completion response. [0050] [0050]FIG. 1B depicts a detailed view of the Ring topology. The exemplary embodiment comprised of a topology comprising two rings concentric or otherwise which broadcast bus operations in opposite directions. Ring 0 (106) interconnects all the nodes (104) in the system and transfers bus operations and data in the clockwise direction. Ring 1 (107) provides the same degree of interconnect but conveys bus operations and data in the counterclockwise direction. [0051] In accordance with an exemplary embodiment, the system contemplates a ring topology whereby each ring is comprised of a physical bus for data and another physical bus for command/address including response. In an exemplary embodiment, a bus operation is initiated from a node (104), and is simultaneously dispatched on both rings each being in opposite directions. As the command/address for a bus operation circulates around the rings, remote controllers of the non-initiating nodes begin processing. If the operation carries a store command, then the data bus conveys the data to the destination node. [0052] The Ring protocol in accordance with an exemplary embodiment permits a multi-cycle data transfer to be initiated for a first operation while allowing a second non-data operation to initiate on the command/address bus of the same ring during subsequent data transfer cycles. As discussed herein data transfer operations traverse the shortest path between the node sourcing the data and the destination node. [0053] A third component or operation of the Ring protocol is the response bus which conveys operational status and coherency information such as cache hit states. An exemplary embodiment of the present invention maintains overall system coherency by ensuring all responses circulate through every node. Additionally, and as they are circulated through each node the responses undergo a prioritization and merging process, described in more detail herein, which further assists in maintaining coherency. [0054] [0054]FIG. 2 lists each of the possible cache ownership states (200) for a particular address on a node. In accordance with an exemplary embodiment, these cache ownership states are used in conjunction with more traditional cache ownership states to achieve overall coherency. When the IM (Intervention Master) bit is active for a particular address on a node, it indicates that this node was the most recent to cache in new data and receive cache ownership for that address. By definition there can no more than one node with IM=1 for a given address. Furthermore, if the cache ownership state for a given address indicates that the data is changed, it follows that the IM bit for that address must be active. [0055] When the MC (Multi-Copy) bit is active for a particular address on a node, it indicates that one or more read-only copies of the data for this address may exist in remote caches. If the cache ownership state for a particular address on a node is Invalid, this means that the data for this address does not exist in the cache on that node. Note that for an address to be valid, either IM=1 or MC=1. Also, if an address is valid, it must be either read-only, exclusive to a central processor, or unowned. All lines held exclusive must be IM=1. Also note that valid lines with IM=0 are always unchanged. [0056] [0056]FIG. 3a lists each of the possible responses (300) that can be propagated on a response bus of a given ring. [0057] No Status—This response is launched on both rings whenever a new remote fetch or store command is launched. [0058] Miss—This local response is generated if the cache ownership state at that node is found to be Invalid. [0059] IM Hit—This local response is generated at a node if the IM bit is on. [0060] Intermediate IM Cast Out—This intermediate response is generated to signal the return of data when the IM bit is on. As shown in FIG. 3d, ring priority logic ensures that the Intermediate IM Cast Out message is always forwarded (307) prior to forwarding of the second message IM Hit response (310). For performance reasons, the Intermediate IM Cast Out response is forwarded as quickly as possible, so as indicated by flow diagram elements 306, 307 and 308, it may also precede the forwarding of the first message IM Hit response. The direction of this response and castout data is such that it is always opposite to the direction of the incoming first message response. This facilitates data transfer with the minimum number of node hops. [0061] Read Only Hit—This local response is generated at a node if the cache ownership state is found Read Only and the IM bit is off. [0062] Memory Data—This local response is generated as a second message response accompanied by data at the target memory node if the local and incoming responses are some combination of Miss, Read Only Hit, or No Status. [0063] IM Reject—This local response is generated whenever an active IM Pending condition is detected during processing of a new incoming response. [0064] MM Reject—This local response is generated whenever an active MM Pending condition is detected during processing of a new incoming response. [0065] Normal Completion—This local response is generated whenever processing for an LRU Write-back of aged out cache data is completed at the target memory node. [0066] [0066]FIG. 3b shows the ordering (301) of ring responses. This ordering is applied whenever incoming ring responses must be merged with local responses, or whenever accumulation of responses must be applied (as depicted in FIG. 3c). For Read Only, Fetch Exclusive, and LRU Write-back operations, a local IM Hit condition always results in cache data being sourced from the node. Similarly, for Read Only Invalidate operations, a local IM Hit always results in the cache ownership state being updated to Invalid at the node. This treatment of the local IM Hit condition necessitates that the IM Hit response be the highest ordered ring response. That is, once a local IM Hit condition has been observed at a node, this condition must subsequently be observed at all other nodes in order to ensure that the proper cache management actions are performed at all nodes. [0067] Next in order behind the IM Hit response are IM and MM Reject responses. In other words, a locally generated reject response will always be reflected back to the requesting node unless an IM Hit condition exists at some other node. Next in order behind the reject responses is the Memory Data response. Since memory data can only be sourced from the target memory node when the incoming and local responses are some combination of Miss, Read Only Hit, and No Status responses, then it stands to reason that the Memory Data response must be the highest ordered response amongst those 4 types of responses. The No Status response only occurs when a ring command is initially launched onto both rings at the requesting node. Therefore, it is the lowest ordered response. The normal completion response applies only to LRU Write-back operations at the target memory node. It must be ordered ahead of the Miss response in order to facilitate notification of completion of the operation back to the requesting node. [0068] [0068]FIG. 3c shows how local ring responses are combined with incoming ring responses to formulate the outgoing ring response. Incoming responses on both rings are captured in HELD RESP latches 302 and 304, which are located on each of the nodes in the system. HELD RESP latches 302 and 304 provide a means for combining local ring responses with incoming ring responses to formulate the outgoing ring response at all remote nodes. [0069] An example of the operation of HELD RESP latches 302 and 304 is described as follows: If the incoming ring 0 response arrives first, it is captured in latch 302 and the incoming ring 1 response is captured in latch 304. If the incoming ring 1 response arrives first, it is captured in latch 302 and the incoming ring 0 response is captured in latch 304. Upon receipt of the incoming Ring X first message, a local response is generated. This local response is merged (303) with the held response from latch 302 using the response coherency ordering described in FIG. 3b. This result is then forwarded out on the first message. Wherein the result of this ordering is then merged (305) with the held response from latch 304—again using the response coherency ordering described in FIG. 3b. This result is then forwarded out on the second message. [0070] In addition to merging the responses, the final response accumulation (305) also provides a means for selecting the direction of outgoing messages. For responses other than IM Cast Out messages, the outbound ring will normally be chosen based on the direction of the incoming message. For example, if the incoming first message arrives on Ring 0, it will be forwarded on Ring 0. Additionally, the second message would arrive on Ring 1, thereby causing the outgoing final response to be sent on Ring 1. In certain topologies, both messages can arrive at a node simultaneously. In this case, the present invention contemplates the use of a toggle latch to determine the direction of the outgoing message. The toggle latch is only used when both incoming messages arrive simultaneously, such that the outbound direction is indeterminant. Upon employing the latch to direct the outgoing message to a specific ring, the toggle latch is subsequently inverted such that the next time it is utilized, the other ring will be selected. This scheme ensures fairness in bus utilization. [0071] In an example of an exemplary embodiment, the calculated average early and late data latencies on a 4-node system are 2.66 and 4 node hops respectively. This contrasts to the 3.33 and 7.33 node hops on topology A, and 4 and 6 node hops for both topologies B and C. Of course, it is contemplated that an exemplary embodiment may be used in systems with more or less than four nodes and that the aforementioned is provided to illustrate an example and is not intended to limit the exemplary embodiments discussed herein. [0072] [0072]FIG. 4a illustrates logic for controlling the setting and resetting of an IM_PEND latch (400). An IM_PEND latch (400) and its controlling logic are present within every local and remote controller on each of the nodes and in accordance with an exemplary embodiment is used to generate an IM Reject response for conflicting requests at the node where the IM_PEND latch (400) is set. [0073] An example of the operation of the IM_PEND latch (400) is described as follows. As seen from the output of logic gate (401), the IM_PEND latch is reset if any of the IM_PEND reset conditions (404) is true. If none of reset conditions (404) is true, then IM_PEND latch 400 is set if the output of OR gate 402 is true. That is, if no reset conditions (404) are true, the IM_PEND latch 400 will be set if either the IM_PEND latch was set the previous cycle or if any of the IM_PEND set conditions 403 is true. For remote fetch operations, the IM_PEND set conditions (403) are a function of the local cache ownership state and the status observed on the incoming command/address busses. In general, the IM_PEND latch is set for a remote fetch operation if: [0074] Cache or memory data will be sourced from this node [0075] Cache or memory data is in process of passing through or arriving at this node (as a result of being sourced from another node) [0076] The cache ownership states for a Read Only Invalidate operation are actively in the process of being updated. [0077] IM Hit final response is in process of passing through or arriving at this node (as a result of being sourced from another node) [0078] The reset conditions (404) for the IM_PEND latch are true if there is a local IM or MM Reject condition active as described in FIGS. 4a and 4 b, or if the remote fetch or store controller operation is no longer valid (i.e. all processing for the remote fetch or store operation has been completed as signified by the departure of all messages relating to the operation). [0079] For LRU Write-back operations, the IM_PEND set conditions (403) are active if either there is incoming LRU store data from another node or if the node is the target memory node. [0080] With any of the IM_PEND set conditions (403) active, any subsequent conflicting requests (competing data requests) from other nodes will result in an IM Reject response being generated at the node where the IM_PEND latch (400) is set. Accordingly, the IM_PEND latch provides a means for restricting storage accesses for a given address to only one operation at a time. [0081] [0081]FIG. 4b illustrates logic for controlling, setting and resetting of the MM_PEND latch (405). An MM_PEND latch (405) and its controlling logic are present within every local and remote controller on each of the nodes and in accordance with an exemplary embodiment the MM_PEND latch is used to generate an MM Reject response for conflicting requests at the node where the MM_PEND latch (405) is set. [0082] An example of the operation of the MM_PEND latch (405) is described as follows. As seen from the output of logic gate 407, the MM_PEND latch is reset if any of the MM_PEND reset conditions (404) is true. If none of reset conditions (404) is true, then MM_PEND latch 405 is set if the output of OR gate 406 is true. That is, if no reset conditions (404) are true, the MM_PEND latch 405 will be set if either the MM_PEND latch was set the previous cycle or if the node is the target memory node and the cache ownership state for the address is such that the IM bit is zero. The reset conditions (404) for the MM_PEND latch are the same as described above for the IM_PEND latch. With the MM_PEND latch (405) active, any subsequent conflicting requests from other nodes will result in an MM Reject response being generated at the node where the MM_PEND latch (405) is set. Accordingly, in the absence of an active IM_PEND latch, the MM_PEND latch provides a means for restricting storage accesses for a given address to only one operation at a time. [0083] Turning now to FIG. 5, an exemplary embodiment of the present invention contemplates three methods of address interlocking which serve to maintain coherency in situations involving competing access to the same address. The three types of interlocks described herein are: [0084] IM Pending Address Interlock [0085] MM Pending Address Interlock [0086] Message Ordering Address Interlock [0087] [0087]FIG. 5a depicts the IM_REJECT latch (500) for a single remote controller along with the supporting address interlock logic. Each remote controller in each node contains an IM_REJECT latch for use in the method of providing an IM Pending Address Interlock. The purpose of the IM Pending Address interlock is to compare the address of the incoming ring operation against the addresses of all local and remote controllers. If the address equates to a local or remote controller with an active IM Pending bit, determined and provided by an IM_PEND latch (400) on any one of the nodes, then the resulting address compare ultimately sets the IM_REJECT latch (500) of the controller receiving the incoming ring operation. [0088] The IM_REJECT latch (500) drives an IM Reject response into the Response Ordering & Merging logic, which may lead to an IM Reject response being returned to the originating requester, thereby preventing said requester from altering the cache state of the desired address. With the exception of LRU Write-back operations, all ring operations must observe any IM Reject conditions that may be detected during processing of the operation. Since LRU Write-back operations can only store changed data to memory, this means that all LRU Write-back operations can only originate from a node with IM=1. Thus the IM node serves as the single point of coherency for LRU Write-back operations, and observance of any IM Reject conditions during the processing of LRU Write-back operations by a remote store controller is not required. [0089] In an exemplary embodiment, the remote controller's IM_REJECT latch (500) is a reset-dominant hold-type latch. The outputs of the address comparators (506) are combined through OR gate (507) with the output of the IM_REJECT latch (500) to form a holding latch. The output of OR gate (507) is fed into AND gate (508) which only allows the set or hold condition to pass through if the current operation is in progress. Once the current operation completes, the IM_REJECT latch (500) will be reset as signified by the departure of all messages relating to the operation. [0090] In an exemplary embodiment, the same Address Compare logic (506) is used for both the local and remote controllers. The outputs of every other remote controllers' Address latches (501) and IM_PEND latches (502) are fed into the Address Comparator (506). If any of the IM_PEND latches is active, the corresponding address register is compared against the Ring Address Register (505) of the incoming ring operation for equality. Simultaneously, the outputs of all local controllers' Address latches (503) and IM_PEND latches (504) are similarly fed into the Address Comparator (506) and checked against the incoming ring operation's Address Register (505). Any match encountered, winds up setting this remote controller's IM_REJECT latch (500). Accordingly, the IM_REJECT Latch provides a means for maintaining coherency in situations involving competing access to the same address by comparing the addresses of the incoming ring operation against those of all local and remote controllers and if necessary causes an IM Reject response to be sent to the requester which prevents the requester from altering the cache state of the desired address until the operation which set the IM_PEND latch has completed. [0091] [0091]FIG. 5b illustrates an MM Pending Address Interlock (509) which is almost identical to the IM Pending Address Interlock. [0092] Each remote controller in each node contains an MM_REJECT latch for use in the method of providing an MM Pending Address Interlock. The purpose of the MM Pending Address interlock is to compare the address of the incoming ring operation against the addresses of all local and remote controllers. If the address equates to a local or remote controller with an active MM Pending bit, determined and provided by an MM_PEND latch (405) on the target memory node, then the resulting address compare ultimately sets the MM_REJECT latch (509) of the controller receiving the incoming ring operation. [0093] The MM_REJECT latch (509) is also reset-dominant with the latch resetting when the operation completes. Once the operation initiates, then OR gate (507) drives either the comparator results or the feedback path of the MM_REJECT latch (509) to set the latch. As with the IM_REJECT latch (500), the OR gate (507) is fed by the output of the Address Comparators (506) which employs copies of common Exclusive-OR logic used in the IM Pending Address Interlock. As shown in FIG. 5b, the same remote (501) and local (503) address registers are compared against the Ring Address Register (505) of the incoming ring operation. [0094] However, in this case the compares are gated with the remote controllers' (510) and local controllers' (511) MM_PEND latches instead of the IM_PEND latches. Thus, any other remote controller with an active MM_PEND latch and a matching address will activate the MM_REJECT latch of the controller receiving the incoming ring operation. Assuming no locally detected IM Reject exists, the MM_REJECT latch (511) drives an MM Reject response into the Response Ordering & Merging logic, which may lead to an MM Reject response being returned to the originating requester, thereby preventing said requester from altering the cache state of the desired address. With the exception of LRU Write-back operations, all ring operations must observe any MM Reject conditions that may be detected during processing of the operation. Since LRU Write-back operations can only store changed data to memory, this means that all LRU Write-back operations can only originate from a node with IM=1. Thus the IM node serves as the single point of coherency for LRU Write-back operations, and observance of any MM Reject conditions during the processing of LRU Write-back operations by a remote store controller is not required. [0095] Accordingly, the MM_REJECT Latch provides a means for maintaining coherency in situations involving competing access to the same address by comparing the addresses of the incoming ring operation against those of all local and remote controllers and if necessary causes an MM Reject response to be sent to the requester which prevents the requester from altering the cache state of the desired address until the operation which set the MM_PEND latch has completed. [0096] An exemplary embodiment also employs a further means of maintaining system level coherency by introducing a third type of interlock specifically designed to ensure that a plurality of first messages targeting the same address leave a node in the same order in which they enter the node. This first-in first-out (FIFO) order is maintained regardless of the order in which the incoming operations are actually processed. FIG. 5c depicts the Message Ordering Address Interlock logic in which all the Remote Address Registers (501) are compared to the Ring Address Register (505) of the incoming operation. The comparison is done with the Address Compare logic (506) which employs copies of the same Exclusive-OR logic used in the previous two interlock mechanisms. [0097] Also, as was the case for the previous two interlock mechanisms, LRU Write-back operations are not required to observe the Message Ordering Address Interlock due to the fact that the IM node already serves as the single point of coherency for all LRU Write-back operations. [0098] Unlike the previous interlocks, this compare does not require any remote controller to have an IM or MM Pending status. Instead, it seeks to find a simple address match in an effort to construct a FIFO queue for incoming messages with common addresses. The output of the Address Comparator (506) feeds the FIFO Queue (512). This logic uses unique identification codes for each remote controller to construct a linked-list. The top of the list indicates the ID of the controller who received the first message with the common address. The second entry in the list indicates the ID of the second controller with a matching address, and so on. [0099] The FIFO Queue (512) is used to drive the Outbound Response Logic (513) which receives requests from the remote controllers to outgate messages onto the ring topology. The Outbound Response Logic (513) uses the results of the FIFO Queue (512) to properly order the controllers' requests and ensure that the controller whose ID is at the top of the FIFO Queue outgates its message before another controller with a matching address. To facilitate performance, an exemplary embodiment permits remote controllers whose addresses do not match any other controllers to interject messages onto the ring in any order with respect to the FIFO Queue. Furthermore, an exemplary embodiment of the present invention also permits a multiplicity of addresses to be managed simultaneously thereby allowing several groups of remote controllers to process data with matching addresses. Since the FIFO Queue (512) tracks each remote controller's address individually, it is capable of constructing as many linked-lists as needed to allow any combination or grouping of controllers with matching addresses. [0100] [0100]FIG. 6 consists of a list of the commands (600) that can be launched onto either ring. The Read Only Fetch, Exclusive Fetch, and Read Only Invalidate are fetch type commands, and the LRU Write-back command is a store type command. With the exception of the Read Only Invalidate command, all commands result in data transfer between source and destination nodes. The Read Only Invalidate command is performed for the purpose of obtaining exclusivity of an address at the requesting node when the initial cache ownership state in the requesting node is MC=1. In this case, data transfer between nodes is not performed since the requesting node already has a copy of the data. [0101] [0101]FIG. 7 lists the priority (700) for arbitrating amongst the six possible ring request types. The priority list is as follows: 1) Data Flow Thru Ops; 2) Remote Data Requests; 3) Local Data Requests; 4) Local Non-Data Requests; 5) First Message Remote Requests; and 6) Second Message Remote Requests. The ring request priority scheme can be summarized as follows: [0102] Data requests are highest priority. This allows for the best utilization of the command/address bus since multiple non-data requests can be launched while the data bus is busy. This is because data requests require the use of the data bus for many more cycles than non-data requests use of the command/address bus. [0103] Local requests are higher priority than first or second message remote requests. The motivation for this is to prevent lock-outs. Local requests require use of both rings, while first and second message remote requests require use of only one ring. Also, remote requests are more likely to occur per unit time than local requests since there are 3 remote nodes for every local node. Thus, it is important to prevent situations whereby the more frequent and less restrictive first and second message remote requests could potentially lockout the less frequent and more restrictive local requests. [0104] First message remote requests are higher priority than second message remote requests. The motivation for this is so that the cache ownership results for any remote operation will be made visible to all other nodes as quickly as possible. [0105] [0105]FIGS. 8a thru 8 e collectively illustrate an example of contention between two concurrent fetch operations on the ring. It is, of course, understood that numerous operations of the exemplary embodiments are contemplated. Thus, the following is but an example of operations of exemplary embodiments and the present invention is not intended to be limited to the above example. It is assumed that both operations are targeting the same address. The initial cache ownership states in this example are as follows: [0106] N0 (800) is Invalid [0107] N1 (801) is Read Only, IM=0, MC=1 [0108] N2 (802) is Invalid [0109] N3 (803) is Read Only, IM=1, MC=1 [0110] N3 (803) is the node which holds a cached copy of the data marked as IM=1, and therefore contains the cache token acting as the system level coherency point for which competing operations to the same address arbitrate for continuation of processing. N2 (802) is the target memory node which holds the memory data for the requested address, and therefore contains the memory token. In the absence of a cache token, the memory token serves as the system level coherency point for which competing operations to the same address arbitrate for continuation of processing. The arbitration result from any cache-based system level coherency point overrides the arbitration result from any memory-based system level coherency point. [0111] [0111]FIG. 8a shows a Fetch Exclusive operation being launched from N0 (800). At the same time, a Read Only Invalidate operation is launched from N1 (801). For both operations, the ring launch for the Fetch Exclusive (804) and for the Read Only Invalidate (805) is performed simultaneously on both rings. [0112] [0112]FIG. 8b assumes that the Fetch Exclusive operation arrived first on N3 (803) via the incoming ring 1 (counterclockwise) command/address bus. This results in the following actions on behalf of the Fetch Exclusive operation: [0113] Setting of IM Pending on N3 (803) [0114] Sourcing of Intermediate IM CO response (806) and fetch data on the ring 0 command/address bus back to N0. [0115] Generation of IM Hit response (807) on ring 1 command/address bus [0116] Meanwhile, at target memory node N2 (802), the incoming Fetch Exclusive operation on the ring 0 command/address bus results in an outgoing MM Reject response on ring 0 due to the Read Only Invalidate operation arriving first on ring 1 and setting MM Pending on N2(802). An outgoing Miss response (809) is generated for the Read Only Invalidate operation at N2(802) as a result of the Invalid cache ownership state observed at this node. On node 3 (803), the incoming Read Only Invalidate operation on the ring 0 command/address bus results in an outgoing IM Reject response on ring 0 due to the Fetch Exclusive operation arriving first on ring 1 and setting IM Pending on N3 (803). [0117] [0117]FIG. 8c shows the results of response accumulation at Node 0 (800) and Node 1 (801), and also shows the setting of IM Pending on N0(800) as a result of the incoming IM CO message (806) being received on this node. At node 1, incoming responses from the Fetch Exclusive operation (ring 0 MM Reject, ring 1 IM Hit) are processed and accumulated using the response coherency ordering scheme depicted in FIG. 3b. This results in an outgoing IM Hit response (812) being launched in both ring directions back towards originating node N0 (800). The cache ownership state at node 1 (801) is also updated to Invalid since the accumulated IM Hit response at this node necessitates that the Read Only state be removed since N0 (800) will ultimately obtain exclusive ownership of this address. At N0 (800), incoming responses from the Read Only Invalidate operation (ring 0 IM Reject, ring 1 Miss) are also processed and accumulated. This results in outgoing IM Reject response (811) being launched in both ring directions back towards the originating node N1 (801). [0118] [0118]FIG. 8d shows the results of processing of second messages for both ring operations at intermediate nodes N2 (802) and N3(803). [0119] For the Fetch Exclusive command, the incoming second message from the Fetch Exclusive operation (ring 1 IM Hit) is received on N2 (802) and forwarded (813) on same ring back to originating node N0 (800). On N3 (803), the incoming second message from the Fetch Exclusive operation (ring 0 IM Hit) is received and forwarded on same ring (813) back to originating node N0. The incoming IM Hit second message on N3 (803) necessitates that the cache ownership state be updated to Invalid since N0(800) will ultimately obtain exclusive ownership of this address. For the Read Only Invalidate command, the incoming second message (ring 0 IM Reject) is received on N2 (802) and forwarded (814) on same ring back to originating node N1 (801). Also, on N3 (803), incoming second message (ring 1 IM Reject) is received and forwarded on same ring (814) back to originating node N1 (801). [0120] [0120]FIG. 8e shows the results of incoming second messages being received at the originating nodes. At N0 (800), the incoming IM Hit message for the Fetch Exclusive command is received on both rings. This results in the N0 cache ownership state being updated to IM, Exclusive to CP. At N1 (801), the incoming IM Reject message is received on both rings for the Read Only Invalidate command. The command is then re-launched on the ring as a Fetch Exclusive command due to the cache ownership state now being Invalid at N1 (801). [0121] Exemplary embodiments disclosed herein are contemplated for use with topologies for shared memory computer systems, an example of one topology is disclosed in related United States Patent Application, entitled: TOPOLOGY FOR SHARED MEMORY COMPUTER SYSTEM, attorney docket number POU920030055 filed contemporaneously with this application. The contents of which are incorporated herein by reference thereto. [0122] While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. It should also be noted that the terms “first”, “second”, and “third” and the like may be used herein to modify elements performing similar and/or analogous functions. These modifiers do not imply a spatial, sequential, or hierarchical order to the modified elements unless specifically stated. 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text:
Meet Richard - An Odoo Story by Odoo 19751 views
How to manage a service company wit... by Odoo 26642 views
Odoo 2016 - Retrospective by Odoo 37942 views
Strategy. Discover the strategy of Odoo for the next 2 years, the direction the product will take and the way we plan to organize the business.
Denise Van der Linden , Sr Technology Business Consultant Finance, Legal & HR at Nike
Thx this has been useful to understand roadmap for the past two years. Are you planning to create an updated version for the next 2 years? One feature I'm especially interested is adding webhooks as a means of integrating to other tools and suppliers e.g. through Zapier or Tradeshift.
Carlos Paz at Carlos Paz
@Anders Wallenquist Fabien wants to buy a $50 million house, like Larry Ellison
Anders @Wallenquist any reference?
Anders Wallenquist at Vertel
Except that Fabien forgot to mention Odoo is switchin to the closed source path during 2015
Iron Mountain at Iron Mountain
Hiromichi Morioka
1. Odoo Roadmap & Strategy Fabien Pinckaers, Founder
2. From 2,000,000 users to 10,000,000 users. or how we will turn Odoo mainstream...
3. from $2M to $10M Investment Areas To Turn Odoo Mainstream 5or how to spend $10M as fast as possible and burn a lot of energy...
4. Release A Product That Deprecates Every Competitor 1This is something we excel at...
5. A product growth no one can follow
6. Version 9: roadmap o 40% Usability: – Improving all existing apps, the right feature at the right place – User onboarding, ease of use o 20% Accounting: – 8 countries in the core o 20% CMS / eCommerce o 10% New design: – Merge front/backend, mobile, modern design o 10% Framework: o New API
7. 1 Release cycle February 2012: v6.1 (13 months)2 January 2013: v7 (11 months)3 June 2014: v8 (18 months)4 June 2015: v9 (12 months)5 Every new version is a revolution. Version 9 will be even more impressive! January 2011: v6.0
8. Attract The Mass Of Users 2It's all about getting users, a lot of users. Not only customers.
9. An attractive pricing... o The cloud, free for 2 users: – Why the cloud? Smooth user experience. High satisfaction rates as everything works out-of-the-box – Unlimited applications: CRM, CMS, eCommerce, Accounting, etc. o Millions of CMS/eCommerce for free: – Already 50k pages on CMS/eCommerce websites built with Odoo CMS Beta – You can do a lot with 2 users: we don't need to get revenues from CMS/eCommerce-only instances as we have so many applications to upsell
10. Affordable implementations o Lower entry barrier - no huge starting costs for SMEs: – No complex implementation projects – A fixed-price packaged offer o New service offer, 100€ / month per application for: – Implementation assistance and configuration – Unlimited customization of screens, reports, workflows – Monthly upgrades – Training material – Unlimited support tickets, 24/24 response time!
11. Disrupt A Market Having A Huge Traction 3Creating the frontend of all apps will not only increase the quality of all apps but also disrupt the CMS/eCommerce market.
12. " " The CMS/eCommerce market looks like the ERP market 6 years ago, before Odoo entered into it. Full of complex products that did not evolve over the past 3 years.
13. Traditional ERPs o The monetization (and main focus) remains on business apps: – Accounting – Warehouse Management – Project Management – Point of sale – Marketing – HR, … o But CMS/eCommerce will bring a huge volume of prospects to our other business apps
14. Make Partners Rich By Making Customers Super-Happy 4 You will like our product and services so much that you will always want to purchase more.
15. Traditional ERPs o Buy an ERP – Invest on 7 years o Maintain as long as you can – Implementations are so painful that you have no other choice – Upgrades are too expensive o After 7 years : it breaks – You change the product and call other vendors
16. Traditional ERPs o Modern companies deserve to: – Evolve continuously – Benefit from top features every year – Be free of any legacy constraints – Have the flexibility to customize easily o Odoo Enterprise – our main value proposition: – Providing so much value to customers through continuous upgrades that they will want to purchase even more
17. Odoo Enterprise o Odoo Enterprise is our core business: – Unlimited upgrades – Unlimited bugfix support – Optional hosting on our cloud – Guarantees : security, performance, legal o Customers shouldn't have to pay for: – Painful upgrades; if upgrades are costly, they tend to not upgrade – Bugs take delay the project and costs man*days of work
18. " " Story of a 1300 users customer I met last week...
19. Let's Burn A Few Millions In Marketing Too 5 We have an awesome product, a huge channel of partners, a strong service offer, ... Now, people need to know it.
20. Marketing activities o Smart Content: – Documentation, books, blog posts, white papers, Q&A – Translations of website and documentation – A super clean website, marketing optimized ! o Inbound Marketing: – SEO, SEA, funnel optimization with a powerful CMS o User/developer on boarding: – Users : usability, clean features, etc. – Devs: docs, easy installation, modules scafolding, ... – Community: efficient tools and communication o Local Events: share, meet and inform people
21. All of this while maintaining a fun working environment and a sane relationship between partners, customers and the community.
22. Relationship between proprietary software vendors and their implementation partners
23. What we do By enforcing full open source rules, we set up the rules to guarantee a sane relationship between all parties of the value chain: ● Vendor: Odoo SA ● Customers ● Partners ● Community
24. 2014-2015 This will be an epic time...

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