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Patent US7877696 - Multi-frame display system with semantic image arrangement - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsMethods and systems for managing presentation of digital images using multiple separate digital media frames each positioned in a separate location and providing images that are viewable within a presentation space, the method comprising the steps of providing access to a source of a plurality of digital...http://www.google.com/patents/US7877696?utm_source=gb-gplus-sharePatent US7877696 - Multi-frame display system with semantic image arrangementAdvanced Patent SearchPublication numberUS7877696 B2Publication typeGrantApplication numberUS 11/650,396Publication dateJan 25, 2011Filing dateJan 5, 2007Priority dateJan 5, 2007Also published asEP2102741A1, US20080235574, WO2008085383A1Publication number11650396, 650396, US 7877696 B2, US 7877696B2, US-B2-7877696, US7877696 B2, US7877696B2InventorsMichael J. Telek, Joel S. Lawther, Dale F. McIntyre, Joseph A. ManicoOriginal AssigneeEastman Kodak CompanyExport CitationBiBTeX, EndNote, RefManPatent Citations (27), Referenced by (3), Classifications (20), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMulti-frame display system with semantic image arrangementUS 7877696 B2Abstract Methods and systems for managing presentation of digital images using multiple separate digital media frames each positioned in a separate location and providing images that are viewable within a presentation space, the method comprising the steps of providing access to a source of a plurality of digital images; determining a semantic type defining at least one semantic element of the digital images to be presented; determining the number of the multiple separate digital media frames that are available to be used for presenting the digital images; determining the semantic content of the accessed digital images; selecting digital images for presentation having determined semantic content that corresponds to the determined semantic type; determining a manner for presenting the selected digital images using the determined number of number of digital media frames; and, presenting the selected digital images in the determined manner.
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Electronics NvVariable size multi-pane display* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS20100293105 *May 15, 2009Nov 18, 2010Microsoft CorporationSocial networking updates for image display devicesUS20120091918 *May 25, 2010Apr 19, 2012Koninklijke Philips Electronics N.V.Picture selection method for modular lighting systemUS20130124518 *Nov 7, 2012May 16, 2013Sony CorporationInformation registration device, information registration method, information registration system, information presentation device, informaton presentation method, informaton presentaton system, and program* Cited by examinerClassifications U.S. Classification715/752, 715/744International ClassificationG06F15/00, G06F13/00Cooperative ClassificationG06F3/147, H04N5/44591, G06F3/1446, H04N5/64, G06F3/1423, H04N21/4122, H04N21/25891, H04N21/84, H04N21/44008, H04N21/4622, H04N21/431European ClassificationG06F3/14C, H04N5/64, G06F3/147, H04N5/445W, G06F3/14C6Legal EventsDateCodeEventDescriptionSep 5, 2013ASAssignmentOwner name: BARCLAYS BANK PLC, AS ADMINISTRATIVE AGENT, NEW YOFree format text: INTELLECTUAL PROPERTY SECURITY AGREEMENT (SECOND LIEN);ASSIGNORS:EASTMAN KODAK COMPANY;FAR EAST DEVELOPMENT LTD.;FPC INC.;AND OTHERS;REEL/FRAME:031159/0001Free format text: RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNORS:CITICORP NORTH AMERICA, INC., AS SENIOR DIP AGENT;WILMINGTON TRUST, NATIONAL ASSOCIATION, AS JUNIOR DIP AGENT;REEL/FRAME:031157/0451Owner name: PAKON, INC., NEW YORKEffective date: 20130903Owner name: EASTMAN KODAK COMPANY, NEW YORKOwner name: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE, DELAFree format text: INTELLECTUAL PROPERTY SECURITY AGREEMENT (FIRST LIEN);ASSIGNORS:EASTMAN KODAK COMPANY;FAR EAST DEVELOPMENT LTD.;FPC INC.;AND OTHERS;REEL/FRAME:031158/0001Free format text: INTELLECTUAL PROPERTY SECURITY AGREEMENT (ABL);ASSIGNORS:EASTMAN KODAK COMPANY;FAR EAST DEVELOPMENTLTD.;FPC INC.;AND OTHERS;REEL/FRAME:031162/0117Owner name: BANK OF AMERICA N.A., AS AGENT, MASSACHUSETTSApr 1, 2013ASAssignmentEffective date: 20130322Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS AGENT,Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:EASTMAN KODAK COMPANY;PAKON, INC.;REEL/FRAME:030122/0235Feb 21, 2012ASAssignmentEffective date: 20120215Free format text: SECURITY INTEREST;ASSIGNORS:EASTMAN KODAK COMPANY;PAKON, INC.;REEL/FRAME:028201/0420Owner name: CITICORP NORTH AMERICA, INC., AS AGENT, NEW YORKJun 9, 2008ASAssignmentOwner name: EASTMAN KODAK COMPANY, NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TELEK, MICHAEL J.;LAWTHER, JOEL S.;MCINTYRE, DALE F.;ANDOTHERS;REEL/FRAME:021066/0914;SIGNING DATES FROM 20070806 TO 20070918Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TELEK, MICHAEL J.;LAWTHER, JOEL S.;MCINTYRE, DALE F.;ANDOTHERS;SIGNING DATES FROM 20070806 TO 20070918;REEL/FRAME:021066/0914RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms 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Patent US5666484 - Control method for distributed processing system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA distributed processor system includes a plurality of processors connected via a transmission medium. A control method for a distributed processor system includes the steps of judging, in each processor, its own receiving capability and performing abnormality processing on the basis of the result of...http://www.google.com/patents/US5666484?utm_source=gb-gplus-sharePatent US5666484 - Control method for distributed processing systemAdvanced Patent SearchPublication numberUS5666484 APublication typeGrantApplication numberUS 07/406,234Publication dateSep 9, 1997Filing dateSep 12, 1989Priority dateSep 14, 1988Fee statusLapsedAlso published asDE68925447D1, DE68925447T2, EP0359241A2, EP0359241A3, EP0359241B1Publication number07406234, 406234, US 5666484 A, US 5666484A, US-A-5666484, US5666484 A, US5666484AInventorsMasayuki Orimo, Kinji Mori, Yasuo Suzuki, Katsumi Kawano, Masuyuki Takeuchi, Masayoshi Matsuura, Yuko TeranishiOriginal AssigneeHitachi, Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (15), Non-Patent Citations (10), Referenced by (44), Classifications (10), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetControl method for distributed processing system
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IBM Systems Journal vol. 26 Nov. 3, 1987.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6070189 *Aug 26, 1997May 30, 2000International Business Machines CorporationSignaling communication events in a computer networkUS6167428 *May 27, 1999Dec 26, 2000Ellis; Frampton E.Personal computer microprocessor firewalls for internet distributed processingUS6334194 *Nov 6, 1998Dec 25, 2001Nec CorporationFault tolerant computer employing double-redundant structureUS6377541 *Nov 29, 1999Apr 23, 2002Siemens AktiengesellschaftMethod and apparatus for transmitting a continuous data stream in packetized formUS6629318 *Aug 2, 1999Sep 30, 2003Koninklijke Philips Electronics N.V.Decoder buffer for streaming video receiver and method of operationUS6725250Dec 17, 1998Apr 20, 2004Ellis, Iii Frampton E.Global network computersUS6732141Nov 26, 1997May 4, 2004Frampton Erroll EllisCommercial distributed processing by personal computers over the internetUS6748550 *Jun 7, 2001Jun 8, 2004International Business Machines CorporationApparatus and method for building metadata using a heartbeat of a clustered systemUS7024449May 20, 1999Apr 4, 2006Ellis Iii Frampton EGlobal network computersUS7035906May 16, 2000Apr 25, 2006Ellis Iii Frampton EGlobal network computersUS7047275Sep 26, 2000May 16, 2006Ellis Frampton EInternal firewall for a personal computer to deny access by a network to a user's secure portionUS7185149 *Oct 17, 2005Feb 27, 2007Nec Electronics CorporationSelective storage in a cache memory deviceUS7305552 *Nov 26, 2003Dec 4, 2007Siemens Communications, Inc.Screen saver displaying identity contentUS7506020Aug 24, 2001Mar 17, 2009Frampton E EllisGlobal network computersUS7535840 *Feb 21, 2002May 19, 2009Sony CorporationInformation processing apparatus and method, recording medium, and programUS7606854Jun 20, 2001Oct 20, 2009Ellis Iii Frampton EInternal hardware firewalls for microchipsUS7634529May 27, 1998Dec 15, 2009Ellis Iii Frampton EPersonal and server computers having microchips with multiple processing units and internal firewallsUS7805756Mar 17, 2004Sep 28, 2010Frampton E EllisMicrochips with inner firewalls, faraday cages, and/or photovoltaic cellsUS7814233Sep 17, 2003Oct 12, 2010Ellis Frampton EComputer and microprocessor control units that are inaccessible from the internetUS7908650Jan 25, 2006Mar 15, 2011Ellis Iii Frampton EComputer or microchip protected from the internet by internal hardwareUS7926097Aug 4, 2005Apr 12, 2011Ellis Iii Frampton EComputer or microchip protected from the internet by internal hardwareUS8209373Feb 3, 2009Jun 26, 2012Ellis Iii Frampton EComputers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewallsUS8225003Jan 11, 2006Jul 17, 2012Ellis Iii Frampton EComputers and microchips with a portion protected by an internal hardware firewallUS8291485Jun 24, 2010Oct 16, 2012Ellis Iii Frampton EComputers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartmentsUS8300535Feb 19, 2010Oct 30, 2012Canon Kabushiki KaishaInformation processing apparatus, method thereof, and storage mediumUS8312529Oct 27, 2011Nov 13, 2012Ellis Frampton EGlobal network computersUS8332924Jun 30, 2008Dec 11, 2012Ellis Frampton EMicrochips with multiple internal hardware-based firewalls and diesUS8516033Jul 11, 2011Aug 20, 2013Frampton E. Ellis, IIIComputers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewallsUS8548068 *Feb 24, 2010Oct 1, 2013Valery Vasilievich OvchinnikovMethod for transmitting discrete electrical signalsUS8555370Aug 24, 2012Oct 8, 2013Frampton E EllisMicrochips with an internal hardware firewallUS8561164Jul 1, 2010Oct 15, 2013Frampton E. Ellis, IIIComputers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a networkUS8627444Aug 30, 2012Jan 7, 2014Frampton E. EllisComputers and microchips with a faraday cage, with a side protected by an internal hardware firewall and unprotected side connected to the internet for network operations, and with internal hardware compartmentsUS8677026Jun 13, 2012Mar 18, 2014Frampton E. Ellis, IIIComputers and microchips with a portion protected by an internal hardware firewallsUS8726303Jan 31, 2011May 13, 2014Frampton E. Ellis, IIIMicrochips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a networkUS8739195Jan 28, 2011May 27, 2014Frampton E. Ellis, IIIMicrochips with an internal hardware firewall protected portion and a network portion with microprocessors which execute shared processing operations with the networkUS8775622 *Aug 1, 2005Jul 8, 2014Sony CorporationComputer-based cluster management system and methodUS8811418Jul 15, 2011Aug 19, 2014Canon Kabushiki KaishaInformation processing apparatus, information processing method, and storage mediumUS8892627Mar 3, 2013Nov 18, 2014Frampton E. EllisComputers or microchips with a primary internal hardware firewall and with multiple internal harware compartments protected by multiple secondary interior hardware firewallsUS8898768Mar 15, 2013Nov 25, 2014Frampton E. EllisComputer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessorUS8948542Jun 3, 2011Feb 3, 2015Canon Kabushiki KaishaImage processing apparatusUS20090276673 *Dec 23, 2008Nov 5, 2009Industrial Technology Research InstituteMethods and systems for optimizing harq communicationUS20090300451 *Feb 11, 2009Dec 3, 2009Fujitsu LimitedFrame transferring apparatus and frame transferring systemUS20120033744 *Feb 24, 2010Feb 9, 2012Valery Vasilievich OvchinnikovMethod for transmitting discrete electrical signalsWO1998026366A2 *Nov 28, 1997Jun 18, 1998Frampton E Ellis IiiGlobal network computers* Cited by examinerClassifications U.S. Classification714/18, 714/748International ClassificationG06F15/177, G06F9/50, G06F15/16, G06F15/173Cooperative ClassificationG06F15/17337, G06F9/5083European ClassificationG06F15/173D, G06F9/50LLegal EventsDateCodeEventDescriptionNov 8, 2005FPExpired due to failure to pay maintenance feeEffective date: 20050909Sep 9, 2005LAPSLapse for failure to pay maintenance feesMar 30, 2005REMIMaintenance fee reminder mailedMar 9, 2001FPAYFee paymentYear of fee payment: 4Sep 12, 1989ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:ORIMO, MASAYUKI;MORI, KINJI;SUZUKI, YASUO;AND OTHERS;REEL/FRAME:005131/0918Effective date: 19890905RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


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Patent US20020160551 - Memory elements and methods for making same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAnnular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium...http://www.google.com/patents/US20020160551?utm_source=gb-gplus-sharePatent US20020160551 - Memory elements and methods for making sameAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20020160551 A1Publication typeApplicationApplication numberUS 09/809,561Publication dateOct 31, 2002Filing dateMar 15, 2001Priority dateMar 15, 2001Also published asUS6563156, US7504730, US8076783, US8362625, US8786101, US20040124503, US20080017953, US20090152737, US20120080798, US20130140703, USRE40842Publication number09809561, 809561, US 2002/0160551 A1, US 2002/160551 A1, US 20020160551 A1, US 20020160551A1, US 2002160551 A1, US 2002160551A1, US-A1-20020160551, US-A1-2002160551, US2002/0160551A1, US2002/160551A1, US20020160551 A1, US20020160551A1, US2002160551 A1, US2002160551A1InventorsSteven HarshfieldOriginal AssigneeHarshfield Steven T.Export CitationBiBTeX, EndNote, RefManReferenced by (89), Classifications (20), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMemory elements and methods for making same
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS [0047] Specific embodiments of memory elements and methods of making such memory elements are described below as they might be implemented for use in semiconductor memory circuits. In the interest of clarity, not all features of an actual implementation are described in this specification. It should be appreciated that in the development of any such actual implementation (as in any semiconductor engineering project), numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of semiconductor design and fabrication for those of ordinary skill having the benefit of this disclosure. [0048] Turning now to the drawings, and referring initially to FIG. 1, a memory device is illustrated and generally designated by a reference numeral 10. The memory device 10 is an integrated circuit memory that is advantageously formed on a semiconductor substrate 12. The memory device 10 includes a memory matrix or array 14 that includes a plurality of memory cells for storing data, as described below. The memory matrix 14 is coupled to periphery circuitry 16 by the plurality of control lines 18. The periphery circuitry 16 may include circuitry for addressing the memory cells contained within the memory matrix 14, along with circuitry for storing data in and retrieving data from the memory cells. The periphery circuitry 16 may also include other circuitry used for controlling or otherwise insuring the proper functioning of the memory device 10. [0049] A more detailed depiction of the memory matrix 14 is illustrated in FIG. 2. As can be seen, the memory matrix 14 includes a plurality of memory cells 20 that are arranged in generally perpendicular rows and columns. The memory cells 20 in each row are coupled together by a respective word line 22, and the memory cells 20 in each column are coupled together by a respective digit line 24. Specifically, each memory cell 20 includes a word line node 26 that is coupled to a respective word line 22, and each memory cell 20 includes a digit line node 28 that is coupled to a respective digit line 24. The conductive word lines 22 and digit lines 24 are collectively referred to as address lines. These address lines are electrically coupled to the periphery circuitry 16 so that each of the memory cells 20 can be accessed for the storage and retrieval of information. [0050] [0050]FIG. 3 illustrates an exemplary memory cell 20 that may be used in the memory matrix 14. The memory cell 20 includes a memory element 30 which is coupled to an access device 32. In this embodiment, the memory element 30 is illustrated as a programmable resistive element, and the access device 32 is illustrated as a diode. Advantageously, the programmable resistive element may be made of a chalcogenide material, as will be more fully explained below. Also, the diode 32 may be a conventional diode, a zener diode, or an avalanche diode, depending upon whether the diode array of the memory matrix 14 is operated in a forward biased mode or a reverse biased mode. As illustrated in FIG. 3, the memory element 30 is coupled to a word line 22, and the access device 32 is coupled to a digit line 24. However, it should be understood that connections of the memory element 20 may be reversed without adversely affecting the operation of the memory matrix 14. [0051] As mentioned previously, a chalcogenide resistor may be used as the memory element 30. A chalcogenide resistor is a structure changing memory element because its molecular order may be changed between an amorphous state and a crystalline state by the application of electrical current. In other words, a chalcogenide resistor is made of a state changeable material that can be switched from one detectable state to another detectable state or states. In state changeable materials, the detectable states may differ in their morphology, surface typography, relative degree of order, relative degree of disorder, electrical properties, optical properties, or combinations of one or more of these properties. The state of a state changeable material may be detected by measuring the electrical conductivity, electrical resistivity, optical transmissivity, optical absorption, optical refraction, optical reflectivity, or a combination of these properties. In the case of a chalcogenide resistor specifically, it may be switched between different structural states of local order across the entire spectrum between the completely amorphous state and the completely crystalline state. [0052] The previously mentioned Ovshinsky patent contains a graphical representation of the resistance of an exemplary chalcogenide resistor as a function of voltage applied across the resistor. It is not unusal for a chalcogenide resistor to demonstrate a wide dynamic range of attainable resistance values of about two orders of magnitude. When the chalcogenide resistor is in its amorphous state, its resistance is relatively high. As the chalcogenide resistor changes to its crystalline state, its resistance decreases. [0053] As discussed in the Ovshinsky patent, low voltages do not alter the structure of a chalcogenide resistor, while higher voltages may alter its structure. Thus, to “program” a chalcogenide resistor, i.e., to place the chalcogenide resistor in a selected physical or resistive state, a selected voltage in the range of higher voltages is applied across the chalcogenide resistor, i.e., between the word line 22 and the digit line 24. Once the state of the chalcogenide resistor has been set by the appropriate programming voltage, the state does not change until another programming voltage is applied to the chalcogenide resistor. Therefore, once the chalcogenide resistor has been programmed, a low voltage may be applied to the chalcogenide resistor, i.e., between the word line 22 and the digit line 24, to determine its resistance without changing its physical state. As mentioned previously, the addressing, programming, and reading of the memory elements 20 and, thus, the application of particular voltages across the word lines 22 and digit lines 24, is facilitated by the periphery circuitry 16. [0054] The memory cell 20, as illustrated in FIG. 3, may offer significant packaging advantages as compared with memory cells used in traditional random access and read only memories. This advantage stems from the fact that the memory cell 20 is a vertically integrated device. In other words, the memory element 30 may be fabricated on top of the access device 32. Therefore, using the memory cell 20, it may be possible to fabricate a cross-point cell that is the same size as the crossing area of the word line 22 and the digit line 24, as illustrated in FIG. 4. However, the size of the access device 32 typically limits the area of the memory cell 20, because the access device 32 must be large enough to handle the programming current needed by the memory element 30. [0055] As discussed previously, to reduce the required programming current, many efforts have been made to reduce the pore size of the chalcogenide material that forms the memory element 30. These efforts have been made in view of the theory that only a small portion of the chalcogenide material, referred to as the “active region,” is structurally altered by the programming current. However, it is believed that the size of the active region of the chalcogenide memory element 30 may be reduced by reducing the size of an electrode which borders the chalcogenide material. By reducing the active region and, thus, the required programming current, the size of the access device may be reduced to create a cross-point cell memory. [0056] To make a commercially viable semiconductor memory array having a plurality of such memory cells, such memory cells should be reproducible so that all memory cells act substantially the same. As alluded to earlier, by controlling the active region of the chalcogenide material of each memory cell, a memory array of relatively uniform memory cells may be created. To control the active region, the contact area between the chalcogenide and one or both of its electrodes may be controlled, and/or the volume of the chalcogenide material may be controlled. However, as described next, one technique for creating a substantially circular memory element using chalcogenide material, which produces good results, may nonetheless be improved upon to create memory cells having more uniformity. Before discussing these improvements, however, it is important to understand the technique for creating a substantially circular memory element. [0057] This technique for creating a circular non-volatile memory element generally begins with a small photolithographically defined feature. This feature, a circular hole, is reduced in circumference by adding a non-conductive material, such as a dielectric, to its sidewalls. The resulting smaller hole serves as a pattern for a pore that holds an electrode and/or the structure changing memory material. In either case, the final contact area between the structure changing memory material and the electrode is approximately equal to the circular area of the smaller hole. [0058] The actual structure of an exemplary memory cell 20 is illustrated in FIG. 15, while a method for fabricating the memory cell 20 is described with reference to FIGS. 5-15. It should be understood that while the fabrication of only a single memory cell 20 is discussed below, thousands of similar memory cells may be fabricated simultaneously. Although not illustrated, each memory cell is electrically isolated from other memory cells in the array in any suitable manner, such as by the addition imbedded field oxide regions between each memory cell. [0059] In the interest of clarity, the reference numerals designating the more general structures described in reference to FIGS. 1-4 will be used to describe the more detailed structures illustrated in FIGS. 5-15, where appropriate. Referring first to FIG. 5, the digit lines 24 are formed in or on a substrate 12. As illustrated in FIG. 5, the digit line 24 is formed in the P-type substrate 12 as a heavily doped N+ type trench. This trench may be strapped with appropriate materials to enhance its conductivity. The access device 32 is formed on top of the digit line 24. The illustrated access device 32 is a diode formed by a layer of N doped polysilicon 40 and a layer of P+ doped polysilicon 42. Next, a layer of insulative or dielectric material 44 is disposed on top of the P+ layer 42. The layer 44 may be formed from any suitable insulative or dielectric material, such as silicon nitride. [0060] The formation of a small pore in the dielectric layer 44 is illustrated with reference to FIGS. 5-9. First, a hard mask 46 is deposited on top of the dielectric layer 44 and patterned to form a window 48, as illustrated in FIG. 6. The window 48 in the hard mask 46 is advantageously as small as possible. For instance, the window 48 may be formed at the photolithographic limit by conventional photolithographic techniques. The photolithographic limit, i.e., the smallest feature that can be patterned using photolithographic techniques, is currently about 0.18 micrometers. Once the window 48 has been formed in the hard mask 46, a layer of spacer material 50, such as silicon dioxide, is deposited over the hard mask 46 in a conformal fashion so that the upper surface of the spacer material 50 is recessed where the spacer material 50 covers the window 48. [0061] The layer of spacer material 50 is subjected to an anisotropic etch using a suitable etchant, such as CHF3. The rate and time of the etch are controlled so that the layer of spacer material 50 is substantially removed from the upper surface of the hard mask 48 and from a portion of the upper surface of the dielectric layer 44 within the window 48, leaving sidewall spacers 52 within the window 48. The sidewall spacers 52 remain after a properly controlled etch because the vertical dimension of the spacer material 50 near the sidewalls of the window 48 is approximately twice as great as the vertical dimension of the spacer material 50 on the surface of the hard mask 46 and in the recessed area of the window 48. [0062] Once the spacers 52 have been formed, an etchant is applied to the structure to form a pore 54 in the dielectric layer 44, as illustrated in FIG. 8. The etchant is an anisotropic etchant that selectively removes the material of the dielectric layer 44 bounded by the spacers 52 until the P+ layer 42 is reached. As a result of the fabrication method to this point, if the window 48 is at the photolithographic limit, the pore 54 is smaller than the photolithigraphic limit, e.g., on the order of 0.06 micrometers. After the pore 54 has been formed, the hard mask 46 and the spacers 52 may be removed, as illustrated in FIG. 9. The hard mask 46 and the spacers 52 may be removed by any suitable method, such as by etching or by chemical mechanical planarization (CMP). [0063] The pore 54 is then filled to a desired level with a material suitable to form the lower electrode of the chalcogenide memory element 30. As illustrated in FIG. 10, a layer of electrode material 56 is deposited using collimated physical vapor deposition (PVD). By using collimated PVD, or another suitable directional deposition technique, the layer of electrode material 56 is formed on top of the dielectric layer 44 and within the pore 54 with substantially no sidewalls. Thus, the layer of electrode material 56 on top of the dielectric layer 44 may be removed, using CMP for instance, to leave the electrode 56 at the bottom of the pore 54, as illustrated in FIG. 11. It should be understood that the electrode material 56 may be comprised of one or more materials, and it may be formed in one or more layers. For instance, a lower layer of carbon may be used as a barrier layer to prevent unwanted migration between the subsequently deposited chalcogenide material and the P+ type layer 42. A layer of titanium nitride (TiN) may then be deposited upon the layer of carbon to complete the formation of the electrode 56. [0064] After the lower electrode 56 has been formed, a layer of chalcogenide material 58 may be deposited so that it contacts the lower electrode 56, as illustrated in FIG. 12. If the lower electrode 56 is recessed within the pore 54, a portion of the chalcogenide material 58 will fill the remaining portion of the pore 54. In this case, any chalcogenide material 58 adjacent the pore 54 on the surface of the dielectric layer 44 may be removed, using CMP for instance, to create a chalcogenide element of extremely small proportions. Alternatively, if the lower electrode 56 completely fills the pore 54, the chalcogenide material 58 adjacent the pore 54 may remain, because the extremely small size of the lower electrode 56 still creates a relatively small active area in a vertical direction through the chalcogenide material 58. Because of this characteristic, even if the lower electrode 56 only partially fills the pore 54, as illustrated, the excess chalcogenide material 58 adjacent the pore 54 need not be removed to create a memory element 30 having an extremely small active area. [0065] Regardless of which alternative is chosen, the upper electrode 60 is deposited on top of the chalcogenide material 58, as illustrated in FIG. 13. After the upper electrode 60, the chalcogenide material 58, the dielectric layer 44, and the access device 32 have been patterned and etched to form an individual memory cell 20, a layer of insulative material 62 is deposited over the structure, as illustrated in FIG. 14. A layer of oxide 64 is then deposited over the insulative layer 62. Finally, the oxide layer 64 is patterned and a contact hole 66 is formed through the oxide layer 64 and the insulative layer 62, as illustrated in FIG. 15. The contact hole 66 is filled with a conductive material to form the word line 22. [0066] Although this technique, as previously mentioned, produces good results, there can be substantial variation in size of the many circular pores 54 formed to create the memory cell array. Lithographic variations during the formation of a structure such as the one described above are typically in the range of �10% of the lithographic feature, i.e., �10% of the diameter of the window 48. A variation in circular area (ΔAfwith respect to the intended circular area (ΔAf) is approximately equal to: Δ   A f A f ≈ Δ   R i R i  ( 2  R i R f ) . Equation   1 [0067] where Ri represents the initial radius of the window 48, and Rf represents the final radius of the pore 54, and ΔRi represents the variation in the radius Ri due to, for example, photolithography and pattern transfer. Photolithographic deviations in pore formation can cause a variation in actual contact area versus intended contact area that is approximately equal to the variation in actual radius of the window 48 versus the desired radius of the window 48 multiplied by twice the ratio of the variation in the actual radius versus desired radius. [0068] Similarly, deposition thickness deviations during formation of the spacers 52 are typically in the range of �10% of the deposited layer's thickness. A variation in circular contact area (ΔAf) with respect to the intended circular contact area (Af) is approximately equal to: Δ   A f A f ≈ Δ   h s h s  ( 2 - 2  R i R f ) , Equation   2 [0069] where hs represents the thickness of the spacer 52, Δhs represents the variation in the thickness of the spacer 52, and Ri and Rf are defined above. Deposition deviations in spacer thickness can cause a variation in actual circular contact area versus intended contact area that is approximately equal to the variation in spacer thickness versus the desired spacer thickness multiplied by a number greater than zero which is dependent upon the initial and final contact hole radius. [0070] Because of photolithographic and deposition variations during processing, such as those discussed above, the reproducibility of small circular contacts between different elements in a semiconductor circuit can suffer. To enhance the uniformity and reproducibility of contacts between different elements in a semiconductor circuit, an annular contact structure, which exhibits a greatly reduced susceptibility to process variations, may be implemented. However, before discussing an exemplary implementation, the reduced susceptibility to process variations will first be explained using many of the terms defined above for clarity and comparison. [0071] Area variation (ΔAf) for an annular contact which is thin with respect to the intended contact area (Af) is approximately equal to the ratio of the variation in the initial contact hole's radius versus the desired initial contact hole radius, Δ   A f A f ≈ Δ   R i R i , Equation   3 [0072] where Ri represents the circular window's initial radius before an annular contact is formed, and ΔRi represents the variation in the annular contact's radius as a result of forming the annulus. [0073] Similarly, deviations in deposition thickness of an annular contact structure cause a variation in contact area (ΔAf) versus intended area (Af) that is approximately equal to the variation in annulus thickness versus the desired annulus thickness, Δ   A f A f ≈ Δ   h A h A , Equation   4 [0074] where hA represents annulus thickness, and ΔhA represents the variation in annulus thickness. [0075] Comparison of Equation 3 with Equation 1 demonstrates that a thin annular contact structure exhibits less deviation due to lithographic variations than does a circular contact structure having an equal area: Δ   A A A f ≈ Δ   R i R i   and   Δ   A C A f ≈ Δ   R i R i  ( 2  R i R f ) . [0076] Since Ri is always greater than Rf,  Δ   R i R i  <  Δ   R i R i  ( 2  R i R f )  . Equation   5 [0077] Thus,  Δ   A A A f  <  Δ   A C A f  . Equation   6 [0078] Here, Af represents the final or desired contact area, ΔAA represents the variation in the annular contact area, ΔAC represents the variation in the circular contact area, Ri represents the contact hole's initial radius, Rf represents the contact hole's final radius, ΔRi represents the variation in the contact hole's radius due to, for example, lithographic and pattern transfer operations, and ∥ represents an absolute value operation. [0079] Likewise, a comparison of Equation 4 and Equation 2 demonstrates that a thin annular contact structure, which would correspond in area to a circular contact with final radius less than approximately two-thirds the initial radius, exhibits less deviation due to deposition variations than does the corresponding circular contact structure: Δ   A A A f ≈ Δ   h A h A   and   Δ   A C A f ≈ Δ   h S h s  ( 2 - 2  R i R f ) .  Where   R f < 2 3  R i ,   Δ   h A h A  <  Δ   h s h s  ( 2 - 2  R i R f )  . Equation   7 [0080] From fabrication experience it is observed Δ   h A h A ≈ Δ   h s h s [0081] that for a large variety of materials over a large range of thicknesses. Thus,  Δ   A A A f  <  Δ   A C A f  , Equation   8 [0082] where all symbols retain their previous definitions. [0083] Thus, as compared to small sublithographic circular contacts, a contact structure having a thin annular geometry provides a more reproducible feature. That is, starting from the same lithographic feature, i.e., a contact hole or window, and ending with the same contact area, a thin annular contact should have less variation in contact area than a comparable circular contact. Furthermore, due to the relatively wide contact hole of the annular contact, it is easier to produce a conformal annular contact than it is a void-free circular contact. Also, the annular extent may be greater for less susceptibility to being blocked by particles. [0084] Turning again to the drawings, and referring to FIG. 16, a flowchart 100 depicts one method for forming a thin annular contact structure. By further referring to FIGS. 17-25, in conjunction with the method set forth in the flowchart 100, there is illustrated a semiconductor device, in various stages of fabrication, in which a thin annular contact structure is formed. [0085] Referring first to block 102 and FIG. 17, a semiconductor substrate 104 is provided. The substrate 104 may contain various device structures that have not been illustrated for the sake of clarity. For instance, the substrate 104 may include a digit line and an access device, such as the digit line 24 and the access device 32 described above with reference to FIGS. 5-15. A conductive layer 106 is deposited onto the substrate 104. This conductive layer 106 may be deposited in any suitable manner, such as by physical or chemical vapor deposition. The conductive layer 106 may be comprised of one or more layers, and it may include one or more materials. For instance, if the conductive layer 106 is to be used as the bottom electrode for a chalcogenide memory element, the conductive layer 106 may include a layer of titanium nitride deposited on the substrate 104, with a layer of carbon deposited on the layer of titanium nitride to prevent unwanted migration between the subsequently deposited chalcogenide material and the substrate 104. [0086] Referring next to block 108 and FIG. 18, a first insulating layer 110 is formed on top of the conductive layer 106. The insulating layer 110 may be formed in any suitable manner, such as by CVD. The material used for the first insulating layer 110 can be, for example, a relatively thick layer of boron and phosphorous doped silicon dioxide glass (BPSG), which may be advantageous for deep contacts, e.g., contact holes having a depth greater than their diameter. Alternatively, the material used for the first insulating layer 110 could be undoped silicon dioxide or silicon nitride, which may be advantageous for shallow contacts, e.g., contact holes having a depth less than their diameter. As will be discussed below, using silicon nitride as the material for the first insulating layer 110 may provide a further benefit in that it can serve as a CMP stop material. [0087] Referring now to block 112 and FIG. 19, a contact hole or window 114 is formed through the insulating layer 110 to expose a portion of the underlying conductive layer 106. Again, any suitable method of forming the window 114 may be used. For instance, using standard photolithographic techniques, a hard mask (not shown) may be deposited on top of the insulating layer 110 and patterned in the size and shape of the resulting window 114, advantageously at the photolithographic limit. An etchant may then be applied to remove the insulating material under the patterned hard mask to form the window 114. After etching, the hard mask is removed. However, the window 114 may also be fabricated to be smaller than the photolithographic limit by using spacer technology, as described previously with reference to FIGS. 6-9. [0088] As can be seen in block 116 and FIG. 20, a thin film 118 is disposed over the insulating layer 110 and the window 114. The thickness of the film 118 is small compared to the radius of the window 114. The film 118 may be a conductive material, if an annular electrode is to be formed, or the film 118 may be a structure changing memory material, such as chalcogenide, if an annular memory element is to be formed. For the purpose of clarity, the formation of an annular electrode will first be discussed, followed by a discussion of the formation of an annular memory element. [0089] Generally speaking, any conductive material that is conformal to the window 114 and which has good adhesion properties for a subsequently formed insulating layer may be suitable to form the film 118. Exemplary conductive materials may include titanium nitride, carbon, aluminum, titanium, tungsten, tungsten silicide, and copper, along with combinations and alloys of these materials. A benefit of using carbon as the conductive material is that it can serve as a mechanical stop for a subsequent CMP process described below. [0090] Referring next to block 120 and FIG. 21, a second insulating layer 122 is formed over the structure. In general, the thickness of the second insulating layer 122 is one to two times the depth of the contact hole 114 for shallow contact holes. The same materials used to form the first insulating layer 110 may also be used to form the second insulating layer 122. [0091] The second insulating layer 122 and the conductive film 118 are removed from the surface of the first insulating layer 110 to form an annular electrode 124, as may be seen from a study of block 126 and FIGS. 22 and 23. One technique for removing the second insulating layer 122 and the conductive film 118 on top of the layer 110 is the CMP process. The CMP process may be performed in one or more steps. For instance, if a CMP stop material, such as carbon, is used as the conductive film 118, or if a layer of carbon is disposed on top of the layer 110, the CMP step may be followed by an etch, such as a plasma-oxygen etch, for example, to remove any horizontally extending carbon that may be left in tact by the CMP operation. Alternatively, the layer 110 may be used as a CMP stop, so the conductive film 118 would not act as a CMP stop. Typical conducting materials that may be used that are not natural CMP stops include titanium nitride and tungsten silicide. Accordingly, in this example, an additional etching step would not be used. [0092] If the annular electrode 124 is to be used as a bottom electrode of a chalcogenide memory element, the remainder of the memory cell is created, as set forth in block 134. To create a memory cell, a layer of chalcogenide 130 may be deposited over the annular electrode 124, and another conductive layer or line 132 may be deposited over the layer of chalcogenide 130, as illustrated in FIG. 24. In this example, the thickness of the layer of chalcogenide 130 is controlled, but the volume of the layer of chalcogenide 130 is not controlled. In fact, the layer of chalcogenide 130 may be a blanket layer or a linear layer formed over other annular electrodes in the array. However, the contact area between the annular electrode 124 and the layer of chalcogenide 130 is controlled well, which in turn controls the chalcogenide active region. Thus, an array of such memory cells should contain a plurality of reproducible memory elements with uniform active regions. In view of current theory, such memory cells should operate in a uniform manner suitable for a modem high density semiconductor memory. [0093] Now, referring back to FIG. 20 and to block 140 of FIG. 16, the formation of an annular memory element will be discussed using the same reference numerals occasionally to refer to different materials than those discussed above for purposes of clarity. For instance, instead of the film 118 being composed of a conductive material, as discussed above, the film 118 may be composed of a structure changing memory material. Such memory material may be chalcogenide or any other suitable memory material. Such memory material should also be suitable for conformal deposition in the window 114 and demonstrate good adhesion properties for a subsequently formed insulating layer. [0094] Various types of chalcogenide materials may be used to form the film 118. For example, chalcogenide alloys may be formed from tellurium, antimony, germanium, selenium, bismuth, lead, strontium, arsenic, sulfur, silicon, phosphorous, and oxygen. Advantageously, the particular alloy selected should be capable of assuming at least two generally stable states in response to a stimulus, for a binary memory, and capable of assuming multiple generally stable states in response to a stimulus, for a higher order memory. Generally speaking, the stimulus will be an electrical signal, and the multiple states will be different states of crystallinity having varying levels of electrical resistance. Alloys that may be particularly advantageous include tellurium, antimony, and germanium having approximately 55 to 85 percent tellurium and 15 to 25 percent germanium, such as Te56Ge22Sb22. [0095] Referring next to block 142 and FIG. 21, a second insulating layer 122 is formed over the structure. In general, the thickness of the second insulating layer 122 is one to two times the depth of the contact hole 114 for shallow contact holes. The same materials used to form the first insulating layer 110 may also be used to form the second insulating layer 122. [0096] The second insulating layer 122 and the memory film 118 are removed from the surface of the first insulating layer 110 to form an annular memory element 124, as may be seen from a study of block 144 and FIGS. 22 and 23. The second insulating layer 122 and the memory film 118 may be removed by any suitable process, such as an etching process, CMP process, or combination thereof, to expose the annular memory element 124. [0097] In this case, the conductive layer 106 serves as the bottom electrode of the chalcogenide memory element. Therefore, a second conductive layer or line 146 may be deposited over the annular memory element 124, as illustrated in FIG. 25. In this example, the volume of the memory film 118 is controlled well (possibly even better than in the prior embodiment), as is the contact area between the annular memory element 124 and the second conductive layer 146. Thus, an array of such memory elements should contain a plurality of reproducible memory cells with very uniform active regions. In view of current theory, such memory cells should operate in a uniform manner suitable for a modem high density semiconductor memory. [0098] To this point the discussion has centered around circular and annular contact areas. However, many of the advantages that annular contact areas have as compared with circular contact areas may also be exhibited by contact areas having different shapes. For instance, linear contact areas and hollow rectangular contact areas, as well as contact areas having various other hollow geometric shapes, may be fabricated to control the contact area and/or the volume of the memory material more precisely than known methods. For example, a hollow rectangular contact area may be formed in virtually the same manner as described above with reference to FIGS. 16-25, the only major difference being that the window 114 should be patterned in a rectangular rather than a circular shape. [0099] The formation of linear contact areas, on the other hand, may benefit from the following additional discussion which refers to FIGS. 26-33. In this discussion, it should be understood that the structures illustrated in FIGS. 26-33 may be formed using the materials and fabrication techniques described above. Therefore, these details will not be repeated. [0100] Rather than patterning a discrete window in an insulating layer, as illustrated in FIG. 19, a trench 150 may be patterned in a first insulating layer 152. As in the earlier embodiment, the first insulating layer 152 is disposed over a conductive layer 154 which is disposed on a substrate 156. As can be seen in FIG. 27, a thin film 158 is disposed over the insulating layer 152 and the trench 150. As before, the thickness of the film 158 is advantageously small compared to the width of the trench 150. [0101] As in the previous embodiment, the film 158 may be a conductive material, if a linear electrode is to be formed, or the film 158 may be a structure changing memory material, such as chalcogenide, if a linear memory element is to be formed. Again, for the purpose of clarity, the formation of a linear electrode will first be discussed, followed by a discussion of the formation of a linear memory element. [0102] If the film 158 is a conductive material, as described previously, a second insulating layer 160 is formed over the structure. In general, the thickness of the second insulating layer 160 is one to two times the depth of the trench 150 for shallow trenches. The second insulating layer 160 and the conductive film 158 are removed from the surface of the first insulating layer 152 to form two linear electrodes 162 and 164, as may be seen from a study of FIGS. 28 and 29. [0103] If the linear electrodes 162 and 164 are to be used as the bottom electrodes for chalcogenide memory elements, the remainder of the memory cell is created. To create a memory cell, a layer of chalcogenide 166 may be deposited over the linear electrodes 162 and 164, and another conductive layer 168 may be deposited over the layer of chalcogenide 166. Then, the layers 166 and 168 may be patterned to create linear features that are perpendicular to the linear electrodes 162 and 164, as illustrated in FIGS. 30 and 31. These features may have a width at or below the photolithographic limit. It should be noted that the patterned conductive layers 168 form word lines (the digit lines being formed in the substrate 156) which are perpendicular to the linear electrodes 162 and 164 to create an array of addressable memory cells. It should also be noted that the portions of the linear electrodes 162 and 164 between the patterned conductive layers 168 may be removed, or otherwise processed, to make each cell electrically distinct. [0104] In this example, the contact area between the linear electrodes 162 and 164 and the layer of chalcogenide 166 is controlled well and can be smaller than an annular contact area. Furthermore, an active region in the layer of chalcogenide 166 can have less volume than the blanket layer of chalcogenide 130 discussed previously. Thus, an array of such memory cells should contain a plurality of reproducible memory elements with small, uniform active regions. In view of current theory, such memory cells should operate in a uniform manner suitable for a modern high density semiconductor memory. [0105] Now, referring back to FIG. 27, the formation of a linear memory element will be discussed using the same reference numerals occasionally to refer to different materials than those discussed above for purposes of clarity. For instance, instead of the film 158 being composed of a conductive material, as discussed above, the film 158 may be composed of a structure changing memory material. Such memory material may be chalcogenide or any other suitable memory material. Such memory material should also be suitable for conformal deposition in the trench 150 and demonstrate good adhesion properties for a subsequently formed insulating layer. [0106] Referring next to FIGS. 28 and 29, a second insulating layer 160 is formed over the structure, and the second insulating layer 160 and the memory film 158 are removed from the surface of the first insulating layer 152 to form two linear memory elements 162 and 164. In this case, the conductive layer 154 serves as the bottom electrode of the chalcogenide memory element. Therefore, a second conductive layer 170 may be deposited over the linear memory elements 162 and 164 and etched to form conductive lines substantially perpendicular to the linear memory elements 162 and 164, as illustrated in FIGS. 32 and 33. As in the previous embodiment, the portions of the linear memory elements 162 and 164 between the conductive layers 170 may be removed, or otherwise processed, to make each memory cell electrically distinct. In this example, the volume of the memory film 158 is controlled well, as is the contact area between the linear memory elements 162 and 164 and the second conductive layer 170. Thus, an array of such memory elements should contain a plurality of reproducible memory cells with small and very uniform active regions. In view of current theory, such memory cells should operate in a uniform manner suitable for a modern high density semiconductor memory. [0107] It should be recognized that methods of fabricating contact structures other than the methods described above may be utilized to fabricate similar contact structures. For instance, a “facet etch” process may be utilized to create similar contact structures without using a CMP process which may be damaging to the chalcogenide material or to the small features of the contact structure. Indeed, a facet etch process can create structures that are difficult, if not impossible, to make using CMP. An example of a facet etch process is described below with reference to FIGS. 34-41. In this discussion, it should be understood that the structures illustrated in FIGS. 34-41 may be formed using the materials and fabrication techniques described above, except as stated otherwise. Therefore, these details will not be repeated. [0108] As illustrated in FIG. 34, a structure similar to the initial structure of the previous embodiments is formed. Specifically, a conductive layer 180 is deposited over a substrate 182. A first insulating layer 184 is deposited over the conductive layer 180, and a window or trench 186 is formed in the first insulating layer 184. Then, a conformal second conductive layer 188 is deposited over the first insulating layer 184 and over the window or trench 186. [0109] Unlike the previously described embodiments, a thin conformal second insulating layer 190 is deposited over the conformal second conductive layer 188, as illustrated in FIG. 35. A facet etch is then performed to remove portions of the second insulating layer 190 at the edges 192 of the window or trench 186, as shown in FIG. 36. A facet etch using an argon etchant, for example, can remove the second insulating layer 190 from the edges 192 at a rate up to four times that which is removed at the planar surfaces. It should be noted that this process leaves the second layer of insulating material 190 on the vertical and horizontal surfaces of the window or trench 186. Thus, the facet etch creates a geometric contact, such as an annular or rectangular contact, if the feature 186 is a window, and it creates a linear contact is the feature 186 is a trench. [0110] Once the second conductive layer 188 is exposed at the edges 192, subsequent layers may be deposited to complete a circuit. For example, the window or trench 186 may be filled with a layer of chalcogenide 194, as shown in FIG. 37. Note that contact between the chalcogenide layer 194 and the second conductive layer 188 occurs only at the edges 192. An upper electrode of conductive material 195 and other features may be formed over the layer of chalcogenide 194 to complete the memory cell and memory array. [0111] Alternatively, as with the previous embodiments, the layer 188 illustrated in FIGS. 34-37 may be a layer of structure changing material, such as chalcogenide. In this case, the facet etch removes the edges of the second insulating layer 190 to expose the corners 192 of the chalcogenide layer 188. Accordingly, rather than filling the window or trench 186 with a layer of chalcogenide material, a second conductive layer 196 is deposited, as illustrated in FIG. 38. As before, other features may be formed on the second conductive layer 196 to finish the circuit. [0112] It should be further appreciated that the facet etch process just described may be used on protruding features, as well as the window or trench 186. In contrast, the CMP process probably cannot be used on protruding features with much success, and the CMP process may also have problems with trenches and other large shapes. As illustrated in FIG. 39, a protruding feature 200 may be formed on a substrate 202. As with the embodiments described above, the substrate 202 may contain features or circuitry, such as an access device. In one example, the protruding feature 200 may be a conductive pillar or line, depending on whether a geometric or linear contact is desired. A conformal insulating layer 204 is deposited over the conductive pillar or line 200, and a facet etch is performed to remove the edges of the insulating layer to expose the edges 206 of the conductive pillar or line 200, as illustrated in FIG. 40. Once the edges 206 of the conductive pillar or line 200 have been exposed to form a contact, a layer of chalcogenide 208 may be formed over the structure, as illustrated in FIG. 41. To complete the memory cell, a second layer of conductive material 210 may be formed over the chalcogenide layer 208. [0113] Of course, the protruding feature 200 may be a chalcogenide pillar or line. In this example, the substrate 202 may also include a conductive layer or layers which form the bottom electrode of a chalcogenide memory cell. Accordingly, after the insulating layer 204 has been deposited and the edges removed to expose the edges 206 of the chalcogenide pillar or line 200, the layer 208 may be formed using a conductive material or materials to complete the memory cell and the layer 210 of FIG. 41 may be omitted. [0114] In addition to forming geometric or linear contacts, the facet etch process may also be utilized to form point contacts. As illustrated in FIGS. 42 and 43, a protruding feature 220 may be formed on a substrate 222. As with the embodiments described above, the substrate 222 may contain features or circuitry, such as an access device. In one example, the protruding feature 220 may be a conductive pillar. Advantageously, the conductive pillar has a shape with one or more corners 223, such as a square or rectangular shape. A conformal insulating layer 224 is deposited over the conductive pillar 220, and a facet etch is performed to remove the corners of the insulating layer to expose the corners 226 of the conductive pillar 220, as illustrated in FIGS. 44 and 45. If the conductive pillar 220 has a square or rectangular shape, the exposed corners 226 of the conductive pillar 220 form four point contacts. [0115] It should be appreciated that one, two, or four memory cells may be fabricated using the four contact points. As a first example, each point contact may be utilized in an individual memory cell. In other words, chalcogenide material (as described in conjunction with the previous embodiments) may be formed over each of the four point contacts to create four separate memory cells, each with its own set of bit lines. As a second example, if the four point contacts are sufficiently closed to one another, all four point contacts may be covered with chalcogenide material and used in a single memory cell. As illustrated in FIG. 46, a layer of chalcogenide 228 may be formed over the structure, and a second layer of conductive material 230 may be formed over the chalcogenide layer 228 to complete the memory cell. As a third example, two of the four point contacts may be used in a first memory cell and the other two of the four point contacts may be used in a second memory cell. In this example, it may be particularly useful to use a rectangular pillar 220 so that one pair of point contacts is sufficiently spaced from the other pair of point contacts to facilitate chalcogenide coverage of each respective pair of point contacts, as well as to facilitate the provision of separate sets of bit lines for each pair of point contacts. [0116] Of course, the protruding feature 220 may be a chalcogenide pillar. In this example, the substrate 222 may also include a conductive layer or layers which form the bottom electrode of a chalcogenide memory cell. Accordingly, after the insulating layer 224 has been deposited and the corners removed to expose the corners 226 of the chalcogenide pillar 220. As described above, for a chalcogenide pillar 220 that yields four point contacts, one, two, or four memory cells may be fabricated. Using the second example above in which a single memory cell is fabricated using four point contacts, the layer 228 may be formed using a conductive material or materials to complete the memory cell and the layer 230 of FIG. 46 may be omitted. [0117] While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims. 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H01L45/16, H01L27/2472, Y10S257/91, H01L29/45European ClassificationH01L45/04, H01L27/24Legal EventsDateCodeEventDescriptionMar 15, 2001ASAssignmentOwner name: MICRON TECHNOLOGY, INC., IDAHOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARSHFIELD, STEVEN T.;REEL/FRAME:011631/0829Effective date: 20010302Apr 19, 2005RFReissue application filedEffective date: 20041209Oct 20, 2006FPAYFee paymentYear of fee payment: 4Jan 4, 2010ASAssignmentOwner name: ROUND ROCK RESEARCH, LLC,NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416Effective date: 20091223Owner name: ROUND ROCK RESEARCH, LLC, NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416Effective date: 20091223RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text:
Of Dreams and Sins: Journey Back Home 2 by Rachel Gilberts | NOOK Book (eBook) | Barnes & Noble®
by Rachel GilbertsRachel Gilberts
HE IS DAMAGED...
A DOCTOR WHO CANNOT HEAL HIS OWN WOUNDS
Eric Collins isn’t an innocent about life’s challenges. He has been through several serious relationships. He even married -- thrice. But an important relationship in his past has scarred him long before he can learn to fight, and he doesn’t know how to heal his own wounds.
Eric has had a lonely childhood. His mother made his life like hell. His first marriage to Kathy is almost like his relationship with his mother. But when Kathy dies delivering his second son, he carried the weight of his guilt into the next marriage.
Eileen is a beautiful woman inside and out -- she is in fact much more than what he feels he deserves. This time, he knows he is entering into a marriage of love. In spite of the odds, they are able to make the marriage work.
And it is his undoing, locking Eileen and their unborn child into an unforgiving chain of pain, sadness and distrust. And noone knew when -- or how -- they can all be freed.
I couldn’t stop laughing with the mental picture of a young girl jerking off a rabbit. Did they use a Jack Rabbit?
2940045670883
Rachel Gilberts was born in Nashville, Tennessee - her hometown, then and now. She works as a Humanities professor and as a freelance self-published Christian book author.Her parents are Frank and Jemimah. Frank, now deceased, supported the family by tending their family farm while Jemimah worked as a local bookshop supervisor. Jemimah, now retired, helps supervise work at the farm.Rachel has three other siblings – Ruth, aged 42, and twins John and Jacob, both 36.Ruth, husband Paul, and daughter Martha now tend to the farm. John, still single, is a civil engineer, while Jacob, now married to college sweetheart Marie, is a hotel front desk manager.Rachel has a child named Maryanne, aged 12, by her husband, Keith. Keith was once a one-hit country singer but is now a comptroller at an insurance and financial services company. Rachel and Keith parted ways for “personal differences."Rachel, as alleged by Keith, is content with “small town” life, and he is not. Custody is not an issue as Keith participates actively in raising Maryanne.

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The National Research Foundation is a foundation of the Ministry of Higher Education and Scientific Research in the United Arab Emirates. It has been designed to promote research activity in private and public universities and colleges, at centers of research in institutes and in companies, by individuals and by research teams in the United Arab Emirates.
In the United Arab Emirates (UAE), a National Research Foundation was created in March 2008, by a decree signed by Sheikh Nahyan bin Mubarak Al Nahyan, Minister of Higher Education & Scientific Research. The National Research Foundation is a Ministry of Higher Education & Scientific Research initiative intended to promote and coordinate research activity, to provide research leadership in the country and to provide funding support on a competitive basis to researchers based in the United Arab Emirates. In its early years, research projects that survive international peer review, that contribute social and economic benefits to the UAE and which enhance the development process in that country, have been favored.
This page contains text from Wikipedia, the Free Encyclopedia - https://wn.com/National_Research_Foundation
It was established on 1 April 1999 as an autonomous statutory body in accordance with the National Research Foundation Act. Dr Molapo Qhobela has been appointed the Chief Executive Officer of the National Research Foundation of South Africa with effect from 1 January 2016. The NRF Board is chaired by Professor Belinda Bozzolli.
This page contains text from Wikipedia, the Free Encyclopedia - https://wn.com/National_Research_Foundation_of_South_Africa

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Snow Falling on Cedars: 21 Great Reads for the 21st Century – Paperback
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