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Broxton Sparkles as Jacksonville Wins 10-0 - Los Angeles - Scout
Broxton Sparkles as Jacksonville Wins 10-0Tot Holmes06/07/2005Las Vegas, and Edwin Jackson, was crushed 18-7 despite four hits by Joe Flores. Jacksonville put some distance between themselves and the league with a 10-0 win over Chattanooga behind a strong performance by Jonathan Broxton. Anthony Raglani slugged a grand slam to help Vero Beach split a doubleheader with Daytona and Columbus got a day off because of rain.LAS VEGAS, Nevada--With Dodger pitchers being placed on the disabled list in droves, Edwin Jackson (3-6) seemingly missed his chance again. Monday night with the wind blowing out, he was pounded for eight runs in 5.2 innings as the 51s were smashed 18-7. The game was tied at 6-6 before Fresno scored two runs in the sixth inning, three runs in the eighth and seven in the ninth. "He's a fly-ball pitcher and a high-strike pitcher. I just want to see him make an adjustment to that," 51s manager Jerry Royster said of Jackson. "It's not all right for him to pitch like that, no matter what the wind is doing." Tom Farmer faced six batters in the ninth inning, and all six scored. The 51s recorded 16 hits and were led by shortstop Joe Flores with a 4-for-5, double, two RBI performance. Catcher Dioner Navarro was 3-for-5, two doubles, two RBI and is batting .667 (8-for-12) in the series. First baseman Brian Myrow reached base safely all five times (2-for-2, 2 walks, HBP). Center fielder Henri Stanley was 2-for-5 with two triples and left fielder Jason Grabowski, who went 2-for-4 and is hitting .474, wrapped up his rehabilitation assignment and is returning back to the Los Angeles Dodgers. X-Files --Right-hander Heath Totten returns to the roster and will pitch in relief today. Totten was suspended 15 days and placed on the restricted list May 20 after violating the minor league drug-testing policy. ...The Dodgers called up right-hander Franquelis Osoria, who was 2-1 with a 2.52 ERA and seven saves in 27 games.
CHATTANOOGA, Tennessee-– Todd Donovan tied a career-high with four hits and hit a two-run home run, sparking a five-run seventh inning in the Suns' 10-0 victory Chattanooga. Donovan also stole two bases, increasing his league-leading total to 30. He swiped second on a pitch-out in the fifth when no one covered the base. Donovan advanced to third as the ball dribbled into center and came around to score when the center fielder bobbled the ball. It was all the cushion Suns starter Jonathan Broxton needed. Broxton (3-2) scattered four singles and walked none while striking out nine en route to the victory. He has not allowed a run in 12 innings vs. the Lookouts this season. Six consecutive Suns reached base in the seventh and the Suns sent 10 batters to the plate, padding the lead to 7-0. The Lookouts did not get a runner to first base until the ninth. The Suns collected their sixth shutout and second in three games against the Lookouts. Right-hander Chad Billingsley (5-3, 4.45 ERA) is scheduled to oppose Chattanooga in the final game of a four-game series at Bellsouth Park. Sun Spots: C Russell Martin was named Southern League Player of the Week and went 0-for-1, but reached base four times. …Donovan is 33-for-81 (.407) over his last 17 games. …The Suns are batting .345 and are 10-2 in their last 12 games. …With the win, the Suns boost their South Division lead to one full game over Birmingham, Mississippi and Montgomery. …The Suns have won all six games vs. Chattanooga this season and are undefeated in June (6-0). --Joe Block
VERO BEACH, Florida--After four days off because of rainouts, the Dodgers split a double header with Daytona, taking the first game 12-5 and losing the second 6-2. The first game was a completion of Sunday's, which was postponed after the third inning by rain. The Dodgers came from behind, thanks to solid pitching out of the bullpen and some timely hits. Danny Muegge earned the win with the first three relief innings. He allowed just one run. Hong-Chih Kuo and Orlando Rodriguez combined to shut out the Cubs over the final three frames. Edwin Bellorin led off the fourth with a double and came home on a single by Chin-lung Hu. The Dodgers took the lead in the fifth. Xavier Paul walked with the bases loaded to force across one run and Tony Abreu singled in two more to put the Dodgers on top 6-5. Vero put the game away in the 8th. Hu bunted for a hit, then Andy LaRoche and Kemp lined back-to-back singles to load the bases. Ruggiano walked to make it 7-5 and Anthony Raglani boomed a grand slam. Bellorin followed with a solo blast to center, completing the 12-5 victory.
In Game Two, the offense was swallowed up by four double plays in only seven innings. The only two runs came in the bottom of the seventh when Raglani pushed a home run down the right field line to knock in Kemp, who had tripled to start the inning. Daytona used a 3-run second inning of Justin Orenduff to cruise to victory. Orenduff (4-3) surrendered four runs in five innings after allowing only a total of four runs in his previous 28 innings pitched. He fell to 4-3. COLUMBUS, Georgia-- The final game of a four-game series versus Asheville was been postponed due to unplayable field conditions. The Catfish begin a four-game road series against the Greensboro Grasshoppers (Florida Marlins) tonight. Share on Facebook Share on TwitterTrending on ScoutLovie: 'We haven't progressed enough'Fafaul On Getting Back On TrackAF Reaper Gets Universal Weapons InterfaceLuke Kuechly's Jersey Retirement CeremonyLi'l Louisville fan sobs after Kentucky cheerLA Dodgers Insider Top StoriesBreaking NewsKershaw VS. Hendricks NLCS Game 6Kershaw VS. Hendricks NLCS Game 6by Jason RutherfordLA Dodgers InsiderSaturday at 1:01 PMHILL- NLCS Game 3 SummaryHILL- NLCS Game 3 Summaryby Jason RutherfordLA Dodgers InsiderWednesday at 12:17 PMUrias VS. Lackey NLCS Game 4Urias VS. Lackey NLCS Game 4by Jason RutherfordLA Dodgers InsiderWednesday at 12:05 PMKERSHAW- NLCS Game 2 SummaryKERSHAW- NLCS Game 2 Summaryby Jason RutherfordLA Dodgers Insider10/17/2016Kershaw VS. Hendricks NLCS Game 2Kershaw VS. Hendricks NLCS Game 2by Jason RutherfordLA Dodgers Insider10/16/2016Maeda vs. Lester NLCS Game 1Maeda vs. Lester NLCS Game 1by Jason RutherfordLA Dodgers Insider10/14/2016SEAGER: Baseball's Top RookieSEAGER: Baseballs Top Rookieby Jason RutherfordLA Dodgers Insider10/09/2016Andrew Toles Leading DodgersAndrew Toles Leading Dodgersby Jason RutherfordLA Dodgers Insider09/20/2016Do Dodgers hitters make contact in the ZONE?Do Dodgers hitters make contact in the ZONE?by Jason RutherfordLA Dodgers Insider09/15/2016Dodgers 2016 Arizona Fall League RosterDodgers 2016 Arizona Fall League Rosterby Jason RutherfordLA Dodgers Insider09/08/2016Hill VS. Arrieta NLCS Game 3Hill VS. Arrieta NLCS Game 3by Jason RutherfordLA Dodgers Insider10/17/2016Notre Dame Post-Game: Coach ShawCoach David Shaw talks about Stanford's thrilling 17-10 win over Notre Dame.by R.J. AbeytiaLA Dodgers Insider10/15/2016Load More

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President Obama on Wednesday nominated Dr. Francis S. Collins, a pioneering geneticist who led the government’s successful effort to sequence the human genome, as head of the National Institutes of Health.Dr. Collins’s selection, which had been rumored for weeks, was praised by top scientists and research advocacy organizations for whom the health institute is a crucial patron.Based in Bethesda, Md., the N.I.H. is the most important source of research money in the world; over the next 14 months it will dole out about $37 billion in research grants and spend $4 billion on research programs at its Maryland campus.“Francis Collins is an extraordinary scientist and one of the nicest guys you could ever meet,” said Dr. Otis W. Brawley, chief medical officer of the American Cancer Society. Continue reading the main story
Douglas C. Pizac/Associated Press Some scientists and advocates for people suffering from diseases criticized the extraordinary amount of money and attention the sequencing effort garnered, saying it distracted from more fruitful areas of research.
He was part of a team at the University of Michigan that in 1989 discovered the gene for cystic fibrosis. At the time, many predicted that the discovery would lead to a quick cure. But like so much in genetic research, that hope is still a long way off.As the leader of the Human Genome Project, Dr. Collins engaged in a fierce public battle with Dr. J. Craig Venter of Celera to finish the sequence first and make it broadly available. The success of Dr. Collins’s project torpedoed much of Celera’s business model. But in a speech last month, Dr. Collins said the N.I.H. needed to form more partnerships with the pharmaceutical industry to create new drugs.

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regex - Regular Expression FS00000 - Stack Overflow
Regular Expression FS00000
What is the regular expression to match FS00000 were the 0s can be a number from 0-9. There can only be 5 numbers following the FS.
regex share|improve this question asked Jun 23 '09 at 15:17
What language? Everyone is being forced to give generic answers, which may or may not be helpful to you.
@phone: ...There can only be 5 numbers .... Exactly 5 "{5}" or up to five? {1,5}, or none to 5? {0,5} or... or... :)
^FS\d{5}$
which matches the line start (^ - you may not need this), then FS, then a digit \d 5 times {5}, then the line end $ (again, you may not need this, but you'd then have to protect against a sixth digit following).
You don't specify which language/regexp, but the above is pretty generic.
EDIT: You can provide word boundary markers instead of line start/end markers, which is a little more generic. \b will mark a word boundary (in Perl - see Perlre - but equivalents exist in other languages)
share|improve this answer edited Jun 23 '09 at 15:51
Cheers I forgot the $ :(
How about adding word boundaries instead of the start-of-line and end-of-line markers?
Yes - I think would be useful. I'll modify to suggest this
... or you could upvote my answer ;-)
A shameless attempt at votemongering! But that would make sense. Done
FS\d{5}
\d means any digit, and {5} means exactly 5 of them.
shouldn't you add something like \D to prevent a sixth digit?
\d will match any Unicode Decimal Digit (fileformat.info/info/unicode/category/Nd/list.htm) if used in .NET
This is the most basic form, and yes, it could be improved. Like for instance, I could have surrounded it with ^$ -- but the question was so vague that I didn't want to add possibly extraneous elements.
you are right - the question can be interpreted as "six digits are not possible"
If the exact word should be matched don't forget word boundaries:
\bFS\d{5}\b
Depending on the language chosen the syntax for a word boundary might differ.
answered Jun 23 '09 at 15:32
Word boundaries look to be a good move here
FS[0-9]{5}
share|improve this answer answered Jun 23 '09 at 15:19
Only 5 numbers means 0-5 numbers?
FS[0-9]\{1,5\}
share|improve this answer answered Jun 23 '09 at 15:21
Note, that if FS00000 is part of other text and doesn't occupy the entire line, you should surround the FS\d{5} pattern by word boundaries rather than line boundaries:
^FS[0-9]{5}$
This matches any string that begins (^) with FS followed by 5 times 0-9 and then ends ($).
Don't use \d in this case since it will also match Unicode Decimal Digits (at least in .NET).

value: This website is a question and answer website for professional and enthusiast programmers. It is the flagship site of the Stack Exchange Network, created in 2008 by Jeff Atwood and Joel Spolsky.


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Protein (RefSeq) Links for PubMed (Select 8978606) - Protein - NCBI
Select item 10397706981.PREDICTED: nitric oxide synthase, brain isoform X4 [Mus musculus]1429 aa proteinAccession: XP_017176196.1 GI: 1039770698 GenPeptIdentical ProteinsFASTAGraphicsSelect item 5689369182.PREDICTED: nitric oxide synthase, brain isoform X3 [Mus musculus]1430 aa proteinAccession: XP_006530255.1 GI: 568936918 GenPeptIdentical ProteinsFASTAGraphicsSelect item 5689369163.PREDICTED: nitric oxide synthase, brain isoform X2 [Mus musculus]1463 aa proteinAccession: XP_006530254.1 GI: 568936916 GenPeptIdentical ProteinsFASTAGraphicsSelect item 5689369144.PREDICTED: nitric oxide synthase, brain isoform X1 [Mus musculus]1464 aa proteinAccession: XP_006530253.1 GI: 568936914 GenPeptIdentical ProteinsFASTAGraphicsSelect item 5689369125.PREDICTED: nitric oxide synthase, brain isoform X1 [Mus musculus]1464 aa proteinAccession: XP_006530252.1 GI: 568936912 GenPeptIdentical ProteinsFASTAGraphicsSelect item 5689369106.PREDICTED: nitric oxide synthase, brain isoform X1 [Mus musculus]1464 aa proteinAccession: XP_006530251.1 GI: 568936910 GenPeptIdentical ProteinsFASTAGraphicsSelect item 5689369087.PREDICTED: nitric oxide synthase, brain isoform X1 [Mus musculus]1464 aa proteinAccession: XP_006530250.1 GI: 568936908 GenPeptIdentical ProteinsFASTAGraphicsSelect item 5689330398.PREDICTED: nitric oxide synthase, endothelial isoform X1 [Mus musculus]1150 aa proteinAccession: XP_006535702.1 GI: 568933039 GenPeptIdentical ProteinsFASTAGraphicsSelect item 1610869889.nitric oxide synthase, endothelial [Mus musculus]1202 aa proteinAccession: NP_032739.3 GI: 161086988 GenPeptIdentical ProteinsFASTAGraphicsSelect item 672432110.nitric oxide synthase, brain [Mus musculus]1429 aa proteinAccession: NP_032738.1 GI: 6724321 GenPeptIdentical ProteinsFASTAGraphics
Turn Off Turn On Protein (RefSeq) Links for PubMed (Select 8978606) (10)

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PRESIDENT-ELECT BARACK OBAMA: There is no doubt that the cost of this plan will be considerable. It will certainly add to the budget deficit in the short term.
SENATE MINORITY LEADER MITCH MCCONNELL R-KY: Well, given the deficit numbers, it really out not to be a trillion dollar spending bill. I think we can start by saying that.
BRET BAIER, HOST: The Senate minority leader reacting to President-elect Obama's speech today on the economy, a speech that was short on details but big on urgency for Congress to act fast on this massive program, whatever the figure is. You heard the Senate minority leader saying it shouldn't be the "T" word — "trillion."
JEFF BIRNBAUM, COLUMNIST, THE WASHINGTON TIMES: I have to say, we've heard President-elect Obama talk about dire predictions of the economy. We have heard him speak about it several times.
But not a major address like this. It really was a stark wakeup call. He used the word "crisis." He warned that unless a major stimulus package isn't passed and a very large one, that the consequence could be recession for years to come and double digit inflation and all sorts of terrible things.
There's no question, though, that this kind of speech has galvanized congress, and Republicans and Democrats both agree now that there needs to be a very large economic recovery plan.
BIRNBAUM: Or more, but probably about $4 trillion worth of people who are interested in it, and that will mean that this will take longer and be a bigger fight than we're now expecting.
MARA LIASSON, NATIONAL POLITICAL CORRESPONDENT, NATIONAL PUBLIC RADIO: I think the reason why the Republicans are warning that this shouldn't get to a trillion is because a trillion is a kind of psychological threshold. It's little scary to spend a trillion dollars.
LIASSON: I know — $800 billion is pretty close. And originally I think the Obama team didn't want to propose something over a trillion. That is why they kept on saying 775.
And the big question is, when you have something this big, it is almost guaranteed there will be all sorts of stuff in it that doesn't meet the standards, the very high-minded standards that Obama has laid down. It really has to work. It has to actually stimulate the economy. It can't just be pork.
The other thing, the heart of this economic crisis, is a credit crisis. And all of that money that has already been shoveled into the banks to improve their balance sheets has not made that go away. Banks still aren't lending. And that's the other part of this that Obama has to address.
CHARLES KRAUTHAMMER, SYNDICATED COLUMNIST: What's so interesting is how the father of the idea of the trillion dollar anything is Hank Paulson. He's the guy who out of the blue came up with $700 billion a year ago, which he got off the back of an envelope, that was five percent of GDP. And now anything less seems like lunch money.
What's really interesting about this speech that Obama gave today is that we are now living in an unprecedented time when we actually have two active presidents. Foreign affairs is entirely the Bush administration acting with a lot of authority on Gaza and other issues, and Obama staying entirely out, as he should, and he knows he has to until Inauguration Day.
On the economy, the Bush administration is entirely irrelevant, and we have a president Obama. He is our domestic president. The markets, the local governments, state governments, foreign governments are all looking to him and to the hints in his speech as to what's going to happen on the economy.
BAIER: Jeff, today, Senate Minority Leader McConnell pointed back to Nancy Pelosi's words saying back when they were originally talking about a stimulus package that it had to be "timely, targeted, and temporary."
BAIER: They're saying will this one be all three things?
BIRNBAUM: I think this is the week of big reversals, with Roland Burris first, and now on this. This will be a little later than expected. About half of it will not be temporary in any way. A lot of it will be for education, for roads that will be there for decades. And whether it will be targeted or not, it probably won't be by design, because no earmarks are involved. So I think a lot of these things will be reversed. I think the components here will be put together based on politics. That is, there will be a lot of trading. There will be geographic questions. There will be partisan questions.
An update on another story we have been talking about a lot on this show, and that is the Illinois House Committee has voted unanimously to recommend impeachment for Illinois governor Rod Blagojevich. We updated that from Steve Brown's reporting earlier as that vote was going on. Now, this moves forward. We'll continue on that story as well.
BAIER: Today as the offensive in Gaza continues rockets came into Israel from the north, from Lebanon. You heard Israeli President Shimon Peres saying they will always fire back. They did fire artillery back. And the Lebanese saying this is not — they don't want to be dragged into another war with Israel.
But is it a new front in this dynamic going on in Gaza? We're back with the panel. Charles, what's the latest here?
KRAUTHAMMER: Well, potentially it is, but it doesn't look as if any of the parties are interested in making it a new front. This was undoubtedly a radical Palestinian offshoot that did this. Israel responded relatively restrained manner. Hezbollah did not respond.
It looks as if the radical Palestinians were interested in dragging in Hezbollah and starting a second front. It's not going to happen.
That's why there is a danger with what is happening now at the U.N. There is a huge effort to have Israel accept an arrangement in Gaza as it has in Lebanon. But what has happened in Lebanon is a huge rearmament of Hezbollah. There is no policing of what's happening.
If you get it in Gaza, you will get rearmament of Hamas. You will get a restoration of its weapons. And you're going to have a round in a year or two that's going to be even worse.
Israel has a chance now to break Hamas and to actually get it out of the power in Gaza if it continues in its offensive. I hope the United States doesn't join with the European Union in stopping this offense. You could have a decisive change of government in Gaza if Israel is allowed to continue, but I'm not sure it's going to be allowed to.
LIASSON: Yes. And pretty soon it's going to be up to the Obama administration to decide what to do.
But pretty soon it will be up to him, and I think Israel's goal is not just to break Hamas but, better yet, to discredit it, to show that it was too weak to even protect its own people. I don't know if that can be accomplished, but I agree, so far it is striking that it hasn't gotten overt help from Iran or Hezbollah.
BIRNBAUM: That's so, but I think Israel is somewhat in danger of overplaying its hand here in trying to root out a lot of caches of weapons. It has to go into hospitals and to schools.
And I think world opinion could easily turn against Israel if it turns up too much heat on this subject. And that's the big danger that Israel faces.

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Breakfast was interesting with local foods, Bed... - Review of Shengjia Business Hotel Jilin Dadongmen - TripAdvisor
Breakfast was interesting with local foods, Bed... - Review of Shengjia Business Hotel Jilin Dadongmen
Search Asia›China›Jilin›Jilin›Jilin Hotels›Shengjia Business Hotel Jilin Dadongmen
“How it ever received the rating it did is a curious thing”
Review of Shengjia Business Hotel Jilin Dadongmen
Shengjia Business Hotel Jilin Dadongmen No.14 Henan Street, Chuanying District, Jilin 132011, China | Name/address in local language “How it ever received the rating it did is a curious thing”
No.14 Henan Street, Chuanying District, Jilin 132011, China 7 Reviews | Ranked #57 of 158 To help you get around Jilin, here's the name and address of this business in the local language
Directions Print Ranked #57 of 158 Hotels in Jilin
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6 helpful votes “How it ever received the rating it did is a curious thing”
Breakfast was interesting with local foods, Bed was very hard, clean linens but the room was very poorly maintained with dirt in every corner and behind the doors. Carpet was matted with spit and food stain, cigarette burns etc. Bathroom smelled bad from leaking sewer gas, floor has crusts of mold and dirt in every corner, toilet stained and leaking, faucet leaked, mold around bathtub.
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Patent US3989894 - Synchronism error detecting and correcting system for a circulating memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA system is disclosed for checking and correcting the synchronism of bits stored in a circulating memory which is part of a PCM switching system. Periodically, bits previously written in an addressable memory are read-out and compared to corresponding bits supplied by the circulating memory. In accordance...http://www.google.com/patents/US3989894?utm_source=gb-gplus-sharePatent US3989894 - Synchronism error detecting and correcting system for a circulating memoryAdvanced Patent SearchPublication numberUS3989894 APublication typeGrantApplication numberUS 05/424,298Publication dateNov 2, 1976Filing dateDec 13, 1973Priority dateDec 21, 1972Also published asDE2363002A1, DE2363002B2, DE2363002C3Publication number05424298, 424298, US 3989894 A, US 3989894A, US-A-3989894, US3989894 A, US3989894AInventorsPierre Charransol, Jacques Salle, Jacques BeckerOriginal AssigneeInternational Standard Electric CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (10), Classifications (12) External Links: USPTO, USPTO Assignment, EspacenetSynchronism error detecting and correcting system for a circulating memoryUS 3989894 AAbstract A system is disclosed for checking and correcting the synchronism of bits stored in a circulating memory which is part of a PCM switching system. Periodically, bits previously written in an addressable memory are read-out and compared to corresponding bits supplied by the circulating memory. In accordance with results of the comparison, a synchronism signal or a fast or slow correction signal is supplied.
We claim: 1. A synchronization correction system for a recirculating memory controlled by an address counter, comprising means for feeding a series of address control bits derived from said counter to said memory, an auxiliary memory, enabling means connected to receive said bits and responsive to said bits for feeding one of said bits for storage in said auxiliary memory at a time having predetermined timed relationship to the feeding of bits to said recirculating memory, means for reading out said one bit from said auxiliary memory at a predetermined time interval thereafter, comparison means for comparing the bit read out of said auxiliary memory with bits fed from said enabling means, correction control means responsive to the comparison of said bits for emitting a first signal when the compared bits are identical and emitting second signals when the compared bits are not identical, and means responsive to said second signals for correcting the timing of feeding of bits to said recirculating memory.
2. A system as claimed in claim 1, wherein said enabling means comprises a plurality of bistable circuits each enabled responsive to successive bits fed to said recirculating memory, and one of said bistable circuits being responsive to said one bit, and others of said bistable circuits responsive to other successive bits of said series.
3. A system as claimed in claim 2 in which said comparison means comprises a plurality of gates, each gate having as one input thereto an output from one of said enabling means and each said gate having as another input thereto a path for the read out of bits from said auxiliary memory.
The present invention concerns a synchronism error detection and correction system for a circulating memory. It may be used, in particular, in a telephone exchange employing time division switching for pulse code modulation signals.
At the inputs of such an exchange, the signals from the lines are sampled at 8 kHz and each sample is converted into a 8-bit coded combination. Each 8-bit combination is transmitted in parallel on eight conductors in a very short time interval constituting a time channel. It is thus possible to time multiplex 256 channels, for example. The recurring period of the successive time slots of a same channel is 125 μs, whereas the duration of each time slot is approximately 500 ns. An incoming multiplex group thus routes the signals from 256 lines. A similar outgoing multiplex group thus routes the signals towards the same 256 lines. The above-mentioned numerical values, without being necessary, are nevertheless currently admitted.
Inside the exchange, it is necessary that a coded signal combination appearing in a channel time slot of a multiplex group be retransmitted in any channel time slot of any multiplex group. This entails space switching operations (connections from group to group) and time switching operations (connections from channel to channel). They will be carried out by means of a network including space switches and stores. This network may be, for example, of the well-known space-time-space type. A connection path between an incoming channel of a first line and an outgoing channel of a second line uses two space switches, arranged, in a way, on each side of a memory cell; they give it access respectively to the incoming multiplex groups and to the outgoing multiplex groups. In this way, at the time slot assigned to the incoming channel and through the first switch oriented onto the appropriate incoming group, a coded combination originated from the incoming channel is stored in the memory cell. At the time assigned to the outgoing channel and through the second switch oriented onto the appropriate outgoing group, the coded combination originated from the incoming channel and stored in the memory cell is retransmitted on the outgoing channel. The connection in the opposite direction between the outgoing channel of the first line and the incoming channel of the second line, is carried out in the same way and uses generally the same memory cell.
In practice, the necessary numerous memory cells are memory cells belonging to several speech stores and two space switches are associated with each store, an incoming group switch and an outgoing group switch. In a speech store, at each time slot, a memory cell is addressed in order to be the object first of a read operation and then of a write operation, according to the just described switching system. At the same time, the incoming group switch and the outgoing group switch must receive a group address in order to take the appropriate orientation.
Thus, there has been provided a path store associated with each speech store and its relevant switches, which will supply, at each time slot, the necessary addresses, that is an address for the speech store and an address for the switches. This path store has 256 cells, one per time slot, which are cyclically read-out in synchronism with the multiplex group time slots.
As in the total cost of such an exchange, the stores are a substantial part of it, the most economical stores are being used, as far as it is possible. At present, the most economical stores are the circulating memories of the MOS type. The basic element of these memories is a shift register which may have 256 stages and thus memorize 256 bits, one per time slot in the concerned application. By juxtaposing n of these registers, a circulating memory is obtained which can memorize 256 words of n bits and be used as a path store. Normally, the output of this circulating memory is connected to its input and the 256 words it contains cyclically circulate in response to pulses corresponding to each time slot; these words are one by one available, at each time slot, when they transit between the output and the input of the path store, in order to supply the addresses to the speech store and to its switches. It is also at that time that a path may be replaced by another one by inhibiting the output of the circulating memory and by replacing the path word it supplies by another path word supplied by the switching center control units.
In order to identify the path words stored in such a circulating memory, a 256-position counter is associated with it. This counter steps once at each clock pulse while the words contained in the circulating memory are shifted by one step. It supplies a binary combination identifying, at once, each time slot and the path word supplied at that time by the circulating memory. This counter may be easily readjusted at each multiplex cycle; the clock delivers not only a stepping pulse at each time slot but also a readjustment pulse with the 256th stepping pulse. This readjustment resets the counter whatever its position.
The practical drawback of such circulating memories relates to the fact that there may occur a lack of synchronism between the circulating memory and its counter. Indeed, a spurious pulse may, for example, cause an untimely shift in the registers of the circulating memory. The address information supplied by the latter will then result erroneously as they will not be supplied at the appropriate times and nothing will enable the detection of the anomaly and therefore its correction. The associated counter may be concerned or not by this spurious pulse. Anyway, the counter will be readjusted at the end of the multiplex cycle and will be anew in synchronism whereas the memory will remain shifted.
In the above-described switching center, such a synchronism failure in a path store will affect all the calls transmitted via this store. This cannot be accepted.
SUMMARY OF THE INVENTION The object of the present invention is thus a synchronism error detection and correction system for a circulating memory, designed in order not only to detect such error but also to correct it. It is obvious that the system, according to the invention, may be used in a general way, in all utilizations of circulating memories.
The present invention is mainly characterized in that the synchronism error detection and correction system of a circulating memory having an address counter includes, in particular, an auxiliary addressable memory, write control means making it possible to record in the addressable memory, at addresses deduced from the address counter position, check bits derived from certain bits selected among those stored in the circulating memory and called checked bits, read control means making it possible to read-out of the addressable memory, at addresses deduced from the address counter position, the check bits recorded therein, as well as a first comparison circuit receiving and comparing, on the one hand, the checked bits supplied by the circulating memory and, on the other hand, the corresponding check bits read-out from the addressable memory, in order to supply a synchronism signal having one value in the case when these bits are respectively identical, and another value in case of lack of synchronism.
According to another feature of the invention, the system includes moreover a second comparison circuit receiving and comparing on the one hand, the bit which follows in the circulating memory each checked bit and, on the other hand, each corresponding check bit, in order to supply a slow operation presumption signal in case of identity, as well as a third comparison circuit receiving and comparing, on the one hand, the bit which procedes in the circulating memory each controlled bit and, on the other hand, each corresponding check bit in order to supply a fast operation presumption signal in case of identity.
According to another feature of the invention, the system includes moreover logic circuits receiving the output signals of the first, second and third comparison circuit and supplying a slow operation correction control, when a slow operation presumption signal is transmitted whereas the synchronism signal indicates a lack of synchronism while the fast operation presumption signal is absent, and a fast operation correction control when a fast operation presumption signal is transmitted whereas the synchronism signal indicates a lack of synchronism while the slow operation presumption signal is absent.
According to another feature of the invention, the system includes means, constituted in particular by a bistable circuit controlled by said fast operation correction control in order to inhibit the transmission of a shift pulse towards the circulating memory.
According to another feature of the invention, the system includes means, constituted in particular by a monostable circuit controlled by the slow operation correction control and by a delay circuit receiving the output signal of the monostable and retransmitting it after a given time interval, in order to supply in response to a slow operation correction control an additional shift pulse towards the circulating memory.
According to another feature of the invention, the system includes means constituted, on the one hand, by logic gates transmitting at the input of the circulating memory either the output bits of this memory, or bits freshly supplied and, on the other hand, logic gates provided for transmitting to the addressable memory check bits derived from certain selected bits only if the latter are freshly supplied bits with the view to recording them in this addressable memory.
BRIEF DESCRIPTION OF THE DRAWINGS Various other features will be disclosed from the following description given by way of non-limited example referring to FIGS. 1 to 8 which represent:
FIG. 1, the block schematic of a well-known time division switching system wherein may be applied the present invention;
FIG. 2, the block schematic of an embodiment of the control circuits of the switching network in FIG. 1;
FIG. 3, an embodiment of the store MT equipped with the detection and correction system according to the present invention;
FIG. 4, an embodiment of circuit HGT of FIG. 3;
FIG. 5, waveshapes illustrating the signals supplied by the circuits of FIGS. 3 and 4;
FIG. 6, an embodiment of the correction circuit DC of FIG. 3;
FIGS. 7 and 8, waveshapes illustrating an example of signals exchanged between the different elements of the correction circuit DC of FIG. 6.
DESCRIPTION OF PREFERRED EMBODIMENTS First will be described referring to FIG. 1, the block schematic of the circuits of a switching network wherein may be applied the present invention.
This network includes incoming multiplex groups such as GE1 to GEn. To each of them corresponds an outgoing multiplex group GS1 to GSn. Each multiplex group includes, for example, 256 time channels. A channel time slot corresponds to each time channel, of about 500 ns. The recurring period of a same channel time slot is 125 μs. Moreover, it is considered that the mutiplex groups are synchronous, that is that the individual channel time slots occur simultaneously in all the groups.
For the call establishment, several switching units identical to that illustrated in FIG. 1 are provided.
This unit includes a path store MT, a speech store MP, an incoming group switch CE and an outgoing group switch CS.
The path store MT is a circulating memory having 256 cells read-out in synchronism with the multiplex group channel time slots. Each cell such as cta and ctb may include an address of one cell of the speech store and a multiplex group number.
The speech store MP may have up to 128 memory cells which will be each assigned to one call. These memory cells are addressed according to the information supplied by the path store MT.
The switch CE associates the input of the store MP to any incoming group, in response to the information supplied by one cell of the path store.
The switch CS associates the output of the store MP to any outgoing group.
The operation of this network will be described considering the case of a call between a subscriber (A) to which corresponds the channel time slot ta on the incoming and outgoing groups GE1 and GS1 and another subscriber (B) to which corresponds the channel time slot tb on the incoming and outgoing groups GEn and GSn. In the path store MT, the memory cell cta corresponds to the channel* time slot ta and the memory cell ctb to the channel time slot tb.
At the channel time slot ta, the memory cell cta of the path store MT is read-out; it supplies on conductors AD the group number G1 and the address adO as illustrated in cta of FIG. 1. The group number G1 is sent to switches CE and CS, in parallel. In response, the latter orientate respectively onto groups GE1 and GS1. Simultaneously, the address adO is transmitted to the speech store MP. In the latter, the memory cell corresponding to this address is successively the object of a read and write operation.
The information read-out at the address adO is transmitted to the multiplex group GS1, via switch CS. Then, the information present on the multiplex group GE1, transmitted via switch CE to the input of the speech store MP, is stored in lieu of that just read-out, at the address adO. Subscriber (A) has thus received a coded sample, whereas the one he supplied has just been recorded.
At the channel time slot tb, the memory cell ctb of the path store MT is read-out ; it supplies the group number Gn and, anew, the address adO as illustrated in ctb of FIG. 1. The group number Gn is transmitted to switches CE and CS in parallel. In response, the latter orientate respectively onto groups GEn and GSn. Simultaneously the address adO is transmitted to the speech store MP.
The information read-out at the address adO is transmitted on the outgoing multiplex group GSn, via switch CS. Then, the information present on the incoming multiplex group GEn, transmitted via switch CE to the input of the speech store MP, is stored in lieu of that just read-out, at the address adO. Subscriber (B) has thus received the coded sample previously received from subscriber (A) and recorded at time ta, whereas the one he supplied has just been recorded at the address adO and is kept until the next time slot ta when it is transmitted to subscriber (A).
It can thus be seen that the considered call between two subscribers to which correspond different channel time slots and multiplex groups, necessitates the two path store cells cta and ctb corresponding to these channel time slots in the path store MT, any memory cell (adO) of the speech store MP and the use of switches CS and CE, at the appropriate time slots (ta and tb), in order to reach any multiplex group.
Other calls, concerning other channel time slots, are established in the same way by the switching system of FIG. 1 and, in a general way, at each channel time slot, a cell of the path store MT must supply addresses associated with a call concerning this channel time slot. Since the different cells of store MT must be cyclically read-out, it may be desirable to design said store as a circulating memory. However, this presents a risk; indeed, it can be easily seen that if, for any reason, a shift occurs in the operation of store MT, the information stored in the memory cell cta, e.g. will be supplied either before or after the time ta, which will result in an undesirable connection instead of that required. It will be the same for all calls established by the system of FIG. 1; this cannot be admitted.
The object of the present invention is thus a system enabling the detection and correction of such a shift, which results in a store MT constituted by economical circulating memories available on the market.
Now will be described, referring to FIG. 2, an embodiment of the control means of the path store MT, in the case when this memory is a circulating memory.
FIG. 2 shows besides store MT, a clock HGC and a control logic circuit LC.
The clock HGC may be the switching network central clock; it supplies on the output conductors CP and CPZ clock pulses which will also be referenced CP and CPZ.
A pulse CP is delivered per channel time slot. Every 256 pulses CP, a pulse CPZ is also supplied in order to mark the end --or the beginning -- of each 256-channel multiplex cycle.
The control logic circuit LC includes an address counter CV, a comparating circuit CR and a register RG.
The address counter CV is a 256-position cyclic counter. It is controlled by the clock pulses CP. A pulse CPZ is added to the 256th pulse CP, which resets counter CV. In this way, if counter CV, due to spurious pulses, for example, has shifted by one or several steps with respect to the central clock HGC, the reset pulse CPV re-establishes the synchronism of counter CV with the clock HGC. Finally, the contents of counter CV, that is the identity of the channel time slot, is transmitted to the path store MT via conductors ADE.
The function of register RG is to receive from the non-represented central control circuits, which are beyond the scope of the invention, information concerning a path to be written into one cell of the path store MT, each time a call must be established or released. This information includes two parts, a part ADR which is the identity of the concerned channel time slot, in the path store, and a part TR which must be written in the appropriate memory cell of store MT, the description of which has been given with FIG. 1.
The comparating circuit CR receives, on the one hand, the information ADE and on the other hand, the information ADR. It compares them and, if they are equal, it supplies a recording signal on conductor EN.
The bits of the path indication TR displayed on conductor PR are then recorded in store MT and, more precisely, in the memory cell which is read-out during the channel time slot in which the identities of ADE and ADR are identical.
Store MT is a 256-stage circulating memory. The path words, such as TR, circulate step by step across these 256 stages due to pulses CP which are directly transmitted to store MT. They are available on the output AD, each one during a channel time slot the identity of which is then displayed on ADE by counter CV. It is at that time that a new path may be written into store MT, by replacing the information read-out by the information TR supplied by register RG, under control of signal EN.
As previously mentioned, it can be feared that, in such an arrangement, a spurious signal causes an untimely shift by one step of store MT. Indeed, store MT has no readjustment means as counter CV (pulse CPZ). After this untimely shift, store MT will supply erroneous information on its output AD, without the error being detected.
The invention thus provides stores MT with a detection and correction system of synchronism error. For the system requirements, the output ADE of counter CV is connected to store MT. The diagram of FIG. 3 represents in detail the detection and correction system, according to the invention.
Conventionally, the "AND" gates have been represented by a dot surrounded by a circle (symbol of logic intersection), the "OR" gates by a cross surrounded by a circle (symbol of logic union), the "EXCLUSIVE OR" gates by two concentric circles containing a cross and the logic inverters by a triangle followed by a small circle. The bistables have been represented by two juxtaposed rectangles respectively containing digits 1 and 0. The monostables by the same two juxtaposed rectangles but diagonally barred; generally the bistable and monostable inputs and outputs are respectively placed at the upper and lower part of the rectangles.
In order to simplify the figure, each information transmitted will have the same reference as the conductor which forwards it.
The path store MT of FIG. 3 includes in particular a circulating memory MC and the control circuits CMC of this memory, an auxiliary memory circuit MA, a recording and transmission circuit RS, a comparison circuit CG and control circuits CC.
The circulating memory MC includes 8 inputs IMO to IM7, 8 outputs OMO to OM7 and 8 circulating memory modules MMCO to MMC7 which are 256-stage shift registers. Each of them shifts by one step the 256 bits it contains at each pulse CPS. Generally, the shift pulse CPS corresponds to the pulse CP supplied by the clock HGC (FIG. 2). Therefore, a bit is supplied at the output of the module, while the bit present on its input enters its first stage by shift. In order to simplify the figure, only the first and last inputs, the first and last outputs and the first and last memory modules have been represented. Although 8 memory modules have been represented, it is to be noted that this number may vary according to the requirements. It could be duplicated, for example, in the previously mentioned application.
The first memory module MMCO receives the first bit bO of a coded sample to be recorded which is supplied on conductors PR via the control circuits CMC. These circuits include in particular, for this modules MMCO, a conductor EDO, an AND gate bgO and an OR gate dgO. The AND gate bgO is enabled by a recording signal supplied on conductor EN. In the absence of this signal, the module MMCO receives, on its input IMO, the data bit present on its output OMO, via an AND gate ago, which is rendered conducting by the output signal of an inverting circuit aiO, that is the reverse of signal EN, and via the OR gate dgO.
Similar means are associated with the module MMC7 and with the non-represented modules. Thus, the bit b7 of the coded sample PR is supplied at the input of the module MMC7 via a conductor ED7, an AND gate bg7 and an OR gate dg7. The AND gate bg7 is controlled by the recording signal EN. In the absence of this signal, the module MMC7 receives, on its input IM7, the data bit present on its output OM7, via an AND gate ag7 enabled by the output signal of an inverting circuit ai7, that is the reverse of signal EN, and via the OR gate dg7.
Thus, practically, if the signal EN is present, the information supplied by the logic circuits LC enter memory MC, for the writing of a new path as above-described. If the signal EN is absent, which will be most frequently the case, the input of the memory is coupled to its output and the information stored in the memory are kept while cyclically appearing on the outputs OMO to OM7 of the modules. These outputs are connected to the link AD with the view to using the information in the previously described way.
The control circuits CC include in particular the clock circuit HGT and a correction circuit DC.
The clock circuit HGT receives from the logic circuits LC the pulses CP as well as the identity ADE of each channel time slot. It supplies in response pulses CPa -1, CPa, CPa +1, CPa +2, CPr as well as an address ADC.
An embodiment of the clock circuit HGT is shown in FIG. 4. This circuit includes four AND gates ps1 to ps4 receiving in particular the clock pulses CP. It has been previously seen that the central clock HGT also supplies pulses CP to counter CV. The latter is here illustrated by 8 bistables FFO to FF7. The outputs Ra2 to Ra7 and Ra2 to Ra7 of the six bistables FF2 to FF7 supply information to the clock HGT which redistributes it in the form of the information ADC. The outputs RaO, RaO, Ra1 and Ra1 of bistables FFO and FF1 supply control signals to gate ps1 to ps4. Accordingly, the gate ps1 is controlled by the signals supplied on the outputs RaO and Ra1. It supplies the signal CPa -1. The gate ps2 is controlled by the signals supplied on the outputs RaO and Ra1 and transmits signal CPa. The gate ps3, controlled by the signals supplied on the outputs RaO and Ra1, transmits the signal CPa +1, and the gate ps4, controlled by the signals supplied on the outputs RaO and Ra1, transmits the signal CP1 +2 . These different signals are represented in FIG. 5. It can be seen that the pulses CPa -1 to CP.sub. a+2 are cyclically generated every four pulses CP.
The clock circuit HGT also includes a delay circuit RT. This circuit receives the signal CP.sub. a+2 and, in response, delivers, after a short delay, a signal CPr. The latter, also represented in the waveshapes of FIG. 5, is generated between the signal CPa +2 the waveshapes of FIG. 5, is generated between the signal CPa +2 and the first next signal CPa -1.
The address ADC, deduced from the address ADE by removing the two lowest order bits, increases by one unit each time the address ADE increases by four units.
The recording and transmission circuit RS (FIG. 3) includes in particular three bistables BS1, BS2 and BS3. The triggering inputs of these bistables respectively receive the pulses CPa -1, CPa and CP.sub. a+1. The input 1 of each of them is connected to the input IM7 of the circulating memory module MMC7. Thus, for four bits inserted into module MMC7, three of them are displayed respectively on bistables BS1, BS2 and BS3. There will be given to these bits the general references ba -1, ba and ba +1. The bistables BS1 to BS3 are reset by the pulses CPr.
The auxiliary memory circuit MA includes in particular an addressable memory MAE and its control circuits. In the presence of a write signal ENR, thus in the absence of a read signal LEC, the bit supplied on the input conductor IMA of the memory MAE is recorded, at the address ADC, in a memory location. When the read signal LEC is present, the bit recorded at the address ADC is supplied on the output conductor OMA of the memory MAE.
The control circuits of this adddressable memory mainly include three AND gates ae1, ae2 and ae6 and one bistable BS6. The latter is set when the recording signal EN supplied on its input 1 appears simultaneously with the pulse CPa supplied on its triggering input. The gate ae2, one input of which is connected to the direct output of the bistable BS6, becomes conducting. It sends at the appearance of the next pulse. CPa +1, a recording signal ENR (FIG. 5) to the memory MAE. When the next pulse CPa +2 appears, the gate ae1 is enabled and retransmits an appropriate signal on a reset input of the bistable BS6; this bistable in then reset. The gate ae6, controlled by the pulse CPa +1 and the complementary output signal of the bistable BS6, supplies, at the appearance of the pulse CPa +1 and further to the absence of the signal EN, a read signal LEC also represented in FIG. 5.
Therefore, at each pulse CPa +1, a read or write operation is carried out in the memory MAE. FIG. 5 shows an example of the signals present at different points of the circuits in FIGS. 3 and 4 in the case when a write operation is carried out followed by a read operation and then by a second write operation followed by two read operations. The address ADC increases by one unit each time. If at the immediately preceding time CPa, the signal EN was present, the operation to be performed at the time CPa +1, in memory MAE is a writing process. Indeed, the bit supplied on conductor ED7 of the link PR, which can be called ba, is sent to the input IM7 of the module MMC7 and, at time CPa, it enters said module. Simultaneously, it is recorded by the bistable BS2. Then, at time CPa +1, said bit ba supplied by the bistable BS2. Then, at time CPa +1, said bit ba supplied by the bistable BS2, is recorded in memory MAE, in a location defined by the address ADC as previously described. Consequently, memory MAE, fed in this way, will keep an "extract" continuously up-dated of what contained the module MMC7; more precisely, it will keep one bit among four, designated by CPa among those contained in the module MMC7.
If in a time CPa, the signal EN is absent, the operation to be performed at time CPa +1 is a reading process. As an example, it may be contemplated that this reading takes place exactly one cycle after the recording of the previous bit ba. At time CPa +1, the memory MAE restores the bit ba on the conductor OMA.
This operation aims at checking the operation of the whole circulating memory and, more particularly, of the module MMC7. Indeed, it has been seen that the bistables BS1, BS2 and BS3 receive the bits stored in the module MMC7 at times CPa -1, CPa and CPa +. If there is no path recording, these bits come from the module output. Consequently, at the time when in memory MAE, the bit ba is read-out, this same bit has just been supplied by the module MMC7. It is recalled that this bit has entered the module at a time CPa. It must normally be present on the module output, one cycle later, also at a time CPa. It must be written on bistable BS2. But if there exists a shift error in the circulating memory, this bit ba may come out from module MMC7, either one time before, at CPa -, or one time later at CPa +. Then it will be displayed on bistable BS1 or BS3.
The comparison circuit CG includes in particular three "EXCLUSIVE OR" gates xg1, xg2 and xg3, two logic inverting circuits am1, am3, three AND gates ae3, ae4, and ae5 and two bistables BS4 and BS5. The first input of each gate xg1 to xg3 is connected to the output conductor OMA of memory MAE. The second inputs of these gates are respectively connected to the outputs 1 of bistables BS1, BS2 and BS3 of circuit RS. The outputs of these gates are connected either directly, or via two inverting circuits am1 and am3 to the inputs of gates ae3 and ae4. Finally, the outputs of both gates are respectively connected to the inputs 1 of bistables BS4 and BS5. The triggering inputs of these bistables are connected to the output of the AND gate ae5 controlled by signals CPa +2 and LEC.
Thus, normally, the bit ba, enters the module MMC7 at time CPa and is recorded at the same time CPa, one cycle later, by bistable BS2. It is available on the bistable output until the next time CPa +2 . In memory MAE, this same bit is read-out at time CPa +1 . It is available on the output conductor OMA of memory MAE during the time CPa +2 . During the latter, the three bits displayed by bistables BS1 to BS3 are compared to the bit displayed on conductor OMA and which has just been read-out from memory MAE.
It will be first assumed that the synchronism is correct, that is that there exists identity between the bit displayed on bistable BS2 and the bit available on the output conductor OMA of memory MAE. the EXCLUSIVE OR gate xg2 then supplies no signal. Gates ae3 and ae4 are non-conducting and deliver no signal to bistables BS4 and BS5. No correction control is sent to the correction circuit DC. The latter retransmits to the modules of the circulating memory MC pulses CP in the form of shift pulses CPS.
It will now be assumed that there is no synchronism, that is, no identity between the bit displayed on bistable BS2 and the bit available on conductor OMA, but that there exists identity between the bit displayed on bistable BS1 at time CPa +1 and the bit available on conductor OMA. There is thus lack of synchronism and it can be assumed that there is a shift forward of the circulating memory. The EXCLUSIVE OR gate xg2 supplies a signal 1 and therefore enables gates ae3 and ae4. The EXCLUSIVE OR gate xg1 supplies no signal and thus disables the gate ae4 and via the inverting signal am1 supplies a signal 1 to gate ae3. This gate becomes conducting when its third input is at 1, that is when the EXCLUSIVE OR gate xg3 supplies a signal. This is obtained when there is no identity between the bit displayed on bistable BS3 at time CPa +1 and the bit present on conductor OMA. It will then be assured that the circulating memory is shifted by one step forward. Gate ae3 delivers a signal to bistable BS4 which, in response, supplies a fast operation correction control fa to the correction circuit DC. The latter, upon receiving it, will not supply one of the next received pulses CP in the form of a shift pulse CPS. The circulating memory is thus prevented from stepping once. It is provided to equip the installations with a signalling means controlled by the fast operation correction control fa.
It will now be assumed that there is no synchronism and that the bit available on conductor OMA is identical to that displayed on the bistable BS3 at time CPa +1. The gate xg2 supplies a signal which enables gates ae3 and ae4. The gate xg3 supplies a 0 signal which renders gate ae3 non conducting. When the bit displayed on the bistable BS1 is different from the bit available on the output conductor OMA of memory MAE, it is assured that the circulating memory MC is shifted by one step backward. In this case, the gate xg1 delivers a 1 signal which is retransmitted by gate ae4 to the bistable BS5. In response, this bistable supplies a slow operation correction control fr to the correction circuit DC. The latter, upon receiving it, will supply when one of the next pulses CP is received, two shift pulses CPs to the memory MC. The shift backward of this memory is thus corrected. It is provided to equip the installations with a signalling means controlled by the slow operation correction control fr.
Thus, in the system according to the invention, the bits present on the input IM7 of the memory module MMC7 at times CPa -1, CPa and CPa +1 are respectively displayed on bistables BS1, BS2 and BS3. If at time CPa, the signal EN is absent, a read signal LEC is supplied to memory MAE. The bit recorded in this memory at the addres defined by ADC, that is the bit which has entered the module MMC7 at the corresponding time CPa, during the preceding cycle, is supplied on the output OMA of memory MAE. It must be the same as the bit displayed on the bistable BS2. If it is the case, no fault correction signal is supplied to the circuit DC. The latter, in this case, supplies simultaneously as it receives a pulse CP, a shift pulse CPS to the modules of the circulating memory MC.
If this condition is not fulfilled and if the bit supplied by the memory MAE is identical to that displayed at time CPa -1 on the bistable BS1 and different from the bit displayed on bistable BS3 at time CPa +1, it is certain that the error concerns the one forward step of the circulating memory. A fast operation correction control fa is supplied to the correction circuit DC. In response, the latter will not supply to the modules of the circulating memory MC a shift pulse CPS in response to the next received pulse CP. The one forward step is thus corrected.
If the bit supplied by memory MAE is identical to that displayed at time CPa -1 on bistable BS3 and different from the bit displayed on bistable BS1 and from the bit displayed on bistable BS2, it is certain that the error concerns one step backward of the circulating memory. A slow operation correction control fr is supplied to the correction circuit DC. In response, the latter as it receives a pulse CP supplies two shift pulses CPS to the modules of the circulating memory MC. The one backward step is then corrected.
Now will be described, referring to FIGS. 6 to 8, an embodiment of the correction circuit DC.
The correction circuit of FIG. 6 includes in particular 3 inputs INA, INB and INC receiving respectively the clock pulses CP, the fast and slow operation correction controls fa and fr. It delivers on its output OUA the shift pulses CPS and on the outputs OUB and OUC the pulses RZ4 and RZ5 which reset bistables BS4 and BS5 of the comparison circuit CG. It also includes one bistable BS7, one monostable MS1, two AND gates pt1 and pt3, one OR gate pt2 and a delay circuit CTP.
The bistable BS7 receives a permanent signal ep, on its input 1, the pulses CP on its triggering input and the fast operation correction control fa on its input 0.
When it receives simultaneously a signal on its triggering input and a signal on its input 1, this bistable triggers to state 1. Similarly, when it receives simultaneously a signal on its triggering input and a signal on its input O, it triggers to state O.
If it simultaneously receives a signal on its three inputs, it triggers. It will be assumed that initially bistable BS7 is in state 1.
When there is no correction signal fa, the first pulse CP maintains the bistable in position 1. The AND gate pt1 becomes conducting due to the signal present on an output conductor sa of bistable BS7. The pulses CP supplied at the input INA are then retransmitted in the form of shift pulses CPS to the output OUA, via the OR gate pt2.
It will be assumed that the comparison circuit CG of FIG. 3 delivers a fast operation correction control fa. As it can be seen in FIG. 3, this signal illustrated by the waveshapes of FIG. 7, is generated from the trailing edge of a pulse CPa +2. The next pulse CP causes the triggering of bistable BS7 to state O. This bistable, on the one hand, disables the gate pt1 and, on the other hand, supplies a signal RZ4 on the output OUB. This signal resets bistable BS4 of circuit CG. The fast operation correction control fa is no longer supplied.
The next pulse CP is not transmitted to the output OUA as gate pt1 is blocked. The trailing edge of this pulse causes bistable BS7 to trigger to state 1. There results, on the one hand, the enabling of gate pt1 and, on the other hand, the removal of signal RZ4 which resets bistable BS4. The operation is then continued as above-described.
Thus, the correction circuit DC has not sent to the circulating memory MC a clock pulse CP. As this pulse is normally supplied to the address counter CV, the memory steps back once with respect to the counter in order to be anew in synchronism.
It will be now assumed that the comparison circuit CG delivers a slow operation correction fr, illustrated by the waveshapes of FIG. 8. The next pulse CP is normally sent in the form of a shift pulse CPS at the output OUA of circuit DC. It is also transmitted on the output ms of the gate pt3 rendered conducting by signal fr. It causes the triggering of the monostable MS1. The output sb of the latter triggers to state 1 and then returns to state O. The positive pulse sb thus produced is supplied to the delay circuit CTP which, in response, supplies, after a time ttm a pulse on its output sc. This pulse is retransmitted via gate pt2 to the output OUA of the circuit DC.
Moreover, the output pulse of the monostable MS1 is supplied on the output OUC, in the form of a pulse RZ5 which resets bistable BS5. The slow operation correction control fr is no longer supplied and the gate pt3 becomes non-conducting. The operation is then continued as above-described.
Thus, the correction circuit DC has transmitted to the circulating memory MC two shift pulses CPS at the reception of one pulse CP. The memory goes one step ahead of counter CV and is in synchronism once again.
The correction circuit DC of FIG. 6 thus meets the definition of circuit DC of FIG. 3 and enables the readjustment of the circulating memory MC upon the appearance of a synchronism error signal.
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text:
Indonesia arrests alleged major people smuggler | Daily Mail Online
Published: 17:38 EDT, 25 September 2016 | Updated: 17:38 EDT, 25 September 2016
By Agustinus Beo Da Costa and Harry Pearl
JAKARTA/SYDNEY, Sept 24 (Reuters) - Indonesian police have arrested an alleged people smuggler who has targeted Australia since 1999, Indonesian and Australian authorities said on Saturday.
Abraham Louhenapessy, also known as Captain Bram, was arrested in Jakarta before dawn on Friday, Indonesia's national police spokesman Boy Rafli Amar said.
"He allegedly helped to smuggle people into Indonesia and out of Indonesia by providing a ship and he was also the captain of that ship," he said.
The Australian Federal Police suspected Louhenapessy was "the boss" of traffickers who have smuggled people into Australia and New Zealand, Amar said.
Louhenapessy is currently in police custody in Jakarta, but will be transferred to East Nusa Tenggara in the south-west of Indonesia to face trial.
Australian Immigration Minister Peter Dutton said: "We know that Captain Bram is a key player in the people smuggling networks across Indonesia."
Minister for Justice Michael Keenan said he could face up to 10 years in prison.
"We are extremely pleased this notorious people smuggler has been stopped ... but we know there are more criminal people smugglers out there and we will continue to work with our regional partners to bring them to justice," Keenan said in a statement.
The Indonesian police confiscated Louhenapessy's documentation, including his passport, along with flight tickets to Thailand, Kenya, Mali, Nigeria, France and the United Arab Emirates during the arrest, Amar said.
In its fight to stop people smugglers, Australia has adopted a tough asylum seeker policy which sees it intercept boats at sea and send the occupants to Australian-funded detention camps in Papua New Guinea and Nauru. They are never eligible to be resettled in Australia.
The United Nations and human rights groups have called for the closure of the camps, which have been rocked by riots, deaths, self-harm by detainees and reports of sexual abuse. (Reporting by Harry Pearl in Sydney and Agustinus Beo Da Costa in Jakarta; Editing by Michael Perry and Andrew Bolton)

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