text: Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3246386 *Jan 26, 1962Apr 19, 1966Corning Glass WorksElectrical connected component and methodUS3290559 *Jun 16, 1964Dec 6, 1966Internat Energy Conversion IncModular assembly for functional electronic blocksUS3313986 *Dec 23, 1965Apr 11, 1967Texas Instruments IncInterconnecting miniature circuit modulesUS3377516 *Aug 4, 1966Apr 9, 1968Hughes Aircraft CoCordwood package with removable plugsUS3403300 *Sep 1, 1966Sep 24, 1968Magnavox CoElectronic moduleUS3515949 *Nov 22, 1967Jun 2, 1970Bunker Ramo3-d flatpack module packaging techniqueUS3535595 *Nov 9, 1967Oct 20, 1970Ferroxcube CorpUniversal cord-wood moduleUS3614541 *Apr 8, 1969Oct 19, 1971North American RockwellPackage for an electronic assemblyUS3671812 *Jul 1, 1970Jun 20, 1972Martin Marietta CorpHigh density packaging of electronic components in three-dimensional modulesUS3949274 *May 30, 1974Apr 6, 1976International Business Machines CorporationPackaging and interconnection for superconductive circuitryUS4017963 *May 19, 1975Apr 19, 1977Signetics CorporationSemiconductor assembly and methodUS4288841 *Sep 20, 1979Sep 8, 1981Bell Telephone Laboratories, IncorporatedDouble cavity semiconductor chip carrierUS4394712 *Mar 18, 1981Jul 19, 1983General Electric CompanyAlignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafersUS4398235 *Sep 11, 1980Aug 9, 1983General Motors CorporationVertical integrated circuit package integrationUS4631573 *May 24, 1985Dec 23, 1986Sundstrand CorporationCooled stack of electrically isolated semiconductorsUS4638406 *Apr 14, 1986Jan 20, 1987Motorola, Inc.Discrete component mounting assemblyUS4642735 *Feb 27, 1984Feb 10, 1987General Electric CompanyFrequency synthesizer moduleUS4698663 *Dec 3, 1986Oct 6, 1987Fujitsu LimitedHeatsink package for flip-chip ICUS4706166 *Apr 25, 1986Nov 10, 1987Irvine Sensors CorporationHigh-density electronic modules--process and productUS4821007 *Feb 6, 1987Apr 11, 1989Tektronix, Inc.Strip line circuit component and method of manufactureUS4924352 *Dec 21, 1988May 8, 1990Societe Anonyme Dite: Alcatel CitMethod and device for cooling an integrated circuit packageUS4953005 *Apr 15, 1988Aug 28, 1990Xoc Devices, Inc.Packaging system for stacking integrated circuitsUS4996583 *Feb 9, 1990Feb 26, 1991Matsushita Electric Industrial Co., Ltd.Stack type semiconductor packageUS4996587 *Mar 23, 1990Feb 26, 1991International Business Machines CorporationIntegrated semiconductor chip packageUS5016138 *Sep 18, 1989May 14, 1991Woodman John KThree dimensional integrated circuit packageUS5025307 *Mar 29, 1990Jun 18, 1991Mitsubishi Denki Kabushiki KaishaModular semiconductor deviceUS5043794 *Sep 24, 1990Aug 27, 1991At&T Bell LaboratoriesIntegrated circuit package and compact assemblies thereofUS5058265 *Sep 10, 1990Oct 22, 1991Rockwell International CorporationMethod for packaging a board of electronic componentsUS5128831 *Oct 31, 1991Jul 7, 1992Micron Technology, Inc.High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled viasUS5140745 *Jul 23, 1990Aug 25, 1992Mckenzie Jr Joseph AMethod for forming traces on side edges of printed circuit boards and devices formed therebyUS5198888 *Dec 20, 1990Mar 30, 1993Hitachi, Ltd.Semiconductor stacked deviceUS5241454 *Jan 22, 1992Aug 31, 1993International Business Machines CorporationMutlilayered flexible circuit packageUS5281852 *Dec 10, 1991Jan 25, 1994Normington Peter J CSemiconductor device including stacked dieUS5343075 *Jun 22, 1992Aug 30, 1994Sony CorporationComposite stacked semiconductor device with contact platesUS5343366 *Jun 24, 1992Aug 30, 1994International Business Machines CorporationPackages for stacked integrated circuit chip cubesFR2645681A1 * Title not availableJPH0396266A * Title not availableJPH02260448A * Title not availableJPH04209562A * Title not availableJPS6163048A * Title not availableJPS6175558A * Title not availableJPS58219757A * Title not availableJPS60160664A * Title not availableJPS60254762A * Title not available* Cited by examinerNon-Patent CitationsReference1 *1992 Proceedings. 42nd Electronic Components & Technology Conference. May 18 20, 1992.21992 Proceedings. 42nd Electronic Components & Technology Conference. May 18-20, 1992.3 *3 D Integrated packaging and Interconnect Technology; Wescon/90 Conference Record, held 13 15 Nov. 1990, Anaheim, Ca.43-D Integrated packaging and Interconnect Technology; Wescon/90 Conference Record, held 13-15 Nov. 1990, Anaheim, Ca.5 *Article/Laminated Memory: A New 3 Dimensional Packaging Technology for MCMs. nCHIP, Inc., 1971 N. Capitol Avenue, San Jose, CA 95132 USA.6 *Dense Pac Microsystems flyer/ While others are still defining it . . . Our customers are cashing in .7 *Dense Pac Microsystems; 16 Megabit high Speed CMOS SRAM.8Dense-Pac Microsystems flyer/"While others are still defining it . . . Our customers are cashing in ".9Dense-Pac Microsystems; 16 Megabit high Speed CMOS SRAM.10 *IBM Technical Disclosure Bulletin, vol. 23 No. 12 May 1981.11 *IBM Technical Disclosure Bulletin. Vo. 32. No. 3B Aug. 1989.12 *IBM Technical Disclosure Bulletin. vol. 20 No. 11A Apr. 1978.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5696031 *Nov 20, 1996Dec 9, 1997Micron Technology, Inc.Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS5754405 *Nov 20, 1995May 19, 1998Mitsubishi Semiconductor America, Inc.Stacked dual in-line package assemblyUS5778522 *May 20, 1996Jul 14, 1998Staktek CorporationMethod of manufacturing a high density integrated circuit module with complex electrical interconnect rails having electrical interconnect strain reliefUS5857858 *Dec 23, 1996Jan 12, 1999General Electric CompanyDemountable and repairable low pitch interconnect for stacked multichip modulesUS5960539 *Feb 11, 1998Oct 5, 1999Staktek CorporationMethod of making high density integrated circuit moduleUS5963464 *Feb 26, 1998Oct 5, 1999International Business Machines CorporationStackable memory cardUS5973403 *Aug 19, 1997Oct 26, 1999Micron Technology, Inc.Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS6051887 *Aug 28, 1998Apr 18, 2000Medtronic, Inc.Semiconductor stacked device for implantable medical apparatusUS6071754 *Aug 19, 1997Jun 6, 2000Micron Technology, Inc.Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS6075284 *Jun 28, 1999Jun 13, 2000Hyundai Electronics Industries Co., Ltd.Stack packageUS6137162 *May 10, 1999Oct 24, 2000Hyundai Electronics Industries Co., Ltd.Chip stack packageUS6140149 *Sep 7, 1999Oct 31, 2000Micron Technology, Inc.Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS6153929 *Aug 21, 1998Nov 28, 2000Micron Technology, Inc.Low profile multi-IC package connectorUS6163459 *Jul 24, 1998Dec 19, 2000Matsushita Electric Industrial Co., Ltd.Semiconductor mounting system and semiconductor chipUS6168973Apr 15, 1999Jan 2, 2001Medtronic, Inc.Semiconductor stacked device for implantable medical apparatus and method for making sameUS6183301 *Jan 16, 1997Feb 6, 2001Berg Technology, Inc.Surface mount connector with integrated PCB assemblyUS6190425May 11, 1999Feb 20, 2001Zomaya Group, Inc.Memory bar and related circuits and methodsUS6222737Apr 23, 1999Apr 24, 2001Dense-Pac Microsystems, Inc.Universal package and method of forming the sameUS6225689Aug 14, 2000May 1, 2001Micron Technology, Inc.Low profile multi-IC chip package connectorUS6258623Jul 8, 1999Jul 10, 2001Micron Technology, Inc.Low profile multi-IC chip package connectorUS6262895Jan 13, 2000Jul 17, 2001John A. ForthunStackable chip package with flex carrierUS6281577 *Apr 22, 1997Aug 28, 2001Pac Tech-Packaging Technologies GmbhChips arranged in plurality of planes and electrically connected to one anotherUS6288907Jun 30, 1999Sep 11, 2001Staktek Group, L.P.High density integrated circuit module with complex electrical interconnect rails having electrical interconnect strain reliefUS6295220Nov 3, 1998Sep 25, 2001Zomaya Group, Inc.Memory bar and related circuits and methodsUS6316825May 10, 1999Nov 13, 2001Hyundai Electronics Industries Co., Ltd.Chip stack package utilizing a connecting hole to improve electrical connection between leadframesUS6329221Aug 18, 2000Dec 11, 2001Micron Technology, Inc.Method of forming a stack of packaged memory die and resulting apparatusUS6331938 *Oct 28, 1997Dec 18, 2001Surecom Technology CorporationStructural and electrical connections for stacked computer devicesUS6352437 *Oct 20, 1999Mar 5, 2002John O. TateSolder ball terminalUS6360433Sep 19, 2000Mar 26, 2002Andrew C. RossUniversal package and method of forming the sameUS6362519Apr 17, 2001Mar 26, 2002Micron Technology, Inc.Low profile multi-IC chip package connectorUS6395578May 19, 2000May 28, 2002Amkor Technology, Inc.Semiconductor package and method for fabricating the sameUS6399416Aug 18, 2000Jun 4, 2002Micron Technology, Inc.Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS6404043Jun 21, 2000Jun 11, 2002Dense-Pac Microsystems, Inc.Panel stacking of BGA devices to form three-dimensional modulesUS6409520 *Jul 31, 2001Jun 25, 2002Agilent Technologies, Inc.Structure and method for interconnection of printed circuit boardsUS6414396Jan 24, 2000Jul 2, 2002Amkor Technology, Inc.Package for stacked integrated circuitsUS6426549Nov 3, 2000Jul 30, 2002Harlan R. IsaakStackable flex circuit IC package and method of making sameUS6437433Mar 24, 2000Aug 20, 2002Andrew C. RossCSP stacking technology using rigid/flex constructionUS6445063Oct 19, 1999Sep 3, 2002Micron Technology, Inc.Method of forming a stack of packaged memory die and resulting apparatusUS6451626Jul 27, 2001Sep 17, 2002Charles W.C. LinThree-dimensional stacked semiconductor packageUS6452278Jun 30, 2000Sep 17, 2002Amkor Technology, Inc.Low profile package for plural semiconductor diesUS6462408Mar 27, 2001Oct 8, 2002Staktek Group, L.P.Contact member stacking system and methodUS6465275Aug 6, 2001Oct 15, 2002Micron Technology, Inc.Method of forming a stack of packaged memory die and resulting apparatusUS6473308Apr 19, 2001Oct 29, 2002John A. ForthunStackable chip package with flex carrierUS6475831Feb 23, 2001Nov 5, 2002Micron Technology, Inc.Methods for a low profile multi-IC chip package connectorUS6486546Feb 6, 2002Nov 26, 2002Micron Technology, Inc.Low profile multi-IC chip package connectorUS6486549Nov 10, 2001Nov 26, 2002Bridge Semiconductor CorporationSemiconductor module with encapsulant baseUS6487078Mar 13, 2000Nov 26, 2002Legacy Electronics, Inc.Electronic module having a three dimensional array of carrier-mounted integrated circuit packagesUS6509639Apr 30, 2002Jan 21, 2003Charles W. C. LinThree-dimensional stacked semiconductor packageUS6527588Feb 6, 2001Mar 4, 2003Fci Americas Technology, Inc.Electrical connector with integrated PCB assemblyUS6542376 *Mar 30, 2001Apr 1, 2003L-3 Communications CorporationHigh density packaging of electronic componentsUS6542393Apr 24, 2002Apr 1, 2003Ma Laboratories, Inc.Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-betweenUS6544045Nov 1, 2000Apr 8, 2003Fci Americas Technology, Inc.Surface mounted right angle electrical connectorUS6544815Aug 6, 2001Apr 8, 2003Harlan R. IsaakPanel stacking of BGA devices to form three-dimensional modulesUS6552416Sep 8, 2000Apr 22, 2003Amkor Technology, Inc.Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiringUS6566746Dec 14, 2001May 20, 2003Dpac Technologies, Corp.Panel stacking of BGA devices to form three-dimensional modulesUS6572387Mar 19, 2002Jun 3, 2003Staktek Group, L.P.Flexible circuit connector for stacked chip moduleUS6573460Sep 20, 2001Jun 3, 2003Dpac Technologies CorpPost in ring interconnect using for 3-D stackingUS6573461Sep 20, 2001Jun 3, 2003Dpac Technologies CorpRetaining ring interconnect used for 3-D stackingUS6576992Oct 26, 2001Jun 10, 2003Staktek Group L.P.Chip scale stacking system and methodUS6605489May 29, 2002Aug 12, 2003Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS6608763Sep 15, 2000Aug 19, 2003Staktek Group L.P.Stacking system and methodUS6642610Dec 20, 2000Nov 4, 2003Amkor Technology, Inc.Wire bonding method and semiconductor package manufactured using the sameUS6656767May 24, 2002Dec 2, 2003Micron Technology, Inc.Method of forming a stack of packaged memory diceUS6660561Jul 24, 2002Dec 9, 2003Dpac Technologies Corp.Method of assembling a stackable integrated circuit chipUS6677671Apr 11, 2002Jan 13, 2004Micron Technology, Inc.Apparatus for forming a stack of packaged memory diceUS6686655Jul 25, 2002Feb 3, 2004Micron Technology, Inc.Low profile multi-IC chip package connectorUS6707684Apr 2, 2001Mar 16, 2004Advanced Micro Devices, Inc.Method and apparatus for direct connection between two integrated circuits via a connectorUS6716670Apr 30, 2002Apr 6, 2004Bridge Semiconductor CorporationMethod of forming a three-dimensional stacked semiconductor package deviceUS6717248Nov 26, 2002Apr 6, 2004Amkor Technology, Inc.Semiconductor package and method for fabricating the sameUS6721196 *Jun 19, 2000Apr 13, 2004Giesecke & Devrient GmbhSemiconductor memory chip moduleUS6759737Mar 23, 2001Jul 6, 2004Amkor Technology, Inc.Semiconductor package including stacked chips with aligned input/output padsUS6762078Jan 30, 2001Jul 13, 2004Amkor Technology, Inc.Semiconductor package having semiconductor chip within central aperture of substrateUS6762487Apr 19, 2002Jul 13, 2004Simpletech, Inc.Stack arrangements of chips and interconnecting membersUS6765287Nov 29, 2002Jul 20, 2004Charles W. C. LinThree-dimensional stacked semiconductor packageUS6773955Jul 22, 2002Aug 10, 2004Micron Technology, Inc.Low profile multi-IC chip package connectorUS6794741Apr 30, 2002Sep 21, 2004Bridge Semiconductor CorporationThree-dimensional stacked semiconductor package with pillars in pillar cavitiesUS6803254Apr 25, 2003Oct 12, 2004Amkor Technology, Inc.Wire bonding method for a semiconductor packageUS6806120Mar 6, 2002Oct 19, 2004Staktek Group, L.P.Contact member stacking system and methodUS6849480Oct 26, 1999Feb 1, 2005Seagate Technology LlcSurface mount IC stacking method and deviceUS6856010Jul 14, 2003Feb 15, 2005Staktek Group L.P.Thin scale outline packageUS6869826Aug 4, 2003Mar 22, 2005Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS6878571Dec 11, 2002Apr 12, 2005Staktek Group L.P.Panel stacking of BGA devices to form three-dimensional modulesUS6884654Aug 4, 2003Apr 26, 2005Micron Technology, Inc.Method of forming a stack of packaged memory diceUS6886076 *Feb 3, 2000Apr 26, 2005Sharp Kabushiki KaishaSemiconductor integrated circuit device having connection pads for superposing expansion memoryUS6897553Aug 4, 2003May 24, 2005Micron Technology, Inc.Apparatus for forming a stack of packaged memory diceUS6914324Jun 3, 2003Jul 5, 2005Staktek Group L.P.Memory expansion and chip scale stacking system and methodUS6940729May 2, 2002Sep 6, 2005Staktek Group L.P.Integrated circuit stacking system and methodUS6955945May 25, 2004Oct 18, 2005Staktek Group L.P.Memory expansion and chip scale stacking system and methodUS6982488Jun 20, 2003Jan 3, 2006Amkor Technology, Inc.Semiconductor package and method for fabricating the sameUS7005350Dec 31, 2002Feb 28, 2006Matrix Semiconductor, Inc.Method for fabricating programmable memory array structures incorporating series-connected transistor stringsUS7005584Feb 13, 2004Feb 28, 2006Honeywell International Inc.Compact navigation device assemblyUS7009296Jan 15, 2004Mar 7, 2006Amkor Technology, Inc.Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor dieUS7023739Dec 5, 2003Apr 4, 2006Matrix Semiconductor, Inc.NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of sameUS7061120Mar 17, 2004Jun 13, 2006Amkor Technology, Inc.Stackable semiconductor package having semiconductor chip within central through hole of substrateUS7067911Oct 15, 2004Jun 27, 2006Bridge Semiconductor CorporationThree-dimensional stacked semiconductor package with metal pillar in encapsulant apertureUS7087442 *Sep 24, 2001Aug 8, 2006Pac Tech-Packaging Technologies GmbhProcess for the formation of a spatial chip arrangement and spatial chip arrangementUS7091061Mar 29, 2005Aug 15, 2006Micron Technology, Inc.Method of forming a stack of packaged memory diceUS7102892Feb 21, 2003Sep 5, 2006Legacy Electronics, Inc.Modular integrated circuit chip carrierUS7103970Mar 14, 2002Sep 12, 2006Legacy Electronics, Inc.Method for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chipsUS7109059Mar 22, 2005Sep 19, 2006Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7129113Oct 22, 2004Oct 31, 2006Bridge Semiconductor CorporationMethod of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant apertureUS7166495Feb 20, 1996Jan 23, 2007Micron Technology, Inc.Method of fabricating a multi-die semiconductor package assemblyUS7190060Oct 28, 2003Mar 13, 2007Bridge Semiconductor CorporationThree-dimensional stacked semiconductor package device with bent and flat leads and method of making sameUS7190071Feb 24, 2004Mar 13, 2007Amkor Technology, Inc.Semiconductor package and method for fabricating the sameUS7211900May 13, 2005May 1, 2007Amkor Technology, Inc.Thin semiconductor package including stacked diesUS7221588Dec 5, 2003May 22, 2007Sandisk 3D LlcMemory array incorporating memory cells arranged in NAND stringsUS7227249Dec 22, 2004Jun 5, 2007Bridge Semiconductor CorporationThree-dimensional stacked semiconductor package with chips on opposite sides of leadUS7233522Dec 5, 2003Jun 19, 2007Sandisk 3D LlcNAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of sameUS7262082Aug 3, 2006Aug 28, 2007Bridge Semiconductor CorporationMethod of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant apertureUS7282791 *Jul 8, 2005Oct 16, 2007Elpida Memory, Inc.Stacked semiconductor device and semiconductor memory moduleUS7282792Oct 18, 2005Oct 16, 2007Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7316060Apr 21, 2004Jan 8, 2008Legacy Electronics, Inc.System for populating a circuit board with semiconductor chipsUS7337522Nov 9, 2005Mar 4, 2008Legacy Electronics, Inc.Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chipsUS7375418 *Jun 14, 2006May 20, 2008Entorian Technologies, LpInterposer stacking system and methodUS7402902Nov 20, 2006Jul 22, 2008Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7405471Aug 26, 2003Jul 29, 2008Legacy Electronics, Inc.Carrier-based electronic moduleUS7411286Nov 20, 2006Aug 12, 2008Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7423338Nov 20, 2006Sep 9, 2008Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7423339Nov 20, 2006Sep 9, 2008Mircon Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7433233Jun 18, 2007Oct 7, 2008Sandisk 3D LlcNAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of sameUS7435097Jan 10, 2006Oct 14, 2008Legacy Electronics, Inc.Radial circuit board, system, and methodsUS7446403 *Jun 14, 2006Nov 4, 2008Entorian Technologies, LpCarrier structure stacking system and methodUS7494843Dec 26, 2006Feb 24, 2009Bridge Semiconductor CorporationMethod of making a semiconductor chip assembly with thermal conductor and encapsulant grindingUS7505321Dec 31, 2002Mar 17, 2009Sandisk 3D LlcProgrammable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of sameUS7508714May 21, 2007Mar 24, 2009Sandisk 3D LlcMemory array incorporating mirrored NAND strings and non-shared global bit lines within a blockUS7656678Oct 31, 2005Feb 2, 2010Entorian Technologies, LpStacked module systemsUS7675155Oct 31, 2008Mar 9, 2010Entorian Technologies, LpCarrier structure stacking system and methodUS7696616 *Apr 13, 2010Spansion LlcStacked type semiconductor device and method of fabricating stacked type semiconductor deviceUS7776652Aug 25, 2008Aug 17, 2010Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7796400Sep 14, 2010Legacy Electronics, Inc.Modular integrated circuit chip carrierUS7811863Oct 12, 2010Bridge Semiconductor CorporationMethod of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachmentUS7812436Oct 12, 2010Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS7902651Sep 28, 2004Mar 8, 2011Stec, Inc.Apparatus and method for stacking integrated circuitsUS7993983Aug 9, 2011Bridge Semiconductor CorporationMethod of making a semiconductor chip assembly with chip and encapsulant grindingUS8344518Jun 30, 2010Jan 1, 2013Stec, Inc.Apparatus for stacking integrated circuitsUS8686572Dec 19, 2012Apr 1, 2014Stec, Inc.Apparatus for stacking integrated circuitsUS9466545Feb 21, 2007Oct 11, 2016Amkor Technology, Inc.Semiconductor package in packageUS20010005042 *Jan 16, 2001Jun 28, 2001Burns Carmen D.Method of manufacturing a surface mount packageUS20020009828 *Sep 24, 2001Jan 24, 2002Pac Tech - Packaging Technologies GmbhProcess for the formation of a spatial chip arrangement and spatial chip arrangementUS20020045290 *Feb 20, 1996Apr 18, 2002Michael B. BallFlip chip and conventional stackUS20020142515 *Mar 6, 2002Oct 3, 2002Staktek Group, L.P.Contact member stacking system and methodUS20020162215 *Mar 14, 2002Nov 7, 2002Kledzik Kenneth J.Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chipsUS20020190367 *Jun 3, 2002Dec 19, 2002Mantz Frank E.Slice interconnect structureUS20030002267 *Jun 3, 2002Jan 2, 2003Mantz Frank E.I/O interface structureUS20030040166 *May 28, 2002Feb 27, 2003Mark MoshayediApparatus and method for stacking integrated circuitsUS20030051911 *Apr 5, 2002Mar 20, 2003Roeters Glen E.Post in ring interconnect using 3-D stackingUS20030064548 *Nov 8, 2002Apr 3, 2003Isaak Harlan R.Panel stacking of BGA devices to form three-dimensional modulesUS20030067082 *May 28, 2002Apr 10, 2003Mark MoshayediApparatus and methods for stacking integrated circuit devices with interconnected stacking structureUS20030081392 *May 2, 2002May 1, 2003Staktek Group, L.P.Integrated circuit stacking system and methodUS20030127746 *Dec 11, 2002Jul 10, 2003Isaak Harlan R.Panel stacking of BGA devices to form three-dimensional modulesUS20030137048 *Mar 27, 2003Jul 24, 2003Staktek Group, L.P.Stacking system and methodUS20030165051 *Feb 21, 2003Sep 4, 2003Kledzik Kenneth J.Modular integrated circuit chip carrierUS20030199118 *Apr 25, 2003Oct 23, 2003Amkor Technology, Inc.Wire bonding method for a semiconductor packageUS20030232085 *May 28, 2003Dec 18, 2003Emisphere Technologies, Inc.Polymeric delivery agents and delivery agent compoundsUS20040000708 *Jun 3, 2003Jan 1, 2004Staktek Group, L.P.Memory expansion and chip scale stacking system and methodUS20040007771 *Jun 20, 2003Jan 15, 2004Amkor Technology, Inc.Semiconductor package and method for fabricating the smaeUS20040026791 *Aug 4, 2003Feb 12, 2004King Jerrold L.Apparatus for forming a stack of packaged memory diceUS20040029315 *Aug 4, 2003Feb 12, 2004Wark James M.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20040052060 *Jul 14, 2003Mar 18, 2004Staktek Group, L.P.Low profile chip scale stacking system and methodUS20040108584 *Jul 14, 2003Jun 10, 2004Roeters Glen E.Thin scale outline packageUS20040124466 *Dec 31, 2002Jul 1, 2004Walker Andrew J.Method for fabricating programmable memory array structures incorporating series-connected transistor stringsUS20040125629 *Dec 31, 2002Jul 1, 2004Scheuerlein Roy E.Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of sameUS20040145024 *Dec 5, 2003Jul 29, 2004En-Hsing ChenNAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of sameUS20040164411 *Feb 24, 2004Aug 26, 2004Amkor Technology, Inc.Semiconductor package and method for fabricating the sameUS20040168316 *Mar 3, 2004Sep 2, 2004Moden Walter L.Low profile multi-IC chip package connectorUS20040175916 *Mar 17, 2004Sep 9, 2004Amkor Technology, Inc.Stackable semiconductor package having semiconductor chip within central through hole of substrateUS20040191442 *Mar 27, 2003Sep 30, 2004Florencia LimSurface modification of expanded ultra high molecular weight polyethylene (eUHMWPE) for improved bondabilityUS20040194301 *Apr 21, 2004Oct 7, 2004Kledzik Kenneth J.Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chipsUS20040197956 *May 25, 2004Oct 7, 2004Staktek Group L.P.Memory expansion and chip scale stacking system and methodUS20040207990 *Apr 21, 2003Oct 21, 2004Rose Andrew C.Stair-step signal routingUS20040245615 *Jul 21, 2003Dec 9, 2004Staktek Group, L.P.Point to point memory expansion system and methodUS20040252474 *Nov 25, 2002Dec 16, 2004Kwanghak LeeIntegrated circuit stack with lead framesUS20050009234 *Aug 6, 2004Jan 13, 2005Staktek Group, L.P.Stacked module systems and methods for CSP packagesUS20050018412 *Aug 9, 2004Jan 27, 2005Staktek Group, L.P.Pitch change and chip scale stacking systemUS20050041402 *Oct 5, 2004Feb 24, 2005Staktek Group, L.P.Integrated circuit stacking system and methodUS20050041404 *Oct 5, 2004Feb 24, 2005Staktek Group. L.P.Integrated circuit stacking system and methodUS20050056923 *Sep 28, 2004Mar 17, 2005Simpletech, Inc.Apparatus and method for stacking integrated circuitsUS20050067683 *Oct 29, 2004Mar 31, 2005Staktek Group L.P.Memory expansion and chip scale stacking system and methodUS20050098873 *Dec 17, 2004May 12, 2005Staktek Group L.P.Stacked module systems and methodsUS20050122779 *Dec 5, 2003Jun 9, 2005Fasoli Luca G.Memory array incorporating memory cells arranged in NAND stringsUS20050122780 *Dec 5, 2003Jun 9, 2005En-Hsing ChenNAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of sameUS20050128807 *Dec 5, 2003Jun 16, 2005En-Hsing ChenNand memory array incorporating multiple series selection devices and method for operation of sameUS20050146031 *Dec 14, 2004Jul 7, 2005Staktek Group, L.P.Low profile stacking system and methodUS20050161796 *Mar 22, 2005Jul 28, 2005Wark James M.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20050170558 *Mar 29, 2005Aug 4, 2005King Jerrold L.Method of forming a stack of packaged memory diceUS20050180120 *Feb 13, 2004Aug 18, 2005Levi Robert W.Compact navigation device assemblyUS20050205979 *May 13, 2005Sep 22, 2005Shin Won SSemiconductor package and method for fabricating the sameUS20060006516 *Jul 8, 2005Jan 12, 2006Elpida Memory, IncStacked semiconductor device and semiconductor memory moduleUS20060033187 *Aug 12, 2004Feb 16, 2006Staktek Group, L.P.Rugged CSP module system and methodUS20060033194 *Oct 18, 2005Feb 16, 2006Wark James MMethods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20060107524 *Nov 9, 2005May 25, 2006Jason EngleMethod and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chipsUS20060157842 *Jan 20, 2005Jul 20, 2006Staktek Group L.P.Inverted CSP stacking system and methodUS20060164820 *Jan 10, 2006Jul 27, 2006Mecker Donald WRadial circuit board, system, and methodsUS20060170090 *Jan 25, 2006Aug 3, 2006Spansion LlcStacked type semiconductor device and method of fabricating stacked type semiconductor deviceUS20060252180 *Jun 30, 2006Nov 9, 2006Moden Walter LMethod for a low profile multi-IC chip package connectorUS20060254809 *Jul 13, 2006Nov 16, 2006Kledzik Kenneth JModular integrated circuit chip carrierUS20070063229 *Nov 20, 2006Mar 22, 2007Wark James MMethods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20070063326 *Nov 20, 2006Mar 22, 2007Wark James MMethods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20070063327 *Nov 20, 2006Mar 22, 2007Wark James MMethods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20070063328 *Nov 20, 2006Mar 22, 2007Wark James MMethods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20070117266 *Jan 23, 2007May 24, 2007Ball Michael BMethod of fabricating a multi-die semiconductor package assemblyUS20070217263 *May 21, 2007Sep 20, 2007Fasoli Luca GMemory array incorporating memory cells arranged in nand stringsUS20070242511 *Jun 18, 2007Oct 18, 2007En-Hsing ChenNand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of sameUS20070290312 *Jun 14, 2006Dec 20, 2007Staktek Group L.P.Carrier structure stacking system and methodUS20070290313 *Jun 14, 2006Dec 20, 2007Staktek Group L.P.Interposer stacking system and methodUS20080003712 *Nov 16, 2006Jan 3, 2008Moden Walter LMethods of making semiconductor fusesUS20080203552 *Mar 8, 2005Aug 28, 2008Unisemicon Co., Ltd.Stacked Package and Method of Fabricating the SameUS20080311702 *Aug 25, 2008Dec 18, 2008Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20080315435 *Aug 25, 2008Dec 25, 2008Micron Technology, Inc.Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit diceUS20090072376 *Oct 31, 2008Mar 19, 2009Entorian Technologies, LpCarrier Structure Stacking System and MethodUS20090267220 *Oct 29, 2009Kuhlman Mark A3-d stacking of active devices over passive devicesUS20100327436 *Jun 30, 2010Dec 30, 2010Stec, Inc.Apparatus and method for stacking integrated circuitsUSD668658 *Oct 9, 2012Connectblue AbModuleUSD668659 *Oct 9, 2012Connectblue AbModuleUSD680119 *Apr 16, 2013Connectblue AbModuleUSD680545 *Apr 23, 2013Connectblue AbModuleUSD689053 *Nov 15, 2011Sep 3, 2013Connectblue AbModuleUSD692896 *Nov 15, 2011Nov 5, 2013Connectblue AbModuleUSRE36916 *Apr 22, 1998Oct 17, 2000Simple Technology IncorporatedApparatus for stacking semiconductor chipsUSRE40112Apr 14, 2004Feb 26, 2008Amkor Technology, Inc.Semiconductor package and method for fabricating the sameUSRE41039Dec 15, 2009Entorian Technologies, LpStackable chip package with flex carrierWO2004012264A1 *Jul 25, 2003Feb 5, 2004Pulse Engineering, Inc.High density electronics assembly and methodWO2004061861A2 *Dec 31, 2003Jul 22, 2004Matrix Semiconductor, Inc.Nand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of sameWO2004061861A3 *Dec 31, 2003Oct 28, 2004Matrix Semiconductor IncNand memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same* Cited by examinerClassifications U.S. Classification257/723, 361/760, 257/698, 257/E25.022, 257/685, 361/735, 257/E25.023, 257/686, 257/724International ClassificationH05K7/02, H01L25/10, H05K1/14Cooperative ClassificationH01L2924/0002, H01L2225/1029, H01L2225/1005, H01L2225/107, H05K1/145, H05K7/023, H01L25/105, H01L25/10European ClassificationH05K1/14E, H05K7/02B, H01L25/10, H01L25/10JLegal EventsDateCodeEventDescriptionMar 21, 1995ASAssignmentOwner name: SIMPLE TECHNOLOGY INCORPORATED, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOSHAYEDI, MARK;REEL/FRAME:007422/0820Effective date: 19950320Jun 2, 1998RFReissue application filedEffective date: 19980422Jul 26, 1999FPAYFee paymentYear of fee payment: 4Apr 18, 2000RFReissue application filedEffective date: 20000228RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text:
October Book Discussion - The Light Between Oceans by M.L. Stedman - Edmonton Book Club & Social Group (Edmonton, AB)
October Book Discussion - The Light Between Oceans by M.L. Stedman
We will read The Light Between Oceans by M.L. Stedman for our October book. The description:
Tom Sherbourne is a lighthouse keeper on Janus Rock, a tiny island a half day’s boat journey from the coast of Western Australia. When a baby washes up in a rowboat, he and his young wife Isabel decide to raise the child as their own. The baby seems like a gift from God, and the couple’s reasoning for keeping her seduces the reader into entering the waters of treacherous morality even as Tom--whose moral code withstood the horrors of World War I--begins to waver. M. L. Stedman’s vivid characters and gorgeous descriptions of the solitude of Janus Rock and of the unpredictable Australian frontier create a perfect backdrop for the tale of longing, loss, and the overwhelming love for a child that is The Light Between Oceans. =================
Jackie B Sitting in back of lounge side, wearing a pink sweater. See you soon! 0 · October 19, 2013 Sharon R. Not finished the book yet and now we are in the process of selling our home, so maybe next month. 0 · October 18, 2013 A former member Sorry friends, late notice shift change at work so I won't be able to make it. Have a drink for me! 0 · October 18, 2013 Violet R. I feel really bad about missing again but I have a friend here from Ontario for the weekend and we are going to be in Jasper on Saturday. I am really sorry. I do hope to make it for the next one. 0 · October 17, 2013 A former member Sorry I had to change my plans. Looking forward to meeting you next month. 0 · October 17, 2013 4 went
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Studyguide for Introduction to Probability with Statistical Applications by Schay, Geza, ISBN 9780817644970 by Cram101 Textbook Reviews | 9781617441103 | Paperback | Barnes & Noble®
Studyguide for Introduction to Probability with Statistical Applications by Schay, Geza, ISBN 9780817644970 available in Paperback
1617441104
9781617441103
Never HIGHLIGHT a Book Again! Includes all testable terms, concepts, persons, places, and events. Cram101 Just the FACTS101 studyguides gives all of the outlines, highlights, and quizzes for your textbook with optional online comprehensive practice tests. Only Cram101 is Textbook Specific. Accompanies: 9780817644970. This item is printed on demand.
Studyguide for Probability and Statistics by deGroot, Morris

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Corrections: February 22, 2015 - The New York Times
Corrections|Corrections: February 22, 2015
An article last Sunday about the decline of delta smelts in Northern California rivers misstated the extent of pumping measures taken to protect smelt. Pumping is sometimes reduced by shutting some of the pumps; all of the pumps are not typically shut at the same time.
A subheading last Sunday with an Associated Press article about legislation in Washington State to ease the way for its utilities to end coal-fired electricity described incorrectly in some editions the location of Montana, whose economy could be affected by the bills. It is separated from Washington by Idaho; it is not a neighboring state to Washington.
An article last Sunday about the growing number of high school wrestlers whose families come from Uzbekistan omitted, in some editions, the given name of the wrestling coach at New Utrecht High School in Brooklyn. He is Chris Friedrich.
A theater review in some editions last Sunday about “Familiar,” at the Yale Repertory Theater, misspelled the given name of the actress who plays Marvelous. She is Saidah Arrika Ekulona, not Saida.
Because of an editing error, an article last Sunday about segregation in Florida’s Grapefruit League referred incorrectly to Walter O’Malley’s role with the Brooklyn Dodgers in 1948. At the time, he was a part-owner of the team, not the owner. (He took over the team in 1950.)
An article in some editions last Sunday about the Millrose Games track meet in Manhattan misstated the given name of the runner-up in the men’s Wanamaker Mile. He is Nick Willis, not Patrick.
The Extra Bases notebook article last Sunday about absurd events in the coming Major League Baseball season misstated the year Atlanta Braves closer Craig Kimbrel struck out half his opposing hitters. It was 2012, not 2013.
An Associated Press report in the winter sports roundup in some editions last Sunday about the World Cup bobsled event in Sochi, Russia, misstated the date Elana Meyers Taylor secured her first overall World Cup bobsled title. It was on Saturday, Feb. 14, not the week before.
An obituary last Sunday about the composer Marvin David Levy referred incorrectly to the production history of his opera “Mourning Becomes Electra” at the Metropolitan Opera in New York. While it had its premiere in March 1967 and was staged at the Met only in that calendar year, there were performances in both the 1966-67 and 1967-68 seasons. It is not the case that the opera “was not staged again in the United States” for 31 years after the Met’s 1966-67 season.
An article in the special Your Taxes section last Sunday about tips to avoid pitfalls in preparing 2014 tax returns misstated the downside of excess withholding. It amounts to an interest-free loan to the Treasury, not a tax-free loan.
An article last Sunday about the value of voluntary climate treaties misstated the stance of the United States, China and India on the Kyoto Protocol. China and India were parties to the treaty; the United States signed the treaty but never ratified it. It is not the case that all three refused to join the agreement. (For China and India, the treaty was largely symbolic; they were not required to make any emissions cuts because they were designated “Non-Annex I” or “developing” nations.)
An article last Sunday about the fashion designer Betsey Johnson misstated part of the name of an award she received from the Council of Fashion Designers of America. It is the Timeless Talent Award, not the Tireless Talent Award.
A report on Feb. 8, about the marriage of Devon Bundy and Clovis Maalouf, misstated the surname of the bride’s father. He is Ken P. Cohen, not Bundy. In addition, the report, using information from the couple, misstated the date of their civil marriage at the Costa Rican vacation home of the bride’s parents. It was on Feb. 5 — not on Feb. 7, which was the date of a cultural ceremony and reception for them.
A cover article last Sunday about developers who seek and get vanity addresses for their projects described incorrectly Douglas Elliman’s involvement at 33 East 74th Street. The company is marketing the building, not developing it.
A review on Feb. 8 about “Founders’ Son: A Life of Abraham Lincoln,” by Richard Brookhiser, referred incorrectly to the book’s treatment of the succession of Union generals who suffered mostly defeats in the Civil War battles of the Seven Days, Second Bull Run, Antietam, Fredericksburg and Chancellorsville . It briefly discusses those generals; they are not “left unnamed."
A review on Jan. 11 about “All Eyes Are Upon Us: Race and Politics From Boston to Brooklyn,” by Jason Sokol, misstated the given name of a baseball player who, despite his historic professional breakthrough, was unwelcome as a homeowner in Northeastern suburbs during his career. He was Jack Roosevelt Robinson (known as Jackie), not James.
An article on Feb. 15 about a sexual-assault allegation misidentified the location in California of the home of Joe Lonsdale, the man who was accused and who has denied the accusation. He lived in the Los Altos hills, not the Los Gatos hills.
Because of an editing error, an article on Feb. 15 about the assassination of Rafik Hariri, the former prime minister of Lebanon, misstated the death toll in an Israeli drone strike in Syria. All seven men, an Iranian general and six members of Hezbollah, were killed, not six of the seven.

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Bigboymatt comments on Today is the 95th anniversary of the Great Train Wreck of 1918 (or the Great Nashville Train Wreck), in which two trains collided, killing more than 100 people.jump to contentmy subredditsannouncementsArtAskRedditaskscienceawwblogbookscreepydataisbeautifulDIYDocumentariesEarthPornexplainlikeimfiveFitnessfoodfunnyFuturologygadgetsgamingGetMotivatedgifshistoryIAmAInternetIsBeautifulJokesLifeProTipslistentothismildlyinterestingmoviesMusicnewsnosleepnottheonionOldSchoolCoolpersonalfinancephilosophyphotoshopbattlespicsscienceShowerthoughtsspacesportstelevisiontifutodayilearnedTwoXChromosomesUpliftingNewsvideosworldnewsWritingPromptsedit subscriptionsfront-all-random | AskReddit-funny-pics-todayilearned-videos-news-gifs-worldnews-movies-gaming-aww-Showerthoughts-mildlyinteresting-IAmA-explainlikeimfive-Jokes-Music-nottheonion-tifu-television-science-TwoXChromosomes-DIY-Futurology-LifeProTips-OldSchoolCool-space-Fitness-photoshopbattles-food-askscience-GetMotivated-UpliftingNews-personalfinance-Documentaries-sports-books-dataisbeautiful-WritingPrompts-Art-nosleep-EarthPorn-InternetIsBeautiful-history-creepy-gadgets-listentothis-philosophy-announcements-blogmore » historycommentsrelatedWant to join? Log in or sign up in seconds.|Englishlimit my search to /r/historyuse the following search parameters to narrow your results:subreddit:subredditfind submissions in "subreddit"author:usernamefind submissions by "username"site:example.comfind submissions from "example.com"url:textsearch for "text" in urlselftext:textsearch for "text" in self post contentsself:yes (or self:no)include (or exclude) self postsnsfw:yes (or nsfw:no)include (or exclude) results marked as NSFWe.g. subreddit:aww site:imgur.com dogsee the search faq for details.advanced search: by author, subreddit...this post was submitted on 09 Jul 20130 points (40% upvoted)shortlink: remember mereset passwordloginSubmit a new linkSubmit a new text posthistoryunsubscribesubscribe5,188,312 readers411 users here now
a community for 8 yearsmessage the moderatorsMODERATORSdavidreiss666Supreme Allied CommandereronankeResident ArchaeologistSamuel_GompersLikes CigarsAutoModeratorcavedavecondemned to repeatGeorgy_K_ZhukovFour Time Hero of /r/HistoryDaerescreeschChief Technologist, Fleet Admiralvertexoflifemarquis_of_chaos...and 16 more »discussions in /r/history<>X28 points · 25 comments See the Doodles Darwin’s Children Made in His “On the Origin of Species” Manuscript22 points · 22 comments Mongol invasion of Europe: Battle of Mohi18 points · 60 comments Civil war questions - Seige of Petersburg - 1864Who cleaned up after Battles? How did it work? Did both sides have a truce to clean up?5 points · 1 comment Ohio's Civil War Presidents18 points · 178 comments How the Soviet Union and China Almost Started World War III· 1 comment Rare audio recording of British troops firing gas shells at German positions during their advance on Lille, France, on October 9, 1918. Said to be the only known audio recording of combat from World War 1.Was overpopulation in Germany ever a concern for the Imperial German government?In the Russo-Soviet era, underground subversive jokes, the *anekdot*, was used to express thoughts and opinions otherwise forbidden.10 points · 29 comments Did all cultures develop identical time scales (ie, hours, minutes, seconds)?This is an archived post. You won't be able to vote or comment.
000Today is the 95th anniversary of the Great Train Wreck of 1918 (or the Great Nashville Train Wreck), in which two trains collided, killing more than 100 people. (gimby.org)submitted 2 years ago by [deleted]1 commentshareloading...sorted by: best (suggested)topnewcontroversialoldrandomq&ayou are viewing a single comment's thread.view the rest of the comments →[–]Bigboymatt 1 point2 points3 points 2 years ago (0 children)This took place roughy 15-20 miles north of Nashville, close to the Kentucky boarder. I remember going to my local historian society on a field trip and this was like a big deal because it took place in my hometown. permalinkembedsavegive goldPosts are automatically archived after 6 months.Got Itaboutblogaboutvaluesteamsource codeadvertisejobshelpsite rulesFAQwikireddiquettetransparencycontact usapps & toolsAlien Blue iOS appmobile betabuttons<3reddit goldreddit storeredditgiftsUse of this site constitutes acceptance of our User Agreement and Privacy Policy (updated). © 2016 reddit inc. All rights reserved.REDDIT and the ALIEN Logo are registered trademarks of reddit inc.Advertise - lifestylescreate a new accountusername:password:verify password:email: (optional)remember meget the best of reddit emailed to you once a week. learn moresign uplog inusername:password:remember mereset passwordlog inBy signing up, you agree to our Terms and that you have read our Privacy Policy and Content Policy.English [en]العربية [ar]Беларуская мова [be]български език [bg]Bosanski [bs]català [ca]česky [cs]dansk [da]Deutsch [de]Ελληνικά [el]English (Australia) [en-au]English (Canadian) [en-ca]English (Great Britain) [en-gb]English [en-us]Esperanto [eo]español [es]español [es-ar]eesti keel [et]Euskara [eu]فارسی [fa]suomi [fi]français [fr]Gàidhlig [gd]עברית [he]मानक हिन्दी [hi]hrvatski [hr]Magyar [hu]Հայերեն լեզու [hy]Bahasa Indonesia [id]íslenska [is]italiano (Italy) [it]日本語 [ja]ಕನ್ನಡ [kn_IN]한국어 [ko]Latin [la]1337 [leet]LOL [lol]lietuvių kalba [lt]latviešu valoda [lv]Nederlands [nl]Nynorsk [nn]Norsk [no]Arrrrrrrr! [pir]polski [pl]português [pt] (*)português [pt-pt]português brasileiro [pt_BR]română [ro]русский [ru]slovenčina [sk]slovenščina [sl]српски језик [sr]Srpski [sr-la]Svenska [sv]தமிழ் [ta]ภาษาไทย [th]Türkçe [tr]українська мова [uk]Tiếng Việt [vi]中文 [zh] (*) incomplete volunteer to translateπ Rendered by PID 25543 on app-12 at 2016-02-13 00:42:31.928755+00:00 running fb6d7b9 country code: US.

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BBB Business Profile | Floor Centre Of St Albert
Home > Alberta > Saint Albert > New Carpet > Floor Centre Of St Albert
367 St Albert Rd
St Albert, AB T8N 0R1
Mail sent to the business on 06/08/2017 was returned by the U.S. Postal Service as Moved Left No Address.

value: This website is a private, nonprofit organization whose self-described mission is to focus on advancing marketplace trust, consisting of 106 independently incorporated local BBB organizations in the United States and Canada, coordinated under the International Association of Better Business Bureaus  in Arlington, Virginia.The Better Business Bureau is not affiliated with any governmental agency. Businesses that affiliate with the BBB and adhere to its standards do so through industry self-regulation.


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Tariff, or Rates of Duties Payable on Goods, Wares and Merchandise, Imported Into the United States of America, Etc. by Ogden, E.D., Editor: Philip E. Bogert, New York Hardcover, First Edition, Thus - Row By Row Bookshop
Ogden, E.D., Editor
Tariff, or Rates of Duties Payable on Goods, Wares and ...
Tariff, or Rates of Duties Payable on Goods, Wares and Merchandise, Imported Into the United States of America, Etc.
Published by Philip E. Bogert, New York, 1865
A tight clean Very Good copy in lightly rubbed black cloth and black leather spine, lettered in gold at the spine and front cover. Includes addenda 1861-1865, and "all the recent circulars and decisions of the Treasury Department relating to commerce and the revenue". Bookseller Inventory # 007198
Title: Tariff, or Rates of Duties Payable on Goods,...
Publisher: Philip E. Bogert, New York

value: This website is an e-commerce global online marketplace with seven websites that offer books, fine art, and collectables from sellers in over 50 countries. Launched in 1996, it specialises in used, rare and out-of-print books.


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BBC News - Piri piri burr found near Forvie reserve
Piri piri burr found near Forvie reserve
Piri piri burr spreads quickly and can threaten other species
A highly invasive plant, originally from New Zealand, has been found on sand dunes near an internationally important nature reserve.
Several patches of piri piri burr are growing a few hundred metres from the Forvie reserve in north east Scotland.
The plant forms a compact ball of seeds, each with its own hook ready to attach to the socks, fur or wool of passing people or animals.
The seed later drops out, allowing the plant to spread. Like many non-native plants, it was first grown in gardens from which it escaped, either by seed spread or by people dumping garden waste in the countryside.
The plant was found by Scottish Natural Heritage (SNH) operations officer Mike Smedley.
He said: "We don't know of any large areas of piri piri burr in north east Scotland, but the island of Lindisfarne off the coast of Northumberland shows how bad the effects can be of unchecked spread. "The plant grows over the ground, creating a dense carpet which can eliminate other less robust species."
Annabel Drysdale, SNH's reserve manager at Forvie, added: "Invasive, non-native species are a worry on any nature reserve. "Because of the risk, we agreed with our neighbour that prompt action was necessary, so we are pulling up the plants before they seed and using herbicide on larger patches. "It is very timely that the Scottish government published its code of practice for invasive non-native species just last week, which explains the part we can all play in avoiding harm to our environment."
The control of non-native species such as Japanese Knotweed and Signal Crayfish is estimated to cost Scotland £244m every year. Scotland is the first country in the UK to aim to protect its native species through the publication of a code of practice.

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P. 1Cancelacion de Los Titulos de CreditoCancelacion de Los Titulos de CreditoRatings: (0)|Views: 2,684
|Likes: 24Published by Jose Francisco Ruiz MoralesMore info:Published by: Jose Francisco Ruiz Morales on Dec 01, 2010Copyright:Attribution Non-commercialAvailability:Read on Scribd mobile: iPhone, iPad and Android.download as DOC, PDF, TXT or read online from ScribdFlag for inappropriate content|Add to collectionSee moreSee lesshttp://www.scribd.com/doc/44442369/Cancelacion-de-Los-Titulos-de-Credito05/21/2013pdftextoriginal You're Reading a Free Preview
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Physical Therapist Jobs, Employment in Tolleson, AZ
Physical Therapist jobs in Tolleson, AZ
are seeking a Physical Therapist to provide excellent... degree in Physical Therapy Current BLS Healthcare Provider Card Current AZ Physical Therapy License in... Sponsored by Dignity Health - 16 days ago
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physical therapist to join our team at our north Phoenix location. Apex Physical Therapy is a therapist... experienced orthopedic therapists and have a strong... Arizona Physical Therapy Association - 9 hours ago
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recruiting for three physical therapy faculty with... for licensure within 60 days of hire as a physical therapist in Arizona and possess a minimum of five... 8 days ago
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Patent US7439965 - Method for driving display device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method is provided for reducing power consumption in a digital display including an array of pixels. The method includes reducing a switching frequency for driving the array of pixels and dividing the array of pixels into groups of a predefined size. A representative value of the input data for the...http://www.google.com/patents/US7439965?utm_source=gb-gplus-sharePatent US7439965 - Method for driving display deviceAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7439965 B2Publication typeGrantApplication numberUS 10/794,621Publication dateOct 21, 2008Filing dateMar 5, 2004Priority dateMar 5, 2004Fee statusPaidAlso published asUS20050195175Publication number10794621, 794621, US 7439965 B2, US 7439965B2, US-B2-7439965, US7439965 B2, US7439965B2InventorsDaryl E. AndersonOriginal AssigneeAnderson Daryl EExport CitationBiBTeX, EndNote, RefManPatent Citations (24), Referenced by (5), Classifications (16), Legal Events (12) External Links: USPTO, USPTO Assignment, EspacenetMethod for driving display device
Referring now to FIG. 2, a display 24 comprises a large number of pixels that are arranged in rows and columns. In the illustrated embodiment, for example, display 24 is arranged into 1280 columns of pixels and 1024 rows of pixels (i.e., display 24 is illustrated with a 1280×1024 pixels display area). In other embodiments, display 24 may have other screen resolution sizes such as 640×480, 800×600, 1024×768, 1152×864, 1600×1200, and 2048×1536 pixel display area.
In the example relationship illustrated in FIG. 3, each frame is formed from 256 subframes (numbered SFRN1, SFRN2, . . . SFRN285). Assuming a sufficiently fast clock rate, the viewer's eye will integrate the individual color levels during the subframes to provide what appears to be a single composite color for the resulting frame. Hence, there are 256 (=28) possible levels of color for each primary color per frame in the illustrated embodiment. Thus, display 26 is capable of displaying 16,777,216 (=2563) different colors in each frame. Since this is generally considered to be far more colors than the human eye is capable of distinguishing, display 26 may be considered to be operating in a “true color” mode. If desired, more or fewer than 256 subframes could be utilized to provide more or fewer than 256 possible color levels for each frame.
With reference now to FIG. 5, an exemplary embodiment is described in the context of a display 30 of the type shown in FIG. 3 (i.e., the three primary colors can be handled simultaneously) but configured in a reduced power mode. In accordance with this embodiment, display 30 is subdivided into pixel groups (or super-pixels) wherein each group has a predetermined dimension. In the embodiment of FIG. 5, for example, display 30 includes a 1280×1024 pixels display area that is divided into 327,680 pixel groups (R/G/B_SP—1 through R/G/B_SP—327680). The pixel groups are numbered sequentially from left to right along each row and from top to bottom along each column. As best shown in FIG. 7, each super-pixel 32 in this embodiment comprises four individual pixels (P1 through P4) arranged in a 2×2 rectangle.
With the pixel groups arranged as in FIG. 5, a weighting function may be utilized to significantly increase the number of colors available for each frame. For example, the weighting function may be used to determine an average (e.g., mean, median or mode) color or intensity level of the input image corresponding to the pixels in each group (R/G/B_SP—1 through R/G/B_SP—327680). The weighting function may also take into account the input image for pixels in one or more adjacent groups. In either case, the representative value (e.g., average) of the pixels in the group may be converted into a second set of pixels (e.g., a halftoned image) for display in the super-pixel. For example, if the image corresponding to super-pixel R/G/B_SP—1 in FIG. 5 has an average color level comprising 50% red, this color level could be provided using super-pixel 32 in FIG. 7 by displaying red in two of the four pixels. According to an exemplary embodiment, a mapping technique may be utilized to distribute each primary color across super-pixel 32. For example, a 50% red color level could be provided in super-pixel 32 by displaying red in pixels P1 and P4. Alternatively, red could be displayed in pixels P2 and P3 of super-pixel 32 to provide an equivalent distribution.
In the embodiment of FIG. 5, the foregoing super-pixel/halftoning technique provides a total of 125 (=53) colors for each pixel grouping. Although this is much less than the 16.7 million colors available during the true color (i.e., full resolution 24-bit color) operation mode described above in connection with FIG. 3, it is significantly better than the eight colors available without halftoning and still obtains the 256× reduction in power consumption compared to full color mode. Moreover, the penalty resulting from halftoning in this example is only a 2× reduction in resolution.
With reference now to FIG. 6, another exemplary embodiment of the present invention will be described in the context of a display 34 of the type shown in FIG. 4 (i.e., the three primary colors are handled sequentially in three subframes) but configured in a reduced power mode with enhanced color resolution. In this, embodiment, the 1280×1024 pixels display area is again divided into 327,680 pixel groups (R/G/B_SP—1 through R/G/B_SP—327680). Hence, each pixel group comprises a 2×2 super-pixel 32 as shown in FIG. 7. As explained above with the embodiment of FIG. 5, this arrangement provides five color (or intensity) levels for each primary, which provides 125 (=53) total colors per super-pixel per frame using the halftoning technique described above. The power consumption mode in this embodiment is still reduced by a factor of 256 compared to true color operation mode.
Referring now to FIG. 8, an alternative embodiment of a super-pixel 36 is shown for configuring a display to provide the same reduced power consumption as in the embodiments of FIGS. 5 and 6 but with more colors. In this embodiment, each super-pixel 36 comprises a 4×4 grouping of pixels (P1 through P16). With this arrangement, there are 17 possible color (or intensity) levels for each primary because anywhere between zero and sixteen pixels in super-pixel 36 may display each primary color (either simultaneously with the device of FIG. 3 or sequentially with the device of FIG. 4) during each frame. This arrangement provides a total of 4,913 (=173) possible colors for each super-pixel 36 during each frame, while still providing the 256× power reduction. Although this operating mode has a 4× reduction in resolution compared to true color mode, this level of resolution may be easily tolerated in many situations such as on displays that are already very high resolution and/or when viewing graphics (i.e., non-natural images).
The above-described super-pixel/halftoning technique could easily be extended for even larger super-pixel sizes to provide more colors. For example, a display of the type shown in FIG. 3 (i.e., all three primaries handled simultaneously) could be divided into super-pixels having dimensions of 5×5 pixels (i.e., 25 pixels per group) to provide for 17,576 (=263) total colors per frame without using any subframes. Similarly, the same color depth (i.e., 17,576 total colors) could be obtained in a display of the type shown in FIG. 4 (i.e., the three primaries handled sequentially) using 5×5 super-pixels and three subframes per frame (i.e., one subframe per primary). Both of these example embodiments would provide the 256× reduction in power compared to true color mode.
Turning now to FIG. 10, an example of a hybrid embodiment is shown in which a display 40 of the type shown in FIGS. 3 and 5 (i.e., all three primaries are handled simultaneously) is configured to provide significantly more colors than in the embodiment of FIG. 5. In this embodiment, the pixels in display 40 are grouped into 4×4 super-pixels (as shown in FIG. 8) that are switched four times per frame (i.e., four subframes per frame), rather than once per frame as in the embodiment of FIG. 5. This arrangement allows 17 color levels per primary per subframe, which provides 68 (=17×4) color levels per primary for the frame. Hence, there are a total of 314,432 (=683) total colors available per frame in this embodiment, while still saving 64 times the power used in true color mode.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5122783Jul 27, 1990Jun 16, 1992Cirrus Logic, Inc.System and method for blinking digitally-commanded pixels of a display screen to produce a palette of many colorsUS5159478Jul 26, 1989Oct 27, 1992Kabushiki Kaisha ToshibaTransmission liquid crystal display apparatusUS5552800Aug 23, 1994Sep 3, 1996Kabushiki Kaisha ToshibaColor display control apparatus for controlling display gray scale of each scanning frame or each plurality of dotsUS5598565Dec 29, 1993Jan 28, 1997Intel CorporationMethod and apparatus for screen power savingUS5691745Jan 6, 1995Nov 25, 1997Microsoft CorporationLow power pixel-based visual display device having dynamically changeable number of grayscale shadesUS5712651Jul 10, 1995Jan 27, 1998Kabushiki Kaisha ToshibaApparatus for performing a full-color emulation on the TFT display deviceUS5790215Mar 13, 1996Aug 4, 1998Kabushiki Kaisha ToshibaLiquid crystal display deviceUS5854627Nov 9, 1995Dec 29, 1998Hitachi, Ltd.TFT liquid crystal display device having a grayscale voltage generation circuit comprising the lowest power consumption resistive stringsUS5940049Aug 15, 1996Aug 17, 1999Polycom, Inc.Remote interactive projector with image enhancementUS6072454Feb 28, 1997Jun 6, 2000Kabushiki Kaisha ToshibaLiquid crystal display deviceUS6175355Jul 11, 1997Jan 16, 2001National Semiconductor CorporationDispersion-based technique for modulating pixels of a digital display panelUS6184853Feb 12, 1998Feb 6, 2001Alps Electric Co., Ltd.Method of driving display deviceUS6198469Jul 1, 1998Mar 6, 2001Ignatius B. Tjandrasuwita“Frame-rate modulation method and apparatus to generate flexible grayscale shading for super twisted nematic displays using stored brightness-level waveforms”US6222508Oct 8, 1999Apr 24, 2001Massachusetts Institute Of TechnologyVLSI visual displayUS6232938Nov 17, 1998May 15, 2001Kabushiki Kaisha ToshibaLiquid crystal display device with low power consumption and high picture qualityUS6326942Jun 23, 1998Dec 4, 2001Sony CorporationOptical spatial modulation device and image display apparatusUS6542141Jun 6, 2000Apr 1, 2003Hitachi, Ltd.Liquid-crystal halftone display systemUS6556181May 14, 1999Apr 29, 2003International Business Machines CorporationMatrix driven liquid crystal display module system apparatus and methodUS6825835 *Nov 23, 2001Nov 30, 2004Mitsubishi Denki Kabushiki KaishaDisplay deviceUS7245272 *Aug 12, 2003Jul 17, 2007Via Technologies, Inc.Continuous graphics display for dual display devices during the processor non-responding periodUS20020063701 *Nov 23, 2001May 30, 2002Ko SanoDisplay deviceUS20040075622 *Aug 12, 2003Apr 22, 2004Shiuan Yi-Fang MichaelContinuous graphics display for dual display devices during the processor non-responding periodJP2001147671A Title not availableJP2003108094A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS8218228Dec 18, 2009Jul 10, 2012Qualcomm Mems Technologies, Inc.Two-terminal variable capacitance MEMS deviceUS8922974Jan 28, 2013Dec 30, 2014Qualcomm IncorporatedMEMS varactorsUS20110148837 *Dec 18, 2009Jun 23, 2011Qualcomm Mems Technologies, Inc.Charge control techniques for selectively activating an array of devicesUS20110149374 *Dec 18, 2009Jun 23, 2011Qualcomm Mems Technologies, Inc.Two-terminal variable capacitance mems deviceCN104952425A *Jul 21, 2015Sep 30, 2015京东方科技集团股份有限公司Display substrate, display device and display substrate resolution adjustment method* Cited by examinerClassifications U.S. Classification345/204, 345/211, 345/1.1, 345/698, 345/699International ClassificationG09G5/00, G09G3/20Cooperative ClassificationG09G3/2074, G09G2360/18, G09G2310/0235, G09G3/2018, G09G3/2077, G09G2340/0407, G09G2330/021European ClassificationG09G3/20G14, G09G3/20G6Legal EventsDateCodeEventDescriptionMar 26, 2004ASAssignmentOwner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXASFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANDERSON, DARYL E.;REEL/FRAME:015915/0133Effective date: 20040303Jul 21, 2009CCCertificate of correctionOct 5, 2011ASAssignmentOwner name: CHIMEI INNOLUX CORPORATION, TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;HEWLETT-PACKARD COMPANY;REEL/FRAME:027016/0958Effective date: 20110728Jun 4, 2012REMIMaintenance fee reminder mailedOct 21, 2012LAPSLapse for failure to pay maintenance feesOct 21, 2012REINReinstatement after maintenance fee payment confirmedDec 11, 2012FPExpired due to failure to pay maintenance feeEffective date: 20121021Apr 3, 2014ASAssignmentOwner name: INNOLUX CORPORATION, TAIWANFree format text: CHANGE OF NAME;ASSIGNOR:CHIMEI INNOLUX CORPORATION;REEL/FRAME:032604/0487Effective date: 20121219Aug 4, 2014PRDPPatent reinstated due to the acceptance of a late maintenance feeEffective date: 20140808Aug 8, 2014FPAYFee paymentYear of fee payment: 4Aug 8, 2014SULPSurcharge for late paymentApr 21, 2016FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

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Patent US5781037 - Method and apparatus for an address transition detection circuit - Google Patents
The present invention relates to an improvement to an address transition detection (ATD) circuit in an IC chip, a method related to the improved ATD circuit is also disclosed. The improved ATD circuit applies a transfer gate and a lot of inverters to construct a new ATD circuit. Not only reduces power...http://www.google.com/patents/US5781037?utm_source=gb-gplus-sharePatent US5781037 - Method and apparatus for an address transition detection circuit
Publication number US5781037 A
Application number US 08/683,459
Publication number 08683459, 683459, US 5781037 A, US 5781037A, US-A-5781037, US5781037 A, US5781037A
Inventors Steve Chaw
Original Assignee United Microelectronics, Inc.
Method and apparatus for an address transition detection circuit
US 5781037 A
The present invention relates to an improvement to an address transition detection (ATD) circuit in an IC chip, a method related to the improved ATD circuit is also disclosed. The improved ATD circuit applies a transfer gate and a lot of inverters to construct a new ATD circuit. Not only reduces power dissipation while an address transition is detecting, but less consumption on transistors is achieved. Each time when the logic state of an input pin is switching, the improved ATD circuit generates an inverting phase signal based on the switching; next, a transfer gate generates a driving signal for waking up the chip from idleness; a delaying circuit then generates a regular time interval for the chip to operate the task indicated by the varied address. At the end of the regular time interval, the chip returns to idleness again to wait another job's coming.
1. An address transition detection apparatus for reducing power consuming, wherein said apparatus comprises:
inputting means responsive to an input signal for generating a pair of outputs including an inverted phase representation of said input signal and a non-inverted phase representation of said input signal;
delaying means responsive to said non-inverted phase representation of said input signal for generating a delayed signal having a substantially same waveform as said input signal but appears after a regular time interval;
transferring means responsive to said inverted phase representation of said input signal, said non-inverted phase representation of said input signal, and said delayed signal for generating a driving signal, said transferring means comprises:
a first MOS transistor, having a gate, a drain, and a source, said source of said first MOS transistor receives said inverted Phase representation of said input signal;
a second MOS transistor, having a gate, a drain, and a source, said gate of said second MOS transistor is coupled with said gate of said first MOS transistor to receive said delayed signal, said source of said second MOS transistor receives said non-inverted phase representation of said input signal, and said drain of said second MOS transistor is coupled with said drain of said first MOS transistor and outputs said driving signal; and
driving means responsive to said driving signal for driving a chip from idleness.
2. The address transition detection apparatus according to claim 1, wherein said inputting means comprises:
a first inverter receives said input signal for outputting said inverting phase signal; and
a second inverter receives said inverting phase signal for reversing the phase of said inverting phase signal.
3. The address transition detection apparatus according to claim 2, wherein inverter is a CMOS (complementary MOS) inverter.
4. The address transition detection apparatus according to claim 1, wherein said delaying means further comprising a plurality of inverters, and the number of said plurality inverters is even.
5. The address transition detection apparatus according to claim 1, wherein said driving means further comprising:
a driving MOS transistor having a gate, a drain, and a source, said gate of said driving MOS transistor receives said driving signal for driving a chip from idleness; and
a loading MOS transistor having a gate, a drain, and a source, said source of said loading MOS transistor is coupled together with said drain of said driving MOS transistor.
6. The address transition detection apparatus according to claim 5, wherein said driving MOS transistor is a NMOS transistor.
7. The address transition detection apparatus according to claim 5, wherein said loading MOS transistor is PMOS transistor.
8. An address transition detection apparatus for reducing power consuming, said apparatus comprises:
inputting means responsive to an input signal for generating a pair of outputs including an inverted phase representation of said input signal and a non-inverted phase representation of said input signal
a transferring means responsive to said inverted phase representation of said input signal, said non-inverted phase representation of said input signal, and said delayed signal for generating a driving signal, said transferring means comprises:
a second MOS transistor, having a gate, a drain, and a source, said gate of said second MOS transistor is coupled with said gate of said first MOS transistor to receive said delayed signal, said source of said second MOS transistor receives said non-inverted phase representation of said input signal, and said drain of said second MOS transistor is coupled with said drain of said first MOS transistor and outputs said driving signal;
driving means responsive to said driving signal for driving a chip from idleness said driving means comprises:
a driving MOS transistor having a gate, a drain, and a source, said gate of said driving MOS transistor receives said driving signal: and
a loading MOS transistor having a gate, a drain, and a source, said source of said loading MOS transistor is coupled together with said drain of said driving MOS transistor for driving said chip from idleness.
9. The address transition detection apparatus according to claim 8, wherein said inputting means comprises:
10. The address transition detection apparatus according to claim 9, wherein said inverter is a CMOS (complementary MOS) inverter.
11. The address transition detection apparatus according to claim 8, wherein said delaying means further comprising a plurality of inverters, and the number of said plurality inverters is even.
12. The address transition detection apparatus according to claim 8 wherein said driving MOS transistor is a NMOS transistor.
13. The address transition detection apparatus according to cIaim 8, wherein said loading MOS transistor is PMOS transistor.
14. The address transition detection apparatus according to claim 8, wherein said amplifying means further comprising a plurality of cascading power amplifiers.
15. A method for detecting an happening of an address transition, said method comprising the steps of:
generating apair of differential outputs according to an input signal, said pair of said differential outputs including an inverted phase representation of said input signal and a non-inverted phase representation of said input signal;
generating a high voltage level by using said inverted phase representation of said input signal and said non-inverted phase representation of said input signal;
driving a chip from idleness by using said high voltage level;
delaying said input signal by using said non-inverted phase representation of said input signal, said delayed input signal having a substantially same waveform as said input signal but appears after a regular time interval;
keeping said chip active in said regular time interval;
generating a low voltage level when said delayed input signal arrives; and said input signal is maintained in said regular time interval while said chip remains active changing said active chip back to idleness by using said low voltage level.
The present invention relates to an address transition detection circuit, and more particularly to a system for reducing power dissipation of a chip each time when the state of an input pin is changing, and furthermore, applying fewer transistors on a chip without losing accuracy and speed of the system.
The present invention relates to an address transition detection (to be referred to "ATD" hereinafter) circuit that consumes less power while driving a chip from idleness, and fewer transistors in building the ATD circuit.
Power dissipation is an important topic of IC technologies. Every one skilled in the art wants to produce a chip with less power dissipation. It is a tendency that a chip consumes little power when the states of input pins of the chip (to be referred to "the address of the chip" hereinafter) keep the same, which is commonly referred to as a "sleep mode". Each time when an address is changing, an ATD circuit of the chip tests this change and "wakes up" the chip from sleep mode for processing the operations indicated by the address.
The operation of the ATD circuit is to detect whether the address of a chip is transiting or not. While an input pin is switching its state (whether the state is changing from logic 0 to logic 1 or from logic 0 to logic 1), the ATD circuit is capable of detecting this switching and then generating a driving signal to wake up the chip from sleeping. The chip will keep wakefully in a regular time interval for operating the specific task indicated by the address where the regular time interval is varying based on the necessity of the specific task. At the end of the regular time interval, the chip returns to sleep mode and waits for another address' transition, or, another task's coming.
The ATD circuit needs to consume power while waking up a sleeping chip. FIG. 1 describes a conventional ATD circuit, which consumes a great deal of DC current. Furthermore, too many transistors used in constructing such a conventional ATD circuit occupy a lot of space and increase the size of a chip. The present invention discloses an improved method and apparatus for overcoming these disadvantages.
The principal object of the present invention is to provide an ATD circuit to be capable of efficiently reducing power dissipation while detecting a transition of an address to a chip.
The other object of the present invention is to provide a skill to construct an ATD circuit with fewer transistors but maintain the similar detecting speed and performance.
The improved ATD circuit according to present invention is composed of delay circuit, a transfer gate, and a lot of inverters to behave as an edge trigger generator. All improvements to a traditional ATD circuit are completing after combining a widespread use of NOR plane. Not only are fewer transistors used in constructing an ATD, but less power dissipation is consumed in practice.
In operations, the improved ATD circuit first generates an inverting phase signal by reversing the phase of each input signal of an address. The transfer gate receives both the input signal and the inverting phase signal and generates at driving signal. While the state of an input pin is changing, the driving signal will drive the NOR plane to wake up the chip from idleness. The chip is wakeful in an operating period to process the task indicated by the address. At the end of the operating period, the chip returns to idleness and waits for another task's coming.
FIG. 1 represents the block diagram of a conventional ATD circuit;
FIG. 2 represents the circuit diagram of the conventional ATD circuit according to FIG. 1;
FIG. 3 represents the waveform diagram while a transition appears in a bit of an address according to the conventional ATD circuit in FIG. 1;
FIG. 4 represents the block diagram of an improved ATD) circuit according to the present invention;
FIG. 5 represents the circuit diagram of the improved ATD circuit according to FIG. 4;
FIG. 6 represents the waveform diagram while a transition appears in a bit of an address according to FIG. 4;
FIG. 7 represents an additional amplifier supplementing in the preferred embodiment; and
FIG. 8 is a flow chart for describing the operations according to the present invention.
The block diagram of a conventional ATD circuit in an input pin of a chip is described in FIG. 1. There are 3 basic units in the conventional ATD circuit: a delaying unit 11 receiving an input signal Si from an input pin of a chip, and providing a delayed input signal Sid based on Si; a testing unit 12 receiving the delayed input signal Sid, and generating a driving signal Sdrive ; and a driving unit 13 receiving the driving signal Sdrive and providing a final output SoATD to drive the chip from idleness.
FIG. 2 shows the circuit diagram of the conventional ATD circuit according to FIG. 1. It is clear that the delaying unit 11 is a conventional delaying circuit composed of 4 inverters 111, 112, 113, and 114, 2 resistors Ri1 and Ri2, an 2 capacitors Ci1 and Ci2. The configuration of resistors Ri1 and Ri2, and capacitors Ci1 and Ci2 is 2 R-C circuit to delay Si. All skilled in the art know that a capacitor costs a lot of time to charge and/or discharge, this characteristic is comprehensively applied in a delaying circuit. The testing unit 12 is composed of a NAND gate 121, 2 NOR gates 122 and 124, and a CMOS inverter 123. Check points A (Sid), B, C, and D (Sdrive) are also chosen for showing their current logic states. Driving unit 13 is composed of a PMOS transistor 131 and an NMOS transistor 132. The transistor 131 is an active load of transistor 132 by coupling the drain of the transistor 131 to the drain of the transistor 132. The configuration of the driving unit 13 is a NOR plane. All input pins can share the same NOR plane by sharing the same active load (transistor 131) and provide SoATD to wake up a chip from sleeping each time while an input pin switches its state.
FIG. 3 represents the waveform of the conventional ATD circuit according to FIG. 2. It simply describes the variation of an input pin Si on a chip. Hereinafter, a positive logic is following for describing the following waveform. That is, the high voltage level is defined as logic 1 (referring to "high" for short) and the low voltage level represents logic 0 (referring to "low" for short). The initial state of Si is low, the state of the point A, the point B and the point D are assumed low, but both the point C and the final output SoATD are assumed high.
When Si switches its state to high, both the points A and B still remain on low but the point D transits its state to high, and the point C drops from high to low at the same time. The delaying unit 11 delays Si in a regular time interval (define this interval as an operating period) to keep the state of the point A remaining on low until the end of the operating period. The point B is also low by the effecting of the delaying unit 11. A branch by passes the delaying unit 11 to affect the states of the points B, C, and D immediately. The state of the point B still remains on low because point A is low. The point C drops to low because the output of the NOR gate 122 is low, and the point D is high because the output of NOR gate 124 is high. The transistor 132 is turned on by the high state of the point D, while the final output SoATD drops to low for waking up the chip from idleness to process the operations indicated by the varied address.
At the end of the operating period, the state of the point A turns to high and also does the point B. The point C still remains on low but the point D drops from high to low, and the transistor 132 is cut off by the low state of the point D at the same time. Thus, the state of the final output SoATD is pulled to high, terminating the operations of the task indicating by the varied address. The chip then goes idleness to wait another address transition, or, another task' coming.
Another operating period starts when Si returns to low. The state of the point A still remains on high and the point C is still low, but the point B drops to low. The point D turns to high to indicate a happening to an address transition. The transistor 132 is turned on by the high state of the point D, and the final output SoATD drops to low to wake up the chip from sleeping once again. The chip also keeps wakefully in the operating period to process the task indicated by the varied address. At the end of the operating period, the state of the point A and point D drop to low, the point B is still on low, but the point C is pulling to high. After the transistor 132 is cut off again by the low state of point D, the final output SoATD turns to high to terminate the operating period and the operations of the task indicated by the address. The chip then goes idleness to wait another address transition. Obviously, it is possible that several input pins of a chip can switch their states simultaneously. However, the final output SoATD is still low even there are several driving signal Sdrive routing to the NOR plane but more transistors are turned on.
It seems that too much power dissipation is consumed and too many transistors are used in constructing such a conventional ATD circuit. There are at least 3 positions where DC current is consumed: the first inverter 111 of the delaying unit 11, and the NAND gate 121 and the NOR gate 122 connecting directly with the delaying unit 11. In addition, 14 transistors are used in constructing the testing unit 12 (a NAND gate contains 4 MOS transistors and so does a NOR gate, and 2 MOS transistors in a CMOS inverter).The present invention suggests an improvement to these disadvantages mentioned above.
FIG. 4 represents a block diagram of the present invention. It detects the variation of an input pin Si on a chip. There are 4 basic elements in this diagram: inputting unit 41 for receiving the input signal Si from an input pin, providing Si and generating an inverting phase signal Si', which has the same characteristics with the input signal Si but the phase is inverted; delaying unit 44 for delaying Si, and generating a delayed signal Sid according to Si; transferring unit 42 for receiving the input signal Si, the inverting signal Si', and the delayed signal Sid, and generating a driving, signal Sdrive ; and driving unit 43 for receiving the driving signal Sdrive and generating a final output SoATD to wake up the chip from idleness.
FIG. 5 illustrates a detailed circuit diagram of an improved ATD circuit according to
FIG. 4. The inputting unit 41 includes 2 inverters 411 and 412. The inverter 411 generates the inverting signal Si' and the inverter 412 inverts Si' back to Si. The delaying unit 44 applies the conventional delay circuit by using 2 resistors Ri1 and Ri2 and 2 capacitors Ci1 and Ci2 to form 2 R-C circuit. The delaying effect is achieved also by using the characteristic that the charging and/or discharging of a capacitor must cost a great deal of time. Transferring unit 42 includes an NMOS transistor 421 and a PMOS transistor 422 with their gates tied together to receive the delayed signal Sid ; the source of the transistor 421 connects with the output of the inverter 411 to receive the inverting signal Si', but the source of the transistor 422 connects with the output of the inverter 412 to receive Si; both drains of the transistors 421 and 422 are coupled together to provide a driving signal Sdrive (in fact, the transferring unit 42 is just a transfer gate). In the driving unit 43, it is constructed as a NOR plane by using a PMOS transistor 431 to be the active load of an NMOS transistor 432, and the NOR plane is capable of sharing by all input pins of the chip. Again, 4 check points A (Si), B (Si'), C (Sdrive), and D (Sid) are chosen for showing their current logic states.
It is obvious that fewer transistors are used in the present invention than traditional ATD circuit. The inputting unit 41 needs 4 transistors (there is 2 MOS transistors in a CMOS inverter), and 2 MOS transistors are needed in the transferring unit 42. In other words, only 6 transistors are required to construct a new ATD circuit. Furthermore, only the first inverter 411 of the inputting unit 41 must consume DC current. In other words, the improved ATD circuit still consumes much less power dissipation than ever. In comparison with traditional ATD circuit according to FIG. 2., the transferring speed of the improved ATD circuit is almost the same as the conventional ATD circuit. In the conventional ATD circuit, it goes through 3 transistors in the testing unit 12; and in the improved ATD circuit, it also goes through 3 transistors from the happening of the address transition to the generating of the driving signal Sdrive. Both the conventional and improved ATD circuits will cost a similar time while they drive a chip from sleeping. Clearly, there is almost no difference while compared with the speed between the conventional ATD circuit and the improved ATD circuit.
Accompanying with the waveform in FIG. 6, the operations of the improved ATD circuit can be described more clearly. It is assumed that the initial state of Si, the point A, the point C and the point D are low, but the point B and the final output SoATD are high. When Si changes its state to high, the points A and C transit their states to high, the point B drops to low but the point D still remains on low. The delaying unit 44 delays the effect of Si in an operating period, and therefore, the state of point D still remains on low until the end of the operating period. The state of point B drops to low because the output of inverter 411 is low, and the point A is high because the output of inverter 412 is high. The transistors 421 is cut off but the transistor 422 is turn on by the low state of D (Sid), this also pulls the state of point C to high. The transistor 432 is turned on by the high state of point C, and the final output SoATD drops to low for waking up the chip from idleness to process the operations indicated by the varied address.
At the end of operating period, the point A keeps on high, the point B is still low, the state of point D turns to high but the point C drops to low. The transistor 432 is cut off by the low state of point C, and the state of the final output SoATD is then pulled to high. It also terminates the operations of the task indicating by the address. The chip then goes idleness to wait another address transition.
When Si returns to low, the state of point D still remains on high, the point A drops to low, but the point B and the point C turn to high to indicate happening of an address transition. At the end of the operating period, the state of point A remains on low, both the point C and the point D drop to low, but the state of point B is pulled to high. Transistor 432 is cut off again by the low state of point C terminating the operating period and the operations of the task indicated by the address. The chip then goes idleness to wait another address transition (that is, another task's coming).
Again, it is possible that several input pins of a chip switch their states simultaneously. However, the final output SoATD is still low even there are several driving signal Sdrive routing to the NOR plane but more transistors are turned on. In addition, the driving signal Sdrive can be amplified if necessary. FIG. 7 describes a simple example that a supplementing amplifier 71 constructed by 2 power amplifiers 711 and 712 is used to amplify the Sdrive. The logic state of check point E is the same as the point C. However, more transistors are used in constructing the brand new ATD circuit, and the detecting speed is longer than before.
FIG. 8 represents a flow chart summarizing the operations of the improved ATD circuit. First, each time when an input signal is arriving (step 81), an inverting phase signal based on the input signal is generated (step 82). A high level voltage (Logic 1) is then provided (step 83) to drive a chip from idleness (step 84). The input signal is delayed for beginning an operating period (step 85). The chip keeps wakefully in a regular time interval (operating period) to process the task indicating by the address (step 86) until the end of the operating period. A low voltage level (Logic 0) is then generated (step 87) to push the chip back to idleness (step 88). The chip will keep "sleeping" until next transition in the address.
US5424661 * Aug 12, 1993 Jun 13, 1995 Winbond Electronics North America Corp. Sensor circuit
US5493538 * Nov 14, 1994 Feb 20, 1996 Texas Instruments Incorporated Minimum pulse width address transition detection circuit
US5623218 * Jul 10, 1995 Apr 22, 1997 Lg Semicon Co., Ltd. Address transition signal detecting circuit
JP3740362A * Title not available
JP35820532A * Title not available
JP40110172A * Title not available
US5999425 * Mar 26, 1999 Dec 7, 1999 Cypress Semiconductor Corp. Charge pump architecture for integrated circuit
WO2001099278A3 * Jun 21, 2001 May 22, 2003 Infineon Technologies Corp Symmetric clock receiver for differential input signals
U.S. Classification 327/18, 327/31
International Classification H03K5/1534, G11C8/18, G11C29/18
Cooperative Classification H03K5/1534, G11C29/18, G11C8/18
European Classification G11C8/18, H03K5/1534, G11C29/18
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHAW, STEVE;REEL/FRAME:008160/0282