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P. 1UJIAN DIAGNOSTIKUJIAN DIAGNOSTIKRatings: (0)|Views: 38
|Likes: 0Published by cyPPPPMore info:Published by: cy on Apr 19, 2013Copyright:Attribution Non-commercialAvailability:Read on Scribd mobile: iPhone, iPad and Android.download as PDF, TXT or read online from ScribdFlag for inappropriate content|Add to collectionSee moreSee lesshttp://www.scribd.com/doc/136835721/UJIAN-DIAGNOSTIK11/24/2013pdftextoriginal You're Reading a Free Preview
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type: global

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text: Hilton Munich Airport is conveniently connected to the Munich Airport and located near a commuter train station. The fit and fly spa houses an indoor pool, a sauna, spa café, and steam bath. Wellness programs include Alegri treatments, and relaxing and therapeutic massage. A health club is also on site. Business amenities include conference spaces, a ballroom, and a business center, while valet parking is also offered. There are also 2 bars on site, and airport surroundings include a shopping mall and ATM banking machines. Indoor pool Poolside bar Spa services on site Spa tub Full-service spa Steam room Sauna Spa treatment room(s) Free newspapers in lobby Breakfast available (surcharge) Restaurant Bar/lounge Limo or Town Car service available Business center Porter/bellhop Multilingual staff 24-hour front desk Total number of rooms - 389 Safe-deposit box at front desk Number of floors - 4 Laundry facilities Dry cleaning/laundry service Coffee/tea in common areas Elevator/lift Conference space Free airport transportation Health club Computer station Free WiFi Luggage storage Garden Shopping on site Meeting rooms 30 Valet parking (surcharge) Terrace Conference space size (meters) - 2600 Conference center Self parking (surcharge) Free long-term parking Year Built 1994 Conference space size (feet) - 27986 Smoke-free property Concierge services Express check-out Show all hotel amenities

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Arsène Wenger wants new signings to lift Arsenal after hellish summer | Football | The Guardian
First published on Friday 9 September 2011 18.04 EDT

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9781854862709: Model Aircraft Aerodynamics - AbeBooks - Martin Simons: 1854862707
Book Description Book Condition: New. Bookseller Inventory # 20972912-n
Published by Special Interest Model Books 2014-11-28 (2014)
Book Description Special Interest Model Books 2014-11-28, 2014. Book Condition: New. Brand new book, sourced directly from publisher. Dispatch time is 24-48 hours from our warehouse. Book will be sent in robust, secure packaging to ensure it reaches you securely. Bookseller Inventory # NU-GRD-05214089
Published by Special Interest Model Books, United Kingdom (2015)
Book Description Special Interest Model Books, United Kingdom, 2015. Paperback. Book Condition: New. 5th Revised edition. Language: English . Brand New Book. This is the latest edition - fully revised and updated - of the standard textbook on aerodynamic theory, as applied to model flight. Everything is explained in a concise and practical form for those enthusiasts who appreciate that a better understanding of model behaviour is the sure path to greater success and enjoyment, whether just for fun or in competition. The revisions for this new edition reflect the significant developments in model aircraft during the last few years, and include brand new data: - The chapter on aerofoils has been rewritten to take account of the vast amount of testing carried out recently in the USA by the University of Illinois. - A brand new chapter explains the latest research into the flight of birds and insects and how it is applied to small drones and model-sized surveillance aircraft. - Older wind tunnel test reports all replaced with the latest trials and measurements. Bookseller Inventory # AAJ9781854862709
4. Model Aircraft Aerodynamics (Paperback)
Book Description Special Interest Model Books 2014-11-28, 2014. Book Condition: New. Brand new book, sourced directly from publisher. Dispatch time is 24-48 hours from our warehouse. Book will be sent in robust, secure packaging to ensure it reaches you securely. Bookseller Inventory # NU-MAR-00006799
Published by Special Interest Model Books (2015)
Book Description Special Interest Model Books, 2015. Book Condition: New. The standard textbook on aerodynamic theory, as applied to model flight. Num Pages: 270 pages, 50 clr photos, 200 clr illus. BIC Classification: TGMF1; WDHR. Category: (G) General (US: Trade). Dimension: 236 x 192 x 20. Weight in Grams: 888. . 2015. 5th Edition. Paperback. . . . . . Bookseller Inventory # V9781854862709
Book Description Special Interest Model Books. Book Condition: New. The standard textbook on aerodynamic theory, as applied to model flight. Num Pages: 270 pages, 50 clr photos, 200 clr illus. BIC Classification: TGMF1; WDHR. Category: (G) General (US: Trade). Dimension: 236 x 192 x 20. Weight in Grams: 888. . 2015. 5th Edition. Paperback. . . . . Books ship from the US and Ireland. Bookseller Inventory # V9781854862709
Book Description Special Interest Model Books, 2015. Book Condition: New. Bookseller Inventory # EH9781854862709
Book Description Special Interest Model Books, 2015. PAP. Book Condition: New. New Book. Shipped from UK in 4 to 14 days. Established seller since 2000. Bookseller Inventory # GB-9781854862709
Published by Special Interest Model Books 2014-10-27, Poole, Dorset, England (2014)
Book Description Special Interest Model Books 2014-10-27, Poole, Dorset, England, 2014. paperback. Book Condition: New. Bookseller Inventory # 9781854862709

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text: Translations French (89) Spanish (87) English (85) Russian (81) Italian (79) Polish (71) Dutch (69) Portuguese (67) Chinese (64) Swedish (57) Hungarian (56) Czech (55) Korean (53) Turkish (53) Brazilian Portuguese (51) License OSI-Approved Open Source (91) GNU General Public License version 2.0 (56) GNU General Public License version 3.0 (19) GNU Library or Lesser General Public License version 2.0 (8) MIT License (4) Mozilla Public License 1.1 (4) BSD License (3) Common Development and Distribution License (3) Academic Free License (2) Affero GNU Public License (2) Artistic License (2) GNU Library or Lesser General Public License version 3.0 (2) wxWindows Library Licence (2) zlib/libpng License (2) Apache License V2.0 (1) Attribution Assurance License (1) Creative Commons Attribution License (3) Creative Commons Attribution Non-Commercial License V2.0 (1) Creative Commons Attribution ShareAlike License V3.0 (1) Programming Language C (21) Java (8) Python (8) C# (6) JavaScript (6) Lua (5) PHP (5) Assembly (3) Unix Shell (3) Delphi/Kylix (2) PL/SQL (2) Perl (2) Tcl (2) VHDL/Verilog (2) Visual Basic .NET (2) Status 5 - Production/Stable (65) 6 - Mature (14) 4 - Beta (11) 3 - Alpha (6) 1 - Planning (4) 2 - Pre-Alpha (4) 7 - Inactive (2) OS Windows (85) Grouping and Descriptive Categories (76) All POSIX (32) 32-bit MS Windows (31) All 32-bit MS Windows (31) 64-bit MS Windows (30) OS Portable (20) All BSD Platforms (13) 32-bit MS Windows (6) OS Independent (2) Project is an Operating System Distribution (1) Project is an Operating System Kernel (1) Modern (66) Linux (37) Windows 7 (32) Vista (30) WinXP (30) OS X (26) Win2K (12) FreeBSD (8) Windows 8 (8) Solaris (4) NetBSD (2) OpenBSD (2) Linux (64) Mac (45) BSD (37) Freshness Recently updated (55) Collection Enterprise (5) Top Apps

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Unshakeable (Audiobook) by Tony Robbins | Audible.com
4.5 out of 5 stars 4.6 (6,072 ratings)
1,222 of 1,292 people found this review helpful
163 of 180 people found this review helpful
meh meh boring buy index funds blah blah not much
meh meh boring buy index funds blah blah not much really nothing here buy bitcoin get a lambo

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text:
NASA Exploration Experience Exhibit to Launch Visitors on 3D Journey Through the Cosmos Oct. 27, 2010 in Providence, R.I.
Oct 15, 2010, 05:27 ET
GREENBELT, Md., Oct. 15 /PRNewswire-USNewswire/ -- On Oct. 27, the "NASA Exploration Experience" will visit Providence, R.I., to propel visitors on a 3D journey across the solar system -- and to demonstrate the countless rewards made possible back on Earth by NASA's 50-plus years of science, discovery and technology development.
The traveling exhibit, which uses 3D imagery and the latest interactive video technology to immerse visitors in the experience, will be at the Nathanael Greene Middle School . The exhibit -- air-conditioned and wheelchair-accessible -- will be open from 8:30 a.m. to 2:30 p.m. on Oct. 27 and 28th for Greene Middle School students and from 10 a.m. to 5 p.m. on Oct 29 for the public.

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text:
Controls Systems Principal Engineer job - Johnson Controls - Milwaukee, WI | Indeed.com
Find similar jobs:Control System Principal Engineer jobs
This position will work as an integral part of the Smart Equipment Applications and Advanced Development team in Milwaukee, WI. This position will be expected to make an impact as both an individual contributor as well as a technical project lead. As an individual contributor, the engineer must possess multiple skills that include a working knowledge of control systems & control methodologies, HVAC/BAS systems and other applicable technologies so they can independently manage the design, implementation and testing for an individual feature. As a project technical lead, the engineer must be self motivated and able to interface directly with other technical leads as well as management to develop system wide solutions, drive a small group of technical resources, communicate status and/or concerns and deliver on team commitments.
Individual Contributor Duties and Responsibilities
Develop specifications for new control objects/methods
Develop and implement applications using high-level software tools (like Matlab/Simulink, Visual Studio C++, etc)
Test applications and control methods using simulation, emulation, field testing. Evaluate test data and generate test summaries.
Will report directly to engineering manager with dotted line responsibilities to project managers and technical leads.
Technical Lead Duties and Responsibilities
Work closely with marketing, project management and system engineers on system/application aspects of the product requirements, development and deployment.
Determine and negotiate requirements for a project, then plan and execute the work with the development team.
Responsible for surfacing and resolving technical issues during all phases of the project.
Promote adherence to good engineering practices and company product development processes.
Excellent at communicating up, down and across the organization. Able to represent the project team within engineering and can speak for the team technically.
Ensure all subsystem/feature designs "fit" together.
Lead technical people:
o Direct, coach and delegate to team members as appropriate
o Exhibit behaviors to engage, motivate and develop team members
o Drive accountability, encourage excellence, enable teamwork
o Provide technical support to team members
Will report directly to engineering manager with dotted line responsibilities to project managers and system engineering lead.
Occasional travel for training and to support other JCI facilities is required.
BS in Electrical, Mechanical or Controls Engineering (MS is a plus)
A minimum of five (5) years direct work experience in control systems and technical leadership (HVAC/BAS experience preferred)
Control System Principal Engineer jobs in Milwaukee, WI
Control System Principal Engineer salaries in Milwaukee, WI

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text:
Mavericks - Los Angeles Lakers Blog - ESPN Los Angeles
Los Angeles Lakers: Mavericks
Tags:Lakers Analysis, Andrew Bynum, Opinion, Kobe Bryant, Phil Jackson, Luke Walton, Jason Terry, NBA Playoffs, Game 4, Lakers, Mavericks, JJ Barea, postgame analysis
"The Lakers are currently third in the West, do you guys think there is a possibility the Lakers can move up to first place given the way the are now playing and hopefully will continue to play come playoff time?... Why not show how many games the Lakers would have to win and the Spurs and Mavs would need to lose to get the #1 spot along with who they may play?"
Tags:Lakers Analysis, playoffs, Lakers, Mavericks

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SAT to CKB: Flights from San Antonio to Clarksburg | Expedia
Cheap Flights from San Antonio to Clarksburg from
San Antonio to Clarksburg Flights
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Whether you’re flying for business or jet-setting on your personal time, you’ve come to the right place. Here at Expedia.com, we’ll pair you up with SAT to CKB flights that won’t make your bank account wince. Ready to temporarily leave behind San Antonio for new horizons? Browse through our cheap airfare, and filter by flight times and dates until you find just what you had in mind. From flights without layovers to ones that arrive early in the morning, you’ll come across plane tickets that suit your travel preferences. You can even bundle your flight to CKB with hotels and car rentals to score even bigger savings.All set to hit the clouds? Book your travel arrangements with us today and have left-over money to put toward your travel outings and adventures.


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The Confidence-Man: His Masquerade: The Authoritative Edition book by Herman Melville | 1 available editions | Alibris Books
The Confidence-Man: His Masquerade: The Authoritative Edition
Long considered Melville's strangest novel, The Confidence-Man is a comic allegory aimed at the optimism and materialism of mid-nineteenth century America. A shape-shifting Confidence-Man approaches passengers on a Mississippi River steamboat and, winning over his not-quite-innocent victims with his charms, urges each to trust in the cosmos, in nature, and even in human nature--with predictable results. In Melville's time the book was such a failure he abandoned fiction writing for twenty years; only in the twentieth ... Read More
Long considered Melville's strangest novel, The Confidence-Man is a comic allegory aimed at the optimism and materialism of mid-nineteenth century America. A shape-shifting Confidence-Man approaches passengers on a Mississippi River steamboat and, winning over his not-quite-innocent victims with his charms, urges each to trust in the cosmos, in nature, and even in human nature--with predictable results. In Melville's time the book was such a failure he abandoned fiction writing for twenty years; only in the twentieth century did critics celebrate its technical virtuosity, wit, comprehensive social vision, and wry skepticism. This scholarly edition includes a Historical Note offering a detailed account of the novel's composition, publication, reception, and subsequent critical history. In addition the editors present the twenty-six surviving manuscript leaves and scraps with full transcriptions and analytical commentary. This scholarly edition aims to present a text as close to the author's intention as surviving evidence permits. Based on collations of both editions publishing during Melville's lifetime, it incorporates 138 emendations made by the present editors. It is an Approved Text of the Center for Editions of American Authors (Modern Language Association of America). Read Less
ISBN 0810119684
ISBN-13 9780810119680
Alibris ID 14332626198
Alibris ID 14417996376
Alibris ID 14423143908
Alibris ID 13299460472
Alibris ID 14166398986
Alibris ID 13639877948
Very Good. 0810119684 Crisp, clean, unread book with some shelfwear and a remainder mark to one edge-NICE.
Alibris ID 14439483559
Good. 0810119684 Bumped and creased book with tears to the extremities, but not affecting the text block and a remainder mark to one edge-Good.
Alibris ID 10876863452
Fine. No dust jacket as issued. Beautiful, tight, unmarked copy. Trade paperback (US). Glued binding. 251 p. Audience: General/trade.
Alibris ID 14385240364
Alibris ID 13670129321

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text:
Organic Farming for the Developing ...
by mattsteven
Sustainable/Organic Farming Systems...
by guestbd5c98
djah744
Organic and Sustainable Farming in the Developing World Solar panels in the fields at Lange Twins Winery and Vineyards.
What is Organic Farming?

The production of crops without the use of synthetic/chemical inputs

No Genetically Modified Organisms

Utilizes biological activity in soil

Uses crop rotation, manure, compost, natural pest control (natural predators)

What is Sustainable Farming?

Farming that considers environmental health, yet is profitable while still considering social and economic equity.

Not necessarily organic, but often uses organic farming techniques

Fair treatment of farm laborers

Very similar to Ecological Agriculture

Ecological Farming ensures healthy farming and healthy food for today and tomorrow, by protecting soil, water and climate, promotes biodiversity, and does not contaminate the environment with chemical inputs or genetic engineering

Why use Organic & Sustainable Farming Techniques?

Water pollution (Nitrogen, Phosphorus, pathogens) from conventional agriculture cause health problems

Also an increase in algal bloom

Decreased soil erosion

Fewer pesticides in groundwater and on food

Fewer farm workers contaminated with pesticides

Why use Organic & Sustainable Farming Techniques?

Fewer antibiotic resistant strains of organisms from less antibiotic use in farm animals

Alleviate rural poverty in the developing world

Organic food production requires more hand labor

It is spread out over the growing season for continued employment

Less dependence on fossil fuels for all agriculture (animal feed & waste transport, vehicles for spraying, etc.)

What Are Some Organic/Sustainable Farming Techniques?

Build crop strength

Build soil strength

Be proactive with the crop and use ecological practices to prevent diseases, pests and weeds

Use reactive management – deal with problems as they arise

Mix animal and crop production as much as possible

Sell products locally whenever possible

Why is This Good for the Developing World?

Return to small-scale farming

Production is higher on small scale farms in both developed and developing world

Fewer farmers will be forced from their land and into slums to starve

Less reliance on imported fertilizers and pesticides

More nutritious food crops due to more diverse crops and higher soil nutrient content

Organics in U.S. - lessen the effects of global warming on the developing world.

What Are Some Roadblocks to Organic/Sustainable Agriculture?

Need markets for crops other than corn and soybeans

In some countries, soil building farm residues (manure, plant material) are used for fuel instead of building the soil

Little to no governmental subsides or assistance

Economics & Education (in U.S.)

References

Badgley, C., Moghtader, J., Quintero, E., Zakem, E., Chappell, J., Avilés- Vázquez, K., Samulon, A., Perfecto, I. (2007). Organic agriculture and the global food supply. Renewable Agriculture and Food Systems, 22 (2), 86-108.

Magdoff, F. (2007) . Ecological agriculture: Principles, practices, and constraints. Renewable Agriculture and Food Systems 22 (2), 109-117.

References

Rodriguez, J.M., Molnar, J.J., Fazio, R.A., Sydnor, E., Lowe, M.J., (2009) . Barriers to adoption of sustainable agriculture practices: Change agent perspectives. Renewable Agriculture and Food Systems, 24 , 60-71.

Tirado, R (2009). Defining Ecological Farming. Greenpeace Research Laboratories. Retrieved From: http://docs.google.com/gview? a=v&q=cache:DjC4xa3W_xkJ:www.greenpeace.to/publications/Defining-Ecological-Farming-2009.pdf+what+is+ecological+farming&hl=en&gl=us&sig=AFQjCNHFjLyKGY5diZ6l-UcCsqlBKyuW4g

Sustainable/Organic Farming Systems in the Developing World
guestbd5c98

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The callipyge mutation enhances the expression of coregulated imprinted genes in cis without affecting their imprinting status. - PubMed - NCBI
Format: AbstractFormatSummarySummary (text)AbstractAbstract (text)MEDLINEXMLPMID ListApplySend toChoose DestinationFileClipboardCollectionsE-mailOrderMy BibliographyCitation managerFormatSummary (text)Abstract (text)MEDLINEXMLPMID ListCSVCreate File1 selected item: 11279514FormatSummarySummary (text)AbstractAbstract (text)MEDLINEXMLPMID ListMeSH and Other DataE-mailSubjectAdditional textE-mailDidn't get the message? Find out why...Add to ClipboardAdd to CollectionsOrder articlesAdd to My BibliographyGenerate a file for use with external citation management software.Create File
See comment in PubMed Commons belowNat Genet. 2001 Apr;27(4):367-9.The callipyge mutation enhances the expression of coregulated imprinted genes in cis without affecting their imprinting status.Charlier C1, Segers K, Karim L, Shay T, Gyapay G, Cockett N, Georges M.Author information1Department of Genetics, Faculty of Veterinary Medicine, University of Liège (B43), Liège, Belgium.AbstractThe callipyge (CLPG) phenotype (from kappa(alpha)lambda(iota), "beautiful," and pi(iota)gamma(epsilon), "buttocks") described in sheep is an inherited muscular hypertrophy that is subject to an unusual parent-of-origin effect referred to as polar overdominance: only heterozygous individuals having inherited the CLPG mutation from their sire exhibit the muscular hypertrophy. The callipyge (clpg) locus was mapped to a chromosome segment of approximately 400 kb (refs. 2-4), which was shown to contain four genes (DLK1, GTL2, PEG11 and MEG8) that are preferentially expressed in skeletal muscle and subject to parental imprinting in this tissue. Here we describe the effect of the CLPG mutation on the expression of these four genes, and demonstrate that callipyge individuals have a unique expression profile that may account for the observed polar overdominance.PMID: 11279514 DOI: 10.1038/86856 [Indexed for MEDLINE] SharePublication types, MeSH terms, SubstancePublication typesResearch Support, Non-U.S. Gov'tResearch Support, U.S. Gov't, Non-P.H.S.MeSH termsAnimalsBase SequenceDNA PrimersGene Expression Regulation/genetics*Genomic Imprinting*Mutation*Reverse Transcriptase Polymerase Chain ReactionSheepSubstanceDNA PrimersLinkOut - more resourcesFull Text SourcesNature Publishing GroupOther Literature SourcesCOS Scholar UniverseMiscellaneousNCI CPTAC Assay PortalNCI CPTC Antibody Characterization ProgramNCI CPTC Antibody Characterization ProgramOMIA - Online Mendelian Inheritance in Animals: Data: Gene Expression - SciCrunchPubMed Commons home

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Patent US7939394 - Multiple-depth STI trenches in integrated circuit fabrication - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsMultiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of...http://www.google.com/patents/US7939394?utm_source=gb-gplus-sharePatent US7939394 - Multiple-depth STI trenches in integrated circuit fabricationAdvanced Patent SearchPublication numberUS7939394 B2Publication typeGrantApplication numberUS 12/057,643Publication dateMay 10, 2011Filing dateMar 28, 2008Priority dateSep 1, 2004Fee statusPaidAlso published asEP1794788A2, US7354812, US20060043455, US20080176378, WO2006028731A2, WO2006028731A3Publication number057643, 12057643, US 7939394 B2, US 7939394B2, US-B2-7939394, US7939394 B2, US7939394B2InventorsShubneesh Batra, Howard C. Kirsch, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen ChoOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (28), Referenced by (2), Classifications (8), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMultiple-depth STI trenches in integrated circuit fabrication
US 7939394 B2Abstract
Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
1. A method of fabricating trenches within an integrated circuit device, comprising:
forming a plurality of trenches in a substrate to a first depth, wherein the plurality of trenches includes first isolation trenches having a width less than some nominal value and second isolation trenches having a width greater than the nominal value;
forming a first dielectric layer overlying the substrate to fill the first isolation trenches and to leave open the second isolation trenches;
removing a portion of the first dielectric layer to expose portions of the underlying substrate at bottoms of the second isolation trenches while leaving the first isolation trenches filled;
removing exposed portions of the underlying substrate to extend the second isolation trenches to a second depth; and
forming a second dielectric layer overlying the substrate to fill the second isolation trenches;
wherein the first dielectric layer and the second dielectric layer comprise the same dielectric material.
2. The method of claim 1, wherein forming a plurality of trenches in a substrate to a first depth further comprises:
forming at least one sacrificial layer overlying the substrate;
forming a mask layer overlying the at least one sacrificial layer, thereby defining exposed portions of the at least one sacrificial layer; and
removing the exposed portions of the at least one sacrificial layer and underlying portions of the substrate.
removing a portion of the second dielectric layer to expose remaining portions of the at least one sacrificial layer;
removing the remaining portions of the at least one sacrificial layer to expose active areas of the substrate; and
fabricating the integrated circuit device on the active areas of the substrate.
4. The method of claim 2, wherein forming at least one sacrificial layer overlying the substrate comprises forming a first sacrificial layer overlying the substrate and a second sacrificial layer overlying the first sacrificial layer, the first and second sacrificial layers being of different materials.
5. The method of claim 1, wherein removing a portion of the first dielectric layer further comprises preferentially removing horizontal portions of the first dielectric layer.
6. The method of claim 5, wherein preferentially removing horizontal portions of the first dielectric layer leaves sidewalls of the second isolation trenches covered with the first dielectric layer.
7. The method of claim 6, wherein forming a second dielectric layer overlying the substrate to fill the second isolation trenches further comprises forming the second dielectric layer overlying the first dielectric layer covering the sidewalls of the second isolation trenches.
8. The method of claim 1, wherein the plurality of trenches further includes third trenches having a width sufficient to remain open after forming the second dielectric layer.
9. A method of fabricating isolation trenches of varying depth within an integrated circuit device, the method comprising:
defining areas of a substrate for future trenches, wherein a first area has a first width and a second area has a second width wider than the first width;
forming a first trench in the first area of the substrate and a second trench in the second area of the substrate;
forming a first dielectric fill layer overlying the substrate to fill the first trench and to leave the second trench open;
removing a portion of the first dielectric fill layer to expose a portion of the substrate at a bottom of the second trench;
extending the second trench into the exposed portion of the substrate; and
forming a second dielectric fill layer overlying the substrate to fill the second trench;
wherein the first dielectric fill layer and the second dielectric fill layer comprise the same dielectric material.
10. The method of claim 9, wherein defining areas of the substrate for future trenches further comprises:
forming at least one sacrificial layer overlying the substrate; and
forming a mask layer overlying the at least one sacrificial layer to expose areas of the at least one sacrificial layer.
11. The method of claim 10, wherein forming at least one sacrificial layer further comprises forming at least one sacrificial layer comprising a material different than a material of the first dielectric fill layer.
12. The method of claim 10, wherein forming a mask layer further comprises forming and patterning a photoresist layer.
13. The method of claim 9, wherein forming a first trench in the first area of the substrate and forming a second trench in the second area of the substrate occur concurrently.
14. The method of claim 13, wherein the first trench and the second trench have substantially the same depth as initially formed.
15. The method of claim 9, wherein removing a portion of the first dielectric fill layer further comprises anisotropically removing a portion of the first dielectric layer.
defining a third area of the substrate for future trenches, wherein the third area, has a third width wider than the second width.
removing a second portion of the first dielectric fill layer from sidewalls of the second trench prior to forming the second dielectric fill layer overlying the substrate to fill the second trench.
18. A method of fabricating trenches within an integrated circuit device, comprising:
forming a plurality of trenches in a substrate to a first depth, wherein the plurality of trenches includes first trenches having a width less than some first value, second trenches having a width greater than the first value and less than a second value, and third trenches having a width greater than the second value;
forming a first dielectric layer overlying the substrate to fill the first trenches and to leave open the second and third trenches;
removing a portion of the first dielectric layer to expose portions of the underlying substrate at bottoms of the second and third trenches while leaving the first trenches filled;
removing exposed portions of the underlying substrate to extend the second and third trenches to a second depth;
forming a second dielectric layer overlying the substrate to fill the second trenches and to leave open the third trenches;
removing a portion of the second dielectric layer to expose portions of the underlying substrate at the bottoms of the third trenches while leaving the first and second trenches filled;
removing exposed portions of the underlying substrate to extend the third trenches to a third depth; and
forming a third dielectric layer overlying the substrate to fill the third trenches;
19. The method of claim 18, wherein forming a plurality of trenches in a substrate to a first depth further comprises:
removing a portion of the third dielectric layer to expose remaining portions of the at least one sacrificial layer;
21. The method of claim 18, wherein removing a portion of the first dielectric layer further comprises anisotropically removing a portion of the first dielectric layer.
This application is a divisional of U.S. application Ser. No. 10/931,946, titled “MULTIPLE-DEPTH STI TRENCES IN INTEGRATED CIRCUIT FABRICATION,” filed Sep. 1, 2004, now U.S. Pat. No. 7,354,812 which is commonly assigned and incorporated herein by reference.
The present invention relates generally to integrated circuit devices and, in particular, to the formation of multiple-depth STI (shallow trench isolation) trenches in an integrated circuit device.
There are several different types of memory. One type is DRAM (dynamic random access memory). This is typically used as main memory in a computer environment. A DRAM memory cell is commonly configured as an access transistor coupled to a capacitor. A charge stored on the capacitor defines a data value of the memory cell. DRAM is generally volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in DRAM is lost. However, it remains popular as it provides high memory density and quick access times.
Another type of memory is a non-volatile memory known as Flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
Memory device fabricators, as well as other integrated circuit device fabricators, are continuously seeking to reduce the size of the devices. Smaller devices facilitate higher productivity and reduced power consumption. However, as device sizes become smaller, isolation within the devices becomes more critical. This is especially true in flash memory architecture because of the high voltages utilized on-chip.
Shallow trench isolation (STI) has been commonly used in semiconductor fabrication to provide field isolation. As devices are scaled ever smaller, and trenches become narrower, dielectric filling of the trenches becomes increasingly difficult. As a result, trench depth is often reduced to lower the aspect ratio of the trench, thereby making it easier to fill. However, field isolation between active areas in the periphery often requires that a certain trench depth be maintained.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate methods of providing isolation within a semiconductor device.
FIGS. 1A-1G are cross-sectional views of a portion of an integrated circuit during various stages of fabrication in accordance with an embodiment of the invention.
FIG. 1H is a cross-sectional view of a portion of an integrated circuit illustrating use of multiple-depth isolation trenches in accordance with an embodiment of the invention.
FIG. 2A is a block schematic of a portion of a memory array and peripheral circuitry in accordance with an embodiment of the invention.
FIG. 2B is a schematic of a portion of a non-volatile memory array in accordance with a further embodiment of the invention.
FIG. 3 is a functional block diagram of a basic memory device in accordance with an embodiment of the invention coupled to a processor.
FIGS. 4A-4J are cross-sectional views of a portion of an integrated circuit during various stages of fabrication in accordance with another embodiment of the invention.
FIGS. 1A-1G generally depict a method of forming a portion of an integrated circuit in accordance with an embodiment of the invention. While the process will be described with specific reference to a semiconductor memory device, it will be apparent that the methods described herein are suitable for a variety of integrated circuit devices. FIG. 1A depicts a portion of the memory array after several processing steps have occurred. In general, FIG. 1A depicts a semiconductor substrate 105 for use in fabricating a semiconductor device. For one embodiment, substrate 105 is a P-type monocrystalline silicon substrate. One or more sacrificial layers, such as first sacrificial layer 110 and second sacrificial layer 115 are formed overlying the substrate 105. These layers will be used to protect portions of the underlying substrate 105 during formation of trenches. For one embodiment, the first sacrificial layer 110 is silicon oxide (SiO2) and the second sacrificial layer 115 is silicon nitride (Si3N4). For such an embodiment, the first sacrificial layer 110 might be formed by thermal oxidation of the silicon substrate 105 while the second sacrificial layer 115 might be formed by blanket deposition of a silicon nitride layer. Further guidance on selection of materials for the sacrificial layers will be provided with reference to subsequent processing.
A mask layer 120 is formed overlying the second sacrificial layer 115. The mask layer 120 defines areas for formation of trenches, i.e., the exposed areas of second sacrificial layer 115. As one example, the mask layer 120 is a patterned photoresist layer. Masking in semiconductor fabrication is well understood and will not be detailed herein.
In FIG. 1B, first isolation trenches 125 and second isolation trenches 130 are formed in the substrate 105. For one embodiment, the trenches 125 and 130 are formed using a plasma etch. However, any anisotropic etch may be utilized to remove exposed portions of the sacrificial layers 110 and 115 and portions of the underlying substrate 105.
The trenches 125 and 130 are formed to substantially the same depth as they are formed concurrently. However, the first isolation trenches 125 are narrower than the second isolation trenches 130. In application, the first isolation trenches 125 might be used where narrow spacing is preferred and where field isolation is less demanding. As one example, this may include an array portion of a semiconductor memory device. Also, in application, the second isolation trenches 130 might be used where field isolation is more demanding and where spacing is less critical. As one example, this may include a periphery portion of the semiconductor memory device.
In FIG. 1C, a first dielectric fill layer 135 is formed. The first dielectric fill layer can include any dielectric material. Some specific examples include silicon oxides (SiO or SiO2) using high-density plasma (HDP) processing or chemical-vapor deposition (CVD) processing to blanket deposit the first dielectric fill layer 135. The first dielectric fill layer 135 should be chosen such that a subsequent removal process is selective to the dielectric material of the first dielectric fill layer 135 over the uppermost sacrificial layer, i.e., second sacrificial layer 115 in this example. In other words, the first dielectric fill layer 135 should be of a different material than the second sacrificial layer 115 such that portions of the first dielectric fill layer 135 can be removed without significantly affecting the second sacrificial layer 115.
The first dielectric fill layer 135 should be deposited to a degree that closes off the narrower first isolation trenches 125 while leaving the second isolation trenches 130 open. It is noted that the first isolation trenches 125 do not have to be uniform in width, but simply must be of a width that will be filled upon formation of the first dielectric fill layer 135. Similarly, the second isolation trenches 130 do not have to be uniform in width, but simply must be of a width that will remain open after formation of the first dielectric fill layer 135. As such, the first isolation trenches 125 are those having a width less than some nominal value while the second isolation trenches 130 are those having a width above that nominal value.
In FIG. 1D, portions of the first dielectric fill layer 135 are removed to expose portions of the substrate 105 in the bottoms of the second isolation trenches 130. By using an etch-back process or an anisotropic removal process, horizontal portions of the first dielectric fill layer 135 may be preferentially removed, thus leaving sidewalls of the isolation trenches 130 covered. This will allow the exposure of portions of the substrate 105 without substantially removing dielectric material from the first isolation trenches 125.
In FIG. 1E, second isolation trenches 130 are deepened. This result can be obtained by using a removal process selective to the material of the substrate 105 over the materials of the second sacrificial layer 115 and the first dielectric fill layer 135. For example, an anisotropic silicon etch can be used to remove exposed portions of a silicon substrate 105 without substantially affecting the exposed portions of the first dielectric fill layer 135 or the second sacrificial layer 115. Following the deepening of the second isolation trenches 130, portions of the first dielectric fill layer 135 on sidewalls of the second isolation trenches 130 may optionally be removed, such as by a wet etch or other removal process.
In FIG. 1F, a second dielectric fill layer 140 is formed. To obtain the structure of FIG. 1F, portions of the second dielectric fill layer 140 have been removed, such as by chemical-mechanical planarization (CMP) using the second sacrificial layer 115 as a stopping layer.
In FIG. 1G, the sacrificial layers 110 and 115 may then be removed, and formation of the integrated circuit device can proceed on active areas 145 and 150 as is well understood in the art of semiconductor fabrication. For example, portions of the integrated circuit device having higher requirements for isolation may be formed on active areas 150 that are isolated from adjacent active areas by a second isolation trench 130 while portions of the integrated circuit device having lower requirements for isolation may be formed on active areas 145 that are isolated from adjacent active areas by a first isolation trench 125. As a specific example, memory cells could be formed on active areas 145 between first isolation trenches 125 while access and control circuitry could be formed on active areas 150 between, or isolated from the array of memory cells by, second isolation trenches 130.
Although the foregoing example provided just two depths for the isolation trenches, it is noted that more than two depths can be formed using methods in accordance with the invention. For example, first isolation trenches could be formed having a first width that will close up upon formation of the first dielectric fill layer, second isolation trenches could be formed having a second width that will close up upon formation of the second dielectric fill layer, and third isolation trenches could be formed having a third width that will remain open after formation of the second dielectric fill layer. By performing processing similar to that described with reference to FIGS. 1E-1F, it will become apparent that a third isolation trench depth could be formed for the third isolation trenches. Through the use of varying trench widths, any number of trench depths could be produced. However, deeper trenches will correspondingly be wider when formed in this manner.
FIGS. 4A-4J are cross-sectional views depicting a processing method, similar to that described with reference to FIGS. 1A-1G, of forming a portion of an integrated circuit having the third isolation trenches. Common numbering is used in FIGS. 4A-4J and FIGS. 1A-1G to denote common elements. Such commonly numbered elements are described above in conjunction with FIGS. 1A-1G. The structure of FIG. 4A is similar to the structure of FIG. 1A, with the exception of the substrate 105 having a third area for future third isolation trenches, and is substantially formed as described above in conjunction with FIG. 1A.
A plurality of trenches is formed in FIG. 4B to a first depth in substrate 105. The plurality of trenches includes first trenches 125 having a width less than some first value, second trenches 130 having a width greater than the first value and less than a second value, and third trenches 430 having a width greater than the second value. A first dielectric layer 135 is formed overlying the substrate 105 to fill the first trenches 125 and to leave open the second trenches 130 and the third trenches 430, as shown in FIG. 4C. A portion of the first dielectric layer 135 is removed in FIG. 4D to expose portions of the underlying substrate 105 at bottoms of the second trenches 130 and of the third trenches 430 while leaving the first trenches 125 filled. Exposed portions of the underlying substrate 105 are removed to extend the second trenches 130 and the third trenches 430 to a second depth in FIG. 4E.
In FIG. 4F, a second dielectric layer 140 is formed overlying the substrate 105 to fill the second trenches 130 and to leave open the third trenches 430. A portion of the second dielectric layer 140 is removed in FIG. 4G to expose portions of the underlying substrate 105 at the bottoms of the third trenches 430 while leaving the first trenches 125 and the second trenches 130 filled. Exposed portions of the underlying substrate 105 are removed to extend the third trenches 430 to a third depth in FIG. 4H.
A third dielectric layer 440 is formed overlying the substrate to fill the third trenches 430. A portion of the third dielectric layer 440 is removed to expose portions of sacrificial layer 115 to obtain the structure of FIG. 4I. In FIG. 4J, the sacrificial layers 110 and 115 are removed to expose active areas 145, 150, and 450 of the substrate, as discussed above in conjunction with FIG. 1G. The integrated circuit device is then formed on active areas 145, 150, and 450, as is well understood in the art of semiconductor fabrication.
FIG. 1H is a cross-sectional view of a portion of an integrated circuit illustrating use of multiple-depth isolation trenches in accordance with an embodiment of the invention. As shown in FIG. 1H, the integrated circuit is formed in a substrate 105. For the following example, it will be assumed that the substrate 105 is a P-type substrate. However, the invention is not limited to a specific conductivity type. In this example, component devices of a first type, such as p-type field effect transistors (pFETs) 209 a and 209 b are formed in an n-well 217. The pFETs 209 a and 209 b have source/drain regions 213 having p+ conductivity. The pFETs 209 a and 209 b are isolated from one another by one or more first isolation regions 125. To further this example, component devices having a second conductivity type, such as n-type field effect transistors (nFETs) 211 a and 211 b are formed in an isolated p-well 219. The nFETs 211 a and 211 b have source/drain regions 215 having n+ conductivity. The nFETs 211 a and 211 b are isolated from one another, and any adjacent nFETs in p-well 219, by one or more first isolation regions 125. The p-well 219 is isolated from the bulk of the P-type substrate using a deep N+ region 221 and one or more of the second isolation regions 130. Similarly, the p-well 219 is isolated from any adjacent n-wells, such as n-well 217, by one or more of the second isolation regions 130. As described with reference to FIGS. 1A-1G, the second isolation regions 130 are deeper than the first isolation regions 125.
It is noted that the isolation regions 125 and 130 may be formed as open trenches (trenches having two or more ends), closed trenches (trenches forming a closed loop of regular or irregular shape) or some combination of the two. For example, isolation regions 130 in FIG. 1H could represent a closed polygon, completely enclosing the N+ region 221 while isolation regions 125 could represent straight lines between rows of FETs 209 and 211. It will be apparent that multiple trench depths can be used in a variety of ways and that the foregoing example illustrates just one possible configuration. Similarly, other well structures could be used in conjunction with the isolation techniques described herein, such as triple well structures well known in the art. By forming isolation trenches in accordance with embodiments of the inventions, performance benefits, e.g., sensitivity, noise rejection, low voltage capability, etc., can be facilitated without the disadvantages of typical large inter-well design rule spacing.
FIG. 2A is a block diagram of a portion of a memory array 200A and peripheral circuitry 207 as a portion of a memory device in accordance with one embodiment of the invention. The memory array 200A can represent a volatile or nonvolatile memory array and is provided to show generally how multiple-depth isolation trenches may be used in a typical integrated circuit device. The memory array 200A includes memory cells 201 arranged generally in row and column fashion. As discussed, field isolation needs may vary within an integrated circuit device. For the example memory array 200A, shallow trenches 203 may be used to isolate adjacent rows or columns of memory cells 201 while deeper trenches 205 may be used to isolate the array of memory cells 201 from access and control circuitry 207.
FIG. 2B is a schematic of a portion of a nonvolatile memory array 200B as a portion of a memory device in accordance with one embodiment of the invention. The detail of memory array 200B is provided to better understand the various embodiments of the invention. The memory array 200B includes at least two types of isolation trenches formed in accordance with an embodiment of the invention. A first type of isolation trench may, for example, isolate adjacent rows or columns of memory cells while a second type of isolation trench may be located at a periphery of the array for isolation of the array from surrounding circuitry. A memory array represents just one application for use of the multiple-depth isolation trenches.
The layout of FIG. 2B corresponds to one example of a NOR flash architecture. However, other types of memory arrays can benefit from embodiments of the invention. As one example, word lines, drain contacts and source interconnects can be fabricated in accordance with the invention for NAND flash architectures as well, although only one drain contact is required per string and only one source interconnect is required per block. Accordingly, the invention is not limited to the specific layout described with reference to FIG. 2B.
As shown in FIG. 2B, the memory block 200B includes word lines 202 and intersecting local bit lines 204. For ease of addressing in the digital environment, the number of word lines 202 and the number of bit lines 204 are each some power of two, e.g., 256 word lines 202 by 4,096 bit lines 204. The local bit lines 204 may be selectively coupled to global bit lines (not shown) for coupling to sense amplifiers (not shown in FIG. 2B).
Floating-gate transistors 206 are located at each intersection of a word line 202 and a local bit line 204. The floating-gate transistors 206 represent the non-volatile memory cells for storage of data. Typical construction of such floating-gate transistors 206 include a source 208 and a drain 210 constructed from an n+-type material of high impurity concentration formed in a P-type semiconductor substrate of low impurity concentration, a channel region formed between the source and drain, a floating gate 212, and a control gate 214. Floating gate 212 is isolated from the channel region by a tunneling dielectric and from the control gate 214 by an intergate dielectric. Floating-gate transistors 206 having their control gates 214 coupled to a word line 202 typically share a common source 208 depicted as array source interconnect 216. As shown in FIG. 2B, floating-gate transistors 206 coupled to two adjacent word lines 202 may share the same array source interconnect 216. Floating-gate transistors 206 have their drains coupled to a local bit line 204. A column of the floating-gate transistors 206 are those transistors commonly coupled to a given local bit line 204. A row of the floating-gate transistors 206 are those transistors commonly coupled to a given word line 202.
FIG. 3 is a block diagram of a memory device 300 coupled to a controller or processor 150 in accordance with an embodiment of the invention. The memory type of the memory device 300 is not dependent upon the invention and can include a variety of volatile or non-volatile memory types. Memory device 300 includes a memory array 302 having a plurality of memory cells arranged in row and column fashion. The memory device 300 includes first isolation trenches, such as shallow isolation trenches, within the memory array 302 and second isolation trenches, such as deeper isolation trenches, at a periphery of the memory array 302 and formed in accordance with an embodiment of the invention.
Memory array 302 can be accessed using externally provided location addresses received by an address register 312 via address signal connections 330. The address signals are decoded, and one or more target memory cells are selected in response to the decoded address signals, using the access circuitry 314 that includes decode and select circuitry.
Data is input and output through an I/O circuit 322 via data connections 332. I/O circuit 322 includes data output registers, output drivers, and output buffers. Command execution logic 324 is provided to control the basic operations of the memory device 300 in response to control signals received via control signal connections 328. A state machine 326 may also be provided to control specific operations performed on the memory array 302 and the memory cells. The command execution logic 324 and/or state machine 326 can be generally referred to as control circuitry 327 to control read, write, erase, and other memory operations. The data connections 332 are typically used for bidirectional data communication. The memory can be coupled to an external processor 150 for operation as part of an electronic system. An example of a processor 150 includes a memory controller in a personal computer.
It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of FIG. 3 has been simplified to help focus on the invention. It will further be understood that the above description of a memory device is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a typical memory device.
Method and apparatus have been described to facilitate formation of multiple trench depths within an integrated circuit device by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
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Further to this, the property also boasts a single garage and a rear car parking space
The property itself is extremely well positioned, being just slightly north of the town of Chesterfield, approximately a 10 minute drive. As well as that, the M1 motorway is 5 minutes away, giving great access to the rest of South Yorkshire and beyond
The property boasts an exceptional ease to all the local amenities that Brimington and Hollingwood are able to offer, including an excellent selection of shops, supermarkets, restaurants and pubs.
Because we are offering this property on a wide variation of different schemes and options, we believe a property of this quality will not hang round for long, so to avoid any potential disappointment, we would recommend a viewing
Please note, this property will be let as Un-furnished
This large open plan kitchen, which is very spacious in its design, is equally well quipped and aesthetically pleasing on the eye. The very good quality tiled flooring is well matched up to the dark pine wall and base units, along with the solid grey worktops. Also features a freestanding Electric Cooker, white sink and plumbing for a dishwasher/washing machine.
The very pleasant living room is extremely well decorated throughout, with an excellent selection of light brown carpets and cream walls. The feature of this room is the decorative marble fire place and it immediately draws any potential tenant's eye.
This ground floor double bedroom is of a great size and offers a great space. Could be used for a variety of uses if not wanted as a bedroom.
This excellent sized Master Bedroom is well decorated in neutral colours with light brown carpets and a neutral decor throughout.
Currently being used as a young child's bedroom, it still presents and excellent amount of space. Easily able to accommodate a double bed and a host of bedroom furniture, perfect spare bedroom for visiting guests and family. There is also a distinct possibility of adding a partition wall to add a further fourth bedroom should it be so desired.
The slightly smaller fourth bedroom is still able to accommodate a single bed, but would be easily able to turn into a small office, study or something similar.
The long utility room provides a good amount of storage and further plumbing for a washing machine.
This excellent sized bathroom is extremely luxurious in its feel. The stone marble bath is separate to the glass shower cubicle. There is a large amount of storage throughout with a wide selection of pine cupboards, well matched with the white WC and pedestal sink. The Baxi boiler is located in one of the storage cupboards - and its approximately 7/8 years old.
The rear exterior is one of the jewels of this properties crown and its absolutely perfect for hosting family and friends gatherings in the summer months. The patio large patio is well looked after and there is a large garden area. Behind the enclosing fence, there is a single garage and parking space for 1 car.
Please Note: A reduced deposit/bond of £350 is required, providing you can provide a suitable Guarantor. Otherwise a deposit/bond of £1200 will be needed for this property.
Marketed by EweMove Sales & Lettings (Sheffield) - Property Reference 8971
To view this media, please visit the on-line version of this page at www.rightmove.co.uk/property-to-rent/property-45389802.html
Property reference 8971. The information displayed about this property comprises a property advertisement. Rightmove.co.uk makes no warranty as to the accuracy or completeness of the advertisement or any linked or associated information, and Rightmove has no control over the content. This property advertisement does not constitute property particulars. The information is provided and maintained by EweMove, UK.

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Maryland DirectoriesEdit This Page	From FamilySearch Wiki	Revision as of 19:38, 9 January 2009 by HealeyJE (Talk | contribs)
Jump to:	navigation	, search	Directories are alphabetical lists of names and addresses. They are usually published yearly and may include an individual's name, address, occupation and spouse's name. Directories may include maps, addresses of churches, cemeteries, courthouses and businesses. Local public and university libraries, historical and genealogical socities and state archives generally have historic directories. The Library of Congress has the largest collection of city and county directories.

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Amazon.co.uk: supernel's review of Pin-ups. Gil Elvgren - 2014 Wall Calendar ...
great calendar, 17 Dec. 2013
By supernel
Top Reviewer Ranking: 1,840,792


text:
Speech Recognition - CodeProject 12,761,424 members (34,612 online)
Atul Khanduri26-Aug-12 21:43 This will help you.... Last Visit: 31-Dec-99 19:00 Last Update: 26-Feb-17 14:34Refresh1

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Gerhard Richter : images of an era (Book, 2011) [WorldCat.org]
I thought you might be interested in this item at http://www.worldcat.org/oclc/711050729 Title: Gerhard Richter : images of an era Author: Gerhard Richter; Uwe M Schneede; Hubertus Butin; Dietmar Elger; Dietmar Rübel; Ortrud Westheider; Michael Philipp; B H D Buchloh; Russell Stockman; Ingrid Schädtler; Bucerius Kunst Forum, Publisher: Munich : London : New York ; Paris : Hirmer Verlag ; Heni Publishing ; Marian Goodman Gallery, [2011] ©2011 ISBN/ISSN: 9783777450018 3777450014 OCLC:711050729
Gerhard Richter; Uwe M Schneede; Hubertus Butin; Dietmar Elger; Dietmar Rübel; All authors
Munich : Hirmer Verlag ; London : Heni Publishing ; New York ; Paris : Marian Goodman Gallery, [2011] ©2011
This volume presents and describes 50 of the artist's works with essays by leading Richter experts. It also includes personal testimonials in previously unpublished letters as well as a conversation between Gerhard Richter and Richter expert Uwe Schneede. This book provides new insight into the complexity of Richter's imagery in which banality and evil confront one another: the dreams and aspirations of the times, fast cars and new travel possibilities; personal memories; the oppressive past; contemporary politics; and both trivial and meaningful everyday objects. The cycle 18 Oktober 1977 (1988), which deals with the death of members of the Red Army Faction ('Baader-Meinhof gang') plays an important role in our understanding of the evocative power of these pictures from the 1960s. Richter's intense preoccupation with this event concludes this group of paintings from photographs. This cycle, which was loaned to the Bucerius Kunst forum in Hamburg by the New York Museum of Modern Art, has led to a new interpretation and positioning of Richter's work. Read more...
Gerhard Richter; Uwe M Schneede; Hubertus Butin; Dietmar Elger; Dietmar Rübel; Ortrud Westheider; Michael Philipp; B H D Buchloh; Russell Stockman; Ingrid Schädtler; Bucerius Kunst Forum,
Find more information about: Gerhard Richter Uwe M Schneede Hubertus Butin Dietmar Elger Dietmar Rübel Ortrud Westheider Michael Philipp B H D Buchloh Russell Stockman Ingrid Schädtler
9783777450018 3777450014
Edited by Ortrud Westheider and Michael Philipp ; translators: Benjamin H. D. Buchloh, Russell Stockman, and Ingrid SchaÌdtler ; curator: Michael Philipp.
Preface / Ortrud Westheider --
Introduction / Uwe M. Schneede --
Gerhard Richter's images of an era / Uwe M. Schneede --
"It is as it is": Gerhard Richter's letters to two artist friends with an introduction by Dietmar Elger and annotations by Benjamin H.D. Buchloh --
The painted photo: Gerhard Richter in his atelier / Dietmar Elger --
Atelier photos 1965-66 / Uwe M. Schneede --
Hero worship and the rejection of ideology: Gerhard Richter's 1966 film Volker Bradke / Hubertus Butin --
Cut and paint: pictures from the popular press and the photo painting if the 1960s / Dietmar Rübel --
On Pop, East and West, and someof the picture sources --
Uwe M. Schneede in conversation with Gerhard Richter --
Paintings 1962-1967 --
An idea pursued to the point of death: the cycle October 18, 1977 / Ortrud Westheider --
Annotated catalog of the exhibited works / Uwe M. Schneede.
Volker Bradke.
exhibition and catalog, Uwe M. Schneede ; with contributions by Hubertus Butin, Dietmar Elger, Dietmar Rübel, Uwe M. Schneede, and Ortrud Westheider.
Practically no other artist today is as internationally acclaimed as Gerhard Richter. After relocating to Western Germany in the early 1960s, he began to interpret his new environment visually by creating large paintings which were based on photographs. This book deals with his life and work. Read more...
Add tags for "Gerhard Richter : images of an era". Be the first.
Richter, Gerhard, -- 1932- -- Volker Bradke -- Exhibitions.
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schema:description "This volume presents and describes 50 of the artist's works with essays by leading Richter experts. It also includes personal testimonials in previously unpublished letters as well as a conversation between Gerhard Richter and Richter expert Uwe Schneede. This book provides new insight into the complexity of Richter's imagery in which banality and evil confront one another: the dreams and aspirations of the times, fast cars and new travel possibilities; personal memories; the oppressive past; contemporary politics; and both trivial and meaningful everyday objects. The cycle 18 Oktober 1977 (1988), which deals with the death of members of the Red Army Faction ('Baader-Meinhof gang') plays an important role in our understanding of the evocative power of these pictures from the 1960s. Richter's intense preoccupation with this event concludes this group of paintings from photographs. This cycle, which was loaned to the Bucerius Kunst forum in Hamburg by the New York Museum of Modern Art, has led to a new interpretation and positioning of Richter's work."@en ;
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Gerhard Richter : images of an era/Gerhard Richter; Uwe M Schneede; Hubertus Butin; Dietmar Elger; Dietmar Rübel; Ortrud Westheider; Michael Philipp; B H D Buchloh; Russell Stockman; Ingrid Schädtler; Bucerius Kunst Forum,; Munich : Hirmer Verlag ; London : Heni Publishing ; New York ; Paris : Marian Goodman Gallery, [2011] ©2011

value: This website is a union catalog that itemizes the collections of 15,637 libraries in 107 countries that participate in the OCLC global cooperative. It is operated by OCLC, Inc.


text:
Earl Leaverton (1921-1989) - Find A Grave Memorial
Earl Leaverton
Birth 19 Jun 1921
Death 24 Feb 1989
Plot Garden of the Holy Family ~ Section 27
Memorial ID 18541902
Eileen Deloris Casabon Leaverton*
Find A Grave Memorial 18541902
Find A Grave, database and images (https://www.findagrave.com : accessed ), memorial page for Earl Leaverton (19 Jun 1921–24 Feb 1989), Find A Grave Memorial no. 18541902, citing Resthaven Gardens Cemetery, Oklahoma City, Cleveland County, Oklahoma, USA ; Maintained by Phil & Donna (Stricklan) Whitaker (contributor 4308835) .
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We have just returned from a fantastic stay with... - Review of Leim Siar Bed and Breakfast - TripAdvisor
We have just returned from a fantastic stay with... - Review of Leim Siar Bed and Breakfast
MFAHEY9
We have just returned from a fantastic stay with Hannah in Leim Siar. She went out of her way to help us settle in. Very welcome cups of tea any time of day! We had a very excited 7 year old with us when we arrived and she took him off on a tour of the B&B to help him settle in. Bags of bricks dispensed to play with and a trip to the polytunnel to pick peas during our stay too! Very rural setting, lovely if you want a quiet break.
Ask MFAHEY9 about Leim Siar Bed and Breakfast
Thank MFAHEY9
All reviews b b scones blacksod bay irish language belmullet peninsula beautiful location hearty breakfast fresh fruit salad local life local butcher eat dinner weather forecast real ireland black pudding irish hospitality wonderful host two nights
emmabh1970
Hidden Gem in Black Sod Bay
On arrival we were welcomed by Hannah owner of Liam Siar and were very pleased with our room. The family room was very spacious with a en-suite shower room and extremely clean with fresh clean linen and towels. The following morning after a very good sleep we were offered a range of cereal , fruit , yogurt , juices, bread and fresh baked scones for breakfast. Also there was a choice of having a tasty full cooked irish breakfast .
I felt really at home at this B&B and nothing was too much trouble for our hosts Hannah and Gerry. They were able to recommend local restaurants/ pubs for our evening meals and were great for all local information.We ate at the local golf course and would fully recommend it the food was superb.
The B&B is located at Black Sod Bay which is a beautiful part of county mayo very unspoilt .Our girls loved the 30 seconds walk to the local beach each morning to watch the boats and to play on the sand.
Hospitality was even extended to my husband's family when they visited us. There is plenty of parking with easy access to the property.
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1 Thank emmabh1970
Darren036
Lig mé mo scíth i Léim Siar!
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Ask Albarin0 about Leim Siar Bed and Breakfast
People still amaze you!!!
The first thing we need to mention is that the people who run this B&B have to be the nicest people you will ever meet.
We stayed in Liam SIar just before the Christmas. From the minute i rang Hannah everything was sorted. Hannah and husband Jerry did everything they possibly could to make our stay one we would never forget. We got engaged that evening we arived in Blacksod and it has to be said that only for Hannah, Gerry and their friends Vincent and Dorin, who kindly showed us around the lighthouse, the evening could not have gone any better. These people made us feel so welcomed and comfortable, it made the evening all the more special. Hannah had also arranged for us to have food in what i can only say is the best kept secret of the west of Ireland. We had dinner that evening in the Ciarn restaurant in the golf club. Once again, the people who owned this restaurant were welcoming and so friendly. The food there has to be mentioned and has to be one of the finest feeds i have had in years. We will definitely be going back. After the food it was down to the local watering hole of teach John Joe, where the craic was in full swing.
The next morning we woke to the wild scenery of the west atlantic coast. After a short walk to the pier and lighthouse to clear the heads, we sat down to a lovely traditional irish breakfast. Once again, Hannah and Gerry had pulled out all the stops and had some personal momentos for us to take away with us. These people and their friends/neighbours really could not have done anymore to make our stay so special and unforgetable. We are now planning when we will get a chance to go back!! We cann't wait.
Ask bigmcmayo about Leim Siar Bed and Breakfast
Thank bigmcmayo
we stayed in quite cold month, in the first days of April, but eventhough place is just beautiful - perfect for quiet weekend away.
House is new and modern, rooms are comfortable and spotless clean. Hannah is such a lovely person, nothing was too much trouble for her and she made us constantly like at home.
Breakfast was just beautiful, we even have found food for people with coeliac disease, what is impossible in 4*-5* stars hotels in European countries.
I would definitely recommend this B&B - I am sure if we will be in this part of Ireland we will be staying here again.
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TripAdvisor is proud to partner with Priceline and Booking.com so you can book your Leim Siar Bed and Breakfast reservations with confidence. We help millions of travelers each month to find the perfect hotel for both vacation and business trips, always with the best discounts and special offers.

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Christianbook.com: Revelation Part 1, Vision of Hope and Promise: Wisdom of the Word Series: Edited By: Jeannie McCullough: 9780834117921
CBD Stock No: WW117924
Format: PaperbackNumber of Pages: 104Vendor: Beacon Hill PressPublication Date: 2000ISBN: 0834117924ISBN-13: 9780834117921Availability: In StockSeries: Wisdom of the Word
http://www.christianbook.com/revelation-vision-promise-wisdom-word-series/9780834117921/pd/117924 Read all Revelation Part 1, Vision of Hope and Promise: Wisdom of the Word Series reviews
Read all Questions/Answers for "Revelation Part 1, Vision of Hope and Promise: Wisdom of the Word Series"

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This website is a Christian catalog and internet retailer.
Christian Book Distributors was started in 1978 by Stephen Hendrickson, 19 years old and a sophomore at Central Bible College in Springfield, Missouri, out of his parents’ home in Lynn, Massachusetts.