unfairScenario :: Scenario
unfairScenario = Scenario {
      -- Difference between fair and one-place is very clear here.
      -- The two fast writers get the same number of writes in either case.
      -- One-place gives the slow writer half as many writes, but fair gives
      -- it a lot more. The cycle time (time to read from all 3 writers) is
      -- the slow writer's write delay, so we expect that the slow writer
      -- should be able to write on every cycle.
      sim_reader = SimulationReader (uniformDistr 5000 5001)
    , sim_writers = [
            SimulationWriter (uniformDistr 4999 5000)
          , SimulationWriter (uniformDistr 4999 5000)
          , SimulationWriter (uniformDistr 14999 15000)
          ]
    }
unfairScenario :: Scenario
unfairScenario = Scenario {
      -- Difference between fair and one-place is very clear here.
      -- The two fast writers get the same number of writes in either case.
      -- One-place gives the slow writer half as many writes, but fair gives
      -- it a lot more. The cycle time (time to read from all 3 writers) is
      -- the slow writer's write delay, so we expect that the slow writer
      -- should be able to write on every cycle.
      sim_reader = SimulationReader (uniformDistr 5000 5001)
    , sim_writers = [
            SimulationWriter (uniformDistr 4999 5000)
          , SimulationWriter (uniformDistr 4999 5000)
          , SimulationWriter (uniformDistr 14999 15000)
          ]
    }
unfairScenario = Scenario {
      -- Difference between fair and one-place is very clear here.
      -- The two fast writers get the same number of writes in either case.
      -- One-place gives the slow writer half as many writes, but fair gives
      -- it a lot more. The cycle time (time to read from all 3 writers) is
      -- the slow writer's write delay, so we expect that the slow writer
      -- should be able to write on every cycle.
      sim_reader = SimulationReader (uniformDistr 5000 5001)
    , sim_writers = [
            SimulationWriter (uniformDistr 4999 5000)
          , SimulationWriter (uniformDistr 4999 5000)
          , SimulationWriter (uniformDistr 14999 15000)
          ]
    }