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Title: ASM and Verilog is a bad mix.
Review: The author obviously is trying to force Verilog and ASM notation into the same book. The result is the implicit use of Verilog states which in effect results in unmanagable Verilog spaghetti code. Having a background in both hardware design and software consulting the Verilog code in the book is terrible. It can be compared to a jumble of assembly language without any comments of structure - sure, if you know the background of the design (i.e. the ASM charts) you might see why the code might work but the Verilog code by itself is not readable!If you do some research you'll quickly see that ASM charts are not widely used these days. Most engineers in the industry are using well defined moore state machines because they are easy to understand and maps very well to case statements in Verilog.I will now skim through the rest of the book to see if there might be some content NOT related to ASM charts that might be worth picking up...
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