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Title: Regurgitation of LRM
Review: This book is basically a regurgitation of the language reference manual and really does not give the reader any insight into when and how to use particular language constructs. For example on page 148 the author discusses module ports and has an example of a port redeclaration, but he neglects to discuss why you would wish to redeclare a port as a wire. If you are learning Verilog because you are going to use it in an actual design look elsewhere.
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