Title: Could be great book, but shows too many deficiencies
Product review: This book should be used only by the experienced users that can filter out problematic sections.Major problems:- first chapter, "recommended" by authors for university courses, is extremely chaotic (begin..end blocks are called loops, exercises ask you to use loops before introducing them, etc.)- cover of the latest edition claims coverage of the latest Verilog standard - unfortunately it is very poor coverage: new interesting features such as libraries and configurations are not mentioned at all!- I had to work hard during many trainings to correct bad coding styles showing in students reading this book as their first Verilog publication- the book is grossly overpriced...Main advantage:- good set of examples
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