<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
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<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/memory_cke_attributes.xml $ -->
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<!-- IBM_PROLOG_END_TAG                                                     -->
<attributes>
    <attribute>
        <id>ATTR_MSS_VPD_CKE_MAP</id>
        <targetType>TARGET_TYPE_MCS</targetType>
        <description>
            The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable signal to its respective rank.
            There are 8 bits, but only 4 are currently used
            [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A]
            E.g. 0x80 -> 0b10000000, which means DIMM0 CKE0 is mapped to that rank.
        </description>
        <initToZero></initToZero>
        <valueType>uint8</valueType>
        <writeable/>
        <mssUnits></mssUnits>
        <mssBlobStart>0</mssBlobStart>
        <mssBlobLength>16</mssBlobLength>
        <mssAccessorName>vpd_cke_map</mssAccessorName>
        <array>2 2 4</array>
    </attribute>

</attributes>

Add VPD decode and attributes for DQ and CKE maps
Add VPD decode and attributes for DQ and CKE maps

  Fix include path in raw_card.C

Change-Id: I66e043e600e53e78817846ee5f0f8b71aae34988
Original-Change-Id: I1d02ed92d11667e639e832be72a86cdec5035a90
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29222
Tested-by: Jenkins Server <8e3f934e4c44875bc48d33da3ea13d93ba9a233f@us.ibm.com>
Tested-by: PPE CI <dc75934ba5befb9221434e67a247b93aec46b36b@us.ibm.com>
Tested-by: Hostboot CI <52521565bd8ea18a2b112942dce4f4220a97c2c8@us.ibm.com>
Reviewed-by: Christian R. Geddes <f397583a9caa8163a06ad1128784fb67413f2fe6@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <65293609e29ccd0ac899f5f3f03aea95be1b215f@us.ibm.com>
Reviewed-by: Matt K. Light <19ba8ed73a0b3c376c81fced381f1ac0f483b7c2@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <ab93eca12e43608f33daa16a67357cd7b7e867ab@us.ibm.com>
