
#Design name ("system" recommended)
set design system

#Project directory ("." recommended)
set projdir ./

#Device name
set partname "xc7z020clg400-1"

#Paths to all IP blocks to use in Vivado "system.bd"

set ip_repos [list "../parallella_base" "../../../../../parallella-fpga/AdiHDLLib/library"]

#All source files
set hdl_files []

#All constraints files
set constraints_files [list \
			   ../parallella_timing.xdc \
			   ../parallella_io.xdc \
			   ../parallella_7020_io.xdc \
			  ]

###########################################################
# PREPARE FOR SYNTHESIS
###########################################################
set oh_verilog_define "CFG_ASIC=0 CFG_PLATFORM=\"ZYNQ\""


#Design name ("system" recommended)
set design system

#Project directory ("." recommended)
set projdir ./

#Device name
set partname "xc7z020clg400-1"

#Paths to all IP blocks to use in Vivado "system.bd"

set ip_repos [list "../parallella_base" "../../../adi/hdl/library"]

#All source files
set hdl_files []

#All constraints files
set constraints_files [list \
			   ../parallella_timing.xdc \
			   ../parallella_io.xdc \
			   ../parallella_7020_io.xdc \
			  ]

###########################################################
# PREPARE FOR SYNTHESIS
###########################################################
set oh_verilog_define "CFG_ASIC=0 CFG_PLATFORM=\"ZYNQ\""

Use in-tree ADI IP repo
parallella/fpga: Use in-tree ADI IP repo
