{"commit":"840893790588d27fadffd24f18a9b073121f4ed4","old_file":"src\/addons\/core-generator\/rocket-chip\/src\/clock.vh","new_file":"src\/addons\/core-generator\/rocket-chip\/src\/clock.vh","old_contents":"`define CLOCK_PERIOD 1.0\n`define PRINTF_COND TestDriver.printf_cond\n`define STOP_COND !TestDriver.reset\n`define RANDOMIZE_MEM_INIT\n`define RANDOMIZE_REG_INIT\n`define RANDOMIZE_GARBAGE_ASSIGN\n`define RANDOMIZE_INVALID_ASSIGN\n","new_contents":"`define CLOCK_PERIOD 1.0\n`ifdef VERILATOR\n`define PRINTF_COND $c(\"done_reset\")\n`define STOP_COND $c(\"done_reset\")\n`else\n`define PRINTF_COND !TestDriver.reset\n`define STOP_COND !TestDriver.reset\n`endif\n`define RANDOMIZE_MEM_INIT\n`define RANDOMIZE_REG_INIT\n`define RANDOMIZE_GARBAGE_ASSIGN\n`define RANDOMIZE_INVALID_ASSIGN\n","subject":"Support Verilator simulation again, {PRINTF,STOP}_COND changed","message":"Support Verilator simulation again, {PRINTF,STOP}_COND changed\n","lang":"SystemVerilog","license":"bsd-3-clause","repos":"ucb-bar\/plsi,ucb-bar\/plsi"}
{"commit":"754895e6ceb7058facc2c1af2be1b804dc044beb","old_file":"src\/test\/sv\/string_utils_unit_test.sv","new_file":"src\/test\/sv\/string_utils_unit_test.sv","old_contents":"module string_utils_unit_test;\n\n  import svunit_pkg::*;\n  `include \"svunit_defines.svh\"\n\n  string name = \"string_utils_ut\";\n  svunit_testcase svunit_ut;\n\n  import svunit_under_test::string_utils;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n    `SVTEST(some_passing_test)\n      `FAIL_UNLESS(svunit_under_test::TRUE)\n    `SVTEST_END\n\n  `SVUNIT_TESTS_END\n\nendmodule\n","new_contents":"module string_utils_unit_test;\n\n  import svunit_pkg::*;\n  `include \"svunit_defines.svh\"\n\n  string name = \"string_utils_ut\";\n  svunit_testcase svunit_ut;\n\n  import svunit_under_test::string_utils;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n    `SVTEST(can_split_string_by_underscore)\n      string some_string = \"some_string\";\n      string parts[] = string_utils::split_by_char(\"_\", some_string);\n      string exp_parts[] = '{ \"some\", \"string\" };\n      `FAIL_UNLESS_EQUAL(parts, exp_parts)\n    `SVTEST_END\n\n\n    `SVTEST(split_string_by_underscore_does_nothing_when_no_underscore)\n      string some_string = \"string\";\n      string parts[] = string_utils::split_by_char(\"_\", some_string);\n      string exp_parts[] = '{ \"string\" };\n      `FAIL_UNLESS_EQUAL(parts, exp_parts)\n    `SVTEST_END\n\n  `SVUNIT_TESTS_END\n\nendmodule\n","subject":"Add tests for `split_by_char` functions","message":"Add tests for `split_by_char` functions\n\nThe `FAIL` macros don't handle string very well, because it's not possible to quote text containing strings. This makes the tests look pretty awkward.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"3cf04203b085cda37909e33fa431c7c1e1b68b6f","old_file":"examples\/experimental\/test_fixture\/queue_test.sv","new_file":"examples\/experimental\/test_fixture\/queue_test.sv","old_contents":"package queue_test;\n\n  `include \"svunit.svh\"\n  `include \"svunit_defines.svh\"\n\n  import queue::*;\n\n\n  virtual class queue_test extends svunit::test;\n\n    protected queue #(int) q0;\n    protected queue #(int) q1;\n    protected queue #(int) q2;\n\n\n    protected virtual function void set_up();\n      q1.enqueue(1);\n      q2.enqueue(2);\n      q2.enqueue(3);\n    endfunction\n\n  endclass\n\n\n  `TEST_F_BEGIN(queue_test, is_empty_initially)\n    `FAIL_UNLESS_EQUAL(q0.size(), 0)\n  `TEST_F_END\n\n\n  `TEST_F_BEGIN(queue_test, dequeue_works)\n    `FAIL_UNLESS_EQUAL(q1.dequeue(), 1)\n    `FAIL_UNLESS_EQUAL(q1.size(), 0)\n\n    `FAIL_UNLESS_EQUAL(q2.dequeue(), 2)\n    `FAIL_UNLESS_EQUAL(q2.size(), 1)\n  `TEST_F_END\n\nendpackage\n","new_contents":"package queue_test;\n\n  `include \"svunit.svh\"\n  `include \"svunit_defines.svh\"\n\n  import queue::*;\n\n\n  virtual class queue_test extends svunit::test;\n\n    protected queue #(int) q0 = new();\n    protected queue #(int) q1 = new();\n    protected queue #(int) q2 = new();\n\n\n    protected virtual function void set_up();\n      q1.enqueue(1);\n      q2.enqueue(2);\n      q2.enqueue(3);\n    endfunction\n\n  endclass\n\n\n  `TEST_F_BEGIN(queue_test, is_empty_initially)\n    `FAIL_UNLESS_EQUAL(q0.size(), 0)\n  `TEST_F_END\n\n\n  `TEST_F_BEGIN(queue_test, dequeue_works)\n    `FAIL_UNLESS_EQUAL(q1.dequeue(), 1)\n    `FAIL_UNLESS_EQUAL(q1.size(), 0)\n\n    `FAIL_UNLESS_EQUAL(q2.dequeue(), 2)\n    `FAIL_UNLESS_EQUAL(q2.size(), 1)\n  `TEST_F_END\n\nendpackage\n","subject":"Fix null pointer exceptions in test","message":"Fix null pointer exceptions in test\n\nThese weren't a problem before, because if a method call on a `null` object doesn't try to access any instance members, the call won't fail.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"70206e85b120163239c76a2265e2d5193600981e","old_file":"test\/svlog\/param_port_list.sv","new_file":"test\/svlog\/param_port_list.sv","old_contents":"\/\/ 6.20 of svlog-2009\n\nmodule A1 #(int a = 5, localparam logic b = 1, type c = int, parameter n);\n\t\/\/ TODO: Check that parameter port is\n\t\/\/ - parameter int a = 5,\n\t\/\/ - localparam logic b = 1,\n\t\/\/ - localparam type c = int,\n\t\/\/ - parameter n\nendmodule\n\nmodule A2;\n\tA1 #(.n(2)) a;\n\t\/\/ TODO: Check that\n\t\/\/ - a.a = non-local (int) 5\n\t\/\/ - a.b = local (logic) 1\n\t\/\/ - a.c = local type int\n\t\/\/ - a.n = non-local (int) 2\nendmodule\n\nclass B #(size = 1);\n\tlogic [size-1:0] v;\nendclass\n\ninterface C #(AWIDTH = 64, type T = word) (input logic clk);\nendinterface\n\nmodule D #(int N = 5, M = N*16, type T = int, T x = 0)();\nendmodule\n\nclass E #(type T, int size);\n\tT words[size];\nendclass\n\ntypedef E#(byte, 1024) F;\n","new_contents":"\/\/ 6.20 of svlog-2009\n\nmodule A1 #(int a = 5, localparam logic b = 1, type c = int, parameter n);\n\t\/\/ TODO: Check that parameter port is\n\t\/\/ - parameter int a = 5,\n\t\/\/ - localparam logic b = 1,\n\t\/\/ - localparam type c = int,\n\t\/\/ - parameter n\nendmodule\n\nmodule A2;\n\tA1 #(.n(2)) a;\n\t\/\/ TODO: Check that\n\t\/\/ - a.a = non-local (int) 5\n\t\/\/ - a.b = local (logic) 1\n\t\/\/ - a.c = local type int\n\t\/\/ - a.n = non-local (int) 2\nendmodule\n\nclass B #(size = 1);\n\tlogic [size-1:0] v;\nendclass\n\ninterface C #(AWIDTH = 64, type T = int) (input logic clk);\nendinterface\n\nmodule D #(int N = 5, M = N*16, type T = int, T x = 0)();\nendmodule\n\n\/\/ class E #(type T, int size);\n\/\/ \tT words[size];\n\/\/ endclass\n\n\/\/ typedef E#(byte, 1024) F;\n","subject":"Disable some weird broken tests","message":"test: Disable some weird broken tests\n","lang":"SystemVerilog","license":"apache-2.0","repos":"fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore"}
{"commit":"ea575f977c8e73ba934091613825e158b296e319","old_file":"hw\/ip\/lc_ctrl\/dv\/env\/seq_lib\/lc_ctrl_prog_failure_vseq.sv","new_file":"hw\/ip\/lc_ctrl\/dv\/env\/seq_lib\/lc_ctrl_prog_failure_vseq.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n\/\/ This sequence triggers prog_failure alert by setting the error bit in otp_program_rsp\n\/\/ Then check in scb if the alert is triggered correctly\nclass lc_ctrl_prog_failure_vseq extends lc_ctrl_smoke_vseq;\n  `uvm_object_utils(lc_ctrl_prog_failure_vseq)\n\n  `uvm_object_new\n\n  constraint otp_prog_err_c {\n    otp_prog_err == 1;\n  }\n\n  virtual task post_start();\n    \/\/ trigger dut_init to make sure always on alert is not firing forever\n    if (do_apply_reset) begin\n      dut_init();\n    end else wait(0); \/\/ wait until upper seq resets and kills this seq\n\n    \/\/ delay to avoid race condition when sending item and checking no item after reset occur\n    \/\/ at the same time\n    #1ps;\n    super.post_start();\n  endtask\n\nendclass\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n\/\/ This sequence triggers prog_failure alert by setting the error bit in otp_program_rsp\n\/\/ Then check in scb if the alert is triggered correctly\nclass lc_ctrl_prog_failure_vseq extends lc_ctrl_smoke_vseq;\n  `uvm_object_utils(lc_ctrl_prog_failure_vseq)\n\n  `uvm_object_new\n\n  constraint otp_prog_err_c {\n    otp_prog_err == 1;\n  }\n\n  virtual task post_start();\n    expect_fatal_alerts = 1;\n    super.post_start();\n  endtask\n\nendclass\n","subject":"Modify lc tests to use post_start alert checking.","message":"[dv\/lc_ctrl] Modify lc tests to use post_start alert checking.\n\nSigned-off-by: Cindy Chen <399ad771a111eac8923348b1e2af093034e5d4f1@opentitan.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"3f12dc2d932d11ba76cdbf233f9830c1499f80a7","old_file":"svunit_base\/svunit_string_utils.svh","new_file":"svunit_base\/svunit_string_utils.svh","old_contents":"\/* package private *\/ class string_utils;\n\n  \/* local *\/ typedef string array_of_string[];\n\n\n  static function array_of_string split_by_char(string char, string s);\n    string parts[$];\n    int last_char_position = -1;\n\n    if (char.len() != 1)\n      $fatal(0, \"Internal error: expected a single character string\");\n\n    for (int i = 0; i < s.len(); i++) begin\n      if (i == s.len()-1)\n        parts.push_back(s.substr(last_char_position+1, i));\n      if (s[i] == char) begin\n        parts.push_back(s.substr(last_char_position+1, i-1));\n        last_char_position = i;\n      end\n    end\n\n    return parts;\n  endfunction\n\nendclass\n","new_contents":"\/* package private *\/ class string_utils;\n\n  \/* local *\/ typedef string array_of_string[];\n\n\n  static function array_of_string split_by_char(string char, string s);\n    string parts[$];\n    int last_char_position = -1;\n\n    if (char.len() != 1)\n      $fatal(0, \"Internal error: expected a single character string\");\n\n    for (int i = 0; i < s.len(); i++) begin\n      if (i == s.len()-1)\n        parts.push_back(s.substr(last_char_position+1, i));\n      if (string'(s[i]) == char) begin\n        parts.push_back(s.substr(last_char_position+1, i-1));\n        last_char_position = i;\n      end\n    end\n\n    return parts;\n  endfunction\n\nendclass\n","subject":"Fix warning related to string comparison","message":"Fix warning related to string comparison\n\n`s[i]` returns a `byte`, whereas `char` is a `string`. DVT and VCS complain about this comparison, while Xcelium and QuestaSim are fine with it. No idea who is in the right here, but we don't want warnings in any of the tools.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"4c531a2b90eb34483820a81b05ad166b5b3199eb","old_file":"SimpleGPUIP\/source\/OutputControllerRAM.sv","new_file":"SimpleGPUIP\/source\/OutputControllerRAM.sv","old_contents":"\/\/ $Id: $\n\/\/ File name:   OutputControllerRAM.sv\n\/\/ Created:     4\/21\/2016\n\/\/ Author:      Diego De La Fuente\n\/\/ Lab Section: 337-08\n\/\/ Version:     1.0  Initial Design Entry\n\/\/ Description: This is how the Output Controller reads and writes to the M9K\n\/\/\n\nmodule OutputControllerRam\n(\n\t    output reg [31:0] q,\n\t\tinput [31:0] d,\n\t\tinput [6:0] write_address, read_address,\n\t\tinput we, clk\n);\n\treg [31:0] mem [2457599:0];\n\talways @ (posedge clk) begin\n\t\tif (we)\n\t\t\tmem[write_address] <= d;\n\t\tq <= mem[read_address]; \/\/ q doesn't get d in this clock cycle\n\tend\nendmodule\n","new_contents":"\/\/ $Id: $\n\/\/ File name:   OutputControllerRAM.sv\n\/\/ Created:     4\/21\/2016\n\/\/ Author:      Diego De La Fuente\n\/\/ Lab Section: 337-08\n\/\/ Version:     1.0  Initial Design Entry\n\/\/ Description: This is how the Output Controller reads and writes to the M9K\n\/\/\n\nmodule OutputControllerRam\n(\n\t    output reg [23:0] q,\n\t\tinput [23:0] data,\n\t\tinput [6:0] write_address, read_address,\n\t\tinput we, clk\n);\n\treg [23:0] mem [2457599:0];\n\talways @ (posedge clk) begin\n\t\tif (we)\n\t\t\tmem[write_address] <= data;\n\t\tq <= mem[read_address]; \/\/ q doesn't get d in this clock cycle\n\tend\nendmodule\n","subject":"Revert \"Revert \"Changes to Output Controller Ram Access\"\"","message":"Revert \"Revert \"Changes to Output Controller Ram Access\"\"\n\nThis reverts commit 7aa9b68244bcd22dad3a1b46e23e69e6e8535e8f.\n","lang":"SystemVerilog","license":"mit","repos":"ddelafue\/SimpleGPU,ddelafue\/SimpleGPU,ddelafue\/SimpleGPU,ddelafue\/SimpleGPU,ddelafue\/SimpleGPU"}
{"commit":"21fce9b0e9a836f6abfe71c02565714a3cac74b5","old_file":"src\/experimental\/sv\/svunit_internal.svh","new_file":"src\/experimental\/sv\/svunit_internal.svh","old_contents":"`define SVUNIT_INTERNAL_TEST_BEGIN(TEST_NAME, BASE_CLASS) \\\n  class TEST_NAME extends BASE_CLASS; \\\n    local static const bit is_test_builder_registerd \\\n        = register_test_builder(concrete_builder#(TEST_NAME)::get()); \\\n    local static string full_name_of_class = $sformatf(\"%m\"); \\\n    \\\n    virtual function string full_name(); \\\n      return full_name_of_class; \\\n    endfunction \\\n    \\\n    virtual function string name(); \\\n      return `\"TEST_NAME`\"; \\\n    endfunction \\\n    \\\n    virtual task test_body(); \\\n\n\n`define SVUNIT_INTERNAL_TEST_END \\\n    endtask \\\n  endclass \\\n","new_contents":"`define SVUNIT_INTERNAL_TEST_BEGIN(TEST_NAME, BASE_CLASS) \\\n  class TEST_NAME extends BASE_CLASS; \\\n    local static const bit is_test_builder_registerd \\\n        = register_test_builder(concrete_builder#(TEST_NAME)::get()); \\\n    local static string full_name_of_class = $sformatf(\"%m\"); \\\n    \\\n    virtual function string full_name(); \\\n      return full_name_of_class; \\\n    endfunction \\\n    \\\n    virtual function string name(); \\\n      return `\"TEST_NAME`\"; \\\n    endfunction \\\n    \\\n    protected virtual task test_body(); \\\n\n\n`define SVUNIT_INTERNAL_TEST_END \\\n    endtask \\\n  endclass \\\n","subject":"Fix access qualifier warnings when using experimental test macros","message":"Fix access qualifier warnings when using experimental test macros\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"5db5f99a9686642785a2ce67e1aff9c830307e16","old_file":"verilog\/tools\/kythe\/testdata\/for_loop_uint.sv","new_file":"verilog\/tools\/kythe\/testdata\/for_loop_uint.sv","old_contents":"\/\/- @my_module defines\/binding _\nmodule my_module();\n    \/\/- @y defines\/binding Y\n    int y = 0;\n    initial begin\n        \/\/- @#0x defines\/binding X\n        \/\/- @#1x ref X\n        \/\/- @#2x ref X\n        for (uint x = 1; x < 5; x++) begin\n            \/\/- @y ref Y\n            y++;\n        end\n    end\nendmodule\n","new_contents":"\/\/- @uint defines\/binding Uint\ntypedef int uint;\n\n\/\/- @my_module defines\/binding _\nmodule my_module();\n    \/\/- @y defines\/binding Y\n    int y = 0;\n    initial begin\n        \/\/- @uint ref Uint\n        \/\/- @#0x defines\/binding X\n        \/\/- @#1x ref X\n        \/\/- @#2x ref X\n        for (uint x = 1; x < 5; x++) begin\n            \/\/- @y ref Y\n            y++;\n        end\n    end\nendmodule\n","subject":"Update test to cover variable declaration inside for-loop header.","message":"Update test to cover variable declaration inside for-loop header.\n\nissues #548\n\nPiperOrigin-RevId: 341669535\n","lang":"SystemVerilog","license":"apache-2.0","repos":"chipsalliance\/verible,chipsalliance\/verible,chipsalliance\/verible,chipsalliance\/verible,chipsalliance\/verible"}
{"commit":"91a82fbcb67e807f5679cd6e4f7e88d1e581b674","old_file":"examples\/experimental\/single_test_suite\/factorial.sv","new_file":"examples\/experimental\/single_test_suite\/factorial.sv","old_contents":"package factorial;\n\n  function automatic int unsigned factorial(int unsigned n);\n    return 0;\n  endfunction\n\nendpackage\n","new_contents":"package factorial;\n\n  function automatic int unsigned factorial(int unsigned n);\n    return 1;\n  endfunction\n\nendpackage\n","subject":"Implement enough production code to make one test pass","message":"Implement enough production code to make one test pass\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"41f9afc4c07e79587f05f6ea5214b5883f15161f","old_file":"test\/svlog\/ports\/nightmare.sv","new_file":"test\/svlog\/ports\/nightmare.sv","old_contents":"\/\/ RUN: moore %s -e foo\n\/\/ IGNORE\n\nmodule foo (\n    .P1(x1[3:0]),\n    .P2(x1[7:0]),\n    .P3(x2),\n    P4,\n    .P5({x3, x4}),\n    {x5, x6}\n);\n    \/\/ This language needs to die.\n    output [7:0] x1;\n    ref x2;\n    input P4;\n    input x3, x5;\n    output x4, x6;\nendmodule\n","new_contents":"\/\/ RUN: moore %s -e foo\n\/\/ IGNORE\n\nmodule foo (\n    .P1(x1[3:0]),\n    .P2(x1[7:0]),\n    .P3(x2),\n    P4,\n    .P5({x3, x4}),\n    {x5, x6}\n);\n    \/\/ This language needs to die.\n    output [7:0] x1;\n    ref x2;\n    input P4;\n    input x3, x5;\n    output x4, x6;\n\n    logic [7:0] x1;\n    int x2;\nendmodule\n","subject":"Update complex SV ports test","message":"test: Update complex SV ports test\n","lang":"SystemVerilog","license":"apache-2.0","repos":"fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore"}
{"commit":"a6aaa2d4a8c1370b574ce8b07b14f9bb89cbd19d","old_file":"hw\/ip\/otbn\/dv\/uvm\/env\/otbn_rf_base_if.sv","new_file":"hw\/ip\/otbn\/dv\/uvm\/env\/otbn_rf_base_if.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\/\/\n\/\/ Bound into the otbn_rf_base and used to help collect call stack information for coverage.\n\ninterface otbn_rf_base_if (\n  input       clk_i,\n  input       rst_ni,\n\n  \/\/ Signal names from the otbn_rf_base module (where we are bound)\n  input logic pop_stack_a, \n  input logic pop_stack_b,\n  input logic pop_stack,\n  input logic push_stack,\n  input logic stack_full,\n  input logic stack_data_valid \n);\n\n  function automatic otbn_env_pkg::call_stack_flags_t get_call_stack_flags();\n    return '{\n              pop_a: pop_stack && pop_stack_a,\n              pop_b: pop_stack && pop_stack_b,\n              push: push_stack\n            };\n  endfunction\n\n  function automatic otbn_env_pkg::stack_fullness_e get_call_stack_fullness();\n    if (stack_full) begin\n      return otbn_env_pkg::StackFull;\n    end\n    if (stack_data_valid) begin\n      return otbn_env_pkg::StackPartial;\n    end\n    return otbn_env_pkg::StackEmpty;\n  endfunction\n\nendinterface\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\/\/\n\/\/ Bound into the otbn_rf_base and used to help collect call stack information for coverage.\n\ninterface otbn_rf_base_if (\n  input       clk_i,\n  input       rst_ni,\n\n  \/\/ Signal names from the otbn_rf_base module (where we are bound)\n  input logic pop_stack_a, \n  input logic pop_stack_b,\n  input logic push_stack_reqd,\n  input logic stack_full,\n  input logic stack_data_valid \n);\n\n  function automatic otbn_env_pkg::call_stack_flags_t get_call_stack_flags();\n    return '{\n              pop_a: pop_stack_a,\n              pop_b: pop_stack_b,\n              push: push_stack_reqd\n            };\n  endfunction\n\n  function automatic otbn_env_pkg::stack_fullness_e get_call_stack_fullness();\n    if (stack_full) begin\n      return otbn_env_pkg::StackFull;\n    end\n    if (stack_data_valid) begin\n      return otbn_env_pkg::StackPartial;\n    end\n    return otbn_env_pkg::StackEmpty;\n  endfunction\n\nendinterface\n","subject":"Fix callstack flags in coverage","message":"[otbn,dv] Fix callstack flags in coverage\n\npop_stack_a (resp. pop_stack_b) is signalled if the instruction in\nquestion tries to read from x1 with operand a (resp b). pop_stack is\nonly true if, furthermore, rd_commit_i holds. This guarantees that the\ninstruction isn't stalled, but also implies that the instruction\ndidn't cause a fault.\n\nWe don't need to check for stalling instructions when calculating\nthese flags: they'll only be read in otbn_trace_monitor.sv if the\ninstruction isn't stalled. But we *do* need to make sure we get the\nraw values for a faulting instruction. Without this fix, it would be\nimpossible to see e.g. how we caused an underflow with an instruction\nlike \"add x0, x1, x1\".\n\nSimilarly, the push_stack signal requires that the instruction didn't\ncause a fault: we actually want the raw signal in push_stack_reqd.\n\nSigned-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"7aa9b68244bcd22dad3a1b46e23e69e6e8535e8f","old_file":"SimpleGPUIP\/source\/OutputControllerRAM.sv","new_file":"SimpleGPUIP\/source\/OutputControllerRAM.sv","old_contents":"\/\/ $Id: $\n\/\/ File name:   OutputControllerRAM.sv\n\/\/ Created:     4\/21\/2016\n\/\/ Author:      Diego De La Fuente\n\/\/ Lab Section: 337-08\n\/\/ Version:     1.0  Initial Design Entry\n\/\/ Description: This is how the Output Controller reads and writes to the M9K\n\/\/\n\nmodule OutputControllerRam\n(\n\t    output reg [23:0] q,\n\t\tinput [23:0] data,\n\t\tinput [6:0] write_address, read_address,\n\t\tinput we, clk\n);\n\treg [23:0] mem [2457599:0];\n\talways @ (posedge clk) begin\n\t\tif (we)\n\t\t\tmem[write_address] <= data;\n\t\tq <= mem[read_address]; \/\/ q doesn't get d in this clock cycle\n\tend\nendmodule\n","new_contents":"\/\/ $Id: $\n\/\/ File name:   OutputControllerRAM.sv\n\/\/ Created:     4\/21\/2016\n\/\/ Author:      Diego De La Fuente\n\/\/ Lab Section: 337-08\n\/\/ Version:     1.0  Initial Design Entry\n\/\/ Description: This is how the Output Controller reads and writes to the M9K\n\/\/\n\nmodule OutputControllerRam\n(\n\t    output reg [31:0] q,\n\t\tinput [31:0] d,\n\t\tinput [6:0] write_address, read_address,\n\t\tinput we, clk\n);\n\treg [31:0] mem [2457599:0];\n\talways @ (posedge clk) begin\n\t\tif (we)\n\t\t\tmem[write_address] <= d;\n\t\tq <= mem[read_address]; \/\/ q doesn't get d in this clock cycle\n\tend\nendmodule\n","subject":"Revert \"Changes to Output Controller Ram Access\"","message":"Revert \"Changes to Output Controller Ram Access\"\n\nThis reverts commit d865033eed25767d82413f5213a9ee4eacf02ed8.\n","lang":"SystemVerilog","license":"mit","repos":"ddelafue\/SimpleGPU,ddelafue\/SimpleGPU,ddelafue\/SimpleGPU,ddelafue\/SimpleGPU,ddelafue\/SimpleGPU"}
{"commit":"50ccb9f782004fc387ad1b82c166adbf921477a7","old_file":"hw\/ip\/edn\/dv\/tests\/edn_alert_test.sv","new_file":"hw\/ip\/edn\/dv\/tests\/edn_alert_test.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass edn_alert_test extends edn_base_test;\n\n  `uvm_component_utils(edn_alert_test)\n  `uvm_component_new\n\n  function void configure_env();\n    super.configure_env();\n\n    cfg.en_scb            = 0;\n    cfg.enable_pct        = 100;\n    cfg.boot_req_mode_pct = 0;\n    cfg.cmd_fifo_rst      = 100;\n    cfg.use_invalid_mubi  = 1;\n    cfg.num_endpoints     = MIN_NUM_ENDPOINTS;\n\n    `DV_CHECK_RANDOMIZE_FATAL(cfg)\n    `uvm_info(`gfn, $sformatf(\"%s\", cfg.convert2string()), UVM_LOW)\n  endfunction\nendclass : edn_alert_test\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass edn_alert_test extends edn_base_test;\n\n  `uvm_component_utils(edn_alert_test)\n  `uvm_component_new\n\n  function void configure_env();\n    super.configure_env();\n\n    cfg.en_scb            = 0;\n    cfg.enable_pct        = 100;\n    cfg.boot_req_mode_pct = 0;\n    cfg.cmd_fifo_rst_pct  = 100;\n    cfg.use_invalid_mubi  = 1;\n    cfg.num_endpoints     = MIN_NUM_ENDPOINTS;\n\n    `DV_CHECK_RANDOMIZE_FATAL(cfg)\n    `uvm_info(`gfn, $sformatf(\"%s\", cfg.convert2string()), UVM_LOW)\n  endfunction\nendclass : edn_alert_test\n","subject":"Fix ENUMERR in DV environment","message":"[edn\/dv] Fix ENUMERR in DV environment\n\nSigned-off-by: Michael Schaffner <a005a2d3342a687ea2d05360c953107acbe83e08@google.com>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"9295d4b6abf43bc05a6b8b56536c66ed393ea081","old_file":"rtl\/core\/config.sv","new_file":"rtl\/core\/config.sv","old_contents":"\/\/ \n\/\/ Copyright 2011-2015 Jeff Bush\n\/\/ \n\/\/ Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/ you may not use this file except in compliance with the License.\n\/\/ You may obtain a copy of the License at\n\/\/ \n\/\/     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/ \n\/\/ Unless required by applicable law or agreed to in writing, software\n\/\/ distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/ See the License for the specific language governing permissions and\n\/\/ limitations under the License.\n\/\/ \n\n`ifndef __CONFIG_V\n`define __CONFIG_V\n\n\/\/ Configurable parameters\n\/\/ Number of ways must be 1, 2, 4, or 8\n\n`define NUM_CORES 1\n`define THREADS_PER_CORE 4\n`define L1D_WAYS 4\n`define L1D_SETS 64\t\t\/\/ 16k\n`define L1I_WAYS 4\n`define L1I_SETS 64\t\t\/\/ 16k\n`define L2_WAYS 8\n`define L2_SETS 256\t\t\/\/ 128k\n`define AXI_DATA_WIDTH 32\n\n`endif\n","new_contents":"\/\/ \n\/\/ Copyright 2011-2015 Jeff Bush\n\/\/ \n\/\/ Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/ you may not use this file except in compliance with the License.\n\/\/ You may obtain a copy of the License at\n\/\/ \n\/\/     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/ \n\/\/ Unless required by applicable law or agreed to in writing, software\n\/\/ distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/ See the License for the specific language governing permissions and\n\/\/ limitations under the License.\n\/\/ \n\n`ifndef __CONFIG_V\n`define __CONFIG_V\n\n\/\/ Configurable parameters\n\/\/ Number of ways must be 1, 2, 4, or 8\n\n`define NUM_CORES 1\n`define THREADS_PER_CORE 4\n`define L1D_WAYS 4\n`define L1D_SETS 64\t\t\/\/ 16k\n`define L1I_WAYS 4\n`define L1I_SETS 64\t\t\/\/ 16k\n`define L2_WAYS 8\n`define L2_SETS 512\t\t\/\/ 256k\n`define AXI_DATA_WIDTH 32\n\n`endif\n","subject":"Increase L2 cache size to 256k","message":"Increase L2 cache size to 256k\n","lang":"SystemVerilog","license":"apache-2.0","repos":"FulcronZ\/NyuziProcessor,hoangt\/NyuziProcessor,FulcronZ\/NyuziProcessor,hoangt\/NyuziProcessor,hoangt\/NyuziProcessor,hoangt\/NyuziProcessor,FulcronZ\/NyuziProcessor,jbush001\/NyuziProcessor,jbush001\/NyuziProcessor,FulcronZ\/NyuziProcessor,jbush001\/NyuziProcessor,jbush001\/NyuziProcessor,jbush001\/NyuziProcessor,jbush001\/NyuziProcessor"}
{"commit":"5c0cafc0bffa40ce0556c65e57e980932580ac0f","old_file":"hw\/ip\/prim_generic\/rtl\/prim_generic_rom.sv","new_file":"hw\/ip\/prim_generic\/rtl\/prim_generic_rom.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n`include \"prim_assert.sv\"\n\nmodule prim_generic_rom #(\n  parameter  int Width     = 32,\n  parameter  int Depth     = 2048, \/\/ 8kB default\n  parameter  int Aw        = $clog2(Depth)\n) (\n  input                        clk_i,\n  input                        rst_ni,\n  input        [Aw-1:0]        addr_i,\n  input                        cs_i,\n  output logic [Width-1:0]     dout_o,\n  output logic                 dvalid_o\n);\n\n  logic [Width-1:0] mem [Depth];\n\n  always_ff @(posedge clk_i) begin\n    if (cs_i) begin\n      dout_o <= mem[addr_i];\n    end\n  end\n\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      dvalid_o <= 1'b0;\n    end else begin\n      dvalid_o <= cs_i;\n    end\n  end\n\n  `include \"prim_util_memload.sv\"\n\n  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n  \/\/ ASSERTIONS \/\/\n  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n  \/\/ Control Signals should never be X\n  `ASSERT(noXOnCsI, !$isunknown(cs_i), clk_i, '0)\nendmodule\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n`include \"prim_assert.sv\"\n\nmodule prim_generic_rom #(\n  parameter  int Width     = 32,\n  parameter  int Depth     = 2048, \/\/ 8kB default\n  localparam int Aw        = $clog2(Depth)\n) (\n  input                        clk_i,\n  input                        rst_ni,\n  input        [Aw-1:0]        addr_i,\n  input                        cs_i,\n  output logic [Width-1:0]     dout_o,\n  output logic                 dvalid_o\n);\n\n  logic [Width-1:0] mem [Depth];\n\n  always_ff @(posedge clk_i) begin\n    if (cs_i) begin\n      dout_o <= mem[addr_i];\n    end\n  end\n\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      dvalid_o <= 1'b0;\n    end else begin\n      dvalid_o <= cs_i;\n    end\n  end\n\n  `include \"prim_util_memload.sv\"\n\n  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n  \/\/ ASSERTIONS \/\/\n  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n  \/\/ Control Signals should never be X\n  `ASSERT(noXOnCsI, !$isunknown(cs_i), clk_i, '0)\nendmodule\n","subject":"Use localparam for derived parameters","message":"[prim_rom] Use localparam for derived parameters\n\nSigned-off-by: Philipp Wagner <5a4b10454c30419e54a1570be358a516ff84bb63@lowrisc.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"2ef90f6b02a312a32a9afd93c2c7ae68cb869fde","old_file":"hw\/ip\/sysrst_ctrl\/dv\/env\/seq_lib\/sysrst_ctrl_smoke_vseq.sv","new_file":"hw\/ip\/sysrst_ctrl\/dv\/env\/seq_lib\/sysrst_ctrl_smoke_vseq.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n\/\/ smoke test vseq\nclass sysrst_ctrl_smoke_vseq extends sysrst_ctrl_base_vseq;\n  `uvm_object_utils(sysrst_ctrl_smoke_vseq)\n\n  `uvm_object_new\n\n  constraint num_trans_c {num_trans == 20;}\n\n  task body();\n   `uvm_info(`gfn, \"Starting the body from smoke_seq\", UVM_LOW)\n\n    repeat (num_trans) begin\n\n      \/\/ Randomize the input pins\n      cfg.vif.randomize_input();\n\n      \/\/ In normal mode sysrst_ctrl should pass the input pins data to output pins as it is\n      @(posedge cfg.vif.clk_i)\n      `DV_CHECK_EQ(cfg.vif.key0_in, cfg.vif.key0_out)\n      `DV_CHECK_EQ(cfg.vif.key1_in, cfg.vif.key1_out)\n      `DV_CHECK_EQ(cfg.vif.key2_in, cfg.vif.key2_out)\n      `DV_CHECK_EQ(cfg.vif.pwrb_in, cfg.vif.pwrb_out)\n    end\n  endtask : body\n\nendclass : sysrst_ctrl_smoke_vseq\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n\/\/ smoke test vseq\nclass sysrst_ctrl_smoke_vseq extends sysrst_ctrl_base_vseq;\n  `uvm_object_utils(sysrst_ctrl_smoke_vseq)\n\n  `uvm_object_new\n\n  constraint num_trans_c {num_trans == 20;}\n\n  task body();\n   `uvm_info(`gfn, \"Starting the body from smoke_seq\", UVM_LOW)\n\n    repeat (num_trans) begin\n\n      \/\/ Randomize the input pins\n      cfg.vif.randomize_input();\n\n      \/\/ In normal mode sysrst_ctrl should pass the input pins data to output pins as it is\n      cfg.clk_aon_rst_vif.wait_clks(1);\n      `DV_CHECK_EQ(cfg.vif.key0_in, cfg.vif.key0_out)\n      `DV_CHECK_EQ(cfg.vif.key1_in, cfg.vif.key1_out)\n      `DV_CHECK_EQ(cfg.vif.key2_in, cfg.vif.key2_out)\n      `DV_CHECK_EQ(cfg.vif.pwrb_in, cfg.vif.pwrb_out)\n      \/\/ Input pin flash_wp_l_in should not affect flash_wp_l_o output pin\n      `DV_CHECK_EQ(cfg.vif.flash_wp_l, 0)\n    end\n  endtask : body\n\nendclass : sysrst_ctrl_smoke_vseq\n","subject":"Add flash_wp_l_o check in smoke test","message":"[sysrst_ctrl,dv] Add flash_wp_l_o check in smoke test\n\nThis pull request will update the smoke test to check\nrandomizing flash_wp_l_in will not affect flash_wp_l_o output pin\n\nSigned-off-by: Madhuri Patel <11ca6de05d3d25e46f997d96738859192826ff1e@ensilica.com>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"3e72898f8cf075bd7f6cf73e02267ce7e3e8479c","old_file":"hw\/ip\/prim_xilinx\/rtl\/prim_xilinx_pad_wrapper.sv","new_file":"hw\/ip\/prim_xilinx\/rtl\/prim_xilinx_pad_wrapper.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\/\/\n\/\/ Bidirectional IO buffer for Xilinx FPGAs. Implements inversion and\n\/\/ virtual open drain feature.\n\n\nmodule prim_xilinx_pad_wrapper #(\n  parameter int unsigned AttrDw = 2\n) (\n  inout wire         inout_io, \/\/ bidirectional pad\n  output logic       in_o,     \/\/ input data\n  input              out_i,    \/\/ output data\n  input              oe_i,     \/\/ output enable\n  \/\/ additional attributes\n  input [AttrDw-1:0] attr_i\n);\n\n  \/\/ get pad attributes\n  logic od, inv;\n  assign {od, inv} = attr_i[1:0];\n\n  \/\/ input inversion\n  logic in;\n  assign in_o     = inv ^ in;\n\n  \/\/ virtual open drain emulation\n  logic oe, out;\n  assign out      = out_i ^ inv;\n  assign oe       = oe_i & ((od & ~out) | ~od);\n\n  \/\/ driver\n  IOBUF i_iobuf (\n    .T(oe),\n    .I(out),\n    .O(in),\n    .IO(inout_io)\n  );\n\nendmodule : prim_xilinx_pad_wrapper\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\/\/\n\/\/ Bidirectional IO buffer for Xilinx FPGAs. Implements inversion and\n\/\/ virtual open drain feature.\n\n\nmodule prim_xilinx_pad_wrapper #(\n  parameter int unsigned AttrDw = 2\n) (\n  inout wire         inout_io, \/\/ bidirectional pad\n  output logic       in_o,     \/\/ input data\n  input              out_i,    \/\/ output data\n  input              oe_i,     \/\/ output enable\n  \/\/ additional attributes\n  input [AttrDw-1:0] attr_i\n);\n\n  \/\/ get pad attributes\n  logic od, inv;\n  assign {od, inv} = attr_i[1:0];\n\n  \/\/ input inversion\n  logic in;\n  assign in_o     = inv ^ in;\n\n  \/\/ virtual open drain emulation\n  logic oe_n, out;\n  assign out      = out_i ^ inv;\n  \/\/ oe_n = 0: enable driver\n  \/\/ oe_n = 1: disable driver\n  assign oe_n     = ~oe_i | (out & od);\n\n  \/\/ driver\n  IOBUF i_iobuf (\n    .T(oe_n),\n    .I(out),\n    .O(in),\n    .IO(inout_io)\n  );\n\nendmodule : prim_xilinx_pad_wrapper\n","subject":"Correct OE signal polarity for Xilinx version","message":"[prim_pad_wrapper] Correct OE signal polarity for Xilinx version\n\nSigned-off-by: Michael Schaffner <a005a2d3342a687ea2d05360c953107acbe83e08@google.com>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"4e2118b89ef6d5532da121af1b75e120f6abd57d","old_file":"examples\/experimental\/single_test_suite\/svunit_main.sv","new_file":"examples\/experimental\/single_test_suite\/svunit_main.sv","old_contents":"module svunit_main;\n\n  initial\n    svunit::run_all_tests();\n\nendmodule\n","new_contents":"module svunit_main;\n\n  import factorial_test::*;\n\n\n  initial\n    svunit::run_all_tests();\n\nendmodule\n","subject":"Make sure test code is elaborated","message":"Make sure test code is elaborated\n\nIt's kind of annoying to have to force the user to write the extra import statement. Let's see if we can do better.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"47d4bfa34b424d29fcaf2d13e2a64ce1bd815ec7","old_file":"hw\/ip\/edn\/dv\/tests\/edn_genbits_test.sv","new_file":"hw\/ip\/edn\/dv\/tests\/edn_genbits_test.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass edn_genbits_test extends edn_base_test;\n\n  `uvm_component_utils(edn_genbits_test)\n  `uvm_component_new\n\n  function void configure_env();\n    super.configure_env();\n\n    cfg.boot_req_mode_pct = 30;\n    cfg.auto_req_mode_pct = 30;\n    cfg.min_num_boot_reqs = 1;\n    cfg.max_num_boot_reqs = 4;\n    cfg.min_num_ep_reqs   = 4;\n    cfg.max_num_ep_reqs   = 16;\n\n    `DV_CHECK_RANDOMIZE_FATAL(cfg)\n    `uvm_info(`gfn, $sformatf(\"%s\", cfg.convert2string()), UVM_HIGH)\n  endfunction\nendclass : edn_genbits_test\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass edn_genbits_test extends edn_base_test;\n\n  `uvm_component_utils(edn_genbits_test)\n  `uvm_component_new\n\n  function void configure_env();\n    super.configure_env();\n\n    cfg.boot_req_mode_pct = 30;\n    cfg.auto_req_mode_pct = 30;\n    cfg.min_num_boot_reqs = 1;\n    cfg.max_num_boot_reqs = 4;\n    cfg.min_num_ep_reqs   = 4;\n    cfg.max_num_ep_reqs   = 64;\n\n    `DV_CHECK_RANDOMIZE_FATAL(cfg)\n    `uvm_info(`gfn, $sformatf(\"%s\", cfg.convert2string()), UVM_HIGH)\n  endfunction\nendclass : edn_genbits_test\n","subject":"Increase edn genbit max size","message":"[dv\/edn] Increase edn genbit max size\n\nThis PR increases genbits max size to increase toggle and functional\ncoverage.\n\nSigned-off-by: Cindy Chen <399ad771a111eac8923348b1e2af093034e5d4f1@opentitan.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"34b1b05e7f26d84a63110c7e7ac52917640c1760","old_file":"svunit_base\/svunit_types.svh","new_file":"svunit_base\/svunit_types.svh","old_contents":"\/\/###########################################################################\n\/\/\n\/\/  Copyright 2011 The SVUnit Authors.\n\/\/\n\/\/  Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/  you may not use this file except in compliance with the License.\n\/\/  You may obtain a copy of the License at\n\/\/\n\/\/      http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/\n\/\/  Unless required by applicable law or agreed to in writing, software\n\/\/  distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/  See the License for the specific language governing permissions and\n\/\/  limitations under the License.\n\/\/\n\/\/###########################################################################\n\n`ifndef SVUNIT_TYPES\n`define SVUNIT_TYPES\n\n  \/*\n    Enum: results_t\n    enumerated type containing PASS\/FAIL\n  *\/\n  typedef enum {PASS=1, FAIL=0}  results_t;\n\n\n  \/*\n    Enum: boolean_t\n    enumerated type containing TRUE\/FALSE\n  *\/\n  typedef enum {TRUE=1, FALSE=0} boolean_t;\n\n`endif\n","new_contents":"\/\/###########################################################################\n\/\/\n\/\/  Copyright 2011-2022 The SVUnit Authors.\n\/\/\n\/\/  Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/  you may not use this file except in compliance with the License.\n\/\/  You may obtain a copy of the License at\n\/\/\n\/\/      http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/\n\/\/  Unless required by applicable law or agreed to in writing, software\n\/\/  distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/  See the License for the specific language governing permissions and\n\/\/  limitations under the License.\n\/\/\n\/\/###########################################################################\n\n\n  \/*\n    Enum: results_t\n    enumerated type containing PASS\/FAIL\n  *\/\n  typedef enum {PASS=1, FAIL=0}  results_t;\n\n\n  \/*\n    Enum: boolean_t\n    enumerated type containing TRUE\/FALSE\n  *\/\n  typedef enum {TRUE=1, FALSE=0} boolean_t;\n","subject":"Fix compile of code under test to work together with stable SVUnit","message":"Fix compile of code under test to work together with stable SVUnit\n\nThe file doesn't need any include guards, as it's not meant to be included by any other file than the package. They bust the compile now, because the define gets set when compiling the stable SVUnit.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"865e8d3fd8ca41f09065c104b5f3033c7a04e13f","old_file":"src\/experimental\/sv\/test.svh","new_file":"src\/experimental\/sv\/test.svh","old_contents":"typedef class global_test_registry;\n\n\nvirtual class test;\n\n  typedef class builder;\n\n\n  protected static function bit register_test_builder(builder b, string typename);\n    full_name_extraction fn_extraction = new();\n    string full_name = fn_extraction.get_full_name(typename);\n    global_test_registry::get().register(b, full_name);\n\n    return 1;\n  endfunction\n\n\n  pure virtual function string name();\n\n\n  task run();\n    set_up();\n    test_body();\n    tear_down();\n  endtask\n\n\n  protected virtual task set_up();\n  endtask\n\n\n  protected pure virtual task test_body();\n\n\n  protected virtual task tear_down();\n  endtask\n\n\n  virtual class builder;\n    pure virtual function test create();\n  endclass\n\n\n  class concrete_builder #(type T = test) extends builder;\n    local static concrete_builder #(T) single_instance;\n\n    static function concrete_builder #(T) get();\n      if (single_instance == null)\n        single_instance = new();\n      return single_instance;\n    endfunction\n\n    virtual function T create();\n      T result = new();\n      return result;\n    endfunction\n  endclass\n\nendclass\n","new_contents":"typedef class global_test_registry;\n\n\nvirtual class test;\n\n  typedef class builder;\n\n\n  protected static function bit register_test_builder(builder b, string typename);\n    full_name_extraction fn_extraction = new();\n    string full_name = fn_extraction.get_full_name(typename);\n    global_test_registry::get().register(b, full_name);\n\n    return 1;\n  endfunction\n\n\n  pure virtual function string name();\n\n\n  task run();\n    set_up();\n    test_body();\n    tear_down();\n  endtask\n\n\n  protected virtual task set_up();\n  endtask\n\n\n  pure virtual protected task test_body();\n\n\n  protected virtual task tear_down();\n  endtask\n\n\n  virtual class builder;\n    pure virtual function test create();\n  endclass\n\n\n  class concrete_builder #(type T = test) extends builder;\n    local static concrete_builder #(T) single_instance;\n\n    static function concrete_builder #(T) get();\n      if (single_instance == null)\n        single_instance = new();\n      return single_instance;\n    endfunction\n\n    virtual function T create();\n      T result = new();\n      return result;\n    endfunction\n  endclass\n\nendclass\n","subject":"Work around compile error due to order of qualifiers","message":"Work around compile error due to order of qualifiers\n\nQuestaSim doesn't like it when `pure virtual` is not the first qualifier.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"7d5e7dd9b7feb18444b704f92d1a371734cc7ae5","old_file":"hw\/ip\/aon_timer\/dv\/env\/aon_timer_env_cfg.sv","new_file":"hw\/ip\/aon_timer\/dv\/env\/aon_timer_env_cfg.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass aon_timer_env_cfg extends cip_base_env_cfg #(.RAL_T(aon_timer_reg_block));\n\n  virtual clk_rst_if        aon_clk_rst_vif;\n  virtual pins_if #(1)      lc_escalate_en_vif;\n  virtual pins_if #(2)      aon_intr_vif;\n  virtual pins_if #(1)      sleep_vif;\n\n  \/\/ ext component cfgs\n\n  `uvm_object_utils_begin(aon_timer_env_cfg)\n  `uvm_object_utils_end\n\n  function new (string name=\"\");\n    super.new(name);\n\n    \/\/ The aon_timer RTL doesn't support a devmode input at the moment.\n    has_devmode = 1'b0;\n  endfunction : new\n\n  virtual function void initialize(bit [31:0] csr_base_addr = '1);\n    list_of_alerts = aon_timer_env_pkg::LIST_OF_ALERTS;\n    super.initialize(csr_base_addr);\n\n    \/\/ set num_interrupts & num_alerts\n    begin\n      uvm_reg rg = ral.get_reg_by_name(\"intr_state\");\n      if (rg != null) begin\n        num_interrupts = ral.intr_state.get_n_used_bits();\n      end\n    end\n  endfunction\n\nendclass\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass aon_timer_env_cfg extends cip_base_env_cfg #(.RAL_T(aon_timer_reg_block));\n\n  virtual clk_rst_if        aon_clk_rst_vif;\n  virtual pins_if #(1)      lc_escalate_en_vif;\n  virtual pins_if #(2)      aon_intr_vif;\n  virtual pins_if #(1)      sleep_vif;\n\n  \/\/ ext component cfgs\n\n  `uvm_object_utils_begin(aon_timer_env_cfg)\n  `uvm_object_utils_end\n\n  function new (string name=\"\");\n    super.new(name);\n\n    \/\/ The aon_timer RTL doesn't support a devmode input at the moment.\n    has_devmode = 1'b0;\n  endfunction : new\n\n  virtual function void initialize(bit [31:0] csr_base_addr = '1);\n    list_of_alerts = aon_timer_env_pkg::LIST_OF_ALERTS;\n    super.initialize(csr_base_addr);\n\n    m_tl_agent_cfg.max_outstanding_req = 1;\n\n    \/\/ set num_interrupts & num_alerts\n    begin\n      uvm_reg rg = ral.get_reg_by_name(\"intr_state\");\n      if (rg != null) begin\n        num_interrupts = ral.intr_state.get_n_used_bits();\n      end\n    end\n  endfunction\n\nendclass\n","subject":"Set TL Outstanding Request Cap as 1","message":"[aon_timer,dv] Set TL Outstanding Request Cap as 1\n\nSigned-off-by: Canberk Topal <e6b05429a51cc3258c31cb1f7836595b60921a29@lowrisc.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"a04e5daf2f6f25b11582279f04581622f7fbc0d2","old_file":"src\/test\/sv\/string_utils_unit_test.sv","new_file":"src\/test\/sv\/string_utils_unit_test.sv","old_contents":"module string_utils_unit_test;\n\n  import svunit_pkg::*;\n  `include \"svunit_defines.svh\"\n\n  string name = \"string_utils_ut\";\n  svunit_testcase svunit_ut;\n\n  import svunit_under_test::string_utils;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n    `SVTEST(can_split_string_by_underscore)\n      string some_string = \"some_string\";\n      string parts[] = string_utils::split_by_char(\"_\", some_string);\n      string exp_parts[] = '{ \"some\", \"string\" };\n      `FAIL_UNLESS_EQUAL(parts, exp_parts)\n    `SVTEST_END\n\n\n    `SVTEST(split_string_by_underscore_does_nothing_when_no_underscore)\n      string some_string = \"string\";\n      string parts[] = string_utils::split_by_char(\"_\", some_string);\n      string exp_parts[] = '{ \"string\" };\n      `FAIL_UNLESS_EQUAL(parts, exp_parts)\n    `SVTEST_END\n\n  `SVUNIT_TESTS_END\n\nendmodule\n","new_contents":"module string_utils_unit_test;\n\n  import svunit_stable_pkg::*;\n  `include \"svunit_stable_defines.svh\"\n\n  string name = \"string_utils_ut\";\n  svunit_testcase svunit_ut;\n\n  import svunit_under_test::string_utils;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n    `SVTEST(can_split_string_by_underscore)\n      string some_string = \"some_string\";\n      string parts[] = string_utils::split_by_char(\"_\", some_string);\n      string exp_parts[] = '{ \"some\", \"string\" };\n      `FAIL_UNLESS_EQUAL(parts, exp_parts)\n    `SVTEST_END\n\n\n    `SVTEST(split_string_by_underscore_does_nothing_when_no_underscore)\n      string some_string = \"string\";\n      string parts[] = string_utils::split_by_char(\"_\", some_string);\n      string exp_parts[] = '{ \"string\" };\n      `FAIL_UNLESS_EQUAL(parts, exp_parts)\n    `SVTEST_END\n\n  `SVUNIT_TESTS_END\n\nendmodule\n","subject":"Update unit test to use updated names for SVUnit version for testing","message":"Update unit test to use updated names for SVUnit version for testing\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"2ed71a499ae2b7199f4797ac748a3dccf126c97c","old_file":"dv\/uvm\/tb\/prim_clock_gating.sv","new_file":"dv\/uvm\/tb\/prim_clock_gating.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\/\/\n\/\/ Dummy clock gating module\n\nmodule prim_clock_gating #(\n    parameter Impl = \"default\"\n) (\n    input        clk_i,\n    input        en_i,\n    input        test_en_i,\n    output logic clk_o\n);\n\n  assign clk_o = en_i ? clk_i : 0;\n\nendmodule\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\/\/\n\/\/ Dummy clock gating module compatible with latch-based register file\n\nmodule prim_clock_gating #(\n    parameter Impl = \"default\"\n) (\n    input        clk_i,\n    input        en_i,\n    input        test_en_i,\n    output logic clk_o\n);\n\n  logic clk_en;\n\n  always_latch begin\n    if (clk_i == 1'b0) begin\n      clk_en <= en_i | test_en_i;\n    end\n  end\n\n  assign clk_o = clk_i & clk_en;\n\nendmodule\n","subject":"Make dummy clock gating module compatible with latch-based reg file","message":"Make dummy clock gating module compatible with latch-based reg file\n\nThe latch-based register file needs a clock gating cell that is\ntransparent for the clock enable signal only during the low clock\nphase.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/ibex,lowRISC\/ibex,AmbiML\/ibex,AmbiML\/ibex,AmbiML\/ibex,lowRISC\/ibex,AmbiML\/ibex,lowRISC\/ibex"}
{"commit":"b5c4116003fb1e0b7b36ecf649a59e721fdc320d","old_file":"examples\/driver\/my_driver.sv","new_file":"examples\/driver\/my_driver.sv","old_contents":"class my_driver extends uvm_driver #(my_item);\n    virtual my_interface vif;\n\n    `uvm_component_utils(my_driver)\n    function new(string name=\"my_driver\", uvm_component parent=null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert (uvm_config_db#(virtual my_interface)::get(this, \"\", \"ifc\", vif) && vif != null)\n        else `uvm_fatal(\"DRIVER_VIF_NOT_FOUND\", \"Did not find virtual my_interface 'vif' in the uvm_config_db\")\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        super.run_phase(phase);\n        fork drive_thread(); join_none\n    endtask\n\n    virtual task drive_thread();\n        forever begin\n            #1;\n            seq_item_port.get(req); \/\/ seq_item_port and req are inherited from uvm_driver\n            vif.foo = req.foo;\n        end\n    endtask\nendclass\n","new_contents":"class my_driver extends uvm_driver #(my_item);\n    virtual my_interface vif;\n\n    `uvm_component_utils(my_driver)\n    function new(string name=\"my_driver\", uvm_component parent=null);\n        super.new(name, parent);\n    endfunction\n\n    virtual function void connect_phase(uvm_phase phase);\n        super.connect_phase(phase);\n        assert (uvm_config_db#(virtual my_interface)::get(this, \"\", \"ifc\", vif) && vif != null)\n        else `uvm_fatal(\"DRIVER_VIF_NOT_FOUND\", \"Did not find virtual my_interface 'vif' in the uvm_config_db\")\n    endfunction\n\n    virtual task run_phase(uvm_phase phase);\n        super.run_phase(phase);\n        fork drive_thread(); join_none\n    endtask\n\n    virtual task drive_thread();\n        forever begin\n            #1;\n            seq_item_port.get_next_item(req); \/\/ seq_item_port and req are inherited from uvm_driver\n            vif.foo = req.foo;\n            seq_item_port.item_done();\n        end\n    endtask\nendclass\n","subject":"Use proper get_next_item()\/item_done() calls in driver example.","message":"Use proper get_next_item()\/item_done() calls in driver example.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"cquickstad\/uvm_unit,cquickstad\/uvm_unit,cquickstad\/uvm_unit"}
{"commit":"2e5df82e1907735dc3ff890e20381a7bcdc5dea4","old_file":"examples\/equals_macros\/equals_macros_example_unit_test.sv","new_file":"examples\/equals_macros\/equals_macros_example_unit_test.sv","old_contents":"\nmodule equals_macros_example_unit_test;\n\n  import svunit_pkg::svunit_testcase;\n  `include \"svunit_defines.svh\"\n\n  string name = \"equals_macros_example_ut\";\n  svunit_testcase svunit_ut;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n\n  `SVTEST(fail_unless_equal__int_variables)\n    int one = 1;\n    int two = 2;\n    `FAIL_UNLESS_EQUAL(one, two);\n  `SVTEST_END\n\n\n  `SVTEST(fail_unless_equal__int_variable_and_int_constant)\n    int one = 1;\n    `FAIL_UNLESS_EQUAL(one, 2);\n  `SVTEST_END\n\n\n  `SVTEST(fail_unless_equal__int_function_and_int_constant)\n    `FAIL_UNLESS_EQUAL(function_returning_one(), 2);\n  `SVTEST_END\n\n\n  `SVUNIT_TESTS_END\n\n\n  function int function_returning_one();\n    return 1;\n  endfunction\n\nendmodule\n","new_contents":"\nmodule equals_macros_example_unit_test;\n\n  import svunit_pkg::svunit_testcase;\n  `include \"svunit_defines.svh\"\n\n  string name = \"equals_macros_example_ut\";\n  svunit_testcase svunit_ut;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n\n  `SVTEST(fail_unless_equal__int_variables)\n    int one = 1;\n    int two = 2;\n    `FAIL_UNLESS_EQUAL(one, two);\n  `SVTEST_END\n\n\n  `SVTEST(fail_unless_equal__int_variable_and_int_constant)\n    int one = 1;\n    `FAIL_UNLESS_EQUAL(one, 2);\n  `SVTEST_END\n\n\n  `SVTEST(fail_unless_equal__int_function_and_int_constant)\n    `FAIL_UNLESS_EQUAL(function_returning_one(), 2);\n  `SVTEST_END\n\n\n  `SVTEST(fail_if_equal__int_variables)\n    int one = 1;\n    int also_one = 1;\n    `FAIL_IF_EQUAL(one, also_one);\n  `SVTEST_END\n\n\n  `SVUNIT_TESTS_END\n\n\n  function int function_returning_one();\n    return 1;\n  endfunction\n\nendmodule\n","subject":"Add example with usage of `FAIL_IF_EQUAL`","message":"Add example with usage of `FAIL_IF_EQUAL`\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"9259ef19adf50b2e68fa7c779e51c70eade75119","old_file":"hw\/ip\/otbn\/dv\/memutil\/otbn_memutil.svh","new_file":"hw\/ip\/otbn\/dv\/memutil\/otbn_memutil.svh","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n`ifndef __OTBN_MEMUTIL_SVH__\n`define __OTBN_MEMUTIL_SVH__\n\n\/\/ Imports for the functions defined in otbn_memutil.h. There are documentation comments explaining\n\/\/ what the functions do there.\n\nimport \"DPI-C\" function chandle OtbnMemUtilMake(string top_scope);\n\nimport \"DPI-C\" function void OtbnMemUtilFree(chandle mem_util);\n\nimport \"DPI-C\" function bit OtbnMemUtilLoadElf(chandle mem_util, string elf_path);\n\nimport \"DPI-C\" function bit OtbnMemUtilStageElf(chandle mem_util, string elf_path);\n\nimport \"DPI-C\" function int OtbnMemUtilGetSegCount(chandle mem_util, bit is_imem);\n\nimport \"DPI-C\" function bit OtbnMemUtilGetSegInfo(chandle mem_util, bit is_imem, int seg_idx,\n                                                  output bit [31:0] seg_off,\n                                                  output bit [31:0] seg_size);\n\nimport \"DPI-C\" function bit OtbnMemUtilGetSegData(chandle mem_util, bit is_imem, int word_off,\n                                                  output bit[31:0] data_value);\n\n\n`endif \/\/ __OTBN_MEMUTIL_SVH__\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\n`ifndef __OTBN_MEMUTIL_SVH__\n`define __OTBN_MEMUTIL_SVH__\n\n\/\/ Imports for the functions defined in otbn_memutil.h. There are documentation comments explaining\n\/\/ what the functions do there.\n\nimport \"DPI-C\" function chandle OtbnMemUtilMake(string top_scope);\n\nimport \"DPI-C\" function void OtbnMemUtilFree(chandle mem_util);\n\nimport \"DPI-C\" context function bit OtbnMemUtilLoadElf(chandle mem_util, string elf_path);\n\nimport \"DPI-C\" function bit OtbnMemUtilStageElf(chandle mem_util, string elf_path);\n\nimport \"DPI-C\" function int OtbnMemUtilGetSegCount(chandle mem_util, bit is_imem);\n\nimport \"DPI-C\" function bit OtbnMemUtilGetSegInfo(chandle mem_util, bit is_imem, int seg_idx,\n                                                  output bit [31:0] seg_off,\n                                                  output bit [31:0] seg_size);\n\nimport \"DPI-C\" function bit OtbnMemUtilGetSegData(chandle mem_util, bit is_imem, int word_off,\n                                                  output bit[31:0] data_value);\n\n\n`endif \/\/ __OTBN_MEMUTIL_SVH__\n","subject":"Add missing context keyword to DPI declaration","message":"[otbn] Add missing context keyword to DPI declaration\n\nOtbnMemUtilLoadElf uses svSetScope to do back-door DPI accesses, which\nisn't allowed unless the DPI declaration is marked \"context\" (and VCS\ncomplains!)\n\nSigned-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"d89f69d5e7580d9fa04ff69c6e6a8ec967a96070","old_file":"hw\/ip\/kmac\/dv\/env\/seq_lib\/kmac_common_vseq.sv","new_file":"hw\/ip\/kmac\/dv\/env\/seq_lib\/kmac_common_vseq.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass kmac_common_vseq extends kmac_base_vseq;\n  `uvm_object_utils(kmac_common_vseq)\n\n  constraint num_trans_c {\n    num_trans inside {[1:2]};\n  }\n  `uvm_object_new\n\n  virtual task pre_start();\n    do_kmac_init = 1'b0;\n    entropy_mode_c.constraint_mode(0);\n    super.pre_start();\n  endtask\n\n  virtual task body();\n    run_common_vseq_wrapper(num_trans);\n  endtask : body\n\nendclass\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass kmac_common_vseq extends kmac_base_vseq;\n  `uvm_object_utils(kmac_common_vseq)\n\n  constraint num_trans_c {\n    num_trans inside {[1:2]};\n  }\n  `uvm_object_new\n\n  virtual task pre_start();\n    do_kmac_init = 1'b0;\n    entropy_mode_c.constraint_mode(0);\n    super.pre_start();\n  endtask\n\n  virtual task body();\n    run_common_vseq_wrapper(num_trans);\n  endtask : body\n\n  virtual function void predict_shadow_reg_status(bit predict_update_err  = 0,\n                                                  bit predict_storage_err = 0);\n    super.predict_shadow_reg_status(predict_update_err, predict_storage_err);\n\n    if (predict_storage_err) begin\n      \/\/ For storage error, the kmac `cfg_regwen` register will be set to 0 internally to lock all\n      \/\/ cfg related CSRs. Because it is a `RO` register, the logic below manually locks the write\n      \/\/ access for its lockable register fields. (If the regwen is `W0C` access policy, the\n      \/\/ lockable fields will be updated automatically in `do_predict` function)\n      ral.cfg_regwen.en.set_lockable_flds_access(.lock(1));\n\n      \/\/ TODO(Issue #8460) - shadow storage error will clear update error status bit.\n      foreach (cfg.shadow_update_err_status_fields[status_field]) begin\n        void'(status_field.predict(~cfg.shadow_update_err_status_fields[status_field]));\n      end\n    end\n  endfunction\nendclass\n","subject":"Fix shadow reg error due to locked regwen","message":"[dv\/kmac] Fix shadow reg error due to locked regwen\n\n1). This PR fixes shadow reg error because when there is fatal alert, design\nlocks `cfg_regwen` to 0.\nBecause this is not a common behavior, in `kmac_common_vseq.sv` I\noverride `predict_shadow_reg_status` to capture this additional change.\n2). This PR follows the discussion in issue #8640 to temp align until\n  kmac behavior is cleared.\n\nSigned-off-by: Cindy Chen <399ad771a111eac8923348b1e2af093034e5d4f1@opentitan.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"21965829e84ab75946d64f1c8c25e525648a5c46","old_file":"hw\/ip\/otbn\/dv\/uvm\/sva\/otbn_bind.sv","new_file":"hw\/ip\/otbn\/dv\/uvm\/sva\/otbn_bind.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nmodule otbn_bind;\n\n  bind otbn tlul_assert #(\n    .EndpointType(\"Device\")\n  ) tlul_checker (\n    .clk_i  (clk_i),\n    .rst_ni (rst_ni),\n    .h2d    (tl_i),\n    .d2h    (tl_o)\n  );\n\n  import otbn_reg_pkg::*;\n  bind otbn otbn_csr_assert_fpv csr_checker (\n    .clk_i  (clk_i),\n    .rst_ni (rst_ni),\n    .h2d    (tl_i),\n    .d2h    (tl_o),\n    .reg2hw (reg2hw),\n    .hw2reg (reg2hw)\n  );\n\nendmodule\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nmodule otbn_bind;\n\n  bind otbn tlul_assert #(\n    .EndpointType(\"Device\")\n  ) tlul_checker (\n    .clk_i  (clk_i),\n    .rst_ni (rst_ni),\n    .h2d    (tl_i),\n    .d2h    (tl_o)\n  );\n\n  import otbn_reg_pkg::*;\n  bind otbn otbn_csr_assert_fpv csr_checker (\n    .clk_i  (clk_i),\n    .rst_ni (rst_ni),\n    .h2d    (tl_i),\n    .d2h    (tl_o),\n    .reg2hw (reg2hw),\n    .hw2reg (hw2reg)\n  );\n\nendmodule\n","subject":"Fix typo in SVA bindings","message":"[otbn] Fix typo in SVA bindings\n\nSigned-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>\n","lang":"SystemVerilog","license":"apache-2.0","repos":"lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan,lowRISC\/opentitan"}
{"commit":"eaa74e963c3bd0e472951b990e77c10b5f40e69a","old_file":"dv\/uvm\/icache\/dv\/ibex_icache_ecc_agent\/ibex_icache_ecc_driver.sv","new_file":"dv\/uvm\/icache\/dv\/ibex_icache_ecc_agent\/ibex_icache_ecc_driver.sv","old_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass ibex_icache_ecc_driver\n  extends dv_base_driver #(.ITEM_T (ibex_icache_ecc_item),\n                           .CFG_T  (ibex_icache_ecc_agent_cfg));\n\n  `uvm_component_utils(ibex_icache_ecc_driver)\n  `uvm_component_new\n\n  virtual task reset_signals();\n    cfg.vif.reset();\n  endtask\n\n  virtual task get_and_drive();\n    forever begin\n      seq_item_port.get_next_item(req);\n      `uvm_info(`gfn, $sformatf(\"rcvd item:\\n%0s\", req.sprint()), UVM_LOW)\n\n      cfg.vif.wait_reads(req.delay);\n      if (req.two_bits) begin\n        cfg.vif.corrupt_read_1(req.bit_pos0);\n      end else begin\n        cfg.vif.corrupt_read_2(req.bit_pos0, req.bit_pos1);\n      end\n\n      seq_item_port.item_done();\n    end\n  endtask\n\nendclass\n","new_contents":"\/\/ Copyright lowRISC contributors.\n\/\/ Licensed under the Apache License, Version 2.0, see LICENSE for details.\n\/\/ SPDX-License-Identifier: Apache-2.0\n\nclass ibex_icache_ecc_driver\n  extends dv_base_driver #(.ITEM_T (ibex_icache_ecc_item),\n                           .CFG_T  (ibex_icache_ecc_agent_cfg));\n\n  `uvm_component_utils(ibex_icache_ecc_driver)\n  `uvm_component_new\n\n  virtual task reset_signals();\n    cfg.vif.reset();\n  endtask\n\n  virtual task get_and_drive();\n    forever begin\n      seq_item_port.get_next_item(req);\n      `uvm_info(`gfn, $sformatf(\"rcvd item:\\n%0s\", req.sprint()), UVM_HIGH)\n\n      cfg.vif.wait_reads(req.delay);\n      if (req.two_bits) begin\n        cfg.vif.corrupt_read_1(req.bit_pos0);\n      end else begin\n        cfg.vif.corrupt_read_2(req.bit_pos0, req.bit_pos1);\n      end\n\n      seq_item_port.item_done();\n    end\n  endtask\n\nendclass\n","subject":"Fix verbosity in ECC UVM driver","message":"Fix verbosity in ECC UVM driver\n\nThis should have been UVM_HIGH (which disables the messages most of\nthe time).\n","lang":"SystemVerilog","license":"apache-2.0","repos":"AmbiML\/ibex,lowRISC\/ibex,lowRISC\/ibex,AmbiML\/ibex,AmbiML\/ibex,AmbiML\/ibex,lowRISC\/ibex,lowRISC\/ibex"}
{"commit":"58e9b2882ede2d580822879fc56689b47da9211b","old_file":"examples\/equals_macros\/equals_macros_example_unit_test.sv","new_file":"examples\/equals_macros\/equals_macros_example_unit_test.sv","old_contents":"","new_contents":"\nmodule equals_macros_example_unit_test;\n\n  import svunit_pkg::svunit_testcase;\n  `include \"svunit_defines.svh\"\n\n  string name = \"equals_macros_example_ut\";\n  svunit_testcase svunit_ut;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n\n  `SVTEST(fail_unless_equal__int_variables)\n    int one = 1;\n    int two = 2;\n    `FAIL_UNLESS_EQUAL(one, two);\n  `SVTEST_END\n\n\n  `SVTEST(fail_unless_equal__int_variable_and_int_constant)\n    int one = 1;\n    `FAIL_UNLESS_EQUAL(one, 2);\n  `SVTEST_END\n\n\n  `SVTEST(fail_unless_equal__int_function_and_int_constant)\n    `FAIL_UNLESS_EQUAL(function_returning_one(), 2);\n  `SVTEST_END\n\n\n  `SVUNIT_TESTS_END\n\n\n  function int function_returning_one();\n    return 1;\n  endfunction\n\nendmodule\n","subject":"Add examples with usage of `FAIL_UNLESS_EQUAL`","message":"Add examples with usage of `FAIL_UNLESS_EQUAL`\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}
{"commit":"a506726ee99f503c1e12b690c890b7fe35c7bd56","old_file":"test\/sequencer_stub_unit_test.sv","new_file":"test\/sequencer_stub_unit_test.sv","old_contents":"","new_contents":"\/\/ Copyright 2016 Tudor Timisescu (verificationgentleman.com)\n\/\/\n\/\/ Licensed under the Apache License, Version 2.0 (the \"License\");\n\/\/ you may not use this file except in compliance with the License.\n\/\/ You may obtain a copy of the License at\n\/\/\n\/\/     http:\/\/www.apache.org\/licenses\/LICENSE-2.0\n\/\/\n\/\/ Unless required by applicable law or agreed to in writing, software\n\/\/ distributed under the License is distributed on an \"AS IS\" BASIS,\n\/\/ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n\/\/ See the License for the specific language governing permissions and\n\/\/ limitations under the License.\n\n\nmodule sequencer_stub_unit_test;\n  import svunit_pkg::svunit_testcase;\n  `include \"svunit_defines.svh\"\n\n  import vgm_svunit_utils::*;\n\n  string name = \"sequencer_stub_ut\";\n  svunit_testcase svunit_ut;\n\n\n  class dummy_item;\n  endclass\n\n\n  sequencer_stub #(dummy_item) seqr;\n\n  function void build();\n    svunit_ut = new(name);\n    \n    seqr = new(\"sequencer_stub_unit_test_seqr\", null);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n\n  `SVUNIT_TESTS_BEGIN\n\n    `SVTEST(check_code_compiles)\n      \/\/ Try compiling with desired UVM version.\n    `SVTEST_END\n\n\n  `SVUNIT_TESTS_END\n\nendmodule\n","subject":"Add dummy unit test for sequencer_stub","message":"Add dummy unit test for sequencer_stub\n\nsequencer_stub cannot be compiled with UVM 1.2 in its current form. The\nonly purpose of these \"unit tests\" currently is to make sure it can be\ncompiled with all required UVM versions.\n","lang":"SystemVerilog","license":"apache-2.0","repos":"tudortimi\/vgm_svunit_utils,tudortimi\/vgm_svunit_utils"}
{"commit":"4e9b5ba1e193d9a574fa9175b789467c18aa9030","old_file":"test\/svlog\/ports\/nightmare.sv","new_file":"test\/svlog\/ports\/nightmare.sv","old_contents":"","new_contents":"\/\/ RUN: moore %s -e foo\n\/\/ IGNORE\n\nmodule foo (\n    .P1(x1[3:0]),\n    .P2(x1[7:0]),\n    .P3(x2),\n    P4,\n    .P5({x3, x4}),\n    {x5, x6}\n);\n    \/\/ This language needs to die.\n    output [7:0] x1;\n    ref x2;\n    input P4;\n    input x3, x5;\n    output x4, x6;\nendmodule\n","subject":"Add worst-case svlog port test case","message":"test: Add worst-case svlog port test case\n","lang":"SystemVerilog","license":"apache-2.0","repos":"fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore,fabianschuiki\/moore"}
{"commit":"8d9311a135f957670e46d473e5a41c292f06993c","old_file":"src\/test\/sv\/string_utils_unit_test.sv","new_file":"src\/test\/sv\/string_utils_unit_test.sv","old_contents":"","new_contents":"module string_utils_unit_test;\n\n  import svunit_pkg::*;\n  `include \"svunit_defines.svh\"\n\n  string name = \"string_utils_ut\";\n  svunit_testcase svunit_ut;\n\n  import svunit_under_test::string_utils;\n\n\n  function void build();\n    svunit_ut = new(name);\n  endfunction\n\n\n  task setup();\n    svunit_ut.setup();\n  endtask\n\n\n  task teardown();\n    svunit_ut.teardown();\n  endtask\n\n\n  `SVUNIT_TESTS_BEGIN\n\n    `SVTEST(some_passing_test)\n      `FAIL_UNLESS(svunit_under_test::TRUE)\n    `SVTEST_END\n\n  `SVUNIT_TESTS_END\n\nendmodule\n","subject":"Add test module which will contain tests for `string_utils`","message":"Add test module which will contain tests for `string_utils`\n","lang":"SystemVerilog","license":"apache-2.0","repos":"svunit\/svunit,svunit\/svunit,svunit\/svunit"}