Deploying waveform script for delayed test

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/clk_i
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/arst_i
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/srst
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/rx_i
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/tx_o
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/cpu_reset
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/gpio_bi
add wave -noupdate -radix hexadecimal /riscv_tb/riscv_udm/gpio_bo
add wave -noupdate -expand -group {udm bus} -radix hexadecimal /riscv_tb/riscv_udm/udm_reset
add wave -noupdate -expand -group bus_unit -radix hexadecimal /riscv_tb/riscv_udm/bus_unit/clk_i
add wave -noupdate -expand -group bus_unit -radix hexadecimal /riscv_tb/riscv_udm/bus_unit/rst_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IFETCH ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IFETCH ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IFETCH ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_active_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IFETCH ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_broken_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IFETCH ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_nextinstr_addr_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_active_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_broken_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_nextinstr_addr_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rd_addr_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_immediate_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rd_req_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rd_source_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_alu_opcode_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_op1_source_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_op2_source_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_jump_req_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_jump_src_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_mem_req_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_mem_cmd_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs1_rdata_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {IDECODE ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs2_rdata_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_active_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_broken_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_addr_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_req_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_source_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_mem_req_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_mem_cmd_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {EXEC ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_wdata_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_active_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_broken_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_addr_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_req_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_source_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_mem_req_ff
add wave -noupdate -expand -group {riscv instrpipe ffs} -expand -group {MEM ffs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_wdata_ff
add wave -noupdate -expand -group {riscv instrpipe combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_pc
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_jump_req_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_jump_vector_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_initiated
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_activereq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_breakreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_broken
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_new
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_repeatreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_working
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_succ
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_finish
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_stalled
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_flushreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_rdy
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_activereq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genpctrl_breakreq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_curinstr_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_nextinstr_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genmcopipe_instr_mem_genvar_req_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genmcopipe_instr_mem_genvar_rdreq_pending
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genmcopipe_instr_mem_genvar_resp_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IFETCH_genmcopipe_instr_mem_genvar_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_ack
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_be
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mcopipe_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mcopipe_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mcopipe_ack
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mcopipe_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_instr_mem_init_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_instr_mem_init_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_instr_mem_init_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_instr_mem_reqbuf_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_instr_mem_reqbuf_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_instr_mem_reqbuf_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IFETCH combs} -expand -group {riscv instr reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_instr_mem_reqbuf_rdy
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal -childformat {{{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[31]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[30]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[29]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[28]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[27]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[26]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[25]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[24]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[23]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[22]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[21]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[20]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[19]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[18]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[17]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[16]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[15]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[14]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[13]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[12]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[11]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[10]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[9]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[8]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[7]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[6]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[5]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[4]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[3]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[2]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[1]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[0]} -radix hexadecimal}} -expand -subitemconfig {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[31]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[30]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[29]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[28]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[27]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[26]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[25]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[24]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[23]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[22]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[21]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[20]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[19]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[18]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[17]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[16]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[15]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[14]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[13]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[12]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[11]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[10]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[9]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[8]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[7]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[6]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[5]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[4]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[3]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[2]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[1]} {-height 21 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile[0]} {-height 21 -radix hexadecimal}} /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_regfile
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_jump_req_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_jump_vector_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_initiated
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_activereq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_breakreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_broken
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_new
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_repeatreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_working
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_succ
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_finish
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_stalled
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_flushreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_rdy
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_activereq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genpctrl_breakreq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_curinstr_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_nextinstr_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_instr_code
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_opcode
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs1_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs1_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs1_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs2_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs2_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rs2_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_immediate_I
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_immediate_S
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_immediate_B
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_immediate_U
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_immediate_J
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_immediate
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rd_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rd_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_rd_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_alu_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_alu_opcode
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_alu_unsigned
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_op1_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_op2_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_funct3
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_funct7
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_shamt
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_pred
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_succ
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_csrnum
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_zimm
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_jump_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_jump_req_cond
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_jump_src
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_mem_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_mem_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genmcopipe_instr_mem_genvar_req_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genmcopipe_instr_mem_genvar_rdreq_pending
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genmcopipe_instr_mem_genvar_resp_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_IDECODE_genmcopipe_instr_mem_genvar_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -expand -group {riscv instr resp bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_resp
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -expand -group {riscv instr resp bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mem_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -expand -group {riscv instr resp bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mcopipe_resp
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {IDECODE combs} -expand -group {riscv instr resp bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/instr_mcopipe_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_jump_req_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpsticky_glbl_jump_vector_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_initiated
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_activereq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_breakreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_broken
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_new
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_repeatreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_working
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_succ
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_finish
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_stalled
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_flushreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_rdy
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_activereq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_genpctrl_breakreq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_curinstr_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_nextinstr_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rs1_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rs2_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_immediate
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_rd_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_op1_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_op2_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_opcode
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_unsigned
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_op1
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_op2
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_op1_wide
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_op2_wide
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_result_wide
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_result
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_CF
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_SF
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_ZF
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_OF
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_alu_overflow
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_jump_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_jump_req_cond
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_jump_vector
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_jump_src
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_funct3
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_mem_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_mem_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_mem_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {EXEC combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_EXEC_mem_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_initiated
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_activereq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_breakreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_broken
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_repeatreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_new
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_working
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_succ
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_finish
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_stalled
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_flushreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_rdy
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_activereq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genpctrl_breakreq_next
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_rd_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_mem_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_mem_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_mem_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_mem_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genmcopipe_data_mem_genvar_req_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genmcopipe_data_mem_genvar_rdreq_pending
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genmcopipe_data_mem_genvar_resp_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_MEM_genmcopipe_data_mem_genvar_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_ack
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_be
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mcopipe_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mcopipe_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mcopipe_ack
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data req bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mcopipe_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_data_mem_init_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_data_mem_init_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_data_mem_init_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_data_mem_reqbuf_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_data_mem_reqbuf_we
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_data_mem_reqbuf_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {MEM combs} -expand -group {riscv data reqbuf} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genmcopipe_data_mem_reqbuf_rdy
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/clk_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/rst_i
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_initiated
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_activereq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_breakreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_broken
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_repeatreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_new
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_working
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_succ
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_finish
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_stalled
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_flushreq
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genpctrl_rdy
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_rd_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_rd_addr
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_rd_wdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_rd_source
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_mem_req
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_mem_cmd
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_mem_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genmcopipe_data_mem_genvar_req_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genmcopipe_data_mem_genvar_rdreq_pending
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genmcopipe_data_mem_genvar_resp_done
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/genpproc_instrpipe_genpstage_WB_genmcopipe_data_mem_genvar_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -expand -group {riscv data resp bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_resp
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -expand -group {riscv data resp bus} -radix hexadecimal -childformat {{{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[31]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[30]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[29]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[28]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[27]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[26]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[25]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[24]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[23]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[22]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[21]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[20]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[19]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[18]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[17]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[16]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[15]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[14]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[13]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[12]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[11]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[10]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[9]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[8]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[7]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[6]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[5]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[4]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[3]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[2]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[1]} -radix hexadecimal} {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[0]} -radix hexadecimal}} -subitemconfig {{/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[31]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[30]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[29]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[28]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[27]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[26]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[25]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[24]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[23]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[22]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[21]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[20]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[19]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[18]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[17]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[16]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[15]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[14]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[13]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[12]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[11]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[10]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[9]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[8]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[7]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[6]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[5]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[4]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[3]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[2]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[1]} {-height 15 -radix hexadecimal} {/riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata[0]} {-height 15 -radix hexadecimal}} /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mem_rdata
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -expand -group {riscv data resp bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mcopipe_resp
add wave -noupdate -expand -group {riscv instrpipe combs} -expand -group {WB combs} -expand -group {riscv data resp bus} -radix hexadecimal /riscv_tb/riscv_udm/genblk1/cpu_test_wrapper/genblk1/riscv/data_mcopipe_rdata
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6144]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6145]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6146]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6147]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6148]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6149]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6150]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6151]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6152]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6153]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6154]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6155]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6156]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6157]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6158]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6159]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6160]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6161]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6162]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6163]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6164]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6165]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6166]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6167]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6168]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6169]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6170]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6171]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6172]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6173]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6174]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6175]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6176]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6177]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6178]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6179]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6180]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6181]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6182]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6183]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6184]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6185]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6186]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6187]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6188]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6189]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6190]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6191]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6192]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6193]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6194]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6195]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6196]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6197]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6198]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6199]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6200]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6201]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6202]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6203]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6204]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6205]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6206]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6207]}
add wave -noupdate -expand -group io_buf -radix decimal {/riscv_tb/riscv_udm/bus_unit/ram_dual_memsplit/ram_dual/ram[6208]}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {214216867 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 527
configure wave -valuecolwidth 104
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {1050 us}

error: pathspec 'designs/rtl/riscv_5stage_udm_memsplit/sim/modelsim_se_10.1/wave_test.do' did not match any file(s) known to git


ietoolkit - help file #124

ietoolkit - help file #124

fatal: unable to access 'https://github.com/worldbank/ietoolkit.git/': The requested URL returned error: 403


Create 00_SetupFolderGlobals.do

Create 00_SetupFolderGlobals.do

fatal: unable to access 'https://github.com/tessam30/Uganda.git/': The requested URL returned error: 403


isfolder : help file initiate

isfolder : help file initiate

{smcl}
{* 26 Dec 2016}{...}
{hline}
help for {hi:iematch}
{hline}

{title:Title}

{phang2}{cmdab:iefolder} {hline 2} Sets up folders and master do-files according to World Bank DIME's standards.

{title:Syntax}

{phang2}
{cmd:iefolder} new {it:itemtype} , {cmdab:proj:ectfolder(}{it:directory}{cmd:)}
	[{cmdab:abb:reviation(}{it:string}{cmd:)}]

{pmore} Where {it:itemtype} is either {it:project}, {it:round}, {it:master} or
	{it:unitofobs}. See details below.

{marker opts}{...}
{synoptset 22}{...}
{synopthdr:options}
{synoptline}
{synopt : {cmdab:proj:ectfolder(}{it:dir}{cmd:)}}The location where
	the {hi:DataWork} folder should be created (new projects), or
	where it is located (existing projects). {p_end}
{synopt : {cmdab:abb:reviation(}{it:string}{cmd:)}}Optional abbreviation
	of round name to be used to make globals shorter. {p_end}

{marker desc}
{title:Description}

{pstd}{cmdab:iematch} matches base observations towards target observations in terms
	of nearest value in {cmd:matchvar()}. Base observations are observations with
	value 1 in {cmd:grpdummy()} and target observations are observations with value
	0. For example, in a typical p-score match, base observations are treatment and
	target is control, however, there are many other examples of matching where it could
	be different.

{pstd}{cmdab:iematch} bases its matching algorithm on the Stable Marriage algorithm.
	This algorithm was chosen because it always provides a solution and allows stable
	matching even if multiple observations have identical match
	values (see {cmd:seed()} option for more details). One disadvantage of this
	algorithm is that it takes into account local efficiency only, and not global efficiency. This
	means that it is possible that other matching algorithms might generate a more
	efficient match in terms of the sum of the difference of all matched pairs/groups.

{marker optslong}
{title:Options}

{phang}{cmdab:proj:ectfolder(}{it:dir}{cmd:)} is

{phang}{cmdab:abb:reviation(}{it:string}{cmd:)} is

{title:Examples}

{pstd} {hi:Example 1.}

{pmore}{inp:iematch , grpdummy({it:tmt}) matchvar({it:p_hat})}

{pmore}In the example above, the observations with value 1 in {it:tmt} will be matched
	towards the nearest, in terms of {it:p_hat}, observations with value 0 in {it:tmt}.

{pstd} {hi:Example 2.}

{pmore}{inp:iematch if {it:baseline} == 1  , grpdummy({it:tmt}) matchvar({it:p_hat}) maxdiff(.001)}

{pmore}In the example above, the observations with value 1 in {it:tmt} will be matched
	towards the nearest, in terms of {it:p_hat}, observations with value 0 in {it:tmt} as
	long as the difference in {it:p_hat} is less than .001. Only observations that has the
	value 1 in variable {it:baseline} will be included in the match.

{title:Acknowledgements}

{phang}I would like to acknowledge the help in testing and proofreading I received in relation to this command and help file from (in alphabetic order):{p_end}
{pmore}Mrijan Rimal, Seungmin Lee, Laura Costica{break}

{title:Author}

{phang}Kristoffer Bjarkefur, The World Bank, DECIE

{phang}Please send bug-reports, suggestions and requests for clarifications
		 writing "ietoolkit iefolder" in the subject line to:{break}
		 kbjarkefur@worldbank.org

{phang}You can also see the code, make comments to the code, see the version
		 history of the code, and submit additions or edits to the code through
		 the github repository of ietoolkit:{break}
		 {browse "https://github.com/worldbank/ietoolkit"}

error: pathspec 'iefolder.sthlp' did not match any file(s) known to git


ensureado: like ensurelib, but for ado files.

Use this to install dependencies without user intervention.
Does not handle depdency versioning.

/* ensureado: automagically install missing commands.
 *
 * This is meant to glue over the lack of dependency tracking in Stata's .pkg format.
 *
 * syntax:
 * ensureado cmd, [pkg(package_name) from(url)]
 *
 * cmd: Stata will look for "cmd.ado" in its adopath.
 * pkg: if not given, the command and package are assumed to have the same name.
 * from: if given, install from that URL; otherwise install from the ssc.
 *
 * At the top of every piece of Stata code which has non-stdlib dependencies,
 *  declare them like this:
 *
 * // example.ado
 * ensureado norm                                     // Ansari & Mussida normalization library
 * ensureado psid, pkg(psidtools)                     // Kohler's panel income data API
 * ensureado boost, from("http://schonlau.net/stata") // Schonlau's machine learning boosting library
 * program define example {
 *   ...
 *   norm x
 *   boost x y z
 *   ...
 * }
 *
 * Nick Guenther <nguenthe@uwaterloo.ca> 2015
 * BSD License
 */
program define ensureado
  // parse arguments
  syntax name, [pkg(string) from(string)]
  local ado = "`namelist'"

  if("`pkg'"=="") {
    local pkg = "`ado'"
  }

  // test if `ado' is installed
  capture which `ado'
  if(_rc!=0) {
    // it's not, so install it
    if("`from'"!="") {
      net install `pkg', from(`from')
    }
    else {
      ssc install `pkg'
    }

    // recurse, to double-check the installation worked
    // DoS WARNING: this will cause an infinite loop
    //              if the remote package exists but
    //              does not include the named command.
    //   (but Stata has bigger security problems in its package system than a DoS)
    ensureado `ado'
  }
end

error: pathspec 'src/ensureado.ado' did not match any file(s) known to git


redo: adapt preliminary redo script from jgfs2 and AVRm68k

#!/bin/bash
# automaton
# (c) 2013 Justin Gottula
# The source code of this project is distributed under the terms of the
# simplified BSD license. See the LICENSE file for details.

exec >&2

TARGET=$1
TARGET_BASE=$2
OUTPUT=$3

CC="ccache avr-gcc"
AS="avr-as"
LD="avr-ld"
NM="avr-nm"
OBJCOPY="avr-objcopy"
OBJDUMP="avr-objdump"

PROJ_NAME="automaton"

MCU="atmega324a"
CPU_KHZ="20000"

DEFINES=("F_CPU=${CPU_KHZ}000UL")
INC_DIRS=()
LIB_DIRS=()
LIBS=()

CFLAGS_CPU=("-mmcu=$MCU" -fpack-struct -ffreestanding)
CFLAGS_DEBUG=(-ggdb)
CFLAGS_OPT=(-Os -flto -fuse-linker-plugin -fwhole-program)
CFLAGS_WARN=(-Wall -Wextra -Wno-unused-function)
CFLAGS_ETC=(-fno-diagnostics-show-caret)

CFLAGS="-std=gnu11 ${CFLAGS_CPU[@]} ${CFLAGS_DEBUG[@]} ${CFLAGS_OPT[@]} \
${CFLAGS_WARN[@]} ${CFLAGS_ETC[@]}"
CFLAGS_COMPILE="$CFLAGS ${DEFINES[@]/#/-D} ${INC_DIRS[@]/#/-I}"
CFLAGS_LINK="$CFLAGS ${LIB_DIRS[@]/#/-L} ${LIBS[@]/#/-l}"

SOURCES=$(find src -type f -iname '*.c')
OBJECTS=${SOURCES//.c/.o}

OUT_ELF="out/$PROJ_NAME.elf"
OUT_BIN="out/PROJ_NAME.bin"
OUT_HEX="out/PROJ_NAME.hex"
OUT_MAP="out/PROJ_NAME.map"
OUT_DUMP="out/PROJ_NAME.dump"

case "$TARGET" in
all)
	redo-ifchange $OUT_ELF $OUT_BIN $OUT_HEX $OUT_MAP $OUT_DUMP
	;;
$OUT_ELF)
	redo-ifchange $OBJECTS
	$CC $CFLAGS_LINK -o $OUTPUT $OBJECTS
	;;
$OUT_BIN)
	redo-ifchange $OUT_ELF
	$OBJCOPY -O binary $OUT_ELF $OUTPUT
	;;
$OUT_HEX)
	redo-ifchange $OUT_ELF
	$OBJCOPY -O ihex $OUT_ELF $OUTPUT
	;;
$OUT_MAP)
	redo-ifchange $OUT_ELF
	$NM -Cn $OUT_ELF >$OUTPUT
	;;
$OUT_DUMP)
	redo-ifchange $OUT_ELF
	$OBJDUMP -aCDfhpS $OUT_ELF >$OUTPUT
	;;
*.o)
	$CC $CFLAGS_COMPILE -o${TARGET//.o/.dep} -MM -MG ${TARGET//.o/.c}

	read DEPS <${TARGET//.o/.dep}
	redo-ifchange ${DEPS#*:}

	$CC $CFLAGS_COMPILE -o$OUTPUT -c ${TARGET//.o/.c}
	;;
clean)
	rm -rf $(find out -type f)
	rm -rf $(find src -type f -iname *.o)
	rm -rf $(find src -type f -iname *.dep)
	;;
sync)
	redo-ifchange $OUT_HEX
	echo "not implemented!"
	exit 1
	;;
*)
	echo "unknown target '$TARGET'"
	exit 1
	;;
esac

error: pathspec 'default.do' did not match any file(s) known to git


remove top line in signals.do

remove top line in signals.do

remote: Support for password authentication was removed on August 13, 2021.
remote: Please see https://docs.github.com/en/get-started/getting-started-with-git/about-remote-repositories#cloning-with-https-urls for information on currently recommended modes of authentication.
fatal: Authentication failed for 'https://github.com/bbrown1867/ObjectTracking.git/'


Create discretize.ado

Create discretize.ado

cap pr drop discretise
pr def discretise, rclass
	syntax varlist, GENerate(name) [CUTpoints(numlist) NBins(numlist)]
	if "`nbins'" != "" {
		loc increments = 100/`nbins'
		loc cutpoints ""
		forv i = `increments'(`increments')100 {
			if `i' < 100 {
				loc cutpoints `cutpoints' `i'
			}
		}
	}
	loc ncutpoints: list sizeof cutpoints
	loc resolved_list ""
	_pctile `varlist',p(`cutpoints')
	forv i = 1/`ncutpoints' {
		loc resolved_list `resolved_list', `r(r`i')'
 	}
 	loc resolved_list `=substr("`resolved_list'",2,.)'
 	g `generate'=irecode(`varlist',`resolved_list')+1
 	if "`nbins'" != "" {
 		qui su `generate'
 		qui replace `generate' = `nbins' if `generate' > `nbins'
 	}
 	return local r_cut "`resolved_list'"
end

error: pathspec 'discretize.ado' did not match any file(s) known to git


esttab t test table

esttab t test table

program t_test

use ${stash}master, clear

local flag `1'

keep if isb == `flag'
keep if year == 2013

labelvar

est clear
estpost ttest bd img text traf, by(treat)

esttab, wide nonumber cells(`"mu_1(fmt(a3)) mu_2(fmt(a3)) b(fmt(a3) nostar) p_l(fmt(2) par("{ralign @modelwidth:{txt:(}" "{txt:)}}"))"') mlabels("") collabels("in-copy mean" "out-of-copy mean" "diff" "p-val") noobs replace

esttab using "${tables}ttest_`flag'.tex", wide nonumber cells("mu_1(fmt(a3)) mu_2(fmt(a3)) b(fmt(a3) nostar) p_l(fmt(2))") collabels("\textbf{in-copy mean}" "\textbf{out-of-copy mean}" "\textbf{diff}" "\textbf{p-val}") noobs replace booktabs label

end

program labelvar

label variable img "\emph{Number of Images}"
label variable text "\emph{Number of Words of Text}"
label variable bd "\emph{Number of Citations to Baseball Digest}"
label variable traf "\emph{Average Monthly Traffic}"

end

error: pathspec 'scripts/stata/ado/t_test.ado' did not match any file(s) known to git


Added cscript.ado.

Added cscript.ado.

It is a copy of the StataCorp command:
*! version 3.6.0  04mar2013

*! version 3.6.0  04mar2013
program define cscript , rclass
	version 9
	set linesize 79
	while !("`1'" == "adofile" | "`1'"=="adofiles" | "`1'"=="") {
		local stuff `stuff' `1'
		mac shift
	}
	local dup = 79-6-length("`stuff'")
	di in smcl in gr "{hline `dup'}" `"BEGIN `stuff'"'

	mac shift			/* adofile[s] */
	while "`1'" != "" {
		di
		di "-> which `1'"
		which `1'
		mac shift
	}

	drop _all
	label drop _all
	macro drop _all
	macro drop S_*
	program drop _all
	scalar drop _all
	matrix drop _all
	constraint drop _all
	discard
	mata: mata clear
	set type float
	set maxiter 100
	set scheme s2color8
	set emptycells keep
	set showbaselevels
	set showemptycells
	set showomitted
	set lstretch
	set cformat
	set pformat
	set sformat
	set fvwrap 1
	set fvwrapon word
	set fvlabel on

	if "$S_FLAVOR"!="Small" {
		qui set matsize 400
	}

end

error: pathspec 'cscript/cscript.ado' did not match any file(s) known to git