LPC8xx: reduce stack sizes

LPC8xx: reduce stack sizes

git-svn-id: 30f789d7039adee4ab6dc5f7dbec2df9251e516b@5535 35acf78f-673a-0410-8e92-d51de3d6d3f4

/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                 2011,2012,2013 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/*
 * LPC812 memory setup.
 */
__main_stack_size__     = 0x0100;
__process_stack_size__  = 0x0100;

MEMORY
{
    flash : org = 0x00000000, len = 16k
    ram : org = 0x10000000, len = 4k
}

__ram_start__           = ORIGIN(ram);
__ram_size__            = LENGTH(ram);
__ram_end__             = __ram_start__ + __ram_size__;

ENTRY(ResetHandler)

SECTIONS
{
    . = 0;
    _text = .;

    startup : ALIGN(16) SUBALIGN(16)
    {
        KEEP(*(vectors))
    } > flash

    constructors : ALIGN(4) SUBALIGN(4)
    {
        PROVIDE(__init_array_start = .);
        KEEP(*(SORT(.init_array.*)))
        KEEP(*(.init_array))
        PROVIDE(__init_array_end = .);
    } > flash

    destructors : ALIGN(4) SUBALIGN(4)
    {
        PROVIDE(__fini_array_start = .);
        KEEP(*(.fini_array))
        KEEP(*(SORT(.fini_array.*)))
        PROVIDE(__fini_array_end = .);
    } > flash

    .text : ALIGN(16) SUBALIGN(16)
    {
        *(.text.startup.*)
        *(.text)
        *(.text.*)
        *(.rodata)
        *(.rodata.*)
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
    } > flash

    .ARM.extab :
    {
        *(.ARM.extab* .gnu.linkonce.armextab.*)
    } > flash

    .ARM.exidx : {
        PROVIDE(__exidx_start = .);
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
        PROVIDE(__exidx_end = .);
     } > flash

    .eh_frame_hdr :
    {
        *(.eh_frame_hdr)
    } > flash

    .eh_frame : ONLY_IF_RO
    {
        *(.eh_frame)
    } > flash

    .textalign : ONLY_IF_RO
    {
        . = ALIGN(8);
    } > flash

    _etext = .;
    _textdata = _etext;

    .stacks :
    {
        . = ALIGN(8);
        __main_stack_base__ = .;
        . += __main_stack_size__;
        . = ALIGN(8);
        __main_stack_end__ = .;
        __process_stack_base__ = .;
        __main_thread_stack_base__ = .;
        . += __process_stack_size__;
        . = ALIGN(8);
        __process_stack_end__ = .;
        __main_thread_stack_end__ = .;
    } > ram

    .data :
    {
        . = ALIGN(4);
        PROVIDE(_data = .);
        *(.data)
        . = ALIGN(4);
        *(.data.*)
        . = ALIGN(4);
        *(.ramtext)
        . = ALIGN(4);
        PROVIDE(_edata = .);
    } > ram AT > flash

    .bss :
    {
        . = ALIGN(4);
        PROVIDE(_bss_start = .);
        *(.bss)
        . = ALIGN(4);
        *(.bss.*)
        . = ALIGN(4);
        *(COMMON)
        . = ALIGN(4);
        PROVIDE(_bss_end = .);
    } > ram
}

PROVIDE(end = .);
_end            = .;

__heap_base__   = _end;
__heap_end__    = __ram_end__;

/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                 2011,2012,2013 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/*
 * LPC812 memory setup.
 */
__main_stack_size__     = 0x0200;
__process_stack_size__  = 0x0200;

MEMORY
{
    flash : org = 0x00000000, len = 16k
    ram : org = 0x10000000, len = 4k
}

__ram_start__           = ORIGIN(ram);
__ram_size__            = LENGTH(ram);
__ram_end__             = __ram_start__ + __ram_size__;

ENTRY(ResetHandler)

SECTIONS
{
    . = 0;
    _text = .;

    startup : ALIGN(16) SUBALIGN(16)
    {
        KEEP(*(vectors))
    } > flash

    constructors : ALIGN(4) SUBALIGN(4)
    {
        PROVIDE(__init_array_start = .);
        KEEP(*(SORT(.init_array.*)))
        KEEP(*(.init_array))
        PROVIDE(__init_array_end = .);
    } > flash

    destructors : ALIGN(4) SUBALIGN(4)
    {
        PROVIDE(__fini_array_start = .);
        KEEP(*(.fini_array))
        KEEP(*(SORT(.fini_array.*)))
        PROVIDE(__fini_array_end = .);
    } > flash

    .text : ALIGN(16) SUBALIGN(16)
    {
        *(.text.startup.*)
        *(.text)
        *(.text.*)
        *(.rodata)
        *(.rodata.*)
        *(.glue_7t)
        *(.glue_7)
        *(.gcc*)
    } > flash

    .ARM.extab :
    {
        *(.ARM.extab* .gnu.linkonce.armextab.*)
    } > flash

    .ARM.exidx : {
        PROVIDE(__exidx_start = .);
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
        PROVIDE(__exidx_end = .);
     } > flash

    .eh_frame_hdr :
    {
        *(.eh_frame_hdr)
    } > flash

    .eh_frame : ONLY_IF_RO
    {
        *(.eh_frame)
    } > flash

    .textalign : ONLY_IF_RO
    {
        . = ALIGN(8);
    } > flash

    _etext = .;
    _textdata = _etext;

    .stacks :
    {
        . = ALIGN(8);
        __main_stack_base__ = .;
        . += __main_stack_size__;
        . = ALIGN(8);
        __main_stack_end__ = .;
        __process_stack_base__ = .;
        __main_thread_stack_base__ = .;
        . += __process_stack_size__;
        . = ALIGN(8);
        __process_stack_end__ = .;
        __main_thread_stack_end__ = .;
    } > ram

    .data :
    {
        . = ALIGN(4);
        PROVIDE(_data = .);
        *(.data)
        . = ALIGN(4);
        *(.data.*)
        . = ALIGN(4);
        *(.ramtext)
        . = ALIGN(4);
        PROVIDE(_edata = .);
    } > ram AT > flash

    .bss :
    {
        . = ALIGN(4);
        PROVIDE(_bss_start = .);
        *(.bss)
        . = ALIGN(4);
        *(.bss.*)
        . = ALIGN(4);
        *(COMMON)
        . = ALIGN(4);
        PROVIDE(_bss_end = .);
    } > ram
}

PROVIDE(end = .);
_end            = .;

__heap_base__   = _end;
__heap_end__    = __ram_end__;


Hide two inherited symbols with the version script.

We inherit facilitynames and prioritynames from syslog.h, but they
should not be exported by us.

Signed-off-by: Gergely Nagy <6780fac3b38619ac20422286e4110a70dbba2203@balabit.hu>

LIBCEE_SYSLOG_0.1.0 {
	global:
        # Our own symbols
          cee_format;
          cee_vformat;
          cee_syslog;
          cee_vsyslog;
          cee_legacy_syslog;
          cee_legacy_vsyslog;
          cee_openlog;
          cee_setlogmask;
        # Overrides
          syslog;
          vsyslog;
          openlog;
          setlogmask;

	local:
        # Inherited from elsewhere, but should not be exported
          facilitynames;
          prioritynames;
};

LIBCEE_SYSLOG_0.1.0 {
	global:
        # Our own symbols
          cee_format;
          cee_vformat;
          cee_syslog;
          cee_vsyslog;
          cee_legacy_syslog;
          cee_legacy_vsyslog;
          cee_openlog;
          cee_setlogmask;
        # Overrides
          syslog;
          vsyslog;
          openlog;
          setlogmask;
};


Fix linker script's boot size to match bsp.yml

/*
 * Licensed to the Apache Software Foundation (ASF) under one
 * or more contributor license agreements.  See the NOTICE file
 * distributed with this work for additional information
 * regarding copyright ownership.  The ASF licenses this file
 * to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance
 * with the License.  You may obtain a copy of the License at
 *
 *  http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing,
 * software distributed under the License is distributed on an
 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
 * KIND, either express or implied.  See the License for the
 * specific language governing permissions and limitations
 * under the License.
 */

/* Linker script to configure memory regions. */
MEMORY
{
  FLASH (rx) :  ORIGIN = 0x08000000, LENGTH = 16K
  CCM (rwx) :   ORIGIN = 0x10000000, LENGTH = 64K
  RAM (rwx) :   ORIGIN = 0x20000000, LENGTH = 128K
}

/* The bootloader does not contain an image header */
_imghdr_size = 0x0;

/*
 * Licensed to the Apache Software Foundation (ASF) under one
 * or more contributor license agreements.  See the NOTICE file
 * distributed with this work for additional information
 * regarding copyright ownership.  The ASF licenses this file
 * to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance
 * with the License.  You may obtain a copy of the License at
 *
 *  http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing,
 * software distributed under the License is distributed on an
 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
 * KIND, either express or implied.  See the License for the
 * specific language governing permissions and limitations
 * under the License.
 */

/* Linker script to configure memory regions. */
MEMORY
{
  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
}

/* The bootloader does not contain an image header */
_imghdr_size = 0x0;


Temp stack was misaligned by 1 byte(!?)

Temp stack was misaligned by 1 byte(!?)

/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt */
boot_paddr   	   = 0x007c00;		/* boot offset */
kernel_paddr       = 0x100000;
kernel_vaddr_off   = 0xffffffff00000000;
kernel_vaddr 	   = kernel_vaddr_off + kernel_paddr;
kernel_pos   	   = 0x001000;		/* physical position in output */
kernel_stack_paddr = 0xa00000;
kernel_size 	   = SIZEOF(.kernel);
user_vaddr 	   = 0x600000;
user_size	   = SIZEOF(.user);
user_pos 	   = kernel_pos + _user_start;
kdata_base	   = 0x00200000;
idt_paddr	   = 0x00201000;
percpu_paddr	   = 0x00202000;
percpu_tbl_paddr   = 0x00202000;
gdt_paddr 	   = 0x00203000;
page_table_paddr   = 0x00400000;
user_paddr	   = 0x00600000;

cpu_stack_size     = 0x400;

SECTIONS
{
	.boot-setup boot_paddr :
	{
		*(.boot)
		setup_pos = .;
		*(.setup)
	}

	.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)
	{
		*.ko(.text)
		*.ko(.data*)
		*.ko(.rodata*)
		*.ko(COMMON*)
		*.ko(.bss*)
		/*
		 * We need to align the start of user to 512 so that we can load
		 * it cleanly as an ATA LSB
		 */
		_user_start = ALIGN(512) - kernel_vaddr;
	}

	.user user_vaddr : AT(LOADADDR(.kernel) + _user_start)
	{
		*.o(.text)
		*.o(.data*)
		*.o(.rodata*)
		*.o(COMMON*)
		*.o(.bss*)
	}

	/DISCARD/ :
	{
		*(.eh_frame)
		*(.comment)
	}
}

/* Copyright (C) 2016 by Soren Telfer - MIT License. See LICENSE.txt */
boot_paddr   	   = 0x007c00;		/* boot offset */
kernel_paddr       = 0x100000;
kernel_vaddr_off   = 0xffffffff00000000;
kernel_vaddr 	   = kernel_vaddr_off + kernel_paddr;
kernel_pos   	   = 0x001000;		/* physical position in output */
kernel_stack_paddr = 0x009fffff;
kernel_size 	   = SIZEOF(.kernel);
user_vaddr 	   = 0x600000;
user_size	   = SIZEOF(.user);
user_pos 	   = kernel_pos + _user_start;
kdata_base	   = 0x00200000;
idt_paddr	   = 0x00201000;
percpu_paddr	   = 0x00202000;
percpu_tbl_paddr   = 0x00202000;
gdt_paddr 	   = 0x00203000;
page_table_paddr   = 0x00400000;
user_paddr	   = 0x00600000;

cpu_stack_size     = 0x400;

SECTIONS
{
	.boot-setup boot_paddr :
	{
		*(.boot)
		setup_pos = .;
		*(.setup)
	}

	.kernel kernel_vaddr : AT(boot_paddr + kernel_pos)
	{
		*.ko(.text)
		*.ko(.data*)
		*.ko(.rodata*)
		*.ko(COMMON*)
		*.ko(.bss*)
		/*
		 * We need to align the start of user to 512 so that we can load
		 * it cleanly as an ATA LSB
		 */
		_user_start = ALIGN(512) - kernel_vaddr;
	}

	.user user_vaddr : AT(LOADADDR(.kernel) + _user_start)
	{
		*.o(.text)
		*.o(.data*)
		*.o(.rodata*)
		*.o(COMMON*)
		*.o(.bss*)
	}

	/DISCARD/ :
	{
		*(.eh_frame)
		*(.comment)
	}
}


Updated link.ld to fix tabbing + add stuff for tests

ENTRY(_start)

SECTIONS {
	. = 0x100000;
	start = .;

	.debug_info : {
		debug_info_start = .;
		*(.debug_info)
		debug_info_end = .;
	}

	.text : ALIGN (0x1000) {
		*(.mboot)
		*(.text)
	}

	.rodata ALIGN (0x1000) : {
		*(.rodata)
	}

	.data ALIGN (0x1000) : {
		*(.data)
		start_initial_tests = .;
		*(initial_tests)
		end_initial_tests = .;
		start_other_tests = .;
		*(other_tests*)
		end_other_tests = .;
	}

	.bss ALIGN (0x1000) : {
		sbss = .;
		*(COMMON)
		*(.bss)
		ebss = .;
	}

	end = .;
}

ENTRY(_start)

SECTIONS {
	. = 0x100000;
	start = .;

  .debug_info : {
    debug_info_start = .;
    *(.debug_info)
    debug_info_end = .;
  }

	.text : ALIGN (0x1000) {
		*(.mboot)
		*(.text)
	}

	.rodata ALIGN (0x1000) : {
		*(.rodata)
	}

	.data ALIGN (0x1000) : {
		*(.data)
	}

	.bss ALIGN (0x1000) : {
		sbss = .;
		*(COMMON)
		*(.bss)
		ebss = .;
	}

	end = .;
}


linker: make _sram_origin lowercase

linker: make _sram_origin lowercase

Co-authored-by: Pat Pannuto <6364fafe2fb638c2c195524856b7e850805ec613@gmail.com>

/* Userland Generic Layout
 *
 * This linker script is designed for Tock apps where the end microcontroller
 * is not known. Therefore, this script over provisions space on some platforms.
 */

/* Memory Spaces Definitions, 448K flash, 64K ram */
PROG_LENGTH = 0x00040000;
RAM_LENGTH  = 0x00010000;

ENTRY(_start)

/* Note: On platforms where apps are position-independent and relocatable, the
 * FLASH address here acts as a sentinel value for relocation fixup routines.
 * The application loader will select the actual location in flash where the app
 * is placed. On platforms where apps are compiled for fixed addresses, these
 * addresses will be changed automatically before the linking step.
 */
MEMORY {
    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH
    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH
}

SECTIONS {
    /* Section for just the app crt0 header.
     * This must be first so that the app can find it.
     */
    .crt0_header :
    {
        /**
         * Populate the header expected by `crt0`:
         *
         *  struct hdr {
         *    uint32_t got_sym_start;
         *    uint32_t got_start;
         *    uint32_t got_size;
         *    uint32_t data_sym_start;
         *    uint32_t data_start;
         *    uint32_t data_size;
         *    uint32_t bss_start;
         *    uint32_t bss_size;
         *    uint32_t reldata_start;
         *    uint32_t stack_size;
         *  };
         */
        /* Offset of GOT symbols in flash from the start of the application
         * binary. */
        LONG(LOADADDR(.got) - ORIGIN(FLASH));
        /* Offset of where the GOT section will be placed in memory from the
         * beginning of the app's assigned memory. */
        LONG(_got - ORIGIN(SRAM));
        /* Size of GOT section. */
        LONG(SIZEOF(.got));
        /* Offset of data symbols in flash from the start of the application
         * binary. */
        LONG(LOADADDR(.data) - ORIGIN(FLASH));
        /* Offset of where the data section will be placed in memory from the
         * beginning of the app's assigned memory. */
        LONG(_data - ORIGIN(SRAM));
        /* Size of data section. */
        LONG(SIZEOF(.data));
        /* Offset of where the BSS section will be placed in memory from the
         * beginning of the app's assigned memory. */
        LONG(_bss - ORIGIN(SRAM));
        /* Size of BSS section */
        LONG(SIZEOF(.bss));
        /* First address offset after program flash, where elf2tab places
         * .rel.data section */
        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));
        /* The size of the stack requested by this application */
        LONG(STACK_SIZE);
    } > FLASH =0xFF

    /* App state section. Used for persistent app data.
     * We put this first so that if the app code changes but the persistent
     * data doesn't, the app_state can be preserved.
     */
    .wfr.app_state :
    {
        KEEP (*(.app_state))
        . = ALIGN(4); /* Make sure we're word-aligned here */
    } > FLASH =0xFF

    /* Text section, Code! */
    .text :
    {
        . = ALIGN(4);
        _text = .;
        KEEP (*(.start))
        *(.text*)
        *(.rodata*)
        KEEP (*(.syscalls))
        _etext = .;
        *(.ARM.extab*)
        . = ALIGN(4); /* Make sure we're word-aligned here */
    } > FLASH =0xFF

    /* Need to reserve room for the stack in the linker file. This makes the
     * _got addresses used by the compiler match what they will be when the
     * app is loaded into memory. This is not necessary for full PIC supported
     * platforms (like Cortex-M), but is needed when an app is compiled for a
     * fixed address.
     */
    .stack :
    {
        /* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to
		 * mark the first address in the SRAM memory. Since ELF files do
		 * not really need to specify this address as they only care about
		 * loading into flash, we need to manually mark this address for
		 * elf2tab. elf2tab will use it to add a fixed address header in the
		 * TBF header if needed.
		 */
	    _sram_origin = .;

        /* Be conservative about our alignment for the stack. Different
         * architectures require different values (8 for ARM, 16 for RISC-V),
         * so we choose the largest value. In practice, this likely will not
         * matter since the start of SRAM is unlikely to be at a very peculiar
         * address.
         */
        . = ALIGN(16);
        _stack = .;
        . = _stack + STACK_SIZE;
        . = ALIGN(16);
    } > SRAM

    /* Global Offset Table */
    .got :
    {
        . = ALIGN(4); /* Make sure we're word-aligned here */
        _got = .;
        *(.got*)
        *(.got.plt*)
        . = ALIGN(4);
    } > SRAM AT > FLASH

    /* Data section, static initialized variables
     *  Note: This is placed in Flash after the text section, but needs to be
     *  moved to SRAM at runtime
     */
    .data :
    {
        . = ALIGN(4); /* Make sure we're word-aligned here */
        _data = .;
        KEEP(*(.data*))
        /* Include the "small data" in the data section. Otherwise it will be
         * dropped when the TBF is created.
         */
        KEEP(*(.sdata*))
        . = ALIGN(4); /* Make sure we're word-aligned at the end of flash */
    } > SRAM AT > FLASH

    /* BSS section, static uninitialized variables */
    .bss :
    {
        . = ALIGN(4); /* Make sure we're word-aligned here */
        _bss = .;
        KEEP(*(.bss*))
        *(COMMON)
        . = ALIGN(4);
    } > SRAM

    /* End of flash. */
    .endflash :
    {
    } > FLASH

    /* ARM Exception support
     *
     * This contains compiler-generated support for unwinding the stack,
     * consisting of key-value pairs of function addresses and information on
     * how to unwind stack frames.
     * https://wiki-archive.linaro.org/KenWerner/Sandbox/libunwind
     * (See also https://github.com/tock/libtock-c/issues/48)
     *
     *
     * .ARM.exidx is sorted, so has to go in its own output section.
     *
     * __NOTE__: It's at the end because we currently don't actually serialize
     * it to the binary in elf2tab. If it was before the RAM sections, it would
     * through off our calculations of the header.
     */
    PROVIDE_HIDDEN (__exidx_start = .);
    .ARM.exidx :
    {
      /* (C++) Index entries for section unwinding */
      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
    } > FLASH
    PROVIDE_HIDDEN (__exidx_end = .);
}

ASSERT(_got <= _bss, "
The GOT section must be before the BSS section for crt0 setup to be correct.");
ASSERT(_data <= _bss, "
The data section must be before the BSS section for crt0 setup to be correct.");

/* Userland Generic Layout
 *
 * This linker script is designed for Tock apps where the end microcontroller
 * is not known. Therefore, this script over provisions space on some platforms.
 */

/* Memory Spaces Definitions, 448K flash, 64K ram */
PROG_LENGTH = 0x00040000;
RAM_LENGTH  = 0x00010000;

ENTRY(_start)

/* Note: On platforms where apps are position-independent and relocatable, the
 * FLASH address here acts as a sentinel value for relocation fixup routines.
 * The application loader will select the actual location in flash where the app
 * is placed. On platforms where apps are compiled for fixed addresses, these
 * addresses will be changed automatically before the linking step.
 */
MEMORY {
    FLASH (rx) : ORIGIN = 0x80000000, LENGTH = PROG_LENGTH
    SRAM (RWX) : ORIGIN = 0x00000000, LENGTH = RAM_LENGTH
}

SECTIONS {
    /* Section for just the app crt0 header.
     * This must be first so that the app can find it.
     */
    .crt0_header :
    {
        /**
         * Populate the header expected by `crt0`:
         *
         *  struct hdr {
         *    uint32_t got_sym_start;
         *    uint32_t got_start;
         *    uint32_t got_size;
         *    uint32_t data_sym_start;
         *    uint32_t data_start;
         *    uint32_t data_size;
         *    uint32_t bss_start;
         *    uint32_t bss_size;
         *    uint32_t reldata_start;
         *    uint32_t stack_size;
         *  };
         */
        /* Offset of GOT symbols in flash from the start of the application
         * binary. */
        LONG(LOADADDR(.got) - ORIGIN(FLASH));
        /* Offset of where the GOT section will be placed in memory from the
         * beginning of the app's assigned memory. */
        LONG(_got - ORIGIN(SRAM));
        /* Size of GOT section. */
        LONG(SIZEOF(.got));
        /* Offset of data symbols in flash from the start of the application
         * binary. */
        LONG(LOADADDR(.data) - ORIGIN(FLASH));
        /* Offset of where the data section will be placed in memory from the
         * beginning of the app's assigned memory. */
        LONG(_data - ORIGIN(SRAM));
        /* Size of data section. */
        LONG(SIZEOF(.data));
        /* Offset of where the BSS section will be placed in memory from the
         * beginning of the app's assigned memory. */
        LONG(_bss - ORIGIN(SRAM));
        /* Size of BSS section */
        LONG(SIZEOF(.bss));
        /* First address offset after program flash, where elf2tab places
         * .rel.data section */
        LONG(LOADADDR(.endflash) - ORIGIN(FLASH));
        /* The size of the stack requested by this application */
        LONG(STACK_SIZE);
    } > FLASH =0xFF

    /* App state section. Used for persistent app data.
     * We put this first so that if the app code changes but the persistent
     * data doesn't, the app_state can be preserved.
     */
    .wfr.app_state :
    {
        KEEP (*(.app_state))
        . = ALIGN(4); /* Make sure we're word-aligned here */
    } > FLASH =0xFF

    /* Text section, Code! */
    .text :
    {
        . = ALIGN(4);
        _text = .;
        KEEP (*(.start))
        *(.text*)
        *(.rodata*)
        KEEP (*(.syscalls))
        _etext = .;
        *(.ARM.extab*)
        . = ALIGN(4); /* Make sure we're word-aligned here */
    } > FLASH =0xFF

    /* Need to reserve room for the stack in the linker file. This makes the
     * _got addresses used by the compiler match what they will be when the
     * app is loaded into memory. This is not necessary for full PIC supported
     * platforms (like Cortex-M), but is needed when an app is compiled for a
     * fixed address.
     */
    .stack :
    {
        /* elf2tab requires that the `_SRAM_ORIGIN` symbol be present to
		 * mark the first address in the SRAM memory. Since ELF files do
		 * not really need to specify this address as they only care about
		 * loading into flash, we need to manually mark this address for
		 * elf2tab. elf2tab will use it to add a fixed address header in the
		 * TBF header if needed.
		 */
	    _SRAM_ORIGIN = .;

        /* Be conservative about our alignment for the stack. Different
         * architectures require different values (8 for ARM, 16 for RISC-V),
         * so we choose the largest value. In practice, this likely will not
         * matter since the start of SRAM is unlikely to be at a very peculiar
         * address.
         */
        . = ALIGN(16);
        _stack = .;
        . = _stack + STACK_SIZE;
        . = ALIGN(16);
    } > SRAM

    /* Global Offset Table */
    .got :
    {
        . = ALIGN(4); /* Make sure we're word-aligned here */
        _got = .;
        *(.got*)
        *(.got.plt*)
        . = ALIGN(4);
    } > SRAM AT > FLASH

    /* Data section, static initialized variables
     *  Note: This is placed in Flash after the text section, but needs to be
     *  moved to SRAM at runtime
     */
    .data :
    {
        . = ALIGN(4); /* Make sure we're word-aligned here */
        _data = .;
        KEEP(*(.data*))
        /* Include the "small data" in the data section. Otherwise it will be
         * dropped when the TBF is created.
         */
        KEEP(*(.sdata*))
        . = ALIGN(4); /* Make sure we're word-aligned at the end of flash */
    } > SRAM AT > FLASH

    /* BSS section, static uninitialized variables */
    .bss :
    {
        . = ALIGN(4); /* Make sure we're word-aligned here */
        _bss = .;
        KEEP(*(.bss*))
        *(COMMON)
        . = ALIGN(4);
    } > SRAM

    /* End of flash. */
    .endflash :
    {
    } > FLASH

    /* ARM Exception support
     *
     * This contains compiler-generated support for unwinding the stack,
     * consisting of key-value pairs of function addresses and information on
     * how to unwind stack frames.
     * https://wiki-archive.linaro.org/KenWerner/Sandbox/libunwind
     * (See also https://github.com/tock/libtock-c/issues/48)
     *
     *
     * .ARM.exidx is sorted, so has to go in its own output section.
     *
     * __NOTE__: It's at the end because we currently don't actually serialize
     * it to the binary in elf2tab. If it was before the RAM sections, it would
     * through off our calculations of the header.
     */
    PROVIDE_HIDDEN (__exidx_start = .);
    .ARM.exidx :
    {
      /* (C++) Index entries for section unwinding */
      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
    } > FLASH
    PROVIDE_HIDDEN (__exidx_end = .);
}

ASSERT(_got <= _bss, "
The GOT section must be before the BSS section for crt0 setup to be correct.");
ASSERT(_data <= _bss, "
The data section must be before the BSS section for crt0 setup to be correct.");


move to libm to flash in case of future use

/* This linker script generated from xt-genldscripts.tpp for LSP . */
/* Linker Script for ld -N */
MEMORY
{
  dport0_0_seg :                        org = 0x3FF00000, len = 0x10
  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000
  iram1_0_seg :                         org = 0x40100000, len = 0x8000
  irom0_0_seg :                         org = 0x40210000, len = 0x58000
}

PHDRS
{
  dport0_0_phdr PT_LOAD;
  dram0_0_phdr PT_LOAD;
  dram0_0_bss_phdr PT_LOAD;
  iram1_0_phdr PT_LOAD;
  irom0_0_phdr PT_LOAD;
}

/*  Default entry point:  */
ENTRY(call_user_start)
EXTERN(_DebugExceptionVector)
EXTERN(_DoubleExceptionVector)
EXTERN(_KernelExceptionVector)
EXTERN(_NMIExceptionVector)
EXTERN(_UserExceptionVector)
PROVIDE(_memmap_vecbase_reset = 0x40000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00000110;
_memmap_cacheattr_wt_base = 0x00000110;
_memmap_cacheattr_bp_base = 0x00000220;
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
_memmap_cacheattr_wb_trapnull = 0x2222211F;
_memmap_cacheattr_wba_trapnull = 0x2222211F;
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
_memmap_cacheattr_wt_trapnull = 0x2222211F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
_memmap_cacheattr_wb_allvalid = 0x22222112;
_memmap_cacheattr_wt_allvalid = 0x22222112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);

SECTIONS
{

  .dport0.rodata : ALIGN(4)
  {
    _dport0_rodata_start = ABSOLUTE(.);
    *(.dport0.rodata)
    *(.dport.rodata)
    _dport0_rodata_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .dport0.literal : ALIGN(4)
  {
    _dport0_literal_start = ABSOLUTE(.);
    *(.dport0.literal)
    *(.dport.literal)
    _dport0_literal_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .dport0.data : ALIGN(4)
  {
    _dport0_data_start = ABSOLUTE(.);
    *(.dport0.data)
    *(.dport.data)
    _dport0_data_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .data : ALIGN(4)
  {
    _data_start = ABSOLUTE(.);
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
    *(.data1)
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    *(.jcr)
    _data_end = ABSOLUTE(.);
  } >dram0_0_seg :dram0_0_phdr

  .rodata : ALIGN(4)
  {
    _rodata_start = ABSOLUTE(.);
    *(.sdk.version)
    *(.rodata)
    *(.rodata.*)
    *(.gnu.linkonce.r.*)
    *(.rodata1)
    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
    *(.xt_except_table)
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
    *(.eh_frame)
    /*  C++ constructor and destructor tables, properly ordered:  */
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    /*  C++ exception handlers table:  */
    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
    *(.xt_except_desc)
    *(.gnu.linkonce.h.*)
    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
    *(.xt_except_desc_end)
    *(.dynamic)
    *(.gnu.version_d)
    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
    _bss_table_start = ABSOLUTE(.);
    LONG(_bss_start)
    LONG(_bss_end)
    _bss_table_end = ABSOLUTE(.);
    _rodata_end = ABSOLUTE(.);
  } >dram0_0_seg :dram0_0_phdr

  .bss ALIGN(8) (NOLOAD) : ALIGN(4)
  {
    . = ALIGN (8);
    _bss_start = ABSOLUTE(.);
    *(.dynsbss)
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    *(.scommon)
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    *(.dynbss)
    *(.bss)
    *(.bss.*)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN (8);
    _bss_end = ABSOLUTE(.);
    _heap_start = ABSOLUTE(.);
/*    _stack_sentry = ALIGN(0x8); */
  } >dram0_0_seg :dram0_0_bss_phdr
/* __stack = 0x3ffc8000; */

  .irom0.text : ALIGN(4)
  {
    _irom0_text_start = ABSOLUTE(.);
    *libm.a:(.literal .text .literal.* .text.*)
    *libmbedtls.a:(.literal .text .literal.* .text.*)

    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
    _irom0_text_end = ABSOLUTE(.);
  } >irom0_0_seg :irom0_0_phdr

  .text : ALIGN(4)
  {
    _stext = .;
    _text_start = ABSOLUTE(.);
    *(.UserEnter.text)
    . = ALIGN(16);
    *(.DebugExceptionVector.text)
    . = ALIGN(16);
    *(.NMIExceptionVector.text)
    . = ALIGN(16);
    *(.KernelExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN(16);
    *(.UserExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN(16);
    *(.DoubleExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN (16);
    *(.entry.text)
    *(.init.literal)
    *(.init)
    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
    *(.fini.literal)
    *(.fini)
    *(.gnu.version)
    _text_end = ABSOLUTE(.);
    _etext = .;
  } >iram1_0_seg :iram1_0_phdr

  .lit4 : ALIGN(4)
  {
    _lit4_start = ABSOLUTE(.);
    *(*.lit4)
    *(.lit4.*)
    *(.gnu.linkonce.lit4.*)
    _lit4_end = ABSOLUTE(.);
  } >iram1_0_seg :iram1_0_phdr
}

/* get ROM code address */
INCLUDE "../sdk/ld/eagle.rom.addr.v6.ld"

/* This linker script generated from xt-genldscripts.tpp for LSP . */
/* Linker Script for ld -N */
MEMORY
{
  dport0_0_seg :                        org = 0x3FF00000, len = 0x10
  dram0_0_seg :                         org = 0x3FFE8000, len = 0x14000
  iram1_0_seg :                         org = 0x40100000, len = 0x8000
  irom0_0_seg :                         org = 0x40210000, len = 0x58000
}

PHDRS
{
  dport0_0_phdr PT_LOAD;
  dram0_0_phdr PT_LOAD;
  dram0_0_bss_phdr PT_LOAD;
  iram1_0_phdr PT_LOAD;
  irom0_0_phdr PT_LOAD;
}

/*  Default entry point:  */
ENTRY(call_user_start)
EXTERN(_DebugExceptionVector)
EXTERN(_DoubleExceptionVector)
EXTERN(_KernelExceptionVector)
EXTERN(_NMIExceptionVector)
EXTERN(_UserExceptionVector)
PROVIDE(_memmap_vecbase_reset = 0x40000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00000110;
_memmap_cacheattr_wt_base = 0x00000110;
_memmap_cacheattr_bp_base = 0x00000220;
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
_memmap_cacheattr_wb_trapnull = 0x2222211F;
_memmap_cacheattr_wba_trapnull = 0x2222211F;
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
_memmap_cacheattr_wt_trapnull = 0x2222211F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
_memmap_cacheattr_wb_allvalid = 0x22222112;
_memmap_cacheattr_wt_allvalid = 0x22222112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);

SECTIONS
{

  .dport0.rodata : ALIGN(4)
  {
    _dport0_rodata_start = ABSOLUTE(.);
    *(.dport0.rodata)
    *(.dport.rodata)
    _dport0_rodata_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .dport0.literal : ALIGN(4)
  {
    _dport0_literal_start = ABSOLUTE(.);
    *(.dport0.literal)
    *(.dport.literal)
    _dport0_literal_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .dport0.data : ALIGN(4)
  {
    _dport0_data_start = ABSOLUTE(.);
    *(.dport0.data)
    *(.dport.data)
    _dport0_data_end = ABSOLUTE(.);
  } >dport0_0_seg :dport0_0_phdr

  .data : ALIGN(4)
  {
    _data_start = ABSOLUTE(.);
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
    *(.data1)
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    *(.jcr)
    _data_end = ABSOLUTE(.);
  } >dram0_0_seg :dram0_0_phdr

  .rodata : ALIGN(4)
  {
    _rodata_start = ABSOLUTE(.);
    *(.sdk.version)
    *(.rodata)
    *(.rodata.*)
    *(.gnu.linkonce.r.*)
    *(.rodata1)
    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
    *(.xt_except_table)
    *(.gcc_except_table)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
    *(.eh_frame)
    /*  C++ constructor and destructor tables, properly ordered:  */
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    /*  C++ exception handlers table:  */
    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
    *(.xt_except_desc)
    *(.gnu.linkonce.h.*)
    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
    *(.xt_except_desc_end)
    *(.dynamic)
    *(.gnu.version_d)
    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
    _bss_table_start = ABSOLUTE(.);
    LONG(_bss_start)
    LONG(_bss_end)
    _bss_table_end = ABSOLUTE(.);
    _rodata_end = ABSOLUTE(.);
  } >dram0_0_seg :dram0_0_phdr

  .bss ALIGN(8) (NOLOAD) : ALIGN(4)
  {
    . = ALIGN (8);
    _bss_start = ABSOLUTE(.);
    *(.dynsbss)
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    *(.scommon)
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    *(.dynbss)
    *(.bss)
    *(.bss.*)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN (8);
    _bss_end = ABSOLUTE(.);
    _heap_start = ABSOLUTE(.);
/*    _stack_sentry = ALIGN(0x8); */
  } >dram0_0_seg :dram0_0_bss_phdr
/* __stack = 0x3ffc8000; */

  .irom0.text : ALIGN(4)
  {
    _irom0_text_start = ABSOLUTE(.);

    *libmbedtls.a:(.literal .text .literal.* .text.*)

    *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
    _irom0_text_end = ABSOLUTE(.);
  } >irom0_0_seg :irom0_0_phdr

  .text : ALIGN(4)
  {
    _stext = .;
    _text_start = ABSOLUTE(.);
    *(.UserEnter.text)
    . = ALIGN(16);
    *(.DebugExceptionVector.text)
    . = ALIGN(16);
    *(.NMIExceptionVector.text)
    . = ALIGN(16);
    *(.KernelExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN(16);
    *(.UserExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN(16);
    *(.DoubleExceptionVector.text)
    LONG(0)
    LONG(0)
    LONG(0)
    LONG(0)
    . = ALIGN (16);
    *(.entry.text)
    *(.init.literal)
    *(.init)
    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
    *(.fini.literal)
    *(.fini)
    *(.gnu.version)
    _text_end = ABSOLUTE(.);
    _etext = .;
  } >iram1_0_seg :iram1_0_phdr

  .lit4 : ALIGN(4)
  {
    _lit4_start = ABSOLUTE(.);
    *(*.lit4)
    *(.lit4.*)
    *(.gnu.linkonce.lit4.*)
    _lit4_end = ABSOLUTE(.);
  } >iram1_0_seg :iram1_0_phdr
}

/* get ROM code address */
INCLUDE "../sdk/ld/eagle.rom.addr.v6.ld"


arch: arm: cortex_r: Add userspace support for non-XIP builds

When running non-XIP, userspace threads need to be able to read .text in
order to execute code.  Cortex-R needs to setup an MPU entry to allow
this, but it must be aligned to a power of 2.  The linker scripts for
other archs follow this same pattern of aligning the location counter,
but outside of an input section.  The linker ignores this and places the
next input section at the LMA of the end of the previous input section.
Avoid this problem by make RODATA the last ROM section.  The MPU_ALIGN
can be moved inside the RODATA input section and correctly pad the
entire ROM section out to a power of 2 boundary.

_image_rom_end_order contains the power of 2 alignment which allow the
soc to set the MPU configuration statically based on the size of the ROM
sections instead of having to do it dynamically.

Signed-off-by: Bradley Bolen <a46f022a58b40f08f87b914d58da7dec46dba40c@lexmark.com>

/*
 * Copyright (c) 2013-2014 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Linker command/script file
 *
 * Linker script for the Cortex-A and Cortex-R platforms.
 */

#include <autoconf.h>
#include <linker/sections.h>
#include <devicetree.h>

#include <linker/linker-defs.h>
#include <linker/linker-tool.h>

/* physical address of RAM */
#ifdef CONFIG_XIP
  #define ROMABLE_REGION FLASH
  #define RAMABLE_REGION SRAM
#else
  #define ROMABLE_REGION SRAM
  #define RAMABLE_REGION SRAM
#endif

#if defined(CONFIG_XIP)
  #define _DATA_IN_ROM __data_rom_start
#else
  #define _DATA_IN_ROM
#endif

#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
  #define ROM_ADDR RAM_ADDR
#else
  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
#endif

#if CONFIG_FLASH_LOAD_SIZE > 0
  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
#else
  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
#endif

#if defined(CONFIG_XIP)
  #if defined(CONFIG_IS_BOOTLOADER)
    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \
                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
  #else
    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
  #endif
#else
  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#endif

/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
 * to make linker section alignment comply with MPU granularity.
 */
#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
#else
/* If building without MPU support, use default 4-byte alignment. */
_region_min_align = 4;
#endif

#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
  #define MPU_ALIGN(region_size) \
    . = ALIGN(_region_min_align); \
    . = ALIGN(1 << LOG2CEIL(region_size))
#else
  #define MPU_ALIGN(region_size) \
    . = ALIGN(_region_min_align)
#endif

MEMORY
{
    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
    /* Used by and documented in include/linker/intlist.ld */
    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
}

ENTRY(CONFIG_KERNEL_ENTRY)

SECTIONS
{
#include <linker/rel-sections.ld>

    /*
     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
     * before text section.
     */
    SECTION_PROLOGUE(.plt,,)
    {
        *(.plt)
    }

    SECTION_PROLOGUE(.iplt,,)
    {
        *(.iplt)
    }

    GROUP_START(ROMABLE_REGION)

#if defined(CONFIG_XIP)
    _image_rom_start = ROM_ADDR;
#else
    _image_rom_start = RAM_ADDR;
#endif

    SECTION_PROLOGUE(rom_start,,)
    {

/* Located in generated directory. This file is populated by calling
 * zephyr_linker_sources(ROM_START ...). This typically contains the vector
 * table and debug information.
 */
#include <snippets-rom-start.ld>

    } GROUP_LINK_IN(ROMABLE_REGION)

#ifdef CONFIG_CODE_DATA_RELOCATION

#include <linker_relocate.ld>

#endif /* CONFIG_CODE_DATA_RELOCATION */

    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
    {
        _image_text_start = .;
        *(.text)
        *(".text.*")
        *(.gnu.linkonce.t.*)

        /*
         * These are here according to 'arm-zephyr-elf-ld --verbose',
         * after .gnu.linkonce.t.*
         */
        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)

#include <linker/kobject-text.ld>

    } GROUP_LINK_IN(ROMABLE_REGION)

    _image_text_end = .;

#if defined (CONFIG_CPLUSPLUS)
    SECTION_PROLOGUE(.ARM.extab,,)
    {
        /*
         * .ARM.extab section containing exception unwinding information.
         */
        *(.ARM.extab* .gnu.linkonce.armextab.*)
    } GROUP_LINK_IN(ROMABLE_REGION)
#endif

    SECTION_PROLOGUE(.ARM.exidx,,)
    {
        /*
         * This section, related to stack and exception unwinding, is placed
         * explicitly to prevent it from being shared between multiple regions.
         * It  must be defined for gcc to support 64-bit math and avoid
         * section overlap.
         */
        __exidx_start = .;
#if defined (__GCC_LINKER_CMD__)
        *(.ARM.exidx* gnu.linkonce.armexidx.*)
#endif
        __exidx_end = .;
    } GROUP_LINK_IN(ROMABLE_REGION)

    _image_rodata_start = .;

#include <linker/common-rom.ld>
#include <linker/thread-local-storage.ld>
#include <linker/cplusplus-rom.ld>

    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
    {
        *(.rodata)
        *(".rodata.*")
        *(.gnu.linkonce.r.*)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rodata.ld>

#include <linker/kobject-rom.ld>

        /*
         * For XIP images, in order to avoid the situation when __data_rom_start
         * is 32-bit aligned, but the actual data is placed right after rodata
         * section, which may not end exactly at 32-bit border, pad rodata
         * section, so __data_rom_start points at data and it is 32-bit aligned.
         *
         * On non-XIP images this may enlarge image size up to 3 bytes. This
         * generally is not an issue, since modern ROM and FLASH memory is
         * usually 4k aligned.
         */
        . = ALIGN(4);

        /*
         * RODATA must be the last section so that the size of the entire read
         * only area will be filled to a power of 2.
         */
        MPU_ALIGN(ABSOLUTE(.) - _image_rom_start);
    } GROUP_LINK_IN(ROMABLE_REGION)

    _image_rodata_end = .;
    _image_rom_end = .;
    _image_rom_end_order = (LOG2CEIL(_image_rom_end) - 1) << 1;

    GROUP_END(ROMABLE_REGION)

    /*
     * These are here according to 'arm-zephyr-elf-ld --verbose',
     * before data section.
     */
    SECTION_PROLOGUE(.got,,)
    {
        *(.got.plt)
        *(.igot.plt)
        *(.got)
        *(.igot)
    }

    GROUP_START(RAMABLE_REGION)

    . = RAM_ADDR;
    /* Align the start of image SRAM with the
     * minimum granularity required by MPU.
     */
    . = ALIGN(_region_min_align);
    _image_ram_start = .;

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-ram-sections.ld>

#if defined(CONFIG_USERSPACE)
#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);
#define SMEM_PARTITION_ALIGN MPU_ALIGN

#include <app_smem.ld>

    _app_smem_size = _app_smem_end - _app_smem_start;
    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
#endif  /* CONFIG_USERSPACE */

    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
    {
        /*
         * For performance, BSS section is assumed to be 4 byte aligned and
         * a multiple of 4 bytes
         */
        . = ALIGN(4);
        __bss_start = .;
        __kernel_ram_start = .;

        *(.bss)
        *(".bss.*")
        *(COMMON)
        *(".kernel_bss.*")

#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_bss_relocate.ld>
#endif

        /*
         * As memory is cleared in words only, it is simpler to ensure the BSS
         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
         */
        __bss_end = ALIGN(4);
    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

#include <linker/common-noinit.ld>

    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
    {
        __data_ram_start = .;
        *(.data)
        *(".data.*")
        *(".kernel.*")

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rwdata.ld>

#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_data_relocate.ld>
#endif

    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)

    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);

#include <linker/common-ram.ld>
#include <linker/kobject-data.ld>
#include <linker/cplusplus-ram.ld>

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-data-sections.ld>

    __data_ram_end = .;

    /* Define linker symbols */

    _image_ram_end = .;
    _end = .; /* end of image */

    __kernel_ram_end = RAM_ADDR + RAM_SIZE;
    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;

    GROUP_END(RAMABLE_REGION)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-sections.ld>

#include <linker/debug-sections.ld>

    SECTION_PROLOGUE(.ARM.attributes, 0,)
    {
        KEEP(*(.ARM.attributes))
        KEEP(*(.gnu.attributes))
    }

    /* Must be last in romable region */
    SECTION_PROLOGUE(.last_section,(NOLOAD),)
    {
    } GROUP_LINK_IN(ROMABLE_REGION)

    /* To provide the image size as a const expression,
     * calculate this value here. */
    _flash_used = LOADADDR(.last_section) - _image_rom_start;

}

/*
 * Copyright (c) 2013-2014 Wind River Systems, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Linker command/script file
 *
 * Linker script for the Cortex-A and Cortex-R platforms.
 */

#include <autoconf.h>
#include <linker/sections.h>
#include <devicetree.h>

#include <linker/linker-defs.h>
#include <linker/linker-tool.h>

/* physical address of RAM */
#ifdef CONFIG_XIP
  #define ROMABLE_REGION FLASH
  #define RAMABLE_REGION SRAM
#else
  #define ROMABLE_REGION SRAM
  #define RAMABLE_REGION SRAM
#endif

#if defined(CONFIG_XIP)
  #define _DATA_IN_ROM __data_rom_start
#else
  #define _DATA_IN_ROM
#endif

#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
  #define ROM_ADDR RAM_ADDR
#else
  #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
#endif

#if CONFIG_FLASH_LOAD_SIZE > 0
  #define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
#else
  #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
#endif

#if defined(CONFIG_XIP)
  #if defined(CONFIG_IS_BOOTLOADER)
    #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
    #define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \
                     (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
  #else
    #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
    #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
  #endif
#else
  #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
  #define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#endif

/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
 * to make linker section alignment comply with MPU granularity.
 */
#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
#else
/* If building without MPU support, use default 4-byte alignment. */
_region_min_align = 4;
#endif

#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
  #define MPU_ALIGN(region_size) \
    . = ALIGN(_region_min_align); \
    . = ALIGN(1 << LOG2CEIL(region_size))
#else
  #define MPU_ALIGN(region_size) \
    . = ALIGN(_region_min_align)
#endif

MEMORY
{
    FLASH    (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
    SRAM     (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
    /* Used by and documented in include/linker/intlist.ld */
    IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
}

ENTRY(CONFIG_KERNEL_ENTRY)

SECTIONS
{
#include <linker/rel-sections.ld>

    /*
     * .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
     * before text section.
     */
    SECTION_PROLOGUE(.plt,,)
    {
        *(.plt)
    }

    SECTION_PROLOGUE(.iplt,,)
    {
        *(.iplt)
    }

    GROUP_START(ROMABLE_REGION)

    _image_rom_start = ROM_ADDR;

    SECTION_PROLOGUE(rom_start,,)
    {

/* Located in generated directory. This file is populated by calling
 * zephyr_linker_sources(ROM_START ...). This typically contains the vector
 * table and debug information.
 */
#include <snippets-rom-start.ld>

    } GROUP_LINK_IN(ROMABLE_REGION)

#ifdef CONFIG_CODE_DATA_RELOCATION

#include <linker_relocate.ld>

#endif /* CONFIG_CODE_DATA_RELOCATION */

    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
    {
        _image_text_start = .;
        *(.text)
        *(".text.*")
        *(.gnu.linkonce.t.*)

        /*
         * These are here according to 'arm-zephyr-elf-ld --verbose',
         * after .gnu.linkonce.t.*
         */
        *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)

#include <linker/kobject-text.ld>

    } GROUP_LINK_IN(ROMABLE_REGION)

    _image_text_end = .;

#if defined (CONFIG_CPLUSPLUS)
    SECTION_PROLOGUE(.ARM.extab,,)
    {
        /*
         * .ARM.extab section containing exception unwinding information.
         */
        *(.ARM.extab* .gnu.linkonce.armextab.*)
    } GROUP_LINK_IN(ROMABLE_REGION)
#endif

    SECTION_PROLOGUE(.ARM.exidx,,)
    {
        /*
         * This section, related to stack and exception unwinding, is placed
         * explicitly to prevent it from being shared between multiple regions.
         * It  must be defined for gcc to support 64-bit math and avoid
         * section overlap.
         */
        __exidx_start = .;
#if defined (__GCC_LINKER_CMD__)
        *(.ARM.exidx* gnu.linkonce.armexidx.*)
#endif
        __exidx_end = .;
    } GROUP_LINK_IN(ROMABLE_REGION)

    _image_rodata_start = .;

#include <linker/common-rom.ld>
#include <linker/thread-local-storage.ld>

    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
    {
        *(.rodata)
        *(".rodata.*")
        *(.gnu.linkonce.r.*)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rodata.ld>

#include <linker/kobject-rom.ld>

        /*
         * For XIP images, in order to avoid the situation when __data_rom_start
         * is 32-bit aligned, but the actual data is placed right after rodata
         * section, which may not end exactly at 32-bit border, pad rodata
         * section, so __data_rom_start points at data and it is 32-bit aligned.
         *
         * On non-XIP images this may enlarge image size up to 3 bytes. This
         * generally is not an issue, since modern ROM and FLASH memory is
         * usually 4k aligned.
         */
        . = ALIGN(4);
    } GROUP_LINK_IN(ROMABLE_REGION)

#include <linker/cplusplus-rom.ld>

    _image_rodata_end = .;
    MPU_ALIGN(_image_rodata_end -_image_rom_start);
    _image_rom_end = .;

    GROUP_END(ROMABLE_REGION)

    /*
     * These are here according to 'arm-zephyr-elf-ld --verbose',
     * before data section.
     */
    SECTION_PROLOGUE(.got,,)
    {
        *(.got.plt)
        *(.igot.plt)
        *(.got)
        *(.igot)
    }

    GROUP_START(RAMABLE_REGION)

    . = RAM_ADDR;
    /* Align the start of image SRAM with the
     * minimum granularity required by MPU.
     */
    . = ALIGN(_region_min_align);
    _image_ram_start = .;

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-ram-sections.ld>

#if defined(CONFIG_USERSPACE)
#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);
#define SMEM_PARTITION_ALIGN MPU_ALIGN

#include <app_smem.ld>

    _app_smem_size = _app_smem_end - _app_smem_start;
    _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
#endif  /* CONFIG_USERSPACE */

    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
    {
        /*
         * For performance, BSS section is assumed to be 4 byte aligned and
         * a multiple of 4 bytes
         */
        . = ALIGN(4);
        __bss_start = .;
        __kernel_ram_start = .;

        *(.bss)
        *(".bss.*")
        *(COMMON)
        *(".kernel_bss.*")

#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_bss_relocate.ld>
#endif

        /*
         * As memory is cleared in words only, it is simpler to ensure the BSS
         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
         */
        __bss_end = ALIGN(4);
    } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

#include <linker/common-noinit.ld>

    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
    {
        __data_ram_start = .;
        *(.data)
        *(".data.*")
        *(".kernel.*")

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rwdata.ld>

#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_data_relocate.ld>
#endif

    } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)

    __data_rom_start = LOADADDR(_DATA_SECTION_NAME);

#include <linker/common-ram.ld>
#include <linker/kobject-data.ld>
#include <linker/cplusplus-ram.ld>

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-data-sections.ld>

    __data_ram_end = .;

    /* Define linker symbols */

    _image_ram_end = .;
    _end = .; /* end of image */

    __kernel_ram_end = RAM_ADDR + RAM_SIZE;
    __kernel_ram_size = __kernel_ram_end - __kernel_ram_start;

    GROUP_END(RAMABLE_REGION)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-sections.ld>

#include <linker/debug-sections.ld>

    SECTION_PROLOGUE(.ARM.attributes, 0,)
    {
        KEEP(*(.ARM.attributes))
        KEEP(*(.gnu.attributes))
    }

    /* Must be last in romable region */
    SECTION_PROLOGUE(.last_section,(NOLOAD),)
    {
    } GROUP_LINK_IN(ROMABLE_REGION)

    /* To provide the image size as a const expression,
     * calculate this value here. */
    _flash_used = LOADADDR(.last_section) - _image_rom_start;

}


Stack location is pinned to the top of RAM.  Reduce RAM footprint.

/* Linker script for Silicon Labs EFM32TG devices */
/*                                                                  */
/* This file is subject to the license terms as defined in ARM's    */
/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       */
/* Example Code.                                                    */
/*                                                                  */
/* Silicon Laboratories, Inc. 2015                                  */
/*                                                                  */
/* Version 4.1.0 */
/*                                                                  */

MEMORY
{
  /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 */
  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192
  /* RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768 */
  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 1024
}

/* Linker script to place sections and symbol values. Should be used together
 * with other linker script that defines memory regions FLASH and RAM.
 * It references following symbols, which must be defined in code:
 *   Reset_Handler : Entry of reset handler
 *
 * It defines following symbols, which code can use without definition:
 *   __exidx_start
 *   __exidx_end
 *   __copy_table_start__
 *   __copy_table_end__
 *   __zero_table_start__
 *   __zero_table_end__
 *   __etext
 *   __data_start__
 *   __preinit_array_start
 *   __preinit_array_end
 *   __init_array_start
 *   __init_array_end
 *   __fini_array_start
 *   __fini_array_end
 *   __data_end__
 *   __bss_start__
 *   __bss_end__
 *   __end__
 *   end
 *   __HeapLimit
 *   __StackLimit
 *   __StackTop
 *   __stack
 *   __Vectors_End
 *   __Vectors_Size
 */
ENTRY(Reset_Handler)

SECTIONS
{
  .text :
  {
    KEEP(*(.vectors))
    __Vectors_End = .;
    __Vectors_Size = __Vectors_End - __Vectors;
    __end__ = .;

    *(.text*)

    KEEP(*(.init))
    KEEP(*(.fini))

    /* .ctors */
    *crtbegin.o(.ctors)
    *crtbegin?.o(.ctors)
    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
    *(SORT(.ctors.*))
    *(.ctors)

    /* .dtors */
    *crtbegin.o(.dtors)
    *crtbegin?.o(.dtors)
    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
    *(SORT(.dtors.*))
    *(.dtors)

    *(.rodata*)

    KEEP(*(.eh_frame*))
  } > FLASH

  .ARM.extab :
  {
    *(.ARM.extab* .gnu.linkonce.armextab.*)
  } > FLASH

  __exidx_start = .;
  .ARM.exidx :
  {
    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
  } > FLASH
  __exidx_end = .;

  /* To copy multiple ROM to RAM sections,
   * uncomment .copy.table section and,
   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
  /*
  .copy.table :
  {
    . = ALIGN(4);
    __copy_table_start__ = .;
    LONG (__etext)
    LONG (__data_start__)
    LONG (__data_end__ - __data_start__)
    LONG (__etext2)
    LONG (__data2_start__)
    LONG (__data2_end__ - __data2_start__)
    __copy_table_end__ = .;
  } > FLASH
  */

  /* To clear multiple BSS sections,
   * uncomment .zero.table section and,
   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
  /*
  .zero.table :
  {
    . = ALIGN(4);
    __zero_table_start__ = .;
    LONG (__bss_start__)
    LONG (__bss_end__ - __bss_start__)
    LONG (__bss2_start__)
    LONG (__bss2_end__ - __bss2_start__)
    __zero_table_end__ = .;
  } > FLASH
  */

  __etext = .;

  .data : AT (__etext)
  {
    __data_start__ = .;
    *(vtable)
    *(.data*)
    . = ALIGN (4);
    *(.ram)

    . = ALIGN(4);
    /* preinit data */
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP(*(.preinit_array))
    PROVIDE_HIDDEN (__preinit_array_end = .);

    . = ALIGN(4);
    /* init data */
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP(*(SORT(.init_array.*)))
    KEEP(*(.init_array))
    PROVIDE_HIDDEN (__init_array_end = .);

    . = ALIGN(4);
    /* finit data */
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP(*(SORT(.fini_array.*)))
    KEEP(*(.fini_array))
    PROVIDE_HIDDEN (__fini_array_end = .);

    KEEP(*(.jcr*))
    . = ALIGN(4);
    /* All data end */
    __data_end__ = .;

  } > RAM

  .bss :
  {
    . = ALIGN(4);
    __bss_start__ = .;
    *(.bss*)
    *(COMMON)
    . = ALIGN(4);
    __bss_end__ = .;
  } > RAM

  /* .stack_dummy section doesn't contains any symbols. It is only
   * used for linker to calculate size of stack sections, and assign
   * values to stack symbols later */
  .stack_dummy (COPY):
  {
    KEEP(*(.stack*))
  } > RAM

  /* Set stack top to end of RAM, and stack limit move down by
   * size of stack_dummy section */
  __StackTop = ORIGIN(RAM) + LENGTH(RAM);
  __StackLimit = __StackTop - SIZEOF(.stack_dummy);
  PROVIDE(__stack = __StackTop);

  /* Check if data + heap + stack exceeds RAM limit */
  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

  /* Check if FLASH usage exceeds FLASH size */
  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
}

/* Linker script for Silicon Labs EFM32TG devices */
/*                                                                  */
/* This file is subject to the license terms as defined in ARM's    */
/* CMSIS END USER LICENSE AGREEMENT.pdf, governing the use of       */
/* Example Code.                                                    */
/*                                                                  */
/* Silicon Laboratories, Inc. 2015                                  */
/*                                                                  */
/* Version 4.1.0 */
/*                                                                  */

MEMORY
{
  /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 262144 */
  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 8192
  /* RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 32768 */
  RAM (rwx)  : ORIGIN = 0x20000000, LENGTH = 2048 + 512
}

/* Linker script to place sections and symbol values. Should be used together
 * with other linker script that defines memory regions FLASH and RAM.
 * It references following symbols, which must be defined in code:
 *   Reset_Handler : Entry of reset handler
 *
 * It defines following symbols, which code can use without definition:
 *   __exidx_start
 *   __exidx_end
 *   __copy_table_start__
 *   __copy_table_end__
 *   __zero_table_start__
 *   __zero_table_end__
 *   __etext
 *   __data_start__
 *   __preinit_array_start
 *   __preinit_array_end
 *   __init_array_start
 *   __init_array_end
 *   __fini_array_start
 *   __fini_array_end
 *   __data_end__
 *   __bss_start__
 *   __bss_end__
 *   __end__
 *   end
 *   __HeapLimit
 *   __StackLimit
 *   __StackTop
 *   __stack
 *   __Vectors_End
 *   __Vectors_Size
 */
ENTRY(Reset_Handler)

SECTIONS
{
  .text :
  {
    KEEP(*(.vectors))
    __Vectors_End = .;
    __Vectors_Size = __Vectors_End - __Vectors;
    __end__ = .;

    *(.text*)

    KEEP(*(.init))
    KEEP(*(.fini))

    /* .ctors */
    *crtbegin.o(.ctors)
    *crtbegin?.o(.ctors)
    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
    *(SORT(.ctors.*))
    *(.ctors)

    /* .dtors */
    *crtbegin.o(.dtors)
    *crtbegin?.o(.dtors)
    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
    *(SORT(.dtors.*))
    *(.dtors)

    *(.rodata*)

    KEEP(*(.eh_frame*))
  } > FLASH

  .ARM.extab :
  {
    *(.ARM.extab* .gnu.linkonce.armextab.*)
  } > FLASH

  __exidx_start = .;
  .ARM.exidx :
  {
    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
  } > FLASH
  __exidx_end = .;

  /* To copy multiple ROM to RAM sections,
   * uncomment .copy.table section and,
   * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
  /*
  .copy.table :
  {
    . = ALIGN(4);
    __copy_table_start__ = .;
    LONG (__etext)
    LONG (__data_start__)
    LONG (__data_end__ - __data_start__)
    LONG (__etext2)
    LONG (__data2_start__)
    LONG (__data2_end__ - __data2_start__)
    __copy_table_end__ = .;
  } > FLASH
  */

  /* To clear multiple BSS sections,
   * uncomment .zero.table section and,
   * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
  /*
  .zero.table :
  {
    . = ALIGN(4);
    __zero_table_start__ = .;
    LONG (__bss_start__)
    LONG (__bss_end__ - __bss_start__)
    LONG (__bss2_start__)
    LONG (__bss2_end__ - __bss2_start__)
    __zero_table_end__ = .;
  } > FLASH
  */

  __etext = .;

  .data : AT (__etext)
  {
    __data_start__ = .;
    *(vtable)
    *(.data*)
    . = ALIGN (4);
    *(.ram)

    . = ALIGN(4);
    /* preinit data */
    PROVIDE_HIDDEN (__preinit_array_start = .);
    KEEP(*(.preinit_array))
    PROVIDE_HIDDEN (__preinit_array_end = .);

    . = ALIGN(4);
    /* init data */
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP(*(SORT(.init_array.*)))
    KEEP(*(.init_array))
    PROVIDE_HIDDEN (__init_array_end = .);

    . = ALIGN(4);
    /* finit data */
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP(*(SORT(.fini_array.*)))
    KEEP(*(.fini_array))
    PROVIDE_HIDDEN (__fini_array_end = .);

    KEEP(*(.jcr*))
    . = ALIGN(4);
    /* All data end */
    __data_end__ = .;

  } > RAM

  .bss :
  {
    . = ALIGN(4);
    __bss_start__ = .;
    *(.bss*)
    *(COMMON)
    . = ALIGN(4);
    __bss_end__ = .;
  } > RAM

  /* .stack_dummy section doesn't contains any symbols. It is only
   * used for linker to calculate size of stack sections, and assign
   * values to stack symbols later */
  .stack_dummy (COPY):
  {
    KEEP(*(.stack*))
  } > RAM

  /* Set stack top to end of RAM, and stack limit move down by
   * size of stack_dummy section */
  __StackTop = ORIGIN(RAM) + LENGTH(RAM);
  __StackLimit = __StackTop - SIZEOF(.stack_dummy);
  PROVIDE(__stack = __StackTop);

  /* Check if data + heap + stack exceeds RAM limit */
  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")

  /* Check if FLASH usage exceeds FLASH size */
  ASSERT( LENGTH(FLASH) >= (__etext + SIZEOF(.data)), "FLASH memory overflowed !")
}


Changed link script. STM32F103C8 has 20K of flash

/* Define memory regions. 20K of flash*/
MEMORY
{
	rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
}

INCLUDE libopencm3_stm32f1.ld

/* Define memory regions. */
MEMORY
{
	rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
}

INCLUDE libopencm3_stm32f1.ld


feat: disable mbedtls rom code on master

/*
 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* ROM function interface esp32c2.rom.mbedtls.ld for esp32c2
 *
 *
 * Generated from ./interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3
 *
 * Compatible with ROM where ECO version equal or greater to 1.
 *
 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
 */

/***************************************
 Group rom_mbedtls
 ***************************************/

/* Functions */
mbedtls_md5_starts_ret = 0x40002be4;
mbedtls_md5_update_ret = 0x40002be8;
mbedtls_md5_finish_ret = 0x40002bec;
/* Data (.data, .bss, .rodata) */

/*
 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* ROM function interface esp32c2.rom.mbedtls.ld for esp32c2
 *
 *
 * Generated from ./interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3
 *
 * Compatible with ROM where ECO version equal or greater to 1.
 *
 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
 */

/***************************************
 Group rom_mbedtls
 ***************************************/

/* Functions */
mbedtls_aes_init = 0x40002664;
ssl_write_client_hello = 0x40002668;
ssl_parse_server_hello = 0x4000266c;
ssl_parse_server_key_exchange = 0x40002670;
ssl_parse_certificate_request = 0x40002674;
ssl_parse_server_hello_done = 0x40002678;
ssl_write_client_key_exchange = 0x4000267c;
ssl_write_certificate_verify = 0x40002680;
ssl_parse_new_session_ticket = 0x40002684;
mbedtls_aes_free = 0x40002688;
mbedtls_aes_setkey_enc = 0x4000268c;
mbedtls_aes_setkey_dec = 0x40002690;
mbedtls_aes_crypt_ecb = 0x40002694;
mbedtls_aes_crypt_cbc = 0x40002698;
mbedtls_internal_aes_encrypt = 0x4000269c;
mbedtls_internal_aes_decrypt = 0x400026a0;
mbedtls_asn1_get_len = 0x400026a4;
mbedtls_asn1_get_tag = 0x400026a8;
mbedtls_asn1_get_bool = 0x400026ac;
mbedtls_asn1_get_int = 0x400026b0;
mbedtls_asn1_get_bitstring = 0x400026b4;
mbedtls_asn1_get_bitstring_null = 0x400026b8;
mbedtls_asn1_get_sequence_of = 0x400026bc;
mbedtls_asn1_get_mpi = 0x400026c0;
mbedtls_asn1_get_alg = 0x400026c4;
mbedtls_asn1_get_alg_null = 0x400026c8;
mbedtls_asn1_write_len = 0x400026cc;
mbedtls_asn1_write_tag = 0x400026d0;
mbedtls_asn1_write_mpi = 0x400026d4;
mbedtls_base64_decode = 0x400026d8;
mbedtls_mpi_init = 0x400026dc;
mbedtls_mpi_free = 0x400026e0;
mbedtls_mpi_grow = 0x400026e4;
mbedtls_mpi_shrink = 0x400026e8;
mbedtls_mpi_copy = 0x400026ec;
mbedtls_mpi_safe_cond_assign = 0x400026f0;
mbedtls_mpi_safe_cond_swap = 0x400026f4;
mbedtls_mpi_lset = 0x400026f8;
mbedtls_mpi_get_bit = 0x400026fc;
mbedtls_mpi_set_bit = 0x40002700;
mbedtls_mpi_lsb = 0x40002704;
mbedtls_mpi_bitlen = 0x40002708;
mbedtls_mpi_size = 0x4000270c;
mbedtls_mpi_read_binary = 0x40002710;
mbedtls_mpi_write_binary = 0x40002714;
mbedtls_mpi_shift_l = 0x40002718;
mbedtls_mpi_shift_r = 0x4000271c;
mbedtls_mpi_cmp_abs = 0x40002720;
mbedtls_mpi_cmp_mpi = 0x40002724;
mbedtls_mpi_lt_mpi_ct = 0x40002728;
mbedtls_mpi_cmp_int = 0x4000272c;
mbedtls_mpi_add_abs = 0x40002730;
mbedtls_mpi_sub_abs = 0x40002734;
mbedtls_mpi_add_mpi = 0x40002738;
mbedtls_mpi_sub_mpi = 0x4000273c;
mbedtls_mpi_add_int = 0x40002740;
mbedtls_mpi_sub_int = 0x40002744;
mbedtls_mpi_mul_mpi = 0x40002748;
mbedtls_mpi_mul_int = 0x4000274c;
mbedtls_mpi_div_mpi = 0x40002750;
mbedtls_mpi_div_int = 0x40002754;
mbedtls_mpi_mod_mpi = 0x40002758;
mbedtls_mpi_mod_int = 0x4000275c;
mbedtls_mpi_exp_mod = 0x40002760;
mbedtls_mpi_fill_random = 0x40002764;
mbedtls_mpi_gcd = 0x40002768;
mbedtls_mpi_inv_mod = 0x4000276c;
mbedtls_mpi_is_prime_ext = 0x40002770;
mbedtls_ccm_star_encrypt_and_tag = 0x40002774;
mbedtls_ccm_star_auth_decrypt = 0x40002778;
mbedtls_cipher_init = 0x4000277c;
mbedtls_cipher_set_padding_mode = 0x40002780;
mbedtls_cipher_reset = 0x40002784;
mbedtls_cipher_finish = 0x40002788;
mbedtls_cipher_crypt = 0x4000278c;
mbedtls_cipher_cmac_starts = 0x40002790;
mbedtls_cipher_cmac_update = 0x40002794;
mbedtls_cipher_cmac_finish = 0x40002798;
mbedtls_ctr_drbg_init = 0x4000279c;
mbedtls_ctr_drbg_seed = 0x400027a0;
mbedtls_ctr_drbg_free = 0x400027a4;
mbedtls_ctr_drbg_reseed = 0x400027a8;
mbedtls_ctr_drbg_random_with_add = 0x400027ac;
mbedtls_ctr_drbg_random = 0x400027b0;
mbedtls_dhm_init = 0x400027b4;
mbedtls_dhm_read_params = 0x400027b8;
mbedtls_dhm_make_public = 0x400027bc;
mbedtls_dhm_calc_secret = 0x400027c0;
mbedtls_dhm_free = 0x400027c4;
mbedtls_ecdh_init = 0x400027c8;
mbedtls_ecdh_setup = 0x400027cc;
mbedtls_ecdh_free = 0x400027d0;
mbedtls_ecdh_read_params = 0x400027d4;
mbedtls_ecdh_get_params = 0x400027d8;
mbedtls_ecdh_make_public = 0x400027dc;
mbedtls_ecdh_calc_secret = 0x400027e0;
mbedtls_ecdh_enable_restart = 0x400027e4;
mbedtls_ecdsa_write_signature = 0x400027e8;
mbedtls_ecdsa_write_signature_restartable = 0x400027ec;
mbedtls_ecdsa_read_signature = 0x400027f0;
mbedtls_ecdsa_read_signature_restartable = 0x400027f4;
mbedtls_ecdsa_from_keypair = 0x400027f8;
mbedtls_ecdsa_init = 0x400027fc;
mbedtls_ecdsa_free = 0x40002800;
mbedtls_ecdsa_restart_init = 0x40002804;
mbedtls_ecdsa_restart_free = 0x40002808;
mbedtls_ecjpake_init = 0x4000280c;
mbedtls_ecjpake_check = 0x40002810;
mbedtls_ecjpake_write_round_one = 0x40002814;
mbedtls_ecjpake_read_round_one = 0x40002818;
mbedtls_ecjpake_write_round_two = 0x4000281c;
mbedtls_ecjpake_read_round_two = 0x40002820;
mbedtls_ecjpake_derive_secret = 0x40002824;
mbedtls_ecjpake_free = 0x40002828;
mbedtls_ecp_check_budget = 0x4000282c;
mbedtls_ecp_restart_is_enabled = 0x40002830;
mbedtls_ecp_curve_list = 0x40002834;
mbedtls_ecp_grp_id_list = 0x40002838;
mbedtls_ecp_curve_info_from_grp_id = 0x4000283c;
mbedtls_ecp_curve_info_from_tls_id = 0x40002840;
mbedtls_ecp_point_init = 0x40002844;
mbedtls_ecp_group_init = 0x40002848;
mbedtls_ecp_keypair_init = 0x4000284c;
mbedtls_ecp_point_free = 0x40002850;
mbedtls_ecp_group_free = 0x40002854;
mbedtls_ecp_keypair_free = 0x40002858;
mbedtls_ecp_restart_init = 0x4000285c;
mbedtls_ecp_restart_free = 0x40002860;
mbedtls_ecp_copy = 0x40002864;
mbedtls_ecp_group_copy = 0x40002868;
mbedtls_ecp_set_zero = 0x4000286c;
mbedtls_ecp_is_zero = 0x40002870;
mbedtls_ecp_point_cmp = 0x40002874;
mbedtls_ecp_point_write_binary = 0x40002878;
mbedtls_ecp_point_read_binary = 0x4000287c;
mbedtls_ecp_tls_read_point = 0x40002880;
mbedtls_ecp_tls_write_point = 0x40002884;
mbedtls_ecp_group_load = 0x40002888;
mbedtls_ecp_tls_read_group = 0x4000288c;
mbedtls_ecp_tls_read_group_id = 0x40002890;
mbedtls_ecp_tls_write_group = 0x40002894;
mbedtls_ecp_mul = 0x40002898;
mbedtls_ecp_mul_restartable = 0x4000289c;
mbedtls_ecp_muladd = 0x400028a0;
mbedtls_ecp_muladd_restartable = 0x400028a4;
mbedtls_ecp_check_pubkey = 0x400028a8;
mbedtls_ecp_check_privkey = 0x400028ac;
mbedtls_ecp_gen_privkey = 0x400028b0;
mbedtls_ecp_gen_keypair_base = 0x400028b4;
mbedtls_ecp_check_pub_priv = 0x400028b8;
mbedtls_entropy_add_source = 0x400028bc;
mbedtls_entropy_func = 0x400028c0;
mbedtls_gcm_crypt_and_tag = 0x400028c4;
mbedtls_gcm_starts = 0x400028c8;
mbedtls_gcm_update = 0x400028cc;
mbedtls_gcm_finish = 0x400028d0;
mbedtls_hmac_drbg_init = 0x400028d4;
mbedtls_hmac_drbg_seed_buf = 0x400028d8;
mbedtls_hmac_drbg_update_ret = 0x400028dc;
mbedtls_hmac_drbg_reseed = 0x400028e0;
mbedtls_hmac_drbg_random_with_add = 0x400028e4;
mbedtls_hmac_drbg_random = 0x400028e8;
mbedtls_hmac_drbg_free = 0x400028ec;
mbedtls_md_list = 0x400028f0;
mbedtls_md_init = 0x400028f4;
mbedtls_md_free = 0x400028f8;
mbedtls_md_setup = 0x400028fc;
mbedtls_md_clone = 0x40002900;
mbedtls_md_get_size = 0x40002904;
mbedtls_md_get_type = 0x40002908;
mbedtls_md_starts = 0x4000290c;
mbedtls_md_update = 0x40002910;
mbedtls_md_finish = 0x40002914;
mbedtls_md = 0x40002918;
mbedtls_md_hmac_starts = 0x4000291c;
mbedtls_md_hmac_update = 0x40002920;
mbedtls_md_hmac_finish = 0x40002924;
mbedtls_md_hmac_reset = 0x40002928;
mbedtls_oid_get_x509_ext_type = 0x4000292c;
mbedtls_oid_get_pk_alg = 0x40002930;
mbedtls_oid_get_ec_grp = 0x40002934;
mbedtls_oid_get_sig_alg = 0x40002938;
mbedtls_oid_get_md_alg = 0x4000293c;
mbedtls_oid_get_md_hmac = 0x40002940;
mbedtls_oid_get_oid_by_md = 0x40002944;
mbedtls_oid_get_cipher_alg = 0x40002948;
mbedtls_oid_get_pkcs12_pbe_alg = 0x4000294c;
mbedtls_pem_init = 0x40002950;
mbedtls_pem_free = 0x40002954;
mbedtls_pkcs12_pbe_sha1_rc4_128 = 0x40002958;
mbedtls_pkcs12_pbe = 0x4000295c;
mbedtls_pkcs12_derivation = 0x40002960;
mbedtls_pkcs5_pbes2 = 0x40002964;
mbedtls_pkcs5_pbkdf2_hmac = 0x40002968;
mbedtls_pk_info_from_type = 0x4000296c;
mbedtls_pk_init = 0x40002970;
mbedtls_pk_free = 0x40002974;
mbedtls_pk_restart_init = 0x40002978;
mbedtls_pk_restart_free = 0x4000297c;
mbedtls_pk_setup = 0x40002980;
mbedtls_pk_can_do = 0x40002984;
mbedtls_pk_verify = 0x40002988;
mbedtls_pk_verify_restartable = 0x4000298c;
mbedtls_pk_verify_ext = 0x40002990;
mbedtls_pk_sign_restartable = 0x40002994;
mbedtls_pk_encrypt = 0x40002998;
mbedtls_pk_get_type = 0x4000299c;
mbedtls_pk_parse_subpubkey = 0x400029a0;
mbedtls_rsa_init = 0x400029a4;
mbedtls_rsa_import = 0x400029a8;
mbedtls_rsa_import_raw = 0x400029ac;
mbedtls_rsa_complete = 0x400029b0;
mbedtls_rsa_set_padding = 0x400029b4;
mbedtls_rsa_get_len = 0x400029b8;
mbedtls_rsa_check_pubkey = 0x400029bc;
mbedtls_rsa_check_privkey = 0x400029c0;
mbedtls_rsa_check_pub_priv = 0x400029c4;
mbedtls_rsa_public = 0x400029c8;
mbedtls_rsa_private = 0x400029cc;
mbedtls_rsa_pkcs1_encrypt = 0x400029d0;
mbedtls_rsa_rsaes_pkcs1_v15_encrypt = 0x400029d4;
mbedtls_rsa_rsaes_oaep_encrypt = 0x400029d8;
mbedtls_rsa_pkcs1_decrypt = 0x400029dc;
mbedtls_rsa_rsaes_pkcs1_v15_decrypt = 0x400029e0;
mbedtls_rsa_rsaes_oaep_decrypt = 0x400029e4;
mbedtls_rsa_pkcs1_sign = 0x400029e8;
mbedtls_rsa_rsassa_pkcs1_v15_sign = 0x400029ec;
mbedtls_rsa_rsassa_pss_sign = 0x400029f0;
mbedtls_rsa_pkcs1_verify = 0x400029f4;
mbedtls_rsa_rsassa_pkcs1_v15_verify = 0x400029f8;
mbedtls_rsa_rsassa_pss_verify = 0x400029fc;
mbedtls_rsa_rsassa_pss_verify_ext = 0x40002a00;
mbedtls_rsa_free = 0x40002a04;
mbedtls_rsa_deduce_primes = 0x40002a08;
mbedtls_rsa_deduce_private_exponent = 0x40002a0c;
mbedtls_rsa_deduce_crt = 0x40002a10;
mbedtls_rsa_validate_params = 0x40002a14;
mbedtls_rsa_validate_crt = 0x40002a18;
mbedtls_sha1_init = 0x40002a1c;
mbedtls_sha1_free = 0x40002a20;
mbedtls_sha1_clone = 0x40002a24;
mbedtls_sha1_starts_ret = 0x40002a28;
mbedtls_sha1_finish_ret = 0x40002a2c;
mbedtls_sha256_init = 0x40002a30;
mbedtls_sha256_free = 0x40002a34;
mbedtls_sha256_clone = 0x40002a38;
mbedtls_sha256_starts_ret = 0x40002a3c;
mbedtls_sha256_finish_ret = 0x40002a40;
mbedtls_sha256_ret = 0x40002a44;
mbedtls_sha512_init = 0x40002a48;
mbedtls_sha512_free = 0x40002a4c;
mbedtls_sha512_clone = 0x40002a50;
mbedtls_sha512_starts_ret = 0x40002a54;
mbedtls_sha512_update_ret = 0x40002a58;
mbedtls_sha512_finish_ret = 0x40002a5c;
mbedtls_internal_sha512_process = 0x40002a60;
mbedtls_sha512_ret = 0x40002a64;
mbedtls_ssl_conf_endpoint = 0x40002a68;
mbedtls_ssl_conf_transport = 0x40002a6c;
mbedtls_ssl_set_bio = 0x40002a70;
mbedtls_ssl_conf_dh_param_bin = 0x40002a74;
mbedtls_ssl_get_max_frag_len = 0x40002a78;
mbedtls_ssl_get_max_out_record_payload = 0x40002a7c;
mbedtls_ssl_handshake = 0x40002a80;
mbedtls_ssl_handshake_step = 0x40002a84;
mbedtls_ssl_renegotiate = 0x40002a88;
mbedtls_ssl_send_alert_message = 0x40002a8c;
mbedtls_ssl_config_defaults = 0x40002a90;
mbedtls_ssl_session_init = 0x40002a94;
mbedtls_ssl_session_free = 0x40002a98;
mbedtls_ssl_transform_free = 0x40002a9c;
mbedtls_ssl_handshake_free = 0x40002aa0;
mbedtls_ssl_handshake_client_step = 0x40002aa4;
mbedtls_ssl_handshake_wrapup = 0x40002aa8;
mbedtls_ssl_derive_keys = 0x40002aac;
mbedtls_ssl_handle_message_type = 0x40002ab0;
mbedtls_ssl_prepare_handshake_record = 0x40002ab4;
mbedtls_ssl_update_handshake_status = 0x40002ab8;
mbedtls_ssl_read_record = 0x40002abc;
mbedtls_ssl_fetch_input = 0x40002ac0;
mbedtls_ssl_write_handshake_msg = 0x40002ac4;
mbedtls_ssl_write_record = 0x40002ac8;
mbedtls_ssl_flush_output = 0x40002acc;
mbedtls_ssl_parse_certificate = 0x40002ad0;
mbedtls_ssl_write_certificate = 0x40002ad4;
mbedtls_ssl_parse_change_cipher_spec = 0x40002ad8;
mbedtls_ssl_write_change_cipher_spec = 0x40002adc;
mbedtls_ssl_parse_finished = 0x40002ae0;
mbedtls_ssl_write_finished = 0x40002ae4;
mbedtls_ssl_optimize_checksum = 0x40002ae8;
mbedtls_ssl_psk_derive_premaster = 0x40002aec;
mbedtls_ssl_sig_from_pk = 0x40002af0;
mbedtls_ssl_pk_alg_from_sig = 0x40002af4;
mbedtls_ssl_md_alg_from_hash = 0x40002af8;
mbedtls_ssl_hash_from_md_alg = 0x40002afc;
mbedtls_ssl_check_curve = 0x40002b00;
mbedtls_ssl_check_sig_hash = 0x40002b04;
mbedtls_ssl_write_version = 0x40002b08;
mbedtls_ssl_read_version = 0x40002b0c;
mbedtls_ssl_get_key_exchange_md_ssl_tls = 0x40002b10;
mbedtls_ssl_get_key_exchange_md_tls1_2 = 0x40002b14;
mbedtls_ssl_cf_hmac = 0x40002b18;
mbedtls_ssl_cf_memcpy_offset = 0x40002b1c;
mbedtls_x509_crt_parse_der = 0x40002b20;
mbedtls_x509_crt_verify_restartable = 0x40002b24;
mbedtls_x509_crt_check_key_usage = 0x40002b28;
mbedtls_x509_crt_check_extended_key_usage = 0x40002b2c;
mbedtls_x509_crt_is_revoked = 0x40002b30;
mbedtls_x509_crt_init = 0x40002b34;
mbedtls_x509_crt_free = 0x40002b38;
mbedtls_x509_crt_restart_init = 0x40002b3c;
mbedtls_x509_crt_restart_free = 0x40002b40;
mbedtls_x509_get_name = 0x40002b44;
mbedtls_x509_get_alg_null = 0x40002b48;
mbedtls_x509_get_alg = 0x40002b4c;
mbedtls_x509_get_rsassa_pss_params = 0x40002b50;
mbedtls_x509_get_sig = 0x40002b54;
mbedtls_x509_get_sig_alg = 0x40002b58;
mbedtls_x509_get_time = 0x40002b5c;
mbedtls_x509_get_serial = 0x40002b60;
mbedtls_x509_get_ext = 0x40002b64;
mbedtls_aes_xts_init = 0x40002b68;
mbedtls_aes_xts_free = 0x40002b6c;
mbedtls_aes_xts_setkey_enc = 0x40002b70;
mbedtls_aes_xts_setkey_dec = 0x40002b74;
mbedtls_aes_crypt_xts = 0x40002b78;
mbedtls_aes_crypt_cfb128 = 0x40002b7c;
mbedtls_aes_crypt_ofb = 0x40002b80;
mbedtls_aes_crypt_ctr = 0x40002b84;
mbedtls_arc4_init = 0x40002b88;
mbedtls_arc4_free = 0x40002b8c;
mbedtls_arc4_setup = 0x40002b90;
mbedtls_arc4_crypt = 0x40002b94;
mbedtls_ccm_init = 0x40002b98;
mbedtls_ccm_setkey = 0x40002b9c;
mbedtls_ccm_free = 0x40002ba0;
mbedtls_ccm_encrypt_and_tag = 0x40002ba4;
mbedtls_ccm_auth_decrypt = 0x40002ba8;
mbedtls_dhm_make_params = 0x40002bac;
mbedtls_dhm_set_group = 0x40002bb0;
mbedtls_dhm_read_public = 0x40002bb4;
mbedtls_ecdh_make_params = 0x40002bb8;
mbedtls_ecdh_read_public = 0x40002bbc;
mbedtls_entropy_init = 0x40002bc0;
mbedtls_entropy_free = 0x40002bc4;
mbedtls_gcm_init = 0x40002bc8;
mbedtls_gcm_setkey = 0x40002bcc;
mbedtls_gcm_auth_decrypt = 0x40002bd0;
mbedtls_gcm_free = 0x40002bd4;
mbedtls_md5_init = 0x40002bd8;
mbedtls_md5_free = 0x40002bdc;
mbedtls_md5_clone = 0x40002be0;
mbedtls_md5_starts_ret = 0x40002be4;
mbedtls_md5_update_ret = 0x40002be8;
mbedtls_md5_finish_ret = 0x40002bec;
mbedtls_internal_md5_process = 0x40002bf0;
mbedtls_md5_ret = 0x40002bf4;
mbedtls_pk_get_bitlen = 0x40002bf8;
mbedtls_pk_sign = 0x40002bfc;
mbedtls_pk_decrypt = 0x40002c00;
mbedtls_pk_parse_key = 0x40002c04;
mbedtls_sha1_ret = 0x40002c08;
mbedtls_ssl_init = 0x40002c0c;
mbedtls_ssl_setup = 0x40002c10;
mbedtls_ssl_conf_authmode = 0x40002c14;
mbedtls_ssl_conf_rng = 0x40002c18;
mbedtls_ssl_conf_ca_chain = 0x40002c1c;
mbedtls_ssl_conf_own_cert = 0x40002c20;
mbedtls_ssl_read = 0x40002c24;
mbedtls_ssl_write = 0x40002c28;
mbedtls_ssl_config_init = 0x40002c2c;
mbedtls_ssl_sig_hash_set_find = 0x40002c30;
mbedtls_ssl_sig_hash_set_add = 0x40002c34;
mbedtls_ssl_sig_hash_set_const_hash = 0x40002c38;
mbedtls_ssl_sig_from_pk_alg = 0x40002c3c;
mbedtls_ssl_set_calc_verify_md = 0x40002c40;
mbedtls_x509_crt_parse = 0x40002c44;
/* Data (.data, .bss, .rodata) */
p_osi_mbedtls_rom_funcs = 0x3fcdfaa0;
mbedtls_x509_crt_profile_default = 0x3ff4fba4;
mbedtls_x509_crt_profile_suiteb = 0x3ff4fb94;
aes_FSb_ptr = 0x3fcdfa9c;
AES_RT0_ptr = 0x3fcdfa98;
AES_RT1_ptr = 0x3fcdfa94;
AES_RT2_ptr = 0x3fcdfa90;
AES_RT3_ptr = 0x3fcdfa8c;
AES_FT0_ptr = 0x3fcdfa88;
AES_FT1_ptr = 0x3fcdfa84;
AES_FT2_ptr = 0x3fcdfa80;
AES_FT3_ptr = 0x3fcdfa7c;
bignum_small_prime_ptr = 0x3fcdfa78;
sha512_K_ptr = 0x3fcdfa74;


Update linker script.

Update linker script.

/*
 * Copyright (C) 2015-2017 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */

/**
 * @addtogroup      cpu_{{ family }}
 * @{
 *
 * @file
 * @brief           Memory definitions for the {{ cpu|upper }} CPU
 *
 * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
 * @author          Bas Stottelaar <basstottelaar@gmail.com>
 *
 * @}
 */

MEMORY
{
    rom (rx)    : ORIGIN = {{ flash_base|hex(8) }}, LENGTH = {{ flash_size }}
    ram (rwx)   : ORIGIN = {{ sram_base|hex(8) }}, LENGTH = {{ sram_size }}
}

INCLUDE cortexm_base.ld

/*
 * Copyright (C) 2016 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */

/**
 * @addtogroup      cpu_{{ family }}
 * @{
 *
 * @file
 * @brief           Memory definitions for the {{ cpu|upper }} CPU
 *
 * @}
 */

MEMORY
{
    rom (rx)    : ORIGIN = 0x00000000, LENGTH = {{ flash_size }}
    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = {{ sram_size }}
}

INCLUDE cortexm_base.ld