xtensa: cavs_v18: use uncached addresses to support SMP

SMP support on cAVS is implemented by using uncached addresses
for all writable data sections except for stack, i.e. for .data,
.bss and some other specialised ones. So far that has been
implemented for cAVS 1.5. This patch does the same for cAVS 1.8.

Signed-off-by: Guennadi Liakhovetski <974fc78730de35b120231422a86eeefcb293601e@linux.intel.com>

/*
 * Copyright (c) 2019 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Linker command/script file
 *
 * Linker script for the intel_apl_adsp platform
 */

OUTPUT_ARCH(xtensa)

#include <devicetree.h>
#include <xtensa/config/core-isa.h>
#include <soc/memory.h>
#include <autoconf.h>
#include <linker/sections.h>

#include <linker/linker-defs.h>
#include <linker/linker-tool.h>

PROVIDE(__memctl_default = 0x00000000);
PROVIDE(_MemErrorHandler = 0x00000000);

#define LP_SRAM_REGION lpram

/* DSP RAM regions (all of them) are mapped twice on the DSP: once in
 * a 512MB region from 0x80000000-0x9fffffff and again from
 * 0xa0000000-0xbfffffff.  The first mapping is set up to bypass the
 * L1 cache, so it must be used when multiprocessor coherence is
 * desired, where the latter mapping is best used for processor-local
 * data (e.g. stacks) or shared data that is managed with explicit
 * cache flush/invalidate operations.
 *
 * These macros will set up a segment start address correctly,
 * including alignment to a cache line.  Be sure to also emit the
 * section to ">ram :ram_phdr" or ">ucram :ucram_phdr" as
 * appropriate. (Forgetting the correct PHDR will actually work, as
 * the output tooling ignores it, but it will cause the linker to emit
 * 512MB of unused data into the output file!)
 *
 */
#define SEGSTART_CACHED   (ALIGN(64) | 0x20000000)
#define SEGSTART_UNCACHED (ALIGN(64) & ~0x20000000)

MEMORY
{
  vector_memory_lit :
	org = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,
        len = MEM_ERROR_LIT_SIZE
  vector_memory_text :
	org = XCHAL_MEMERROR_VECTOR_PADDR,
        len = MEM_ERROR_TEXT_SIZE
  vector_base_text :
	org = XCHAL_VECBASE_RESET_PADDR_SRAM,
        len = MEM_VECBASE_LIT_SIZE
  vector_int2_lit :
	org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int2_text :
        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int3_lit :
	org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int3_text :
	org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int4_lit :
	org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int4_text :
	org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int5_lit :
	org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int5_text :
	org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int6_lit :
	org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int6_text :
	org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int7_lit :
	org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int7_text :
	org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_kernel_lit :
	org = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_kernel_text :
	org = XCHAL_KERNEL_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_user_lit :
	org = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_user_text :
	org = XCHAL_USER_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_double_lit :
	org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_double_text :
	org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  ram :
	org = RAM_BASE,
	len = RAM_SIZE
  ucram :
	org = RAM_BASE - 0x20000000,
	len = RAM_SIZE
#ifdef CONFIG_GEN_ISR_TABLES
  IDT_LIST :
	org = IDT_BASE,
	len = IDT_SIZE
#endif
  lpram :
	org = LP_SRAM_BASE,
	len = LP_SRAM_SIZE

  static_uuid_entries_seg (!ari) :
        org = UUID_ENTRY_ELF_BASE,
        len = UUID_ENTRY_ELF_SIZE
  static_log_entries_seg (!ari) :
        org = LOG_ENTRY_ELF_BASE,
        len = LOG_ENTRY_ELF_SIZE
  fw_metadata_seg (!ari) :
        org = EXT_MANIFEST_ELF_BASE,
        len = EXT_MANIFEST_ELF_SIZE
}

PHDRS
{
  vector_memory_lit_phdr PT_LOAD;
  vector_memory_text_phdr PT_LOAD;
  vector_base_text_phdr PT_LOAD;
  vector_int2_lit_phdr PT_LOAD;
  vector_int2_text_phdr PT_LOAD;
  vector_int3_lit_phdr PT_LOAD;
  vector_int3_text_phdr PT_LOAD;
  vector_int4_lit_phdr PT_LOAD;
  vector_int4_text_phdr PT_LOAD;
  vector_int5_lit_phdr PT_LOAD;
  vector_int5_text_phdr PT_LOAD;
  vector_int6_lit_phdr PT_LOAD;
  vector_int6_text_phdr PT_LOAD;
  vector_int7_lit_phdr PT_LOAD;
  vector_int7_text_phdr PT_LOAD;
  vector_kernel_lit_phdr PT_LOAD;
  vector_kernel_text_phdr PT_LOAD;
  vector_user_lit_phdr PT_LOAD;
  vector_user_text_phdr PT_LOAD;
  vector_double_lit_phdr PT_LOAD;
  vector_double_text_phdr PT_LOAD;
  ram_phdr PT_LOAD;
  ucram_phdr PT_LOAD;
  static_uuid_entries_phdr PT_NOTE;
  static_log_entries_phdr PT_NOTE;
  metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);

ENTRY(CONFIG_KERNEL_ENTRY)

/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
_memmap_cacheattr_wt_base = 0x11021000;
_memmap_cacheattr_bp_base = 0x22022000;
_memmap_cacheattr_unused_mask = 0x00F00FFF;
_memmap_cacheattr_wb_trapnull = 0x4422422F;
_memmap_cacheattr_wba_trapnull = 0x4422422F;
_memmap_cacheattr_wbna_trapnull = 0x25222222;
_memmap_cacheattr_wt_trapnull = 0x1122122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0x44F24FFF;
_memmap_cacheattr_wt_strict = 0x11F21FFF;
_memmap_cacheattr_bp_strict = 0x22F22FFF;
_memmap_cacheattr_wb_allvalid = 0x44224222;
_memmap_cacheattr_wt_allvalid = 0x11221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;

/*
 * Cache attributes for memory addresses:
 * (Each 4 bits correspond to 512MB of memory)
 *
 * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache
 *                                         (region for hardware registers)
 * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access
 * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access
 * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access
 * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache
 * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back
 * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access
 * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access
 *
 * Note that this is both for instruction and data caches,
 * as cacheattr_set macro sets them both to the same set of
 * attributes.
 */
_memmap_cacheattr_intel_cavs18_adsp = 0xFF42FFF2;

PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);

_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)

SECTIONS
{

#include <linker/rel-sections.ld>

 .MemoryExceptionVector.literal : ALIGN(4)
  {
    _MemoryExceptionVector_literal_start = ABSOLUTE(.);
    KEEP (*(.MemoryExceptionVector.literal))
    _MemoryExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_memory_lit :vector_memory_lit_phdr
  .MemoryExceptionVector.text : ALIGN(4)
  {
    _MemoryExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.MemoryExceptionVector.text))
    _MemoryExceptionVector_text_end = ABSOLUTE(.);
  } >vector_memory_text :vector_memory_text_phdr
   .WindowVectors.text : ALIGN(4)
  {
    _WindowVectors_text_start = ABSOLUTE(.);
    KEEP (*(.WindowVectors.text))
    _WindowVectors_text_end = ABSOLUTE(.);
  } >vector_base_text :vector_base_text_phdr
  .Level2InterruptVector.literal : ALIGN(4)
  {
    _Level2InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level2InterruptVector.literal)
    _Level2InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int2_lit :vector_int2_lit_phdr
  .Level2InterruptVector.text : ALIGN(4)
  {
    _Level2InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level2InterruptVector.text))
    _Level2InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int2_text :vector_int2_text_phdr
  .Level3InterruptVector.literal : ALIGN(4)
  {
    _Level3InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level3InterruptVector.literal)
    _Level3InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int3_lit :vector_int3_lit_phdr
  .Level3InterruptVector.text : ALIGN(4)
  {
    _Level3InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level3InterruptVector.text))
    _Level3InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int3_text :vector_int3_text_phdr
  .Level4InterruptVector.literal : ALIGN(4)
  {
    _Level4InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level4InterruptVector.literal)
    _Level4InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int4_lit :vector_int4_lit_phdr
  .Level4InterruptVector.text : ALIGN(4)
  {
    _Level4InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level4InterruptVector.text))
    _Level4InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int4_text :vector_int4_text_phdr
  .Level5InterruptVector.literal : ALIGN(4)
  {
    _Level5InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level5InterruptVector.literal)
    _Level5InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int5_lit :vector_int5_lit_phdr
  .Level5InterruptVector.text : ALIGN(4)
  {
    _Level5InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level5InterruptVector.text))
    _Level5InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int5_text :vector_int5_text_phdr
  .DebugExceptionVector.literal : ALIGN(4)
  {
    _DebugExceptionVector_literal_start = ABSOLUTE(.);
    *(.DebugExceptionVector.literal)
    _DebugExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_int6_lit :vector_int6_lit_phdr
  .DebugExceptionVector.text : ALIGN(4)
  {
    _DebugExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.DebugExceptionVector.text))
    _DebugExceptionVector_text_end = ABSOLUTE(.);
  } >vector_int6_text :vector_int6_text_phdr
  .NMIExceptionVector.literal : ALIGN(4)
  {
    _NMIExceptionVector_literal_start = ABSOLUTE(.);
    *(.NMIExceptionVector.literal)
    _NMIExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_int7_lit :vector_int7_lit_phdr
  .NMIExceptionVector.text : ALIGN(4)
  {
    _NMIExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.NMIExceptionVector.text))
    _NMIExceptionVector_text_end = ABSOLUTE(.);
  } >vector_int7_text :vector_int7_text_phdr
  .KernelExceptionVector.literal : ALIGN(4)
  {
    _KernelExceptionVector_literal_start = ABSOLUTE(.);
    *(.KernelExceptionVector.literal)
    _KernelExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_kernel_lit :vector_kernel_lit_phdr
  .KernelExceptionVector.text : ALIGN(4)
  {
    _KernelExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.KernelExceptionVector.text))
    _KernelExceptionVector_text_end = ABSOLUTE(.);
  } >vector_kernel_text :vector_kernel_text_phdr
  .UserExceptionVector.literal : ALIGN(4)
  {
    _UserExceptionVector_literal_start = ABSOLUTE(.);
    *(.UserExceptionVector.literal)
    _UserExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_user_lit :vector_user_lit_phdr
  .UserExceptionVector.text : ALIGN(4)
  {
    _UserExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.UserExceptionVector.text))
    _UserExceptionVector_text_end = ABSOLUTE(.);
  } >vector_user_text :vector_user_text_phdr
  .DoubleExceptionVector.literal : ALIGN(4)
  {
    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
    *(.DoubleExceptionVector.literal)
    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_double_lit :vector_double_lit_phdr
  .DoubleExceptionVector.text : ALIGN(4)
  {
    _DoubleExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.DoubleExceptionVector.text))
    _DoubleExceptionVector_text_end = ABSOLUTE(.);
  } >vector_double_text :vector_double_text_phdr

  .text : ALIGN(4)
  {
    _stext = .;
    _text_start = ABSOLUTE(.);
    KEEP(*(.MainEntry.text))
    *(.MainEntry.literal)
    KEEP (*(.ResetVector.text))
    *(.ResetVector.literal)
    *(.entry.text)
    *(.init.literal)
    *(.iram0.text)
    KEEP(*(.init))
    KEEP(*(.lps_vector))
    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
    *(.fini.literal)
    KEEP(*(.fini))
    *(.gnu.version)
    _text_end = ABSOLUTE(.);
    _etext = .;
    . = ALIGN(4096);
  } >ram :ram_phdr

  .rodata : ALIGN(4096)
  {
    _rodata_start = ABSOLUTE(.);
    *(.rodata)
    *(.rodata.*)
    *(.gnu.linkonce.r.*)
    *(.rodata1)
    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
    KEEP (*(.xt_except_table))
    KEEP (*(.gcc_except_table .gcc_except_table.*))
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
    KEEP (*(.eh_frame))
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
    *(.xt_except_desc)
    *(.gnu.linkonce.h.*)
    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
    *(.xt_except_desc_end)
    *(.dynamic)
    *(.gnu.version_d)
    . = ALIGN(4);
    _bss_table_start = ABSOLUTE(.);
    LONG(_bss_start)
    LONG(_bss_end)
    _bss_table_end = ABSOLUTE(.);
    _rodata_end = ABSOLUTE(.);
  } >ram :ram_phdr

  .module_init : ALIGN(4)
  {
    _module_init_start = ABSOLUTE(.);
    *(*.module_init)
    _module_init_end = ABSOLUTE(.);
  } >ram :ram_phdr

#define RAMABLE_REGION ram :ram_phdr
#define ROMABLE_REGION ram :ram_phdr
#include <linker/common-rom.ld>

  .fw_ready : ALIGN(4)
  {
    KEEP(*(".fw_ready"));
    KEEP (*(.fw_ready_metadata))
  } >ram :ram_phdr

  .noinit SEGSTART_UNCACHED : ALIGN(4)
  {
    *(.noinit)
    *(.noinit.*)
  } >ucram :ucram_phdr

  .data SEGSTART_UNCACHED : ALIGN(4)
  {
    _data_start = ABSOLUTE(.);
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
    KEEP(*(.gnu.linkonce.d.*personality*))
    *(.data1)
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    KEEP(*(.jcr))
    . = ALIGN(4096);
    *(.gna_model)
    _data_end = ABSOLUTE(.);
    . = ALIGN(4096);
  } >ucram :ucram_phdr

  .lit4 SEGSTART_CACHED : ALIGN(4)
  {
    _lit4_start = ABSOLUTE(.);
    *(*.lit4)
    *(.lit4.*)
    *(.gnu.linkonce.lit4.*)
    _lit4_end = ABSOLUTE(.);
  } >ram :ram_phdr

/* These values need to change in our scheme, where the common-ram
 * sections need to be linked in safe/uncached memory but common-rom
 * wants to use the cache
 */

  . = SEGSTART_UNCACHED;

#undef RAMABLE_REGION
#undef ROMABLE_REGION
#define RAMABLE_REGION ucram :ucram_phdr
#define ROMABLE_REGION ucram :ucram_phdr

#include <linker/common-ram.ld>

  /* This section is cached.  By default it contains only declared
   * thread stacks, but applications can put symbols here too.
   */
  .cached SEGSTART_CACHED :
  {
    *(.cached .cached.*)
  } >ram :ram_phdr

  . = ALIGN(4096);

  .bss SEGSTART_UNCACHED (NOLOAD) :
  {
    _bss_start = ABSOLUTE(.);
    *(.dynsbss)
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    *(.scommon)
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    *(.dynbss)
    *(.bss)
    *(.bss.*)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN(8);
    _bss_end = ABSOLUTE(.);
  } >ucram :ucram_phdr

  . = SEGSTART_UNCACHED;
  _end = ALIGN(8);
  PROVIDE(end = ALIGN(8));

  /* Re-adjust to the upper mapping for the final symbols below */
  . = SEGSTART_CACHED;
  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;

  . = SEGSTART_UNCACHED;

  /* dma buffers */
  .lpbuf (NOLOAD): ALIGN(4)
  {
    _dma_buf_start = ABSOLUTE(.);
    *(.dma_buffers)
    _dma_buf_end = ABSOLUTE(.);
  } >LP_SRAM_REGION

  . = L2_SRAM_BASE + L2_SRAM_SIZE;
  . = SEGSTART_UNCACHED;
  _heap_sentry = .;

  .comment  0 :  { *(.comment) }
  .debug 0 : { *(.debug) }
  .line 0 : { *(.line) }
  .debug_srcinfo 0 : { *(.debug_srcinfo) }
  .debug_sfnames 0 : { *(.debug_sfnames) }
  .debug_aranges 0 : { *(.debug_aranges) }
  .debug_pubnames 0 : { *(.debug_pubnames) }
  .debug_info 0 : { *(.debug_info) }
  .debug_abbrev 0 : { *(.debug_abbrev) }
  .debug_line 0 : { *(.debug_line) }
  .debug_frame 0 : { *(.debug_frame) }
  .debug_str 0 : { *(.debug_str) }
  .debug_loc 0 : { *(.debug_loc) }
  .debug_macinfo 0 : { *(.debug_macinfo) }
  .debug_weaknames 0 : { *(.debug_weaknames) }
  .debug_funcnames 0 : { *(.debug_funcnames) }
  .debug_typenames 0 : { *(.debug_typenames) }
  .debug_varnames 0 : { *(.debug_varnames) }
  .debug_ranges  0 :  { *(.debug_ranges) }
  .xtensa.info  0 :  { *(.xtensa.info) }
  .xt.insn 0 :
  {
    KEEP (*(.xt.insn))
    KEEP (*(.gnu.linkonce.x.*))
  }
  .xt.prop 0 :
  {
    KEEP (*(.xt.prop))
    KEEP (*(.xt.prop.*))
    KEEP (*(.gnu.linkonce.prop.*))
  }
  .xt.lit 0 :
  {
    KEEP (*(.xt.lit))
    KEEP (*(.xt.lit.*))
    KEEP (*(.gnu.linkonce.p.*))
  }
  .xt.profile_range 0 :
  {
    KEEP (*(.xt.profile_range))
    KEEP (*(.gnu.linkonce.profile_range.*))
  }
  .xt.profile_ranges 0 :
  {
    KEEP (*(.xt.profile_ranges))
    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
  }
  .xt.profile_files 0 :
  {
    KEEP (*(.xt.profile_files))
    KEEP (*(.gnu.linkonce.xt.profile_files.*))
  }
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif

 .static_uuid_entries (COPY) : ALIGN(1024)
  {
    *(*.static_uuids)
  } > static_uuid_entries_seg :static_uuid_entries_phdr

  .static_log_entries (COPY) : ALIGN(1024)
  {
    *(*.static_log*)
  } > static_log_entries_seg :static_log_entries_phdr

  .fw_metadata (COPY) : ALIGN(1024)
  {
    KEEP (*(.fw_metadata))
    . = ALIGN(_EXT_MAN_ALIGN_);
  } >fw_metadata_seg :metadata_entries_phdr
}

/*
 * Copyright (c) 2019 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Linker command/script file
 *
 * Linker script for the intel_apl_adsp platform
 */

OUTPUT_ARCH(xtensa)

#include <devicetree.h>
#include <xtensa/config/core-isa.h>
#include <soc/memory.h>
#include <autoconf.h>
#include <linker/sections.h>

#include <linker/linker-defs.h>
#include <linker/linker-tool.h>

PROVIDE(__memctl_default = 0x00000000);
PROVIDE(_MemErrorHandler = 0x00000000);

#define RAMABLE_REGION ram :ram_phdr
#define ROMABLE_REGION ram :ram_phdr
#define LP_SRAM_REGION lpram

MEMORY
{
  vector_memory_lit :
	org = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,
        len = MEM_ERROR_LIT_SIZE
  vector_memory_text :
	org = XCHAL_MEMERROR_VECTOR_PADDR,
        len = MEM_ERROR_TEXT_SIZE
  vector_base_text :
	org = XCHAL_VECBASE_RESET_PADDR_SRAM,
        len = MEM_VECBASE_LIT_SIZE
  vector_int2_lit :
	org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int2_text :
        org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int3_lit :
	org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int3_text :
	org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int4_lit :
	org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int4_text :
	org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int5_lit :
	org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int5_text :
	org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int6_lit :
	org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int6_text :
	org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_int7_lit :
	org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_int7_text :
	org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_kernel_lit :
	org = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_kernel_text :
	org = XCHAL_KERNEL_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_user_lit :
	org = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_user_text :
	org = XCHAL_USER_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  vector_double_lit :
	org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
        len = MEM_VECT_LIT_SIZE
  vector_double_text :
	org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,
        len = MEM_VECT_TEXT_SIZE
  ram :
	org = RAM_BASE,
	len = RAM_SIZE
#ifdef CONFIG_GEN_ISR_TABLES
  IDT_LIST :
	org = IDT_BASE,
	len = IDT_SIZE
#endif
  lpram :
	org = LP_SRAM_BASE,
	len = LP_SRAM_SIZE

  static_uuid_entries_seg (!ari) :
        org = UUID_ENTRY_ELF_BASE,
        len = UUID_ENTRY_ELF_SIZE
  static_log_entries_seg (!ari) :
        org = LOG_ENTRY_ELF_BASE,
        len = LOG_ENTRY_ELF_SIZE
  fw_metadata_seg (!ari) :
        org = EXT_MANIFEST_ELF_BASE,
        len = EXT_MANIFEST_ELF_SIZE
}

PHDRS
{
  vector_memory_lit_phdr PT_LOAD;
  vector_memory_text_phdr PT_LOAD;
  vector_base_text_phdr PT_LOAD;
  vector_int2_lit_phdr PT_LOAD;
  vector_int2_text_phdr PT_LOAD;
  vector_int3_lit_phdr PT_LOAD;
  vector_int3_text_phdr PT_LOAD;
  vector_int4_lit_phdr PT_LOAD;
  vector_int4_text_phdr PT_LOAD;
  vector_int5_lit_phdr PT_LOAD;
  vector_int5_text_phdr PT_LOAD;
  vector_int6_lit_phdr PT_LOAD;
  vector_int6_text_phdr PT_LOAD;
  vector_int7_lit_phdr PT_LOAD;
  vector_int7_text_phdr PT_LOAD;
  vector_kernel_lit_phdr PT_LOAD;
  vector_kernel_text_phdr PT_LOAD;
  vector_user_lit_phdr PT_LOAD;
  vector_user_text_phdr PT_LOAD;
  vector_double_lit_phdr PT_LOAD;
  vector_double_text_phdr PT_LOAD;
  ram_phdr PT_LOAD;

  static_uuid_entries_phdr PT_NOTE;
  static_log_entries_phdr PT_NOTE;
  metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);

ENTRY(CONFIG_KERNEL_ENTRY)

/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
_memmap_cacheattr_wt_base = 0x11021000;
_memmap_cacheattr_bp_base = 0x22022000;
_memmap_cacheattr_unused_mask = 0x00F00FFF;
_memmap_cacheattr_wb_trapnull = 0x4422422F;
_memmap_cacheattr_wba_trapnull = 0x4422422F;
_memmap_cacheattr_wbna_trapnull = 0x25222222;
_memmap_cacheattr_wt_trapnull = 0x1122122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0x44F24FFF;
_memmap_cacheattr_wt_strict = 0x11F21FFF;
_memmap_cacheattr_bp_strict = 0x22F22FFF;
_memmap_cacheattr_wb_allvalid = 0x44224222;
_memmap_cacheattr_wt_allvalid = 0x11221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;

/*
 * Cache attributes for memory addresses:
 * (Each 4 bits correspond to 512MB of memory)
 *
 * 0x00000000 - 0x1FFFFFFF (bit  0 -  3) : Bypass cache
 *                                         (region for hardware registers)
 * 0x20000000 - 0x3FFFFFFF (bit  4 -  7) : No access
 * 0x40000000 - 0x5FFFFFFF (bit  8 - 11) : No access
 * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access
 * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache
 * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-back
 * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : No access
 * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : No access
 *
 * Note that this is both for instruction and data caches,
 * as cacheattr_set macro sets them both to the same set of
 * attributes.
 */
#ifndef CONFIG_SMP
_memmap_cacheattr_intel_cavs18_adsp = 0xFF42FFF2;
#else
/*
 * FIXME: Make 0xA0000000 - 0xBFFFFFFF to bypass cache under SMP
 * since there is no data cache manipulation for spinlock, kernel
 * object, scheduler, etc...
 */
_memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2;
#endif

PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);

_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)

SECTIONS
{

#include <linker/rel-sections.ld>

 .MemoryExceptionVector.literal : ALIGN(4)
  {
    _MemoryExceptionVector_literal_start = ABSOLUTE(.);
    KEEP (*(.MemoryExceptionVector.literal))
    _MemoryExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_memory_lit :vector_memory_lit_phdr
  .MemoryExceptionVector.text : ALIGN(4)
  {
    _MemoryExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.MemoryExceptionVector.text))
    _MemoryExceptionVector_text_end = ABSOLUTE(.);
  } >vector_memory_text :vector_memory_text_phdr
   .WindowVectors.text : ALIGN(4)
  {
    _WindowVectors_text_start = ABSOLUTE(.);
    KEEP (*(.WindowVectors.text))
    _WindowVectors_text_end = ABSOLUTE(.);
  } >vector_base_text :vector_base_text_phdr
  .Level2InterruptVector.literal : ALIGN(4)
  {
    _Level2InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level2InterruptVector.literal)
    _Level2InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int2_lit :vector_int2_lit_phdr
  .Level2InterruptVector.text : ALIGN(4)
  {
    _Level2InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level2InterruptVector.text))
    _Level2InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int2_text :vector_int2_text_phdr
  .Level3InterruptVector.literal : ALIGN(4)
  {
    _Level3InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level3InterruptVector.literal)
    _Level3InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int3_lit :vector_int3_lit_phdr
  .Level3InterruptVector.text : ALIGN(4)
  {
    _Level3InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level3InterruptVector.text))
    _Level3InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int3_text :vector_int3_text_phdr
  .Level4InterruptVector.literal : ALIGN(4)
  {
    _Level4InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level4InterruptVector.literal)
    _Level4InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int4_lit :vector_int4_lit_phdr
  .Level4InterruptVector.text : ALIGN(4)
  {
    _Level4InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level4InterruptVector.text))
    _Level4InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int4_text :vector_int4_text_phdr
  .Level5InterruptVector.literal : ALIGN(4)
  {
    _Level5InterruptVector_literal_start = ABSOLUTE(.);
    *(.Level5InterruptVector.literal)
    _Level5InterruptVector_literal_end = ABSOLUTE(.);
  } >vector_int5_lit :vector_int5_lit_phdr
  .Level5InterruptVector.text : ALIGN(4)
  {
    _Level5InterruptVector_text_start = ABSOLUTE(.);
    KEEP (*(.Level5InterruptVector.text))
    _Level5InterruptVector_text_end = ABSOLUTE(.);
  } >vector_int5_text :vector_int5_text_phdr
  .DebugExceptionVector.literal : ALIGN(4)
  {
    _DebugExceptionVector_literal_start = ABSOLUTE(.);
    *(.DebugExceptionVector.literal)
    _DebugExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_int6_lit :vector_int6_lit_phdr
  .DebugExceptionVector.text : ALIGN(4)
  {
    _DebugExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.DebugExceptionVector.text))
    _DebugExceptionVector_text_end = ABSOLUTE(.);
  } >vector_int6_text :vector_int6_text_phdr
  .NMIExceptionVector.literal : ALIGN(4)
  {
    _NMIExceptionVector_literal_start = ABSOLUTE(.);
    *(.NMIExceptionVector.literal)
    _NMIExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_int7_lit :vector_int7_lit_phdr
  .NMIExceptionVector.text : ALIGN(4)
  {
    _NMIExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.NMIExceptionVector.text))
    _NMIExceptionVector_text_end = ABSOLUTE(.);
  } >vector_int7_text :vector_int7_text_phdr
  .KernelExceptionVector.literal : ALIGN(4)
  {
    _KernelExceptionVector_literal_start = ABSOLUTE(.);
    *(.KernelExceptionVector.literal)
    _KernelExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_kernel_lit :vector_kernel_lit_phdr
  .KernelExceptionVector.text : ALIGN(4)
  {
    _KernelExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.KernelExceptionVector.text))
    _KernelExceptionVector_text_end = ABSOLUTE(.);
  } >vector_kernel_text :vector_kernel_text_phdr
  .UserExceptionVector.literal : ALIGN(4)
  {
    _UserExceptionVector_literal_start = ABSOLUTE(.);
    *(.UserExceptionVector.literal)
    _UserExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_user_lit :vector_user_lit_phdr
  .UserExceptionVector.text : ALIGN(4)
  {
    _UserExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.UserExceptionVector.text))
    _UserExceptionVector_text_end = ABSOLUTE(.);
  } >vector_user_text :vector_user_text_phdr
  .DoubleExceptionVector.literal : ALIGN(4)
  {
    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
    *(.DoubleExceptionVector.literal)
    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
  } >vector_double_lit :vector_double_lit_phdr
  .DoubleExceptionVector.text : ALIGN(4)
  {
    _DoubleExceptionVector_text_start = ABSOLUTE(.);
    KEEP (*(.DoubleExceptionVector.text))
    _DoubleExceptionVector_text_end = ABSOLUTE(.);
  } >vector_double_text :vector_double_text_phdr

  .text : ALIGN(4)
  {
    _stext = .;
    _text_start = ABSOLUTE(.);
    KEEP(*(.MainEntry.text))
    *(.MainEntry.literal)
    KEEP (*(.ResetVector.text))
    *(.ResetVector.literal)
    *(.entry.text)
    *(.init.literal)
    *(.iram0.text)
    KEEP(*(.init))
    KEEP(*(.lps_vector))
    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
    *(.fini.literal)
    KEEP(*(.fini))
    *(.gnu.version)
    _text_end = ABSOLUTE(.);
    _etext = .;
    . = ALIGN(4096);
  } >ram :ram_phdr

  .rodata : ALIGN(4096)
  {
    _rodata_start = ABSOLUTE(.);
    *(.rodata)
    *(.rodata.*)
    *(.gnu.linkonce.r.*)
    *(.rodata1)
    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
    KEEP (*(.xt_except_table))
    KEEP (*(.gcc_except_table .gcc_except_table.*))
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
    KEEP (*(.eh_frame))
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
    *(.xt_except_desc)
    *(.gnu.linkonce.h.*)
    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
    *(.xt_except_desc_end)
    *(.dynamic)
    *(.gnu.version_d)
    . = ALIGN(4);
    _bss_table_start = ABSOLUTE(.);
    LONG(_bss_start)
    LONG(_bss_end)
    _bss_table_end = ABSOLUTE(.);
    _rodata_end = ABSOLUTE(.);
  } >ram :ram_phdr
  .module_init : ALIGN(4)
  {
    _module_init_start = ABSOLUTE(.);
    *(*.module_init)
    _module_init_end = ABSOLUTE(.);
  } >ram :ram_phdr

#include <linker/common-rom.ld>

  .fw_ready : ALIGN(4)
  {
    KEEP(*(".fw_ready"));
    KEEP (*(.fw_ready_metadata))
  } >ram :ram_phdr

  .noinit : ALIGN(4)
  {
    *(.noinit)
    *(.noinit.*)
  } >ram :ram_phdr

  .data : ALIGN(4)
  {
    _data_start = ABSOLUTE(.);
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
    KEEP(*(.gnu.linkonce.d.*personality*))
    *(.data1)
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    KEEP(*(.jcr))
    . = ALIGN(4096);
    *(.gna_model)
    _data_end = ABSOLUTE(.);
    . = ALIGN(4096);
  } >ram :ram_phdr
  .lit4 : ALIGN(4)
  {
    _lit4_start = ABSOLUTE(.);
    *(*.lit4)
    *(.lit4.*)
    *(.gnu.linkonce.lit4.*)
    _lit4_end = ABSOLUTE(.);
  } >ram :ram_phdr
#include <linker/common-ram.ld>

  .bss (NOLOAD) : ALIGN(4096)
  {
    . = ALIGN(4096);
    _bss_start = ABSOLUTE(.);
    *(.dynsbss)
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    *(.scommon)
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    *(.dynbss)
    *(.bss)
    *(.bss.*)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN(8);
    _bss_end = ABSOLUTE(.);
  } >ram :ram_phdr

  /* stack */
  _end = ALIGN(8);
  PROVIDE(end = ALIGN(8));
  __stack = L2_SRAM_BASE + L2_SRAM_SIZE;
  /* dma buffers */
  .lpbuf (NOLOAD): ALIGN(4)
  {
    _dma_buf_start = ABSOLUTE(.);
    *(.dma_buffers)
    _dma_buf_end = ABSOLUTE(.);
  } >LP_SRAM_REGION
  _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE;
  .comment  0 :  { *(.comment) }
  .debug 0 : { *(.debug) }
  .line 0 : { *(.line) }
  .debug_srcinfo 0 : { *(.debug_srcinfo) }
  .debug_sfnames 0 : { *(.debug_sfnames) }
  .debug_aranges 0 : { *(.debug_aranges) }
  .debug_pubnames 0 : { *(.debug_pubnames) }
  .debug_info 0 : { *(.debug_info) }
  .debug_abbrev 0 : { *(.debug_abbrev) }
  .debug_line 0 : { *(.debug_line) }
  .debug_frame 0 : { *(.debug_frame) }
  .debug_str 0 : { *(.debug_str) }
  .debug_loc 0 : { *(.debug_loc) }
  .debug_macinfo 0 : { *(.debug_macinfo) }
  .debug_weaknames 0 : { *(.debug_weaknames) }
  .debug_funcnames 0 : { *(.debug_funcnames) }
  .debug_typenames 0 : { *(.debug_typenames) }
  .debug_varnames 0 : { *(.debug_varnames) }
  .debug_ranges  0 :  { *(.debug_ranges) }
  .xtensa.info  0 :  { *(.xtensa.info) }
  .xt.insn 0 :
  {
    KEEP (*(.xt.insn))
    KEEP (*(.gnu.linkonce.x.*))
  }
  .xt.prop 0 :
  {
    KEEP (*(.xt.prop))
    KEEP (*(.xt.prop.*))
    KEEP (*(.gnu.linkonce.prop.*))
  }
  .xt.lit 0 :
  {
    KEEP (*(.xt.lit))
    KEEP (*(.xt.lit.*))
    KEEP (*(.gnu.linkonce.p.*))
  }
  .xt.profile_range 0 :
  {
    KEEP (*(.xt.profile_range))
    KEEP (*(.gnu.linkonce.profile_range.*))
  }
  .xt.profile_ranges 0 :
  {
    KEEP (*(.xt.profile_ranges))
    KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
  }
  .xt.profile_files 0 :
  {
    KEEP (*(.xt.profile_files))
    KEEP (*(.gnu.linkonce.xt.profile_files.*))
  }
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif

 .static_uuid_entries (COPY) : ALIGN(1024)
  {
    *(*.static_uuids)
  } > static_uuid_entries_seg :static_uuid_entries_phdr

  .static_log_entries (COPY) : ALIGN(1024)
  {
    *(*.static_log*)
  } > static_log_entries_seg :static_log_entries_phdr

  .fw_metadata (COPY) : ALIGN(1024)
  {
    KEEP (*(.fw_metadata))
    . = ALIGN(_EXT_MAN_ALIGN_);
  } >fw_metadata_seg :metadata_entries_phdr
}


some minor improvements

some minor improvements

ENTRY (init)

SECTIONS
{

    . = 0x00100000;

    .text ALIGN (0x1000) :
    {
        *(.mboot)
        *(.text)
    }

    .data ALIGN (0x1000) :
    {
        *(.rodata*)
        *(.data)
    }

    .bss :
    {
        *(.bss)
    }

}

ENTRY (init)

SECTIONS
{

    . = 0x00100000;

    .text :
    {
        *(.mboot)
        *(.text)
    }

    .data ALIGN (0x1000) :
    {
        *(.data)
        *(.rodata)
        *(.bss)
    }

}


linker: clarify CONFIG_KOBJECT_TEXT_AREA too small message

The assert error message when CONFIG_KOBJECT_TEXT_AREA is
too small is confusing. Probably the original idea is for
the linker to substitue CONFIG_KOBJECT_TEXT_AREA with
the actual value. However, linker does not do that.
So change the message to say that the kconfig value needs
to be increased.

Fixes #34387

Signed-off-by: Daniel Leung <d94e04d205b5962d7873a139ef298b03c1717f72@intel.com>

/* SPDX-License-Identifier: Apache-2.0 */

#ifdef CONFIG_USERSPACE
	/* We need to reserve room for the gperf generated hash functions.
	 * Fortunately, unlike the data tables, the size of the code is
	 * reasonably predictable.
	 *
	 * The linker will error out complaining that the location pointer
	 * is moving backwards if the reserved room isn't large enough.
	 */
	_kobject_text_area_start = .;
	*(".kobject_data.text*")
	_kobject_text_area_end = .;
	_kobject_text_area_used = _kobject_text_area_end - _kobject_text_area_start;
#ifndef LINKER_ZEPHYR_FINAL
#ifdef CONFIG_DYNAMIC_OBJECTS
	PROVIDE(z_object_gperf_find = .);
	PROVIDE(z_object_gperf_wordlist_foreach = .);
#else
	PROVIDE(z_object_find = .);
	PROVIDE(z_object_wordlist_foreach = .);
#endif
#endif

	/* In a valid build the MAX function will always evaluate to the
	second argument below, but to give the user a good error message
	when the area overflows we need to temporarily corrupt the
	location counter, and then detect the overflow with an assertion
	later on. */

	. = MAX(., _kobject_text_area_start + CONFIG_KOBJECT_TEXT_AREA);

	ASSERT(
		CONFIG_KOBJECT_TEXT_AREA >= _kobject_text_area_used,
"Reserved space for kobject text area is too small. \
Please change CONFIG_KOBJECT_TEXT_AREA to a larger number."
		);
#endif /* CONFIG_USERSPACE */

/* SPDX-License-Identifier: Apache-2.0 */

#ifdef CONFIG_USERSPACE
	/* We need to reserve room for the gperf generated hash functions.
	 * Fortunately, unlike the data tables, the size of the code is
	 * reasonably predictable.
	 *
	 * The linker will error out complaining that the location pointer
	 * is moving backwards if the reserved room isn't large enough.
	 */
	_kobject_text_area_start = .;
	*(".kobject_data.text*")
	_kobject_text_area_end = .;
	_kobject_text_area_used = _kobject_text_area_end - _kobject_text_area_start;
#ifndef LINKER_ZEPHYR_FINAL
#ifdef CONFIG_DYNAMIC_OBJECTS
	PROVIDE(z_object_gperf_find = .);
	PROVIDE(z_object_gperf_wordlist_foreach = .);
#else
	PROVIDE(z_object_find = .);
	PROVIDE(z_object_wordlist_foreach = .);
#endif
#endif

	/* In a valid build the MAX function will always evaluate to the
	second argument below, but to give the user a good error message
	when the area overflows we need to temporarily corrupt the
	location counter, and then detect the overflow with an assertion
	later on. */

	. = MAX(., _kobject_text_area_start + CONFIG_KOBJECT_TEXT_AREA);

	ASSERT(
		CONFIG_KOBJECT_TEXT_AREA >= _kobject_text_area_used,
"The configuration system has incorrectly set \
'CONFIG_KOBJECT_TEXT_AREA' to \
CONFIG_KOBJECT_TEXT_AREA, which is not big enough. You must \
through Kconfig either disable 'CONFIG_USERSPACE', or set \
'CONFIG_KOBJECT_TEXT_AREA' to a value larger than \
CONFIG_KOBJECT_TEXT_AREA."
		);
#endif /* CONFIG_USERSPACE */


Updated linker.ld

Updated linker.ld

OUTPUT_FORMAT(elf32-i386)
OUTPUT_ARCH(i386)
ENTRY(start)

Physical_address = 1M;

SECTIONS
{
	/* Load kernel at 1MB */
	. = Physical_address;

	/* Multiboot Header */
	.multiboot :
	{
		*(.multiboot)
	}

	/* Text section */
	.text :
	{
		*(.text)
	}

	/* Read-only data */
	.rodata :
	{
		*(.rodata)
	}

	/* Read-write data (initialized) */
	.data :
	{
		*(.data)
	}

	/* Read-write data (uninitialized) and stack */
	.bss :
	{
		*(COMMON)
		*(.bss)
	}

	.note.gnu.build-id :
	{
		*(.note.gnu.build-id)
	}
}

OUTPUT_FORMAT(elf32-i386)
OUTPUT_ARCH(i386)
ENTRY(start)

SECTIONS
{
	/* Load kernel at 1MB */
	. = 1M;

	/* Multiboot Header */
	.multiboot :
	{
		*(.multiboot)
	}

	/* Text section */
	.text :
	{
		*(.text)
	}

	/* Read-only data */
	.rodata :
	{
		*(.rodata)
	}

	/* Read-write data (initialized) */
	.data :
	{
		*(.data)
	}

	/* Read-write data (uninitialized) and stack */
	.bss :
	{
		*(COMMON)
		*(.bss)
	}

	.note.gnu.build-id :
	{
		*(.note.gnu.build-id)
	}
}


Try to fix broken build on some templates

PROVIDE(diag_init = nosys);
PROVIDE(diag_getc = nosys);
PROVIDE(diag_putc = nosys);

PROVIDE(irq_init     = nosys);
PROVIDE(irq_attach   = nosys);
PROVIDE(irq_detach   = nosys);
PROVIDE(irq_dispatch = nosys);

PROVIDE(softirq_init     = nosys);
PROVIDE(softirq_install  = nosys);
PROVIDE(softirq_raise    = nosys);
PROVIDE(softirq_dispatch = nosys);

PROVIDE(sched_lock = nosys);
PROVIDE(sched_unlock = nosys);

PROVIDE(printk = nosys);

PROVIDE(timer_init = nosys);
PROVIDE(set_timer = nosys);
PROVIDE(close_timer = nosys);
PROVIDE(timers_off = nosys);
PROVIDE(irq_func_tmr_1mS = nosys);
PROVIDE(usleep = nosys);

/* XXX remove from here. -- Eldar */
PROVIDE(uart_init = nosys);

PROVIDE(diag_init = nosys);
PROVIDE(diag_getc = nosys);
PROVIDE(diag_putc = nosys);

PROVIDE(irq_init     = nosys);
PROVIDE(irq_attach   = nosys);
PROVIDE(irq_detach   = nosys);
PROVIDE(irq_dispatch = nosys);

PROVIDE(softirq_init     = nosys);
PROVIDE(softirq_install  = nosys);
PROVIDE(softirq_raise    = nosys);
PROVIDE(softirq_dispatch = nosys);

PROVIDE(scheduler_lock = nosys);
PROVIDE(scheduler_unlock = nosys);

PROVIDE(printk = nosys);

PROVIDE(timer_init = nosys);
PROVIDE(set_timer = nosys);
PROVIDE(close_timer = nosys);
PROVIDE(timers_off = nosys);
PROVIDE(irq_func_tmr_1mS = nosys);
PROVIDE(usleep = nosys);

/* XXX remove from here. -- Eldar */
PROVIDE(uart_init = nosys);


esp8266/esp8266.ld: Move help.o to iROM.

/* GNU linker script for ESP8266 */

MEMORY
{
    dport0_0_seg : org = 0x3ff00000, len = 0x10
    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000
    iram1_0_seg :  org = 0x40100000, len = 0x8000
    irom0_0_seg :  org = 0x40209000, len = 0x87000
}

/* define the top of RAM */
_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);

PHDRS
{
    dport0_0_phdr PT_LOAD;
    dram0_0_phdr PT_LOAD;
    dram0_0_bss_phdr PT_LOAD;
    iram1_0_phdr PT_LOAD;
    irom0_0_phdr PT_LOAD;
}

ENTRY(firmware_start)
EXTERN(_DebugExceptionVector)
EXTERN(_DoubleExceptionVector)
EXTERN(_KernelExceptionVector)
EXTERN(_NMIExceptionVector)
EXTERN(_UserExceptionVector)

PROVIDE(_memmap_vecbase_reset = 0x40000000);

/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00000110;
_memmap_cacheattr_wt_base = 0x00000110;
_memmap_cacheattr_bp_base = 0x00000220;
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
_memmap_cacheattr_wb_trapnull = 0x2222211F;
_memmap_cacheattr_wba_trapnull = 0x2222211F;
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
_memmap_cacheattr_wt_trapnull = 0x2222211F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
_memmap_cacheattr_wb_allvalid = 0x22222112;
_memmap_cacheattr_wt_allvalid = 0x22222112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);

SECTIONS
{

    .dport0.rodata : ALIGN(4)
    {
        _dport0_rodata_start = ABSOLUTE(.);
        *(.dport0.rodata)
        *(.dport.rodata)
        _dport0_rodata_end = ABSOLUTE(.);
    } >dport0_0_seg :dport0_0_phdr

    .dport0.literal : ALIGN(4)
    {
        _dport0_literal_start = ABSOLUTE(.);
        *(.dport0.literal)
        *(.dport.literal)
        _dport0_literal_end = ABSOLUTE(.);
    } >dport0_0_seg :dport0_0_phdr

    .dport0.data : ALIGN(4)
    {
        _dport0_data_start = ABSOLUTE(.);
        *(.dport0.data)
        *(.dport.data)
        _dport0_data_end = ABSOLUTE(.);
    } >dport0_0_seg :dport0_0_phdr

    .irom0.text : ALIGN(4)
    {
        _irom0_text_start = ABSOLUTE(.);
        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)

        /* we put some specific text in this section */

        *py/argcheck.o*(.literal* .text*)
        *py/asm*.o*(.literal* .text*)
        *py/bc.o*(.literal* .text*)
        *py/binary.o*(.literal* .text*)
        *py/builtin*.o*(.literal* .text*)
        *py/compile.o*(.literal* .text*)
        *py/emit*.o*(.literal* .text*)
        *py/formatfloat.o*(.literal* .text*)
        *py/frozenmod.o*(.literal* .text*)
        *py/gc.o*(.literal* .text*)
        *py/lexer*.o*(.literal* .text*)
        *py/malloc*.o*(.literal* .text*)
        *py/map*.o*(.literal* .text*)
        *py/mod*.o*(.literal* .text*)
        *py/mpprint.o*(.literal* .text*)
        *py/mpstate.o*(.literal* .text*)
        *py/mpz.o*(.literal* .text*)
        *py/native*.o*(.literal* .text*)
        *py/nlr*.o*(.literal* .text*)
        *py/obj*.o*(.literal* .text*)
        *py/opmethods.o*(.literal* .text*)
        *py/parse*.o*(.literal* .text*)
        *py/qstr.o*(.literal* .text*)
        *py/repl.o*(.literal* .text*)
        *py/runtime.o*(.literal* .text*)
        *py/scope.o*(.literal* .text*)
        *py/sequence.o*(.literal* .text*)
        *py/showbc.o*(.literal* .text*)
        *py/smallint.o*(.literal* .text*)
        *py/stackctrl.o*(.literal* .text*)
        *py/stream.o*(.literal* .text*)
        *py/unicode.o*(.literal* .text*)
        *py/vm.o*(.literal* .text*)
        *py/vstr.o*(.literal* .text*)
        *py/warning.o*(.literal* .text*)

        *extmod/*.o*(.literal* .text*)

        *lib/fatfs/*.o*(.literal*, .text*)
        */libaxtls.a:(.literal*, .text*)
        *lib/berkeley-db-1.xx/*.o(.literal*, .text*)
        *lib/libm/*.o*(.literal*, .text*)
        *lib/mp-readline/*.o(.literal*, .text*)
        *lib/netutils/*.o*(.literal*, .text*)
        *lib/timeutils/*.o*(.literal*, .text*)
        *lib/utils/*.o*(.literal*, .text*)

        *stmhal/pybstdio.o(.literal*, .text*)

        *gccollect.o(.literal* .text*)
        *gchelper.o(.literal* .text*)
        *help.o(.literal* .text*)
        *lexerstr32.o(.literal* .text*)
        *utils.o(.literal* .text*)
        *modpyb.o(.literal*, .text*)
        *modpybpin.o(.literal*, .text*)
        *modpybpwm.o(.literal*, .text*)
        *modpybrtc.o(.literal*, .text*)
        *modpybadc.o(.literal*, .text*)
        *modpybuart.o(.literal*, .text*)
        *modpybi2c.o(.literal*, .text*)
        *modmachinewdt.o(.literal*, .text*)
        *modpybspi.o(.literal*, .text*)
        *modpybhspi.o(.literal*, .text*)
        *hspi.o(.literal*, .text*)
        *modesp.o(.literal* .text*)
        *modnetwork.o(.literal* .text*)
        *moduos.o(.literal* .text*)
        *modutime.o(.literal* .text*)
        *modlwip.o(.literal* .text*)
        *modsocket.o(.literal* .text*)
        *modonewire.o(.literal* .text*)

        /* we put as much rodata as possible in this section */
        /* note that only rodata accessed as a machine word is allowed here */
        *py/qstr.o(.rodata.const_pool)
        *.o(.rodata.mp_type_*) /* catches type: mp_obj_type_t */
        *.o(.rodata.*_locals_dict*) /* catches types: mp_obj_dict_t, mp_map_elem_t */
        *.o(.rodata.mp_module_*) /* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t */
        */frozen.o(.rodata.mp_frozen_sizes) /* frozen modules */
        */frozen.o(.rodata.mp_frozen_content) /* frozen modules */

        /* for -mforce-l32 */
        build/*.o(.rodata*)

        _irom0_text_end = ABSOLUTE(.);
    } >irom0_0_seg :irom0_0_phdr

    .text : ALIGN(4)
    {
        _stext = .;
        _text_start = ABSOLUTE(.);
        *(.UserEnter.text)
        . = ALIGN(16);
        *(.DebugExceptionVector.text)
        . = ALIGN(16);
        *(.NMIExceptionVector.text)
        . = ALIGN(16);
        *(.KernelExceptionVector.text)
        LONG(0)
        LONG(0)
        LONG(0)
        LONG(0)
        . = ALIGN(16);
        *(.UserExceptionVector.text)
        LONG(0)
        LONG(0)
        LONG(0)
        LONG(0)
        . = ALIGN(16);
        *(.DoubleExceptionVector.text)
        LONG(0)
        LONG(0)
        LONG(0)
        LONG(0)
        . = ALIGN (16);
        *(.entry.text)
        *(.init.literal)
        *(.init)
        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
        *(.fini.literal)
        *(.fini)
        *(.gnu.version)
        _text_end = ABSOLUTE(.);
        _etext = .;
    } >iram1_0_seg :iram1_0_phdr

    .lit4 : ALIGN(4)
    {
        _lit4_start = ABSOLUTE(.);
        *(*.lit4)
        *(.lit4.*)
        *(.gnu.linkonce.lit4.*)
        _lit4_end = ABSOLUTE(.);
    } >iram1_0_seg :iram1_0_phdr

    .data : ALIGN(4)
    {
        _data_start = ABSOLUTE(.);
        *(.data)
        *(.data.*)
        *(.gnu.linkonce.d.*)
        *(.data1)
        *(.sdata)
        *(.sdata.*)
        *(.gnu.linkonce.s.*)
        *(.sdata2)
        *(.sdata2.*)
        *(.gnu.linkonce.s2.*)
        *(.jcr)
        _data_end = ABSOLUTE(.);
    } >dram0_0_seg :dram0_0_phdr

    .rodata : ALIGN(4)
    {
        _rodata_start = ABSOLUTE(.);
        *(.sdk.version)
        *(.rodata)
        *(.rodata.*)
        *(.gnu.linkonce.r.*)
        *(.rodata1)
        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
        *(.xt_except_table)
        *(.gcc_except_table)
        *(.gnu.linkonce.e.*)
        *(.gnu.version_r)
        *(.eh_frame)
        /*  C++ constructor and destructor tables, properly ordered:  */
        KEEP (*crtbegin.o(.ctors))
        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
        KEEP (*(SORT(.ctors.*)))
        KEEP (*(.ctors))
        KEEP (*crtbegin.o(.dtors))
        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
        KEEP (*(SORT(.dtors.*)))
        KEEP (*(.dtors))
        /*  C++ exception handlers table:  */
        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
        *(.xt_except_desc)
        *(.gnu.linkonce.h.*)
        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
        *(.xt_except_desc_end)
        *(.dynamic)
        *(.gnu.version_d)
        . = ALIGN(4);        /* this table MUST be 4-byte aligned */
        _bss_table_start = ABSOLUTE(.);
        LONG(_bss_start)
        LONG(_bss_end)
        _bss_table_end = ABSOLUTE(.);
        _rodata_end = ABSOLUTE(.);
    } >dram0_0_seg :dram0_0_phdr

    .bss ALIGN(8) (NOLOAD) : ALIGN(4)
    {
        . = ALIGN (8);
        _bss_start = ABSOLUTE(.);
        *(.dynsbss)
        *(.sbss)
        *(.sbss.*)
        *(.gnu.linkonce.sb.*)
        *(.scommon)
        *(.sbss2)
        *(.sbss2.*)
        *(.gnu.linkonce.sb2.*)
        *(.dynbss)
        *(.bss)
        *(.bss.*)
        *(.gnu.linkonce.b.*)
        *(COMMON)
        . = ALIGN (8);
        _bss_end = ABSOLUTE(.);
        _heap_start = ABSOLUTE(.);
    } >dram0_0_seg :dram0_0_bss_phdr
}

/* get ROM code address */
INCLUDE "eagle.rom.addr.v6.ld"

/* GNU linker script for ESP8266 */

MEMORY
{
    dport0_0_seg : org = 0x3ff00000, len = 0x10
    dram0_0_seg :  org = 0x3ffe8000, len = 0x14000
    iram1_0_seg :  org = 0x40100000, len = 0x8000
    irom0_0_seg :  org = 0x40209000, len = 0x87000
}

/* define the top of RAM */
_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);

PHDRS
{
    dport0_0_phdr PT_LOAD;
    dram0_0_phdr PT_LOAD;
    dram0_0_bss_phdr PT_LOAD;
    iram1_0_phdr PT_LOAD;
    irom0_0_phdr PT_LOAD;
}

ENTRY(firmware_start)
EXTERN(_DebugExceptionVector)
EXTERN(_DoubleExceptionVector)
EXTERN(_KernelExceptionVector)
EXTERN(_NMIExceptionVector)
EXTERN(_UserExceptionVector)

PROVIDE(_memmap_vecbase_reset = 0x40000000);

/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00000110;
_memmap_cacheattr_wt_base = 0x00000110;
_memmap_cacheattr_bp_base = 0x00000220;
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
_memmap_cacheattr_wb_trapnull = 0x2222211F;
_memmap_cacheattr_wba_trapnull = 0x2222211F;
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
_memmap_cacheattr_wt_trapnull = 0x2222211F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
_memmap_cacheattr_wb_allvalid = 0x22222112;
_memmap_cacheattr_wt_allvalid = 0x22222112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);

SECTIONS
{

    .dport0.rodata : ALIGN(4)
    {
        _dport0_rodata_start = ABSOLUTE(.);
        *(.dport0.rodata)
        *(.dport.rodata)
        _dport0_rodata_end = ABSOLUTE(.);
    } >dport0_0_seg :dport0_0_phdr

    .dport0.literal : ALIGN(4)
    {
        _dport0_literal_start = ABSOLUTE(.);
        *(.dport0.literal)
        *(.dport.literal)
        _dport0_literal_end = ABSOLUTE(.);
    } >dport0_0_seg :dport0_0_phdr

    .dport0.data : ALIGN(4)
    {
        _dport0_data_start = ABSOLUTE(.);
        *(.dport0.data)
        *(.dport.data)
        _dport0_data_end = ABSOLUTE(.);
    } >dport0_0_seg :dport0_0_phdr

    .irom0.text : ALIGN(4)
    {
        _irom0_text_start = ABSOLUTE(.);
        *(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)

        /* we put some specific text in this section */

        *py/argcheck.o*(.literal* .text*)
        *py/asm*.o*(.literal* .text*)
        *py/bc.o*(.literal* .text*)
        *py/binary.o*(.literal* .text*)
        *py/builtin*.o*(.literal* .text*)
        *py/compile.o*(.literal* .text*)
        *py/emit*.o*(.literal* .text*)
        *py/formatfloat.o*(.literal* .text*)
        *py/frozenmod.o*(.literal* .text*)
        *py/gc.o*(.literal* .text*)
        *py/lexer*.o*(.literal* .text*)
        *py/malloc*.o*(.literal* .text*)
        *py/map*.o*(.literal* .text*)
        *py/mod*.o*(.literal* .text*)
        *py/mpprint.o*(.literal* .text*)
        *py/mpstate.o*(.literal* .text*)
        *py/mpz.o*(.literal* .text*)
        *py/native*.o*(.literal* .text*)
        *py/nlr*.o*(.literal* .text*)
        *py/obj*.o*(.literal* .text*)
        *py/opmethods.o*(.literal* .text*)
        *py/parse*.o*(.literal* .text*)
        *py/qstr.o*(.literal* .text*)
        *py/repl.o*(.literal* .text*)
        *py/runtime.o*(.literal* .text*)
        *py/scope.o*(.literal* .text*)
        *py/sequence.o*(.literal* .text*)
        *py/showbc.o*(.literal* .text*)
        *py/smallint.o*(.literal* .text*)
        *py/stackctrl.o*(.literal* .text*)
        *py/stream.o*(.literal* .text*)
        *py/unicode.o*(.literal* .text*)
        *py/vm.o*(.literal* .text*)
        *py/vstr.o*(.literal* .text*)
        *py/warning.o*(.literal* .text*)

        *extmod/*.o*(.literal* .text*)

        *lib/fatfs/*.o*(.literal*, .text*)
        */libaxtls.a:(.literal*, .text*)
        *lib/berkeley-db-1.xx/*.o(.literal*, .text*)
        *lib/libm/*.o*(.literal*, .text*)
        *lib/mp-readline/*.o(.literal*, .text*)
        *lib/netutils/*.o*(.literal*, .text*)
        *lib/timeutils/*.o*(.literal*, .text*)
        *lib/utils/*.o*(.literal*, .text*)

        *stmhal/pybstdio.o(.literal*, .text*)

        *gccollect.o(.literal* .text*)
        *gchelper.o(.literal* .text*)
        *lexerstr32.o(.literal* .text*)
        *utils.o(.literal* .text*)
        *modpyb.o(.literal*, .text*)
        *modpybpin.o(.literal*, .text*)
        *modpybpwm.o(.literal*, .text*)
        *modpybrtc.o(.literal*, .text*)
        *modpybadc.o(.literal*, .text*)
        *modpybuart.o(.literal*, .text*)
        *modpybi2c.o(.literal*, .text*)
        *modmachinewdt.o(.literal*, .text*)
        *modpybspi.o(.literal*, .text*)
        *modpybhspi.o(.literal*, .text*)
        *hspi.o(.literal*, .text*)
        *modesp.o(.literal* .text*)
        *modnetwork.o(.literal* .text*)
        *moduos.o(.literal* .text*)
        *modutime.o(.literal* .text*)
        *modlwip.o(.literal* .text*)
        *modsocket.o(.literal* .text*)
        *modonewire.o(.literal* .text*)

        /* we put as much rodata as possible in this section */
        /* note that only rodata accessed as a machine word is allowed here */
        *py/qstr.o(.rodata.const_pool)
        *.o(.rodata.mp_type_*) /* catches type: mp_obj_type_t */
        *.o(.rodata.*_locals_dict*) /* catches types: mp_obj_dict_t, mp_map_elem_t */
        *.o(.rodata.mp_module_*) /* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t */
        */frozen.o(.rodata.mp_frozen_sizes) /* frozen modules */
        */frozen.o(.rodata.mp_frozen_content) /* frozen modules */

        /* for -mforce-l32 */
        build/*.o(.rodata*)

        _irom0_text_end = ABSOLUTE(.);
    } >irom0_0_seg :irom0_0_phdr

    .text : ALIGN(4)
    {
        _stext = .;
        _text_start = ABSOLUTE(.);
        *(.UserEnter.text)
        . = ALIGN(16);
        *(.DebugExceptionVector.text)
        . = ALIGN(16);
        *(.NMIExceptionVector.text)
        . = ALIGN(16);
        *(.KernelExceptionVector.text)
        LONG(0)
        LONG(0)
        LONG(0)
        LONG(0)
        . = ALIGN(16);
        *(.UserExceptionVector.text)
        LONG(0)
        LONG(0)
        LONG(0)
        LONG(0)
        . = ALIGN(16);
        *(.DoubleExceptionVector.text)
        LONG(0)
        LONG(0)
        LONG(0)
        LONG(0)
        . = ALIGN (16);
        *(.entry.text)
        *(.init.literal)
        *(.init)
        *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
        *(.fini.literal)
        *(.fini)
        *(.gnu.version)
        _text_end = ABSOLUTE(.);
        _etext = .;
    } >iram1_0_seg :iram1_0_phdr

    .lit4 : ALIGN(4)
    {
        _lit4_start = ABSOLUTE(.);
        *(*.lit4)
        *(.lit4.*)
        *(.gnu.linkonce.lit4.*)
        _lit4_end = ABSOLUTE(.);
    } >iram1_0_seg :iram1_0_phdr

    .data : ALIGN(4)
    {
        _data_start = ABSOLUTE(.);
        *(.data)
        *(.data.*)
        *(.gnu.linkonce.d.*)
        *(.data1)
        *(.sdata)
        *(.sdata.*)
        *(.gnu.linkonce.s.*)
        *(.sdata2)
        *(.sdata2.*)
        *(.gnu.linkonce.s2.*)
        *(.jcr)
        _data_end = ABSOLUTE(.);
    } >dram0_0_seg :dram0_0_phdr

    .rodata : ALIGN(4)
    {
        _rodata_start = ABSOLUTE(.);
        *(.sdk.version)
        *(.rodata)
        *(.rodata.*)
        *(.gnu.linkonce.r.*)
        *(.rodata1)
        __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
        *(.xt_except_table)
        *(.gcc_except_table)
        *(.gnu.linkonce.e.*)
        *(.gnu.version_r)
        *(.eh_frame)
        /*  C++ constructor and destructor tables, properly ordered:  */
        KEEP (*crtbegin.o(.ctors))
        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
        KEEP (*(SORT(.ctors.*)))
        KEEP (*(.ctors))
        KEEP (*crtbegin.o(.dtors))
        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
        KEEP (*(SORT(.dtors.*)))
        KEEP (*(.dtors))
        /*  C++ exception handlers table:  */
        __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
        *(.xt_except_desc)
        *(.gnu.linkonce.h.*)
        __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
        *(.xt_except_desc_end)
        *(.dynamic)
        *(.gnu.version_d)
        . = ALIGN(4);        /* this table MUST be 4-byte aligned */
        _bss_table_start = ABSOLUTE(.);
        LONG(_bss_start)
        LONG(_bss_end)
        _bss_table_end = ABSOLUTE(.);
        _rodata_end = ABSOLUTE(.);
    } >dram0_0_seg :dram0_0_phdr

    .bss ALIGN(8) (NOLOAD) : ALIGN(4)
    {
        . = ALIGN (8);
        _bss_start = ABSOLUTE(.);
        *(.dynsbss)
        *(.sbss)
        *(.sbss.*)
        *(.gnu.linkonce.sb.*)
        *(.scommon)
        *(.sbss2)
        *(.sbss2.*)
        *(.gnu.linkonce.sb2.*)
        *(.dynbss)
        *(.bss)
        *(.bss.*)
        *(.gnu.linkonce.b.*)
        *(COMMON)
        . = ALIGN (8);
        _bss_end = ABSOLUTE(.);
        _heap_start = ABSOLUTE(.);
    } >dram0_0_seg :dram0_0_bss_phdr
}

/* get ROM code address */
INCLUDE "eagle.rom.addr.v6.ld"


[kernel] Fix a rather embarassing typo in link.ld causing .rodata to load in the same place as .data

/* Based on OSDev Bare Bones tutorial
   http://wiki.osdev.org/Bare_Bones */

/* The bootloader will look at this image and start execution at the symbol
   designated as the entry point. */
ENTRY(_bootstrap)

KERNEL_LMA = 0x100000;           /* Physical address */
KERNEL_VMA = 0xffff800000000000; /* Virtual (higher half) address */

/* Tell where the various sections of the object files will be put in the final
   kernel image. */
SECTIONS
{
  /* 32-bit and 64-bit bootstrap routines at 1 MB */
  .                = KERNEL_LMA;
  _bootstrap_begin = .;

  .bootstrap :
  {
    build/kernel/boot32.o (.multiboot)
    build/kernel/boot32.o (.text)
    . = ALIGN(4K);
  }

  .bootstrap64 :
  {
    build/kernel/boot64.o (.text)
    . = ALIGN(4K);
  }

  .bootstrap_data :
  {
    build/kernel/boot32.o (.bootstrap_gdt64)
    build/kernel/boot32.o (.bootstrap_stack)
    build/kernel/boot32.o (.rodata)
    build/kernel/boot32.o (.data)
    . = ALIGN(4K);
  }

  /* 64-bit kernel in the higher half of the 48-bit addressing scheme */
  .             += KERNEL_VMA;
  _kernel_begin  = .;

  /* Kernel executable code. */
  .text : AT(ADDR(.text) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) .text)
    . = ALIGN(4K);
  }

  /* Read-only data. */
  .rodata : AT(ADDR(.rodata) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) .rodata*)
    . = ALIGN(4K);
  }

  /* Read-write data (initialized) */
  .data : AT(ADDR(.data) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) .data)
    . = ALIGN(4K);
  }

  /* Read-write data (uninitialized) */
  .bss : AT(ADDR(.bss) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) COMMON)
    *(EXCLUDE_FILE(build/kernel/boot*.o) .bss)
    . = ALIGN(4K);
  }

  /* The compiler may produce other sections, by default it will put them in
     a segment with the same name. Simply add stuff here as needed. */

  _kernel_end = .;

  /DISCARD/ :
  {
    *(.comment)
    *(.eh_frame)
  }
}

/* Based on OSDev Bare Bones tutorial
   http://wiki.osdev.org/Bare_Bones */

/* The bootloader will look at this image and start execution at the symbol
   designated as the entry point. */
ENTRY(_bootstrap)

KERNEL_LMA = 0x100000;           /* Physical address */
KERNEL_VMA = 0xffff800000000000; /* Virtual (higher half) address */

/* Tell where the various sections of the object files will be put in the final
   kernel image. */
SECTIONS
{
  /* 32-bit and 64-bit bootstrap routines at 1 MB */
  .                = KERNEL_LMA;
  _bootstrap_begin = .;

  .bootstrap :
  {
    build/kernel/boot32.o (.multiboot)
    build/kernel/boot32.o (.text)
    . = ALIGN(4K);
  }

  .bootstrap64 :
  {
    build/kernel/boot64.o (.text)
    . = ALIGN(4K);
  }

  .bootstrap_data :
  {
    build/kernel/boot32.o (.bootstrap_gdt64)
    build/kernel/boot32.o (.bootstrap_stack)
    build/kernel/boot32.o (.rodata)
    build/kernel/boot32.o (.data)
    . = ALIGN(4K);
  }

  /* 64-bit kernel in the higher half of the 48-bit addressing scheme */
  .             += KERNEL_VMA;
  _kernel_begin  = .;

  /* Kernel executable code. */
  .text : AT(ADDR(.text) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) .text)
    . = ALIGN(4K);
  }

  /* Read-only data. */
  .rodata : AT(ADDR(.rodata) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) .rodata*)
    . = ALIGN(4K);
  }

  /* Read-write data (initialized) */
  .data : AT(ADDR(.rodata) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) .data)
    . = ALIGN(4K);
  }

  /* Read-write data (uninitialized) */
  .bss : AT(ADDR(.bss) - KERNEL_VMA)
  {
    *(EXCLUDE_FILE(build/kernel/boot*.o) COMMON)
    *(EXCLUDE_FILE(build/kernel/boot*.o) .bss)
    . = ALIGN(4K);
  }

  /* The compiler may produce other sections, by default it will put them in
     a segment with the same name. Simply add stuff here as needed. */

  _kernel_end = .;

  /DISCARD/ :
  {
    *(.comment)
    *(.eh_frame)
  }
}


esp32s3: Reserve RTC memory in bootloader in the app linker script

/**
 *                    ESP32-S3 Linker Script Memory Layout
 * This file describes the memory layout (memory blocks) by virtual memory addresses.
 * This linker script is passed through the C preprocessor to include configuration options.
 * Please use preprocessor features sparingly!
 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
 */

#include "sdkconfig.h"

#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
#elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
#else
#define ESP_BOOTLOADER_RESERVE_RTC 0
#endif

#define SRAM_IRAM_START     0x40370000
#define SRAM_DRAM_START     0x3FC80000
#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END       0x403BA000 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */

#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
#define SRAM_DRAM_ORG       (SRAM_DRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)

#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG

#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
ASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE
#else
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE

MEMORY
{
  /**
   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
   *  are connected to the data port of the CPU and eg allow byte-wise access.
   */

  /* IRAM for PRO CPU. */
  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
  /* Flash mapped instruction data */
  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20

  /**
   * (0x20 offset above is a convenience for the app binary image generation.
   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
   * header. Setting this offset makes it simple to meet the flash cache MMU's
   * constraint that (paddr % 64KB == vaddr % 64KB).)
   */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

  /**
   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
   */
  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
  /* Flash mapped constant data */
  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20

  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

  /**
   * RTC fast memory (executable). Persists over deep sleep.
   */
  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC

  /**
   * RTC fast memory (same block as above), viewed from data bus
   */
  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000

  /**
   * RTC slow memory (data accessible). Persists over deep sleep.
   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
   */
  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
                                     len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
}

#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
/* static data ends at defined address */
_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;
#else
_static_data_end = _bss_end;
#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE

/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000;

_data_seg_org = ORIGIN(rtc_data_seg);

#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
REGION_ALIAS("rtc_data_location", rtc_slow_seg );
#else
REGION_ALIAS("rtc_data_location", rtc_data_seg );
#endif // CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_code_seg", iram0_2_seg);
#else
REGION_ALIAS("default_code_seg", iram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

/**
 *                    ESP32-S3 Linker Script Memory Layout
 * This file describes the memory layout (memory blocks) by virtual memory addresses.
 * This linker script is passed through the C preprocessor to include configuration options.
 * Please use preprocessor features sparingly!
 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
 */

#include "sdkconfig.h"

#define SRAM_IRAM_START     0x40370000
#define SRAM_DRAM_START     0x3FC80000
#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END       0x403BA000 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */

#define SRAM_IRAM_ORG       (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
#define SRAM_DRAM_ORG       (SRAM_DRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)

#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG

#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
ASSERT((CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
#define DRAM0_0_SEG_LEN CONFIG_ESP32S3_FIXED_STATIC_RAM_SIZE
#else
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE

MEMORY
{
  /**
   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
   *  are connected to the data port of the CPU and eg allow byte-wise access.
   */

  /* IRAM for PRO CPU. */
  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
  /* Flash mapped instruction data */
  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20

  /**
   * (0x20 offset above is a convenience for the app binary image generation.
   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
   * header. Setting this offset makes it simple to meet the flash cache MMU's
   * constraint that (paddr % 64KB == vaddr % 64KB).)
   */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

  /**
   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
   */
  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
  /* Flash mapped constant data */
  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20

  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

  /**
   * RTC fast memory (executable). Persists over deep sleep.
   */
  rtc_iram_seg(RWX) :                org = 0x600fe000, len = 0x2000

  /**
   * RTC fast memory (same block as above), viewed from data bus
   */
  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000

  /**
   * RTC slow memory (data accessible). Persists over deep sleep.
   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
   */
  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
                                     len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
}

#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
/* static data ends at defined address */
_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;
#else
_static_data_end = _bss_end;
#endif // CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE

/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000;

_data_seg_org = ORIGIN(rtc_data_seg);

#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
REGION_ALIAS("rtc_data_location", rtc_slow_seg );
#else
REGION_ALIAS("rtc_data_location", rtc_data_seg );
#endif // CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_code_seg", iram0_2_seg);
#else
REGION_ALIAS("default_code_seg", iram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS


[build] Add PHDRS to kernel linker script

OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
ENTRY(_start)
SEARCH_DIR("=/tmp/x86-i686--glibc--stable/usr/i686-buildroot-linux-gnu/lib32");
SEARCH_DIR("=/tmp/x86-i686--glibc--stable/usr/i686-buildroot-linux-gnu/lib");

kernel_base_va     = 0xC0000000;
kernel_paddr       = 0x00100000;
kernel_text_paddr  = kernel_paddr + 0x1000;

PHDRS
{
  ro_segment PT_LOAD FILEHDR PHDRS;
  rw_segment PT_LOAD;
}

SECTIONS
{
  . = SEGMENT_START("text-segment", kernel_base_va + kernel_text_paddr);

  .text : AT(kernel_text_paddr)
  {
    text = .;
    *(.text.unlikely .text.*_unlikely .text.unlikely.*)
    *(.text.exit .text.exit.*)
    *(.text.startup .text.startup.*)
    *(.text.hot .text.hot.*)
    *(.text .stub .text.* .gnu.linkonce.t.*)
    . = ALIGN(4);
  } : ro_segment

   .rodata : AT(kernel_text_paddr + (rodata - text))
   {
      rodata = .;
      *(.rodata .rodata.* .gnu.linkonce.r.*)
      . = ALIGN(4096);
   } : ro_segment

  .data : AT(kernel_text_paddr + (data - text))
  {
    data = .;
    *(.data .data.* .gnu.linkonce.d.*)
    . = ALIGN(4);
  } : rw_segment

  .bss : AT(kernel_text_paddr + (bss - text))
  {
    bss = .;
    *(.bss .bss.* .gnu.linkonce.b.*)
    . = ALIGN(4);
  } : rw_segment

  . = ALIGN(4);
  _end = .;

  /DISCARD/ : { *(.eh_frame*) }
  /DISCARD/ : { *(.comment) }
}

OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
ENTRY(_start)
SEARCH_DIR("=/tmp/x86-i686--glibc--stable/usr/i686-buildroot-linux-gnu/lib32");
SEARCH_DIR("=/tmp/x86-i686--glibc--stable/usr/i686-buildroot-linux-gnu/lib");

kernel_base_va = 0xC0000000;
kernel_paddr   = 0x00100000;

SECTIONS
{
  . = SEGMENT_START("text-segment", kernel_base_va + kernel_paddr);

  .text : AT(kernel_paddr)
  {
    text = .;
    *(.text.unlikely .text.*_unlikely .text.unlikely.*)
    *(.text.exit .text.exit.*)
    *(.text.startup .text.startup.*)
    *(.text.hot .text.hot.*)
    *(.text .stub .text.* .gnu.linkonce.t.*)
    . = ALIGN(4);
  }

   .rodata : AT(kernel_paddr + (rodata - text))
   {
      rodata = .;
      *(.rodata .rodata.* .gnu.linkonce.r.*)
      . = ALIGN(4096);
   }

  .data : AT(kernel_paddr + (data - text))
  {
    data = .;
    *(.data .data.* .gnu.linkonce.d.*)
    . = ALIGN(4096);
  }

  .bss : AT(kernel_paddr + (bss - text))
  {
    bss = .;
    *(.bss .bss.* .gnu.linkonce.b.*)
  }

  . = ALIGN(4);
  _end = .;

  /DISCARD/ : { *(.eh_frame*) }
  /DISCARD/ : { *(.comment) }
}


[test, sw/silicon_creator] Emit .rodata even if it's empty

extract_sw_logs_db requires .rodata to exist. Since we build for sim_dv
unconditionally and pass .rodata as an argument to that script, build
fails if a flash binary does not have the .rodata section. This commit
adds a workaround for this issue so that .rodata is emitted even if it's
empty. See #14636.

Signed-off-by: Alphan Ulusoy <23b245cc5a07aacf75a9db847b24c67dee1707bf@google.com>

/* Copyright lowRISC contributors. */
/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
/* SPDX-License-Identifier: Apache-2.0 */

/**
 * NOTE:
 * This is an incomplete common portion of ROM_EXT linker file, and should not
 * be used directly. Instead it should be included by a top level ROM_EXT slot
 * linker file.
 */

OUTPUT_ARCH(riscv)

/**
 * Indicate that there are no dynamic libraries, whatsoever.
 */
__DYNAMIC = 0;

/* Reserving space at the top of the RAM for the stack. */
_stack_size = 0x2000;
_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);
_stack_start = _stack_end - _stack_size;

/**
 * Symbols to be used in the setup of the address translation for ROM_EXT.
 */
_owner_virtual_start_address = ORIGIN(owner_virtual);
_owner_virtual_size = LENGTH(owner_virtual);

/**
 * Marking the entry point correctly for the ELF file. The signer tool will
 * transfer this value to the `entry_point` field of the manifest, which will
 * then be used by `rom_boot` to handover execution to ROM_EXT.
 */
ENTRY(_rom_ext_start_boot)

/* DV Log offset (has to be different to other boot stages). */
_dv_log_offset = 0x10000;

/*
 * The start of the .text section relative to the beginning of the associated
 * slot for use in the manifest.
 */
_manifest_code_start = _text_start - _rom_ext_start_address;
/*
 * The end of the .text section relative to the beginning of the associated slot
 * for use in the manifest.
 */
_manifest_code_end = _text_end - _rom_ext_start_address;
/*
 * The location of the entry point relative to the beginning of the associated
 * slot for use in the manifest.
 */
_manifest_entry_point = _rom_ext_start_boot - _rom_ext_start_address;

/**
 * NOTE: We have to align each section to word boundaries as our current
 * s19->slm conversion scripts are not able to handle non-word aligned sections.
 */
SECTIONS {
  .manifest _rom_ext_start_address : {
    KEEP(*(.manifest))
    . = ALIGN(256);
  } > rom_ext_flash

  /**
   * Ibex interrupt vector.
   *
   * This has to be set up at a 256-byte offset, so that we can use it with
   * Ibex.
   */
  .vectors : ALIGN(256) {
    _text_start = .;
    KEEP(*(.vectors))
  } > rom_ext_flash

  /**
   * C runtime (CRT) section, containing program initialization code.
   */
  .crt : ALIGN(4) {
    KEEP(*(.crt))
  } > rom_ext_flash

  /**
   * Standard text section, containing program code.
   */
  .text : ALIGN(4) {
    *(.text)
    *(.text.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
  } > rom_ext_flash

  /**
   * Shutdown text section, containing shutdown function(s).
   *
   * This must be the last executable section in the ROM_EXT flash image.
   */
  .shutdown : ALIGN(4) {
    *(.shutdown)
    *(.shutdown.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
    _text_end = .;
  } > rom_ext_flash

  /**
   * Read-only data section, containing all large compile-time constants, like
   * strings.
   */
  .rodata : ALIGN(4) {
    /* Small read-only data comes before regular read-only data for the same
     * reasons as in the data section */
    *(.srodata)
    *(.srodata.*)
    *(.rodata)
    *(.rodata.*)
    /* TODO(#14636): extract_sw_logs_db requires .rodata section. */
    . = ALIGN(4);
    _rodata_end = .;
  } > rom_ext_flash

  /**
   * Critical static data that is accessible by both the ROM and the ROM
   * extension.
   */
  INCLUDE sw/device/silicon_creator/lib/base/static_critical.ld

  /**
   * Mutable data section, at the bottom of ram_main. This will be initialized
   * from flash at runtime by the CRT.
   *
   * Load this by copying the bytes from [_data_init_start, _data_init_end] into
   * the range [_data_start, _data_end].
   */
  .data : ALIGN(4) {
    _data_start = .;
    _data_init_start = LOADADDR(.data);

    /* This will get loaded into `gp`, and the linker will use that register for
     * accessing data within [-2048,2047] of `__global_pointer$`.
     *
     * This is much cheaper (for small data) than materializing the
     * address and loading from that (which will take one extra instruction).
     */
    __global_pointer$ = . + 2048;

    /* Small data should come before larger data. This helps to ensure small
     * globals are within 2048 bytes of the value of `gp`, making their accesses
     * hopefully only take one instruction. */
    *(.sdata)
    *(.sdata.*)

    /* Other data will likely need multiple instructions to load, so we're less
     * concerned about address materialisation taking more than one instruction.
     */
    *(.data)
    *(.data.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
    _data_end = .;
    _data_init_end = LOADADDR(.data) + SIZEOF(.data);

    /* This puts it in ram_main at runtime (for the VMA), but puts the section
     * into flash for load time (for the LMA). This is why `_data_init_*` uses
     * `LOADADDR`.
     *
     * Using `AT>` means we don't have to keep track of the next free part of
     * flash, as we do in our other linker scripts. */
  } > ram_main AT> rom_ext_flash

  /**
   * Standard BSS section. This will be zeroed at runtime by the CRT.
   */
  .bss : ALIGN(4) {
    _bss_start = .;

    /* Small BSS comes before regular BSS for the same reasons as in the data
     * section */
    *(.sbss)
    *(.sbss.*)
    *(.bss)
    *(.bss.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
    _bss_end = .;
  } > ram_main

  INCLUDE sw/device/info_sections.ld
}

/* Copyright lowRISC contributors. */
/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
/* SPDX-License-Identifier: Apache-2.0 */

/**
 * NOTE:
 * This is an incomplete common portion of ROM_EXT linker file, and should not
 * be used directly. Instead it should be included by a top level ROM_EXT slot
 * linker file.
 */

OUTPUT_ARCH(riscv)

/**
 * Indicate that there are no dynamic libraries, whatsoever.
 */
__DYNAMIC = 0;

/* Reserving space at the top of the RAM for the stack. */
_stack_size = 0x2000;
_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);
_stack_start = _stack_end - _stack_size;

/**
 * Symbols to be used in the setup of the address translation for ROM_EXT.
 */
_owner_virtual_start_address = ORIGIN(owner_virtual);
_owner_virtual_size = LENGTH(owner_virtual);

/**
 * Marking the entry point correctly for the ELF file. The signer tool will
 * transfer this value to the `entry_point` field of the manifest, which will
 * then be used by `rom_boot` to handover execution to ROM_EXT.
 */
ENTRY(_rom_ext_start_boot)

/* DV Log offset (has to be different to other boot stages). */
_dv_log_offset = 0x10000;

/*
 * The start of the .text section relative to the beginning of the associated
 * slot for use in the manifest.
 */
_manifest_code_start = _text_start - _rom_ext_start_address;
/*
 * The end of the .text section relative to the beginning of the associated slot
 * for use in the manifest.
 */
_manifest_code_end = _text_end - _rom_ext_start_address;
/*
 * The location of the entry point relative to the beginning of the associated
 * slot for use in the manifest.
 */
_manifest_entry_point = _rom_ext_start_boot - _rom_ext_start_address;

/**
 * NOTE: We have to align each section to word boundaries as our current
 * s19->slm conversion scripts are not able to handle non-word aligned sections.
 */
SECTIONS {
  .manifest _rom_ext_start_address : {
    KEEP(*(.manifest))
    . = ALIGN(256);
  } > rom_ext_flash

  /**
   * Ibex interrupt vector.
   *
   * This has to be set up at a 256-byte offset, so that we can use it with
   * Ibex.
   */
  .vectors : ALIGN(256) {
    _text_start = .;
    KEEP(*(.vectors))
  } > rom_ext_flash

  /**
   * C runtime (CRT) section, containing program initialization code.
   */
  .crt : ALIGN(4) {
    KEEP(*(.crt))
  } > rom_ext_flash

  /**
   * Standard text section, containing program code.
   */
  .text : ALIGN(4) {
    *(.text)
    *(.text.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
  } > rom_ext_flash

  /**
   * Shutdown text section, containing shutdown function(s).
   *
   * This must be the last executable section in the ROM_EXT flash image.
   */
  .shutdown : ALIGN(4) {
    *(.shutdown)
    *(.shutdown.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
    _text_end = .;
  } > rom_ext_flash

  /**
   * Read-only data section, containing all large compile-time constants, like
   * strings.
   */
  .rodata : ALIGN(4) {
    /* Small read-only data comes before regular read-only data for the same
     * reasons as in the data section */
    *(.srodata)
    *(.srodata.*)
    *(.rodata)
    *(.rodata.*)
  } > rom_ext_flash

  /**
   * Critical static data that is accessible by both the ROM and the ROM
   * extension.
   */
  INCLUDE sw/device/silicon_creator/lib/base/static_critical.ld

  /**
   * Mutable data section, at the bottom of ram_main. This will be initialized
   * from flash at runtime by the CRT.
   *
   * Load this by copying the bytes from [_data_init_start, _data_init_end] into
   * the range [_data_start, _data_end].
   */
  .data : ALIGN(4) {
    _data_start = .;
    _data_init_start = LOADADDR(.data);

    /* This will get loaded into `gp`, and the linker will use that register for
     * accessing data within [-2048,2047] of `__global_pointer$`.
     *
     * This is much cheaper (for small data) than materializing the
     * address and loading from that (which will take one extra instruction).
     */
    __global_pointer$ = . + 2048;

    /* Small data should come before larger data. This helps to ensure small
     * globals are within 2048 bytes of the value of `gp`, making their accesses
     * hopefully only take one instruction. */
    *(.sdata)
    *(.sdata.*)

    /* Other data will likely need multiple instructions to load, so we're less
     * concerned about address materialisation taking more than one instruction.
     */
    *(.data)
    *(.data.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
    _data_end = .;
    _data_init_end = LOADADDR(.data) + SIZEOF(.data);

    /* This puts it in ram_main at runtime (for the VMA), but puts the section
     * into flash for load time (for the LMA). This is why `_data_init_*` uses
     * `LOADADDR`.
     *
     * Using `AT>` means we don't have to keep track of the next free part of
     * flash, as we do in our other linker scripts. */
  } > ram_main AT> rom_ext_flash

  /**
   * Standard BSS section. This will be zeroed at runtime by the CRT.
   */
  .bss : ALIGN(4) {
    _bss_start = .;

    /* Small BSS comes before regular BSS for the same reasons as in the data
     * section */
    *(.sbss)
    *(.sbss.*)
    *(.bss)
    *(.bss.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
    _bss_end = .;
  } > ram_main

  INCLUDE sw/device/info_sections.ld
}


Use full flash in S110 linker script

Use full flash in S110 linker script

/* Linker script to configure memory regions. */
MEMORY
{
  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x2C000 /* 80 kB is taken by S110, 176 kB for app. */
  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 /* 8 kB is taken by S110,8 kB for app. */
}
INCLUDE "gcc_nrf51_common.ld"

/* Linker script to configure memory regions. */
MEMORY
{
  FLASH (rx) : ORIGIN = 0x14000, LENGTH = 0x26000 /* 80 kB is taken by S110, 176 kB for app. */
  RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 /* 8 kB is taken by S110,8 kB for app. */
}
INCLUDE "gcc_nrf51_common.ld"


Added comments back to linker script and changedgp location

/* ========================================================================
 *
 * n64ld.x
 *
 * GNU Linker script for building an image that is set up for the N64
 * but still has the data factored into sections.  It is not directly
 * runnable, and it contains the debug info if available.  It will need
 * a 'loader' to perform the final stage of transformation to produce
 * a raw image.
 *
 * Copyright (c) 1999 Ground Zero Development, All rights reserved.
 * Developed by Frank Somers <frank@g0dev.com>
 * Modifications by hcs (halleyscometsoftware@hotmail.com)
 *
 * $Header: /afs/icequake.net/users/nemesis/n64/sf/asdf/n64dev/lib/alt-libn64/n64ld.x,v 1.2 2006-08-11 15:54:11 halleyscometsw Exp $
 *
 * ========================================================================
 */

OUTPUT_FORMAT ("elf32-bigmips", "elf32-bigmips", "elf32-littlemips")
OUTPUT_ARCH (mips)
EXTERN (_start)
ENTRY (_start)

MEMORY
{
    mem : ORIGIN = 0x80000400, LENGTH = 4M-0x0400
}

SECTIONS {
   /* Start address of code is 1K up in uncached, unmapped RAM.  We have
    * to be at least this far up in order to not interfere with the cart
    * boot code which is copying it down from the cart
    */
    . = 0x80000400;

    /* The text section carries the app code and its relocation addr is
    * the first byte of the cart domain in cached, unmapped memory
    */
    .text : {
        *(.boot)
        . = ALIGN(16);
        __text_start = .;
        *(.text)
        *(.text.*)
        *(.init)
        *(.fini)
        *(.gnu.linkonce.t.*)
        __text_end  = .;
    } > mem

   .eh_frame_hdr : { *(.eh_frame_hdr) } > mem
   .eh_frame : { KEEP (*(.eh_frame)) } > mem
   .gcc_except_table : { *(.gcc_except_table*) } > mem
   .jcr : { KEEP (*(.jcr)) } > mem

    .rodata : {
        *(.rdata)
        *(.rodata)
        *(.rodata.*)
        *(.gnu.linkonce.r.*)
    } > mem

    . = ALIGN(8);

    .ctors : {
        __CTOR_LIST_SIZE__ = .;
        LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 1)
        __CTOR_LIST__ = .;
        *(.ctors)
        LONG(0)
        __CTOR_END__ = .;
    } > mem

    . = ALIGN(8);

    .dtors : {
        __DTOR_LIST__ = .;
        LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
        *(.dtors)
        LONG(0)
        __DTOR_END__ = .;
    } > mem

    . = ALIGN(8);

    /* Data section has relocation address at start of RAM in cached,
    * unmapped memory, but is loaded just at the end of the text segment,
    * and must be copied to the correct location at startup
    * Gather all initialised data together.  The memory layout
    * will place the global initialised data at the lowest addrs.
    * The lit8, lit4, sdata and sbss sections have to be placed
    * together in that order from low to high addrs with the _gp symbol
    * positioned (aligned) at the start of the sdata section.
    * We then finish off with the standard bss section
    */
    .data : {
        __data_start = .;
        *(.data)
        *(.data.*)
        *(.gnu.linkonce.d.*)
    } > mem

    .lit8 : {
        *(.lit8)
    } > mem
    .lit4 : {
        *(.lit4)
    } > mem

    . = ALIGN(8);
    .sdata : {
        _gp = .;
        *(.sdata)
        *(.sdata.*)
        *(.gnu.linkonce.s.*)
    } > mem

    __data_end = .;

    . = ALIGN(8);
    .sbss (NOLOAD) : {
         __bss_start = .;
        *(.sbss)
        *(.sbss.*)
        *(.gnu.linkonce.sb.*)
        *(.scommon)
        *(.scommon.*)
    } > mem

    . = ALIGN(8);
    .bss (NOLOAD) : {
        *(.bss)
        *(.bss*)
        *(.gnu.linkonce.b.*)
        *(COMMON)
        __bss_end = .;
    } > mem

    . = ALIGN(8);
    end = .;
}

/* ========================================================================
 *
 * n64ld.x
 *
 * GNU Linker script for building an image that is set up for the N64
 * but still has the data factored into sections.  It is not directly
 * runnable, and it contains the debug info if available.  It will need
 * a 'loader' to perform the final stage of transformation to produce
 * a raw image.
 *
 * Copyright (c) 1999 Ground Zero Development, All rights reserved.
 * Developed by Frank Somers <frank@g0dev.com>
 * Modifications by hcs (halleyscometsoftware@hotmail.com)
 *
 * $Header: /afs/icequake.net/users/nemesis/n64/sf/asdf/n64dev/lib/alt-libn64/n64ld.x,v 1.2 2006-08-11 15:54:11 halleyscometsw Exp $
 *
 * ========================================================================
 */

OUTPUT_FORMAT ("elf32-bigmips", "elf32-bigmips", "elf32-littlemips")
OUTPUT_ARCH (mips)
EXTERN (_start)
ENTRY (_start)

MEMORY
{
    mem : ORIGIN = 0x80000400, LENGTH = 4M-0x0400
}

SECTIONS {
    . = 0x80000400;

    .text : {
        *(.boot)
        . = ALIGN(16);
        __text_start = .;
        *(.text)
        *(.text.*)
        *(.init)
        *(.fini)
        *(.gnu.linkonce.t.*)
        __text_end  = .;
    } > mem

   .eh_frame_hdr : { *(.eh_frame_hdr) } > mem
   .eh_frame : { KEEP (*(.eh_frame)) } > mem
   .gcc_except_table : { *(.gcc_except_table*) } > mem
   .jcr : { KEEP (*(.jcr)) } > mem

    .rodata : {
        *(.rdata)
        *(.rodata)
        *(.rodata.*)
        *(.gnu.linkonce.r.*)
    } > mem

    . = ALIGN(8);

    .ctors : {
        __CTOR_LIST_SIZE__ = .;
        LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 1)
        __CTOR_LIST__ = .;
        *(.ctors)
        LONG(0)
        __CTOR_END__ = .;
    } > mem

    . = ALIGN(8);

    .dtors : {
        __DTOR_LIST__ = .;
        LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
        *(.dtors)
        LONG(0)
        __DTOR_END__ = .;
    } > mem

    . = ALIGN(8);

    .data : {
        __data_start = .;
        *(.data)
        *(.data.*)
        *(.gnu.linkonce.d.*)
    } > mem

    .lit8 : {
        *(.lit8)
    } > mem
    .lit4 : {
        *(.lit4)
    } > mem

    . = ALIGN(8);
    .sdata : {
        /* Ideally, this should be _gp = . + 0x8000 - GCC is complaining about small data not being smaller than 64k - Any ideas? */
        _gp = . + 0x7000;
        *(.sdata)
        *(.sdata.*)
        *(.gnu.linkonce.s.*)
    } > mem

    __data_end = .;

    . = ALIGN(8);
    .sbss (NOLOAD) : {
         __bss_start = .;
        *(.sbss)
        *(.sbss.*)
        *(.gnu.linkonce.sb.*)
        *(.scommon)
        *(.scommon.*)
    } > mem

    . = ALIGN(8);
    .bss (NOLOAD) : {
        *(.bss)
        *(.bss*)
        *(.gnu.linkonce.b.*)
        *(COMMON)
        __bss_end = .;
    } > mem

    . = ALIGN(8);
    end = .;
}


[sound driver linker script] fix NMI routine length

/* vlink linker script for freemlib sound driver */

MEMORY
{
	start:   ORIGIN = 0x0000, LENGTH = 0x0004 /* 0x0000: entry point */
	delay1:  ORIGIN = 0x0008, LENGTH = 0x0003 /* 0x0008: port write delay (addr) */
	delay2:  ORIGIN = 0x0010, LENGTH = 0x0003 /* 0x0010: port write delay (data) */
	write45: ORIGIN = 0x0018, LENGTH = 0x0003 /* 0x0018: shortcut to write_45 */
	write67: ORIGIN = 0x0020, LENGTH = 0x0003 /* 0x0020: shortcut to write_67 */
	ymwait:  ORIGIN = 0x0028, LENGTH = 0x0006 /* 0x0028: YM2610 busy wait */
	IRQ:     ORIGIN = 0x0038, LENGTH = 0x0004 /* 0x0038: IRQ trampoline */
	idstr:   ORIGIN = 0x0040, LENGTH = 0x0020 /* 0x0040: driver identification */
	NMI:     ORIGIN = 0x0066, LENGTH = 0x003A /* 0x0066: NMI routine */
	rom:     ORIGIN = 0x00A0, LENGTH = 0xF760 /* 0x00A0: start of the rest of ROM */
	ram:     ORIGIN = 0xF800, LENGTH = 0x0800 /* RAM at 0xF800-0xFFFF */
}

SECTIONS
{
	.start : { *(start) } > start
	.delay1 : { *(delay1) } > delay1
	.delay2 : { *(delay2) } > delay2
	.write45 : { *(write45) } > write45
	.write67 : { *(write67) } > write67
	.ymwait : { *(ymwait) } > ymwait
	.IRQ : { *(IRQ) } > IRQ
	.idstr : { *(idstr) } > idstr
	.NMI : { *(NMI) } > NMI
	.code : { *(code) } > rom
	.bss (NOLOAD) : { *(bss) } > ram
}

/* vlink linker script for freemlib sound driver */

MEMORY
{
	start:   ORIGIN = 0x0000, LENGTH = 0x0004 /* 0x0000: entry point */
	delay1:  ORIGIN = 0x0008, LENGTH = 0x0003 /* 0x0008: port write delay (addr) */
	delay2:  ORIGIN = 0x0010, LENGTH = 0x0003 /* 0x0010: port write delay (data) */
	write45: ORIGIN = 0x0018, LENGTH = 0x0003 /* 0x0018: shortcut to write_45 */
	write67: ORIGIN = 0x0020, LENGTH = 0x0003 /* 0x0020: shortcut to write_67 */
	ymwait:  ORIGIN = 0x0028, LENGTH = 0x0006 /* 0x0028: YM2610 busy wait */
	IRQ:     ORIGIN = 0x0038, LENGTH = 0x0004 /* 0x0038: IRQ trampoline */
	idstr:   ORIGIN = 0x0040, LENGTH = 0x0020 /* 0x0040: driver identification */
	NMI:     ORIGIN = 0x0066, LENGTH = 0x004A /* 0x0066: NMI routine */
	rom:     ORIGIN = 0x00A0, LENGTH = 0xF760 /* 0x00A0: start of the rest of ROM */
	ram:     ORIGIN = 0xF800, LENGTH = 0x0800 /* RAM at 0xF800-0xFFFF */
}

SECTIONS
{
	.start : { *(start) } > start
	.delay1 : { *(delay1) } > delay1
	.delay2 : { *(delay2) } > delay2
	.write45 : { *(write45) } > write45
	.write67 : { *(write67) } > write67
	.ymwait : { *(ymwait) } > ymwait
	.IRQ : { *(IRQ) } > IRQ
	.idstr : { *(idstr) } > idstr
	.NMI : { *(NMI) } > NMI
	.code : { *(code) } > rom
	.bss (NOLOAD) : { *(bss) } > ram
}


[IA64] check-segrel.lds vs --build-id

[IA64] check-segrel.lds vs --build-id

Some versions of ld with --build-id support will crash when using the flag
with a linker script that discards notes.  This bites ia64's check-segrel.lds.
The bug is easy to avoid.

Signed-off-by: Roland McGrath <0d270388f2f92757a5de0f4bd891d3b392c44c4f@redhat.com>
Signed-off-by: Tony Luck <e7984595ec0368ff920a7b3521dc7093683f6f26@intel.com>

SECTIONS {
	. = SIZEOF_HEADERS;
	.rodata : { *(.rodata) } :ro
	.note : { *(.note*) }
	. = 0xa0000;
	.data : { *(.data) } :dat
	/DISCARD/ : { *(*) }
}
PHDRS {
  ro PT_LOAD FILEHDR PHDRS;
  dat PT_LOAD;
}

SECTIONS {
	. = SIZEOF_HEADERS;
	.rodata : { *(.rodata) } :ro
	. = 0xa0000;
	.data : { *(.data) } :dat
	/DISCARD/ : { *(*) }
}
PHDRS {
  ro PT_LOAD FILEHDR PHDRS;
  dat PT_LOAD;
}