fix identation [skip ci]

fix identation [skip ci]

YAPB_ABI_1.0 {
   global:
      Meta_*;
      GiveFnptrsToDll;
      GetBotAPI;
      GetEntityAPI;
   local:
      *;
};


fix boot stack size

fix boot stack size

ENTRY(nautilus_entry)

VIRT_BASE = 0Xffffffff80000000;

SECTIONS
{
    . = 0x100000;

    .boot :
    {
        *(.mbhdr)
        _loadStart = .;
        *(.boot)
        . = ALIGN(4096);
        pml4 = .;
        . += 0x1000;
        pdpt = .;
        . += 0x1000;
        pd = .;
        . += 0x1000;
        pt = .;
        . += 0x1000;
        boot_stack = .;
        . += 0x8000;
    }

    . += VIRT_BASE;

    .text ALIGN(0x1000) : AT(ADDR(.text) - VIRT_BASE)
    {
        *(.text)
        *(.gnu.linkonce.t*)
    }

    .data ALIGN(0x1000) : AT(ADDR(.data) - VIRT_BASE)
    {
        *(.data)
        *(.gnu.linkonce.d*)
    }

    .rodata ALIGN(0x1000) : AT(ADDR(.rodata) - VIRT_BASE)
    {
        *(.rodata*)
        *(.gnu.linkonce.r*)
    }

    _loadEnd = . - VIRT_BASE;

    .bss ALIGN(0x1000) : AT(ADDR(.bss) - VIRT_BASE)
    {
        *(COMMON)
        *(.bss)
        *(.gnu.linkonce.b*)
    }

    _bssEnd = . - VIRT_BASE;

    /DISCARD/ :
    {
        *(.comment)
        *(.eh_frame)
    }
}

ENTRY(nautilus_entry)

VIRT_BASE = 0Xffffffff80000000;

SECTIONS
{
    . = 0x100000;

    .boot :
    {
        *(.mbhdr)
        _loadStart = .;
        *(.boot)
        . = ALIGN(4096);
        pml4 = .;
        . += 0x1000;
        pdpt = .;
        . += 0x1000;
        pd = .;
        . += 0x1000;
        pt = .;
        . += 0x1000;
        . += 0x8000;
        boot_stack = .;
    }

    . += VIRT_BASE;

    .text ALIGN(0x1000) : AT(ADDR(.text) - VIRT_BASE)
    {
        *(.text)
        *(.gnu.linkonce.t*)
    }

    .data ALIGN(0x1000) : AT(ADDR(.data) - VIRT_BASE)
    {
        *(.data)
        *(.gnu.linkonce.d*)
    }

    .rodata ALIGN(0x1000) : AT(ADDR(.rodata) - VIRT_BASE)
    {
        *(.rodata*)
        *(.gnu.linkonce.r*)
    }

    _loadEnd = . - VIRT_BASE;

    .bss ALIGN(0x1000) : AT(ADDR(.bss) - VIRT_BASE)
    {
        *(COMMON)
        *(.bss)
        *(.gnu.linkonce.b*)
    }

    _bssEnd = . - VIRT_BASE;

    /DISCARD/ :
    {
        *(.comment)
        *(.eh_frame)
    }
}


Correct the .bss end setting.

Correct the .bss end setting.

MEMORY
{
	flash	: ORIGIN = 0x00000000, LENGTH = 500K
	ram	: ORIGIN = 0x40000000, LENGTH = 32K
	usbram   : ORIGIN = 0x7FD00000, LENGTH = 8K
	ethram   : ORIGIN = 0x7FE00000, LENGTH = 16K
}

__stack_end__ = 0x40000000 + 32K - 4;

SECTIONS
{
	. = 0;
	startup : { *(.startup)} >flash

	prog :
	{
		*(.text)
		*(.rodata)
		*(.rodata*)
		*(.glue_7)
		*(.glue_7t)
	} >flash

	__end_of_text__ = .;

	.data :
	{
		__data_beg__ = .;
		__data_beg_src__ = __end_of_text__;
		*(.data)
		__data_end__ = .;
	} >ram AT>flash

	.bss :
	{
		__bss_beg__ = .;
		*(.bss)
	} >ram

	/* Align here to ensure that the .bss section occupies space up to
	_end.  Align after .bss to ensure correct alignment even if the
	.bss section disappears because there are no input sections.  */
	. = ALIGN(32 / 8);
	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;

	.usbram (NOLOAD):
	{
	__usbram_beg__ = .;
	*(.dmaram)
		__usbram_end__ = .;
	} >usbram

	.ethram (NOLOAD):
	{
	__ethram_beg__ = .;
	*(.ethram)
		__ethram_end__ = .;
	} >ethram

}
	. = ALIGN(32 / 8);
	_end = .;

	PROVIDE (end = .);

MEMORY
{
	flash	: ORIGIN = 0x00000000, LENGTH = 500K
	ram	: ORIGIN = 0x40000000, LENGTH = 32K
	usbram   : ORIGIN = 0x7FD00000, LENGTH = 8K
	ethram   : ORIGIN = 0x7FE00000, LENGTH = 16K
}

__stack_end__ = 0x40000000 + 32K - 4;

SECTIONS
{
	. = 0;
	startup : { *(.startup)} >flash

	prog :
	{
		*(.text)
		*(.rodata)
		*(.rodata*)
		*(.glue_7)
		*(.glue_7t)
	} >flash

	__end_of_text__ = .;

	.data :
	{
		__data_beg__ = .;
		__data_beg_src__ = __end_of_text__;
		*(.data)
		__data_end__ = .;
	} >ram AT>flash

	.bss :
	{
		__bss_beg__ = .;
		*(.bss)
	} >ram

	/* Align here to ensure that the .bss section occupies space up to
	_end.  Align after .bss to ensure correct alignment even if the
	.bss section disappears because there are no input sections.  */
	. = ALIGN(32 / 8);

	.usbram (NOLOAD):
	{
	__usbram_beg__ = .;
	*(.dmaram)
		__usbram_end__ = .;
	} >usbram

	.ethram (NOLOAD):
	{
	__ethram_beg__ = .;
	*(.ethram)
		__ethram_end__ = .;
	} >ethram

}
	. = ALIGN(32 / 8);
	_end = .;
	_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
	PROVIDE (end = .);


add comments to z80/sound driver linker script

/* vlink linker script for freemlib sound driver */

MEMORY
{
	start:   ORIGIN = 0x0000, LENGTH = 0x0004 /* 0x0000: entry point */
	delay1:  ORIGIN = 0x0008, LENGTH = 0x0003 /* 0x0008: port write delay (addr) */
	delay2:  ORIGIN = 0x0010, LENGTH = 0x0003 /* 0x0010: port write delay (data) */
	write45: ORIGIN = 0x0018, LENGTH = 0x0003 /* 0x0018: shortcut to write_45 */
	write67: ORIGIN = 0x0020, LENGTH = 0x0003 /* 0x0020: shortcut to write_67 */
	ymwait:  ORIGIN = 0x0028, LENGTH = 0x0006 /* 0x0028: YM2610 busy wait */
	IRQ:     ORIGIN = 0x0038, LENGTH = 0x0004 /* 0x0038: IRQ trampoline */
	idstr:   ORIGIN = 0x0040, LENGTH = 0x0020 /* 0x0040: driver identification */
	NMI:     ORIGIN = 0x0066, LENGTH = 0x002B /* 0x0066: NMI routine */
	rom:     ORIGIN = 0x00A0, LENGTH = 0xF760 /* 0x00A0: start of the rest of ROM */
	ram:     ORIGIN = 0xF800, LENGTH = 0x0800 /* RAM at 0xF800-0xFFFF */
}

SECTIONS
{
	.start : { *(start) } > start
	.delay1 : { *(delay1) } > delay1
	.delay2 : { *(delay2) } > delay2
	.write45 : { *(write45) } > write45
	.write67 : { *(write67) } > write67
	.ymwait : { *(ymwait) } > ymwait
	.IRQ : { *(IRQ) } > IRQ
	.idstr : { *(idstr) } > idstr
	.NMI : { *(NMI) } > NMI
	.code : { *(code) } > rom
	.bss (NOLOAD) : { *(bss) } > ram
}

/* vlink linker script for freemlib sound driver */

MEMORY
{
	start:   ORIGIN = 0x0000, LENGTH = 0x0038
	delay1:  ORIGIN = 0x0008, LENGTH = 0x0003
	delay2:  ORIGIN = 0x0010, LENGTH = 0x0003
	write45: ORIGIN = 0x0018, LENGTH = 0x0003
	write67: ORIGIN = 0x0020, LENGTH = 0x0003
	ymwait:  ORIGIN = 0x0028, LENGTH = 0x0006
	IRQ:     ORIGIN = 0x0038, LENGTH = 0x0024
	idstr:   ORIGIN = 0x0040, LENGTH = 0x0020
	NMI:     ORIGIN = 0x0066, LENGTH = 0x002B
	rom:     ORIGIN = 0x00A0, LENGTH = 0xF760
	ram:     ORIGIN = 0xF800, LENGTH = 0x0800
}

SECTIONS
{
	.start : { *(start) } > start
	.delay1 : { *(delay1) } > delay1
	.delay2 : { *(delay2) } > delay2
	.write45 : { *(write45) } > write45
	.write67 : { *(write67) } > write67
	.ymwait : { *(ymwait) } > ymwait
	.IRQ : { *(IRQ) } > IRQ
	.idstr : { *(idstr) } > idstr
	.NMI : { *(NMI) } > NMI
	.code : { *(code) } > rom
	.bss (NOLOAD) : { *(bss) } > ram
}


riscv: linker: align end of ROM area to a "page" boundary for QEMU

QEMU does its dynamic instruction translation in 4096-byte-sized chunks.
Therefore it doesn't vet PMP access for each instruction prefetch but
for the whole "page" at once. If the end of the ROM area lands in the
middle of such a page with a corresponding PMP entry then any instruction
access within that page will fault even if it is located in the PMP
mapped portion.

To work around this QEMU peculiarity, we simply align the end of the ROM
area to a page boundary.

Signed-off-by: Nicolas Pitre <76342682d5afc62854e1102d9578521fe1ed6813@baylibre.com>

/*
 * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Linker command/script file
 *
 * Generic Linker script for the riscv platform
 */

#include <soc.h>
#include <zephyr/devicetree.h>

#include <linker/sections.h>
#include <linker/devicetree_regions.h>

#include <linker/linker-defs.h>
#include <linker/linker-tool.h>

#ifdef CONFIG_XIP
#define ROMABLE_REGION              ROM
#else
#define ROMABLE_REGION              RAM
#endif
#define RAMABLE_REGION              RAM

#define _VECTOR_SECTION_NAME        vector
#define _EXCEPTION_SECTION_NAME     exceptions
#define _RESET_SECTION_NAME         reset

#ifdef CONFIG_XIP
#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)
#ifdef CONFIG_FLASH_LOAD_OFFSET
#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \
				CONFIG_FLASH_LOAD_OFFSET)
#else /* !CONFIG_FLASH_LOAD_OFFSET */
#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
#endif /* CONFIG_FLASH_LOAD_OFFSET */
#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)
/* For jedec,spi-nor we expect the spi controller to memory map the flash
 * and for that mapping to be the second register property of the spi
 * controller.
 */
#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
#endif
#else /* CONFIG_XIP */
#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS
#define ROM_SIZE KB(CONFIG_SRAM_SIZE)
#endif /* CONFIG_XIP */

#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RAM_SIZE KB(CONFIG_SRAM_SIZE)

#ifdef CONFIG_RISCV_PMP
	#define MPU_MIN_SIZE 4
	#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);
	#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
		#define MPU_ALIGN(region_size) \
			. = ALIGN(MPU_MIN_SIZE); \
			. = ALIGN( 1 << LOG2CEIL(region_size))
	#else
		#define MPU_ALIGN(region_size) \
			. = ALIGN(MPU_MIN_SIZE)
	#endif
#else
	#define MPU_MIN_SIZE_ALIGN
	#define MPU_ALIGN(region_size) . = ALIGN(4)
#endif

MEMORY
{
#ifdef CONFIG_XIP
    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
#endif
    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE

    LINKER_DT_REGIONS()

    /* Used by and documented in include/linker/intlist.ld */
    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
}

ENTRY(CONFIG_KERNEL_ENTRY)

SECTIONS
    {

#include <linker/rel-sections.ld>

    /*
     * The .plt and .iplt are here according to
     * 'riscv32-zephyr-elf-ld --verbose', before text section.
     */
    SECTION_PROLOGUE(.plt,,)
	{
		*(.plt)
	}

    SECTION_PROLOGUE(.iplt,,)
	{
		*(.iplt)
	}

    GROUP_START(ROMABLE_REGION)
    __rom_region_start = ROM_BASE;

    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)
    {
		. = ALIGN(4);
		KEEP(*(.vectors.*))
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(rom_start,,)
    {
		. = ALIGN(16);
/* Located in generated directory. This file is populated by calling
 * zephyr_linker_sources(ROM_START ...).
 */
#include <snippets-rom-start.ld>
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
    {
		KEEP(*(.reset.*))
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
    {
		 KEEP(*(".exception.entry.*"))
		 *(".exception.other.*")
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
	{
		. = ALIGN(4);
		KEEP(*(.openocd_debug))
		KEEP(*(".openocd_debug.*"))

		__text_region_start = .;

		*(.text)
		*(".text.*")
		*(.gnu.linkonce.t.*)
#include <linker/kobject-text.ld>
#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION
		. = ALIGN(0x1000);
		_ram_code_start = .;
		KEEP(*(.__ram_code))
		__ram_code_size = . - _ram_code_start;
		ASSERT((__ram_code_size <= 0x1000),
			"__ram_code_size <= 4k bytes");
#endif
	} GROUP_LINK_IN(ROMABLE_REGION)

    __text_region_end = .;

	__rodata_region_start = .;
#include <linker/common-rom.ld>
#include <linker/thread-local-storage.ld>

    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
	{
		 . = ALIGN(4);
		 *(.srodata)
		 *(".srodata.*")
		 *(.rodata)
		 *(".rodata.*")
		 *(.gnu.linkonce.r.*)
		 *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rodata.ld>
#include <linker/kobject-rom.ld>
	. = ALIGN(4);
	} GROUP_LINK_IN(ROMABLE_REGION)

#include <linker/cplusplus-rom.ld>
	__rodata_region_end = .;

	/* For non-XIP system, __rom_region_end symbol should be set to
	 * the end of common ROMABLE_REGIONs (text and rodata) instead of
	 * the linker script end, so it wouldn't mistakenly contain
	 * RAMABLE_REGION in it.
	 */
#ifndef CONFIG_XIP
#ifdef CONFIG_RISCV_PMP
	SECTION_PROLOGUE(rom_mpu_padding,,)
	{
		MPU_ALIGN(__rodata_region_end - __rom_region_start);
#ifdef CONFIG_QEMU_TARGET
		/*
		 * QEMU doesn't vet each instruction fetch individually.
		 * Instead, it grabs a whole page and perform dynamic
		 * transation on it in a batch. It therefore validates
		 * PMP permissions using page-sized and -aligned chunks.
		 */
		. = ALIGN(0x1000);
#endif
	} GROUP_LINK_IN(ROMABLE_REGION)
#endif /* CONFIG_RISCV_PMP */

	__rom_region_end = .;
	__rom_region_size = __rom_region_end - __rom_region_start;
#endif /* CONFIG_XIP */
    GROUP_END(ROMABLE_REGION)

    GROUP_START(RAMABLE_REGION)

	. = RAM_BASE;
	_image_ram_start = .;
/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-ram-sections.ld>

#if defined(CONFIG_USERSPACE)
#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN
#define SMEM_PARTITION_ALIGN MPU_ALIGN

#include <app_smem.ld>

	_app_smem_size = _app_smem_end - _app_smem_start;
	_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
#endif /* CONFIG_USERSPACE */

    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
	{
		MPU_MIN_SIZE_ALIGN
		/*
		 * For performance, BSS section is assumed to be 4 byte aligned and
		 * a multiple of 4 bytes
		 */
		 . = ALIGN(4);
		 __bss_start = .;
		__kernel_ram_start = .;
		 *(.sbss)
		 *(".sbss.*")
		 *(.bss)
		 *(".bss.*")
		 COMMON_SYMBOLS
		 /*
		  * As memory is cleared in words only, it is simpler to ensure the BSS
		  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
		  */
		  __bss_end = ALIGN(4);
	}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

#include <linker/common-noinit.ld>

    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
	{
		 . = ALIGN(4);
		/* _image_ram_start = .; */
		 __data_region_start = .;
		 __data_start = .;

		 *(.data)
		 *(".data.*")

#ifdef CONFIG_RISCV_GP
		/*
		 * RISC-V architecture has 12-bit signed immediate offsets in the
		 * instructions. If we can put the most commonly accessed globals
		 * in a special 4K span of memory addressed by the GP register, then
		 * we can access those values in a single instruction, saving both
		 * codespace and runtime.
		 *
		 * Since these immediate offsets are signed, place gp 0x800 past the
		 * beginning of .sdata so that we can use both positive and negative
		 * offsets.
		 */
		 . = ALIGN(8);
		 PROVIDE (__global_pointer$ = . + 0x800);
#endif

		 *(.sdata .sdata.* .gnu.linkonce.s.*)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rwdata.ld>
		 __data_end = .;

	}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
	__data_size = __data_end - __data_start;
	__data_load_start = LOADADDR(_DATA_SECTION_NAME);

	__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);

#include <linker/common-ram.ld>
#include <linker/kobject-data.ld>
#include <linker/cplusplus-ram.ld>

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-data-sections.ld>

    __data_region_end = .;

    MPU_MIN_SIZE_ALIGN

     _image_ram_end = .;
     _end = .; /* end of image */

	__kernel_ram_end = .;
	__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;

#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
GROUP_START(ITCM)

	SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))
	{
		__itcm_start = .;
		*(.itcm)
		*(".itcm.*")
		__itcm_end = .;
	} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)

	__itcm_size = __itcm_end - __itcm_start;
	__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);

GROUP_END(ITCM)
#endif

#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
GROUP_START(DTCM)

	SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))
	{
		__dtcm_start = .;
		__dtcm_bss_start = .;
		*(.dtcm_bss)
		*(".dtcm_bss.*")
		__dtcm_bss_end = .;
	} GROUP_LINK_IN(DTCM)

	SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))
	{
		__dtcm_noinit_start = .;
		*(.dtcm_noinit)
		*(".dtcm_noinit.*")
		__dtcm_noinit_end = .;
	} GROUP_LINK_IN(DTCM)

	SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))
	{
		__dtcm_data_start = .;
		*(.dtcm_data)
		*(".dtcm_data.*")
		__dtcm_data_end = .;
	} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)

	__dtcm_end = .;

	__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);

GROUP_END(DTCM)
#endif

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-sections.ld>

     GROUP_END(RAMABLE_REGION)

#include <linker/debug-sections.ld>

    /DISCARD/ : { *(.note.GNU-stack) }

    SECTION_PROLOGUE(.riscv.attributes, 0,)
	{
	KEEP(*(.riscv.attributes))
	KEEP(*(.gnu.attributes))
	}

/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid
 * to set __rom_region_end symbol at the end of linker script and
 * doesn't mistakenly contain the RAMABLE_REGION in it.
 */
#ifdef CONFIG_XIP
/* Must be last in romable region */
SECTION_PROLOGUE(.last_section,(NOLOAD),)
{
} GROUP_LINK_IN(ROMABLE_REGION)

/* To provide the image size as a const expression,
 * calculate this value here. */
__rom_region_end = LOADADDR(.last_section);
__rom_region_size = __rom_region_end - __rom_region_start;
#endif

}

/*
 * Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief Linker command/script file
 *
 * Generic Linker script for the riscv platform
 */

#include <soc.h>
#include <zephyr/devicetree.h>

#include <linker/sections.h>
#include <linker/devicetree_regions.h>

#include <linker/linker-defs.h>
#include <linker/linker-tool.h>

#ifdef CONFIG_XIP
#define ROMABLE_REGION              ROM
#else
#define ROMABLE_REGION              RAM
#endif
#define RAMABLE_REGION              RAM

#define _VECTOR_SECTION_NAME        vector
#define _EXCEPTION_SECTION_NAME     exceptions
#define _RESET_SECTION_NAME         reset

#ifdef CONFIG_XIP
#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)
#ifdef CONFIG_FLASH_LOAD_OFFSET
#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \
				CONFIG_FLASH_LOAD_OFFSET)
#else /* !CONFIG_FLASH_LOAD_OFFSET */
#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
#endif /* CONFIG_FLASH_LOAD_OFFSET */
#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)
/* For jedec,spi-nor we expect the spi controller to memory map the flash
 * and for that mapping to be the second register property of the spi
 * controller.
 */
#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
#endif
#else /* CONFIG_XIP */
#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS
#define ROM_SIZE KB(CONFIG_SRAM_SIZE)
#endif /* CONFIG_XIP */

#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RAM_SIZE KB(CONFIG_SRAM_SIZE)

#ifdef CONFIG_RISCV_PMP
	#define MPU_MIN_SIZE 4
	#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);
	#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
		#define MPU_ALIGN(region_size) \
			. = ALIGN(MPU_MIN_SIZE); \
			. = ALIGN( 1 << LOG2CEIL(region_size))
	#else
		#define MPU_ALIGN(region_size) \
			. = ALIGN(MPU_MIN_SIZE)
	#endif
#else
	#define MPU_MIN_SIZE_ALIGN
	#define MPU_ALIGN(region_size) . = ALIGN(4)
#endif

MEMORY
{
#ifdef CONFIG_XIP
    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
#endif
    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE

    LINKER_DT_REGIONS()

    /* Used by and documented in include/linker/intlist.ld */
    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
}

ENTRY(CONFIG_KERNEL_ENTRY)

SECTIONS
    {

#include <linker/rel-sections.ld>

    /*
     * The .plt and .iplt are here according to
     * 'riscv32-zephyr-elf-ld --verbose', before text section.
     */
    SECTION_PROLOGUE(.plt,,)
	{
		*(.plt)
	}

    SECTION_PROLOGUE(.iplt,,)
	{
		*(.iplt)
	}

    GROUP_START(ROMABLE_REGION)
    __rom_region_start = ROM_BASE;

    SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)
    {
		. = ALIGN(4);
		KEEP(*(.vectors.*))
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(rom_start,,)
    {
		. = ALIGN(16);
/* Located in generated directory. This file is populated by calling
 * zephyr_linker_sources(ROM_START ...).
 */
#include <snippets-rom-start.ld>
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
    {
		KEEP(*(.reset.*))
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
    {
		 KEEP(*(".exception.entry.*"))
		 *(".exception.other.*")
    } GROUP_LINK_IN(ROMABLE_REGION)

    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
	{
		. = ALIGN(4);
		KEEP(*(.openocd_debug))
		KEEP(*(".openocd_debug.*"))

		__text_region_start = .;

		*(.text)
		*(".text.*")
		*(.gnu.linkonce.t.*)
#include <linker/kobject-text.ld>
#ifdef CONFIG_SOC_FLASH_RAMCODE_SECTION
		. = ALIGN(0x1000);
		_ram_code_start = .;
		KEEP(*(.__ram_code))
		__ram_code_size = . - _ram_code_start;
		ASSERT((__ram_code_size <= 0x1000),
			"__ram_code_size <= 4k bytes");
#endif
	} GROUP_LINK_IN(ROMABLE_REGION)

    __text_region_end = .;

	__rodata_region_start = .;
#include <linker/common-rom.ld>
#include <linker/thread-local-storage.ld>

    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
	{
		 . = ALIGN(4);
		 *(.srodata)
		 *(".srodata.*")
		 *(.rodata)
		 *(".rodata.*")
		 *(.gnu.linkonce.r.*)
		 *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rodata.ld>
#include <linker/kobject-rom.ld>
	. = ALIGN(4);
	} GROUP_LINK_IN(ROMABLE_REGION)

#include <linker/cplusplus-rom.ld>
	__rodata_region_end = .;

	/* For non-XIP system, __rom_region_end symbol should be set to
	 * the end of common ROMABLE_REGIONs (text and rodata) instead of
	 * the linker script end, so it wouldn't mistakenly contain
	 * RAMABLE_REGION in it.
	 */
#ifndef CONFIG_XIP
#ifdef CONFIG_RISCV_PMP
	SECTION_PROLOGUE(rom_mpu_padding,,)
	{
		MPU_ALIGN(__rodata_region_end - __rom_region_start);
	} GROUP_LINK_IN(ROMABLE_REGION)
#endif /* CONFIG_RISCV_PMP */

	__rom_region_end = .;
	__rom_region_size = __rom_region_end - __rom_region_start;
#endif /* CONFIG_XIP */
    GROUP_END(ROMABLE_REGION)

    GROUP_START(RAMABLE_REGION)

	. = RAM_BASE;
	_image_ram_start = .;
/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-ram-sections.ld>

#if defined(CONFIG_USERSPACE)
#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN
#define SMEM_PARTITION_ALIGN MPU_ALIGN

#include <app_smem.ld>

	_app_smem_size = _app_smem_end - _app_smem_start;
	_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
#endif /* CONFIG_USERSPACE */

    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
	{
		MPU_MIN_SIZE_ALIGN
		/*
		 * For performance, BSS section is assumed to be 4 byte aligned and
		 * a multiple of 4 bytes
		 */
		 . = ALIGN(4);
		 __bss_start = .;
		__kernel_ram_start = .;
		 *(.sbss)
		 *(".sbss.*")
		 *(.bss)
		 *(".bss.*")
		 COMMON_SYMBOLS
		 /*
		  * As memory is cleared in words only, it is simpler to ensure the BSS
		  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
		  */
		  __bss_end = ALIGN(4);
	}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

#include <linker/common-noinit.ld>

    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
	{
		 . = ALIGN(4);
		/* _image_ram_start = .; */
		 __data_region_start = .;
		 __data_start = .;

		 *(.data)
		 *(".data.*")

#ifdef CONFIG_RISCV_GP
		/*
		 * RISC-V architecture has 12-bit signed immediate offsets in the
		 * instructions. If we can put the most commonly accessed globals
		 * in a special 4K span of memory addressed by the GP register, then
		 * we can access those values in a single instruction, saving both
		 * codespace and runtime.
		 *
		 * Since these immediate offsets are signed, place gp 0x800 past the
		 * beginning of .sdata so that we can use both positive and negative
		 * offsets.
		 */
		 . = ALIGN(8);
		 PROVIDE (__global_pointer$ = . + 0x800);
#endif

		 *(.sdata .sdata.* .gnu.linkonce.s.*)

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-rwdata.ld>
		 __data_end = .;

	}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
	__data_size = __data_end - __data_start;
	__data_load_start = LOADADDR(_DATA_SECTION_NAME);

	__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);

#include <linker/common-ram.ld>
#include <linker/kobject-data.ld>
#include <linker/cplusplus-ram.ld>

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-data-sections.ld>

    __data_region_end = .;

    MPU_MIN_SIZE_ALIGN

     _image_ram_end = .;
     _end = .; /* end of image */

	__kernel_ram_end = .;
	__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;

#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
GROUP_START(ITCM)

	SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))
	{
		__itcm_start = .;
		*(.itcm)
		*(".itcm.*")
		__itcm_end = .;
	} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)

	__itcm_size = __itcm_end - __itcm_start;
	__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);

GROUP_END(ITCM)
#endif

#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
GROUP_START(DTCM)

	SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))
	{
		__dtcm_start = .;
		__dtcm_bss_start = .;
		*(.dtcm_bss)
		*(".dtcm_bss.*")
		__dtcm_bss_end = .;
	} GROUP_LINK_IN(DTCM)

	SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))
	{
		__dtcm_noinit_start = .;
		*(.dtcm_noinit)
		*(".dtcm_noinit.*")
		__dtcm_noinit_end = .;
	} GROUP_LINK_IN(DTCM)

	SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))
	{
		__dtcm_data_start = .;
		*(.dtcm_data)
		*(".dtcm_data.*")
		__dtcm_data_end = .;
	} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)

	__dtcm_end = .;

	__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);

GROUP_END(DTCM)
#endif

/* Located in generated directory. This file is populated by the
 * zephyr_linker_sources() Cmake function.
 */
#include <snippets-sections.ld>

     GROUP_END(RAMABLE_REGION)

#include <linker/debug-sections.ld>

    /DISCARD/ : { *(.note.GNU-stack) }

    SECTION_PROLOGUE(.riscv.attributes, 0,)
	{
	KEEP(*(.riscv.attributes))
	KEEP(*(.gnu.attributes))
	}

/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid
 * to set __rom_region_end symbol at the end of linker script and
 * doesn't mistakenly contain the RAMABLE_REGION in it.
 */
#ifdef CONFIG_XIP
/* Must be last in romable region */
SECTION_PROLOGUE(.last_section,(NOLOAD),)
{
} GROUP_LINK_IN(ROMABLE_REGION)

/* To provide the image size as a const expression,
 * calculate this value here. */
__rom_region_end = LOADADDR(.last_section);
__rom_region_size = __rom_region_end - __rom_region_start;
#endif

}


Increased maximum ROM size (up to almost 4GB)

OUTPUT_ARCH(m68k)
SEARCH_DIR(.)
/*GROUP(-lbcc -lc -lgcc)*/
__DYNAMIC  =  0;

/*
 * Setup the memory map of the SEGA Genesis.
 * stack grows down from high memory.
 *
 * The memory map look like this:
 * +--------------------+ <- low memory
 * | .text              |
 * |        _etext      |
 * |        ctor list   | the ctor and dtor lists are for
 * |        dtor list   | C++ support
 * +--------------------+
 * .                    .
 * .                    .
 * .                    .
 * +--------------------+ <- 0xFFFF0000
 * | .data              | initialized data goes here
 * |        _data       |
 * |        _edata      |
 * +--------------------+
 * | .bss               |
 * |        _bstart     | start of bss, cleared by crt0
 * |        _bend       | start of heap, used by sbrk()
 * +--------------------+
 * .                    .
 * .                    .
 * .                    .
 * |        __stack     | top of stack
 * +--------------------+ <- 0x00000000
 */
MEMORY
{
	rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x10000000
	ram : ORIGIN = 0xFFFF0000, LENGTH = 0x00010000
}

/*
 * allocate the stack to be at the top of memory, since the stack
 * grows down
 */

PROVIDE (__stack = 0x00000000);

SECTIONS
{
  .text 0x00000000:
  {
    KEEP(*(.text.keepboot)) *(.text.*) *(.text)
    . = ALIGN(0x4);
     __CTOR_LIST__ = .;
    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
    *(.ctors)
    LONG(0)
    __CTOR_END__ = .;
    __DTOR_LIST__ = .;
    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
    *(.dtors)
     LONG(0)
    __DTOR_END__ = .;

    *(.rodata .rodata.*)
    *(.gcc_except_table .gcc_except_table.*)

    . = ALIGN(0x4);
    __INIT_SECTION__ = . ;
    *(.init)
    SHORT (0x4E75)	/* rts */

    __FINI_SECTION__ = . ;
    *(.fini)
    SHORT (0x4E75)	/* rts */

    _etext = .;
    *(.lit)

    *(.rodata_bin)
    *(.rodata_binf)
  } > rom
  _stext = SIZEOF (.text);

  .data 0xFFFF0000 :
  AT ( ADDR (.text) + SIZEOF (.text) )
  {
    *(.got.plt) *(.got)
    *(.shdata)
    *(.data .data.*)
    _edata = .;
  } > ram
  _sdata = SIZEOF (.data);

  .bss 0xFFFF0000 + SIZEOF (.data) :
  {
    _start = . ;
    *(.shbss)
    *(.bss .bss.*)
    *(COMMON)
    _bend = . ;
  } > ram

  .stab 0 (NOLOAD) :
  {
    *(.stab)
  }

  .stabstr 0 (NOLOAD) :
  {
    *(.stabstr)
  }

  .eh_frame 0 (NOLOAD) :
  {
    *(.eh_frame)
  }
}

OUTPUT_ARCH(m68k)
SEARCH_DIR(.)
/*GROUP(-lbcc -lc -lgcc)*/
__DYNAMIC  =  0;

/*
 * Setup the memory map of the SEGA Genesis.
 * stack grows down from high memory.
 *
 * The memory map look like this:
 * +--------------------+ <- low memory
 * | .text              |
 * |        _etext      |
 * |        ctor list   | the ctor and dtor lists are for
 * |        dtor list   | C++ support
 * +--------------------+
 * .                    .
 * .                    .
 * .                    .
 * +--------------------+ <- 0x00FF0000
 * | .data              | initialized data goes here
 * |        _data       |
 * |        _edata      |
 * +--------------------+
 * | .bss               |
 * |        _bstart     | start of bss, cleared by crt0
 * |        _bend       | start of heap, used by sbrk()
 * +--------------------+
 * .                    .
 * .                    .
 * .                    .
 * |        __stack     | top of stack
 * +--------------------+ <- 0x01000000
 */
MEMORY
{
	rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00C00000
	ram : ORIGIN = 0x00FF0000, LENGTH = 0x00010000
}

/*
 * allocate the stack to be at the top of memory, since the stack
 * grows down
 */

PROVIDE (__stack = 0x01000000);

SECTIONS
{
  .text 0x00000000:
  {
    KEEP(*(.text.keepboot)) *(.text.*) *(.text)
    . = ALIGN(0x4);
     __CTOR_LIST__ = .;
    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
    *(.ctors)
    LONG(0)
    __CTOR_END__ = .;
    __DTOR_LIST__ = .;
    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
    *(.dtors)
     LONG(0)
    __DTOR_END__ = .;

    *(.rodata .rodata.*)
    *(.gcc_except_table .gcc_except_table.*)

    . = ALIGN(0x4);
    __INIT_SECTION__ = . ;
    *(.init)
    SHORT (0x4E75)	/* rts */

    __FINI_SECTION__ = . ;
    *(.fini)
    SHORT (0x4E75)	/* rts */

    _etext = .;
    *(.lit)

    *(.rodata_bin)
    *(.rodata_binf)
  } > rom
  _stext = SIZEOF (.text);

  .data 0xFF0000 :
  AT ( ADDR (.text) + SIZEOF (.text) )
  {
    *(.got.plt) *(.got)
    *(.shdata)
    *(.data .data.*)
    _edata = .;
  } > ram
  _sdata = SIZEOF (.data);

  .bss 0xFF0000 + SIZEOF (.data) :
  {
    _start = . ;
    *(.shbss)
    *(.bss .bss.*)
    *(COMMON)
    _bend = . ;
  } > ram

  .stab 0 (NOLOAD) :
  {
    *(.stab)
  }

  .stabstr 0 (NOLOAD) :
  {
    *(.stabstr)
  }

  .eh_frame 0 (NOLOAD) :
  {
    *(.eh_frame)
  }
}


cpu/esp32: fix for crashes of tests/pkg_spiffs

ESP32 nodes can crash during SPI Flash write operations if required parts of the code are not in the IRAM but in the cached SPI Flash memory, which is disabled during the SPI Flash write operations. Therefore, the code of the SPIFFS package and the VFS module are now stored in the IRAM.

/*  Default entry point:  */
ENTRY(call_start_cpu0);

SECTIONS
{
  /* RTC fast memory holds RTC wake stub code,
     including from any source file named rtc_wake_stub*.c
  */
  .rtc.text :
  {
    . = ALIGN(4);
    *(.rtc.literal .rtc.text)
    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)
  } >rtc_iram_seg

  /* RTC bss, from any source file named rtc_wake_stub*.c */
  .rtc.bss (NOLOAD) :
  {
    /* part that is initialized if not waking up from deep sleep */
    _rtc_bss_start = ABSOLUTE(.);
    *rtc_wake_stub*.o(.bss .bss.*)
    *rtc_wake_stub*.o(COMMON)
    _rtc_bss_end = ABSOLUTE(.);
    /* part that saves some data for rtc periph module, this part is
       only initialized at power on reset */
    _rtc_bss_rtc_start = ABSOLUTE(.);
    *(.rtc.bss .rtc.bss.*)
    _rtc_bss_rtc_end = ABSOLUTE(.);
  } > rtc_slow_seg

  /* RTC slow memory holds RTC wake stub
     data/rodata, including from any source file
     named rtc_wake_stub*.c
  */
  .rtc.data :
  {
    _rtc_data_start = ABSOLUTE(.);
    *(.rtc.data)
    *(.rtc.rodata)
    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
    _rtc_data_end = ABSOLUTE(.);
  } > rtc_slow_seg

  /* Send .iram0 code to iram */
  .iram0.vectors :
  {
    /* Vectors go to IRAM */
    _init_start = ABSOLUTE(.);
    /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
    . = 0x0;
    KEEP(*(.WindowVectors.text));
    . = 0x180;
    KEEP(*(.Level2InterruptVector.text));
    . = 0x1c0;
    KEEP(*(.Level3InterruptVector.text));
    . = 0x200;
    KEEP(*(.Level4InterruptVector.text));
    . = 0x240;
    KEEP(*(.Level5InterruptVector.text));
    . = 0x280;
    KEEP(**(.DebugExceptionVector.text));
    . = 0x2c0;
    KEEP(*(.NMIExceptionVector.text));
    . = 0x300;
    KEEP(*(.KernelExceptionVector.text));
    . = 0x340;
    KEEP(*(.UserExceptionVector.text));
    . = 0x3C0;
    KEEP(*(.DoubleExceptionVector.text));
    . = 0x400;
    *(.*Vector.literal)

    *(.UserEnter.literal);
    *(.UserEnter.text);
    . = ALIGN (16);
    *(.entry.text)
    *(.init.literal)
    *(.init)
    _init_end = ABSOLUTE(.);

    /* This goes here, not at top of linker script, so addr2line finds it last,
       and uses it in preference to the first symbol in IRAM */
    _iram_start = ABSOLUTE(0);
  } > iram0_0_seg

  .iram0.text :
  {
    /* Code marked as running out of IRAM */
    _iram_text_start = ABSOLUTE(.);
    *(.iram1 .iram1.*)

    *libhal.a:(.literal .text .literal.* .text.*)
    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)
    *libgcov.a:(.literal .text .literal.* .text.*)
    /* *libc.a:(.literal .text .literal.* .text.*) */

    /* Xtensa basic functionality written in assembler should be placed in iram */
    *xtensa.a:*(.literal .text .literal.* .text.*)
    /* ESP-IDF parts that have to run in IRAM */
    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)
    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)
    /* parts of RIOT that should to run in IRAM */
    *core.a:*(.literal .text .literal.* .text.*)
    *spiffs_fs.a:*(.literal .text .literal.* .text.*)
    *spiffs.a:*(.literal .text .literal.* .text.*)
    *vfs.a:*(.literal .text .literal.* .text.*)

    /* part of RIOT ports that should run in IRAM */
    *cpu.a:*(.literal .text .literal.* .text.*)
    *periph.a:*(.literal .text .literal.* .text.*)
    *mtd.a:**(.literal .text .literal.* .text.*)

    INCLUDE esp32.spiram.rom-functions-iram.ld
    _iram_text_end = ABSOLUTE(.);
  } > iram0_0_seg

  .dram0.data :
  {
    _data_start = ABSOLUTE(.);
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
    *(.data1)
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    *(.jcr)
    *(.dram1 .dram1.*)
    *libesp32.a:panic.o(.rodata .rodata.*)
    *libphy.a:(.rodata .rodata.*)
    *libsoc.a:rtc_clk.o(.rodata .rodata.*)
    *libapp_trace.a:(.rodata .rodata.*)
    *libgcov.a:(.rodata .rodata.*)
    *libheap.a:multi_heap.o(.rodata .rodata.*)
    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)
    INCLUDE esp32.spiram.rom-functions-dram.ld
    _data_end = ABSOLUTE(.);
    . = ALIGN(4);
  } >dram0_0_seg

  /* Shared RAM */
  .dram0.bss (NOLOAD) :
  {
    . = ALIGN (8);
    _bss_start = ABSOLUTE(.);
    *(.dynsbss)
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    *(.scommon)
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    *(.dynbss)
    *(.bss)
    *(.bss.*)
    *(.share.mem)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN (8);
    _bss_end = ABSOLUTE(.);
    _heap_start = ABSOLUTE(.);
    _sheap = ABSOLUTE(.);
  } >dram0_0_seg

  /* TODO HEAP handling when BT is used
     ETS system memory seems to start at 0x3FFE0000 if BT is not used.
     This is the top of the heap for the app */
    . = 0x3FFE0000;
  _heap_top = ABSOLUTE(.);
  _eheap = ABSOLUTE(.);

  .flash.rodata :
  {
    _rodata_start = ABSOLUTE(.);
    *(.rodata)
    *(.rodata.*)
    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
    *(.gnu.linkonce.r.*)
    *(.rodata1)
    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
    *(.xt_except_table)
    *(.gcc_except_table .gcc_except_table.*)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
    . = (. + 3) & ~ 3;
    __eh_frame = ABSOLUTE(.);
    KEEP(*(.eh_frame))
    . = (. + 7) & ~ 3;
    /*  C++ constructor and destructor tables, properly ordered:  */
    __init_array_start = ABSOLUTE(.);
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    __init_array_end = ABSOLUTE(.);
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    /*  C++ exception handlers table:  */
    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
    *(.xt_except_desc)
    *(.gnu.linkonce.h.*)
    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
    *(.xt_except_desc_end)
    *(.dynamic)
    *(.gnu.version_d)
    _rodata_end = ABSOLUTE(.);
    /* Literals are also RO data. */
    _lit4_start = ABSOLUTE(.);
    *(*.lit4)
    *(.lit4.*)
    *(.gnu.linkonce.lit4.*)
    _lit4_end = ABSOLUTE(.);
    . = ALIGN(4);
    _thread_local_start = ABSOLUTE(.);
    *(.tdata)
    *(.tdata.*)
    *(.tbss)
    *(.tbss.*)
    _thread_local_end = ABSOLUTE(.);
    . = ALIGN(4);
  } >drom0_0_seg

  .flash.text :
  {
    _stext = .;
    _text_start = ABSOLUTE(.);
    /* place everything else in iram0_2_seg (cached ROM) */
    *(.literal .text .literal.* .text.* .stub)
    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
    *(.fini.literal)
    *(.fini)
    *(.gnu.version)
    _text_end = ABSOLUTE(.);
    _etext = .;

    /* Similar to _iram_start, this symbol goes here so it is
       resolved by addr2line in preference to the first symbol in
       the flash.text segment.
    */
    _flash_cache_start = ABSOLUTE(0);
  } >iram0_2_seg
}

/*  Default entry point:  */
ENTRY(call_start_cpu0);

SECTIONS
{
  /* RTC fast memory holds RTC wake stub code,
     including from any source file named rtc_wake_stub*.c
  */
  .rtc.text :
  {
    . = ALIGN(4);
    *(.rtc.literal .rtc.text)
    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)
  } >rtc_iram_seg

  /* RTC bss, from any source file named rtc_wake_stub*.c */
  .rtc.bss (NOLOAD) :
  {
    /* part that is initialized if not waking up from deep sleep */
    _rtc_bss_start = ABSOLUTE(.);
    *rtc_wake_stub*.o(.bss .bss.*)
    *rtc_wake_stub*.o(COMMON)
    _rtc_bss_end = ABSOLUTE(.);
    /* part that saves some data for rtc periph module, this part is
       only initialized at power on reset */
    _rtc_bss_rtc_start = ABSOLUTE(.);
    *(.rtc.bss .rtc.bss.*)
    _rtc_bss_rtc_end = ABSOLUTE(.);
  } > rtc_slow_seg

  /* RTC slow memory holds RTC wake stub
     data/rodata, including from any source file
     named rtc_wake_stub*.c
  */
  .rtc.data :
  {
    _rtc_data_start = ABSOLUTE(.);
    *(.rtc.data)
    *(.rtc.rodata)
    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
    _rtc_data_end = ABSOLUTE(.);
  } > rtc_slow_seg

  /* Send .iram0 code to iram */
  .iram0.vectors :
  {
    /* Vectors go to IRAM */
    _init_start = ABSOLUTE(.);
    /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
    . = 0x0;
    KEEP(*(.WindowVectors.text));
    . = 0x180;
    KEEP(*(.Level2InterruptVector.text));
    . = 0x1c0;
    KEEP(*(.Level3InterruptVector.text));
    . = 0x200;
    KEEP(*(.Level4InterruptVector.text));
    . = 0x240;
    KEEP(*(.Level5InterruptVector.text));
    . = 0x280;
    KEEP(**(.DebugExceptionVector.text));
    . = 0x2c0;
    KEEP(*(.NMIExceptionVector.text));
    . = 0x300;
    KEEP(*(.KernelExceptionVector.text));
    . = 0x340;
    KEEP(*(.UserExceptionVector.text));
    . = 0x3C0;
    KEEP(*(.DoubleExceptionVector.text));
    . = 0x400;
    *(.*Vector.literal)

    *(.UserEnter.literal);
    *(.UserEnter.text);
    . = ALIGN (16);
    *(.entry.text)
    *(.init.literal)
    *(.init)
    _init_end = ABSOLUTE(.);

    /* This goes here, not at top of linker script, so addr2line finds it last,
       and uses it in preference to the first symbol in IRAM */
    _iram_start = ABSOLUTE(0);
  } > iram0_0_seg

  .iram0.text :
  {
    /* Code marked as running out of IRAM */
    _iram_text_start = ABSOLUTE(.);
    *(.iram1 .iram1.*)

    *libhal.a:(.literal .text .literal.* .text.*)
    *libgcc.a:lib2funcs.o(.literal .text .literal.* .text.*)
    *libgcov.a:(.literal .text .literal.* .text.*)
    /* *libc.a:(.literal .text .literal.* .text.*) */

    /* Xtensa basic functionality written in assembler should be placed in iram */
    *xtensa.a:*(.literal .text .literal.* .text.*)
    /* ESP-IDF parts that have to run in IRAM */
    *esp_idf_heap.a:*(.literal .text .literal.* .text.*)
    *esp_idf_spi_flash.a:*(.literal .text .literal.* .text.*)
    /* parts of RIOT that should to run in IRAM */
    *core.a:*(.literal .text .literal.* .text.*)
    /* *spiffs_fs.a:*(.literal .text .literal.* .text.*) */
    /* *spiffs.a:*(.literal .text .literal.* .text.*) */

    /* part of RIOT ports that should run in IRAM */
    *cpu.a:*(.literal .text .literal.* .text.*)
    *periph.a:*(.literal .text .literal.* .text.*)
    *mtd.a:**(.literal .text .literal.* .text.*)

    INCLUDE esp32.spiram.rom-functions-iram.ld
    _iram_text_end = ABSOLUTE(.);
  } > iram0_0_seg

  .dram0.data :
  {
    _data_start = ABSOLUTE(.);
    *(.data)
    *(.data.*)
    *(.gnu.linkonce.d.*)
    *(.data1)
    *(.sdata)
    *(.sdata.*)
    *(.gnu.linkonce.s.*)
    *(.sdata2)
    *(.sdata2.*)
    *(.gnu.linkonce.s2.*)
    *(.jcr)
    *(.dram1 .dram1.*)
    *libesp32.a:panic.o(.rodata .rodata.*)
    *libphy.a:(.rodata .rodata.*)
    *libsoc.a:rtc_clk.o(.rodata .rodata.*)
    *libapp_trace.a:(.rodata .rodata.*)
    *libgcov.a:(.rodata .rodata.*)
    *libheap.a:multi_heap.o(.rodata .rodata.*)
    *libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)
    INCLUDE esp32.spiram.rom-functions-dram.ld
    _data_end = ABSOLUTE(.);
    . = ALIGN(4);
  } >dram0_0_seg

  /* Shared RAM */
  .dram0.bss (NOLOAD) :
  {
    . = ALIGN (8);
    _bss_start = ABSOLUTE(.);
    *(.dynsbss)
    *(.sbss)
    *(.sbss.*)
    *(.gnu.linkonce.sb.*)
    *(.scommon)
    *(.sbss2)
    *(.sbss2.*)
    *(.gnu.linkonce.sb2.*)
    *(.dynbss)
    *(.bss)
    *(.bss.*)
    *(.share.mem)
    *(.gnu.linkonce.b.*)
    *(COMMON)
    . = ALIGN (8);
    _bss_end = ABSOLUTE(.);
    _heap_start = ABSOLUTE(.);
    _sheap = ABSOLUTE(.);
  } >dram0_0_seg

  /* TODO HEAP handling when BT is used
     ETS system memory seems to start at 0x3FFE0000 if BT is not used.
     This is the top of the heap for the app */
    . = 0x3FFE0000;
  _heap_top = ABSOLUTE(.);
  _eheap = ABSOLUTE(.);

  .flash.rodata :
  {
    _rodata_start = ABSOLUTE(.);
    *(.rodata)
    *(.rodata.*)
    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
    *(.gnu.linkonce.r.*)
    *(.rodata1)
    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
    *(.xt_except_table)
    *(.gcc_except_table .gcc_except_table.*)
    *(.gnu.linkonce.e.*)
    *(.gnu.version_r)
    . = (. + 3) & ~ 3;
    __eh_frame = ABSOLUTE(.);
    KEEP(*(.eh_frame))
    . = (. + 7) & ~ 3;
    /*  C++ constructor and destructor tables, properly ordered:  */
    __init_array_start = ABSOLUTE(.);
    KEEP (*crtbegin.o(.ctors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
    KEEP (*(SORT(.ctors.*)))
    KEEP (*(.ctors))
    __init_array_end = ABSOLUTE(.);
    KEEP (*crtbegin.o(.dtors))
    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
    KEEP (*(SORT(.dtors.*)))
    KEEP (*(.dtors))
    /*  C++ exception handlers table:  */
    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
    *(.xt_except_desc)
    *(.gnu.linkonce.h.*)
    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
    *(.xt_except_desc_end)
    *(.dynamic)
    *(.gnu.version_d)
    _rodata_end = ABSOLUTE(.);
    /* Literals are also RO data. */
    _lit4_start = ABSOLUTE(.);
    *(*.lit4)
    *(.lit4.*)
    *(.gnu.linkonce.lit4.*)
    _lit4_end = ABSOLUTE(.);
    . = ALIGN(4);
    _thread_local_start = ABSOLUTE(.);
    *(.tdata)
    *(.tdata.*)
    *(.tbss)
    *(.tbss.*)
    _thread_local_end = ABSOLUTE(.);
    . = ALIGN(4);
  } >drom0_0_seg

  .flash.text :
  {
    _stext = .;
    _text_start = ABSOLUTE(.);
    /* place everything else in iram0_2_seg (cached ROM) */
    *(.literal .text .literal.* .text.* .stub)
    *(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
    *(.fini.literal)
    *(.fini)
    *(.gnu.version)
    _text_end = ABSOLUTE(.);
    _etext = .;

    /* Similar to _iram_start, this symbol goes here so it is
       resolved by addr2line in preference to the first symbol in
       the flash.text segment.
    */
    _flash_cache_start = ABSOLUTE(0);
  } >iram0_2_seg
}


Amend memory layout to match tock 1.5 release

/* Layout for the nRF52-DK, used by the examples in this repository. */

MEMORY {
  /* The application region is 64 bytes (0x40) */
  FLASH (rx) : ORIGIN = 0x00030040, LENGTH = 0x0005FFC0
  SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 62K
}

/*
 * Any change to STACK_SIZE should be accompanied by a corresponding change to
 * `elf2tab`'s `--stack` option
 */
STACK_SIZE = 2048;

MPU_MIN_ALIGN = 8K;

INCLUDE layout_generic.ld

/* Layout for the nRF52-DK, used by the examples in this repository. */

MEMORY {
  /* The application region is 64 bytes (0x40) */
  FLASH (rx) : ORIGIN = 0x00030040, LENGTH = 0x0005FFC0
  SRAM (rwx) : ORIGIN = 0x20002000, LENGTH = 62K
}

/*
 * Any change to STACK_SIZE should be accompanied by a corresponding change to
 * `elf2tab`'s `--stack` option
 */
STACK_SIZE = 2048;

MPU_MIN_ALIGN = 8K;

INCLUDE layout_generic.ld


core/host: Format linker script

core/host: Format linker script

This is a cleanup/reformat of the linker script.
This brings no functional change.

BRANCH=none
BUG=b:146083406
TEST=make buildall

Change-Id: I55bef2d9f1a4e3e544b2ef1b4d28825b3a628a44
Signed-off-by: Craig Hesling <383db090fd8ef907a606ac8a9eccd2962bc489cf@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1966288
Reviewed-by: Daisuke Nojiri <fd5f93af191bf7e8f73ea71cc3c0f66b41b1dd49@chromium.org>

/* Copyright 2013 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */
SECTIONS {
	.rodata.ec_sections : {
		/* Symbols defined here are declared in link_defs.h */
		__irqprio = .;
		*(.rodata.irqprio)
		__irqprio_end = .;

		. = ALIGN(8);
		__cmds = .;
		*(SORT(.rodata.cmds*))
		__cmds_end = .;

		. = ALIGN(8);
		__hcmds = .;
		*(SORT(.rodata.hcmds*))
		__hcmds_end = .;

		. = ALIGN(4);
		__mkbp_evt_srcs = .;
		KEEP(*(.rodata.evtsrcs))
		__mkbp_evt_srcs_end = .;

		. = ALIGN(8);
		__hooks_init = .;
		*(.rodata.HOOK_INIT)
		__hooks_init_end = .;

		__hooks_pre_freq_change = .;
		*(.rodata.HOOK_PRE_FREQ_CHANGE)
		__hooks_pre_freq_change_end = .;

		__hooks_freq_change = .;
		*(.rodata.HOOK_FREQ_CHANGE)
		__hooks_freq_change_end = .;

		__hooks_sysjump = .;
		*(.rodata.HOOK_SYSJUMP)
		__hooks_sysjump_end = .;

		__hooks_chipset_pre_init = .;
		*(.rodata.HOOK_CHIPSET_PRE_INIT)
		__hooks_chipset_pre_init_end = .;

		__hooks_chipset_startup = .;
		*(.rodata.HOOK_CHIPSET_STARTUP)
		__hooks_chipset_startup_end = .;

		__hooks_chipset_resume = .;
		*(.rodata.HOOK_CHIPSET_RESUME)
		__hooks_chipset_resume_end = .;

		__hooks_chipset_suspend = .;
		*(.rodata.HOOK_CHIPSET_SUSPEND)
		__hooks_chipset_suspend_end = .;

		__hooks_chipset_shutdown = .;
		*(.rodata.HOOK_CHIPSET_SHUTDOWN)
		__hooks_chipset_shutdown_end = .;

		__hooks_chipset_reset = .;
		*(.rodata.HOOK_CHIPSET_RESET)
		__hooks_chipset_reset_end = .;

		__hooks_ac_change = .;
		*(.rodata.HOOK_AC_CHANGE)
		__hooks_ac_change_end = .;

		__hooks_lid_change = .;
		*(.rodata.HOOK_LID_CHANGE)
		__hooks_lid_change_end = .;

		__hooks_tablet_mode_change = .;
		KEEP(*(.rodata.HOOK_TABLET_MODE_CHANGE))
		__hooks_tablet_mode_change_end = .;

		__hooks_base_attached_change = .;
		KEEP(*(.rodata.HOOK_BASE_ATTACHED_CHANGE))
		__hooks_base_attached_change_end = .;

		__hooks_pwrbtn_change = .;
		*(.rodata.HOOK_POWER_BUTTON_CHANGE)
		__hooks_pwrbtn_change_end = .;

		__hooks_battery_soc_change = .;
		*(.rodata.HOOK_BATTERY_SOC_CHANGE)
		__hooks_battery_soc_change_end = .;

		__hooks_tick = .;
		*(.rodata.HOOK_TICK)
		__hooks_tick_end = .;

		__hooks_second = .;
		*(.rodata.HOOK_SECOND)
		__hooks_second_end = .;

		__hooks_usb_pd_disconnect = .;
		*(.rodata.HOOK_USB_PD_DISCONNECT)
		__hooks_usb_pd_disconnect_end = .;

		__hooks_usb_pd_connect = .;
		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
		__hooks_usb_pd_connect_end = .;

		__deferred_funcs = .;
		*(.rodata.deferred)
		__deferred_funcs_end = .;

		__test_i2c_xfer = .;
		*(.rodata.test_i2c.xfer)
		__test_i2c_xfer_end = .;
	}
}
INSERT BEFORE .rodata;

SECTIONS {
	.bss.ec_sections : {
		/* Symbols defined here are declared in link_defs.h */
		. = ALIGN(8);
		__deferred_until = .;
		. += (__deferred_funcs_end - __deferred_funcs) * (8 / 4);
		__deferred_until_end = .;
	}
}
INSERT BEFORE .bss;


New linkscript including stuff from supplied AArch64 scripts

OUTPUT_ARCH(aarch64)
ENTRY(_start)

PHDRS
{
	code   PT_LOAD FLAGS(5) /* Read | Execute */;
	rodata PT_LOAD FLAGS(4) /* Read */;
	data   PT_LOAD FLAGS(6) /* Read | Write */;
}

SECTIONS
{
	/* =========== CODE section =========== */
	PROVIDE(__start__ = 0x0);
	. = __start__;

	.crt0 :
	{
		KEEP (*(.crt0))
		. = ALIGN(8);
	} :code

	.init :
	{
		KEEP( *(.init) )
		. = ALIGN(8);
	} :code

	.plt :
	{
		*(.plt)
		*(.iplt)
		. = ALIGN(8);
	} :code

	.text :
	{
		*(.text.unlikely .text.*_unlikely .text.unlikely.*)
		*(.text.exit .text.exit.*)
		*(.text.startup .text.startup.*)
		*(.text.hot .text.hot.*)
		*(.text .stub .text.* .gnu.linkonce.t.*)
		. = ALIGN(8);
	} :code

	.fini :
	{
		KEEP( *(.fini) )
		. = ALIGN(8);
	} :code

	/* =========== RODATA section =========== */
	. = ALIGN(0x1000);

	.rodata :
	{
		*(.rodata .rodata.* .gnu.linkonce.r.*)
		. = ALIGN(8);
	} :rodata

	.eh_frame_hdr     : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } :rodata
	.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata
	.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata
	.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata

	.interp            : { *(.interp) } :rodata
	.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata
	.hash              : { *(.hash) } :rodata
	.gnu.hash          : { *(.gnu.hash) } :rodata
	.gnu.version       : { *(.gnu.version) } :rodata
	.gnu.version_d     : { *(.gnu.version_d) } :rodata
	.gnu.version_r     : { *(.gnu.version_r) } :rodata
	.dynsym            : { *(.dynsym) } :rodata
	.dynstr            : { *(.dynstr) } :rodata
	.rela.dyn          : { *(.rela.*) } :rodata

	/* =========== DATA section =========== */
	. = ALIGN(0x1000);

	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data
	.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data
	.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data
	.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data

	.tdata ALIGN(8) :
	{
		__tdata_lma = .;
		*(.tdata .tdata.* .gnu.linkonce.td.*)
		. = ALIGN(8);
		__tdata_lma_end = .;
	} :data

	.tbss ALIGN(8) :
	{
		*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
		. = ALIGN(8);
	} :data

	.preinit_array ALIGN(8) :
	{
		PROVIDE (__preinit_array_start = .);
		KEEP (*(.preinit_array))
		PROVIDE (__preinit_array_end = .);
	} :data

	.init_array ALIGN(8) :
	{
		PROVIDE (__init_array_start = .);
		KEEP (*(SORT(.init_array.*)))
		KEEP (*(.init_array))
		PROVIDE (__init_array_end = .);
	} :data

	.fini_array ALIGN(8) :
	{
		PROVIDE (__fini_array_start = .);
		KEEP (*(.fini_array))
		KEEP (*(SORT(.fini_array.*)))
		PROVIDE (__fini_array_end = .);
	} :data

	.ctors ALIGN(8) :
	{
		KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
		KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
		KEEP (*(SORT(.ctors.*)))
		KEEP (*(.ctors))
	} :data

	.dtors ALIGN(8) :
	{
		KEEP (*crtbegin.o(.dtors))
		KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
		KEEP (*(SORT(.dtors.*)))
		KEEP (*(.dtors))
	} :data

	__got_start__ = .;

	.got            : { *(.got) *(.igot) } :data
	.got.plt        : { *(.got.plt)  *(.igot.plt) } :data

	__got_end__ = .;

	.data ALIGN(8) :
	{
		*(.data .data.* .gnu.linkonce.d.*)
		SORT(CONSTRUCTORS)
	} :data

	.dynamic ALIGN(8) :
	{
		*(.dynamic)
	} :data

	__bss_start__ = .;
	.bss ALIGN(8) :
	{
		*(.dynbss)
		*(.bss .bss.* .gnu.linkonce.b.*)
		*(COMMON)
		. = ALIGN(8);

		/* Reserve space for the TLS segment of the main thread */
		__tls_start = .;
		. += + SIZEOF(.tdata) + SIZEOF(.tbss);
		__tls_end = .;
	} : data
	__bss_end__ = .;

	__end__ = ABSOLUTE(.) ;

	/* ==================
	   ==== Metadata ====
	   ================== */

	/* Discard sections that difficult post-processing */
	/DISCARD/ : { *(.group .comment .note) }

	/* Stabs debugging sections. */
	.stab          0 : { *(.stab) }
	.stabstr       0 : { *(.stabstr) }
	.stab.excl     0 : { *(.stab.excl) }
	.stab.exclstr  0 : { *(.stab.exclstr) }
	.stab.index    0 : { *(.stab.index) }
	.stab.indexstr 0 : { *(.stab.indexstr) }

	/* DWARF debug sections.
	   Symbols in the DWARF debugging sections are relative to the beginning
	   of the section so we begin them at 0. */

	/* DWARF 1 */
	.debug          0 : { *(.debug) }
	.line           0 : { *(.line) }

	/* GNU DWARF 1 extensions */
	.debug_srcinfo  0 : { *(.debug_srcinfo) }
	.debug_sfnames  0 : { *(.debug_sfnames) }

	/* DWARF 1.1 and DWARF 2 */
	.debug_aranges  0 : { *(.debug_aranges) }
	.debug_pubnames 0 : { *(.debug_pubnames) }

	/* DWARF 2 */
	.debug_info     0 : { *(.debug_info) }
	.debug_abbrev   0 : { *(.debug_abbrev) }
	.debug_line     0 : { *(.debug_line) }
	.debug_frame    0 : { *(.debug_frame) }
	.debug_str      0 : { *(.debug_str) }
	.debug_loc      0 : { *(.debug_loc) }
	.debug_macinfo  0 : { *(.debug_macinfo) }
}

OUTPUT_ARCH(aarch64)
ENTRY(_start)

PHDRS
{
	code   PT_LOAD FLAGS(5) /* Read | Execute */;
	rodata PT_LOAD FLAGS(4) /* Read */;
	data   PT_LOAD FLAGS(6) /* Read | Write */;
}

SECTIONS
{
	/* =========== CODE section =========== */

	PROVIDE(__start__ = 0x0);
	. = __start__;

	.text ALIGN(0x1000) :
	{
		/* .init */
		KEEP( *(.crt0) )
		KEEP( *(.init) )
		. = ALIGN(4);

		/* .text */
		*(.text)
		*(.text.*)
		*(.glue_7)
		*(.glue_7t)
		*(.stub)
		*(.gnu.warning)
		*(.gnu.linkonce.t*)
		. = ALIGN(4);

		/* .fini */
		KEEP( *(.fini) )
		. = ALIGN(4);
	} : code

	/* =========== RODATA section =========== */

	.rodata ALIGN(0x1000) :
	{
		*(.rodata)
		*(.roda)
		*(.rodata.*)
		*all.rodata*(*)
		*(.gnu.linkonce.r*)
		SORT(CONSTRUCTORS)
		. = ALIGN(4);
	} : rodata

	.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } : rodata
	__exidx_start = .;
	ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } : rodata
	__exidx_end = .;

	/* =========== DATA section =========== */

	.data ALIGN(0x1000) :
	{
		*(.data)
		*(.data.*)
		*(.gnu.linkonce.d*)
		CONSTRUCTORS
		. = ALIGN(4);
                __got_start__ = .;
                *(.got)
	        __got_end__ = .;
	} : data

	.tdata ALIGN(4) :
	{
		__tdata_lma = .;
		*(.tdata)
		*(.tdata.*)
		*(.gnu.linkonce.td.*)
		. = ALIGN(4);
		__tdata_lma_end = .;
	} : data

	.tbss ALIGN(4) :
	{
		*(.tbss)
		*(.tbss.*)
		*(.gnu.linkonce.tb.*)
		*(.tcommon)
		. = ALIGN(4);
	} : data

	.preinit_array ALIGN(4) :
	{
		PROVIDE (__preinit_array_start = .);
		KEEP (*(.preinit_array))
		PROVIDE (__preinit_array_end = .);
	} : data

	.init_array ALIGN(4) :
	{
		PROVIDE (__init_array_start = .);
		KEEP (*(SORT(.init_array.*)))
		KEEP (*(.init_array))
		PROVIDE (__init_array_end = .);
	} : data

	.fini_array ALIGN(4) :
	{
		PROVIDE (__fini_array_start = .);
		KEEP (*(.fini_array))
		KEEP (*(SORT(.fini_array.*)))
		PROVIDE (__fini_array_end = .);
	} : data

	.ctors ALIGN(4) :
	{
		KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
		KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
		KEEP (*(SORT(.ctors.*)))
		KEEP (*(.ctors))
	} : data

	.dtors ALIGN(4) :
	{
		KEEP (*crtbegin.o(.dtors))
		KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
		KEEP (*(SORT(.dtors.*)))
		KEEP (*(.dtors))
	} : data

	__bss_start__ = .;
	.bss ALIGN(4) :
	{
		*(.dynbss)
		*(.bss)
		*(.bss.*)
		*(.gnu.linkonce.b*)
		*(COMMON)
		. = ALIGN(4);

		/* Reserve space for the TLS segment of the main thread */
		__tls_start = .;
		. += + SIZEOF(.tdata) + SIZEOF(.tbss);
		__tls_end = .;
	} : data
	__bss_end__ = .;

	__end__ = ABSOLUTE(.) ;

	/* ==================
	   ==== Metadata ====
	   ================== */

	/* Discard sections that difficult post-processing */
	/DISCARD/ : { *(.group .comment .note) }

	/* Stabs debugging sections. */
	.stab          0 : { *(.stab) }
	.stabstr       0 : { *(.stabstr) }
	.stab.excl     0 : { *(.stab.excl) }
	.stab.exclstr  0 : { *(.stab.exclstr) }
	.stab.index    0 : { *(.stab.index) }
	.stab.indexstr 0 : { *(.stab.indexstr) }

	/* DWARF debug sections.
	   Symbols in the DWARF debugging sections are relative to the beginning
	   of the section so we begin them at 0. */

	/* DWARF 1 */
	.debug          0 : { *(.debug) }
	.line           0 : { *(.line) }

	/* GNU DWARF 1 extensions */
	.debug_srcinfo  0 : { *(.debug_srcinfo) }
	.debug_sfnames  0 : { *(.debug_sfnames) }

	/* DWARF 1.1 and DWARF 2 */
	.debug_aranges  0 : { *(.debug_aranges) }
	.debug_pubnames 0 : { *(.debug_pubnames) }

	/* DWARF 2 */
	.debug_info     0 : { *(.debug_info) }
	.debug_abbrev   0 : { *(.debug_abbrev) }
	.debug_line     0 : { *(.debug_line) }
	.debug_frame    0 : { *(.debug_frame) }
	.debug_str      0 : { *(.debug_str) }
	.debug_loc      0 : { *(.debug_loc) }
	.debug_macinfo  0 : { *(.debug_macinfo) }
}


Fix up GPIO addresses

Fix up GPIO addresses

PROVIDE(isr_dac          = isr_hardfault);
PROVIDE(isr_m0app        = isr_hardfault);
PROVIDE(isr_dma          = isr_hardfault);
PROVIDE(isr_reserved     = isr_hardfault);
PROVIDE(isr_flasheeprom  = isr_hardfault);
PROVIDE(isr_enet         = isr_hardfault);
PROVIDE(isr_sdio         = isr_hardfault);
PROVIDE(isr_lcd          = isr_hardfault);
PROVIDE(isr_usb0         = isr_hardfault);
PROVIDE(isr_usb1         = isr_hardfault);
PROVIDE(isr_sctimer_pwm  = isr_hardfault);
PROVIDE(isr_ritimer      = isr_hardfault);
PROVIDE(isr_timer_0      = isr_hardfault);
PROVIDE(isr_timer_1      = isr_hardfault);
PROVIDE(isr_timer_2      = isr_hardfault);
PROVIDE(isr_timer_3      = isr_hardfault);
PROVIDE(isr_mcpwm        = isr_hardfault);
PROVIDE(isr_adc0         = isr_hardfault);
PROVIDE(isr_i2c_0        = isr_hardfault);
PROVIDE(isr_i2c_1        = isr_hardfault);
PROVIDE(isr_spi          = isr_hardfault);
PROVIDE(isr_adc1         = isr_hardfault);
PROVIDE(isr_ssp_0        = isr_hardfault);
PROVIDE(isr_ssp_1        = isr_hardfault);
PROVIDE(isr_uart_0       = isr_hardfault);
PROVIDE(isr_uart_1       = isr_hardfault);
PROVIDE(isr_uart_2       = isr_hardfault);
PROVIDE(isr_uart_3       = isr_hardfault);
PROVIDE(isr_i2s0         = isr_hardfault);
PROVIDE(isr_i2s1         = isr_hardfault);
PROVIDE(isr_spifi        = isr_hardfault);
PROVIDE(isr_sgpio        = isr_hardfault);
PROVIDE(isr_pin_int0     = isr_hardfault);
PROVIDE(isr_pin_int1     = isr_hardfault);
PROVIDE(isr_pin_int2     = isr_hardfault);
PROVIDE(isr_pin_int3     = isr_hardfault);
PROVIDE(isr_pin_int4     = isr_hardfault);
PROVIDE(isr_pin_int5     = isr_hardfault);
PROVIDE(isr_pin_int6     = isr_hardfault);
PROVIDE(isr_pin_int7     = isr_hardfault);
PROVIDE(isr_gint0        = isr_hardfault);
PROVIDE(isr_gint1        = isr_hardfault);
PROVIDE(isr_eventrouter  = isr_hardfault);
PROVIDE(isr_c_can1       = isr_hardfault);
PROVIDE(isr_reserved     = isr_hardfault);
PROVIDE(isr_adchs        = isr_hardfault);
PROVIDE(isr_atimer       = isr_hardfault);
PROVIDE(isr_rtc          = isr_hardfault);
PROVIDE(isr_reserved     = isr_hardfault);
PROVIDE(isr_wwdt         = isr_hardfault);
PROVIDE(isr_m0sub        = isr_hardfault);
PROVIDE(isr_c_can0       = isr_hardfault);
PROVIDE(isr_qei          = isr_hardfault);

/* --- LPC43XX specific peripheral definitions ----------------------------- */
/* local SRAM / external static memory banks (0x1000 0000 - 0x2000 0000) */

lpc17xx_iomem_SPIFI_DATA = 0x14000000;

/* Memory map for all busses */
lpc17xx_iomem_PERIPH_AHB  = 0x40000000;
lpc17xx_iomem_PERIPH_APB0 = 0x40080000;
lpc17xx_iomem_PERIPH_APB1 = 0x400A0000;
lpc17xx_iomem_PERIPH_APB2 = 0x400C0000;
lpc17xx_iomem_PERIPH_APB3 = 0x400E0000;

/* Register boundary addresses */
/* AHB (0x4000 0000 - 0x4001 2000) */
lpc17xx_iomem_SCT = (lpc17xx_iomem_PERIPH_AHB + 0x00000);

/* PERIPH_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
lpc17xx_iomem_GPDMA = (lpc17xx_iomem_PERIPH_AHB + 0x02000);
lpc17xx_iomem_SPIFI = (lpc17xx_iomem_PERIPH_AHB + 0x03000);
lpc17xx_iomem_SDIO  = (lpc17xx_iomem_PERIPH_AHB + 0x04000);
lpc17xx_iomem_EMC   = (lpc17xx_iomem_PERIPH_AHB + 0x05000);
lpc17xx_iomem_USB0  = (lpc17xx_iomem_PERIPH_AHB + 0x06000);
lpc17xx_iomem_USB1  = (lpc17xx_iomem_PERIPH_AHB + 0x07000);
lpc17xx_iomem_LCD   = (lpc17xx_iomem_PERIPH_AHB + 0x08000);

/* PERIPH_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
lpc17xx_iomem_ETHERNET = (lpc17xx_iomem_PERIPH_AHB + 0x10000);

/* 0x4001 2000 - 0x4003 FFFF Reserved */

/* RTC domain peripherals */
lpc17xx_iomem_ATIMER      = 0x40040000;
lpc17xx_iomem_BACKUP_REG  = 0x40041000;
lpc17xx_iomem_PMC         = 0x40042000;
lpc17xx_iomem_CREG        = 0x40043000;
lpc17xx_iomem_EVENTROUTER = 0x40044000;
lpc17xx_iomem_OTP         = 0x40045000;
lpc17xx_iomem_RTC         = 0x40046000;

/* 0x4004 7000 - 0x4004 FFFF Reserved */

/* clocking/reset control peripherals */
lpc17xx_iomem_CGU  = 0x40050000;
lpc17xx_iomem_CCU1 = 0x40051000;
lpc17xx_iomem_CCU2 = 0x40052000;
lpc17xx_iomem_RGU  = 0x40053000;

/* 0x4005 4000 - 0x4005 FFFF Reserved */
/* 0x4006 0000 - 0x4007 FFFF Reserved */

/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
lpc17xx_iomem_WWDT                  = (lpc17xx_iomem_PERIPH_APB0 + 0x00000);
lpc17xx_iomem_USART0                = (lpc17xx_iomem_PERIPH_APB0 + 0x01000);
lpc17xx_iomem_UART1                 = (lpc17xx_iomem_PERIPH_APB0 + 0x02000);
lpc17xx_iomem_SSP0                  = (lpc17xx_iomem_PERIPH_APB0 + 0x03000);
lpc17xx_iomem_TIMER0                = (lpc17xx_iomem_PERIPH_APB0 + 0x04000);
lpc17xx_iomem_TIMER1                = (lpc17xx_iomem_PERIPH_APB0 + 0x05000);
lpc17xx_iomem_SCU                   = (lpc17xx_iomem_PERIPH_APB0 + 0x06000);
lpc17xx_iomem_GPIO_PIN_INTERRUPT    = (lpc17xx_iomem_PERIPH_APB0 + 0x07000);
lpc17xx_iomem_GPIO_GROUP0_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x08000);
lpc17xx_iomem_GPIO_GROUP1_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x09000);

/* 0x4008 A000 - 0x4008 FFFF Reserved */
/* 0x4009 0000 - 0x4009 FFFF Reserved */

/* APB1 (0x400A 0000 - 0x400A FFFF) */
lpc17xx_iomem_MCPWM   = (lpc17xx_iomem_PERIPH_APB1 + 0x00000);
lpc17xx_iomem_I2C0    = (lpc17xx_iomem_PERIPH_APB1 + 0x01000);
lpc17xx_iomem_I2S0    = (lpc17xx_iomem_PERIPH_APB1 + 0x02000);
lpc17xx_iomem_I2S1    = (lpc17xx_iomem_PERIPH_APB1 + 0x03000);
lpc17xx_iomem_C_CCAN1 = (lpc17xx_iomem_PERIPH_APB1 + 0x04000);

/* 0x400A 5000 - 0x400A FFFF Reserved */
/* 0x400B 0000 - 0x400B FFFF Reserved */

/* APB2 (0x400C 0000 - 0x400C FFFF) */
lpc17xx_iomem_RITIMER = (lpc17xx_iomem_PERIPH_APB2 + 0x00000);
lpc17xx_iomem_USART2  = (lpc17xx_iomem_PERIPH_APB2 + 0x01000);
lpc17xx_iomem_USART3  = (lpc17xx_iomem_PERIPH_APB2 + 0x02000);
lpc17xx_iomem_TIMER2  = (lpc17xx_iomem_PERIPH_APB2 + 0x03000);
lpc17xx_iomem_TIMER3  = (lpc17xx_iomem_PERIPH_APB2 + 0x04000);
lpc17xx_iomem_SSP1    = (lpc17xx_iomem_PERIPH_APB2 + 0x05000);
lpc17xx_iomem_QEI     = (lpc17xx_iomem_PERIPH_APB2 + 0x06000);
lpc17xx_iomem_GIMA    = (lpc17xx_iomem_PERIPH_APB2 + 0x07000);

/* 0x400C 8000 - 0x400C FFFF Reserved */
/* 0x400D 0000 - 0x400D FFFF Reserved */

/* APB3 (0x400E 0000 - 0x400E FFFF) */
lpc17xx_iomem_I2C1   = (lpc17xx_iomem_PERIPH_APB3 + 0x00000);
lpc17xx_iomem_DAC    = (lpc17xx_iomem_PERIPH_APB3 + 0x01000);
lpc17xx_iomem_C_CAN0 = (lpc17xx_iomem_PERIPH_APB3 + 0x02000);
lpc17xx_iomem_ADC0   = (lpc17xx_iomem_PERIPH_APB3 + 0x03000);
lpc17xx_iomem_ADC1   = (lpc17xx_iomem_PERIPH_APB3 + 0x04000);

/* 0x400E 5000 - 0x400E FFFF Reserved */
/* 0x400F 0000 - 0x400F 0FFF Reserved */

lpc17xx_iomem_AES = 0x400F1000;

/* 0x400F 2000 - 0x400F 3FFF Reserved */

lpc17xx_iomem_GPIO_PORT = 0x400F4000;

/* 0x400F 8000 - 0x400F FFFF Reserved */

lpc17xx_iomem_SPI_PORT   = 0x40100000;
lpc17xx_iomem_SGPIO_PORT = 0x40101000;

/* 0x4010 2000 - 0x41FF FFFF Reserved */
/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
/* 0x4400 0000 - 0x5FFF FFFF Reserved */

/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
lpc17xx_iomem_SPIFI_DATA_UNCACHED = 0x80000000;

/* Lifted from a real lpc17xx, maybe (probably) incorrect) */
lpc17xx_iomem_PINSEL0   = 0x4002C000;
lpc17xx_iomem_PINSEL1   = 0x4002C004;
lpc17xx_iomem_PINSEL2   = 0x4002C008;
lpc17xx_iomem_PINSEL3   = 0x4002C00C;
lpc17xx_iomem_PINSEL4   = 0x4002C010;
lpc17xx_iomem_PINSEL7   = 0x4002C01C;
lpc17xx_iomem_PINSEL9   = 0x4002C024;
lpc17xx_iomem_PINSEL10  = 0x4002C028;

lpc17xx_iomem_PINMODE0  = 0x4002C040;
lpc17xx_iomem_PINMODE1  = 0x4002C044;
lpc17xx_iomem_PINMODE2  = 0x4002C048;
lpc17xx_iomem_PINMODE3  = 0x4002C04C;
lpc17xx_iomem_PINMODE4  = 0x4002C050;
lpc17xx_iomem_PINMODE7  = 0x4002C05C;
lpc17xx_iomem_PINMODE9  = 0x4002C064;

lpc17xx_iomem_PCONP     = 0x400FC0C4;

lpc17xx_iomem_PCLKSEL0  = 0x400FC1A8;
lpc17xx_iomem_PCLKSEL1  = 0x400FC1AC;

lpc17xx_iomem_ADC       = 0x40034000;

GPIO_LPC_PORT_OFFSET = lpc17xx_iomem_GPIO_PORT + 0x2000;
lpc17xx_iomem_GPIO0  = GPIO_LPC_PORT_OFFSET + (0*4);
lpc17xx_iomem_GPIO1  = GPIO_LPC_PORT_OFFSET + (1*4);
lpc17xx_iomem_GPIO2  = GPIO_LPC_PORT_OFFSET + (2*4);
lpc17xx_iomem_GPIO3  = GPIO_LPC_PORT_OFFSET + (3*4);
lpc17xx_iomem_GPIO4  = GPIO_LPC_PORT_OFFSET + (4*4);
lpc17xx_iomem_GPIO5  = GPIO_LPC_PORT_OFFSET + (5*4);
lpc17xx_iomem_GPIO6  = GPIO_LPC_PORT_OFFSET + (6*4);
lpc17xx_iomem_GPIO7  = GPIO_LPC_PORT_OFFSET + (7*4);

PROVIDE(isr_dac          = isr_hardfault);
PROVIDE(isr_m0app        = isr_hardfault);
PROVIDE(isr_dma          = isr_hardfault);
PROVIDE(isr_reserved     = isr_hardfault);
PROVIDE(isr_flasheeprom  = isr_hardfault);
PROVIDE(isr_enet         = isr_hardfault);
PROVIDE(isr_sdio         = isr_hardfault);
PROVIDE(isr_lcd          = isr_hardfault);
PROVIDE(isr_usb0         = isr_hardfault);
PROVIDE(isr_usb1         = isr_hardfault);
PROVIDE(isr_sctimer_pwm  = isr_hardfault);
PROVIDE(isr_ritimer      = isr_hardfault);
PROVIDE(isr_timer_0      = isr_hardfault);
PROVIDE(isr_timer_1      = isr_hardfault);
PROVIDE(isr_timer_2      = isr_hardfault);
PROVIDE(isr_timer_3      = isr_hardfault);
PROVIDE(isr_mcpwm        = isr_hardfault);
PROVIDE(isr_adc0         = isr_hardfault);
PROVIDE(isr_i2c_0        = isr_hardfault);
PROVIDE(isr_i2c_1        = isr_hardfault);
PROVIDE(isr_spi          = isr_hardfault);
PROVIDE(isr_adc1         = isr_hardfault);
PROVIDE(isr_ssp_0        = isr_hardfault);
PROVIDE(isr_ssp_1        = isr_hardfault);
PROVIDE(isr_uart_0       = isr_hardfault);
PROVIDE(isr_uart_1       = isr_hardfault);
PROVIDE(isr_uart_2       = isr_hardfault);
PROVIDE(isr_uart_3       = isr_hardfault);
PROVIDE(isr_i2s0         = isr_hardfault);
PROVIDE(isr_i2s1         = isr_hardfault);
PROVIDE(isr_spifi        = isr_hardfault);
PROVIDE(isr_sgpio        = isr_hardfault);
PROVIDE(isr_pin_int0     = isr_hardfault);
PROVIDE(isr_pin_int1     = isr_hardfault);
PROVIDE(isr_pin_int2     = isr_hardfault);
PROVIDE(isr_pin_int3     = isr_hardfault);
PROVIDE(isr_pin_int4     = isr_hardfault);
PROVIDE(isr_pin_int5     = isr_hardfault);
PROVIDE(isr_pin_int6     = isr_hardfault);
PROVIDE(isr_pin_int7     = isr_hardfault);
PROVIDE(isr_gint0        = isr_hardfault);
PROVIDE(isr_gint1        = isr_hardfault);
PROVIDE(isr_eventrouter  = isr_hardfault);
PROVIDE(isr_c_can1       = isr_hardfault);
PROVIDE(isr_reserved     = isr_hardfault);
PROVIDE(isr_adchs        = isr_hardfault);
PROVIDE(isr_atimer       = isr_hardfault);
PROVIDE(isr_rtc          = isr_hardfault);
PROVIDE(isr_reserved     = isr_hardfault);
PROVIDE(isr_wwdt         = isr_hardfault);
PROVIDE(isr_m0sub        = isr_hardfault);
PROVIDE(isr_c_can0       = isr_hardfault);
PROVIDE(isr_qei          = isr_hardfault);

/* --- LPC43XX specific peripheral definitions ----------------------------- */
/* local SRAM / external static memory banks (0x1000 0000 - 0x2000 0000) */

lpc17xx_iomem_SPIFI_DATA = 0x14000000;

/* Memory map for all busses */
lpc17xx_iomem_PERIPH_AHB  = 0x40000000;
lpc17xx_iomem_PERIPH_APB0 = 0x40080000;
lpc17xx_iomem_PERIPH_APB1 = 0x400A0000;
lpc17xx_iomem_PERIPH_APB2 = 0x400C0000;
lpc17xx_iomem_PERIPH_APB3 = 0x400E0000;

/* Register boundary addresses */
/* AHB (0x4000 0000 - 0x4001 2000) */
lpc17xx_iomem_SCT = (lpc17xx_iomem_PERIPH_AHB + 0x00000);

/* PERIPH_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
lpc17xx_iomem_GPDMA = (lpc17xx_iomem_PERIPH_AHB + 0x02000);
lpc17xx_iomem_SPIFI = (lpc17xx_iomem_PERIPH_AHB + 0x03000);
lpc17xx_iomem_SDIO  = (lpc17xx_iomem_PERIPH_AHB + 0x04000);
lpc17xx_iomem_EMC   = (lpc17xx_iomem_PERIPH_AHB + 0x05000);
lpc17xx_iomem_USB0  = (lpc17xx_iomem_PERIPH_AHB + 0x06000);
lpc17xx_iomem_USB1  = (lpc17xx_iomem_PERIPH_AHB + 0x07000);
lpc17xx_iomem_LCD   = (lpc17xx_iomem_PERIPH_AHB + 0x08000);

/* PERIPH_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
lpc17xx_iomem_ETHERNET = (lpc17xx_iomem_PERIPH_AHB + 0x10000);

/* 0x4001 2000 - 0x4003 FFFF Reserved */

/* RTC domain peripherals */
lpc17xx_iomem_ATIMER      = 0x40040000;
lpc17xx_iomem_BACKUP_REG  = 0x40041000;
lpc17xx_iomem_PMC         = 0x40042000;
lpc17xx_iomem_CREG        = 0x40043000;
lpc17xx_iomem_EVENTROUTER = 0x40044000;
lpc17xx_iomem_OTP         = 0x40045000;
lpc17xx_iomem_RTC         = 0x40046000;

/* 0x4004 7000 - 0x4004 FFFF Reserved */

/* clocking/reset control peripherals */
lpc17xx_iomem_CGU  = 0x40050000;
lpc17xx_iomem_CCU1 = 0x40051000;
lpc17xx_iomem_CCU2 = 0x40052000;
lpc17xx_iomem_RGU  = 0x40053000;

/* 0x4005 4000 - 0x4005 FFFF Reserved */
/* 0x4006 0000 - 0x4007 FFFF Reserved */

/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
lpc17xx_iomem_WWDT                  = (lpc17xx_iomem_PERIPH_APB0 + 0x00000);
lpc17xx_iomem_USART0                = (lpc17xx_iomem_PERIPH_APB0 + 0x01000);
lpc17xx_iomem_UART1                 = (lpc17xx_iomem_PERIPH_APB0 + 0x02000);
lpc17xx_iomem_SSP0                  = (lpc17xx_iomem_PERIPH_APB0 + 0x03000);
lpc17xx_iomem_TIMER0                = (lpc17xx_iomem_PERIPH_APB0 + 0x04000);
lpc17xx_iomem_TIMER1                = (lpc17xx_iomem_PERIPH_APB0 + 0x05000);
lpc17xx_iomem_SCU                   = (lpc17xx_iomem_PERIPH_APB0 + 0x06000);
lpc17xx_iomem_GPIO_PIN_INTERRUPT    = (lpc17xx_iomem_PERIPH_APB0 + 0x07000);
lpc17xx_iomem_GPIO_GROUP0_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x08000);
lpc17xx_iomem_GPIO_GROUP1_INTERRUPT = (lpc17xx_iomem_PERIPH_APB0 + 0x09000);

/* 0x4008 A000 - 0x4008 FFFF Reserved */
/* 0x4009 0000 - 0x4009 FFFF Reserved */

/* APB1 (0x400A 0000 - 0x400A FFFF) */
lpc17xx_iomem_MCPWM   = (lpc17xx_iomem_PERIPH_APB1 + 0x00000);
lpc17xx_iomem_I2C0    = (lpc17xx_iomem_PERIPH_APB1 + 0x01000);
lpc17xx_iomem_I2S0    = (lpc17xx_iomem_PERIPH_APB1 + 0x02000);
lpc17xx_iomem_I2S1    = (lpc17xx_iomem_PERIPH_APB1 + 0x03000);
lpc17xx_iomem_C_CCAN1 = (lpc17xx_iomem_PERIPH_APB1 + 0x04000);

/* 0x400A 5000 - 0x400A FFFF Reserved */
/* 0x400B 0000 - 0x400B FFFF Reserved */

/* APB2 (0x400C 0000 - 0x400C FFFF) */
lpc17xx_iomem_RITIMER = (lpc17xx_iomem_PERIPH_APB2 + 0x00000);
lpc17xx_iomem_USART2  = (lpc17xx_iomem_PERIPH_APB2 + 0x01000);
lpc17xx_iomem_USART3  = (lpc17xx_iomem_PERIPH_APB2 + 0x02000);
lpc17xx_iomem_TIMER2  = (lpc17xx_iomem_PERIPH_APB2 + 0x03000);
lpc17xx_iomem_TIMER3  = (lpc17xx_iomem_PERIPH_APB2 + 0x04000);
lpc17xx_iomem_SSP1    = (lpc17xx_iomem_PERIPH_APB2 + 0x05000);
lpc17xx_iomem_QEI     = (lpc17xx_iomem_PERIPH_APB2 + 0x06000);
lpc17xx_iomem_GIMA    = (lpc17xx_iomem_PERIPH_APB2 + 0x07000);

/* 0x400C 8000 - 0x400C FFFF Reserved */
/* 0x400D 0000 - 0x400D FFFF Reserved */

/* APB3 (0x400E 0000 - 0x400E FFFF) */
lpc17xx_iomem_I2C1   = (lpc17xx_iomem_PERIPH_APB3 + 0x00000);
lpc17xx_iomem_DAC    = (lpc17xx_iomem_PERIPH_APB3 + 0x01000);
lpc17xx_iomem_C_CAN0 = (lpc17xx_iomem_PERIPH_APB3 + 0x02000);
lpc17xx_iomem_ADC0   = (lpc17xx_iomem_PERIPH_APB3 + 0x03000);
lpc17xx_iomem_ADC1   = (lpc17xx_iomem_PERIPH_APB3 + 0x04000);

/* 0x400E 5000 - 0x400E FFFF Reserved */
/* 0x400F 0000 - 0x400F 0FFF Reserved */

lpc17xx_iomem_AES = 0x400F1000;

/* 0x400F 2000 - 0x400F 3FFF Reserved */

lpc17xx_iomem_GPIO_PORT = 0x400F4000;

/* 0x400F 8000 - 0x400F FFFF Reserved */

lpc17xx_iomem_SPI_PORT   = 0x40100000;
lpc17xx_iomem_SGPIO_PORT = 0x40101000;

/* 0x4010 2000 - 0x41FF FFFF Reserved */
/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
/* 0x4400 0000 - 0x5FFF FFFF Reserved */

/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
lpc17xx_iomem_SPIFI_DATA_UNCACHED = 0x80000000;

/* Lifted from a real lpc17xx, maybe (probably) incorrect) */
lpc17xx_iomem_PINSEL0   = 0x4002C000;
lpc17xx_iomem_PINSEL1   = 0x4002C004;
lpc17xx_iomem_PINSEL2   = 0x4002C008;
lpc17xx_iomem_PINSEL3   = 0x4002C00C;
lpc17xx_iomem_PINSEL4   = 0x4002C010;
lpc17xx_iomem_PINSEL7   = 0x4002C01C;
lpc17xx_iomem_PINSEL9   = 0x4002C024;
lpc17xx_iomem_PINSEL10  = 0x4002C028;

lpc17xx_iomem_PINMODE0  = 0x4002C040;
lpc17xx_iomem_PINMODE1  = 0x4002C044;
lpc17xx_iomem_PINMODE2  = 0x4002C048;
lpc17xx_iomem_PINMODE3  = 0x4002C04C;
lpc17xx_iomem_PINMODE4  = 0x4002C050;
lpc17xx_iomem_PINMODE7  = 0x4002C05C;
lpc17xx_iomem_PINMODE9  = 0x4002C064;

lpc17xx_iomem_PCONP     = 0x400FC0C4;

lpc17xx_iomem_PCLKSEL0  = 0x400FC1A8;
lpc17xx_iomem_PCLKSEL1  = 0x400FC1AC;

lpc17xx_iomem_ADC       = 0x40034000;

lpc17xx_iomem_GPIO0     = 0x2009C000;
lpc17xx_iomem_GPIO1     = 0x2009C020;
lpc17xx_iomem_GPIO2     = 0x2009C040;
lpc17xx_iomem_GPIO3     = 0x2009C060;
lpc17xx_iomem_GPIO4     = 0x2009C080;