Title: Complete DFM Model for High-Performance Computing SoCs with Guard Ring and Dummy Fill Effect,
Abstract: For nanotechnology, the semiconductor device is scaled down dramatically with
additional strain engineering for device enhancement, the overall device
characteristic is no longer dominated by the device size but also circuit
layout. The higher order layout effects, such as well proximity effect (WPE),
oxide spacing effect (OSE) and poly spacing effect (PSE), play an important
role for the device performance, it is critical to understand Design for
Manufacturability (DFM) impacts with various layout topology toward the overall
circuit performance. Currently, the layout effects (WPE, OSE and PSE) are
validated through digital standard cell and analog differential pair test
structure. However, two analog layout structures: the guard ring and dummy fill
impact are not well studied yet, then, this paper describes the current mirror
test circuit to examine the guard ring and dummy fills DFM impacts using TSMC
28nm HPM process.