Title: Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations,
Abstract: Level-sensitive latches are widely used in high- performance designs. For
such circuits efficient statistical timing analysis algorithms are needed to
take increasing process vari- ations into account. But existing methods solving
this problem are still computationally expensive and can only provide the yield
at a given clock period. In this paper we propose a method combining reduced
iterations and graph transformations. The reduced iterations extract setup time
constraints and identify a subgraph for the following graph transformations
handling the constraints from nonpositive loops. The combined algorithms are
very efficient, more than 10 times faster than other existing methods, and
result in a parametric minimum clock period, which together with the hold time
constraints can be used to compute the yield at any given clock period very
easily.