Title: An Accurate Interconnect Test Structure for Parasitic Validation in On-Chip Machine Learning Accelerators,
Abstract: For nanotechnology nodes, the feature size is shrunk rapidly, the wire
becomes narrow and thin, it leads to high RC parasitic, especially for
resistance. The overall system performance are dominated by interconnect rather
than device. As such, it is imperative to accurately measure and model
interconnect parasitic in order to predict interconnect performance on silicon.
Despite many test structures developed in the past to characterize device
models and layout effects, only few of them are available for interconnects.
Nevertheless, they are either not suitable for real chip implementation or too
complicated to be embedded. A compact yet comprehensive test structure to
capture all interconnect parasitic in a real chip is needed. To address this
problem, this paper describes a set of test structures that can be used to
study the timing performance (i.e. propagation delay and crosstalk) of various
interconnect configurations. Moreover, an empirical model is developed to
estimate the actual RC parasitic. Compared with the state-of-the-art
interconnect test structures, the new structure is compact in size and can be
easily embedded on die as a parasitic variation monitor. We have validated the
proposed structure on a test chip in TSMC 28nm HPM process. Recently, the test
structure is further modified to identify the serious interconnect process
issues for critical path design using TSMC 7nm FF process.