
gadiyara domine crossing

digital electronic designlo clack domine crossing (sidisi), ledhaa kevalam clack crossing, anedi oka gadiyara domine nundi maroka gadiyara domainloki synchronous digital circuitlo signal yokka traversal. oka signal ekkuvasepu nokki cheppakapothe mariyu namodu cheyabadakapothe, adhi incoming clack boundarypai asynchronousga kanipinchavacchu.
oka samakaaleekarana vyavastha gadiyara sanketaanni utpatti chese oke electronic ausilator mariyu daani gadiyara domaintho koodi untundi-aaa ausilator nundi aaa signal dwara neerugaa gadiyaram cheyabadina memory elements mariyu aaa memory elements yokka avutputlaku jodinchina combinational logic.
kaanti vegam alasyam, samaya vakrata modalaina vaati kaaranamgaa.atuvanti samakaaleekarana vyavasthalo gadiyara domine parimaanam gadiyaram yokka pounahpunyaaniki vilomaanupaatamlo untundi. prarambha computerlalo, saadhaaranamgaa anni digital tarkam oke gadiyara domainlo nadustundi. transmission line nashtam mariyu vakreekarana kaaranamgaa praamaanika pcb jadalapai 66 emhechz kante ekkuva digital sankethaalanu teesukelladam kashtam (gadiyara sanketam synchronous digital vyavasthalo atyadhika frequency), aaa vegam kante vaegamgaa nadiche sipus sthiramgaa faze-locked loop (pll) ledhaa itara aann-chip aasiletartho kuudina single-chip sipus, vegavantamaina sankethaalanu chiplo unchutundi. modata, prati cpu chip daani swantha single clack domainlo nadichindi, mariyu computer yokka migilina digital logic maroka sloe clack domainlo nadichindi. konni aadhunika sipaslalo chaalaa adhika vegam gala gadiyaram untundi, designerlu oke cpu chiplo aneka vibhina gadiyara domainlanu srushtinchavalasi vastundi.
ververu gadiyara domainlalo ververu frequency, ververu dasha (ververu gadiyara jaapyam ledhaa ververu gadiyara muulam kaaranamgaa) ledhaa rendoo untaayi. yea vidhamgaanainaa rendu domainlalo gadiyara anchula madhya sambandhaanni aadhaarapadaleru.
adhika frequencytho gadiyara domainku oke bitt signalnu samakaaleekarinchadam anedi soars domine dwara clack cheyabadina flip-flap dwara signalnu namodu cheyadam dwara saadhinchavachchu, tadwara adhika frequency clack cheyabadina gamya domine dwara gurtinchagaligenta ekkuva signalnu pattukondi.
sidisi metastability samasyalu asynchronous clack domainla madhya sambhavinchavachhu; idhi domine crossing metastabilityni reset cheyadaaniki viruddhamgaa untundi, idhi synchronous & asynchronous clack domainla madhya sambhavinchavachhu. gamya gadiyara domainlo sidisi metastabilitytho samasyalanu nivaarinchadaaniki, gamya domainlo rii-synchronisation flip-flaps yokka kaneesam 2 dasalu cherchabaddaayi. gadiyara domainloki nemmadigaa vachhe single bitt signalnu samakaaleekarinchadam marinta gajibijigaa untundi. dheeniki saadhaaranamgaa prati gadiyara domainlo gamya domine nundi muulam domainku pratispandanato kuudina register avasaram, idhi signal kanugonabadindani suuchistumdi. itara sambhaavya clack domine crossing design lopaalu lopaalu mariyu dayta nashtam.
konni sandarbhaallo, clack gating rendu clack domainlaku daariteeyavachchu, ikkada "nemmadigaa" domine oka sekanu nundi marokadaaniki maarutundi.

