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Efficient resource utilization of FPGAs

With growing use of FPGAs it is becoming more and more crucial that how to effectively and efficiently utilize the internal resources of these devices. Normal coding techniques and synthesis tools implement every logic to a LUT based architecture. Which utilizes more area on the chip and some fast and dedicated area of the chip remain unutilized. Which in turn results in slow clock rates and bigger critical path lengths, hence the design remain inefficient in terms of both speed and area. In this paper we will present and discuss some techniques to effectively utilize the FPGA resources in order to speed up the clock rates and reduce the area utilization.