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Evaluating Device Reliability Using Wafer-level Methodology

This paper demonstrates the viability of wafer-level methods as a means of evaluating device reliability using special reliability test structures and process control monitors (PCM). The results presented illustrate how this methodology can be employed to rapidly and effectively assess the impact of process or material changes on over-all reliability. The wafer-level methodology provides a quick feedback loop for the manufacturing group enhancing their ability to continuously improve on their processes. INTRODUCTION: In the compound semiconductor manufacturing environment making changes to an existing process or material to further enhance the performance of devices is commonplace. This fluidity necessitates a methodology that quickly evaluates the effects of these changes on fundamental process reliability. The method of wafer-level accelerated lifetesting allows reliability studies in a straightforward and efficient manner. It can be accomplished on individual devices on a single wafer or on multiple devices on entire wafers. The waferlevel aspect of stressing provides a spatial map of reliability for a wafer and a single wafer can provide enough samples. Without the need for hundreds of devices and long-term lifetesting at lower temperatures this technique allows for a rapid and efficient means of evaluating device reliability. Packaging considerations are eliminated by doing these studies on wafer. This makes it easier to observe devices and do root cause analysis of the failure mechanism. The results from wafer-level lifetesting provide a firsthand look at the consequences a process or material change affects on the reliability of devices. Wafer-level studies augment existing HTOL procedures and protocols. Based on the results, a decision to expend additional resources to do complete reliability studies can be made. THE NATURE OF WAFER-LEVEL RELIABILITY STUDIES The wafer-level approach to reliability studies at TriQuint Semiconductor builds on an extensive history of reliability studies in general. A crucial aspect of utilizing wafer-level reliability studies is the ability to interpret the results against a well-defined baseline. The historical context is built on data obtained from more traditional methods such as HTOL. This knowledge helps define key elements of wafer-level lifetesting among them selecting which parameters matter, what failure criteria is acceptable and what wafer-level stresses are appropriate for these studies. Another aspect of the wafer-level methodology is the use of standard test vehicles. At TriQuint Semiconductor, the standard test vehicle includes a unique reliability test mask populated by proprietary test structures as well as process control monitor (PCM) structures. These test structures allow wider latitudes of flexibility and efficiency that is not possible when employing specific circuitry. The wafer-level methodology is most powerful when evaluating a process or material change against an established standard. This entails a careful measurement of key device parameters before and after wafer-level stress, comparing any notable shifts between the experimental and control cells. In general, the method of wafer-level lifetesting is a measure of relative reliability between a new process or material system and an established process or material system. METHODOLOGY: Wafer reliability testing involves two types of aging. Wafer-Scale Reliability (WSR) refers to reliability testing performed simultaneously on all structures contained on a whole wafer. All structures of interested are measured before the stress and once again after the stress. WSR aging is particularly applicable for whole-wafer stresses such as autoclave and temperature cycling. Wafer-Level Reliability (WLR) refers to aging tests applied to one structure at a time. An individual structure is measured and stressed and re-measured. Then, the next structure can be measured under the same stress or with different stress, so that distribution parameters and/or acceleration factors can be determined, and spatially mapped, within an individual wafer. WLR aging is particularly applicable for metal or resistor electromigration evaluations and capacitor Time Dependent Dielectric Breakdown (TDDB) studies. A. WAFER-SCALE BAKE A first-pass evaluation of device reliability involves a simple wafer-bake of wafers at 275°C. Key device parameters such as pinch-off, channel current, gate diode turn-on, breakdown voltage and gate leakage current are measured prior to and after the bake. This is done on whole wafers containing numerous devices. The bake is done in an ambient-air oven for 168 hours. This temperature is designed to cause a 20% decrease in channel current in a MESFET device as determined in a previous study [1]. CS MANTECH Conference, April 14-17, 2008, Chicago, Illinois, USA B. WAFER-SCALE AUTOCLAVE Wafer-scale autoclave is a rudimentary evaluation of device moisture sensitivity. Following JEDEC Standard Number 22, Method A102, whole wafers are autoclaved at 121°C with 100% relative humidity for 96-hours. Like wafer bake, key device parameters are measured before and after moisture exposure. C. WAFER-LEVEL ACCELERATED LIFETESTING A more in-depth characterization of device reliability includes a determination of the activation energy of a device under test (DUT). In this study, this is determined by thermally stressing individual DUTs using a specially designed reliability test structure. The test structure includes an on-wafer heating element that surrounds the DUT. The heating element utilizes a thin film resistor (TFR). Using this test structure, heating is localized around the DUT. FIGURE 1. WAFER-LEVEL ACCELERATED LIFETEST STRUCTURE. FIGURE 2. ON-WAFER HEATING ELEMENT AND DUT. This allows different DUTs on the same wafer to be stressed at different temperatures. For the results presented in this paper, the DUT was a single-gate pHEMT device. But this methodology can be implemented for any given device of interest. Figure 1 shows the proprietary reliability test structure used in this study. The on-wafer test structure is a module in a broader reliability maskset. A single wafer can provide adequate test structures for the pHEMT device. Prior to the HTOL studies, the temperature-power relationship of the heating element was characterized. By controlling the power across the heating element it is possible to stress individual devices at different temperatures. This heater also allows a feedback circuit to maintain a constant temperature around the device. Key device parameters are measured at room temperature throughout the lifetesting. This allows a careful monitoring of the over-all health of the DUT.