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Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects

We present a new structural delay test methodology that identifies small timing anomalies in dual/multi core processor circuits by comparing the relative switching time of identical circuit paths in the multiple cores. A difference in switching delay beyond the statistically observed worst case within-die timing variation indicates a defect. The proposed test is purely a comparison test between identical cores to detect manufacturing defects and does not measure absolute circuit timing. Common mode noise effects such as power supply droop, clock stretching, etc. are automatically compensated and do not impact the test results. Furthermore, the test response can be captured at multiple sample times, including faster than the rated clock period to target small delays on short paths. We present a practical approach for implementing such a test that alternately uses one core as a timing reference to test for delays in another identical core using slightly different capture clocks to allow for normal intradie parameter variations. Test results are obtained in real time without the need for any post processing. Early experimental results show good potential for this new technique.