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Towards a schedulable fault tolerant HW-SW mapping for real time systems

An important part in the design of real-time systems is the allocation and scheduling of the software tasks onto the hardware architecture. This faces the challenge of meeting deadlines, completion times, earliest start times and tolerating faults. Unfortunately, these processes are far from trivial due to the wide range of complex constraints that typically appear in real-time systems. The lack of edibility and expressive power in existing scheduling frameworks makes it difficult to model the system accurately. Moreover, the designed system must be cost-effective in terms of resource utilization which implies the need for an optimization approach. In order to tackle these deficiencies this paper proposes a schedulable fault-tolerant hardware-software mapping methodology for real time systems. The design optimization approach decides the mapping of jobs to nodes such that the timing constraints of the application are satisfied. Experimental studies show that the proposed method outperforms existing dominant work.