{'fraction_non_alphanumeric': 0.02759980285855101, 'fraction_numerical': 0.002957121734844751, 'mean_word_length': 5.655737704918033, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Hardware-accelerated MC Simulation for PDT Treatment Planning using FPGAs and GPUs

Photodynamic therapy (PDT) is an emerging treatment modality in oncology and other fields. Improvements in PDT efficacy, particularly for interstitial applications, require faster computational tools to enable efficient treatment planning beyond relying on diffusion theory and homogeneity [1]. To maximize PDT efficacy, accurate models of light propagation should be employed to account for target volume geometry and its heterogeneity. Light dosimetry plays a critical role in PDT treatment planning. For computing light dose (fluence) distribution, the Monte Carlo (MC) method is often employed due to its flexibility and accuracy. Unfortunately, MC-based models are very time-consuming, particularly for iterative optimization problems such as PDT treatment planning, highlighting the need to accelerate MC-based light dose computation. To explore this possibility, this work aims to accelerate an MC simulation for PDT, based on the widely accepted Monte Carlo for Multi-Layered media (MCML) code [2]. We demonstrate the feasibility of achieving this goal using a development platform with multiple field-programmable gate arrays (FPGAs) and another system with multiple graphics processing units (GPUs) comprising a total of 480 cores. Particularly, the GPU-based approach has gained popularity with the release of the Compute Unified Device Architecture (CUDA) [3], a C-like programming interface for NVIDIA GPUs, as it suits general-purpose applications much better than traditional GPU languages. However, the underlying NVIDIA architecture presents several unique challenges that necessitate a new approach to code optimization. Conversely, an FPGA-based approach offers greater flexibility as one has the opportunity to customize the underlying architecture to suit the application. The results for both approaches are presented and the development process will be compared to highlight the key differences between the two approaches.