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Design of optimal fast adder

The complexity in digital circuits has increased with rapid growth in technology permeating into all areas including ALU, Memory addressing, PC updates etc. All of them depend on logical elements and Adders are logic elements that play a critical role in design and performance of different operations. Thus there exists a considerable interest in digital electronics for designing high speed and low complex adder architectures. Different adders came into existence such as Carry save Adder, Carry Look-a-head Adder, and Ripple Carry Adder, Carry Select Adder etc. Carry Select adder uses multiple pairs of Ripple Carry Adder. Using Carry Select Adder (CSLA) the carry propagation delay can be reduced to a certain extent. The carry is selected in this case and the architecture is modified. CSLA is a way to improve the speed by duplicating Ripple Carry Adder (RCA), due to the fact that the carry can only be either 0 or 1. This method is based on the Conditional Sum Adder and extended to a Carry-Select Adder. CSLA uses multiple pairs of RCA with each computing the case of the one polarity of the carry-in, and the sum is obtained with a 2-1 multiplexer with the carry-in as the select signal. Parallel Prefix Adders (PPA) are used to reduce the delay caused due to carry propagation. They use carry trees wherein the delay will be in the order of log2N for an N-bit width adder. This study opted for the Ling algorithm among the many phenomenon developed on Kogge-Stone structure. The logic is to utilize and employ the property of carry propagation and generation. Using a PPA the delay will be reduced by a percentage of up to 20% of the original delay. This study is an attempt of comparing various fast adders in 45nm CMOS technology with the support of CADENCE tools. The result analysis revealed that the proposed adder is optimal when compared with various fast adders of 16 bit.