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Impact and cost of modeling memories for ATPG for partial scan designs

Automatic Test Pattern Generation (ATPG) for state-of-the-art commercial grade circuits is far more complex and requires much more engineering than for the ISCAS benchmark circuits. One among the several reasons for this increased complexity is the presence of embedded memories or register arrays in the circuit. Most ATPG research has focussed solely on algorithmic techniques for test generation disregarding much of the engineering aspects required to make automatic test generation a commercial reality. While commercial ATPG tools have provides memory simple primitives to model memories, a significant amount of expertise, research and design rule checking is required to utilize the ATPG provided primitives to usefully model memories and obtain substantial amounts of additional fault-coverage in a true partial scan industrial design of considerable size. In this paper we discuss a memory modeling methodology that shows promise and we present results to show its effectiveness in terms of increased fault-coverage.