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A high speed FPGA parameter extractor for an efficient analytical model of the submicron MOS transistor

A new and original high speed FPGA architecture for the parameter extractor of an analytical model of the sub micron MOS transistor is proposed. The architecture is based on the Levenberg-Marquardt optimization algorithm. Experimental results validate the performance and accuracy of parameter extraction for the model used, for characteristics measured on several transistor types of different aspect ratios. The parameter extraction is accomplished in under 3.5 ms per device and is precise over an extended biasing range. This FPGA extractor is very useful for any technology engineer in need of quick and accurate evaluation of a new technology node.