{'fraction_non_alphanumeric': 0.02368421052631579, 'fraction_numerical': 0.0021929824561403508, 'mean_word_length': 4.955613577023499, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Physics and Design of SOI FED Based Memory Cells

Memory arrays occupy a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory (6T-SRAM) and the single transistor dynamic random access memory (DRAM) cells both suffer from excessive leakage current. Therefore, there is a widely recognized need for urgent progress in memory technology to meet the increasing demand for highly for compact, high density and low power memory arrays. Several new memory device approaches are currently under extensive investigation around the world. One such approach is the thin capacitively coupled thyristor (TCCT) memory cell where a gate assisted PNPN thyristor is utilized as a memory cell, which exploits the ON and the OFF states of the thyristor. TCCT breaks through the performance density trade-off of conventional SRAM and DRAM and it is compatible with CMOS process which make it a promising alternative to the current memory cells. In this thesis we present a new volatile memory cell with promising characteristics, which improves on the TCCT concept above. The proposed cell is based on the field effect diode (FED), and it is essentially a p-i-n diode to which two closely spaced, independent gates have been added between the anode and the cathode. This new cell is similar to the TCCT in concept and operation, however, the thyristor-like structure is gate-induced in the FED cell whereas it is built-in in the TCCT cell. TCAD simulation results showed that the FED cell has important advantages such as high read 0/1 margins, fast write/read, thermal stability and good retention time. We also re-evaluate the recent interpretation of the physical storage mechanism of the thyristor based memories as the presence (state “1”) or absence (state “0”) of charge under the gate: we demonstrate that this interpretation is incorrect, and we describe the correct physical mechanism, by carefully studying the carrier profiles within the TCCT and FED memory cell structures. This new understanding should result in better cell design and feasibility analysis. A copy of this doctoral dissertation is on reserve at the Johnson Center Library.