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Research and Implementation of the Visual Location Algorithm Based on FPGA

Aiming at the problem that the traditional placement machine adopts mechanical claw to grab the patch element, which is easy to damage, slow speed and poor applicability, and combined with the advantages of FPGA high-speed parallel computing, a FPGA placement algorithm is proposed. It analyzes and studies the PCB MARK point recognition, to achieve accelerated algorithm based on FPGA placement heads localization algorithm, and using a single instruction stream algorithms. Experiments show that, compared with the traditional host computer algorithm, the algorithm further improves the positioning accuracy, and in the case of ensuring the accuracy, greatly reduce the positioning time, the placement speed of up to 5000 chip/ h, the patch accuracy of±0.02mm.