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Towards a mixed NoC/AFDX architecture for avionics applications

An heterogeneous network, where a switched-Ethernet backbone, as AFDX, interconnects several End Systems based on Network-On-Chip (NoC), is a promising candidate to build new avionics architecture. However, current avionics End System includes many functions, as performing a traffic shaping for each Virtual Link (VL) and scheduling the output frames in such a way the jitter on each VL is bounded. This paper describes how the NoC implements these functions in order to compute the worst-case traversal time (WCTT) of avionics frames on a NoC to reach the AFDX network. Besides, we illustrate the problem of guaranteeing a bounded jitter at the output of a NoC. We show that the existing mapping strategies present some limitations to reduce the congestion on the outgoing I/O flows (i.e. going from the NoC to the AFDX network) and so do not reduce the jitter on a given VL. We propose an extended mapping approach which considers the outgoing I/O flows. Experimental results on realistic avionics case studies show significant improvements of the jitter value.