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A 90-nm CMOS V-Band Low-Power Image-Reject Receiver Front-End With High-Speed Auto-Wake-Up and Gain Controls

A low-power auto-wake-up image-reject receiver front-end in 90-nm CMOS technology is presented for V-band applications. The proposed front-end generally operates in the sleep mode and consumes 19 mW. When an RF signal greater than -50 dBm is received, the front-end wakes up automatically and enters into the active mode consuming only 46-mW power. Adjustable linearity (IP1dB) of the front-end is provided by changing two gain modes (high- and low-gain modes). When input RF power is higher than -30 dBm, IP1dB will be improved (from high-gain mode to low-gain mode). Experiments show IP1dB of -25.2 and -22.5 dBm in high- and low-gain modes, respectively. An image-reject ratio greater than 32 dB is measured when using the proposed image-reject mixer topology. All passive phase-shift couplers for realizing the image-rejection are composed of standard CMOS lumped elements, thereby considerably reducing the chip size (0.82 mm 2).