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New Built-In Self-Test Scheme for SoC Interconnect

Interconnect testing in a SoC environment is a new area of research. It represents a further development of traditional board-level testing with respect to the new interconnect paradigm, new fault models, and required high level of autonomy. This article analyzes available interconnect self-test solutions and comes up with a new BIST scheme for at-speed testing of SoC interconnect. We adapt a recently proposed very efficient architecture of test pattern generation and response analysis hardware and demonstrate advantages of this new testing paradigm over other known methods. It is shown that this brings a high level of universality, scalability, and configuration independence into at-speed testing and diagnosis of SoC interconnects. The framework allows detection and precise diagnosis of both static and dynamic faults.