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Reducing Shift Cycles and Test Power using Linear Feedforward Network

A scheme is proposed for inserting a linear feedforward network composed of XOR gates in scan chains. The proposed scheme reduces scan-in, scan-out, and scan clocking power by reducing the number of shift cycles required to load test patterns into scan chains. Reducing shift cycles also contributes to test time and test storage reduction. After inserting the linear feedforward network, the corresponding test stimulus and test response are obtained by solving linear equations for the specified bits. Using the feedforward XOR gates, the number of shift cycles can be reduced significantly with relatively small hardware overhead. The proposed scheme can be used in standard scan architectures as well as in conjunction with other test data compression techniques. Because it can preserve many of the X's in the test cubes, it is very efficient when used with linear expansion schemes to reduce power significantly.