{'fraction_non_alphanumeric': 0.02131979695431472, 'fraction_numerical': 0.005076142131979695, 'mean_word_length': 5.4868421052631575, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
General Multicarrier Modulation Hardware Accelerator for the Internet of Things

General frequency division multiplexing (GFDM) provides a proven approach for a flexible physical layer implementation in wireless communication systems. However, this flexibility requires additional processing steps within the critical system path, the hybrid automatic repeat request. This is especially critical for devices of the Internet of Things, which have a very small power footprint. To tackle this problem, we present a data mapping that allows efficient parallel computation of the GFDM algorithm by a standard Harvard CPU architecture. To utilize the new mapping, we derive semi-custom processor configurations based on fixed-point arithmetic, which achieve a throughput close to the theoretical bound. In comparison with a custom FPGA implementation, we deliver 9 percent of the throughput, while only consuming 0.1 percent of the power. Thus, we achieve 14 times higher energy efficiency.