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Implementation of an RTL synthesizable asynchronous FIFO for conveying data by avoiding actual data movement via FIFO

An enhanced approach of integrating asynchronous design is thoroughly adapted into the conventional synchronous flow design to avoid problems like critical delays, clock skew or power consumption control. This feature comes as an outcome of accepting Verilog models, thereby allowing the logical synthesis and functional verification of the design based on the RTL synthesis. The modified pipeline design followed in this paper are based on asynchronous nature which exhibits an exceptional dynamic feature of being a latch-less in control operations, thus with proper sequencing can achieve the implied latching functionality of the dynamic gates. This work analyses the performance evaluation of asynchronous and synchronous design topologies of FIFO been constructed based on a scheme where data movement is avoided in the FIFO. This work is implemented and synthesized in register-transfer-level (RTL) using Verilog alongside few sequential latches and digital logic gates and simulation is done at the gate-level using Xilinx-ISE 12.1 tool to deliver delay and power for the same, together with simple and easy integration in advance design flows and processes.