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Design of a DBN Hardware Accelerator for Handwritten Digit Recognitions

With the development of artificial intelligence, researches on speech recognition and deep learning become increasingly popular. In this paper, the deep belief network (DBN) hardware accelerator for handwritten digit recognition was implemented in TSMC 90nm CMOS process. Addition, the MNIST database is used as a functional verification for the proposed hardware architecture, and the accuracy of the proposed design is 97.3%. The gate count of the proposed design is 1,160k, and power consumption is 353mW at 73.6MHz. The energy efficiency of the proposed design is 1.7337GOPs/W.