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Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing

A soft/write-error-resilient nonvolatile flip-flop (NVFF) using three-terminal magnetic tunnel junctions (MTJs) is presented. The proposed NVFF exploits a redundant structure with a majority bit implicitly stored, which is tolerant to soft errors including both single-event transients (SETs) and single-event upsets (SEUs). For write-error resilience, all the bits of the redundant MTJs are written using the majority bit with a shared write-current path, exhibiting 1-bit soft-error correction and 1-bit write-error masking. In addition, the shared writing scheme reduces the number of write-current paths to one-third of that with a redundant NVFF with 1-bit soft/write-error masking. Using 65 nm CMOS/MTJ technologies, the proposed NVFF achieves a few orders-of-magnitude reduction in the failure in time (FIT), a 31% reduction in the transistor count, and a 65% reduction in the write energy in comparison with the redundant NVFF.