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Integration and Verification of IP Cores on SoC

As predicted by Moore's law, due to the shrinking transistor sizes, the density of ICs in a chip has increased exponentially and the VLSI trends have seen a sudden drift from computation-based cores to communication-based cores. As a result, the primary challenge in SoC design is to efficiently integrate all IP cores while maintaining their ability to perform their specific functions and communicate with one another, and the quality of integration must be verified at the SoC level, which confirms the same. The paper showcases the design of the various IP Cores such as interface controller block, PCIe block, Ethernet block, throttle and pipeline blocks, and various protocols used to transfer information between the cores via Network-on-Chip. It also explains the process of verification of the SoC design using Universal Verification Methodology(UVM). The IP Cores were integrated with no errors, zero undriven inputs ports and multi-driven ports. The developed test cases for verification were found to achieve a 100% pass after subsequent runs on the SoC. Additionally, the use of UVM helped to achieve a functional coverage of 88.35%, which is seen to be higher than coverage achieved in the absence of UVM.