{'fraction_non_alphanumeric': 0.016268260292164674, 'fraction_numerical': 0.0, 'mean_word_length': 5.50755939524838, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Hardware synthesis and analysis of control-intensive designs from high level specifications

The goal of high level synthesis is to automate the synthesis of a VLSI circuit from its algorithmic description. Successful high level synthesis methodologies exist for arithmetic-intensive designs. This dissertation targets issues in synthesis of control-intensive designs which may contain nested conditional statements and nested loops. Major tasks in high level synthesis include allocation, scheduling, assignment, and register transfer level (RTL) circuit generation. The objective of performing these tasks efficiently is to produce circuits optimized for cost functions such as delay, area and testability. 
The time required to execute the algorithmic specification by the synthesized circuit is a product of the number of clock cycles required to execute the specification and the clock period of the circuit. We propose techniques which target efficient scheduling of operations in loops to minimize the number of clock cycles required to execute the specification (algorithm LDS). To produce circuits with a small clock period, traditional techniques use more resources or faster resources. We demonstrate that even when the resource allocation is fixed, the clock period of the circuit can be minimized using assignment techniques (algorithm ClkMin). 
An RTL circuit is generated following the scheduling and assignment phases. The RTL designs produced may not be optimized for area, and may not be completely testable at the gate level. We propose a general methodology to generate RTL designs optimized for area which uses the hierarchy of the RTL design and the interaction between control and data path (algorithm WONDER). The optimized RTL circuits are completely testable under full-scan at the gate level. 
In general, there may be multiple solutions to the scheduling, assignment and RTL generation tasks. Hence fast and accurate estimation tools are essential to evaluate the quality of different possible implementations. Good techniques exist for area estimation. In this dissertation, we develop efficient techniques for estimating the number of clock cycles required to execute a specification and the clock period of the implementation. We apply Markov chain techniques for computing the expected number of clock cycles required by a schedule to execute the complete algorithmic specification for various possible inputs (algorithm PERSIS). The clock period estimation technique uses high level information about scheduling and assignment to compute the true delay as opposed to the topological delay of the implementation (algorithm FEST). 
The algorithms developed in this dissertation have been integrated in the SECONDS high level synthesis system. SECONDS has successfully produced circuit descriptions from control-intensive algorithmic specifications. Experiments with SECONDS demonstrate that high level synthesis can create competitive designs but reduces design time significantly.