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FPGA in The Loop Based Single Phase Power Factor Correction

The aim from this work is to invest the interest of using hardware solutions such as FPGAs for the digital implementation of control algorithms of Power factor correction converter. For this reason, a methodical approach based on an appropriate design methodology is firstly presented and discussed. An FPGA in the loop control for the PFC was done using Matlab, Altera Quartus II, and Altera DE1-SoC FPGA. The FIL test was performed to examine the PFC control with a hardware solution. In the FPGA in the loop (FIL) approach, the control algorithm is running in real time as the hardware. In the other hand, the controlled system and its components are simulated in Matlab environment. This technique combines between the software flexibility with real-time accuracy and hardware speed execution, in this paper, an FPGA in the loop control for the single-phase boost power factor corrector conditioner was performed to examine the PFC control with a Hardware solution. The main purpose of this research is the investigation of the hardware solution control technic applied on PFC converter.