{'fraction_non_alphanumeric': 0.022339027595269383, 'fraction_numerical': 0.001314060446780552, 'mean_word_length': 5.145161290322581, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Integration of Hardware Assertions in Systems-on-Chip

Assertions in silicon help post-silicon debug by providing observability of internal properties within a system which are otherwise hard to observe. Besides generating synthesizable assertions, they also need to be integrated in a design. In this paper we have shown how hardware assertions can be integrated in existing on-chip debug infrastructures, i.e., in a scan-based run-stop debug infrastructure and in a debug trace infrastructure. Experimental results on an industrial test SoC show that assertion based bus protocol checkers can be integrated with less than 1% additional area cost, including both the hardware assertions and the additional logic required to integrate the assertions in the SoC.