About memory(RAM and Flash) usage in MPC5748G

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About memory(RAM and Flash) usage in MPC5748G

Contributor I

Hi, I have some issues at MPC5748G memory.

I use MPC5748G motherboard.

[Question 1]

For two cores' shared variable, I used shared RAM. (I modified linker files)


Then, for the test, I make simple LED ON code.


What is really strange is that the GPDO [99] LED (core 2) is on but the GPDO [98] LED (core 1) is not on.

GPDO[99] LED is on -> shared RAM address 0x400B8024 contain value 0x00000001.

Core 1 checks the value of 0x400B8024 address. The value is 0x00000001 but GPDO[98] LED is not on.

Why this issue happens?

Can not two cores access RAM at the same time?

How can I fix that issue?

I attached my test project file.

[Question 2]

Is it possible two cores access RAM and Flash at the same time?

For example, 

Core 1 write the RAM memory some values. At the same time, core 2 write Flash memory some values.

I am not sure that the action is possible When I saw the block diagram.


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NXP TechSupport
NXP TechSupport


this is copied from the reference manual, Crossbar Switch section:


If two masters are going to access a slave at the same cycle then priority takes effect. Higher priority is served first and then the low priority is served. If a slave is already occupied at that time, current access is finished and then another one starts.

And yes, two masters can access two slaves at the same time.

So, everything is managed in predictable way.

In case of shared resources, it's usually needed to ensure coherent access. Semaphores are used for this purpose. You can find simple example here:

Example MPC5775K Semaphores S32DS_1.0 

Your example does not work due to data cache. The area for shared RAM memory should be configured as cache inhibited. Or you would have to invalidate the cache each time when accessing this area but that's not efficient. You can use SMPU module to configure that area as cache inhibited. Here are some examples for SMPU configuration:



You can quite easily modify it for your purpose.

Another option (rather for test purposes to not lose the performance) is to disable the data cache.



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