A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator
Oliver Bause Paul Palomero Bernardo Oliver Bringmann


Framework for Polarized Magnetic Neutron Scattering from Nanoparticle Assemblies with Vortex-Type Spin Textures
    Andreas Michels
    April 29, 2024
===============================================================================================================





§ INTRODUCTION

In recent years, machine learning has revolutionized various fields including video, sound, and language processing. dnn can learn and recognize complex patterns in data by building a hierarchy of increasingly complex features, starting from simple edge detection and progressing to more abstract concepts like object recognition <cit.>. In embedded systems, hardware accelerators can greatly improve the required runtime of dnn. These accelerators are specialized hardware modules designed to speed up the highly parallel mathematical operations of running neural networks. This can be particularly useful in areas where resources are limited and the ability to run dnn efficiently is crucial. The cpu of a mc cannot efficiently perform the processing of these data-parallel networks as they utilize only a few cores. Additionally, their broad instruction set will not be used since neural networks often require basic arithmetic operations. Therefore, a growing number of specialized hardware accelerators are being developed <cit.>. Requirements for accelerators include small chip size, low power consumption, and implementation of a memory interface that minimizes the number of expensive accesses to the off-chip memory <cit.>.

The development of a suitable on-chip memory hierarchy is particularly important because the required memory occupies a large portion of the total chip area and is responsible for a major part of the accelerator’s energy consumption. Thus, a trade-off must be found toward determining the minimal capacity required to maximize the accelerator’s performance and throughput. Developing and evaluating different designs is time-consuming. The sheer size of the design space itself renders it practically impossible to manually test all possible configurations, which can result in potentially superior memory architectures being passed over. Thus, assisting the engineer to explore and evaluate a larger portion of the available design space more easily and quickly could improve the implemented architecture and simultaneously reduce development time.

In this paper, we introduce a configurable memory framework that can semi-automatically generate and test an efficient memory hierarchy with multiple hierarchy levels and banks, different memory macros, and a pattern-based prefetching algorithm. Loop analyses of neural networks are used to determine their memory accesses and create possible framework configurations. The resulting simulation and synthesis reports can be used by engineers to select the most suitable memory hierarchy for their application. 




§ RELATED WORK

In the area of neural network accelerator design, the optimization of memory structures is a critical consideration, given their substantial impact on both area and power requirements. To support designers, dse tools were developed. They utilize high level system models to evaluate different design options, like different memory configurations or type and amount of processing units. The automated search of the enormous available design space can accelerate the development time while simultaneously improving the final design in regard of chip area, power consumption, and production costs <cit.>. The dse tool ZigZag <cit.> stands out for its systematic approach to exploring the design space, with a specific emphasis on memory architectures. By enabling efficient evaluation of diverse memory configurations, it facilitates the identification of optimal choices that strike a delicate balance between performance and resource utilization.

However, ZigZag does not provide a hardware implementation of the found memory hierarchies, which is a crucial step when aiming for accurate performance, power, and area measures and the ability for fast prototyping in existing rtl designs.

Complementary to ZigZag, other works contribute valuable insights into memory optimization techniques tailored to the specific requirements of neural network workloads. For instance, <cit.>, <cit.>, and <cit.> delve into strategies such as weight pruning, quantization, memory compression, and minimizing off-chip memory accesses. These techniques aim to reduce the memory footprint while preserving the accuracy of neural network models, thereby addressing the challenges posed by limited resources in hardware accelerators.




§ EMBEDDED MEMORIES

Memory has always been a major aspect of the development of computing systems. However, especially the performance of non-volatile memories is usually several orders of magnitude slower than that of the dpu, thus increasing the dependence of the overall system performance on memory-access optimization. As a result, the most efficient utilization of memory should always be taken into account in the development of applications and hardware, respectively.

Memory architectures can easily take up more than 60% of the entire soc chip area. Therefore, they are also responsible for a huge fraction of the total power consumption. Embedded systems mostly have strict requirements in terms of size, power, and cost. Thus, the goal is to reduce production costs and avoid heat generation which could result in performance deterioration, possible hardware damage, and shortened battery life <cit.>.

sram play a crucial role in the proposed memory hierarchy framework, serving as integral components in the memory architecture. sram, characterized by their ability to retain stored information without the need for periodic refreshing, contribute to the framework's efficiency and speed. Their utilization in the memory hierarchy enables rapid access and retrieval of data within one clock cycle <cit.>.



 §.§ Memory Requirements

A dnn has multiple types of data to store: features, weights, and intermediate results. The maximum and current size of these data types highly depends on the architectural design and data flow of the neural network. The resulting storage requirements of the features and weights from common neural networks like tcresnet <cit.> and AlexNet <cit.> can range from only 64 to more than 500, respectively. Therefore, dnn hardware accelerators often utilize small on-chip memories and only load the currently needed subset of data from a larger off-chip memory. However, these off-chip memory accesses are time-consuming and require up to two orders of magnitude more energy than the on-chip memory accesses. 

Siu et al. <cit.> concluded, that the peak memory requirements are often dominated by only a few convolutional layers.
As a result, it may be reasonable to tailor the on-chip memory architecture towards the average memory requirements.
The consequent loss in performance can be justified by the substantial reduction in chip area and energy requirements.



 §.§ Memory Access Pattern


dnn are commonly trained and executed on parallel architectures like 2D systolic arrays, simd, or mimd compute units. Each approach has its benefits and drawbacks. 2D systolic arrays, as an example, are dedicated dpu performing static functions, enabling them to require very little chip area. However, the array offers almost no flexibility. The instruction cannot be changed after the synthesis and individual dpu cannot be stalled <cit.>.

Nevertheless, all architectures need several data words for each clock cycle, which have to be loaded from memory beforehand. Depending on the dnn's data flow and layer mapping onto the target hardware, different memory access patterns can occur. This paper will focus on the patterns shown in Figure <ref>, that are classified as inspired by Byunghyun et al.'s research <cit.>.

	
  a) Sequential: The data is stored in the memory on successive addresses and accessed sequentially starting from a base address. Every address is accessed exactly once, whereby there is no data reuse.
	
  b) Cyclic: The cyclic pattern has a defined cycle length l. Like the sequential pattern, data is accessed at successive addresses in the memory, but after loading l data words, the pattern returns to the base address and starts again. Therefore, the pattern accesses a constant data stream and if the memory architecture can buffer the whole cycle, the data from every off-chip memory address will only be read once.
	
  c) Shifted cyclic or overlapping: The shifted cyclic pattern is an extension of the cyclic pattern with the addition that, after the completion of each cycle, the base address will be shifted by some constant s. As a result, the individual cycles are overlapping and a portion of the required data has already been loaded in a previous cycle, the rest has to be preloaded.
	
  d) Strided: In contrast to the previous patterns, data in a strided pattern is not stored at successive memory addresses, but have a constant offset from each other. The data of addresses in between is not requested and thus skipped. Note that it is possible to combine this pattern with the (shifted) cyclic pattern.
	
  e) Pseudo-random: In the pseudo-random access pattern, non pre-calculable addresses are accessed. A determination of the next targeted addresses is hardly possible, if at all.
    
  f) Parallel-shifted cyclic: The access pattern can also consist of multiple simple patterns, that are executed in parallel or are nested within each other. The parallel-shifted cyclic pattern, for example, involves several shifted cyclic patterns that switches to the next pattern after one cycle. Only after all patterns have run through one cycle each, the outer pattern returns to the first shifted-cyclic pattern and executes the shift of each nested pattern.





§ DESIGN CONCEPT OF THE MEMORY FRAMEWORK

The design concept of the memory framework was derived from the goal to minimize the memory footprint of an accelerator's memory modules. The memory requirements regarding power consumption, chip area, capacity, and throughput are tightly coupled to the data flow through the accelerator and its use-case. A high data reuse percentage decreases the number of expensive off-chip memory accesses. However, depending on the data access pattern, the needed storage requirements to achieve a higher data reuse rate can grow significantly. As a result, the chip area and energy consumption will increase. Therefore, an optimal co-design between the network’s data flow and
available hardware configurations must be found.

The design space of hardware accelerators, however, has reached an extent, that is no longer manually explorable. Engineers have a large degree of freedom in adjusting data flow and selecting the right hardware components so that dse tools are needed to support and accelerate the design process. However, they mostly only utilize single sram or dram modules, but the integration of a memory hierarchy could increase performance, lower chip area and energy consumption, or a trade-off between both <cit.>.



 §.§ Architecture

The memory framework offers a highly parameterized and runtime-adjustable SystemVerilog template.
It is specialized for the deployment within neural network hardware accelerators and could be integrated into existing dse tools.

The parameters include:

    
  * Off-chip interface: The off-chip data width is needed to initiate the data input port. Additionally, the address width will be used to generate valid off-chip read requests.
    
  * Hierarchy depth: The number of generated hierarchy levels can range from one to five.
    
  * Hierarchy level configuration: Each hierarchy level is configured independently. The settings for each level include the memory macro name, the number of banks, the word width and RAM depth of the given macro, and whether the memory module is single- or dual-ported.
    
  * osr: If the osr is enabled, the bit width of the shift register and a list of available shifts have to be defined.






Figure <ref> illustrates an exemplary memory framework configuration with two hierarchy levels. All memory modules are fully controlled by the on-chip mcu.
The controller activates memory modules, adjusts read and write addresses of each module according to the currently selected access pattern and, most importantly, ensures data integrity and correctness within the whole hierarchy.
To preload data from the off-chip memory, an interface will request data from the global address space and buffer the incoming data stream.
The input buffer and interface are also controlled by the mcu.
To support even more access patterns efficiently, the memory framework has an optional powerful osr.
It is a register file located between the last hierarchy level and the accelerator's processing units.
The osr buffers data one last time and performs customizable, non-unit shifts.
The memory hierarchy can be controlled fully by an off-chip mc or partly by the accelerator.



  §.§.§ Input Buffer

The data words received from the off-chip memory undergo temporary buffering in the input buffer before being stored in the memory hierarchy.
This addresses three key challenges.
The primary challenge arises from potential clock mismatches between the accelerator and the connected mc <cit.>.
The input buffer is clocked by the mc's clock source.
This ensures synchronization between the input buffer and the off-chip mc and prevents communication failures.
A handshake protocol is utilized to enable data transfer from the input buffer to the first hierarchy level.

Second, the input buffer aligns the incoming data stream for the hierarchy.
The buffer is a register file with the same word width as the first level of the hierarchy.
If the off-chip architecture has a smaller word width, the input buffer will hold multiple words before passing them to the hierarchy.
This optimizes memory efficiency and reduces the write load on the first level.

Lastly, the input buffer prevents potential blocking of the off-chip memory during data storage in the hierarchy, enhancing overall system performance by allowing the mc to manage other tasks.
This dynamic buffering process ensures a smooth and synchronized flow of data, promoting stable communication between different clock domains and optimizing the use of memory resources.



  §.§.§ Memory Hierarchy

The memory hierarchy, storing requested data words from the off-chip memory, is fully configurable with one to five levels. Each level can utilize different memory modules, macros, and types. In Figure <ref>, level 0 is closest to the off-chip memory, forming the initial data pass-through point, while each subsequent level follows in the data flow. This nomenclature, contrary to traditional cpu cache architectures, is a consequence of the data-flow-driven design. Unlike standard cpu designs, hardware accelerators' predetermined data accesses render traditional caching strategies obsolete.

Each level of the hierarchy can feature one or two banks for data storage.
Dual-banked levels with single-ported memory modules strike a balance between performance and chip area.
However, both banks must utilize the same memory module.
The framework optimizes the virtual address space to evenly distribute the load between banks, minimizing the risk of simultaneous read and write attempts to the same single-ported bank.
In this use case, two single-ported memory banks are used to emulate a single dual-ported memory module.
Therefore, it is not reasonable to use more than two banks in a hierarchy level.
A maximum of one word can be written and read simultaneously per level in one clock cycle.
A more dynamic implementation, allowing multiple simultaneous reads and writes, would require significantly more chip area and power, which would defeat the purpose of the framework.

Additionally, to prevent system failures, the framework ensures that dual-ported memory modules do not access the same address with both ports simultaneously. If multiple levels are configured, all data must traverse each level, simplifying control mechanisms at the expense of a minor initialization phase. Note, that higher levels do not retain subsets of data from lower levels. They instantly clear memory space after the last specified pattern read was executed to expedite loading new data.



  §.§.§ Memory Control Unit

The mcu controls the framework from the data retrieval from the off-chip memory to the output of the last memory hierarchy level.
Furthermore, it calculates memory accesses of the selected pattern and ensures data integrity throughout the hierarchy’s runtime.



The accelerator's clock source may operate at a different frequency than the external clock source, necessitating the implementation of synchronizers for bidirectional communication across the cdc.
The buffer full control signal and the data bus from the input buffer to the first hierarchy level must be synchronized to the accelerator's clock domain.
This involves holding the signal for at least an entire cycle to ensure stability in the slower domain and preventing metastability.
Metastability refers to a transient state where the output of a circuit is undetermined, leading to potential glitches and unpredictable behavior.
Additionally, challenges arise from the uncertainty regarding the number of cycles needed by the hierarchy to store its content, stemming from conflicts in bank access and RAM availability.
Figure <ref> presents the handshake mechanism to synchronize communication between both clock domains.
The buffer full signals the memory controller, that data is available to be written into the first hierarchy level.
After the write is complete, the memory controller sends a reset signal to the buffer controller.



  §.§.§ Pattern Selection and Calculation




The mcu executes the currently selected pattern which can be altered during a reset cycle.
The ports are described in Table <ref>.
The pattern management within the mcu facilitates the creation of diverse cyclic, overlapping, and sequential patterns.
The starting point in the off-chip address space from which the memory hierarchy will request data from, can be configured by either an absolute or relative address.
The cycle length signifies the pattern iteration's length, where accessing the cycle length-th element leads to a cyclical return to the first one.
To augment pattern flexibility, the inter-cycle shift introduces a customizable shift activated after skip shift cycle completions.
However, the framework lacks runtime input validation, entrusting the engineer with the responsibility of understanding and aligning chosen parameters with the accelerator's architecture.
This design choice, avoiding runtime verification, is a deliberate trade-off to prevent unnecessary increases in chip area and power consumption, emphasizing the need for careful parameter selection and alignment with the overall architecture.





The mcu manages the pattern state and controls memory accesses by using internal registers. 
These registers can be reset, facilitating the initiation of a new pattern.
Each hierarchy level, except the last, follows a consistent calculation process shown in Listing <ref>, with minor adjustments for level-specific settings.
Before a hierarchy level outputs data, it must be loaded from the input buffer or the preceding level (line 7-14).
Internal pointers manage the writing address, ensuring systematic loading.
A pattern and an offset pointer are used to calculate the next address to be read from (l. 31).
After each completed cycle, the pattern pointer will be reset and the offset pointer will be adjusted according to the selected inter-cycle shift (l. 20-28).
As illustrated in Figure <ref>, the mcu only activates a write cycle, after the preceding level executed a read cycle.
A write-over-read policy prevents deadlocks of single-ported memories within the hierarchy.
Since a write needs an active read in the preceding level, the mcu can at most activate the write mode every two clock cycles.
The last hierarchy level, positioned closest to the processing units, employs a dual-ported memory module for optimal performance.
The disable output control signal stalls data output, allowing efficient data preloading and preventing premature outputs.




  §.§.§ Output Shift Register

The osr, an optional register file positioned between the memory hierarchy and the accelerator's processing units, boasts a fully configurable bit width that can surpass that of the last hierarchy level. This flexibility enables the osr to store multiple words concurrently. Operating on each clock cycle, the osr executes a left shift operation and, with sufficient register space, requests the next data word from the hierarchy. The osr's flexibility extends to configurable shifts during runtime, controlled by the mc. However, it's essential to consider that shifts exceeding the bit width of the last hierarchy level can be impractical, as the memory module requires multiple cycles to fill the osr, while the register could perform a shift every cycle. Furthermore, each additional available shift width contributes to increased chip size and energy consumption.




§ RESULTS



 §.§ Verification

The functional verification and simulation of the memory hierarchy written in SystemVerilog was realized using cocotb <cit.>. A Python model replicates the framework's functionality. Comprising an input buffer, multi-level storage hierarchy, and an osr, the class utilizes the bitstring module <cit.> as back-end to efficiently support arbitrary word widths. The input buffer and osr consist of individual bitstrings with configured bit width, while the memory hierarchy employs an array of bitstrings for each level, mirroring the combined RAM depth of all banks in a given level. During initialization, the model validates parameters, ensuring a valid configuration, and initializes components like the input buffer, memory hierarchy, osr, and state variables. To accommodate different patterns or test cases, a new model instance can be initialized for each test, preventing interference from previous ones.

The model allows customization of the memory access pattern through an interface similar to the dut. The pattern configuration is validated, catching invalid configurations that might lead to unknown system states. Pattern execution involves the two phases data insertion and retrieval. The model handles the off-chip data stream independently, transforming each new data word into a bitstring and storing it in the input buffer. Upon buffer fullness, the content is written into the array representing the first hierarchy level. Unused entries are promptly cleared to avoid data loss. The model's output and general behavior are updated selectively, reflecting only the design's external behavior.



 §.§ Performance Analysis



  §.§.§ Increasing Cycle Lengths


The memory framework aims to match the best-case performance of a standard sram memory, targeting a data word output in every clock cycle. Three configurations were tested with increasing cycle lengths from 8 to 1,024, utilizing the same 1,024-word capacity for hierarchy level 0. However, level 1 had varying RAM depths: 32, 128, or 512 words. Tests were conducted both with and without data preloading. As shown in Figure <ref>, performance notably decreases after the cycle length surpasses the storage capacity of level 1, doubling the runtime due to internal data word replacement in a round-robin fashion and a write cycle limitation of every two cycles. Cycle lengths beyond level 1 capacity, larger memory hardly improves performance, with all hierarchies requiring similar clock cycles to complete the longest cyclic pattern. Preloading data enhances performance, as demonstrated by a 21% decrease in clock cycles needed for the configuration with a 512 RAM depth level 1, emphasizing the potential for runtime optimization during pattern execution.



  §.§.§ Equal Capacity at Different Word Widths




The second test case contrasts two memory frameworks, both having equal bit capacities. The first hierarchy, with a 32-bit word width, features RAM depths of 512 and 128 words for levels 0 and 1, respectively. In contrast, the second hierarchy adopts a 128-bit word width with shallower RAM depths of 128 and 32 words for the same levels and includes an osr to output 32-bit words. Figure <ref> depicts the clock cycles required to generate 5,000 outputs across varying cycle lengths. The first hierarchy mirrors the previous test case, doubling its clock cycles beyond a cycle length of 128 words. However, the second hierarchy, with a wider word width, consistently performs optimally throughout all cycle lengths, copying four 32-bit words per write cycle. Although this wider word width significantly increases hierarchy costs, as evident in Figure <ref>, doubling the required chip area from 7566^2 to 15202^2, it also incurs a higher energy consumption of 0.31, nearly 2.5 times more than the 32-bit architecture.



  §.§.§ Impact of the Inter-Cycle Shifts


The performance impact of the inter-cycle shift on the memory framework was evaluated using configurations with two hierarchy levels. Both levels had a 32-bit word width, with level 0 and level 1 having RAM depths of 512 and 128 words, respectively. One configuration utilized a single-ported memory for level 0, while the second configuration employed a dual-ported module. Despite sharing the same pattern selections, the test revealed notable differences in throughput. Figure <ref> displays results for increasing inter-cycle shifts at static cycle lengths, indicating optimal throughput when the inter-cycle shift is less than one-third of the cycle length. However, performance decreases significantly with larger inter-cycle shifts, reaching the worst-case scenario with an output every three clock cycles when the inter-cycle shift equals the cycle length. The dual-ported design delays this performance decline but doesn't improve the worst-case scenario. In cases requiring data reloading from off-chip memory, the bottleneck is the single-ported memory module in level 0, affecting throughput and synchronization with the input buffer. The dual-ported level 0 enhances performance at larger inter-cycle shifts with minimal additional chip area, as depicted in Figure <ref>. However, the power consumption increases by 130%, emphasizing the need to balance performance gains with energy requirements in the final design.



 §.§ Case Study


To analyze the capabilities of the memory framework, a case study was performed with the low power hardware accelerator UltraTrail <cit.>.
It is trained for kws to classify a subset of the Google speech commands data set and utilized a TC-ResNet model.
The accelerator is standardly equipped with 64 mac units arranged in an 8 × 8 array.
Therefore, it is desirable to unroll the loop nests of the dnn layers in a fashion to maximize the utilization of the processing units.
The memory access patterns of the weight and input data sets of all feasible unrollings were analyzed.

Each convolutional layer can be unrolled along its factors batch size N, number of groups G, number of output channels K, number of input channels C, width of input channel X, and filter width F.
However, since the accelerator's data flow is mostly static, each layer must be unrolled along the same factors.
The resulting memory traces of the selected unrolling can be analyzed to determine performance predictions.
To optimize the runtime needed to execute the dnn, a high average data-parallelism should be possible within all layers with the given unrolling.
Otherwise, the utilization of the mac array will be low.
Additionally, the number of unique data words per loop step needs to be considered as they dictate the required port width of the data set.
Wide ports complicate routing of the chip and possibly require multiple memory banks to support the word widths.
Finally, the memory access pattern can be evaluated using the memory traces.
Complex nested patterns with a low data reuse rate should be avoided as they need to utilize a larger memory hierarchy to support their difficult memory accesses.

The weight data sets exhibit a sequential pattern, allowing a single-level, small memory hierarchy to efficiently handle the access pattern, minimizing capacity needs and chip area. In contrast, the input data sets, with more intricate patterns depending on loop unrolling and layer, may require multiple levels. Some unrolling scenarios currently lack mcu support, necessitating the storage of complete nested patterns, significantly increasing capacity requirements. Under worst case conditions, data from a single off-chip address must be stored several times in the hierarchy, highlighting the challenge of efficiently managing complex input patterns. If parallel access patterns were supported, a more optimized memory configuration could be employed, potentially reducing chip area and power consumption.



  §.§.§ Memory Hierarchy compared to Dual-ported SRAMs

Originally designed for 8-bit inputs and 6-bit weights, in this subsection we suppose that UltraTrail now employs 8-bit data words and a 32-bit off-chip memory architecture for both data sets, simplifying memory module selection.
In this context, a comprehensive comparison emerges between a manually configured memory framework and basic dual-ported modules, aimed at achieving optimal throughput.
Significantly, the memory hierarchy and dual-ported memories align in word width.
Since the weight dataset always has a simple shifted cyclic access pattern, the framework was configured with only one hierarchy level.
A multi level framework would increase chip area and power consumption, while the offered pattern space would not be utilized.



Regarding the weights, layer eleven of the TC-ResNet model has the highest capacity requirement among all layers with 20,736 unique data words.
Unrollings featuring only eight unique addresses per loop step, demand a 64-bit word width with at least 2,592 RAM depth.
While dual-ported 64-bit memory can only offer a maximum capacity of 2,048, necessitating two banks, the memory framework efficiently uses a single 64-bit dual-ported memory with a capacity of 32 words, occupying only 6.5% of the chip area compared to the dual-ported alternatives.
For unrollings with 16 distinct addresses, either two 128-bit banks (accessed consecutively) or two 64-bit banks (working in parallel) are required.
However, unrollings with 32 and 64 unique addresses need multiple banks for data parallelism.
As shown in Figure <ref>, despite a 17.1% increase, the dual-ported sram remain 3.1 times larger than the parallel memory frameworks.
Figure <ref> illustrates runtime comparisons, demonstrating the memory framework's relative efficiency of 58.8%, 60.6%, 85.7%, and 97.6% for 8, 16, 32, and 64 unique addresses per step, respectively.
Note that an efficiency of 100 % represents one data word output in each clock cycle.
However, the framework was executed without any preloading, which resulted in a loss of performance due to the need for data fetching.
This highlights the potential for further improvements by using idle time between layers for data preloading.




Shifting focus to input data sets, the limitations of the memory framework become evident, as certain patterns are not supported efficiently yet.
An updated mcu is needed to address these complex parallel nested patterns to achieve optimal performance.



  §.§.§ Integration as Weight Memory

The standard UltraTrail 8x8 configuration utilizes three single-ported 1024x128-bit sram modules to be able to store the complete weight data set of the TC-ResNet model as shown in Figure <ref>a. These macros alone occupy more than 70% of the accelerators chip area.
After we replaced the memory modules with a single level memory hierarchy, the accelerators chip area was reduced by 62.2%. The hierarchy has one dual-ported memory module with a 128-bit word width. An osr is used to generate the required word with of 384 bits. 

The hierarchy needs three clock cycles to fill the osr if the data is already stored in the memory level 0.
The time needed loading these weights from the off-chip memory depends on the three factors off-chip word width, off-chip clock frequency, and average response time.
Our test bench simulated an 32-bit off-chip architecture that is clocked at 1.
The accelerator is clocked four times slower at 250.
This very slow clock rate was chosen to meet the real-time requirement of 100 per inference while reducing the power consumption of the chip <cit.>.
Data requests of the hierarchy were delivered with a latency of one clock cycle.
As a result, three accelerator clock cycles were needed to request and store a 128-bit weight within the hierarchy.

The loop-nest analysis of the TC-ResNet revealed that only fc layers (layer eight and twelve) do not reuse their weights for multiple loop iterations.
As exposed by Table <ref>, these layers do not dominate the computational costs of the neural network.
Thus, their low efficiency can be ignored.
At four, the conv layer eleven has the shortest cycle length.
These cycle lengths are too short for the hierarchy to be able to read data from the off-chip memory and provide it to the mac array in time.
However, these delays could be reduced by preloading the data during the execution of preceding layers.
Three inference runs were used to estimate the power consumption of the adjusted UltraTrail and to compare it to its baseline counterpart. As illustrated in Figure <ref>b, the power consumption does slightly increase by 6.2% if the hierarchy is used instead of standard single-ported modules. This is due to the significantly greater leakage power of dual-ported memory compared to single-ported memories.



 §.§ Discussion and Future Work


The case study revealed the potential of an on-demand streaming interface for hardware accelerators.
Instead of loading the weight data set once and storing it in large on-chip memory macros before the first inference, the hierarchy enables a significant reduction of required chip area.
At the same time, the hierarchy increases the accelerator's flexibility by enabling it to switch between different dnn more frequently.
To start the execution of another dnn, the hierarchy just needs a reset cycle with the new pattern settings.
However, the power consumption does slightly increase as dual-ported memories have higher leakage and switching power than their single-ported counterparts.
Also, the continuous off-chip memory accesses result in additional power consumption.
The actual amount of energy consumed, however, does highly depend on the soc and its memory system.
A slight redesign with a dual-banked, single-ported hierarchy could solve this issue with only a minor chip area overhead.


The framework achieved promising results regarding the weight data sets, however, it should be improved to be efficiently utilizable for the input data set.
A more modular and customizable design could increase the supported pattern range.
Additionally, the redesign could also further increase the throughput of the hierarchy, if required.




§ CONCLUSION

This paper presented a configurable memory hierarchy framework dedicated for neural network hardware accelerators. By exploiting the calculability of dnn memory access patterns, it is possible to deploy smaller memory configurations than the conventional approach of storing the complete data set on the accelerator. The on-demand data fetching and delivery increases the possibilities of the accelerator's design space. The performance analysis verified the efficient support of common access patterns. Finally, the UltraTrail case study showed, that the hierarchy can reduce the required chip area by up to 62.2% while only resulting in a performance degradation of 2.4%.

IEEEtran

