Efficient charge modulation in ultrathin LaAlO$_3$-SrTiO$_3$ field-effect transistors
A. E. M. Smink B. Prabowo B. Stadhouder N. Gauquelin J. Schmitz H. Hilgenkamp W. G. van der Wiel








	MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands

	MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands

	MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands

	MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands
	EMAT, University of Antwerp, Groenenborgerlaan 171, 2020 Antwerp, Belgium

	MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands

	MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands

	MESA+ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands




At the -interface, electronic phase transitions can be triggered by modulation of the charge carrier density, making this system an excellent prospect for the realization of versatile electronic devices. Here, we report repeatable transistor operation in locally gated -field-effect devices of which the dielectric is only four unit cells thin, the critical thickness for conduction at this interface. This extremely thin dielectric allows a very efficient charge modulation of ∼3.2×10^13 cm^-2 within a gate-voltage window of ±1 V, as extracted from capacitance-voltage measurements. These also reveal a large stray capacitance between gate and source, presenting a complication for nanoscale device operation. Despite the small thickness, we observe a negligible gate leakage current, which we ascribe to the extension of the conducting states into the substrate. 


Efficient charge modulation in ultrathin -field-effect transistors
    W.G. van der Wiel
    December 30, 2023
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Charge modulation in field-effect transistors (FETs) is the core physical mechanism enabling modern-day electronics. In a standard semiconductor such as silicon, its main purpose is to change the electrical conductivity, defining the “0” and “1” states in digital electronics. In other classes of materials, e.g., transition metal dichalcogenides and complex oxides, tuning the charge carrier density can trigger quantum phase transitions, offering possibilities for fundamental studies and for using such transitions in electronic devices  <cit.>. However, these transitions mostly take place at very high charge carrier densities, exceeding 10^14 cm^-2. Significant tuning of such a high charge carrier densities can only be achieved by means of chemical doping techniques and electrolyte gating, which are both impractical for functional devices.

In doped strontium titanate () and at the conducting interface between and selected other insulators such as , (super)conducting and insulating phases are near each other in terms of charge carrier density <cit.>, typically in the range of a few times 10^13  cm^-2. In the interface case, the geometry is intrinsically the same as the semiconductor-oxide stack of a metal-oxide-semiconductor FET (MOSFET), making such interfaces appealing for use in field-effect devices. Moreover, at low temperatures the substrate can also be used as a gate dielectric (backgating), owing to its huge permittivity <cit.>. For the archetypical -interface, reports on the significant field-effect tuning of the critical temperature for superconductivity <cit.>, the considerable low-temperature mobility <cit.>, and of spin-orbit coupling strength <cit.> showed the versatility of this system both for fundamental studies and for its possible use in future electronics.

However, backgating takes place over large areas and requires the application of voltages in the order of 100 V across the typically 0.5-mm-thick substrate to achieve a carrier density modulation of up to ∼ 4 × 10^13 cm^-2 electrostatically <cit.>. Hence, the backgating geometry is unsuitable for integration into circuits, which requires local operation by voltages of ∼1 V. Achieving a MOSFET-like (topgate) geometry with the -interface, where the voltage is applied across the layer, is challenging because structuring these materials into (small) channels is not a trivial process <cit.>. Low-voltage, topgate FETs were first realized by Förg and coworkers <cit.>, after which the functionality of such devices was extended greatly <cit.>. Unfortunately, the emergence of gate leakage currents across the thin layer – typically 8 to 20 unit cells (uc) thick – limited the charge modulation to about 2 × 10^13 cm^-2. In parallel, the capability of achieving extreme charge modulations in -based FETs, up to a record value of 2.4 × 10^14 cm^-2, was demonstrated in inverted structures with a thick layer as the dielectric <cit.>. Still, these devices have thick dielectrics and a high intrinsic carrier density, compromising low-voltage and local operation. The ultimate oxide-based FET, in which a small gate voltage achieves a charge modulation of several times 10^13 cm^-2, possibly enabling local switching of quantum phase transitions, therefore has remained elusive.

In this Letter, we demonstrate such efficient charge modulation in Au--FETs in which the dielectric has a nominal thickness of only four unit cells (uc), the critical thickness for interface conduction <cit.>. The devices display repeatable transistor behavior with low leakage currents and high ON/OFF ratios. Capacitance-voltage measurements reveal a large voltage-independent contribution to the capacitance, and a low effective permittivity for the layer. The latter can be ascribed to a dielectric `dead layer' forming on the Au-interface, as indicated by scanning transmission electron microscopy. Despite this layer, the charge modulation is very efficient with a high capacitance per unit area, proving the principle of low voltage modulation of high charge densities in complex-oxide based FETs.


The fabrication of our devices started with a standard procedure to terminate the substrate on the TiO_2 sites of the (001) surface plane <cit.>. To enable structuring of the film into channels, we deposited an layer at room temperature, which was etched in OPD4262 developer used for UV lithography <cit.>. The subsequent growth of and Au by pulsed laser deposition (PLD) was done , ensuring the interface between these layers to be as clean as possible. The was deposited in an O_2 process pressure of 1 × 10^-4 mbar at T=850 , with a laser fluence of 1.3 J cm^-2, spot size of 2 mm^2 and a frequency of 1 Hz, resulting in a growth rate of one uc per ∼20 pulses, monitored by reflective high-energy electron diffraction (RHEED). The distance between the substrate and the single-crystalline target was 45 mm. After the deposition, the sample was annealed for 1 h in an O_2 pressure of 400 mbar at a temperature of 600 . Then, the Au was deposited in an Ar process pressure of 0.22 mbar, at T=100 with a laser fluence of 3.6 J cm^-2 and a spot size of 1 mm^2. To reduce the energy of the particles arriving at the substrate, the target-substrate distance was increased to 60 mm. This way, a layer of ∼30 nm was grown after 9000 pulses at f = 5 Hz. Then, electrical contacts to the interface were patterned using UV lithography, followed by a standard technique using Ar ion etching and subsequent sputtering of Ti/Au contacts <cit.>, which were structured by lift-off. Finally, the gate electrode was patterned using UV lithography and structured using a buffered KI solution <cit.>. 

In the dc current-voltage measurements, the drain current, 𝕀, was measured by a Keithley 2401 source-measure unit that also provided the drain-source voltage, . The gate current, , was determined by measuring the voltage over a 1 kΩ resistor using a Keithley 2000 multimeter. The capacitance-voltage characteristics were measured with a Keithley 4200-SCS parameter analyzer with a 4210 capacitance-voltage unit, using an ac voltage of 25 mV and a frequency of 10 kHz: close to the optimal frequency of ∼30 kHz for these devices <cit.>. All measurements were performed at room temperature with the source terminal connected to ground.



Figure <ref> presents electron microscopy images of two of our devices. In the cross-sectional image (Fig. <ref>(a)), four unit cells of are clearly visible. Like previously reported by another group<cit.>, we also observe a thin disordered layer between the and Au layer with a thickness of ∼0.7 nm. The dark color indicates the absence of heavy elements such as Au, which appears light in this image; we therefore assume that this layer is not conducting and adds to the effective thickness of the dielectric. Further analysis of this layer is to be published elsewhere; we discuss the consequences of this layer for the transistor properties below. Figure <ref>(b) shows the top view of a FET.


Figure <ref> summarizes the transistor operation of device A, a Au--FET like the one shown in Fig. <ref>(b), with a 4-uc-thin dielectric and channel length, L, and width, W, both equal to 10 . We measured over ten devices on two different samples, with varying channel dimensions. All of these devices displayed transistor behavior, with ON/OFF ratios between 10^2 and 10^4. In Fig. <ref>(a), we observe clear ohmic (triode/linear) and saturation (active) regimes. The circles separating these regimes represent the saturation voltage and current, which both increase monotonously with . For higher gate voltages, the saturation current does not follow the expected quadratic trend anymore <cit.>, which we ascribe to a suppression of carrier mobility with increasing topgate voltage as previously observed <cit.>. 



In Figure <ref>(b), switching of the channel conductivity is clearly demonstrated for all , from which we extract the transfer characteristics of this device. From a linear fit to √(𝕀) versus , we determine the threshold voltage, , at -0.81 ± 0.01 V. The subthreshold swing of 98 ± 2 mV per decade – of which the minimum lies at , thus is not strictly subthreshold – and the maximum ON/OFF ratio of ∼10^4 for = +5 V are quite comparable to the first semiconductor MOSFETs with a similar dielectric thickness <cit.>. Note that the ON/OFF ratio is limited by a finite OFF current, caused by a (minute) gate current emerging below = -0.7 V.

To further characterize our devices and to determine the charge modulation in the channel, we carried out capacitance-voltage measurements between gate and source. Using a simple model with a shunt and a series resistor next to the capacitance (Fig. <ref>(a)), we extract the capacitance-voltage characteristics of device A. The result, representative for all measured devices, is presented in Figure <ref>(b). The most prominent difference of this C(V) characteristic to semiconductor-based devices is that below threshold, the capacitance remains constant, instead of increasing due to the formation of an accumulation region <cit.>. This voltage-independent capacitance at negative gate voltage is observed commonly in metal--junctions <cit.> and is generally ascribed to a voltage-driven metal-insulator transition (MIT) <cit.>. When comparing this curve to Fig. <ref>(c), we find that the voltage-independent and voltage-dependent regions are separated by the threshold voltage of -0.81 V.



For a quantitative analysis, we assume that the voltage-independent, or `stray', capacitance, , is a parallel element to the capacitance between the gate and the conducting channel, , yielding () =  + (). To substantiate this assumption, we measured the capacitance-voltage characteristics of several devices with varying dimensions. This allows to extract the scaling of gate-source capacitance with device area, as depicted in Figure <ref>(d). Here, we consider devices with a square channel, i.e. L = W, and extract the capacitances  and  at = +0.5 V, where the capacitance is fairly constant as function of gate voltage. We find that the total capacitance does not follow a power law dependence on W, but that  and  do. The channel capacitance scales with device area (L × W), in excellent agreement with a parallel-plate capacitor model. Hence, we can extract the effective relative permittivity, ≈ 6.1 ± 0.4, using d = 1.5 nm. The stray capacitance scales with the channel dimension to the power 1/3, thus depends on the geometry in a nontrivial way. To our knowledge, there is no theory yet that explains such a dependence on the device geometry. Extrapolation of our data suggests a crossover to occur at L = W ≈ 3.5 , implying that the stray capacitance becomes dominant in small devices.

We postulate that this large stray capacitance is due to the very large permittivity of the channel material, , which is ∼300 at room temperature <cit.>. As illustrated by the blue lines in Fig. <ref>(c), the gate terminal is capacitively coupled to the source and the drain through an electric field. The capacitance associated with this electric field depends on the permittivity of the insulator and of the channel material. In most materials, this would not be very significant; here, the very high permittivity of the channel material implies that the gate-source capacitance in absence of a conducting channel remains sizable.

To obtain the modulation of charge density in the channel, we omit the stray capacitance and integrate  with respect to . Between threshold and +1 V, this yields a carrier density modulation of 3.2×10^13 cm^-2. Above +1 V, the measurement becomes inaccurate due to emerging gate leakage. If we assume that the capacitance remains constant above +1 V, the projected charge modulation during the measurements presented in Fig. <ref>(b) is ∼5.2×10^13 cm^-2. The gate voltage required for this modulation does not exceed +2 V; within this window, the gate leakage current remains more than an order of magnitude smaller than the current through the channel.



As a benchmark to compare these FETs to silicon-based devices, we calculate the equivalent oxide thickness (EOT) compared to SiO_2, which has = 3.9. Using ≈ 6.1 ± 0.4 and d = 1.5 nm, we find an EOT of only 0.96 ± 0.1 nm. However, this value for  is much lower than ones reported in literature for thick films <cit.>, which range from 18 to 30. This suppression of  in metal--junctions is a widely observed phenomenon <cit.>; with increasing layer thickness,  was reported to approach the bulk value <cit.>. This was ascribed to a `dead layer' forming inside the film because of structural interface effects <cit.>. Because Fig. <ref>(a) shows a disordered layer forming on top of the fully intact, 4-uc-thin layer, we propose an alternative scenario in which the `dead layer' forms on top of the rather than inside it. A series capacitor model in this scenario is mathematically equivalent to the one used by Hosoda <cit.>:


    + ddead/,tot =  /,lao + ddead/,dead.


By using ,lao = 18, = 1.52 nm, and ddead = 0.7 nm, we find ,dead≈ 2.5 ± 0.3, which we deem a reasonable value for a disordered layer. Therefore, this disordered layer at the -Au interface poses a viable alternative scenario to the dead layer within the film; further investigations on devices with varying layer thickness made using different fabrication procedures may distinguish between these two possibilities.

Despite the suppression of , the charge modulation in our devices is efficient and not compromised by gate leakage currents. Moreover, in comparison to previous reports on Au--stacks with 4-uc-thin barriers, where the gate current was used to perform tunneling spectroscopy of the interface <cit.>, the gate current density is about four orders of magnitude smaller. To investigate the factors determining the gate leakage current, we carried out temperature-dependent measurements as described in the Supplementary Information. The results show that ohmic and hopping-based conduction are negligible, and that the gate current is dominated by direct tunneling and Schottky emission. Accordingly, the density of defects inside the layer must be very low and memristive effects based on the movement of defects should be absent. To confirm this, we measured the device response against repeated gate voltage cycling and up to high gate voltages of ± 5 V. The results presented in Fig. <ref> confirm the absence of resistive switching in our devices. Moreover, the behavior at high voltage in Fig. <ref>(c) fits the description of a Schottky diode with a forward-reverse bias ratio of ∼3 × 10^4, in good agreement with previous results <cit.>.



To explain the surprisingly large difference in gate current between the tunneling spectroscopy devices of Refs. richter_interface_2013, boschker_electronphonon_2015, kurten_-gap_2017 and our FETs, we consider the factors determining direct tunneling currents. Since both types of devices have the same material stack with the same thicknesses and the `dead layer' is present in the tunneling spectroscopy studies <cit.> as well, the energy landscape in terms of barriers and thickness should be the same. Therefore, we argue that the out-of-plane distribution of mobile charges in the differs greatly between the two types of devices, increasing or decreasing the effective barrier thickness. In , the mobile charges do not reside exactly at the surface, but are distributed within a quantum well <cit.>. This charge distribution depends crucially on the electrostatic boundary conditions for the well, which are highly susceptible to the environment in which the film is grown <cit.>. In consequence, samples grown in different conditions have varying charge distributions in the quantum well. Especially for samples with thin layers, the effective depth at which the mobile charges reside can thus vary greatly among samples grown under different conditions. We note that this effect may be enhanced greatly by a recently proposed region of negative polarization directly on the side of the interface <cit.>. Of great importance for device operation is that this effective thickness increase should not suppress the capacitance by much, for the permittivity of exceeds 300 even at room temperature <cit.>. Hence, we propose that this increase of the effective tunnel barrier thickness, without lowering the capacitance, is the key enabler of the efficient charge modulation observed in our devices.



In summary, we characterized the operation of Au--field-effect transistors with a layer thickness of only four unit cells, or 1.5 nm. Our devices exhibit highly repeatable transistor behavior with very low gate leakage currents. In capacitance-voltage measurements, the gate-source capacitance becomes voltage-independent below threshold, which we attribute to stray fields coupling the gate to the source and drain terminals in absence of a conducting channel. Integration of the voltage-dependent part of the capacitance yields a charge modulation of about 3.2× 10^13 cm^-2, within a gate voltage range of ± 1 V.

This highly efficient charge modulation is limited by a commonly observed suppression of the permittivity in very thin layers grown on . Scanning transmission electron microscopy imaging suggests that this suppression is due to a dielectric `dead layer' forming at the Au-interface, with a thickness of ∼0.7 nm. The surprisingly low leakage current cannot be due to this layer, but is likely due to the out-of-plane distribution of charges in the channel. Because of the high dielectric permittivity of , this does not significantly affect the gate-source capacitance, enabling efficient modulation of high charge densities by low gate voltages without excessive gate leakage currents. We foresee that making use of this delocalization in quantum wells opens new venues to engineer high-charge-density field-effect transistors based on advanced materials.


We thank Maurits de Jong for his help with the capacitance-voltage measurements, Jochen Mannhart and Hans Boschker for stimulating discussions, and Frank Roesthuis, Dick Veldhuis, and Thijs Bolhuis for technical assistance. We acknowledge financial support through the DESCO program of the Foundation for Fundamental Research on Matter (FOM), associated with the Netherlands Organization for Scientific Research (NWO).




