Design of Configurable Sequential Circuits in Quantum-dot Cellular Automata
Mrinal Goswami Mayukh Roy Chowdhury Bibhash Sen

 
Design of Configurable Sequential Circuits in Quantum-dot Cellular Automata      

M. Goswami et. al. 
M. Goswami, M. R. Chowdhury and B. Sen Department of Computer Science and Engineering, 
National Institute of Technology, Durgapur,
 West Bengal - 713209, India 

              mg.16cs1102@phd.nitdgp.ac.in           

Design of Configurable Sequential Circuits in Quantum-dot Cellular Automata
    Mrinal Goswami Mayukh Roy Chowdhury Bibhash Sen
    Received: date / Accepted: date
===========================================================================


Quantum-dot cellular automata (QCA) is a likely candidate for future low power nano-scale electronic devices. Sequential circuits in QCA attract more attention due to its numerous application in digital industry. On the other hand, configurable devices provide low device cost and efficient utilization of device area. Since the fundamental building block of any sequential logic circuit is flip flop, hence constructing configurable, multi-purpose QCA flip-flops are one of the prime importance of current research. This work proposes a design of configurable flip-flop (CFF) which is the first of its kind in QCA domain. The proposed flip-flop can be configured to D, T and JK flip-flop by configuring its control inputs. In addition, to make more efficient configurable flip-flop, a clock pulse generator (CPG) is designed which can trigger all types of edges (falling, rising and dual) of a clock. The same CFF design is used to realize an edge configurable (dual/rising/falling) flip-flop with the help of CPG. The biggest advantage of using edge configurable (dual/rising/falling) flip-flop is that it can be used in 9 different ways using the same single circuit. All the proposed designs are verified using QCADesigner simulator.




§ INTRODUCTION

CMOS based VLSI designs play a very important role in digital design. The operation of computer chips has shown outstanding growth in the last few decade. But the exponential increase of computing power over the last decades has relied on shrinking the transistor. The recent survey of International Technology Roadmap for Semiconductors (ITRS-2015) shows that the transistor could face the challenge of feature size limitation by 2021 <cit.>. Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology with extremely small feature size and ultra low power consumption which is suggested as an alternative technology of current CMOS <cit.>.
Flip-flop plays a significant role in any sequential circuits. Sequential circuits in QCA gain maximum attention due to its realization difficulties in terms of architectural complexity and synchronous mechanism <cit.>. Till date, various studies have been performed on flip-flop design. However, all the previous designs realized different flip-flops with disparate designs and thus they differ in terms of area and latency. No regular, uniform or symmetric design paradigm is addressed so far for a simple implementation of flip-flops in QCA. The disparity of designs (SR, D, T and JK) leads to various problems in a single circuit having multiple flip-flops. The inter-connection of the different flip-flops (SR, D, T and JK) is another big issue. So, to tackle these issues, a uniform design methodology is to be explored for flip-flops having same area and latency.     
In the recent past, conventional QCA based flip-flops were studied extensively <cit.> but, most of the previous designs are not robust and highly error prone due to defective wire-crossing employed in their designs <cit.>. Generally,  two well known wire-crossing techniques have been used in QCA technology: multi-layer and coplanar wire-crossing (using rotated QCA cells). Multi-layer wire-crossing has several fabrication limitations <cit.> <cit.> due to which it is not considered for our proposed designs. On the other hand, coplanar wire-crossing in QCA can be realized with 45^0 (normal QCA cell) cells and 90^0 (rotated QCA cell) cells. However, production of 90^0 cell needs a high level of precision in placing which increases the overall cost and the implementation complexity <cit.> <cit.>.
On the other hand, flexibility and performance are the two big issues of any digital logic circuit <cit.>. The intermediate trade-off between flexibility and performance is the utmost necessity for current digital logic circuit which can be attained by reconfigurability <cit.>. It is observed that reconfigurability in the nanoscale era can lead to the design of various low power and energy efficient system which is the need of the hour <cit.>.
All these above factors motivate us to design configurable, robust flip-flop structures for QCA which can address the irregular behaviour of designs as well as reliability issue of wire-crossing in QCA. The main contribution of this research is as follows:


  * A configurable level triggered QCA flip-flop (CFF) is designed which can be configured to JK, D and T flip-flop. This is the very first attempt to design a configurable flip-flop in QCA.    

  * To remove the wire-crossing difficulties, clock-zone based coplanar crossover technique is employed, which is the most robust wire-crossing technique in QCA technology <cit.><cit.>.

  * Considering CFF as a basic element, an edge configurable (dual/rising/falling) flip-flop is designed using a clock pulse generator (CPG).

  * Based on the edge configurable (dual/rising/falling) flip-flop, an n-bit edge configurable (dual/rising/ 
falling) counter/shift register is also proposed.


The rest of the paper is organized as follows: section <ref> introduces fundamentals of quantum-dot cellular automata (QCA). Existing works based on reconfigurable logic are discussed in section <ref>. The proposed design of level triggered configurable flip-flop (CFF) is introduced in section <ref>. The design of edge configurable flip-flop is introduced in section <ref>. The higher order QCA configurable circuits are proposed in section <ref> employing edge configurable flip-flop as the basic element. Finally, section <ref>, concludes the paper.  


§ BASICS OF QCA


A QCA cell comprises of four quantum dots (Figure <ref>(a)) which can carry two free electrons. These free electrons can move between the four quantum dots. As shown in Figure <ref>(b), the two polarization states of a QCA cell can be represented as P=-1 (logic 0) and P=+1 (logic 1). The basic structures of QCA technology are majority voter (Figure <ref>(c)) and inverter (Figure <ref>(d)). The QCA majority voter (MV) can be expressed as,


MV(A, B, C) = AB + BC + CA


A majority voter can serve as a 2-input AND gate if one of the inputs is fixed at P=-1. Alternatively, if any one input of the majority voter is fixed at P=+1 then the modified majority voter can serve as a 2-input OR gate. There are two different types of inverter available in QCA technology as shown in Figure <ref>(d). The possible two orientations (“+") and (“×") (90^ 0 and 45^ 0 respectively) of QCA cell are shown in Figure <ref>(e). There are two fundamental wire-crossing techniques (co-planar and multi-layer) available in QCA. As shown in Figure <ref>(e), the co-planar wire-crossing can be implemented with the mix combination of two different orientations (90^0 and 45^0) of QCA cells. The multi-layer wire-crossing can be implemented with the help of two or more different layers. As discussed earlier, co-planar and multi-layer wire-crossing techniques are facing serious issues <cit.> <cit.> due to which we consider clock-zone based wire-crossing technique which can be implemented using non-adjacent clock zones (phase difference is equal to 180^0)  on the same plane <cit.><cit.> as shown in Figure <ref>. This eliminates the problem of interference between the QCA cells.   

The QCA clock controls the flow of information within the circuit. The circuit information is carried from one end to another with the help of clock. The clock zones of QCA are distinct and 90^0 phase shifted <cit.> <cit.>. At the time of computation, the previous clock zone must hold its output, which can be achieved by splitting the clock into four phases: switch, hold, release and relax <cit.> which is shown in Figure <ref>(f).








Four types of implementation technology exists in QCA: (a) metal-island <cit.>; (b) semiconductor <cit.>; (c) molecular <cit.> <cit.>; and (d) magnetic <cit.> <cit.>. The metal-island is the first implementation technology created to demonstrate the behaviour of QCA which requires cryogenic temperature to operate <cit.>. The semiconductor technology, now-a- days becomes operable in room temperature <cit.>. The semiconductor QCA technology is adopted as the implementation technology for our proposed QCA designs. The molecular technology, not yet implemented, is a single molecule implementation technology. This technology is highly promising due to its highly symmetric QCA cell structure, very high switching speeds, extremely high device density, operation at room temperature and even the possibility of mass-production by means of self-assembly. Magnetic QCA (MQCA) is based on the interaction between the nanoparticles of the magnet. The MQCA depends on the quantum mechanical nature of magnetic interactions, which can be operated at room temperature <cit.> <cit.>.


§ RELATED WORK


Limited attempts have been made to realize reconfigurable designs in QCA <cit.>. An And-OR-Inverter (AOI) logic is proposed in <cit.> where by fixing one or more input various logic functions can be implemented such as OR-AND, NAND-OR, NOR-NAND etc. which is shown in Figure <ref>(a). In <cit.>, a complex 7-input QCA configurable gate (out of 7 inputs, 3 inputs are used as control inputs) is proposed by cascading three 3-input majority voter as shown in Figure <ref>(b). The sum of product, product of sum, four-input AND, four-input OR logic etc. can be constructed by fixing control inputs to “0" or “1". In <cit.>, under the presence of different QCA  defects, a symmetric configurable fault tolerant reconfigurable gate (RFTG) has been proposed as shown in Figure <ref>(c). A novel configurable QCA design is proposed in <cit.>. The design (Figure <ref>(d)) is capable of realizing various logic functions such as 2-input OR, 3-input AND, 2-input OR, 3-input OR etc. A reconfigurable majority gate (Figure <ref>(e)) is presented in <cit.>. It is apparent that most of the previous work is limited to implement small logic functions only. Configurable memory structures in QCA are yet to be explored.


§ PROPOSED LEVEL TRIGGERED CONFIGURABLE FLIP-FLOP

The main advantage of realizing configurable hardware is low device cost and efficient utilization of device area.  Till date, all the existing configurable designs in QCA strictly follow design rules mentioned below as in <cit.>:


  * Fixing input cells (control inputs) to logic “0" or “1" to produce different functions.  

  * Displacing some of the input cells to change the distance between driver cells of the device to generate different functionality.

The first method is adopted to realize the proposed configurable designs as mentioned in <cit.>. To realize a configurable flip-flop, we first choose a JK flip-flop. The characteristic equation of JK flip-flop is Q(t+1) = JQ + KQ. To produce D and T flip-flop, either a complemented value of input J or an un-complemented value of input J need to pass to both the inputs of JK flip-flop. The output function of XNOR is F = A.B + A.B. If we choose B as a control input then we can use XNOR function as a simple QCA wire or an inverter. If B is zero then it will act as an inverter otherwise it will act as a simple QCA wire. So, the XNOR function can be used to produce a complemented value as well as an un-complemented value of its inputs controlling one of the inputs to zero or one. Moreover, a multiplexer is the best possible choice to select any one input between two input values. 
The QCA representation of the proposed configurable flip-flop (CFF) is shown in Figure <ref>. The proposed CFF has 5 inputs (A, B, C1, C2 and CLK) and two outputs (Q and Q) where C1, C2 are control inputs. The primary output of the proposed CFF is as follows:

    Q_t+1 = { A.Q_t + 
        (B.C1 + A.C2. C1 + A. C1. C2)Q_t} CLK +  CLK. Q_t


    Q_t+1 = { A.Q_t + {A. B(C1+C2) + A.B(C1+C2) + 
    B.C1 + C1(A.C2 + A.C2)} Q_t} CLK + CLK.Q_t



 §.§ Case 1:

If C1 = C2 = 0 and CLK=1 then the equation <ref> will be 

    Q_t+1   = { A.Q_t + { A.B + A } Q_t}
    
    Q_t+1   = A.Q_t + A.Q_t
       
    Q_t+1   = A



 §.§ Case 2:

If C1 = 0, C2 = 1 and CLK = 1 then the equation <ref> will be 

    Q_t+1   = A.Q_t + {A.B + A} Q_t
    
    Q_t+1   = A.Q_t + A.Q_t



 §.§ Case 3:

If C1 = 1, C2 = X (Don't Care) and CLK = 1 then the equation <ref> will be 

    Q_t+1   = A.Q_t + {A.B + A.B + B} Q_t
    
    Q_t+1   = A.Q_t + B.Q_t

The Table <ref> shows the different functionality of the proposed CFF based on control inputs C1 and C2. The CFF will obey the rules of T FF if C1C2 = 01 and if C1C2 = 00 then CFF will behave as D FF. The CFF will behave as JK FF if C1C2 = 1X where X means don't care. The truth table of the proposed CFF is shown in Table <ref>.

 



  §.§.§ Module 1 (XNOR)
 The function produced by this module is: F1= A.C2 + A.C2. The output of module 1 is passed to module 2 as shown in Figure <ref>. Depending on the value of input C2, module 1 generates a complemented or un-complemented value of input A to module 2. If C2=0 then a complemented value of the input A is passed to module 2 otherwise uncomplemented value of input A is passed to module 2. 


  §.§.§ Module 2 (2:1 MUX)
 The output function of this module is : F2=B.C1+F1.C1. If C1=1, input B will be selected and module 3 will behave according to JK flip-flop. On the other hand, if C1=0, the module 3 will behave either D flip-flop or T flip-flop depending on the output F1. If F1= A then the module 3 will behave as a D flip-flop otherwise it will behave as a T flip-flop.


  §.§.§ Module 3 (JK FF)
 This module follows the instructions of module 1 and 2. Module 3 behaves as T flip-flop if module 1  produces F1 = A and at the same time module 2 produces F2 = F1 (Figure <ref>(a)). Alternatively, if module 1 produces F1= A and at the same time module 2 produces F2 = F1 then module 3 behaves as a D flip-flop. Finally, if module 2 produce F2 = B (module 1: F1= don't care ) then module 3 behaves like a JK flip-flop.


The advantage of configurable memory units lies in its application domain. These can be used to design circuits with architectural similarity eliminating the need to design separate hardware performing a specific function. For example, counters and shift registers can be implemented in a single design with the option to configure the flip-flop according to the need. The biggest advantage of the proposed CFF is that single module can serve as a D, T and JK FF. Table <ref> shows the performance of CFF with the existing D, T and JK FF. The proposed CFF consists of 2.75 delay covering an area of 0.20 μ m^2 with 159 QCA cells. Although, the proposed CFF exceeds in all the respect compared to existing designs, but these small overheads can be accepted due to the configurable superiority of CFF over the existing designs. All the previous designs <cit.> <cit.> <cit.> <cit.> <cit.> <cit.> <cit.> <cit.> are not configurable in nature and can produce only one function. On the other hand, the CFF can produce three different functions using the same circuit. Moreover, the CFF allows us to present an all in one flip-flop, which can also be perceived as a standard universal design. A universal, scalable, efficient (USE) realistic clock distribution scheme for QCA is proposed in <cit.>. The CFF layout under the USE clocking scheme (CFF-USE) is shown in Figure <ref>. The proposed CFF-USE consists of 541 QCA cells covering an area of 1.81 μ m^2. 




















 §.§ Memory design using proposed level triggered flip-flop

In this section, a 1-bit RAM is designed to test the proposed CFF functionality. All the pervious memory (RAM) designs in QCA can be categorized into two groups: line based and loop based. In the loop-based RAM design, four clock zones are utilized to store the previous value but in the line-based RAM design, a QCA wire is used to store the previous value of the output <cit.>. The proposed RAM design also utilizes the property of loop based design which is shown in Figure <ref>(b). The incoming input value is circulated inside the memory loop if the Enable input is set to 1 and at the same time Write/Read input is set to 0. If the Enable input is set to 1 and Write/Read input is 1 then the current stored value inside the memory loop is fed to the output. In both the cases i.e. read or write, the control input value of C2 is set to zero. The simulation result of the proposed RAM is shown in Figure <ref>. The inputs Enable and Write/Read are configured in such a way that they can provide the values needed for C1 and B input (Figure <ref>(a)). The proposed 1-bit RAM has 209 QCA cells covering an area of 0.31 μ m^2. 
















§ DESIGN OF  EDGE CONFIGURABLE FLIP-FLOP

The level triggered JK flip-flop is susceptible to noise due to which it leads to race-round condition <cit.>. In order to avoid such unstable phenomenon, edge triggered (falling, rising and dual) flip-flops are extensively studied. There are two well-known schemes in QCA to implement edge triggered flip-flop, the clock pulse generator scheme and the MUX/latch scheme <cit.>. In QCA, the clock pulse generator scheme is explored more than the MUX/latch scheme. Figure <ref> shows the proposed pulse generator which can produce clock pulses for the falling edge, rising edge as well as dual edges with the help of the two control inputs C3 and C4. To detect a falling edge it takes the help of the previous clock pulse (CLK_old) and compares it with the current clock pulse (CLK). The CLK_old is produced by using four consecutive clock zones (one clock cycle delay) as shown in Figure <ref>(b). The majority voter representation of the falling edge operation is as follows: 




Out1= MV(MV(CLK, C3, -1), CLK_old, -1)


The value of (CLK. CLK_old) will give a resultant boolean value of 1 which triggers a pulse in the output if the control inputs are set to C3=1 and C4=0 (Table <ref>). At the same time, the proposed clock pulse generator can generate rising edge (CLK (CLK_old)) which results to 1) if C3=0 and C4=1 (Table <ref>) and hence producing a trigger in the final output. The majority voter representation of the rising edge operation is as follows: 


Out2= MV(MV(CLK, C4, -1), CLK_old, -1)


The output of Out1 and Out2 (Figure <ref>(b)) is passed through an OR gate to produce the final output. If both the control inputs (C3=1 and C4=1) are set to 1 then the proposed clock pulse generator can produce pulses for both the edges (rising as well as falling) and hence works as a dual edge triggered clock pulse generator (Table <ref>). The majority voter representation of the dual edge operation is as follows:


Output=MV(Out1, Out2, 1) 



The job of the control inputs (C3 and C4) is to activate the pulse generator to get the necessary output pulse. The function of the control inputs are as follows:


  1. If C3=0 and C4=1 then the pulse generator acts as a rising edge triggered pulse generator.

  2. If C3=1 and C4=0 then the pulse generator acts as a falling edge triggered pulse generator.

  3. If C3=1 and C4=1 then the pulse generator acts as a dual edge pulse generator.

The simulation waveform of the proposed clock pulse generator is shown in Figure <ref> which establishes the correctness of the proposed clock pulse generator.
The proposed edge configurable flip-flop (ECFF) (Figure <ref>) can be implemented with the help of a clock pulse generator (Figure <ref>) using CFF as the basic element. Efforts have been made to increase the functionality of ECFF by trying to incorporate a clock pulse generator whose effectiveness is determined by implementing all three types of pulses generated in a single design. The additional design is incorporated within the proposed structure to devise a configurable edge triggered flip-flop. The manifold advantage being that 9 different types of flip-flop designs usually done separately can be incorporated within one. This means the proposed ECFF can be reconfigured to falling edge D/T/JK FF, rising edge D/T/JK FF and dual edge D/T/JK FF using the same circuit. The simulation results of falling/rising/dual edge triggered JK FF is shown in Figure <ref>. The performance of the proposed ECFF is shown in Table <ref>. The existing dual edge triggered flip-flops are compared with the proposed ECFF which can be configured to falling edge D/T/JK FF, rising edge D/T/JK FF and dual edge D/T/JK FF using the same circuit. This means 9 different functions can be produced using the same ECFF whereas the existing flip-flops can produce only one function. 


 














§ REALIZATION OF EDGE CONFIGURABLE N-BIT COUNTER/SHIFT REGISTER

In this section, the edge configurable flip-flop is used as a basic element to realize the proposed counter/ shift register. In order to synchronize the clock of the proposed configurable counter/shift register one additional delay control circuit (DCC) (Figure <ref>) is introduced. The additional delay circuitry is used to delay the clock (fixing C3=0) by one complete cycle so that the clock can be synchronized. The function of the delay circuit is shown in Table <ref>.

The proposed configurable 2-bit counter/ shift register is shown in Figure <ref>. It can be configured to a shift register or a counter as necessary. The proposed configurable 2-bit counter/ shift register has 7 control inputs (C1, C1, C2, C2, C3, C4, C5), two primary inputs (A, B) and two primary outputs (Q_0 and Q_1). The basic unit of the proposed counter/ shift register is the edge configurable flip-flop (CFF). A counter can be constructed using T or JK FF whereas shift register can be constructed using D FF. In the proposed 2-bit counter/ shift register, C1 and C2 inputs are used to adjust the CFF module to the required flip-flop whereas C5 input defines the behaviour of the circuit i.e. if C5=0 then the circuit behaves as a shift register otherwise it behaves as a counter. The two ECFF (configured as a D FF; C1=C1=0, C2=C2=0 and C5=0) are cascaded to design the proposed 2-bit shift register. 

The 3-bit design of the proposed configurable counter/ shift register is shown in Figure <ref>. To synchronize the input and output of the 3-bit configurable counter/ shift register circuit, additional three delay control circuits need to be added to the ECFF module. The top delay control circuit is used to synchronize the output of the first module with rest modules whereas the bottom two delay control circuits are used to synchronize clock signal (CLK) of the proposed circuit. In the case of a 3-bit proposed edge configurable counter/ shift register, if C5=C6=0 then the circuit behaves as a shift register whereas if C5=C6=1 then the circuit will behave as a counter. Similarly, by cascading n-CFF modules, we can construct n-bit edge configurable counter/ shift register as shown in Figure <ref> which can be configured to (dual/rising/falling) edge shift register as well as (dual/rising/falling) edge counter. The QCA representation of the proposed n-bit edge configurable counter/ shift register is shown in Figure <ref>. The performance of the proposed edge configurable counter/shift register is shown in Table <ref>. If we want to construct a shift register then there is no extra space requirement for the proposed configurable counter/ shift register due to its configurable nature hence it is more cost effective than the conventional designs. The main benefit of the configurable n-bit counter/shift register is that the same circuit can be configured to six different forms, (Dual/Falling/Rising) counter as well as (Dual/Falling/Rising) shift register. 



















§ SIMULATION SETUP

QCADesigner (version 2.0.3) <cit.> has been used to verify the functional correctness of all the proposed QCA designs using both coherence
vector and bistable approximation simulation engines using all the default parameters. 























§ CONCLUSION

This paper attempts for the very first time, to design a level triggered configurable flip-flop (CFF) which can be used as a D, T and JK flip-flop as per the requirement. A 1-bit RAM is designed considering CFF as a basic element. Moreover, an edge configurable flip-flop (ECFF) is designed with the help of a clock pulse generator (CPG). The CPG can produce three different (rising/falling and dual) types of pulses using the same circuit. The edge configurable flip-flop (ECFF) can be used as 9 different flip-flops controlling only single module. An efficient edge configurable n-bit counter/shift register is proposed which can be configured as an n-bit counter or n-bit shift register as per the requirement. 


§ ACKNOWLEDGEMENT

This research is supported by the Department of Electronics and Information Technology, Ministry of Communications and IT, Government of India under the Visvesvaraya PhD Scheme administered by Media Lab Asia.
spmpsci

