Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets
Akhilesh Jaiswal Indranil Chakraborty Kaushik Roy

	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
		

	
	
	Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets
    Akhilesh Jaiswal,
		Indranil Chakraborty
		and Kaushik Roy, Fellow, IEEE
		A. Jaiswal, I. Chakraborty and K. Roy are with the School
			of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
			, 47907 USA e-mail: jaiswal@purdue.edu; ichakra@purdue.edu;  kaushik@purdue.edu. The work was supported in part by, C-SPIN, a MARCO and DARPA sponsored StarNet center, by the Semiconductor Research Corporation, the National Science Foundation, Intel Corporation and by the DoD Vannevar Bush Fellowship.
		
    January 27, 2017
==============================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================



	
	
	
	
Voltage driven magneto-electric (ME) switching of ferro-magnets has shown potential for future low-energy spintronic memories. In this paper, we first analyze two different ME devices viz. ME-MTJ and ME-XNOR device with respect to writability, readability and switching speed. Our analysis is based on a coupled magnetization dynamics and electron transport model. Subsequently, we show that the decoupled read/write path of ME-MTJs can be utilized to construct an energy-efficient dual port memory. Further, we also propose a novel content addressable memory (CAM) exploiting the compact XNOR operation enabled by ME-XNOR device.

	
	
	
	
		Magneto-electric effect, CAM, dual port, memory, XNOR, LLG.
	
	
	
	

	
	
	
	
	
	
	
	
	
	
	
	

	

	
	

§ INTRODUCTION

	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	Magneto-resistive memories based on current driven Spin Transfer Torque (STT) <cit.>, have attracted immense research interest due to their non-volatility, almost unlimited endurance and area-efficiency <cit.>. However, STT based memories suffer from inherent low switching speed and high write-energy consumption <cit.>. Recently, voltage induced Magneto-Electric (ME) effect,  has shown potential for fast and energy-efficient switching of ferromagnets <cit.>. 
	
Many device proposals for memory <cit.>, <cit.> and logic applications <cit.> of the ME effect can be found in the literature.  In this paper, we explore two different ME devices  - i) ME magnetic tunnel junctions (ME-MTJs) <cit.> and ii) ME-XNOR device <cit.>. We analyze the ME devices with respect to writability, readability and switching speed using a coupled magnetization dynamics and transport model. Further, we propose two novel energy-efficient memories - i) a dual port memory and ii) a content addressable memory (CAM), using the aforementioned ME devices.
	

	

	
	

§  ME EFFECT

Various single phase <cit.> and composite multi-ferroic materials <cit.> have been experimentally demonstrated to exhibit the ME effect. ME effect is due to exchange bias coupling in single phase materials <cit.> and is usually due to strain coupling <cit.> in case of composite materials. For example,  in single phase BiFeO_3 due to the coupling between the ferro-electric polarization, the (anti) ferromagnetism of BiFeO_3, and the ferromagnetism of an underlying nano-magnet, the magnetization of the nano-magnet can be switched by application of an electric field <cit.>. Similarly, strain coupled magnetization reversal in PMN-PT has been proposed in <cit.> .

Note, since multi-ferroics in general and ME effect in particular, is currently an area of intense research investigation, we do not follow a particular material set or experiment. Rather, in this work, we treat the ME effect by a generic parameter referred to as the magneto-electric co-efficient (α_ME) <cit.> (explained later in the manuscript). Such an abstraction of the ME effect is justified, since the aim of the present paper is not to explore the various physical phenomenons driving the ME effect. Instead we intend to examine the implications of ME based devices with focus on memory applications. 






§  ME DEVICES UNDER CONSIDERATION




		
			

We consider two ME based devices - ME-MTJ <cit.> and ME-XNOR <cit.>, with focus on memory applications. ME-MTJ consists of an MTJ in contact with an ME oxide underlayer as shown in Fig. <ref>(a). The MTJ itself is composed of a pinned layer (PL), a free layer (FL) and an oxide spacer (usually MgO <cit.>). Depending on the orientations of the free and the pinned layer the ME-MTJ can be in either low resistance parallel (P) state or high resistance anti-parallel (AP) state.  The normalized difference in the resistances of the AP and P state is expressed by the tunnel magneto-resistance (TMR) ratio of the MTJ.

In order to switch the ME-MTJ from P (AP) to AP (P) state a positive (negative) voltage exceeding a certain threshold needs to be applied on terminal 1 in Fig. <ref>(a). 
The metal contact to the ME oxide, the ME oxide itself and the free layer of the MTJ can be considered as a capacitor. 
 On the other hand, the value stored in the ME-MTJ can be read by sensing the resistance between terminals 1 and 2. 

In Fig. <ref>(b) we show the ME-XNOR device. The ME-XNOR device consists of two free layers separated by MgO and in contact with respective ME oxides. If the voltage polarity on the terminals 1 and 2 are the same, the MTJ stack would be in P state (measured between terminals 3 and 4), while a different voltage polarity on the two terminals would lead to an AP state. Thus, the proposed device emulates an XNOR functionality. ME-XNOR device in previous works have been used for logic applications <cit.>. In this work, we would later show that ME-XNOR device can be used to construct an energy efficient CAM. In the next section, we describe the simulation model. 
		
			
		
	
	
	
	

	

§ DEVICE MODELING
	
	

	
	 Under mono-domain approximation, magnetization dynamics can be modeled using the LLG equation, proposed by Landau, Lifshitz and Gilbert, as shown below <cit.>, <cit.> 
	 	
		

	
    ∂m̂/∂ t=-|γ|  m̂× H_EFF+αm̂×∂m̂/∂ t

			

where H_EFF is the effective magnetic field. H_EFF is the sum of
	the demagnetization field <cit.>, <cit.>, the interface anisotropy field <cit.> and any other external field. m̂ is the unit magnetization vector, γ is the gyromagnetic ratio and α is the Gilbert damping constant.  The thermal noise is modeled using the Brown's model <cit.> and is accounted for by expressing a contributing field to H_EFF as  H⃗_thermal = ζ⃗√(2α kT/|γ|M_SVdt),
	
	
	
	where ζ⃗ is a vector with components that are zero mean Gaussian random variables with standard deviation of 1. V is volume of the free layer, T is the temperature and k is the Boltzmann's constant and dt is time step. The ME effect can be included in H_EFF by writing the ME field as <cit.> H_ME = 1/μ_0α_MEE = 1/μ_0α_MEV_ME/t_ME, where the magneto-electric constant is α_ME <cit.>, E is the electric field and V_ME is the voltage across the ME capacitor.  
		
	
	
	
	
	Equation (1) can be solved numerically through the Heun's method <cit.>. In addition, we used the Non Equilibrium Green's Function (NEGF) formalism <cit.> for estimation of the resistance of the MTJ stack. 
		
	

	
	

§ DEVICE CHARACTERISTICS

	
	
	

 §.§ Writability

		
	

	Writing into ME devices is accomplished by application of appropriate voltages across the ME capacitor. An important parameter that dictates the write voltage and hence the write energy is the magneto-electric co-efficient (α_ME). α_ME is the ratio of magnetic field generated per unit applied electric field <cit.>. Experimentally, various ME materials have shown α_ME in the range 0.1/c to 1/c (c is speed of light) <cit.>. In Fig. <ref> (a), we show a typical magnetization switching curve and in Fig. <ref> (b) we plot the switching probability as a function of voltage across the ME capacitor for different values of α_ME. 
	It can be seen, ME materials with high α_ME are desirable for achieving low write energy.
		
		
	

 §.§ Readability

	

	

In a memory configuration, a CMOS transistor is used in series with the storage device. Therefore, the bit-cell TMR i.e. the TMR of the device with the series resistance of the CMOS transistor is a more relevant metric for the sensing margin as opposed to the device TMR. In Fig. <ref>(a), we have shown the bit-cell TMR as a function of MgO thickness assuming a 45nm PTM <cit.> transistor in series with varying W/L (width/length) ratios. It can be seen a higher value of MgO thickness is required to increase the bit-cell TMR and reduce the parasitic effect of the transistor series resistance <cit.>. For the ME devices, due to the decoupled read/write paths, the thickness of the MgO oxide can be increased without degrading the write efficiency (which is dictated by the ME oxide). Thus, the decoupled read/write paths for ME devices allows for better sensing due to increased bit-cell TMR.
	
		

	
						
		
		


		
	

 §.§ Switching Speed
	
			
			
Though, a detailed switching dynamics for ME devices is still under research investigation <cit.>, yet it is expected that ME switching would be much faster as compared to STT switching <cit.>. This is because ME switching dynamics behaves as if the magnetization direction is being switched by an external field which does not require an incubation delay  <cit.> to initiate the switching process. In Fig. <ref>(b) we have shown a typical 3D trajectory of the ME switching mechanism, based on the model presented in section IV. It can be seen if the applied electric field is strong enough, the magnetization  vector starts switching without any initial incubation delay. In our simulations for an α_ME of 1/c, complete reversal was obtained within 500ps.
	
	
		

	
	

§ ME MEMORY DESIGN

	
	
		

			
	

 §.§ ME Dual Port Memory
	
	
	
	
			
	
The proposed dual port memory using ME-MTJs is shown in Fig. <ref>. Each bit-cell consists of one ME-MTJ and two transistors. The transistor connected to WWLs are the write transistors and those connected to RWLs are the read transistors. Data can be written into the ME-MTJs by activating the write transistors of a particular row and applying appropriate write voltages (positive or negative) on WBLs. Similarly, for reading out the data, the read transistors of a given row are activated and a read voltage is applied on RBLs. The current flowing through the bit-cell is then compared with a reference to sense the current state of the ME-MTJ. 

A dual port memory is characterized by simultaneous read and write operations i.e. while one row of the memory array is being read simultaneously another row of the memory array can be written into, thereby, improving the memory throughput <cit.>. The dual port nature of the proposed ME-MTJ memory can be explained as follows. 

Let us consider row-1 in Fig. <ref> is being written into. The write transistors corresponding to row-1 would be activated and by application of proper voltages on WBLs, a P or an AP state can be written into the ME-MTJs. 
Simultaneously, the read transistors corresponding to row-2 are activated and by sensing the current flowing through the RBLs, the state of the ME-MTJs connected to row-2 can be sensed. 
Our simulations indicate, write energy consumption per bit of 0.072 fJ for α_ME = 1/c and read energy consumption of 1.3fJ for read voltage of 200mV and read time of 0.5ns. For the present proposal ME switching enables two orders of magnitude improvement in write energy and 8x improvement in switching speed as compared to STT based MTJs <cit.>, in addition to improved TMR and throughput.






	

 §.§ ME CAM
	
	


The ME-XNOR based CAM cell is shown in Fig. 5 (a). The function of M1 is to selectively provide the ME-oxide capacitor with a ground connection when Data Input Line (D_in) is activated. In the read circuit, a reference MTJ (Ref_MTJ) forms a voltage divider with the resistance of the MTJ (R_MTJ). The match signal is obtained at the drain of p-MOS M2 (denoted by node match), where a low voltage indicates a match is obtained and vice-versa. 
The node match is pre-charged to V_DD. The strengths of the n-MOS and the p-MOS transistors, connected to the match line, are adjusted such that even one activated p-MOS in a row is enough to maintain the output node in its pre-charged state.  


	The operation of the circuit can be divided into three modes: i) Write Mode, ii) Data Input Mode and iii) Read Mode. To write data in the lower (upper) ferromagnet, a write pulse corresponding to bit `1' (positive voltage) and `0' (negative voltage), respectively, is applied on the BL (D_in) with the WL (DWL) activated. If the digital bit written in the lower ferromagnet is same as the data to be matched (stored in the upper ferromagnet), the MTJ switches to low resistance state. Finally in the read mode, a read pulse of 1 V (V_READ) is applied for the read process. The output of the inverter goes `high' only if the MTJ is in low resistance state indicating that the bit written in the top magnet in mode (ii) matches the bit stored in the bottom magnet. Matching of all bits in a row turns all the p-MOS OFF and match goes low, indicating that a match is found. The write and read energy per bit was found to be 0.072 fJ and 15 fJ, respectively, indicating two orders of magnitude improvement in write energy and comparable read energy as compared to previous works as in <cit.>.
	
	


	
	

§ CONCLUSION

The prospects of achieving voltage driven switching of magnetization has renewed the interest for future low-power non-volatile spintronic memories. In this paper, we first analyze the writability, readability and switching speed of devices based on ME effect. Further, we propose two energy efficient memories using the ME devices. The proposed dual port memory allows for energy-efficient write operations in addition to faster speed, improved TMR and throughput. The proposed CAM requires lesser number of transistors due to the compact XNOR operation enabled by the ME XNOR device, resulting in an area-efficient as well as energy-efficient CAM.

	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	

	
	
	
	

	

	
	

	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	IEEEtran
	

10

url@samestyle








toshiba
H. Noguchi, K. Ikegami, K. Kushida, K. Abe, S. Itai, S. Takaya, N. Shimomura,
  J. Ito, A. Kawasumi, H. Hara et al., “7.5 a 3.3 ns-access-time
  71.2μw/mhz 1mb embedded stt-mram using physically eliminated read-disturb
  scheme and normally-off memory architecture,” in 2015 IEEE
  International Solid-State Circuits Conference-(ISSCC) Digest of Technical
  Papers.1em plus 0.5em minus 0.4emIEEE, 2015, pp. 1–3.

fong_bit
X. Fong, S. H. Choday, and K. Roy, “Bit-cell level optimization for
  non-volatile memories using magnetic tunnel junctions and spin-transfer
  torque switching,” IEEE Transactions on Nanotechnology, vol. 11,
  no. 1, pp. 172–181, 2012.

jaiswal_sca
A. Jaiswal, X. Fong, and K. Roy, “Comprehensive scaling analysis of current
  induced switching in magnetic memories based on in-plane and perpendicular
  anisotropies,” Journal on emerging and selected topics in circuits and
  systems.

Revival_ME
M. Fiebig, “Revival of the magnetoelectric effect,” Journal of Physics
  D: Applied Physics, vol. 38, no. 8, p. R123, 2005.

me_mem_1
N. Sharma, A. Marshall, J. Bird, and P. Dowben, “Magneto-electric magnetic
  tunnel junction as process adder for non-volatile memory applications,” in
  2015 IEEE Dallas Circuits and Systems Conference (DCAS), Oct 2015, pp.
  1–4.

me_mem_2
J.-M. Hu, Z. Li, L.-Q. Chen, and C.-W. Nan, “High-density magnetoresistive
  random access memory operating at ultralow voltage at room temperature,”
  Nature communications, vol. 2, p. 553, 2011.

me_logic_1
N. Sharma, A. Marshall, J. Bird, and P. Dowben, “Magneto-electric magnetic
  tunnel junction logic devices,” in Energy Efficient Electronic Systems
  (E3S), 2015 Fourth Berkeley Symposium on.1em plus 0.5em minus
  0.4emIEEE, 2015, pp. 1–3.

Intel_ME
S. Manipatruni, D. E. Nikonov, and I. A. Young, “Spin-orbit logic with
  magnetoelectric nodes: A scalable charge mediated nonvolatile spintronic
  logic,” arXiv preprint arXiv:1512.05428, 2015.

mesl
A. Jaiswal and K. Roy, “Mesl: Proposal for a non-volatile cascadable
  magneto-electric spin logic,” arXiv preprint arXiv:1611.07738, 2016.

BFO_story
R. Ramesh, “Electric field control of ferromagnetism using multi-ferroics: the
  bismuth ferrite story,” Philosophical Transactions of the Royal
  Society of London A: Mathematical, Physical and Engineering Sciences, vol.
  372, no. 2009, p. 20120437, 2014.

strain
S. Wu, J. Miao, X. Xu, W. Yan, R. Reeve, X. Zhang, and Y. Jiang,
  “Strain-mediated electric-field control of exchange bias in a
  co90fe10/bifeo3/srruo3/pmn-pt heterostructure,” Scientific reports,
  vol. 5, 2015.

ramesh_exchange
S. Wu, S. A. Cybart, D. Yi, J. M. Parker, R. Ramesh, and R. Dynes, “Full
  electric control of exchange bias,” Physical review letters, vol.
  110, no. 6, p. 067202, 2013.

determinis
J. Heron, J. Bosse, Q. He, Y. Gao, M. Trassin, L. Ye, J. Clarkson, C. Wang,
  J. Liu, S. Salahuddin et al., “Deterministic switching of
  ferromagnetism at room temperature using an electric field,” Nature,
  vol. 516, no. 7531, pp. 370–373, 2014.

ikeda
S. Ikeda, K. Miura, H. Yamamoto, K. Mizunuma, H. Gan, M. Endo, S. Kanai,
  J. Hayakawa, F. Matsukura, and H. Ohno, “A perpendicular-anisotropy
  cofeb–mgo magnetic tunnel junction,” Nature materials, vol. 9,
  no. 9, pp. 721–724, 2010.

why_mgo
W. Butler, X.-G. Zhang, T. Schulthess, and J. MacLaren, “Spin-dependent
  tunneling conductance of fe| mgo| fe sandwiches,” Physical Review B,
  vol. 63, no. 5, p. 054416, 2001.

llg
T. L. Gilbert, “A phenomenological theory of damping in ferromagnetic
  materials,” IEEE Transactions on Magnetics, vol. 40, no. 6, pp.
  3443–3449, 2004.

llg_thesis
M. d'Aquino, “Nonlinear magnetization dynamics in thin-films and
  nanoparticles,” Ph.D. dissertation, Università degli Studi di Napoli
  Federico II, 2005.

demag
Z. Wang, G. Yu, X. Liu, B. Zhang, X. Chen, and W. Lu, “Magnetization
  characteristic of ferromagnetic thin strip by measuring anisotropic
  magnetoresistance and ferromagnetic resonance,” Solid State
  Communications, vol. 182, pp. 10–13, 2014.

demag_f
A. Aharoni, “Demagnetizing factors for rectangular ferromagnetic prisms,”
  Journal of applied physics, vol. 83, no. 6, pp. 3432–3434, 1998.

Brown
W. F. Brown Jr, “Thermal fluctuations of a single-domain particle,”
  Journal of Applied Physics, vol. 34, no. 4, pp. 1319–1320, 1963.

nikonov_bench
D. E. Nikonov and I. A. Young, “Benchmarking spintronic logic devices based on
  magnetoelectric oxides,” Journal of Materials Research, vol. 29,
  no. 18, pp. 2109–2115, 2014.

Heun
W. Scholz, T. Schrefl, and J. Fidler, “Micromagnetic simulation of thermally
  activated switching in fine particles,” Journal of Magnetism and
  Magnetic Materials, vol. 233, no. 3, pp. 296–304, 2001.

knack
X. Fong, S. K. Gupta, N. N. Mojumder, S. H. Choday, C. Augustine, and K. Roy,
  “Knack: A hybrid spin-charge mixed-mode simulator for evaluating different
  genres of spin-transfer torque mram bit-cells,” in 2011 International
  Conference on Simulation of Semiconductor Processes and Devices.1em
  plus 0.5em minus 0.4emIEEE, 2011, pp. 51–54.

PTM
[Online] http://ptm.asu.edu/.

amiri
P. K. Amiri, Z. Zeng, P. Upadhyaya, G. Rowlands, H. Zhao, I. Krivorotov, J.-P.
  Wang, H. Jiang, J. Katine, J. Langer et al., “Low write-energy
  magnetic tunnel junctions for high-speed spin-transfer-torque mram,”
  IEEE Electron Device Letters, vol. 32, no. 1, pp. 57–59, 2011.

incubation
N. N. Mojumder and K. Roy, “Proposal for switching current reduction using
  reference layer with tilted magnetic anisotropy in magnetic tunnel junctions
  for spin-transfer torque (stt) mram,” IEEE Transactions on Electron
  Devices, vol. 59, no. 11, pp. 3054–3060, 2012.

yusung
Y. Seo, K. W. Kwon, X. Fong, and K. Roy, “High performance and
  energy-efficient on-chip cache using dual port (1r/1w) spin-orbit torque
  mram,” IEEE Journal on Emerging and Selected Topics in Circuits and
  Systems, vol. 6, no. 3, pp. 293–304, Sept 2016.

toshibaa
H. Noguchi, K. Ikegami, N. Shimomura, T. Tetsufumi, J. Ito, and S. Fujita,
  “Highly reliable and low-power nonvolatile cache memory with advanced
  perpendicular stt-mram for high-performance cpu,” in 2014 Symposium on
  VLSI Circuits Digest of Technical Papers, June 2014, pp. 1–2.

vcma_cam
K. L. Wang, H. Lee, and P. K. Amiri, “Magnetoelectric random access
  memory-based circuit design by using voltage-controlled magnetic anisotropy
  in magnetic tunnel junctions,” IEEE Transactions on Nanotechnology,
  vol. 14, no. 6, pp. 992–997, 2015.



	
	
	
	
	
	
		
	
	
	
		
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	

	