text: //-----------------------------------------------------------------
  //                     RISC-V ISA Simulator 
  //                            V1.0
  //                     Ultra-Embedded.com
  //                     Copyright 2014-2017
  //
  //                   admin@ultra-embedded.com
  //
  //                       License: BSD
  //-----------------------------------------------------------------
  //
  // Copyright (c) 2014, Ultra-Embedded.com
  // All rights reserved.
  // 
  // Redistribution and use in source and binary forms, with or without
  // modification, are permitted provided that the following conditions 
  // are met:
  //   - Redistributions of source code must retain the above copyright
  //     notice, this list of conditions and the following disclaimer.
  //   - Redistributions in binary form must reproduce the above copyright
  //     notice, this list of conditions and the following disclaimer 
  //     in the documentation and/or other materials provided with the 
  //     distribution.
  //   - Neither the name of the author nor the names of its contributors 
  //     may be used to endorse or promote products derived from this 
  //     software without specific prior written permission.
  // 
  // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
  // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
  // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 
  // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE 
  // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
  // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
  // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
  // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
  // SUCH DAMAGE.
  //-----------------------------------------------------------------
  #include <stdio.h>
  #include <string.h>
  #include <stdlib.h>
  #include <assert.h>
  
  #include "riscv_main.h"
  #include "riscv.h"
  #include "cosim_api.h"
  
  //-----------------------------------------------------------------
  // main
  //-----------------------------------------------------------------
  int main(int argc, char *argv[])
  {
      int exitcode;
  
      Riscv * sim = new Riscv();
  
      cosim::instance()->attach_cpu("sim", sim);
      cosim::instance()->attach_mem("sim", sim, 0, 0xFFFFFFFF);
  
      exitcode = riscv_main(sim, argc, argv);
  
      // Show execution stats
      sim->stats_dump();
  
      delete sim;
      sim = NULL;
  
      return exitcode;
  }
  