text: 
  #include "si4455_revb1_bidir_fixed_crc_pre10_sync4_pay8_433mhz_20kbps.hpp"
  
  // INPUT DATA
  /*
  // Crys_freq(Hz): 30000000    Crys_tol(ppm): 30    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0
  // MOD_type: 2    Rsymb(sps): 20000    Fdev(Hz): 30000    RXBW(Hz): 114000    Manchester: 1    AFC_en: 1    Rsymb_error: 0.0    Chip-Version: 2
  // RF Freq.(MHz): 433    API_TC: 28    fhst: 250000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 0
  //
  // # WB filter 2 (BW = 137.42 kHz);  NB-filter 2 (BW = 137.42 kHz)
  
  //
  // Modulation index: 3
  */
  
  
  // CONFIGURATION COMMANDS
  
  /*
  // Command:                  RF_POWER_UP
  // Description:              Command to power-up the device and select the operational mode and functionality.
  */
  #define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
  
  /*
  // Set properties:           RF_INT_CTL_ENABLE_2
  // Number of properties:     2
  // Group ID:                 0x01
  // Start ID:                 0x00
  // Default values:           0x04, 0x00,
  // Descriptions:
  //   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
  //   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
  */
  #define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x05, 0x38
  
  /*
  // Set properties:           RF_INT_CTL_CHIP_ENABLE_1
  // Number of properties:     1
  // Group ID:                 0x01
  // Start ID:                 0x03
  // Default values:           0x04,
  // Descriptions:
  //   INT_CTL_CHIP_ENABLE - Enable individual interrupt sources within the Chip Interrupt Group to generate a HW interrupt on the NIRQ output pin.
  */
  #define RF_INT_CTL_CHIP_ENABLE_1 0x11, 0x01, 0x01, 0x03, 0x6C
  
  /*
  // Set properties:           RF_FRR_CTL_A_MODE_4
  // Number of properties:     4
  // Group ID:                 0x02
  // Start ID:                 0x00
  // Default values:           0x01, 0x02, 0x09, 0x00,
  // Descriptions:
  //   FRR_CTL_A_MODE - Fast Response Register A Configuration.
  //   FRR_CTL_B_MODE - Fast Response Register B Configuration.
  //   FRR_CTL_C_MODE - Fast Response Register C Configuration.
  //   FRR_CTL_D_MODE - Fast Response Register D Configuration.
  */
  #define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x09, 0x04, 0x06, 0x08
  
  /*
  // Set properties:           RF_EZCONFIG_XO_TUNE_1
  // Number of properties:     1
  // Group ID:                 0x24
  // Start ID:                 0x03
  // Default values:           0x40,
  // Descriptions:
  //   EZCONFIG_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
  */
  #define RF_EZCONFIG_XO_TUNE_1 0x11, 0x24, 0x01, 0x03, 0x52
  
  /*
  // Command:                  RF_WRITE_TX_FIFO
  // Description:              Writes data byte(s) to the TX FIFO.
  */
  #define RF_WRITE_TX_FIFO 0x66, 0xFF, 0x04, 0x91, 0xEB, 0x96, 0x34, 0xC0, 0x19, 0x24, 0x83, 0xF4, 0x2A, 0x0C, 0x23, 0x88, 0xEE, 0x8A, 0x57, 0xEA, \
  0x3B, 0x51, 0x57, 0x70, 0xBD, 0x6C, 0x67, 0x1C, 0xAC, 0x43, 0x3C, 0x24, 0x79, 0x34, 0xAA, 0x99, 0x0C, 0x19, 0x60, 0x5D, \
  0x47, 0xAB, 0x93, 0xB6, 0x68, 0x73, 0x74, 0x80, 0x9C, 0x6F, 0x2D, 0x20, 0xB4, 0x1D, 0x5D, 0xAC, 0xFD, 0xF0, 0x9D, 0xCF, \
  0xA1, 0x96, 0xF9, 0x5E, 0x45, 0xF6, 0x10, 0xC5, 0x9E, 0x2E, 0x2D, 0x04, 0x5F, 0x5C, 0x24, 0xFF, 0xF5, 0x32, 0xDB, 0x5C, \
  0xA3, 0xB3, 0x62, 0x6D, 0xAF, 0x34, 0x54, 0xEB, 0x2F, 0x65, 0x95, 0xF2, 0xCC, 0x47, 0xD9, 0x3C, 0x4F, 0x52, 0x2C, 0xBA, \
  0x04, 0x7D, 0x63, 0x1D, 0x89, 0x9F, 0x83, 0x17, 0xD5, 0x81, 0x31, 0xB6, 0x56, 0xED
  
  /*
  // Command:                  RF_NOP
  // Description:              No Operation command.
  */
  #define RF_NOP 0x00
  
  /*
  // Command:                  RF_WRITE_TX_FIFO_1
  // Description:              Writes data byte(s) to the TX FIFO.
  */
  #define RF_WRITE_TX_FIFO_1 0x66, 0x20, 0x06, 0x11, 0x13, 0xD7, 0xBD, 0xA1, 0xCE, 0x48, 0x26, 0x3E, 0xDC, 0x4F, 0x50, 0xA1, 0x48, 0xCC, 0x33, 0xC3, \
  0xDB, 0xB8, 0x6F, 0xBB, 0x23, 0x61, 0xC6, 0x59, 0x93, 0xA9, 0xA2, 0x22, 0x37, 0x39, 0x46, 0x47, 0xCC, 0x7C, 0x8E, 0x96, \
  0x58, 0x63, 0xBF, 0xE8, 0x06, 0x66, 0x64, 0xA5, 0x4B, 0x59, 0xEB, 0xA2, 0x49, 0xE5, 0xC0, 0xBD, 0xFA, 0x96, 0x4C, 0x75, \
  0x67, 0x6E, 0x1D, 0x85, 0xA2, 0xD9, 0x38, 0xE6, 0x36, 0xE7, 0xCB, 0x4A, 0xF0, 0x24, 0xDC, 0x8C, 0x18, 0x75, 0x45, 0x03, \
  0x63, 0x47, 0xF5, 0x0A, 0xFF, 0x39, 0xB3, 0x96, 0x20, 0xBC, 0x63, 0x7F, 0xD1, 0xB6, 0x3F, 0x98, 0x4F, 0xFF, 0xC4, 0x33, \
  0xCF, 0x05, 0x9B, 0xEE, 0xC0, 0xEA, 0xDE, 0x14, 0x41, 0xF9, 0xBD, 0x34
  
  /*
  // Command:                  RF_EZCONFIG_CHECK
  // Description:              Validates the EZConfig array was written correctly.
  */
  #define RF_EZCONFIG_CHECK 0x19, 0xB6, 0x72
  
  /*
  // Command:                  RF_GPIO_PIN_CFG
  // Description:              Configures the GPIO pins.
  */
  #define RF_GPIO_PIN_CFG 0x13, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00
  
  
  namespace ZetaRfConfigs {
  
  const uint8_t Config433_FixedLength_CRC_Preamble10_Sync4_Payload8_20kbps::RadioConfigurationDataArray[]
  {
      0x07, RF_POWER_UP, \
      0x06, RF_INT_CTL_ENABLE_2, \
      0x05, RF_INT_CTL_CHIP_ENABLE_1, \
      0x08, RF_FRR_CTL_A_MODE_4, \
      0x05, RF_EZCONFIG_XO_TUNE_1, \
      0x72, RF_WRITE_TX_FIFO, \
      0x01, RF_NOP, \
      0x70, RF_WRITE_TX_FIFO_1, \
      0x03, RF_EZCONFIG_CHECK, \
      0x08, RF_GPIO_PIN_CFG, \
      0x00
  };
  
  } // namespace ZetaRfConfigs
  