text: /******************************************************************************
   *
   * Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
   *
   * Permission is hereby granted, free of charge, to any person obtaining a copy
   * of this software and associated documentation files (the "Software"), to deal
   * in the Software without restriction, including without limitation the rights
   * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   * copies of the Software, and to permit persons to whom the Software is
   * furnished to do so, subject to the following conditions:
   *
   * The above copyright notice and this permission notice shall be included in
   * all copies or substantial portions of the Software.
   *
   * Use of the Software is limited solely to applications:
   * (a) running on a Xilinx device, or
   * (b) that interact with a Xilinx device through a bus or interconnect.
   *
   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
   * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
   * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
   * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
   * SOFTWARE.
   *
   * Except as contained in this notice, the name of the Xilinx shall not be used
   * in advertising or otherwise to promote the sale, use or other dealings in
   * this Software without prior written authorization from Xilinx.
   *
   ******************************************************************************/
  
  #include "xparameters.h"
  #include "xil_cache.h"
  
  #include "platform_config.h"
  
  #ifdef STDOUT_IS_16550
   #include "xuartns550_l.h"
  
   #define UART_BAUD 9600
  #endif
  
  void
  enable_caches(void)
  {
  #ifdef __PPC__
      Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
      Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
  #elif __MICROBLAZE__
  #ifdef XPAR_MICROBLAZE_USE_ICACHE
      Xil_ICacheEnable();
  #endif
  #ifdef XPAR_MICROBLAZE_USE_DCACHE
      Xil_DCacheEnable();
  #endif
  #endif
  }
  
  void
  disable_caches(void)
  {
      Xil_DCacheDisable();
      Xil_ICacheDisable();
  }
  
  void
  init_uart(void)
  {
  #ifdef STDOUT_IS_16550
      XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
      XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
  #endif
      /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
  }
  
  void
  init_platform(void)
  {
      enable_caches();
      init_uart();
  }
  
  void
  cleanup_platform(void)
  {
      disable_caches();
  }
  