text: 
  /*******************************************************************************
  * File Name: cyfitter_cfg.c
  * 
  * PSoC Creator  4.4
  *
  * Description:
  * This file contains device initialization code.
  * Except for the user defined sections in CyClockStartupError(), this file should not be modified.
  * This file is automatically generated by PSoC Creator.
  *
  ********************************************************************************
  * Copyright (c) 2007-2020 Cypress Semiconductor.  All rights reserved.
  * You may use this file only in accordance with the license, terms, conditions, 
  * disclaimers, and limitations in the end user license agreement accompanying 
  * the software package with which this file was provided.
  ********************************************************************************/
  
  #include <string.h>
  #include "cytypes.h"
  #include "cydevice_trm.h"
  #include "cyfitter.h"
  #include "CyLib.h"
  #include "cyfitter_cfg.h"
  
  #define CY_NEED_CYCLOCKSTARTUPERROR 1
  
  
  #if defined(__C51__) || defined(__CX51__)
  	#define CYPACKED
  	#define CYPACKED_ATTR
  	#define CYALIGNED
  	#define DMAINITSEC
      #define CY_CFG_UNUSED
  	#define CY_CFG_MEMORY_BARRIER() do { } while (0)
  
  
  
  	#define CYMEMZERO(a,c) cymemzero((a),(c))
  	#define CYCONFIGCPY(d,s,c) cyconfigcpy((c),(s),(d))
  	#define CYCONFIGCPYCODE(d,s,c) cyconfigcpycode((c),(s),(d))
  #else
  	#error Unsupported toolchain
  #endif
  
  
  
  
  /* Clock startup error codes                                                   */
  #define CYCLOCKSTART_NO_ERROR    0u
  #define CYCLOCKSTART_XTAL_ERROR  1u
  #define CYCLOCKSTART_32KHZ_ERROR 2u
  #define CYCLOCKSTART_PLL_ERROR   3u
  #define CYCLOCKSTART_FLL_ERROR   4u
  #define CYCLOCKSTART_WCO_ERROR   5u
  
  
  #ifdef CY_NEED_CYCLOCKSTARTUPERROR
  /*******************************************************************************
  * Function Name: CyClockStartupError
  ********************************************************************************
  * Summary:
  *  If an error is encountered during clock configuration (crystal startup error,
  *  PLL lock error, etc.), the system will end up here.  Unless reimplemented by
  *  the customer, this function will stop in an infinite loop.
  *
  * Parameters:
  *   void
  *
  * Return:
  *   void
  *
  *******************************************************************************/
  CY_CFG_UNUSED
  static void CyClockStartupError(uint8 errorCode);
  CY_CFG_UNUSED
  static void CyClockStartupError(uint8 errorCode)
  {
      /* To remove the compiler warning if errorCode not used.                */
      errorCode = errorCode;
  
      /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */
      /* we will end up here to allow the customer to implement something to  */
      /* deal with the clock condition.                                       */
  
  #ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK
      CY_CFG_Clock_Startup_ErrorCallback();
  #else
      /*  If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */
      /* `#START CyClockStartupError` */
  
      /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.),  */
      /* we will end up here to allow the customer to implement something to  */
      /* deal with the clock condition.                                       */
  
      /* `#END` */
  
      while(1) {}
  #endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */
  }
  #endif
  
  /* IDMUX Address: CYREG_IDMUX_DRQ_CTL0 Size (bytes): 6 */
  #define BS_IDMUX_VAL ((const uint8 CYFAR *)(0x00080000u + CYAPP_ECC_OFFSET))
  
  /* IOPORT_0 Address: CYDEV_PRTDSI_PRT0_BASE Size (bytes): 7 */
  #define BS_IOPORT_0_VAL ((const uint8 CYFAR *)(0x00080008u + CYAPP_ECC_OFFSET))
  
  /* IOPORT_1 Address: CYDEV_PRTDSI_PRT1_BASE Size (bytes): 7 */
  #define BS_IOPORT_1_VAL ((const uint8 CYFAR *)(0x00080010u + CYAPP_ECC_OFFSET))
  
  /* IOPORT_2 Address: CYDEV_PRTDSI_PRT2_BASE Size (bytes): 7 */
  #define BS_IOPORT_2_VAL ((const uint8 CYFAR *)(0x00080018u + CYAPP_ECC_OFFSET))
  
  /* IOPORT_7 Address: CYDEV_PRTDSI_PRT12_BASE Size (bytes): 6 */
  #define BS_IOPORT_7_VAL ((const uint8 CYFAR *)(0x00080020u + CYAPP_ECC_OFFSET))
  
  /* IOPORT_8 Address: CYDEV_PRTDSI_PRT15_BASE Size (bytes): 7 */
  #define BS_IOPORT_8_VAL ((const uint8 CYFAR *)(0x00080028u + CYAPP_ECC_OFFSET))
  
  /* IDMUX_IRQ Address: CYREG_IDMUX_IRQ_CTL0 Size (bytes): 8 */
  #define BS_IDMUX_IRQ_VAL ((const uint8 CYFAR *)(0x00080030u + CYAPP_ECC_OFFSET))
  
  /* TMR0 Address: CYREG_TMR0_CFG0 Size (bytes): 12 */
  #define BS_TMR0_VAL ((const uint8 CYFAR *)(0x00080038u + CYAPP_ECC_OFFSET))
  
  /* TMR1 Address: CYREG_TMR1_CFG0 Size (bytes): 12 */
  #define BS_TMR1_VAL ((const uint8 CYFAR *)(0x00080044u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_5_0_CONFIG Address: CYDEV_UCFG_B0_P0_U0_BASE Size (bytes): 128 */
  #define BS_UDB_1_5_0_CONFIG_VAL ((const uint8 CYFAR *)(0x00080050u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_5_1_CONFIG Address: CYDEV_UCFG_B0_P0_U1_BASE Size (bytes): 128 */
  #define BS_UDB_1_5_1_CONFIG_VAL ((const uint8 CYFAR *)(0x000800D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_4_1_CONFIG Address: CYDEV_UCFG_B0_P1_U0_BASE Size (bytes): 128 */
  #define BS_UDB_1_4_1_CONFIG_VAL ((const uint8 CYFAR *)(0x00080150u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_4_0_CONFIG Address: CYDEV_UCFG_B0_P1_U1_BASE Size (bytes): 128 */
  #define BS_UDB_1_4_0_CONFIG_VAL ((const uint8 CYFAR *)(0x000801D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */
  #define BS_UDB_1_3_0_CONFIG_VAL ((const uint8 CYFAR *)(0x00080250u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_3_1_CONFIG Address: CYDEV_UCFG_B0_P2_U1_BASE Size (bytes): 128 */
  #define BS_UDB_1_3_1_CONFIG_VAL ((const uint8 CYFAR *)(0x000802D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */
  #define BS_UDB_1_2_1_CONFIG_VAL ((const uint8 CYFAR *)(0x00080350u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */
  #define BS_UDB_1_2_0_CONFIG_VAL ((const uint8 CYFAR *)(0x000803D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_2_1_CONFIG Address: CYDEV_UCFG_B0_P4_U0_BASE Size (bytes): 128 */
  #define BS_UDB_0_2_1_CONFIG_VAL ((const uint8 CYFAR *)(0x00080450u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_2_0_CONFIG Address: CYDEV_UCFG_B0_P4_U1_BASE Size (bytes): 128 */
  #define BS_UDB_0_2_0_CONFIG_VAL ((const uint8 CYFAR *)(0x000804D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_3_0_CONFIG Address: CYDEV_UCFG_B0_P5_U0_BASE Size (bytes): 128 */
  #define BS_UDB_0_3_0_CONFIG_VAL ((const uint8 CYFAR *)(0x00080550u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_3_1_CONFIG Address: CYDEV_UCFG_B0_P5_U1_BASE Size (bytes): 128 */
  #define BS_UDB_0_3_1_CONFIG_VAL ((const uint8 CYFAR *)(0x000805D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_4_1_CONFIG Address: CYDEV_UCFG_B0_P6_U0_BASE Size (bytes): 128 */
  #define BS_UDB_0_4_1_CONFIG_VAL ((const uint8 CYFAR *)(0x00080650u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_4_0_CONFIG Address: CYDEV_UCFG_B0_P6_U1_BASE Size (bytes): 128 */
  #define BS_UDB_0_4_0_CONFIG_VAL ((const uint8 CYFAR *)(0x000806D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_5_0_CONFIG Address: CYDEV_UCFG_B0_P7_U0_BASE Size (bytes): 128 */
  #define BS_UDB_0_5_0_CONFIG_VAL ((const uint8 CYFAR *)(0x00080750u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_5_1_CONFIG Address: CYDEV_UCFG_B0_P7_U1_BASE Size (bytes): 128 */
  #define BS_UDB_0_5_1_CONFIG_VAL ((const uint8 CYFAR *)(0x000807D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
  #define BS_UDB_1_0_0_CONFIG_VAL ((const uint8 CYFAR *)(0x00080850u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_0_1_CONFIG Address: CYDEV_UCFG_B1_P2_U1_BASE Size (bytes): 128 */
  #define BS_UDB_1_0_1_CONFIG_VAL ((const uint8 CYFAR *)(0x000808D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */
  #define BS_UDB_1_1_1_CONFIG_VAL ((const uint8 CYFAR *)(0x00080950u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_1_0_CONFIG Address: CYDEV_UCFG_B1_P3_U1_BASE Size (bytes): 128 */
  #define BS_UDB_1_1_0_CONFIG_VAL ((const uint8 CYFAR *)(0x000809D0u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_1_1_CONFIG Address: CYDEV_UCFG_B1_P4_U0_BASE Size (bytes): 128 */
  #define BS_UDB_0_1_1_CONFIG_VAL ((const uint8 CYFAR *)(0x00080A50u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_1_0_CONFIG Address: CYDEV_UCFG_B1_P4_U1_BASE Size (bytes): 128 */
  #define BS_UDB_0_1_0_CONFIG_VAL ((const uint8 CYFAR *)(0x00080AD0u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_0_0_CONFIG Address: CYDEV_UCFG_B1_P5_U0_BASE Size (bytes): 128 */
  #define BS_UDB_0_0_0_CONFIG_VAL ((const uint8 CYFAR *)(0x00080B50u + CYAPP_ECC_OFFSET))
  
  /* UDB_0_0_1_CONFIG Address: CYDEV_UCFG_B1_P5_U1_BASE Size (bytes): 128 */
  #define BS_UDB_0_0_1_CONFIG_VAL ((const uint8 CYFAR *)(0x00080BD0u + CYAPP_ECC_OFFSET))
  
  /* UWRK_B0_WRK_STATCTL_BITS Address: CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u Size (bytes): 32 */
  #define BS_UWRK_B0_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)(0x00080C50u + CYAPP_ECC_OFFSET))
  
  /* UWRK_B1_WRK_STATCTL_BITS Address: CYDEV_UWRK_UWRK8_B1_BASE + 0x00000070u Size (bytes): 32 */
  #define BS_UWRK_B1_WRK_STATCTL_BITS_VAL ((const uint8 CYFAR *)(0x00080C70u + CYAPP_ECC_OFFSET))
  
  /* UCFG_BCTL1 Address: CYREG_BCTL1_MDCLK_EN Size (bytes): 16 */
  #define BS_UCFG_BCTL1_VAL ((const uint8 CYFAR *)(0x00080C90u + CYAPP_ECC_OFFSET))
  
  /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
  #define BS_UCFG_BCTL0_VAL ((const uint8 CYFAR *)(0x00080CA0u + CYAPP_ECC_OFFSET))
  
  /* DSI0_0_HV_ROUTING Address: CYDEV_UCFG_DSI13_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_DSI0_0_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00080CB0u + CYAPP_ECC_OFFSET))
  
  /* DSISWITCH_0_1 Address: CYDEV_UCFG_DSI12_BASE Size (bytes): 128 */
  #define BS_DSISWITCH_0_1_VAL ((const uint8 CYFAR *)(0x00080D30u + CYAPP_ECC_OFFSET))
  
  /* DSI0_1_HV_ROUTING Address: CYDEV_UCFG_DSI12_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_DSI0_1_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00080DB0u + CYAPP_ECC_OFFSET))
  
  /* DSI0_2_HV_ROUTING Address: CYDEV_UCFG_DSI7_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_DSI0_2_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00080E30u + CYAPP_ECC_OFFSET))
  
  /* DSISWITCH_0_3 Address: CYDEV_UCFG_DSI6_BASE Size (bytes): 128 */
  #define BS_DSISWITCH_0_3_VAL ((const uint8 CYFAR *)(0x00080EB0u + CYAPP_ECC_OFFSET))
  
  /* DSI0_3_HV_ROUTING Address: CYDEV_UCFG_DSI6_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_DSI0_3_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00080F30u + CYAPP_ECC_OFFSET))
  
  /* DSISWITCH_0_4 Address: CYDEV_UCFG_DSI5_BASE Size (bytes): 128 */
  #define BS_DSISWITCH_0_4_VAL ((const uint8 CYFAR *)(0x00080FB0u + CYAPP_ECC_OFFSET))
  
  /* DSI0_4_HV_ROUTING Address: CYDEV_UCFG_DSI5_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_DSI0_4_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081030u + CYAPP_ECC_OFFSET))
  
  /* DSISWITCH_0_5 Address: CYDEV_UCFG_DSI4_BASE Size (bytes): 128 */
  #define BS_DSISWITCH_0_5_VAL ((const uint8 CYFAR *)(0x000810B0u + CYAPP_ECC_OFFSET))
  
  /* DSI0_5_HV_ROUTING Address: CYDEV_UCFG_DSI4_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_DSI0_5_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081130u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_0_0 Address: CYDEV_UCFG_B1_P5_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_0_0_VAL ((const uint8 CYFAR *)(0x000811B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_0_HV_ROUTING Address: CYDEV_UCFG_B1_P5_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_1_0_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081230u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_1_0 Address: CYDEV_UCFG_B1_P2_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_1_0_VAL ((const uint8 CYFAR *)(0x000812B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_2_0_HV_ROUTING Address: CYDEV_UCFG_B1_P2_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_2_0_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081330u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_0_1 Address: CYDEV_UCFG_B1_P4_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_0_1_VAL ((const uint8 CYFAR *)(0x000813B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_1_HV_ROUTING Address: CYDEV_UCFG_B1_P4_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_1_1_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081430u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_1_1 Address: CYDEV_UCFG_B1_P3_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_1_1_VAL ((const uint8 CYFAR *)(0x000814B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_2_1_HV_ROUTING Address: CYDEV_UCFG_B1_P3_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_2_1_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081530u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_0_2 Address: CYDEV_UCFG_B0_P4_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_0_2_VAL ((const uint8 CYFAR *)(0x000815B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_2_HV_ROUTING Address: CYDEV_UCFG_B0_P4_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_1_2_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081630u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_1_2 Address: CYDEV_UCFG_B0_P3_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_1_2_VAL ((const uint8 CYFAR *)(0x000816B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_2_2_HV_ROUTING Address: CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_2_2_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081730u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_0_3 Address: CYDEV_UCFG_B0_P5_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_0_3_VAL ((const uint8 CYFAR *)(0x000817B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_3_HV_ROUTING Address: CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_1_3_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081830u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_1_3 Address: CYDEV_UCFG_B0_P2_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_1_3_VAL ((const uint8 CYFAR *)(0x000818B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_2_3_HV_ROUTING Address: CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_2_3_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081930u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_0_4 Address: CYDEV_UCFG_B0_P6_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_0_4_VAL ((const uint8 CYFAR *)(0x000819B0u + CYAPP_ECC_OFFSET))
  
  /* UDB_1_4_HV_ROUTING Address: CYDEV_UCFG_B0_P6_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  #define BS_UDB_1_4_HV_ROUTING_VAL ((const uint8 CYFAR *)(0x00081A30u + CYAPP_ECC_OFFSET))
  
  /* UDBSWITCH_1_4 Address: CYDEV_UCFG_B0_P1_ROUTE_BASE Size (bytes): 128 */
  #define BS_UDBSWITCH_1_4_VAL ((const uint8 CYFAR *)(0x00081AB0u + CYAPP_ECC_OFFSET))
  
  /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */
  #define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)(0x00081B30u + CYAPP_ECC_OFFSET))
  
  /* CYDEV_CLKDIST_ACFG0_CFG0 Address: CYREG_CLKDIST_ACFG0_CFG0 Size (bytes): 4 */
  #define BS_CYDEV_CLKDIST_ACFG0_CFG0_VAL ((const uint8 CYFAR *)(0x00081B38u + CYAPP_ECC_OFFSET))
  
  
  /*******************************************************************************
  * Function Name: cfg_dma_init
  ********************************************************************************
  * Summary:
  *  This function is used to copy device configuration data from constant values
  *  stored in memory into the proper chip configuration registers using DMA.  It
  *  pulls data out of the CFG_TD_LISTs to know exactly how/what to configure.
  *
  * Parameters:  
  *   void
  *
  * Return:
  *   void
  *
  *******************************************************************************/
  static void cfg_dma_init(void);
  static void cfg_dma_init(void)
  {
  	/* TD structure for big-endian systems. Requires 2-byte endian swap */
  	CYPACKED struct td_t {
  		uint16 size;
  		uint8 flags;
  		uint8 next_td_ptr;
  		uint16 src;
  		uint16 dest;
  	} CYPACKED_ATTR;
  
  	/* UDB_2_4_HV_ROUTING Address: CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_UDB_2_4_HV_ROUTING_VAL[] = {
  		0x00u, 0x10u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x00u, 
  		0x04u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x81u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x80u, 0x20u, 0x02u, 0x90u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x54u, 0x00u, 0x2Bu, 0x00u, 0x4Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x59u, 0x00u, 0x76u, 0x00u, 0x1Eu, 0x00u, 
  		0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* UDBSWITCH_0_5 Address: CYDEV_UCFG_B0_P7_ROUTE_BASE Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_UDBSWITCH_0_5_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x28u, 0x40u, 0x00u, 0x02u, 0x00u, 0x00u, 0x90u, 0x00u, 0xA0u, 0x00u, 
  		0x02u, 0x00u, 0x00u, 0x00u, 0x0Au, 0x01u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x20u, 0x80u, 0x48u, 0x00u, 0x00u, 0x00u, 0x00u, 0xA0u, 0x10u, 0x08u, 0x01u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x50u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x41u, 0x00u, 0x20u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x00u, 0x40u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, 0x02u, 0x04u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x40u, 0x02u, 0x02u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* UDB_1_5_HV_ROUTING Address: CYDEV_UCFG_B0_P7_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_UDB_1_5_HV_ROUTING_VAL[] = {
  		0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x70u, 0x00u, 0xF8u, 0x00u, 0xF1u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x00u, 0xF0u, 0x00u, 0xB0u, 0x00u, 
  		0xE0u, 0x00u, 0x30u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* UDBSWITCH_1_5 Address: CYDEV_UCFG_B0_P0_ROUTE_BASE Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_UDBSWITCH_1_5_VAL[] = {
  		0x34u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x81u, 0x00u, 0x00u, 0x12u, 0x00u, 0x00u, 
  		0x88u, 0x00u, 0x20u, 0x22u, 0x00u, 0x00u, 0x00u, 0x80u, 0x04u, 0x00u, 0x40u, 0x00u, 0x00u, 0x80u, 0x20u, 0x00u, 
  		0x00u, 0x10u, 0x24u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 
  		0x08u, 0x00u, 0x60u, 0x80u, 0x00u, 0x04u, 0x20u, 0x82u, 0x14u, 0x00u, 0x00u, 0x80u, 0x04u, 0x00u, 0x03u, 0x00u, 
  		0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x08u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x48u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* UDB_2_5_HV_ROUTING Address: CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_UDB_2_5_HV_ROUTING_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x26u, 0x00u, 0x59u, 0x00u, 0x8Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x81u, 0x00u, 0xFEu, 0x00u, 0xCEu, 0x00u, 
  		0x07u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSI3_0_HV_ROUTING Address: CYDEV_UCFG_DSI9_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSI3_0_HV_ROUTING_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x01u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSISWITCH_1_1 Address: CYDEV_UCFG_DSI8_BASE Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSISWITCH_1_1_VAL[] = {
  		0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSI3_1_HV_ROUTING Address: CYDEV_UCFG_DSI8_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSI3_1_HV_ROUTING_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xA0u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSISWITCH_1_2 Address: CYDEV_UCFG_DSI3_BASE Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSISWITCH_1_2_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSI3_2_HV_ROUTING Address: CYDEV_UCFG_DSI3_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSI3_2_HV_ROUTING_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 
  		0x00u, 0x00u, 0x20u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x10u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSISWITCH_1_3 Address: CYDEV_UCFG_DSI2_BASE Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSISWITCH_1_3_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 
  		0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSI3_3_HV_ROUTING Address: CYDEV_UCFG_DSI2_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSI3_3_HV_ROUTING_VAL[] = {
  		0x00u, 0x00u, 0x01u, 0x00u, 0x0Au, 0x80u, 0x00u, 0x00u, 0x20u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x20u, 0x80u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x20u, 0x00u, 0x60u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x20u, 0x00u, 0x50u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSISWITCH_1_4 Address: CYDEV_UCFG_DSI1_BASE Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSISWITCH_1_4_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSI3_4_HV_ROUTING Address: CYDEV_UCFG_DSI1_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSI3_4_HV_ROUTING_VAL[] = {
  		0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSISWITCH_1_5 Address: CYDEV_UCFG_DSI0_BASE Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSISWITCH_1_5_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x02u, 0x00u, 0x80u, 0x00u, 0x00u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* DSI3_5_HV_ROUTING Address: CYDEV_UCFG_DSI0_BASE + 0x00000080u Size (bytes): 128 */
  	DMAINITSEC static const uint8 CYCODE BS_DSI3_5_HV_ROUTING_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 
  		0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
  
  	/* PHUB_CH1_CFGMEM_CFG0/1 initialization data */
  	DMAINITSEC static const uint8 CYCODE CH1_ADDR_DATA0[] = { 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u };
  
  	/* PHUB_CH2_CFGMEM_CFG0/1 initialization data */
  	DMAINITSEC static const uint8 CYCODE CH2_ADDR_DATA0[] = { 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u };
  
  	/* PHUB_CH4_CFGMEM_CFG0/1 initialization data */
  	DMAINITSEC static const uint8 CYCODE CH4_ADDR_DATA0[] = { 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x01u, 0x00u };
  
  	/* PHUB_CH5_CFGMEM_CFG0/1 initialization data */
  	DMAINITSEC static const uint8 CYCODE CH5_ADDR_DATA0[] = { 0x01u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u };
  
  	/* PHUB_CH6_CFGMEM_CFG0/1 initialization data */
  	DMAINITSEC static const uint8 CYCODE CH6_ADDR_DATA0[] = { 0x01u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x01u, 0x00u };
  
  	/* Initialization data for each DMA channel's TD registers */
  	DMAINITSEC static const uint8 CYCODE DMA_TD_START_CMD[] = { 0x01u, 0x00u, 0x00u, 0x00u, 0x01u };
  
  	CYALIGNED static uint32 CYXDATA DMA_ZERO_VAL;
  
  	/* This table holds all of the initialization data necessary for the DMA
  	   process to transfer data from the source location to the destination. */
  	DMAINITSEC static const struct td_t CYCODE CFG_TD_LIST0[] = {
  		/* Size, Flags, Next, Source, Destination */
  		{ 8u, 0x23u, 0x02u, (uint16)(uint32)(CH1_ADDR_DATA0), (uint16)(CYREG_PHUB_CFGMEM1_CFG0) },	/* TD 1 */
  		{ 8u, 0x23u, 0x03u, (uint16)(uint32)(CH2_ADDR_DATA0), (uint16)(CYREG_PHUB_CFGMEM2_CFG0) },	/* TD 2 */
  		{ 8u, 0x23u, 0x04u, (uint16)(uint32)(CH4_ADDR_DATA0), (uint16)(CYREG_PHUB_CFGMEM4_CFG0) },	/* TD 3 */
  		{ 8u, 0x23u, 0x05u, (uint16)(uint32)(CH5_ADDR_DATA0), (uint16)(CYREG_PHUB_CFGMEM5_CFG0) },	/* TD 4 */
  		{ 8u, 0x23u, 0x06u, (uint16)(uint32)(CH6_ADDR_DATA0), (uint16)(CYREG_PHUB_CFGMEM6_CFG0) },	/* TD 5 */
  		{ 5u, 0x23u, 0x07u, (uint16)(uint32)(DMA_TD_START_CMD), (uint16)(CYREG_PHUB_CH1_BASIC_CFG) },	/* TD 6 */
  		{ 5u, 0x23u, 0x08u, (uint16)(uint32)(DMA_TD_START_CMD), (uint16)(CYREG_PHUB_CH2_BASIC_CFG) },	/* TD 7 */
  		{ 5u, 0x23u, 0x09u, (uint16)(uint32)(DMA_TD_START_CMD), (uint16)(CYREG_PHUB_CH4_BASIC_CFG) },	/* TD 8 */
  		{ 5u, 0x23u, 0x0Au, (uint16)(uint32)(DMA_TD_START_CMD), (uint16)(CYREG_PHUB_CH5_BASIC_CFG) },	/* TD 9 */
  		{ 5u, 0x23u, 0xFEu, (uint16)(uint32)(DMA_TD_START_CMD), (uint16)(CYREG_PHUB_CH6_BASIC_CFG) },	/* TD 10 */
  		{ 64u, 0x22u, 0xFEu, (uint16)(uint32)(&DMA_ZERO_VAL), (uint16)(CYREG_PRT3_DR) },	/* TD 11 */
  		{ 128u, 0x22u, 0x0Du, (uint16)(uint32)(&DMA_ZERO_VAL), (uint16)(CYDEV_UCFG_DSI7_BASE) },	/* TD 12 */
  		{ 128u, 0x22u, 0x0Eu, (uint16)(uint32)(&DMA_ZERO_VAL), (uint16)(CYDEV_UCFG_DSI9_BASE) },	/* TD 13 */
  		{ 128u, 0x22u, 0xFEu, (uint16)(uint32)(&DMA_ZERO_VAL), (uint16)(CYDEV_UCFG_DSI13_BASE) },	/* TD 14 */
  		{ 128u, 0x23u, 0x10u, (uint16)(uint32)(BS_UDB_2_4_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE + 0x00000080u) },	/* TD 15 */
  		{ 128u, 0x23u, 0x11u, (uint16)(uint32)(BS_UDBSWITCH_0_5_VAL), (uint16)(CYDEV_UCFG_B0_P7_ROUTE_BASE) },	/* TD 16 */
  		{ 128u, 0x23u, 0x12u, (uint16)(uint32)(BS_UDB_1_5_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P7_ROUTE_BASE + 0x00000080u) },	/* TD 17 */
  		{ 128u, 0x23u, 0x13u, (uint16)(uint32)(BS_UDBSWITCH_1_5_VAL), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE) },	/* TD 18 */
  		{ 128u, 0x23u, 0x14u, (uint16)(uint32)(BS_UDB_2_5_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P0_ROUTE_BASE + 0x00000080u) },	/* TD 19 */
  		{ 128u, 0x23u, 0x15u, (uint16)(uint32)(BS_DSI3_0_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI9_BASE + 0x00000080u) },	/* TD 20 */
  		{ 128u, 0x23u, 0x16u, (uint16)(uint32)(BS_DSISWITCH_1_1_VAL), (uint16)(CYDEV_UCFG_DSI8_BASE) },	/* TD 21 */
  		{ 128u, 0x23u, 0x17u, (uint16)(uint32)(BS_DSI3_1_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI8_BASE + 0x00000080u) },	/* TD 22 */
  		{ 128u, 0x23u, 0x18u, (uint16)(uint32)(BS_DSISWITCH_1_2_VAL), (uint16)(CYDEV_UCFG_DSI3_BASE) },	/* TD 23 */
  		{ 128u, 0x23u, 0x19u, (uint16)(uint32)(BS_DSI3_2_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI3_BASE + 0x00000080u) },	/* TD 24 */
  		{ 128u, 0x23u, 0x1Au, (uint16)(uint32)(BS_DSISWITCH_1_3_VAL), (uint16)(CYDEV_UCFG_DSI2_BASE) },	/* TD 25 */
  		{ 128u, 0x23u, 0x1Bu, (uint16)(uint32)(BS_DSI3_3_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI2_BASE + 0x00000080u) },	/* TD 26 */
  		{ 128u, 0x23u, 0x1Cu, (uint16)(uint32)(BS_DSISWITCH_1_4_VAL), (uint16)(CYDEV_UCFG_DSI1_BASE) },	/* TD 27 */
  		{ 128u, 0x23u, 0x1Du, (uint16)(uint32)(BS_DSI3_4_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI1_BASE + 0x00000080u) },	/* TD 28 */
  		{ 128u, 0x23u, 0x1Eu, (uint16)(uint32)(BS_DSISWITCH_1_5_VAL), (uint16)(CYDEV_UCFG_DSI0_BASE) },	/* TD 29 */
  		{ 128u, 0x23u, 0xFEu, (uint16)(uint32)(BS_DSI3_5_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI0_BASE + 0x00000080u) },	/* TD 30 */
  		{ 7u, 0x23u, 0x20u, (uint16)(uint32)(BS_IOPORT_0_VAL), (uint16)(CYDEV_PRTDSI_PRT0_BASE) },	/* TD 31 */
  		{ 7u, 0x23u, 0x21u, (uint16)(uint32)(BS_IOPORT_1_VAL), (uint16)(CYDEV_PRTDSI_PRT1_BASE) },	/* TD 32 */
  		{ 7u, 0x23u, 0x22u, (uint16)(uint32)(BS_IOPORT_2_VAL), (uint16)(CYDEV_PRTDSI_PRT2_BASE) },	/* TD 33 */
  		{ 6u, 0x23u, 0x23u, (uint16)(uint32)(BS_IOPORT_7_VAL), (uint16)(CYDEV_PRTDSI_PRT12_BASE) },	/* TD 34 */
  		{ 7u, 0x23u, 0x24u, (uint16)(uint32)(BS_IOPORT_8_VAL), (uint16)(CYDEV_PRTDSI_PRT15_BASE) },	/* TD 35 */
  		{ 12u, 0x23u, 0x25u, (uint16)(uint32)(BS_TMR0_VAL), (uint16)(CYREG_TMR0_CFG0) },	/* TD 36 */
  		{ 12u, 0x23u, 0x26u, (uint16)(uint32)(BS_TMR1_VAL), (uint16)(CYREG_TMR1_CFG0) },	/* TD 37 */
  		{ 32u, 0x23u, 0x27u, (uint16)(uint32)(BS_UWRK_B0_WRK_STATCTL_BITS_VAL), (uint16)(CYDEV_UWRK_UWRK8_B0_BASE + 0x00000070u) },	/* TD 38 */
  		{ 32u, 0x23u, 0xFEu, (uint16)(uint32)(BS_UWRK_B1_WRK_STATCTL_BITS_VAL), (uint16)(CYDEV_UWRK_UWRK8_B1_BASE + 0x00000070u) },	/* TD 39 */
  		{ 8u, 0x23u, 0x29u, (uint16)(uint32)(BS_IDMUX_IRQ_VAL), (uint16)(CYREG_IDMUX_IRQ_CTL0) },	/* TD 40 */
  		{ 128u, 0x23u, 0x2Au, (uint16)(uint32)(BS_UDB_1_5_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P0_U0_BASE) },	/* TD 41 */
  		{ 128u, 0x23u, 0x2Bu, (uint16)(uint32)(BS_UDB_1_5_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P0_U1_BASE) },	/* TD 42 */
  		{ 128u, 0x23u, 0x2Cu, (uint16)(uint32)(BS_UDB_1_4_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P1_U0_BASE) },	/* TD 43 */
  		{ 128u, 0x23u, 0x2Du, (uint16)(uint32)(BS_UDB_1_4_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P1_U1_BASE) },	/* TD 44 */
  		{ 128u, 0x23u, 0x2Eu, (uint16)(uint32)(BS_UDB_1_3_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P2_U0_BASE) },	/* TD 45 */
  		{ 128u, 0x23u, 0x2Fu, (uint16)(uint32)(BS_UDB_1_3_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P2_U1_BASE) },	/* TD 46 */
  		{ 128u, 0x23u, 0x30u, (uint16)(uint32)(BS_UDB_1_2_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P3_U0_BASE) },	/* TD 47 */
  		{ 128u, 0x23u, 0x31u, (uint16)(uint32)(BS_UDB_1_2_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P3_U1_BASE) },	/* TD 48 */
  		{ 128u, 0x23u, 0x32u, (uint16)(uint32)(BS_UDB_0_2_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P4_U0_BASE) },	/* TD 49 */
  		{ 128u, 0x23u, 0x33u, (uint16)(uint32)(BS_UDB_0_2_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P4_U1_BASE) },	/* TD 50 */
  		{ 128u, 0x23u, 0x34u, (uint16)(uint32)(BS_UDB_0_3_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P5_U0_BASE) },	/* TD 51 */
  		{ 128u, 0x23u, 0x35u, (uint16)(uint32)(BS_UDB_0_3_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P5_U1_BASE) },	/* TD 52 */
  		{ 128u, 0x23u, 0x36u, (uint16)(uint32)(BS_UDB_0_4_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P6_U0_BASE) },	/* TD 53 */
  		{ 128u, 0x23u, 0x37u, (uint16)(uint32)(BS_UDB_0_4_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P6_U1_BASE) },	/* TD 54 */
  		{ 128u, 0x23u, 0x38u, (uint16)(uint32)(BS_UDB_0_5_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P7_U0_BASE) },	/* TD 55 */
  		{ 128u, 0x23u, 0x39u, (uint16)(uint32)(BS_UDB_0_5_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B0_P7_U1_BASE) },	/* TD 56 */
  		{ 128u, 0x23u, 0x3Au, (uint16)(uint32)(BS_UDB_1_0_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P2_U0_BASE) },	/* TD 57 */
  		{ 128u, 0x23u, 0x3Bu, (uint16)(uint32)(BS_UDB_1_0_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P2_U1_BASE) },	/* TD 58 */
  		{ 128u, 0x23u, 0x3Cu, (uint16)(uint32)(BS_UDB_1_1_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P3_U0_BASE) },	/* TD 59 */
  		{ 128u, 0x23u, 0x3Du, (uint16)(uint32)(BS_UDB_1_1_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P3_U1_BASE) },	/* TD 60 */
  		{ 128u, 0x23u, 0x3Eu, (uint16)(uint32)(BS_UDB_0_1_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P4_U0_BASE) },	/* TD 61 */
  		{ 128u, 0x23u, 0x3Fu, (uint16)(uint32)(BS_UDB_0_1_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P4_U1_BASE) },	/* TD 62 */
  		{ 128u, 0x23u, 0x40u, (uint16)(uint32)(BS_UDB_0_0_0_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P5_U0_BASE) },	/* TD 63 */
  		{ 128u, 0x23u, 0x41u, (uint16)(uint32)(BS_UDB_0_0_1_CONFIG_VAL), (uint16)(CYDEV_UCFG_B1_P5_U1_BASE) },	/* TD 64 */
  		{ 16u, 0x23u, 0x42u, (uint16)(uint32)(BS_UCFG_BCTL1_VAL), (uint16)(CYREG_BCTL1_MDCLK_EN) },	/* TD 65 */
  		{ 16u, 0x23u, 0x43u, (uint16)(uint32)(BS_UCFG_BCTL0_VAL), (uint16)(CYREG_BCTL0_MDCLK_EN) },	/* TD 66 */
  		{ 128u, 0x23u, 0x44u, (uint16)(uint32)(BS_DSI0_0_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI13_BASE + 0x00000080u) },	/* TD 67 */
  		{ 128u, 0x23u, 0x45u, (uint16)(uint32)(BS_DSISWITCH_0_1_VAL), (uint16)(CYDEV_UCFG_DSI12_BASE) },	/* TD 68 */
  		{ 128u, 0x23u, 0x46u, (uint16)(uint32)(BS_DSI0_1_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI12_BASE + 0x00000080u) },	/* TD 69 */
  		{ 128u, 0x23u, 0x47u, (uint16)(uint32)(BS_DSI0_2_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI7_BASE + 0x00000080u) },	/* TD 70 */
  		{ 128u, 0x23u, 0x48u, (uint16)(uint32)(BS_DSISWITCH_0_3_VAL), (uint16)(CYDEV_UCFG_DSI6_BASE) },	/* TD 71 */
  		{ 128u, 0x23u, 0x49u, (uint16)(uint32)(BS_DSI0_3_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI6_BASE + 0x00000080u) },	/* TD 72 */
  		{ 128u, 0x23u, 0x4Au, (uint16)(uint32)(BS_DSISWITCH_0_4_VAL), (uint16)(CYDEV_UCFG_DSI5_BASE) },	/* TD 73 */
  		{ 128u, 0x23u, 0x4Bu, (uint16)(uint32)(BS_DSI0_4_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI5_BASE + 0x00000080u) },	/* TD 74 */
  		{ 128u, 0x23u, 0x4Cu, (uint16)(uint32)(BS_DSISWITCH_0_5_VAL), (uint16)(CYDEV_UCFG_DSI4_BASE) },	/* TD 75 */
  		{ 128u, 0x23u, 0x4Du, (uint16)(uint32)(BS_DSI0_5_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_DSI4_BASE + 0x00000080u) },	/* TD 76 */
  		{ 128u, 0x23u, 0x4Eu, (uint16)(uint32)(BS_UDBSWITCH_0_0_VAL), (uint16)(CYDEV_UCFG_B1_P5_ROUTE_BASE) },	/* TD 77 */
  		{ 128u, 0x23u, 0x4Fu, (uint16)(uint32)(BS_UDB_1_0_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B1_P5_ROUTE_BASE + 0x00000080u) },	/* TD 78 */
  		{ 128u, 0x23u, 0x50u, (uint16)(uint32)(BS_UDBSWITCH_1_0_VAL), (uint16)(CYDEV_UCFG_B1_P2_ROUTE_BASE) },	/* TD 79 */
  		{ 128u, 0x23u, 0x51u, (uint16)(uint32)(BS_UDB_2_0_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B1_P2_ROUTE_BASE + 0x00000080u) },	/* TD 80 */
  		{ 128u, 0x23u, 0x52u, (uint16)(uint32)(BS_UDBSWITCH_0_1_VAL), (uint16)(CYDEV_UCFG_B1_P4_ROUTE_BASE) },	/* TD 81 */
  		{ 128u, 0x23u, 0x53u, (uint16)(uint32)(BS_UDB_1_1_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B1_P4_ROUTE_BASE + 0x00000080u) },	/* TD 82 */
  		{ 128u, 0x23u, 0x54u, (uint16)(uint32)(BS_UDBSWITCH_1_1_VAL), (uint16)(CYDEV_UCFG_B1_P3_ROUTE_BASE) },	/* TD 83 */
  		{ 128u, 0x23u, 0x55u, (uint16)(uint32)(BS_UDB_2_1_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B1_P3_ROUTE_BASE + 0x00000080u) },	/* TD 84 */
  		{ 128u, 0x23u, 0x56u, (uint16)(uint32)(BS_UDBSWITCH_0_2_VAL), (uint16)(CYDEV_UCFG_B0_P4_ROUTE_BASE) },	/* TD 85 */
  		{ 128u, 0x23u, 0x57u, (uint16)(uint32)(BS_UDB_1_2_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P4_ROUTE_BASE + 0x00000080u) },	/* TD 86 */
  		{ 128u, 0x23u, 0x58u, (uint16)(uint32)(BS_UDBSWITCH_1_2_VAL), (uint16)(CYDEV_UCFG_B0_P3_ROUTE_BASE) },	/* TD 87 */
  		{ 128u, 0x23u, 0x59u, (uint16)(uint32)(BS_UDB_2_2_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P3_ROUTE_BASE + 0x00000080u) },	/* TD 88 */
  		{ 128u, 0x23u, 0x5Au, (uint16)(uint32)(BS_UDBSWITCH_0_3_VAL), (uint16)(CYDEV_UCFG_B0_P5_ROUTE_BASE) },	/* TD 89 */
  		{ 128u, 0x23u, 0x5Bu, (uint16)(uint32)(BS_UDB_1_3_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P5_ROUTE_BASE + 0x00000080u) },	/* TD 90 */
  		{ 128u, 0x23u, 0x5Cu, (uint16)(uint32)(BS_UDBSWITCH_1_3_VAL), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE) },	/* TD 91 */
  		{ 128u, 0x23u, 0x5Du, (uint16)(uint32)(BS_UDB_2_3_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P2_ROUTE_BASE + 0x00000080u) },	/* TD 92 */
  		{ 128u, 0x23u, 0x5Eu, (uint16)(uint32)(BS_UDBSWITCH_0_4_VAL), (uint16)(CYDEV_UCFG_B0_P6_ROUTE_BASE) },	/* TD 93 */
  		{ 128u, 0x23u, 0x5Fu, (uint16)(uint32)(BS_UDB_1_4_HV_ROUTING_VAL), (uint16)(CYDEV_UCFG_B0_P6_ROUTE_BASE + 0x00000080u) },	/* TD 94 */
  		{ 128u, 0x23u, 0xFEu, (uint16)(uint32)(BS_UDBSWITCH_1_4_VAL), (uint16)(CYDEV_UCFG_B0_P1_ROUTE_BASE) },	/* TD 95 */
  	};
  
  	DMA_ZERO_VAL = 0u;
  	CY_SET_REG8((void CYXDATA *)CYREG_PHUB_CFGMEM0_CFG0, 0x10u);	/* set burstcnt */
  	CY_SET_REG8((void CYXDATA *)CYREG_PHUB_CH0_BASIC_CFG, 0x01u);	/* enable ch0 */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH0_BASIC_STATUS+1u), 0x00u);	/* set first TD to 0 */
  	CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD0, 95u*8u);	/* transfer size */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_TDMEM0_ORIG_TD0+2u), 0x01u);	/* set next TD to 1 */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_TDMEM0_ORIG_TD0+3u), 0xA3u);	/* set TD flags */
  	CY_SET_REG16((void CYXDATA *)CYREG_PHUB_TDMEM0_ORIG_TD1, (uint16)((uint32)CFG_TD_LIST0 & 0x0000FFFFu));	/* set td0's src addr */
  	CY_SET_REG16((void CYXDATA *)(CYREG_PHUB_TDMEM0_ORIG_TD1+2u), CYDEV_PHUB_TDMEM1_BASE);	/* set td0's dst addr */
  	CY_SET_REG16((void CYXDATA *)CYREG_PHUB_CFGMEM0_CFG1, (uint16)(CYDEV_FLS_BASE >> 16));	/* set ch0's src high addr */
  	CY_SET_REG16((void CYXDATA *)(CYREG_PHUB_CFGMEM0_CFG1+2u), (uint16)(CYDEV_PHUB_TDMEM1_BASE >> 16));	/* set ch0's dst high addr */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH1_BASIC_STATUS+1u), 0x0Bu);	/* ch1 first TD: 11 */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH2_BASIC_STATUS+1u), 0x0Cu);	/* ch2 first TD: 12 */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH4_BASIC_STATUS+1u), 0x0Fu);	/* ch4 first TD: 15 */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH5_BASIC_STATUS+1u), 0x1Fu);	/* ch5 first TD: 31 */
  	CY_SET_REG8((void CYXDATA *)(CYREG_PHUB_CH6_BASIC_STATUS+1u), 0x28u);	/* ch6 first TD: 40 */
  
  	CY_CFG_MEMORY_BARRIER();
  	CY_SET_REG8((void CYXDATA *)CYREG_PHUB_CH0_ACTION, 0x01u); /* cpu_req */
  	CY_CFG_MEMORY_BARRIER();
  
  	/* Wait for all DMA transfers to complete */
  	while(0u != (CY_GET_REG8((void CYXDATA *)CYREG_PHUB_CH0_BASIC_STATUS) & 0x01u)){}
  	while(0u != (CY_GET_REG8((void CYXDATA *)CYREG_PHUB_CH1_BASIC_STATUS) & 0x01u)){}
  	while(0u != (CY_GET_REG8((void CYXDATA *)CYREG_PHUB_CH2_BASIC_STATUS) & 0x01u)){}
  	while(0u != (CY_GET_REG8((void CYXDATA *)CYREG_PHUB_CH4_BASIC_STATUS) & 0x01u)){}
  	while(0u != (CY_GET_REG8((void CYXDATA *)CYREG_PHUB_CH5_BASIC_STATUS) & 0x01u)){}
  	while(0u != (CY_GET_REG8((void CYXDATA *)CYREG_PHUB_CH6_BASIC_STATUS) & 0x01u)){}
  
  
  	CYCONFIGCPY((void CYFAR *)(CYREG_IDMUX_DRQ_CTL0), (const void CYFAR *)(BS_IDMUX_VAL), 6u);
  
  }
  /*******************************************************************************
  * Function Name: ClockSetup
  ********************************************************************************
  *
  * Summary:
  *  Performs the initialization of all of the clocks in the device based on the
  *  settings in the Clock tab of the DWR.  This includes enabling the requested
  *  clocks and setting the necessary dividers to produce the desired frequency. 
  *
  * Parameters:
  *  void
  *
  * Return:
  *  void
  *
  *******************************************************************************/
  static void ClockSetup(void);
  static void ClockSetup(void)
  {
  	uint32 timeout;
  	uint8 pllLock;
  
  
  	/* Configure Digital Clocks based on settings from Clock DWR */
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0002u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x18u);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x50u);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0FFFu);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x1Bu);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x000Bu);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x19u);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG4_CFG0), 0x002Fu);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG4_CFG0 + 0x2u), 0x18u);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG5_CFG0), 0x00EFu);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG5_CFG0 + 0x2u), 0x18u);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG6_CFG0), 0xBB7Fu);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG6_CFG0 + 0x2u), 0x19u);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG7_CFG0), 0x270Fu);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DCFG7_CFG0 + 0x2u), 0x1Bu);
  
  	/* Configure Analog Clocks based on settings from Clock DWR */
  	CYCONFIGCPY((void CYFAR *)(CYREG_CLKDIST_ACFG0_CFG0), (const void CYFAR *)(BS_CYDEV_CLKDIST_ACFG0_CFG0_VAL), 4u);
  
  	/* Configure ILO based on settings from Clock DWR */
  	CY_SET_REG8((void CYXDATA *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);
  
  	/* Configure IMO based on settings from Clock DWR */
  	CY_SET_REG8((void CYXDATA *)(CYREG_FASTCLK_IMO_CR), 0x52u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));
  
  	/* Configure PLL based on settings from Clock DWR */
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0710u);
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
  	/* Wait up to 250us for the PLL to lock */
  	pllLock = 0u;
  	for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)
  	{ 
  		pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_REG8((void CYXDATA *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));
  		CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */
  	}
  	/* If we ran out of time the PLL didn't lock so go to the error function */
  	if (timeout == 0u)
  	{
  		CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
  	}
  
  	/* Configure Bus/Master Clock based on settings from Clock DWR */
  	CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_MSTR0), 0x07u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_BCFG0), 0x00u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_BCFG2), 0x48u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_MSTR0), 0x00u);
  
  	/* Configure USB Clock based on settings from Clock DWR */
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_UCFG), 0x00u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_LD), 0x02u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_CLKDIST_DLY1), 0x04u);
  
  	CY_SET_REG8((void CYXDATA *)(CYREG_PM_ACT_CFG2), ((CY_GET_REG8((void CYXDATA *)CYREG_PM_ACT_CFG2) | 0xFFu)));
  	CY_SET_REG8((void CYXDATA *)(CYREG_PM_ACT_CFG1), ((CY_GET_REG8((void CYXDATA *)CYREG_PM_ACT_CFG1) | 0x01u)));
  	CY_SET_REG8((void CYXDATA *)(CYREG_PM_ACT_CFG0), ((CY_GET_REG8((void CYXDATA *)CYREG_PM_ACT_CFG0) | 0x80u)));
  }
  
  
  /* Analog API Functions */
  
  
  /*******************************************************************************
  * Function Name: AnalogSetDefault
  ********************************************************************************
  *
  * Summary:
  *  Sets up the analog portions of the chip to default values based on chip
  *  configuration options from the project.
  *
  * Parameters:
  *  void
  *
  * Return:
  *  void
  *
  *******************************************************************************/
  static void AnalogSetDefault(void);
  static void AnalogSetDefault(void)
  {
  	uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
  	CY_SET_REG8((void CYXDATA *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
  	CY_SET_REG8((void CYXDATA *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
  	CY_SET_REG8((void CYXDATA *)CYREG_PRT0_AG, 0x60u);
  	CY_SET_REG8((void CYXDATA *)CYREG_PRT1_AG, 0x80u);
  	CY_SET_REG8((void CYXDATA *)CYREG_PRT15_AG, 0x01u);
  	CY_SET_REG8((void CYXDATA *)CYREG_DSM0_SW0, 0x78u);
  	CY_SET_REG8((void CYXDATA *)CYREG_BUS_SW0, 0x18u);
  	CY_SET_REG8((void CYXDATA *)CYREG_PUMP_CR0, 0x44u);
  }
  
  
  /*******************************************************************************
  * Function Name: SetAnalogRoutingPumps
  ********************************************************************************
  *
  * Summary:
  * Enables or disables the analog pumps feeding analog routing switches.
  * Intended to be called at startup, based on the Vdda system configuration;
  * may be called during operation when the user informs us that the Vdda voltage
  * crossed the pump threshold.
  *
  * Parameters:
  *  enabled - 1 to enable the pumps, 0 to disable the pumps
  *
  * Return:
  *  void
  *
  *******************************************************************************/
  void SetAnalogRoutingPumps(uint8 enabled)
  {
  	uint8 regValue = CY_GET_REG8((void CYXDATA *)CYREG_PUMP_CR0);
  	if (enabled != 0u)
  	{
  		regValue |= 0x22u;
  	}
  	else
  	{
  		regValue &= (uint8)~0x22u;
  	}
  	CY_SET_REG8((void CYXDATA *)CYREG_PUMP_CR0, regValue);
  }
  
  
  #define CY_AMUX_UNUSED CYREG_BOOST_SR
  /* This is an implementation detail of the AMux. Code that depends on it may be
     incompatible with other versions of PSoC Creator. */
  uint8 CYXDATA * const CYCODE ADC_AMux__addrTable[2] = {
  	(uint8 CYXDATA *)CYREG_DSM0_SW3, 
  	(uint8 CYXDATA *)CY_AMUX_UNUSED, 
  };
  
  /* This is an implementation detail of the AMux. Code that depends on it may be
     incompatible with other versions of PSoC Creator. */
  const uint8 CYCODE ADC_AMux__maskTable[2] = {
  	0x40u, 
  	0x00u, 
  };
  
  /*******************************************************************************
  * Function Name: ADC_AMux_Set
  ********************************************************************************
  * Summary:
  *  This function is used to set a particular channel as active on the AMux.
  *
  * Parameters:  
  *   channel - The mux channel input to set as active
  *
  * Return:
  *   void
  *
  *******************************************************************************/
  void ADC_AMux_Set(uint8 channel)
  {
  	if (channel < 2)
  	{
  		*ADC_AMux__addrTable[channel] |= ADC_AMux__maskTable[channel];
  	}
  }
  
  /*******************************************************************************
  * Function Name: ADC_AMux_Unset
  ********************************************************************************
  * Summary:
  *  This function is used to clear a particular channel from being active on the
  *  AMux.
  *
  * Parameters:  
  *   channel - The mux channel input to mark inactive
  *
  * Return:
  *   void
  *
  *******************************************************************************/
  void ADC_AMux_Unset(uint8 channel)
  {
  	if (channel < 2)
  	{
  		*ADC_AMux__addrTable[channel] &= (uint8)~ADC_AMux__maskTable[channel];
  	}
  }
  
  
  
  /*******************************************************************************
  * Function Name: cyfitter_cfg
  ********************************************************************************
  * Summary:
  *  This function is called by the start-up code for the selected device. It
  *  performs all of the necessary device configuration based on the design
  *  settings.  This includes settings from the Design Wide Resources (DWR) such
  *  as Clocks and Pins as well as any component configuration that is necessary.
  *
  * Parameters:
  *   void
  *
  * Return:
  *   void
  *
  *******************************************************************************/
  
  void cyfitter_cfg(void)
  {
  	/* IOPINS0_7 Address: CYREG_PRT12_DM0 Size (bytes): 8 */
  	DMAINITSEC static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {
  		0x00u, 0x0Cu, 0x0Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u};
  
  	/* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */
  	DMAINITSEC static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {
  		0x04u, 0x00u, 0x00u, 0x0Cu, 0x08u, 0x00u, 0x08u, 0x01u, 0x01u, 0x00u};
  
  	/* IOPINS0_1 Address: CYREG_PRT1_DR Size (bytes): 10 */
  	DMAINITSEC static const uint8 CYCODE BS_IOPINS0_1_VAL[] = {
  		0x00u, 0x00u, 0x00u, 0x7Fu, 0x7Bu, 0x00u, 0x7Bu, 0x80u, 0x80u, 0x00u};
  
  	/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
  	DMAINITSEC static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {
  		0x30u, 0xD8u, 0xC8u, 0x00u, 0xD8u, 0x00u, 0x00u, 0x00u};
  
  	/* PHUB_CFGMEM10 Address: CYREG_PHUB_CFGMEM10_CFG0 Size (bytes): 4 */
  	DMAINITSEC static const uint8 CYCODE BS_PHUB_CFGMEM10_VAL[] = {
  		0x00u, 0x0Au, 0x00u, 0x00u};
  
  	/* Enable/Disable Debug functionality based on settings from System DWR */
  	CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x01u));
  
  	{
  		cfg_dma_init();
  
  		/* Perform normal device configuration. Order is not critical for these items. */
  		CY_SET_REG8((void CYXDATA *)(CYREG_DSM0_CR3), 0x0Au);
  		CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM10_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM10_VAL), 4u);
  
  		/* Enable digital routing */
  		CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
  		CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
  
  		/* Enable UDB array */
  		CY_SET_REG8((void CYXDATA *)CYREG_PM_ACT_CFG0, CY_GET_REG8((void CYXDATA *)CYREG_PM_ACT_CFG0) | 0x40u);
  		CY_SET_REG8((void CYXDATA *)CYREG_PM_AVAIL_CR2, CY_GET_REG8((void CYXDATA *)CYREG_PM_AVAIL_CR2) | 0x10u);
  	}
  
  
  	/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
  	CYCONFIGCPY((void CYFAR *)(CYREG_PRT0_DM0), (const void CYFAR *)(BS_IOPINS0_0_VAL), 8u);
  	CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0), (const void CYCODE *)(BS_IOPINS0_7_VAL), 8u);
  	CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
  	CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DR), (const void CYCODE *)(BS_IOPINS0_1_VAL), 10u);
  	CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);
  	CY_SET_REG8((void CYXDATA *)(CYREG_INTC_CSR_EN), 0x01u);
  	/* Switch Boost to the precision bandgap reference from its internal reference */
  	CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
  	if (CYDEV_CHIP_REV_ACTUAL < 5u)
  	{
  		CY_SET_REG8((void CYXDATA *)CYREG_PWRSYS_WAKE_TR2, 0x3Au);
  	}
  
  
  	/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
  	CY_SET_REG8((void CYXDATA *)(CYREG_CACHE_CR), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xF1u : 0xC0u));
  	/* Setup clocks based on selections from Clock DWR */
  	ClockSetup();
  
  	/* Perform basic analog initialization to defaults */
  	AnalogSetDefault();
  
  	/* Configure alternate active mode */
  	CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);
  	CY_SET_REG8((void CYXDATA *)CYREG_PM_STBY_CFG0, CY_GET_REG8((void CYXDATA *)CYREG_PM_STBY_CFG0) & (uint8)~0x02u);	/* Disable CPU */
  }
  