text: /**
    ******************************************************************************
    * @file    cx32l003_hal_pwr.c
  	* @author  MCU Software Team
  	* @Version V1.2.0
    * @Date    2021-01-11
    * @brief   PWR HAL module driver.
    *
    *          This file provides firmware functions to manage the following
    *          functionalities of the Power Controller (PWR) peripheral:
    *           + Initialization/de-initialization functions
    *           + Peripheral Control functions 
    *
    ******************************************************************************
  
    */
  
  /* Includes ------------------------------------------------------------------*/
  #include "cx32l003_hal.h"
  
  
  /** @addtogroup CX32L003_HAL_Driver
    * @{
    */
  
  #ifdef HAL_PWR_MODULE_ENABLED
  
  /** @defgroup PWR PWR
    * @brief    PWR HAL module driver
    * @{
    */
  
  /* Private typedef -----------------------------------------------------------*/
  /* Private define ------------------------------------------------------------*/
  /* Private variables ---------------------------------------------------------*/
  /* Private function prototypes -----------------------------------------------*/
  
  
  /** @defgroup PWR_Exported_Functions PWR Exported Functions
    * @{
    */
  
  /** @defgroup PWR_Exported_Functions_Group1 Peripheral Control functions 
    * @brief    Low Power modes configuration functions
    *
  @verbatim
   ===============================================================================
                   ##### Peripheral Control functions #####
   ===============================================================================
   
      *** Low Power modes configuration ***
      =====================================
       [..]
        The device features 3 low-power modes:
        (+) Sleep mode: CPU clock off, all peripherals not driven by HCLK like 
                        NVIC, IWDG, RTC, etc. are kept running
        (+) Deep Sleep mode: All high speed clocks are stopped, low speed clock can be configured to run.
  											NVIC is kept running.
    
    
     *** Sleep mode ***
     ==================
      [..]
        (+) Entry:
            The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_SLEEPENTRY_WFx)
                functions with
            (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
            (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
       
        (+) Exit:
          (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
               controller (NVIC) can wake up the device from Sleep mode.
          (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
             (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
             (+++) Any EXTI Line (Internal or External) configured in Event mode
  
  
     *** Deep Sleep mode ***
     =================
      [..]
        The Deep Sleep mode is based on the Cortex-M0+ deepsleep mode combined with peripheral
        clock gating.
        In Deep Sleep mode, all high speed clocks are stopped, the HSI and the HSE RC oscillators are 
  			disabled. SRAM and register contents are preserved.
        In Deep Sleep mode, all I/O pins keep the same state as in Run mode.
  			
        (+) Entry:
             The Deep Sleep mode is entered using the HAL_PWR_EnterDEEPSLEEPMode(void) function.
        (+) Exit:
            (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
          
    @endverbatim
    ******************************************************************************
   **/
  
  
  /**
    * @brief Enters Sleep mode.
    * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
    * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
    *           When WFI entry is used, tick interrupt have to be disabled if not desired as 
    *           the interrupt wake up source.
    *           This parameter can be one of the following values:
    *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
    *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
    * @retval None
    */
  void HAL_PWR_EnterSLEEPMode(uint8_t SLEEPEntry)
  {
    /* Check the parameters */
    assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
  	
    /* Clear SLEEPDEEP bit of Cortex System Control Register */
    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));	
  	
    /* Select SLEEP mode entry -------------------------------------------------*/
    if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
    {
      /* Request Wait For Interrupt */
      __WFI();
    }
    else
    {
      /* Request Wait For Event */
      __SEV();
      __WFE();
      __WFE();
    }
  }
  
  
  /**
    * @brief Enters Deep Sleep mode. 
    * @note  In Deep Sleep mode, all I/O pins keep the same state as in Run mode.
    * @retval None
    */
  void HAL_PWR_EnterDEEPSLEEPMode(void)
  {
    /* Set SLEEPDEEP bit of Cortex System Control Register */
    SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 
  //	__NOP();
  //	__NOP();
  //	__NOP();
    /* This option is used to ensure that store operations are completed */
  #if defined ( __CC_ARM)
    __force_stores();
  #endif
    /* Request Wait For Interrupt */
  	
  	__WFI();
  
  }
  
  
  /**
    * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
    * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
    *       re-enters SLEEP mode when an interruption handling is over.
    *       Setting this bit is useful when the processor is expected to run only on
    *       interruptions handling.         
    * @retval None
    */
  void HAL_PWR_EnableSleepOnExit(void)
  {
    /* Set SLEEPONEXIT bit of Cortex System Control Register */
    SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  }
  
  
  /**
    * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
    * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
    *       re-enters SLEEP mode when an interruption handling is over.          
    * @retval None
    */
  void HAL_PWR_DisableSleepOnExit(void)
  {
    /* Clear SLEEPONEXIT bit of Cortex System Control Register */
    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  }
  
  
  /**
    * @brief Enables CORTEX M0+ SEVONPEND bit. 
    * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
    *       WFE to wake up when an interrupt moves from inactive to pended.
    * @retval None
    */
  void HAL_PWR_EnableSEVOnPend(void)
  {
    /* Set SEVONPEND bit of Cortex System Control Register */
    SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));	
  }
  
  
  /**
    * @brief Disables CORTEX M0+ SEVONPEND bit. 
    * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
    *       WFE to wake up when an interrupt moves from inactive to pended.         
    * @retval None
    */
  void HAL_PWR_DisableSEVOnPend(void)
  {
    /* Clear SEVONPEND bit of Cortex System Control Register */
    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  }
  
  
  /**
    * @}
    */
  
  /**
    * @}
    */ /* End of group PWR */
  
  #endif /* HAL_PWR_MODULE_ENABLED */
  
  /**
    * @}
    */ /* group CX32L003_HAL_Driver */
  