text: #!/usr/bin/env python3
  
  # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
  # License: BSD
  
  import os
  import argparse
  
  from migen import *
  
  from litex_boards.platforms import forest_kitten_33
  
  from litex.soc.cores.clock import *
  from litex.soc.integration.soc_core import *
  from litex.soc.integration.builder import *
  from litex.soc.cores.led import LedChaser
  
  # CRG ----------------------------------------------------------------------------------------------
  
  class _CRG(Module):
      def __init__(self, platform, sys_clk_freq):
          self.clock_domains.cd_sys    = ClockDomain()
  
          # # #
  
          self.submodules.pll = pll = USMMCM(speedgrade=-2)
          pll.register_clkin(platform.request("clk200"), 200e6)
          pll.create_clkout(self.cd_sys, sys_clk_freq)
  
  # BaseSoC ------------------------------------------------------------------------------------------
  
  class BaseSoC(SoCCore):
      def __init__(self, sys_clk_freq=int(125e6), **kwargs):
          platform = forest_kitten_33.Platform()
  
          # SoCCore ----------------------------------------------------------------------------------
          SoCCore.__init__(self, platform, sys_clk_freq,
              ident          = "LiteX SoC on Forest Kitten 33",
              ident_version  = True,
              **kwargs)
  
          # CRG --------------------------------------------------------------------------------------
          self.submodules.crg = _CRG(platform, sys_clk_freq)
  
          # Leds -------------------------------------------------------------------------------------
          self.submodules.leds = LedChaser(
              pads         = Cat(*[platform.request("user_led", i) for i in range(7)]),
              sys_clk_freq = sys_clk_freq)
          self.add_csr("leds")
  
  # Build --------------------------------------------------------------------------------------------
  
  def main():
      parser = argparse.ArgumentParser(description="LiteX SoC on Forest Kitten 33")
      parser.add_argument("--build", action="store_true", help="Build bitstream")
      parser.add_argument("--load",  action="store_true", help="Load bitstream")
      builder_args(parser)
      soc_core_args(parser)
      args = parser.parse_args()
  
      soc = BaseSoC(**soc_core_argdict(args))
      builder = Builder(soc, **builder_argdict(args))
      builder.build(run=args.build)
  
      if args.load:
          prog = soc.platform.create_programmer()
          prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
  
  if __name__ == "__main__":
      main()
  