text: // ==============================================================
  // RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
  // Version: 2017.2
  // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
  // 
  // ===========================================================
  
  #include "Loop_1_proc.h"
  #include "AESL_pkg.h"
  
  using namespace std;
  
  namespace ap_rtl {
  
  const sc_logic Loop_1_proc::ap_const_logic_1 = sc_dt::Log_1;
  const sc_logic Loop_1_proc::ap_const_logic_0 = sc_dt::Log_0;
  const sc_lv<3> Loop_1_proc::ap_ST_fsm_state1 = "1";
  const sc_lv<3> Loop_1_proc::ap_ST_fsm_pp0_stage0 = "10";
  const sc_lv<3> Loop_1_proc::ap_ST_fsm_state8 = "100";
  const bool Loop_1_proc::ap_const_boolean_1 = true;
  const sc_lv<32> Loop_1_proc::ap_const_lv32_0 = "00000000000000000000000000000000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_1 = "1";
  const bool Loop_1_proc::ap_const_boolean_0 = false;
  const sc_lv<1> Loop_1_proc::ap_const_lv1_0 = "0";
  const sc_lv<1> Loop_1_proc::ap_const_lv1_1 = "1";
  const sc_lv<21> Loop_1_proc::ap_const_lv21_0 = "000000000000000000000";
  const sc_lv<21> Loop_1_proc::ap_const_lv21_1F8C94 = "111111000110010010100";
  const sc_lv<21> Loop_1_proc::ap_const_lv21_1 = "1";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_40 = "1000000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_5F = "1011111";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_C0 = "11000000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_DF = "11011111";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_100 = "100000000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_11F = "100011111";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_20 = "100000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_3E = "111110";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_60 = "1100000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_7E = "1111110";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_80 = "10000000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_9D = "10011101";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_A0 = "10100000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_BE = "10111110";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_E0 = "11100000";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_FE = "11111110";
  const sc_lv<2> Loop_1_proc::ap_const_lv2_0 = "00";
  const sc_lv<32> Loop_1_proc::ap_const_lv32_2 = "10";
  
  Loop_1_proc::Loop_1_proc(sc_module_name name) : sc_module(name), mVcdFile(0) {
  
      SC_METHOD(thread_ap_clk_no_reset_);
      dont_initialize();
      sensitive << ( ap_clk.pos() );
  
      SC_METHOD(thread_ap_CS_fsm_pp0_stage0);
      sensitive << ( ap_CS_fsm );
  
      SC_METHOD(thread_ap_CS_fsm_state1);
      sensitive << ( ap_CS_fsm );
  
      SC_METHOD(thread_ap_CS_fsm_state8);
      sensitive << ( ap_CS_fsm );
  
      SC_METHOD(thread_ap_block_pp0_stage0_flag00000000);
  
      SC_METHOD(thread_ap_block_pp0_stage0_flag00001001);
      sensitive << ( p_hw_input_stencil_stream_V_value_V_empty_n );
      sensitive << ( p_mul_stencil_update_stream_V_value_V_full_n );
      sensitive << ( ap_enable_reg_pp0_iter1 );
      sensitive << ( exitcond_flatten_reg_287 );
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( ap_reg_pp0_iter4_exitcond_flatten_reg_287 );
  
      SC_METHOD(thread_ap_block_pp0_stage0_flag00011001);
      sensitive << ( p_hw_input_stencil_stream_V_value_V_empty_n );
      sensitive << ( p_mul_stencil_update_stream_V_value_V_full_n );
      sensitive << ( ap_enable_reg_pp0_iter1 );
      sensitive << ( exitcond_flatten_reg_287 );
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( ap_reg_pp0_iter4_exitcond_flatten_reg_287 );
  
      SC_METHOD(thread_ap_block_pp0_stage0_flag00011011);
      sensitive << ( p_hw_input_stencil_stream_V_value_V_empty_n );
      sensitive << ( p_mul_stencil_update_stream_V_value_V_full_n );
      sensitive << ( ap_enable_reg_pp0_iter1 );
      sensitive << ( exitcond_flatten_reg_287 );
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( ap_reg_pp0_iter4_exitcond_flatten_reg_287 );
  
      SC_METHOD(thread_ap_block_state1);
      sensitive << ( real_start );
      sensitive << ( ap_done_reg );
  
      SC_METHOD(thread_ap_block_state2_pp0_stage0_iter0);
  
      SC_METHOD(thread_ap_block_state3_pp0_stage0_iter1);
      sensitive << ( p_hw_input_stencil_stream_V_value_V_empty_n );
      sensitive << ( exitcond_flatten_reg_287 );
  
      SC_METHOD(thread_ap_block_state4_pp0_stage0_iter2);
  
      SC_METHOD(thread_ap_block_state5_pp0_stage0_iter3);
  
      SC_METHOD(thread_ap_block_state6_pp0_stage0_iter4);
  
      SC_METHOD(thread_ap_block_state7_pp0_stage0_iter5);
      sensitive << ( p_mul_stencil_update_stream_V_value_V_full_n );
      sensitive << ( ap_reg_pp0_iter4_exitcond_flatten_reg_287 );
  
      SC_METHOD(thread_ap_condition_pp0_exit_iter0_state2);
      sensitive << ( exitcond_flatten_fu_116_p2 );
  
      SC_METHOD(thread_ap_done);
      sensitive << ( ap_done_reg );
      sensitive << ( ap_CS_fsm_state8 );
  
      SC_METHOD(thread_ap_enable_pp0);
      sensitive << ( ap_idle_pp0 );
  
      SC_METHOD(thread_ap_idle);
      sensitive << ( real_start );
      sensitive << ( ap_CS_fsm_state1 );
  
      SC_METHOD(thread_ap_idle_pp0);
      sensitive << ( ap_enable_reg_pp0_iter1 );
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( ap_enable_reg_pp0_iter0 );
      sensitive << ( ap_enable_reg_pp0_iter2 );
      sensitive << ( ap_enable_reg_pp0_iter3 );
      sensitive << ( ap_enable_reg_pp0_iter4 );
  
      SC_METHOD(thread_ap_ready);
      sensitive << ( internal_ap_ready );
  
      SC_METHOD(thread_exitcond_flatten_fu_116_p2);
      sensitive << ( ap_CS_fsm_pp0_stage0 );
      sensitive << ( indvar_flatten_reg_105 );
      sensitive << ( ap_block_pp0_stage0_flag00011001 );
      sensitive << ( ap_enable_reg_pp0_iter0 );
  
      SC_METHOD(thread_indvar_flatten_next_fu_122_p2);
      sensitive << ( indvar_flatten_reg_105 );
  
      SC_METHOD(thread_internal_ap_ready);
      sensitive << ( ap_CS_fsm_state8 );
  
      SC_METHOD(thread_p_327_fu_128_p1);
      sensitive << ( p_hw_input_stencil_stream_V_value_V_dout );
  
      SC_METHOD(thread_p_336_fu_212_p3);
      sensitive << ( tmp_s_reg_316 );
  
      SC_METHOD(thread_p_348_fu_261_p3);
      sensitive << ( ap_reg_pp0_iter2_tmp_11_reg_321 );
  
      SC_METHOD(thread_p_354_fu_219_p3);
      sensitive << ( tmp_12_reg_326 );
  
      SC_METHOD(thread_p_360_fu_226_p3);
      sensitive << ( tmp_13_reg_331 );
  
      SC_METHOD(thread_p_372_fu_233_p3);
      sensitive << ( tmp_14_reg_336 );
  
      SC_METHOD(thread_p_379_fu_282_p2);
      sensitive << ( tmp1_reg_356 );
      sensitive << ( tmp4_fu_278_p2 );
  
      SC_METHOD(thread_p_hw_input_stencil_stream_V_value_V_blk_n);
      sensitive << ( p_hw_input_stencil_stream_V_value_V_empty_n );
      sensitive << ( ap_CS_fsm_pp0_stage0 );
      sensitive << ( ap_enable_reg_pp0_iter1 );
      sensitive << ( ap_block_pp0_stage0_flag00000000 );
      sensitive << ( exitcond_flatten_reg_287 );
  
      SC_METHOD(thread_p_hw_input_stencil_stream_V_value_V_read);
      sensitive << ( ap_CS_fsm_pp0_stage0 );
      sensitive << ( ap_enable_reg_pp0_iter1 );
      sensitive << ( exitcond_flatten_reg_287 );
      sensitive << ( ap_block_pp0_stage0_flag00011001 );
  
      SC_METHOD(thread_p_mul_stencil_update_stream_V_value_V_blk_n);
      sensitive << ( p_mul_stencil_update_stream_V_value_V_full_n );
      sensitive << ( ap_block_pp0_stage0_flag00000000 );
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( ap_reg_pp0_iter4_exitcond_flatten_reg_287 );
  
      SC_METHOD(thread_p_mul_stencil_update_stream_V_value_V_din);
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( ap_reg_pp0_iter4_exitcond_flatten_reg_287 );
      sensitive << ( p_379_reg_361 );
      sensitive << ( ap_block_pp0_stage0_flag00001001 );
  
      SC_METHOD(thread_p_mul_stencil_update_stream_V_value_V_write);
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( ap_reg_pp0_iter4_exitcond_flatten_reg_287 );
      sensitive << ( ap_block_pp0_stage0_flag00011001 );
  
      SC_METHOD(thread_real_start);
      sensitive << ( ap_start );
      sensitive << ( real_start_status_reg );
  
      SC_METHOD(thread_start_out);
      sensitive << ( real_start );
  
      SC_METHOD(thread_start_write);
      sensitive << ( ap_start );
      sensitive << ( start_control_reg );
  
      SC_METHOD(thread_tmp1_fu_273_p2);
      sensitive << ( tmp2_reg_341 );
      sensitive << ( tmp3_fu_268_p2 );
  
      SC_METHOD(thread_tmp2_fu_240_p2);
      sensitive << ( p_327_reg_296 );
      sensitive << ( p_336_fu_212_p3 );
  
      SC_METHOD(thread_tmp3_fu_268_p2);
      sensitive << ( ap_reg_pp0_iter2_p_339_reg_301 );
      sensitive << ( p_348_fu_261_p3 );
  
      SC_METHOD(thread_tmp4_fu_278_p2);
      sensitive << ( ap_reg_pp0_iter3_tmp5_reg_346 );
      sensitive << ( ap_reg_pp0_iter3_tmp6_reg_351 );
  
      SC_METHOD(thread_tmp5_fu_245_p2);
      sensitive << ( p_360_fu_226_p3 );
      sensitive << ( p_354_fu_219_p3 );
  
      SC_METHOD(thread_tmp6_fu_256_p2);
      sensitive << ( p_363_reg_306 );
      sensitive << ( tmp7_fu_251_p2 );
  
      SC_METHOD(thread_tmp7_fu_251_p2);
      sensitive << ( p_375_reg_311 );
      sensitive << ( p_372_fu_233_p3 );
  
      SC_METHOD(thread_ap_NS_fsm);
      sensitive << ( real_start );
      sensitive << ( ap_done_reg );
      sensitive << ( ap_CS_fsm );
      sensitive << ( ap_CS_fsm_state1 );
      sensitive << ( ap_enable_reg_pp0_iter1 );
      sensitive << ( ap_enable_reg_pp0_iter5 );
      sensitive << ( exitcond_flatten_fu_116_p2 );
      sensitive << ( ap_enable_reg_pp0_iter0 );
      sensitive << ( ap_block_pp0_stage0_flag00011011 );
      sensitive << ( ap_enable_reg_pp0_iter4 );
  
      real_start_status_reg = SC_LOGIC_0;
      ap_done_reg = SC_LOGIC_0;
      ap_CS_fsm = "001";
      start_once_reg = SC_LOGIC_0;
      start_control_reg = SC_LOGIC_0;
      ap_enable_reg_pp0_iter1 = SC_LOGIC_0;
      ap_enable_reg_pp0_iter5 = SC_LOGIC_0;
      ap_enable_reg_pp0_iter0 = SC_LOGIC_0;
      ap_enable_reg_pp0_iter2 = SC_LOGIC_0;
      ap_enable_reg_pp0_iter3 = SC_LOGIC_0;
      ap_enable_reg_pp0_iter4 = SC_LOGIC_0;
      static int apTFileNum = 0;
      stringstream apTFilenSS;
      apTFilenSS << "Loop_1_proc_sc_trace_" << apTFileNum ++;
      string apTFn = apTFilenSS.str();
      mVcdFile = sc_create_vcd_trace_file(apTFn.c_str());
      mVcdFile->set_time_unit(1, SC_PS);
      if (1) {
  #ifdef __HLS_TRACE_LEVEL_PORT_HIER__
      sc_trace(mVcdFile, ap_clk, "(port)ap_clk");
      sc_trace(mVcdFile, ap_rst, "(port)ap_rst");
      sc_trace(mVcdFile, ap_start, "(port)ap_start");
      sc_trace(mVcdFile, start_full_n, "(port)start_full_n");
      sc_trace(mVcdFile, ap_ready, "(port)ap_ready");
      sc_trace(mVcdFile, ap_done, "(port)ap_done");
      sc_trace(mVcdFile, ap_continue, "(port)ap_continue");
      sc_trace(mVcdFile, ap_idle, "(port)ap_idle");
      sc_trace(mVcdFile, start_out, "(port)start_out");
      sc_trace(mVcdFile, start_write, "(port)start_write");
      sc_trace(mVcdFile, p_hw_input_stencil_stream_V_value_V_dout, "(port)p_hw_input_stencil_stream_V_value_V_dout");
      sc_trace(mVcdFile, p_hw_input_stencil_stream_V_value_V_empty_n, "(port)p_hw_input_stencil_stream_V_value_V_empty_n");
      sc_trace(mVcdFile, p_hw_input_stencil_stream_V_value_V_read, "(port)p_hw_input_stencil_stream_V_value_V_read");
      sc_trace(mVcdFile, p_mul_stencil_update_stream_V_value_V_din, "(port)p_mul_stencil_update_stream_V_value_V_din");
      sc_trace(mVcdFile, p_mul_stencil_update_stream_V_value_V_full_n, "(port)p_mul_stencil_update_stream_V_value_V_full_n");
      sc_trace(mVcdFile, p_mul_stencil_update_stream_V_value_V_write, "(port)p_mul_stencil_update_stream_V_value_V_write");
  #endif
  #ifdef __HLS_TRACE_LEVEL_INT__
      sc_trace(mVcdFile, real_start, "real_start");
      sc_trace(mVcdFile, real_start_status_reg, "real_start_status_reg");
      sc_trace(mVcdFile, internal_ap_ready, "internal_ap_ready");
      sc_trace(mVcdFile, ap_done_reg, "ap_done_reg");
      sc_trace(mVcdFile, ap_CS_fsm, "ap_CS_fsm");
      sc_trace(mVcdFile, ap_CS_fsm_state1, "ap_CS_fsm_state1");
      sc_trace(mVcdFile, start_once_reg, "start_once_reg");
      sc_trace(mVcdFile, start_control_reg, "start_control_reg");
      sc_trace(mVcdFile, p_hw_input_stencil_stream_V_value_V_blk_n, "p_hw_input_stencil_stream_V_value_V_blk_n");
      sc_trace(mVcdFile, ap_CS_fsm_pp0_stage0, "ap_CS_fsm_pp0_stage0");
      sc_trace(mVcdFile, ap_enable_reg_pp0_iter1, "ap_enable_reg_pp0_iter1");
      sc_trace(mVcdFile, ap_block_pp0_stage0_flag00000000, "ap_block_pp0_stage0_flag00000000");
      sc_trace(mVcdFile, exitcond_flatten_reg_287, "exitcond_flatten_reg_287");
      sc_trace(mVcdFile, p_mul_stencil_update_stream_V_value_V_blk_n, "p_mul_stencil_update_stream_V_value_V_blk_n");
      sc_trace(mVcdFile, ap_enable_reg_pp0_iter5, "ap_enable_reg_pp0_iter5");
      sc_trace(mVcdFile, ap_reg_pp0_iter4_exitcond_flatten_reg_287, "ap_reg_pp0_iter4_exitcond_flatten_reg_287");
      sc_trace(mVcdFile, indvar_flatten_reg_105, "indvar_flatten_reg_105");
      sc_trace(mVcdFile, exitcond_flatten_fu_116_p2, "exitcond_flatten_fu_116_p2");
      sc_trace(mVcdFile, ap_block_state2_pp0_stage0_iter0, "ap_block_state2_pp0_stage0_iter0");
      sc_trace(mVcdFile, ap_block_state3_pp0_stage0_iter1, "ap_block_state3_pp0_stage0_iter1");
      sc_trace(mVcdFile, ap_block_state4_pp0_stage0_iter2, "ap_block_state4_pp0_stage0_iter2");
      sc_trace(mVcdFile, ap_block_state5_pp0_stage0_iter3, "ap_block_state5_pp0_stage0_iter3");
      sc_trace(mVcdFile, ap_block_state6_pp0_stage0_iter4, "ap_block_state6_pp0_stage0_iter4");
      sc_trace(mVcdFile, ap_block_state7_pp0_stage0_iter5, "ap_block_state7_pp0_stage0_iter5");
      sc_trace(mVcdFile, ap_block_pp0_stage0_flag00011001, "ap_block_pp0_stage0_flag00011001");
      sc_trace(mVcdFile, ap_reg_pp0_iter1_exitcond_flatten_reg_287, "ap_reg_pp0_iter1_exitcond_flatten_reg_287");
      sc_trace(mVcdFile, ap_reg_pp0_iter2_exitcond_flatten_reg_287, "ap_reg_pp0_iter2_exitcond_flatten_reg_287");
      sc_trace(mVcdFile, ap_reg_pp0_iter3_exitcond_flatten_reg_287, "ap_reg_pp0_iter3_exitcond_flatten_reg_287");
      sc_trace(mVcdFile, indvar_flatten_next_fu_122_p2, "indvar_flatten_next_fu_122_p2");
      sc_trace(mVcdFile, ap_enable_reg_pp0_iter0, "ap_enable_reg_pp0_iter0");
      sc_trace(mVcdFile, p_327_fu_128_p1, "p_327_fu_128_p1");
      sc_trace(mVcdFile, p_327_reg_296, "p_327_reg_296");
      sc_trace(mVcdFile, p_339_reg_301, "p_339_reg_301");
      sc_trace(mVcdFile, ap_reg_pp0_iter2_p_339_reg_301, "ap_reg_pp0_iter2_p_339_reg_301");
      sc_trace(mVcdFile, p_363_reg_306, "p_363_reg_306");
      sc_trace(mVcdFile, p_375_reg_311, "p_375_reg_311");
      sc_trace(mVcdFile, tmp_s_reg_316, "tmp_s_reg_316");
      sc_trace(mVcdFile, tmp_11_reg_321, "tmp_11_reg_321");
      sc_trace(mVcdFile, ap_reg_pp0_iter2_tmp_11_reg_321, "ap_reg_pp0_iter2_tmp_11_reg_321");
      sc_trace(mVcdFile, tmp_12_reg_326, "tmp_12_reg_326");
      sc_trace(mVcdFile, tmp_13_reg_331, "tmp_13_reg_331");
      sc_trace(mVcdFile, tmp_14_reg_336, "tmp_14_reg_336");
      sc_trace(mVcdFile, tmp2_fu_240_p2, "tmp2_fu_240_p2");
      sc_trace(mVcdFile, tmp2_reg_341, "tmp2_reg_341");
      sc_trace(mVcdFile, tmp5_fu_245_p2, "tmp5_fu_245_p2");
      sc_trace(mVcdFile, tmp5_reg_346, "tmp5_reg_346");
      sc_trace(mVcdFile, ap_reg_pp0_iter3_tmp5_reg_346, "ap_reg_pp0_iter3_tmp5_reg_346");
      sc_trace(mVcdFile, tmp6_fu_256_p2, "tmp6_fu_256_p2");
      sc_trace(mVcdFile, tmp6_reg_351, "tmp6_reg_351");
      sc_trace(mVcdFile, ap_reg_pp0_iter3_tmp6_reg_351, "ap_reg_pp0_iter3_tmp6_reg_351");
      sc_trace(mVcdFile, tmp1_fu_273_p2, "tmp1_fu_273_p2");
      sc_trace(mVcdFile, tmp1_reg_356, "tmp1_reg_356");
      sc_trace(mVcdFile, p_379_fu_282_p2, "p_379_fu_282_p2");
      sc_trace(mVcdFile, p_379_reg_361, "p_379_reg_361");
      sc_trace(mVcdFile, ap_block_state1, "ap_block_state1");
      sc_trace(mVcdFile, ap_block_pp0_stage0_flag00011011, "ap_block_pp0_stage0_flag00011011");
      sc_trace(mVcdFile, ap_condition_pp0_exit_iter0_state2, "ap_condition_pp0_exit_iter0_state2");
      sc_trace(mVcdFile, ap_enable_reg_pp0_iter2, "ap_enable_reg_pp0_iter2");
      sc_trace(mVcdFile, ap_enable_reg_pp0_iter3, "ap_enable_reg_pp0_iter3");
      sc_trace(mVcdFile, ap_enable_reg_pp0_iter4, "ap_enable_reg_pp0_iter4");
      sc_trace(mVcdFile, ap_block_pp0_stage0_flag00001001, "ap_block_pp0_stage0_flag00001001");
      sc_trace(mVcdFile, p_336_fu_212_p3, "p_336_fu_212_p3");
      sc_trace(mVcdFile, p_360_fu_226_p3, "p_360_fu_226_p3");
      sc_trace(mVcdFile, p_354_fu_219_p3, "p_354_fu_219_p3");
      sc_trace(mVcdFile, p_372_fu_233_p3, "p_372_fu_233_p3");
      sc_trace(mVcdFile, tmp7_fu_251_p2, "tmp7_fu_251_p2");
      sc_trace(mVcdFile, p_348_fu_261_p3, "p_348_fu_261_p3");
      sc_trace(mVcdFile, tmp3_fu_268_p2, "tmp3_fu_268_p2");
      sc_trace(mVcdFile, tmp4_fu_278_p2, "tmp4_fu_278_p2");
      sc_trace(mVcdFile, ap_CS_fsm_state8, "ap_CS_fsm_state8");
      sc_trace(mVcdFile, ap_NS_fsm, "ap_NS_fsm");
      sc_trace(mVcdFile, ap_idle_pp0, "ap_idle_pp0");
      sc_trace(mVcdFile, ap_enable_pp0, "ap_enable_pp0");
  #endif
  
      }
  }
  
  Loop_1_proc::~Loop_1_proc() {
      if (mVcdFile) 
          sc_close_vcd_trace_file(mVcdFile);
  
  }
  
  void Loop_1_proc::thread_ap_clk_no_reset_() {
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_CS_fsm = ap_ST_fsm_state1;
      } else {
          ap_CS_fsm = ap_NS_fsm.read();
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_done_reg = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(ap_const_logic_1, ap_continue.read())) {
              ap_done_reg = ap_const_logic_0;
          } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state8.read())) {
              ap_done_reg = ap_const_logic_1;
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_enable_reg_pp0_iter0 = ap_const_logic_0;
      } else {
          if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_pp0_stage0.read()) && 
               esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0) && 
               esl_seteq<1,1,1>(ap_const_logic_1, ap_condition_pp0_exit_iter0_state2.read()))) {
              ap_enable_reg_pp0_iter0 = ap_const_logic_0;
          } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state1.read()) && 
                      !(esl_seteq<1,1,1>(ap_const_logic_0, real_start.read()) || esl_seteq<1,1,1>(ap_done_reg.read(), ap_const_logic_1)))) {
              ap_enable_reg_pp0_iter0 = ap_const_logic_1;
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_enable_reg_pp0_iter1 = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0)) {
              if (esl_seteq<1,1,1>(ap_const_logic_1, ap_condition_pp0_exit_iter0_state2.read())) {
                  ap_enable_reg_pp0_iter1 = (ap_condition_pp0_exit_iter0_state2.read() ^ ap_const_logic_1);
              } else if (esl_seteq<1,1,1>(ap_const_boolean_1, ap_const_boolean_1)) {
                  ap_enable_reg_pp0_iter1 = ap_enable_reg_pp0_iter0.read();
              }
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_enable_reg_pp0_iter2 = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0)) {
              ap_enable_reg_pp0_iter2 = ap_enable_reg_pp0_iter1.read();
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_enable_reg_pp0_iter3 = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0)) {
              ap_enable_reg_pp0_iter3 = ap_enable_reg_pp0_iter2.read();
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_enable_reg_pp0_iter4 = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0)) {
              ap_enable_reg_pp0_iter4 = ap_enable_reg_pp0_iter3.read();
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          ap_enable_reg_pp0_iter5 = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0)) {
              ap_enable_reg_pp0_iter5 = ap_enable_reg_pp0_iter4.read();
          } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state1.read()) && 
                      !(esl_seteq<1,1,1>(ap_const_logic_0, real_start.read()) || esl_seteq<1,1,1>(ap_done_reg.read(), ap_const_logic_1)))) {
              ap_enable_reg_pp0_iter5 = ap_const_logic_0;
          }
      }
      if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_pp0_stage0.read()) && 
           esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0) && 
           esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter0.read()) && 
           esl_seteq<1,1,1>(ap_const_lv1_0, exitcond_flatten_fu_116_p2.read()))) {
          indvar_flatten_reg_105 = indvar_flatten_next_fu_122_p2.read();
      } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state1.read()) && 
                  !(esl_seteq<1,1,1>(ap_const_logic_0, real_start.read()) || esl_seteq<1,1,1>(ap_done_reg.read(), ap_const_logic_1)))) {
          indvar_flatten_reg_105 = ap_const_lv21_0;
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          real_start_status_reg = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(start_full_n.read(), ap_const_logic_1)) {
              real_start_status_reg = ap_const_logic_0;
          } else if ((esl_seteq<1,1,1>(ap_const_logic_0, start_full_n.read()) && 
                      esl_seteq<1,1,1>(ap_const_logic_1, internal_ap_ready.read()))) {
              real_start_status_reg = ap_const_logic_1;
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          start_control_reg = ap_const_logic_0;
      } else {
          if ((esl_seteq<1,1,1>(ap_const_logic_1, real_start.read()) && 
               (esl_seteq<1,1,1>(ap_const_logic_1, internal_ap_ready.read()) || 
                esl_seteq<1,1,1>(ap_const_logic_0, start_once_reg.read())))) {
              start_control_reg = ap_const_logic_1;
          } else if (esl_seteq<1,1,1>(ap_const_logic_1, start_control_reg.read())) {
              start_control_reg = ap_const_logic_0;
          }
      }
      if ( ap_rst.read() == ap_const_logic_1) {
          start_once_reg = ap_const_logic_0;
      } else {
          if (esl_seteq<1,1,1>(ap_const_logic_1, real_start.read())) {
              start_once_reg = ap_const_logic_1;
          } else if (esl_seteq<1,1,1>(ap_const_logic_0, ap_start.read())) {
              start_once_reg = ap_const_logic_0;
          }
      }
      if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_pp0_stage0.read()) && esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0))) {
          ap_reg_pp0_iter1_exitcond_flatten_reg_287 = exitcond_flatten_reg_287.read();
          exitcond_flatten_reg_287 = exitcond_flatten_fu_116_p2.read();
      }
      if (esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0)) {
          ap_reg_pp0_iter2_exitcond_flatten_reg_287 = ap_reg_pp0_iter1_exitcond_flatten_reg_287.read();
          ap_reg_pp0_iter2_p_339_reg_301 = p_339_reg_301.read();
          ap_reg_pp0_iter2_tmp_11_reg_321 = tmp_11_reg_321.read();
          ap_reg_pp0_iter3_exitcond_flatten_reg_287 = ap_reg_pp0_iter2_exitcond_flatten_reg_287.read();
          ap_reg_pp0_iter3_tmp5_reg_346 = tmp5_reg_346.read();
          ap_reg_pp0_iter3_tmp6_reg_351 = tmp6_reg_351.read();
          ap_reg_pp0_iter4_exitcond_flatten_reg_287 = ap_reg_pp0_iter3_exitcond_flatten_reg_287.read();
      }
      if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_pp0_stage0.read()) && esl_seteq<1,1,1>(exitcond_flatten_reg_287.read(), ap_const_lv1_0) && esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0))) {
          p_327_reg_296 = p_327_fu_128_p1.read();
          p_339_reg_301 = p_hw_input_stencil_stream_V_value_V_dout.read().range(95, 64);
          p_363_reg_306 = p_hw_input_stencil_stream_V_value_V_dout.read().range(223, 192);
          p_375_reg_311 = p_hw_input_stencil_stream_V_value_V_dout.read().range(287, 256);
          tmp_11_reg_321 = p_hw_input_stencil_stream_V_value_V_dout.read().range(126, 96);
          tmp_12_reg_326 = p_hw_input_stencil_stream_V_value_V_dout.read().range(157, 128);
          tmp_13_reg_331 = p_hw_input_stencil_stream_V_value_V_dout.read().range(190, 160);
          tmp_14_reg_336 = p_hw_input_stencil_stream_V_value_V_dout.read().range(254, 224);
          tmp_s_reg_316 = p_hw_input_stencil_stream_V_value_V_dout.read().range(62, 32);
      }
      if ((esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0) && esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter3_exitcond_flatten_reg_287.read()))) {
          p_379_reg_361 = p_379_fu_282_p2.read();
      }
      if ((esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0) && esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter2_exitcond_flatten_reg_287.read()))) {
          tmp1_reg_356 = tmp1_fu_273_p2.read();
      }
      if ((esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0) && esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter1_exitcond_flatten_reg_287.read()))) {
          tmp2_reg_341 = tmp2_fu_240_p2.read();
          tmp5_reg_346 = tmp5_fu_245_p2.read();
          tmp6_reg_351 = tmp6_fu_256_p2.read();
      }
  }
  
  void Loop_1_proc::thread_ap_CS_fsm_pp0_stage0() {
      ap_CS_fsm_pp0_stage0 = ap_CS_fsm.read()[1];
  }
  
  void Loop_1_proc::thread_ap_CS_fsm_state1() {
      ap_CS_fsm_state1 = ap_CS_fsm.read()[0];
  }
  
  void Loop_1_proc::thread_ap_CS_fsm_state8() {
      ap_CS_fsm_state8 = ap_CS_fsm.read()[2];
  }
  
  void Loop_1_proc::thread_ap_block_pp0_stage0_flag00000000() {
      ap_block_pp0_stage0_flag00000000 = !esl_seteq<1,1,1>(ap_const_boolean_1, ap_const_boolean_1);
  }
  
  void Loop_1_proc::thread_ap_block_pp0_stage0_flag00001001() {
      ap_block_pp0_stage0_flag00001001 = ((esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter1.read()) && 
    esl_seteq<1,1,1>(exitcond_flatten_reg_287.read(), ap_const_lv1_0) && 
    esl_seteq<1,1,1>(ap_const_logic_0, p_hw_input_stencil_stream_V_value_V_empty_n.read())) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter5.read()) && 
    esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter4_exitcond_flatten_reg_287.read()) && 
    esl_seteq<1,1,1>(ap_const_logic_0, p_mul_stencil_update_stream_V_value_V_full_n.read())));
  }
  
  void Loop_1_proc::thread_ap_block_pp0_stage0_flag00011001() {
      ap_block_pp0_stage0_flag00011001 = ((esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter1.read()) && 
    esl_seteq<1,1,1>(exitcond_flatten_reg_287.read(), ap_const_lv1_0) && 
    esl_seteq<1,1,1>(ap_const_logic_0, p_hw_input_stencil_stream_V_value_V_empty_n.read())) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter5.read()) && 
    esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter4_exitcond_flatten_reg_287.read()) && 
    esl_seteq<1,1,1>(ap_const_logic_0, p_mul_stencil_update_stream_V_value_V_full_n.read())));
  }
  
  void Loop_1_proc::thread_ap_block_pp0_stage0_flag00011011() {
      ap_block_pp0_stage0_flag00011011 = ((esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter1.read()) && 
    esl_seteq<1,1,1>(exitcond_flatten_reg_287.read(), ap_const_lv1_0) && 
    esl_seteq<1,1,1>(ap_const_logic_0, p_hw_input_stencil_stream_V_value_V_empty_n.read())) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter5.read()) && 
    esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter4_exitcond_flatten_reg_287.read()) && 
    esl_seteq<1,1,1>(ap_const_logic_0, p_mul_stencil_update_stream_V_value_V_full_n.read())));
  }
  
  void Loop_1_proc::thread_ap_block_state1() {
      ap_block_state1 = (esl_seteq<1,1,1>(ap_const_logic_0, real_start.read()) || esl_seteq<1,1,1>(ap_done_reg.read(), ap_const_logic_1));
  }
  
  void Loop_1_proc::thread_ap_block_state2_pp0_stage0_iter0() {
      ap_block_state2_pp0_stage0_iter0 = !esl_seteq<1,1,1>(ap_const_boolean_1, ap_const_boolean_1);
  }
  
  void Loop_1_proc::thread_ap_block_state3_pp0_stage0_iter1() {
      ap_block_state3_pp0_stage0_iter1 = (esl_seteq<1,1,1>(exitcond_flatten_reg_287.read(), ap_const_lv1_0) && esl_seteq<1,1,1>(ap_const_logic_0, p_hw_input_stencil_stream_V_value_V_empty_n.read()));
  }
  
  void Loop_1_proc::thread_ap_block_state4_pp0_stage0_iter2() {
      ap_block_state4_pp0_stage0_iter2 = !esl_seteq<1,1,1>(ap_const_boolean_1, ap_const_boolean_1);
  }
  
  void Loop_1_proc::thread_ap_block_state5_pp0_stage0_iter3() {
      ap_block_state5_pp0_stage0_iter3 = !esl_seteq<1,1,1>(ap_const_boolean_1, ap_const_boolean_1);
  }
  
  void Loop_1_proc::thread_ap_block_state6_pp0_stage0_iter4() {
      ap_block_state6_pp0_stage0_iter4 = !esl_seteq<1,1,1>(ap_const_boolean_1, ap_const_boolean_1);
  }
  
  void Loop_1_proc::thread_ap_block_state7_pp0_stage0_iter5() {
      ap_block_state7_pp0_stage0_iter5 = (esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter4_exitcond_flatten_reg_287.read()) && esl_seteq<1,1,1>(ap_const_logic_0, p_mul_stencil_update_stream_V_value_V_full_n.read()));
  }
  
  void Loop_1_proc::thread_ap_condition_pp0_exit_iter0_state2() {
      if (esl_seteq<1,1,1>(exitcond_flatten_fu_116_p2.read(), ap_const_lv1_1)) {
          ap_condition_pp0_exit_iter0_state2 = ap_const_logic_1;
      } else {
          ap_condition_pp0_exit_iter0_state2 = ap_const_logic_0;
      }
  }
  
  void Loop_1_proc::thread_ap_done() {
      if (esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state8.read())) {
          ap_done = ap_const_logic_1;
      } else {
          ap_done = ap_done_reg.read();
      }
  }
  
  void Loop_1_proc::thread_ap_enable_pp0() {
      ap_enable_pp0 = (ap_idle_pp0.read() ^ ap_const_logic_1);
  }
  
  void Loop_1_proc::thread_ap_idle() {
      if ((esl_seteq<1,1,1>(ap_const_logic_0, real_start.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state1.read()))) {
          ap_idle = ap_const_logic_1;
      } else {
          ap_idle = ap_const_logic_0;
      }
  }
  
  void Loop_1_proc::thread_ap_idle_pp0() {
      if ((esl_seteq<1,1,1>(ap_const_logic_0, ap_enable_reg_pp0_iter0.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_0, ap_enable_reg_pp0_iter1.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_0, ap_enable_reg_pp0_iter2.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_0, ap_enable_reg_pp0_iter3.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_0, ap_enable_reg_pp0_iter4.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_0, ap_enable_reg_pp0_iter5.read()))) {
          ap_idle_pp0 = ap_const_logic_1;
      } else {
          ap_idle_pp0 = ap_const_logic_0;
      }
  }
  
  void Loop_1_proc::thread_ap_ready() {
      ap_ready = internal_ap_ready.read();
  }
  
  void Loop_1_proc::thread_exitcond_flatten_fu_116_p2() {
      exitcond_flatten_fu_116_p2 = (!indvar_flatten_reg_105.read().is_01() || !ap_const_lv21_1F8C94.is_01())? sc_lv<1>(): sc_lv<1>(indvar_flatten_reg_105.read() == ap_const_lv21_1F8C94);
  }
  
  void Loop_1_proc::thread_indvar_flatten_next_fu_122_p2() {
      indvar_flatten_next_fu_122_p2 = (!indvar_flatten_reg_105.read().is_01() || !ap_const_lv21_1.is_01())? sc_lv<21>(): (sc_biguint<21>(indvar_flatten_reg_105.read()) + sc_biguint<21>(ap_const_lv21_1));
  }
  
  void Loop_1_proc::thread_internal_ap_ready() {
      if (esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state8.read())) {
          internal_ap_ready = ap_const_logic_1;
      } else {
          internal_ap_ready = ap_const_logic_0;
      }
  }
  
  void Loop_1_proc::thread_p_327_fu_128_p1() {
      p_327_fu_128_p1 = p_hw_input_stencil_stream_V_value_V_dout.read().range(32-1, 0);
  }
  
  void Loop_1_proc::thread_p_336_fu_212_p3() {
      p_336_fu_212_p3 = esl_concat<31,1>(tmp_s_reg_316.read(), ap_const_lv1_0);
  }
  
  void Loop_1_proc::thread_p_348_fu_261_p3() {
      p_348_fu_261_p3 = esl_concat<31,1>(ap_reg_pp0_iter2_tmp_11_reg_321.read(), ap_const_lv1_0);
  }
  
  void Loop_1_proc::thread_p_354_fu_219_p3() {
      p_354_fu_219_p3 = esl_concat<30,2>(tmp_12_reg_326.read(), ap_const_lv2_0);
  }
  
  void Loop_1_proc::thread_p_360_fu_226_p3() {
      p_360_fu_226_p3 = esl_concat<31,1>(tmp_13_reg_331.read(), ap_const_lv1_0);
  }
  
  void Loop_1_proc::thread_p_372_fu_233_p3() {
      p_372_fu_233_p3 = esl_concat<31,1>(tmp_14_reg_336.read(), ap_const_lv1_0);
  }
  
  void Loop_1_proc::thread_p_379_fu_282_p2() {
      p_379_fu_282_p2 = (!tmp1_reg_356.read().is_01() || !tmp4_fu_278_p2.read().is_01())? sc_lv<32>(): (sc_biguint<32>(tmp1_reg_356.read()) + sc_biguint<32>(tmp4_fu_278_p2.read()));
  }
  
  void Loop_1_proc::thread_p_hw_input_stencil_stream_V_value_V_blk_n() {
      if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_pp0_stage0.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter1.read()) && 
           esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00000000.read(), ap_const_boolean_0) && 
           esl_seteq<1,1,1>(exitcond_flatten_reg_287.read(), ap_const_lv1_0))) {
          p_hw_input_stencil_stream_V_value_V_blk_n = p_hw_input_stencil_stream_V_value_V_empty_n.read();
      } else {
          p_hw_input_stencil_stream_V_value_V_blk_n = ap_const_logic_1;
      }
  }
  
  void Loop_1_proc::thread_p_hw_input_stencil_stream_V_value_V_read() {
      if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_pp0_stage0.read()) && 
           esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter1.read()) && 
           esl_seteq<1,1,1>(exitcond_flatten_reg_287.read(), ap_const_lv1_0) && 
           esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0))) {
          p_hw_input_stencil_stream_V_value_V_read = ap_const_logic_1;
      } else {
          p_hw_input_stencil_stream_V_value_V_read = ap_const_logic_0;
      }
  }
  
  void Loop_1_proc::thread_p_mul_stencil_update_stream_V_value_V_blk_n() {
      if ((esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00000000.read(), ap_const_boolean_0) && 
           esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter5.read()) && 
           esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter4_exitcond_flatten_reg_287.read()))) {
          p_mul_stencil_update_stream_V_value_V_blk_n = p_mul_stencil_update_stream_V_value_V_full_n.read();
      } else {
          p_mul_stencil_update_stream_V_value_V_blk_n = ap_const_logic_1;
      }
  }
  
  void Loop_1_proc::thread_p_mul_stencil_update_stream_V_value_V_din() {
      p_mul_stencil_update_stream_V_value_V_din = p_379_reg_361.read();
  }
  
  void Loop_1_proc::thread_p_mul_stencil_update_stream_V_value_V_write() {
      if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter5.read()) && 
           esl_seteq<1,1,1>(ap_const_lv1_0, ap_reg_pp0_iter4_exitcond_flatten_reg_287.read()) && 
           esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011001.read(), ap_const_boolean_0))) {
          p_mul_stencil_update_stream_V_value_V_write = ap_const_logic_1;
      } else {
          p_mul_stencil_update_stream_V_value_V_write = ap_const_logic_0;
      }
  }
  
  void Loop_1_proc::thread_real_start() {
      if (esl_seteq<1,1,1>(ap_const_logic_1, real_start_status_reg.read())) {
          real_start = ap_const_logic_0;
      } else {
          real_start = ap_start.read();
      }
  }
  
  void Loop_1_proc::thread_start_out() {
      start_out = real_start.read();
  }
  
  void Loop_1_proc::thread_start_write() {
      start_write = (ap_start.read() & start_control_reg.read());
  }
  
  void Loop_1_proc::thread_tmp1_fu_273_p2() {
      tmp1_fu_273_p2 = (!tmp2_reg_341.read().is_01() || !tmp3_fu_268_p2.read().is_01())? sc_lv<32>(): (sc_biguint<32>(tmp2_reg_341.read()) + sc_biguint<32>(tmp3_fu_268_p2.read()));
  }
  
  void Loop_1_proc::thread_tmp2_fu_240_p2() {
      tmp2_fu_240_p2 = (!p_327_reg_296.read().is_01() || !p_336_fu_212_p3.read().is_01())? sc_lv<32>(): (sc_biguint<32>(p_327_reg_296.read()) + sc_biguint<32>(p_336_fu_212_p3.read()));
  }
  
  void Loop_1_proc::thread_tmp3_fu_268_p2() {
      tmp3_fu_268_p2 = (!p_348_fu_261_p3.read().is_01() || !ap_reg_pp0_iter2_p_339_reg_301.read().is_01())? sc_lv<32>(): (sc_biguint<32>(p_348_fu_261_p3.read()) + sc_biguint<32>(ap_reg_pp0_iter2_p_339_reg_301.read()));
  }
  
  void Loop_1_proc::thread_tmp4_fu_278_p2() {
      tmp4_fu_278_p2 = (!ap_reg_pp0_iter3_tmp5_reg_346.read().is_01() || !ap_reg_pp0_iter3_tmp6_reg_351.read().is_01())? sc_lv<32>(): (sc_biguint<32>(ap_reg_pp0_iter3_tmp5_reg_346.read()) + sc_biguint<32>(ap_reg_pp0_iter3_tmp6_reg_351.read()));
  }
  
  void Loop_1_proc::thread_tmp5_fu_245_p2() {
      tmp5_fu_245_p2 = (!p_360_fu_226_p3.read().is_01() || !p_354_fu_219_p3.read().is_01())? sc_lv<32>(): (sc_biguint<32>(p_360_fu_226_p3.read()) + sc_biguint<32>(p_354_fu_219_p3.read()));
  }
  
  void Loop_1_proc::thread_tmp6_fu_256_p2() {
      tmp6_fu_256_p2 = (!p_363_reg_306.read().is_01() || !tmp7_fu_251_p2.read().is_01())? sc_lv<32>(): (sc_biguint<32>(p_363_reg_306.read()) + sc_biguint<32>(tmp7_fu_251_p2.read()));
  }
  
  void Loop_1_proc::thread_tmp7_fu_251_p2() {
      tmp7_fu_251_p2 = (!p_375_reg_311.read().is_01() || !p_372_fu_233_p3.read().is_01())? sc_lv<32>(): (sc_biguint<32>(p_375_reg_311.read()) + sc_biguint<32>(p_372_fu_233_p3.read()));
  }
  
  void Loop_1_proc::thread_ap_NS_fsm() {
      switch (ap_CS_fsm.read().to_uint64()) {
          case 1 : 
              if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_CS_fsm_state1.read()) && !(esl_seteq<1,1,1>(ap_const_logic_0, real_start.read()) || esl_seteq<1,1,1>(ap_done_reg.read(), ap_const_logic_1)))) {
                  ap_NS_fsm = ap_ST_fsm_pp0_stage0;
              } else {
                  ap_NS_fsm = ap_ST_fsm_state1;
              }
              break;
          case 2 : 
              if ((!(esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter5.read()) && esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0) && esl_seteq<1,1,1>(ap_enable_reg_pp0_iter4.read(), ap_const_logic_0)) && !(esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter0.read()) && esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0) && esl_seteq<1,1,1>(exitcond_flatten_fu_116_p2.read(), ap_const_lv1_1) && esl_seteq<1,1,1>(ap_enable_reg_pp0_iter1.read(), ap_const_logic_0)))) {
                  ap_NS_fsm = ap_ST_fsm_pp0_stage0;
              } else if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter5.read()) && 
    esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0) && 
    esl_seteq<1,1,1>(ap_enable_reg_pp0_iter4.read(), ap_const_logic_0)) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_enable_reg_pp0_iter0.read()) && 
    esl_seteq<1,1,1>(ap_block_pp0_stage0_flag00011011.read(), ap_const_boolean_0) && 
    esl_seteq<1,1,1>(exitcond_flatten_fu_116_p2.read(), ap_const_lv1_1) && 
    esl_seteq<1,1,1>(ap_enable_reg_pp0_iter1.read(), ap_const_logic_0)))) {
                  ap_NS_fsm = ap_ST_fsm_state8;
              } else {
                  ap_NS_fsm = ap_ST_fsm_pp0_stage0;
              }
              break;
          case 4 : 
              ap_NS_fsm = ap_ST_fsm_state1;
              break;
          default : 
              ap_NS_fsm = "XXX";
              break;
      }
  }
  
  }
  
  