text: /*
   * Generated by gen_defines.py
   *
   * DTS input file:
   *   /home/arachidi/zephyrproject/zephyr/build/zephyr/zephyr.dts.pre
   *
   * Directories with bindings:
   *   $ZEPHYR_BASE/dts/bindings
   *
   * Node dependency ordering (ordinal and path):
   *   0   /
   *   1   /aliases
   *   2   /chosen
   *   3   /leds
   *   4   /soc
   *   5   /cpus
   *   6   /cpus/cpu@0
   *   7   /cpus/cpu@0/interrupt-controller
   *   8   /soc/interrupt-controller@c000000
   *   9   /soc/pwm@10025000
   *   10  /leds/led_0
   *   11  /leds/led_1
   *   12  /leds/led_2
   *   13  /soc/aon@10000040
   *   14  /soc/clint@2000000
   *   15  /soc/debug-controller@0
   *   16  /soc/dtim@80000000
   *   17  /soc/error-device@3000
   *   18  /soc/i2c@10016000
   *   19  /soc/itim@8000000
   *   20  /soc/otp@10010000
   *   21  /soc/prci@10008000
   *   22  /soc/pwm@10015000
   *   23  /soc/pwm@10035000
   *   24  /soc/rom@1000
   *   25  /soc/rom@10000
   *   26  /soc/serial@10013000
   *   27  /soc/serial@10023000
   *   28  /soc/spi@10024000
   *   29  /soc/spi@10034000
   *   30  /soc/teststatus@4000
   *   31  /soc/wdog@10000000
   *   32  /soc/gpio@10012000
   *   33  /soc/gpio@10012000/pinctrl@10012038
   *   34  /soc/spi@10014000
   *   35  /soc/spi@10014000/flash@0
   *
   * Definitions derived from these nodes in dependency order are next,
   * followed by /chosen nodes.
   */
  
  /*
   * Devicetree node: /
   *
   * Node identifier: DT_N
   */
  
  /* Node's full path: */
  #define DT_N_PATH "/"
  
  /* Node's name with unit-address: */
  #define DT_N_FULL_NAME "/"
  #define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_cpus) fn(DT_N_S_soc) fn(DT_N_S_aliases) fn(DT_N_S_chosen) fn(DT_N_S_leds)
  #define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__)
  #define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus) fn(DT_N_S_soc) fn(DT_N_S_aliases) fn(DT_N_S_chosen) fn(DT_N_S_leds) 
  #define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) 
  
  /* Node's dependency ordinal: */
  #define DT_N_ORD 0
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_REQUIRES_ORDS /* nothing */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_SUPPORTS_ORDS \
  	1, /* /aliases */ \
  	2, /* /chosen */ \
  	3, /* /leds */ \
  	4, /* /soc */ \
  	5, /* /cpus */
  
  /* Existence and alternate IDs: */
  #define DT_N_EXISTS 1
  #define DT_N_INST_0_sifive_artya7 DT_N
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_REG_NUM 0
  #define DT_N_RANGES_NUM 0
  #define DT_N_FOREACH_RANGE(fn) 
  #define DT_N_IRQ_NUM 0
  #define DT_N_COMPAT_MATCHES_sifive_artya7 1
  #define DT_N_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_P_compatible {"sifive,artyA7"}
  #define DT_N_P_compatible_IDX_0 "sifive,artyA7"
  #define DT_N_P_compatible_IDX_0_EXISTS 1
  #define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
  #define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
  #define DT_N_P_compatible_LEN 1
  #define DT_N_P_compatible_EXISTS 1
  
  /*
   * Devicetree node: /aliases
   *
   * Node identifier: DT_N_S_aliases
   */
  
  /* Node's full path: */
  #define DT_N_S_aliases_PATH "/aliases"
  
  /* Node's name with unit-address: */
  #define DT_N_S_aliases_FULL_NAME "aliases"
  
  /* Node parent (/) identifier: */
  #define DT_N_S_aliases_PARENT DT_N
  #define DT_N_S_aliases_FOREACH_CHILD(fn) 
  #define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_aliases_ORD 1
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_aliases_REQUIRES_ORDS \
  	0, /* / */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_aliases_EXISTS 1
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_aliases_REG_NUM 0
  #define DT_N_S_aliases_RANGES_NUM 0
  #define DT_N_S_aliases_FOREACH_RANGE(fn) 
  #define DT_N_S_aliases_IRQ_NUM 0
  #define DT_N_S_aliases_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_aliases_PINCTRL_NUM 0
  
  /* (No generic property macros) */
  
  /*
   * Devicetree node: /chosen
   *
   * Node identifier: DT_N_S_chosen
   */
  
  /* Node's full path: */
  #define DT_N_S_chosen_PATH "/chosen"
  
  /* Node's name with unit-address: */
  #define DT_N_S_chosen_FULL_NAME "chosen"
  
  /* Node parent (/) identifier: */
  #define DT_N_S_chosen_PARENT DT_N
  #define DT_N_S_chosen_FOREACH_CHILD(fn) 
  #define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_chosen_ORD 2
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_chosen_REQUIRES_ORDS \
  	0, /* / */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_chosen_EXISTS 1
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_chosen_REG_NUM 0
  #define DT_N_S_chosen_RANGES_NUM 0
  #define DT_N_S_chosen_FOREACH_RANGE(fn) 
  #define DT_N_S_chosen_IRQ_NUM 0
  #define DT_N_S_chosen_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_chosen_PINCTRL_NUM 0
  
  /* (No generic property macros) */
  
  /*
   * Devicetree node: /leds
   *
   * Node identifier: DT_N_S_leds
   *
   * Binding (compatible = pwm-leds):
   *   $ZEPHYR_BASE/dts/bindings/led/pwm-leds.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_leds_PATH "/leds"
  
  /* Node's name with unit-address: */
  #define DT_N_S_leds_FULL_NAME "leds"
  
  /* Node parent (/) identifier: */
  #define DT_N_S_leds_PARENT DT_N
  #define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2)
  #define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__)
  #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) 
  #define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_leds_ORD 3
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_leds_REQUIRES_ORDS \
  	0, /* / */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_leds_SUPPORTS_ORDS \
  	10, /* /leds/led_0 */ \
  	11, /* /leds/led_1 */ \
  	12, /* /leds/led_2 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_leds_EXISTS 1
  #define DT_N_INST_0_pwm_leds DT_N_S_leds
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_leds_REG_NUM 0
  #define DT_N_S_leds_RANGES_NUM 0
  #define DT_N_S_leds_FOREACH_RANGE(fn) 
  #define DT_N_S_leds_IRQ_NUM 0
  #define DT_N_S_leds_COMPAT_MATCHES_pwm_leds 1
  #define DT_N_S_leds_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_leds_PINCTRL_NUM 0
  
  /* (No generic property macros) */
  
  /*
   * Devicetree node: /soc
   *
   * Node identifier: DT_N_S_soc
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_PATH "/soc"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_FULL_NAME "soc"
  
  /* Node parent (/) identifier: */
  #define DT_N_S_soc_PARENT DT_N
  #define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_wdog_10000000) fn(DT_N_S_soc_S_aon_10000040) fn(DT_N_S_soc_S_clint_2000000) fn(DT_N_S_soc_S_debug_controller_0) fn(DT_N_S_soc_S_dtim_80000000) fn(DT_N_S_soc_S_error_device_3000) fn(DT_N_S_soc_S_gpio_10012000) fn(DT_N_S_soc_S_i2c_10016000) fn(DT_N_S_soc_S_interrupt_controller_c000000) fn(DT_N_S_soc_S_itim_8000000) fn(DT_N_S_soc_S_otp_10010000) fn(DT_N_S_soc_S_prci_10008000) fn(DT_N_S_soc_S_pwm_10015000) fn(DT_N_S_soc_S_pwm_10025000) fn(DT_N_S_soc_S_pwm_10035000) fn(DT_N_S_soc_S_rom_1000) fn(DT_N_S_soc_S_rom_10000) fn(DT_N_S_soc_S_serial_10013000) fn(DT_N_S_soc_S_serial_10023000) fn(DT_N_S_soc_S_spi_10014000) fn(DT_N_S_soc_S_spi_10024000) fn(DT_N_S_soc_S_spi_10034000) fn(DT_N_S_soc_S_teststatus_4000)
  #define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, __VA_ARGS__) fn(DT_N_S_soc_S_aon_10000040, __VA_ARGS__) fn(DT_N_S_soc_S_clint_2000000, __VA_ARGS__) fn(DT_N_S_soc_S_debug_controller_0, __VA_ARGS__) fn(DT_N_S_soc_S_dtim_80000000, __VA_ARGS__) fn(DT_N_S_soc_S_error_device_3000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_10012000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_10016000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_c000000, __VA_ARGS__) fn(DT_N_S_soc_S_itim_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_otp_10010000, __VA_ARGS__) fn(DT_N_S_soc_S_prci_10008000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10015000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10025000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10035000, __VA_ARGS__) fn(DT_N_S_soc_S_rom_1000, __VA_ARGS__) fn(DT_N_S_soc_S_rom_10000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_10013000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_10023000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10014000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10024000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10034000, __VA_ARGS__) fn(DT_N_S_soc_S_teststatus_4000, __VA_ARGS__)
  #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_wdog_10000000) fn(DT_N_S_soc_S_aon_10000040) fn(DT_N_S_soc_S_clint_2000000) fn(DT_N_S_soc_S_debug_controller_0) fn(DT_N_S_soc_S_dtim_80000000) fn(DT_N_S_soc_S_error_device_3000) fn(DT_N_S_soc_S_gpio_10012000) fn(DT_N_S_soc_S_interrupt_controller_c000000) fn(DT_N_S_soc_S_itim_8000000) fn(DT_N_S_soc_S_otp_10010000) fn(DT_N_S_soc_S_prci_10008000) fn(DT_N_S_soc_S_pwm_10015000) fn(DT_N_S_soc_S_pwm_10025000) fn(DT_N_S_soc_S_pwm_10035000) fn(DT_N_S_soc_S_rom_1000) fn(DT_N_S_soc_S_rom_10000) fn(DT_N_S_soc_S_serial_10013000) fn(DT_N_S_soc_S_spi_10014000) fn(DT_N_S_soc_S_spi_10024000) fn(DT_N_S_soc_S_spi_10034000) fn(DT_N_S_soc_S_teststatus_4000) 
  #define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, __VA_ARGS__) fn(DT_N_S_soc_S_aon_10000040, __VA_ARGS__) fn(DT_N_S_soc_S_clint_2000000, __VA_ARGS__) fn(DT_N_S_soc_S_debug_controller_0, __VA_ARGS__) fn(DT_N_S_soc_S_dtim_80000000, __VA_ARGS__) fn(DT_N_S_soc_S_error_device_3000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_10012000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_c000000, __VA_ARGS__) fn(DT_N_S_soc_S_itim_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_otp_10010000, __VA_ARGS__) fn(DT_N_S_soc_S_prci_10008000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10015000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10025000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10035000, __VA_ARGS__) fn(DT_N_S_soc_S_rom_1000, __VA_ARGS__) fn(DT_N_S_soc_S_rom_10000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_10013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10014000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10024000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10034000, __VA_ARGS__) fn(DT_N_S_soc_S_teststatus_4000, __VA_ARGS__) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_ORD 4
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_REQUIRES_ORDS \
  	0, /* / */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_SUPPORTS_ORDS \
  	8, /* /soc/interrupt-controller@c000000 */ \
  	9, /* /soc/pwm@10025000 */ \
  	13, /* /soc/aon@10000040 */ \
  	14, /* /soc/clint@2000000 */ \
  	15, /* /soc/debug-controller@0 */ \
  	16, /* /soc/dtim@80000000 */ \
  	17, /* /soc/error-device@3000 */ \
  	18, /* /soc/i2c@10016000 */ \
  	19, /* /soc/itim@8000000 */ \
  	20, /* /soc/otp@10010000 */ \
  	21, /* /soc/prci@10008000 */ \
  	22, /* /soc/pwm@10015000 */ \
  	23, /* /soc/pwm@10035000 */ \
  	24, /* /soc/rom@1000 */ \
  	25, /* /soc/rom@10000 */ \
  	26, /* /soc/serial@10013000 */ \
  	27, /* /soc/serial@10023000 */ \
  	28, /* /soc/spi@10024000 */ \
  	29, /* /soc/spi@10034000 */ \
  	30, /* /soc/teststatus@4000 */ \
  	31, /* /soc/wdog@10000000 */ \
  	32, /* /soc/gpio@10012000 */ \
  	34, /* /soc/spi@10014000 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_EXISTS 1
  #define DT_N_INST_0_sifive_fe310g_0002_z0_soc DT_N_S_soc
  #define DT_N_INST_0_fe310_soc                 DT_N_S_soc
  #define DT_N_INST_0_sifive_soc                DT_N_S_soc
  #define DT_N_INST_0_simple_bus                DT_N_S_soc
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_REG_NUM 0
  #define DT_N_S_soc_RANGES_NUM 0
  #define DT_N_S_soc_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_IRQ_NUM 0
  #define DT_N_S_soc_COMPAT_MATCHES_sifive_fe310g_0002_z0_soc 1
  #define DT_N_S_soc_COMPAT_MATCHES_fe310_soc 1
  #define DT_N_S_soc_COMPAT_MATCHES_sifive_soc 1
  #define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
  #define DT_N_S_soc_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_P_compatible {"sifive,FE310G-0002-Z0-soc", "fe310-soc", "sifive-soc", "simple-bus"}
  #define DT_N_S_soc_P_compatible_IDX_0 "sifive,FE310G-0002-Z0-soc"
  #define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_P_compatible_IDX_1 "fe310-soc"
  #define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1
  #define DT_N_S_soc_P_compatible_IDX_2 "sifive-soc"
  #define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1
  #define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
  #define DT_N_S_soc_P_compatible_IDX_3_EXISTS 1
  #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \
  	fn(DT_N_S_soc, compatible, 1) \
  	fn(DT_N_S_soc, compatible, 2) \
  	fn(DT_N_S_soc, compatible, 3)
  #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)
  #define DT_N_S_soc_P_compatible_LEN 4
  #define DT_N_S_soc_P_compatible_EXISTS 1
  
  /*
   * Devicetree node: /cpus
   *
   * Node identifier: DT_N_S_cpus
   */
  
  /* Node's full path: */
  #define DT_N_S_cpus_PATH "/cpus"
  
  /* Node's name with unit-address: */
  #define DT_N_S_cpus_FULL_NAME "cpus"
  
  /* Node parent (/) identifier: */
  #define DT_N_S_cpus_PARENT DT_N
  #define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)
  #define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
  #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0) 
  #define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_cpus_ORD 5
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_cpus_REQUIRES_ORDS \
  	0, /* / */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_cpus_SUPPORTS_ORDS \
  	6, /* /cpus/cpu@0 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_cpus_EXISTS 1
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_cpus_REG_NUM 0
  #define DT_N_S_cpus_RANGES_NUM 0
  #define DT_N_S_cpus_FOREACH_RANGE(fn) 
  #define DT_N_S_cpus_IRQ_NUM 0
  #define DT_N_S_cpus_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_cpus_PINCTRL_NUM 0
  
  /* (No generic property macros) */
  
  /*
   * Devicetree node: /cpus/cpu@0
   *
   * Node identifier: DT_N_S_cpus_S_cpu_0
   */
  
  /* Node's full path: */
  #define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"
  
  /* Node's name with unit-address: */
  #define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"
  
  /* Node parent (/cpus) identifier: */
  #define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus
  #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller)
  #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller, __VA_ARGS__)
  #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller) 
  #define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller, __VA_ARGS__) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_cpus_S_cpu_0_ORD 6
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
  	5, /* /cpus */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \
  	7, /* /cpus/cpu@0/interrupt-controller */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_cpus_S_cpu_0_EXISTS 1
  #define DT_N_INST_0_sifive_rocket0 DT_N_S_cpus_S_cpu_0
  #define DT_N_INST_0_riscv          DT_N_S_cpus_S_cpu_0
  #define DT_N_NODELABEL_cpu         DT_N_S_cpus_S_cpu_0
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_cpus_S_cpu_0_REG_NUM 1
  #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
  #define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
  #define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
  #define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
  #define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_sifive_rocket0 1
  #define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_riscv 1
  #define DT_N_S_cpus_S_cpu_0_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_cpus_S_cpu_0_P_compatible {"sifive,rocket0", "riscv"}
  #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "sifive,rocket0"
  #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_1 "riscv"
  #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_1_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0) \
  	fn(DT_N_S_cpus_S_cpu_0, compatible, 1)
  #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__) \
  	fn(DT_N_S_cpus_S_cpu_0, compatible, 1, __VA_ARGS__)
  #define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 2
  #define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
  #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
  #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, reg, 0)
  #define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, reg, 0, __VA_ARGS__)
  #define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_P_status "okay"
  #define DT_N_S_cpus_S_cpu_0_P_status_STRING_TOKEN okay
  #define DT_N_S_cpus_S_cpu_0_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_cpus_S_cpu_0_P_status_ENUM_IDX 1
  #define DT_N_S_cpus_S_cpu_0_P_status_ENUM_TOKEN okay
  #define DT_N_S_cpus_S_cpu_0_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_cpus_S_cpu_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, status, 0) \
  	fn(DT_N_S_cpus_S_cpu_0, status, 1) \
  	fn(DT_N_S_cpus_S_cpu_0, status, 2) \
  	fn(DT_N_S_cpus_S_cpu_0, status, 3)
  #define DT_N_S_cpus_S_cpu_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_cpus_S_cpu_0, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_cpus_S_cpu_0, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_cpus_S_cpu_0, status, 3, __VA_ARGS__)
  #define DT_N_S_cpus_S_cpu_0_P_status_EXISTS 1
  
  /*
   * Devicetree node: /cpus/cpu@0/interrupt-controller
   *
   * Node identifier: DT_N_S_cpus_S_cpu_0_S_interrupt_controller
   *
   * Binding (compatible = riscv,cpu-intc):
   *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/riscv,cpu-intc.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_PATH "/cpus/cpu@0/interrupt-controller"
  
  /* Node's name with unit-address: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_FULL_NAME "interrupt-controller"
  
  /* Node parent (/cpus/cpu@0) identifier: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_PARENT DT_N_S_cpus_S_cpu_0
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_FOREACH_CHILD(fn) 
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_ORD 7
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_REQUIRES_ORDS \
  	6, /* /cpus/cpu@0 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_SUPPORTS_ORDS \
  	8, /* /soc/interrupt-controller@c000000 */ \
  	14, /* /soc/clint@2000000 */ \
  	15, /* /soc/debug-controller@0 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_EXISTS 1
  #define DT_N_INST_0_riscv_cpu_intc DT_N_S_cpus_S_cpu_0_S_interrupt_controller
  #define DT_N_NODELABEL_hlic        DT_N_S_cpus_S_cpu_0_S_interrupt_controller
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_REG_NUM 0
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_RANGES_NUM 0
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_FOREACH_RANGE(fn) 
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_IRQ_NUM 0
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_COMPAT_MATCHES_riscv_cpu_intc 1
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_interrupt_controller 1
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_interrupt_controller_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_compatible {"riscv,cpu-intc"}
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_compatible_IDX_0 "riscv,cpu-intc"
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller, compatible, 0)
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller, compatible, 0, __VA_ARGS__)
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_compatible_LEN 1
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_compatible_EXISTS 1
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_wakeup_source 0
  #define DT_N_S_cpus_S_cpu_0_S_interrupt_controller_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/interrupt-controller@c000000
   *
   * Node identifier: DT_N_S_soc_S_interrupt_controller_c000000
   *
   * Binding (compatible = sifive,plic-1.0.0):
   *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_PATH "/soc/interrupt-controller@c000000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_FULL_NAME "interrupt-controller@c000000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_interrupt_controller_c000000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_interrupt_controller_c000000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_interrupt_controller_c000000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_interrupt_controller_c000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_ORD 8
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	7, /* /cpus/cpu@0/interrupt-controller */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_SUPPORTS_ORDS \
  	9, /* /soc/pwm@10025000 */ \
  	13, /* /soc/aon@10000040 */ \
  	18, /* /soc/i2c@10016000 */ \
  	22, /* /soc/pwm@10015000 */ \
  	23, /* /soc/pwm@10035000 */ \
  	26, /* /soc/serial@10013000 */ \
  	27, /* /soc/serial@10023000 */ \
  	28, /* /soc/spi@10024000 */ \
  	29, /* /soc/spi@10034000 */ \
  	31, /* /soc/wdog@10000000 */ \
  	32, /* /soc/gpio@10012000 */ \
  	34, /* /soc/spi@10014000 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_EXISTS 1
  #define DT_N_INST_0_sifive_plic_1_0_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_NODELABEL_plic           DT_N_S_soc_S_interrupt_controller_c000000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_NUM 3
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_0_VAL_ADDRESS 201326592 /* 0xc000000 */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_1_VAL_ADDRESS 201334784 /* 0xc002000 */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_1_VAL_SIZE 2088960 /* 0x1fe000 */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_2_VAL_ADDRESS 203423744 /* 0xc200000 */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_2_VAL_SIZE 65011712 /* 0x3e00000 */
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_NAME_prio_VAL_ADDRESS DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_NAME_prio_VAL_SIZE DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_NAME_irq_en_VAL_ADDRESS DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_1_VAL_ADDRESS
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_NAME_irq_en_VAL_SIZE DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_1_VAL_SIZE
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_NAME_reg_VAL_ADDRESS DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_2_VAL_ADDRESS
  #define DT_N_S_soc_S_interrupt_controller_c000000_REG_NAME_reg_VAL_SIZE DT_N_S_soc_S_interrupt_controller_c000000_REG_IDX_2_VAL_SIZE
  #define DT_N_S_soc_S_interrupt_controller_c000000_RANGES_NUM 0
  #define DT_N_S_soc_S_interrupt_controller_c000000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_interrupt_controller_c000000_IRQ_NUM 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_IRQ_IDX_0_VAL_irq 11
  #define DT_N_S_soc_S_interrupt_controller_c000000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_COMPAT_MATCHES_sifive_plic_1_0_0 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_riscv_ndev 52
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_riscv_ndev_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg {201326592 /* 0xc000000 */, 8192 /* 0x2000 */, 201334784 /* 0xc002000 */, 2088960 /* 0x1fe000 */, 203423744 /* 0xc200000 */, 65011712 /* 0x3e00000 */}
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_0 201326592
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_1 8192
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_2 201334784
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_3 2088960
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_4 203423744
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_4_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_5 65011712
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_IDX_5_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 0) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 1) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 2) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 3) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 4) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 5)
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg, 5, __VA_ARGS__)
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_riscv_max_priority 7
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_riscv_max_priority_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_interrupt_controller 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_interrupt_controller_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_compatible {"sifive,plic-1.0.0"}
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_compatible_IDX_0 "sifive,plic-1.0.0"
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_c000000, compatible, 0)
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_c000000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_compatible_LEN 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names {"prio", "irq_en", "reg"}
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_IDX_0 "prio"
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_IDX_1 "irq_en"
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_IDX_2 "reg"
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_c000000, reg_names, 0) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg_names, 1) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg_names, 2)
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_c000000, reg_names, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg_names, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_interrupt_controller_c000000, reg_names, 2, __VA_ARGS__)
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_LEN 3
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_wakeup_source 0
  #define DT_N_S_soc_S_interrupt_controller_c000000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/pwm@10025000
   *
   * Node identifier: DT_N_S_soc_S_pwm_10025000
   *
   * Binding (compatible = sifive,pwm0):
   *   $ZEPHYR_BASE/dts/bindings/pwm/sifive,pwm0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_pwm_10025000_PATH "/soc/pwm@10025000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_pwm_10025000_FULL_NAME "pwm@10025000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_pwm_10025000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_pwm_10025000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_pwm_10025000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_pwm_10025000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_pwm_10025000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_pwm_10025000_ORD 9
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_pwm_10025000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_pwm_10025000_SUPPORTS_ORDS \
  	10, /* /leds/led_0 */ \
  	11, /* /leds/led_1 */ \
  	12, /* /leds/led_2 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_pwm_10025000_EXISTS 1
  #define DT_N_INST_1_sifive_pwm0 DT_N_S_soc_S_pwm_10025000
  #define DT_N_NODELABEL_pwm1     DT_N_S_soc_S_pwm_10025000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_pwm_10025000_REG_NUM 1
  #define DT_N_S_soc_S_pwm_10025000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_REG_IDX_0_VAL_ADDRESS 268587008 /* 0x10025000 */
  #define DT_N_S_soc_S_pwm_10025000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_pwm_10025000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_pwm_10025000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_pwm_10025000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_pwm_10025000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_pwm_10025000_RANGES_NUM 0
  #define DT_N_S_soc_S_pwm_10025000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_pwm_10025000_IRQ_NUM 4
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_0_VAL_irq 11531
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_1_VAL_irq 11787
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_1_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_1_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_1_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_2_VAL_irq 12043
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_2_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_2_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_2_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_3_VAL_irq 12299
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_3_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_3_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10025000_IRQ_IDX_3_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_COMPAT_MATCHES_sifive_pwm0 1
  #define DT_N_S_soc_S_pwm_10025000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_pwm_10025000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_pwm_10025000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_pwm_10025000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_reg {268587008 /* 0x10025000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_pwm_10025000_P_reg_IDX_0 268587008
  #define DT_N_S_soc_S_pwm_10025000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_pwm_10025000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10025000, reg, 0) \
  	fn(DT_N_S_soc_S_pwm_10025000, reg, 1)
  #define DT_N_S_soc_S_pwm_10025000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10025000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10025000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts {44 /* 0x2c */, 1 /* 0x1 */, 45 /* 0x2d */, 1 /* 0x1 */, 46 /* 0x2e */, 1 /* 0x1 */, 47 /* 0x2f */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_0 44
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_2 45
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_3 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_4 46
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_4_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_5 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_5_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_6 47
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_6_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_7 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_IDX_7_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10025000, interrupts, 0) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 1) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 2) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 3) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 4) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 5) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 6) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 7)
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10025000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 5, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 6, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, interrupts, 7, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10025000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_sifive_compare_width 16
  #define DT_N_S_soc_S_pwm_10025000_P_sifive_compare_width_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_label "pwm_1"
  #define DT_N_S_soc_S_pwm_10025000_P_label_STRING_TOKEN pwm_1
  #define DT_N_S_soc_S_pwm_10025000_P_label_STRING_UPPER_TOKEN PWM_1
  #define DT_N_S_soc_S_pwm_10025000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10025000, label, 0) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 1) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 2) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 3) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 4)
  #define DT_N_S_soc_S_pwm_10025000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10025000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10025000_P_label_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_status "okay"
  #define DT_N_S_soc_S_pwm_10025000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_pwm_10025000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_pwm_10025000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_pwm_10025000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_pwm_10025000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_pwm_10025000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10025000, status, 0) \
  	fn(DT_N_S_soc_S_pwm_10025000, status, 1) \
  	fn(DT_N_S_soc_S_pwm_10025000, status, 2) \
  	fn(DT_N_S_soc_S_pwm_10025000, status, 3)
  #define DT_N_S_soc_S_pwm_10025000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10025000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10025000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10025000_P_status_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_compatible {"sifive,pwm0"}
  #define DT_N_S_soc_S_pwm_10025000_P_compatible_IDX_0 "sifive,pwm0"
  #define DT_N_S_soc_S_pwm_10025000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10025000, compatible, 0)
  #define DT_N_S_soc_S_pwm_10025000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10025000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10025000_P_compatible_LEN 1
  #define DT_N_S_soc_S_pwm_10025000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_reg_names {"control"}
  #define DT_N_S_soc_S_pwm_10025000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_pwm_10025000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10025000, reg_names, 0)
  #define DT_N_S_soc_S_pwm_10025000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10025000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10025000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_pwm_10025000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10025000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10025000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10025000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_pwm_10025000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_pwm_10025000_P_wakeup_source 0
  #define DT_N_S_soc_S_pwm_10025000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /leds/led_0
   *
   * Node identifier: DT_N_S_leds_S_led_0
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_leds_S_led_0_PATH "/leds/led_0"
  
  /* Node's name with unit-address: */
  #define DT_N_S_leds_S_led_0_FULL_NAME "led_0"
  
  /* Node parent (/leds) identifier: */
  #define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds
  #define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 
  #define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_leds_S_led_0_ORD 10
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
  	3, /* /leds */ \
  	9, /* /soc/pwm@10025000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_leds_S_led_0_EXISTS 1
  #define DT_N_ALIAS_pwm_led0 DT_N_S_leds_S_led_0
  #define DT_N_NODELABEL_led0 DT_N_S_leds_S_led_0
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_leds_S_led_0_REG_NUM 0
  #define DT_N_S_leds_S_led_0_RANGES_NUM 0
  #define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) 
  #define DT_N_S_leds_S_led_0_IRQ_NUM 0
  #define DT_N_S_leds_S_led_0_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_leds_S_led_0_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_leds_S_led_0_P_pwms_IDX_0_EXISTS 1
  #define DT_N_S_leds_S_led_0_P_pwms_IDX_0_PH DT_N_S_soc_S_pwm_10025000
  #define DT_N_S_leds_S_led_0_P_pwms_IDX_0_VAL_channel 1
  #define DT_N_S_leds_S_led_0_P_pwms_IDX_0_VAL_channel_EXISTS 1
  #define DT_N_S_leds_S_led_0_P_pwms_IDX_0_VAL_period 0
  #define DT_N_S_leds_S_led_0_P_pwms_IDX_0_VAL_period_EXISTS 1
  #define DT_N_S_leds_S_led_0_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, pwms, 0)
  #define DT_N_S_leds_S_led_0_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, pwms, 0, __VA_ARGS__)
  #define DT_N_S_leds_S_led_0_P_pwms_LEN 1
  #define DT_N_S_leds_S_led_0_P_pwms_EXISTS 1
  #define DT_N_S_leds_S_led_0_P_label "Green LED"
  #define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN Green_LED
  #define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN GREEN_LED
  #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0) \
  	fn(DT_N_S_leds_S_led_0, label, 1) \
  	fn(DT_N_S_leds_S_led_0, label, 2) \
  	fn(DT_N_S_leds_S_led_0, label, 3) \
  	fn(DT_N_S_leds_S_led_0, label, 4) \
  	fn(DT_N_S_leds_S_led_0, label, 5) \
  	fn(DT_N_S_leds_S_led_0, label, 6) \
  	fn(DT_N_S_leds_S_led_0, label, 7) \
  	fn(DT_N_S_leds_S_led_0, label, 8)
  #define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 4, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 5, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 6, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 7, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_0, label, 8, __VA_ARGS__)
  #define DT_N_S_leds_S_led_0_P_label_EXISTS 1
  
  /*
   * Devicetree node: /leds/led_1
   *
   * Node identifier: DT_N_S_leds_S_led_1
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_leds_S_led_1_PATH "/leds/led_1"
  
  /* Node's name with unit-address: */
  #define DT_N_S_leds_S_led_1_FULL_NAME "led_1"
  
  /* Node parent (/leds) identifier: */
  #define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds
  #define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 
  #define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_leds_S_led_1_ORD 11
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_leds_S_led_1_REQUIRES_ORDS \
  	3, /* /leds */ \
  	9, /* /soc/pwm@10025000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_leds_S_led_1_EXISTS 1
  #define DT_N_ALIAS_pwm_led1 DT_N_S_leds_S_led_1
  #define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_leds_S_led_1_REG_NUM 0
  #define DT_N_S_leds_S_led_1_RANGES_NUM 0
  #define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn) 
  #define DT_N_S_leds_S_led_1_IRQ_NUM 0
  #define DT_N_S_leds_S_led_1_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_leds_S_led_1_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_leds_S_led_1_P_pwms_IDX_0_EXISTS 1
  #define DT_N_S_leds_S_led_1_P_pwms_IDX_0_PH DT_N_S_soc_S_pwm_10025000
  #define DT_N_S_leds_S_led_1_P_pwms_IDX_0_VAL_channel 2
  #define DT_N_S_leds_S_led_1_P_pwms_IDX_0_VAL_channel_EXISTS 1
  #define DT_N_S_leds_S_led_1_P_pwms_IDX_0_VAL_period 0
  #define DT_N_S_leds_S_led_1_P_pwms_IDX_0_VAL_period_EXISTS 1
  #define DT_N_S_leds_S_led_1_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, pwms, 0)
  #define DT_N_S_leds_S_led_1_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, pwms, 0, __VA_ARGS__)
  #define DT_N_S_leds_S_led_1_P_pwms_LEN 1
  #define DT_N_S_leds_S_led_1_P_pwms_EXISTS 1
  #define DT_N_S_leds_S_led_1_P_label "Blue LED"
  #define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN Blue_LED
  #define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN BLUE_LED
  #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_1, label, 0) \
  	fn(DT_N_S_leds_S_led_1, label, 1) \
  	fn(DT_N_S_leds_S_led_1, label, 2) \
  	fn(DT_N_S_leds_S_led_1, label, 3) \
  	fn(DT_N_S_leds_S_led_1, label, 4) \
  	fn(DT_N_S_leds_S_led_1, label, 5) \
  	fn(DT_N_S_leds_S_led_1, label, 6) \
  	fn(DT_N_S_leds_S_led_1, label, 7)
  #define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_1, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_1, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_1, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_1, label, 4, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_1, label, 5, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_1, label, 6, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_1, label, 7, __VA_ARGS__)
  #define DT_N_S_leds_S_led_1_P_label_EXISTS 1
  
  /*
   * Devicetree node: /leds/led_2
   *
   * Node identifier: DT_N_S_leds_S_led_2
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_leds_S_led_2_PATH "/leds/led_2"
  
  /* Node's name with unit-address: */
  #define DT_N_S_leds_S_led_2_FULL_NAME "led_2"
  
  /* Node parent (/leds) identifier: */
  #define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds
  #define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 
  #define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_leds_S_led_2_ORD 12
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_leds_S_led_2_REQUIRES_ORDS \
  	3, /* /leds */ \
  	9, /* /soc/pwm@10025000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_leds_S_led_2_EXISTS 1
  #define DT_N_ALIAS_pwm_led2 DT_N_S_leds_S_led_2
  #define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_leds_S_led_2_REG_NUM 0
  #define DT_N_S_leds_S_led_2_RANGES_NUM 0
  #define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn) 
  #define DT_N_S_leds_S_led_2_IRQ_NUM 0
  #define DT_N_S_leds_S_led_2_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_leds_S_led_2_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_leds_S_led_2_P_pwms_IDX_0_EXISTS 1
  #define DT_N_S_leds_S_led_2_P_pwms_IDX_0_PH DT_N_S_soc_S_pwm_10025000
  #define DT_N_S_leds_S_led_2_P_pwms_IDX_0_VAL_channel 3
  #define DT_N_S_leds_S_led_2_P_pwms_IDX_0_VAL_channel_EXISTS 1
  #define DT_N_S_leds_S_led_2_P_pwms_IDX_0_VAL_period 0
  #define DT_N_S_leds_S_led_2_P_pwms_IDX_0_VAL_period_EXISTS 1
  #define DT_N_S_leds_S_led_2_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, pwms, 0)
  #define DT_N_S_leds_S_led_2_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, pwms, 0, __VA_ARGS__)
  #define DT_N_S_leds_S_led_2_P_pwms_LEN 1
  #define DT_N_S_leds_S_led_2_P_pwms_EXISTS 1
  #define DT_N_S_leds_S_led_2_P_label "Red LED"
  #define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN Red_LED
  #define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN RED_LED
  #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_2, label, 0) \
  	fn(DT_N_S_leds_S_led_2, label, 1) \
  	fn(DT_N_S_leds_S_led_2, label, 2) \
  	fn(DT_N_S_leds_S_led_2, label, 3) \
  	fn(DT_N_S_leds_S_led_2, label, 4) \
  	fn(DT_N_S_leds_S_led_2, label, 5) \
  	fn(DT_N_S_leds_S_led_2, label, 6)
  #define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_2, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_2, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_2, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_2, label, 4, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_2, label, 5, __VA_ARGS__) \
  	fn(DT_N_S_leds_S_led_2, label, 6, __VA_ARGS__)
  #define DT_N_S_leds_S_led_2_P_label_EXISTS 1
  
  /*
   * Devicetree node: /soc/aon@10000040
   *
   * Node identifier: DT_N_S_soc_S_aon_10000040
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_aon_10000040_PATH "/soc/aon@10000040"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_aon_10000040_FULL_NAME "aon@10000040"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_aon_10000040_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_aon_10000040_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_aon_10000040_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_aon_10000040_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_aon_10000040_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_aon_10000040_ORD 13
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_aon_10000040_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_aon_10000040_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_aon_10000040_EXISTS 1
  #define DT_N_INST_0_sifive_aon0 DT_N_S_soc_S_aon_10000040
  #define DT_N_NODELABEL_aon      DT_N_S_soc_S_aon_10000040
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_aon_10000040_REG_NUM 1
  #define DT_N_S_soc_S_aon_10000040_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_REG_IDX_0_VAL_ADDRESS 268435520 /* 0x10000040 */
  #define DT_N_S_soc_S_aon_10000040_REG_IDX_0_VAL_SIZE 2496 /* 0x9c0 */
  #define DT_N_S_soc_S_aon_10000040_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_aon_10000040_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_aon_10000040_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_aon_10000040_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_aon_10000040_RANGES_NUM 0
  #define DT_N_S_soc_S_aon_10000040_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_aon_10000040_IRQ_NUM 1
  #define DT_N_S_soc_S_aon_10000040_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_IRQ_IDX_0_VAL_irq 779
  #define DT_N_S_soc_S_aon_10000040_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_aon_10000040_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_COMPAT_MATCHES_sifive_aon0 1
  #define DT_N_S_soc_S_aon_10000040_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_aon_10000040_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_aon_10000040_P_compatible {"sifive,aon0"}
  #define DT_N_S_soc_S_aon_10000040_P_compatible_IDX_0 "sifive,aon0"
  #define DT_N_S_soc_S_aon_10000040_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_aon_10000040, compatible, 0)
  #define DT_N_S_soc_S_aon_10000040_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_aon_10000040, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_aon_10000040_P_compatible_LEN 1
  #define DT_N_S_soc_S_aon_10000040_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_interrupts {2 /* 0x2 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_aon_10000040_P_interrupts_IDX_0 2
  #define DT_N_S_soc_S_aon_10000040_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_aon_10000040_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_aon_10000040, interrupts, 0) \
  	fn(DT_N_S_soc_S_aon_10000040, interrupts, 1)
  #define DT_N_S_soc_S_aon_10000040_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_aon_10000040, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_aon_10000040, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_aon_10000040_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_reg {268435520 /* 0x10000040 */, 2496 /* 0x9c0 */}
  #define DT_N_S_soc_S_aon_10000040_P_reg_IDX_0 268435520
  #define DT_N_S_soc_S_aon_10000040_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_reg_IDX_1 2496
  #define DT_N_S_soc_S_aon_10000040_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_aon_10000040, reg, 0) \
  	fn(DT_N_S_soc_S_aon_10000040, reg, 1)
  #define DT_N_S_soc_S_aon_10000040_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_aon_10000040, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_aon_10000040, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_aon_10000040_P_reg_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_reg_names {"control"}
  #define DT_N_S_soc_S_aon_10000040_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_aon_10000040_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_aon_10000040_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_aon_10000040, reg_names, 0)
  #define DT_N_S_soc_S_aon_10000040_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_aon_10000040, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_aon_10000040_P_reg_names_LEN 1
  #define DT_N_S_soc_S_aon_10000040_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/clint@2000000
   *
   * Node identifier: DT_N_S_soc_S_clint_2000000
   *
   * Binding (compatible = riscv,clint0):
   *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/riscv,clint0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_clint_2000000_PATH "/soc/clint@2000000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_clint_2000000_FULL_NAME "clint@2000000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_clint_2000000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_clint_2000000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_clint_2000000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_clint_2000000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_clint_2000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_clint_2000000_ORD 14
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_clint_2000000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	7, /* /cpus/cpu@0/interrupt-controller */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_clint_2000000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_clint_2000000_EXISTS 1
  #define DT_N_INST_0_riscv_clint0 DT_N_S_soc_S_clint_2000000
  #define DT_N_NODELABEL_clint     DT_N_S_soc_S_clint_2000000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_clint_2000000_REG_NUM 1
  #define DT_N_S_soc_S_clint_2000000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_REG_IDX_0_VAL_ADDRESS 33554432 /* 0x2000000 */
  #define DT_N_S_soc_S_clint_2000000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
  #define DT_N_S_soc_S_clint_2000000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_clint_2000000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_clint_2000000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_clint_2000000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_clint_2000000_RANGES_NUM 0
  #define DT_N_S_soc_S_clint_2000000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_clint_2000000_IRQ_NUM 2
  #define DT_N_S_soc_S_clint_2000000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_IRQ_IDX_0_VAL_irq 3
  #define DT_N_S_soc_S_clint_2000000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_IRQ_IDX_1_VAL_irq 7
  #define DT_N_S_soc_S_clint_2000000_IRQ_IDX_1_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_COMPAT_MATCHES_riscv_clint0 1
  #define DT_N_S_soc_S_clint_2000000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_clint_2000000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_clint_2000000_P_reg {33554432 /* 0x2000000 */, 65536 /* 0x10000 */}
  #define DT_N_S_soc_S_clint_2000000_P_reg_IDX_0 33554432
  #define DT_N_S_soc_S_clint_2000000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_reg_IDX_1 65536
  #define DT_N_S_soc_S_clint_2000000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_clint_2000000, reg, 0) \
  	fn(DT_N_S_soc_S_clint_2000000, reg, 1)
  #define DT_N_S_soc_S_clint_2000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_clint_2000000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_clint_2000000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_clint_2000000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_interrupt_controller 1
  #define DT_N_S_soc_S_clint_2000000_P_interrupt_controller_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_compatible {"riscv,clint0"}
  #define DT_N_S_soc_S_clint_2000000_P_compatible_IDX_0 "riscv,clint0"
  #define DT_N_S_soc_S_clint_2000000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_clint_2000000, compatible, 0)
  #define DT_N_S_soc_S_clint_2000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_clint_2000000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_clint_2000000_P_compatible_LEN 1
  #define DT_N_S_soc_S_clint_2000000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_reg_names {"control"}
  #define DT_N_S_soc_S_clint_2000000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_clint_2000000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_clint_2000000, reg_names, 0)
  #define DT_N_S_soc_S_clint_2000000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_clint_2000000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_clint_2000000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_clint_2000000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_clint_2000000_P_wakeup_source 0
  #define DT_N_S_soc_S_clint_2000000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/debug-controller@0
   *
   * Node identifier: DT_N_S_soc_S_debug_controller_0
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_debug_controller_0_PATH "/soc/debug-controller@0"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_debug_controller_0_FULL_NAME "debug-controller@0"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_debug_controller_0_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_debug_controller_0_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_debug_controller_0_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_debug_controller_0_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_debug_controller_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_debug_controller_0_ORD 15
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_debug_controller_0_REQUIRES_ORDS \
  	4, /* /soc */ \
  	7, /* /cpus/cpu@0/interrupt-controller */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_debug_controller_0_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_debug_controller_0_EXISTS 1
  #define DT_N_INST_0_sifive_debug_013 DT_N_S_soc_S_debug_controller_0
  #define DT_N_INST_0_riscv_debug_013  DT_N_S_soc_S_debug_controller_0
  #define DT_N_NODELABEL_debug         DT_N_S_soc_S_debug_controller_0
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_debug_controller_0_REG_NUM 1
  #define DT_N_S_soc_S_debug_controller_0_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
  #define DT_N_S_soc_S_debug_controller_0_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_debug_controller_0_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_debug_controller_0_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_debug_controller_0_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_debug_controller_0_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_debug_controller_0_RANGES_NUM 0
  #define DT_N_S_soc_S_debug_controller_0_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_debug_controller_0_IRQ_NUM 1
  #define DT_N_S_soc_S_debug_controller_0_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_IRQ_IDX_0_VAL_irq 65535
  #define DT_N_S_soc_S_debug_controller_0_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_COMPAT_MATCHES_sifive_debug_013 1
  #define DT_N_S_soc_S_debug_controller_0_COMPAT_MATCHES_riscv_debug_013 1
  #define DT_N_S_soc_S_debug_controller_0_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_debug_controller_0_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_debug_controller_0_P_compatible {"sifive,debug-013", "riscv,debug-013"}
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_IDX_0 "sifive,debug-013"
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_IDX_1 "riscv,debug-013"
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_debug_controller_0, compatible, 0) \
  	fn(DT_N_S_soc_S_debug_controller_0, compatible, 1)
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_debug_controller_0, compatible, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_debug_controller_0, compatible, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_LEN 2
  #define DT_N_S_soc_S_debug_controller_0_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_interrupts_extended_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_reg {0 /* 0x0 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_debug_controller_0_P_reg_IDX_0 0
  #define DT_N_S_soc_S_debug_controller_0_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_debug_controller_0_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_debug_controller_0, reg, 0) \
  	fn(DT_N_S_soc_S_debug_controller_0, reg, 1)
  #define DT_N_S_soc_S_debug_controller_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_debug_controller_0, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_debug_controller_0, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_debug_controller_0_P_reg_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_reg_names {"control"}
  #define DT_N_S_soc_S_debug_controller_0_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_debug_controller_0_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_debug_controller_0_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_debug_controller_0, reg_names, 0)
  #define DT_N_S_soc_S_debug_controller_0_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_debug_controller_0, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_debug_controller_0_P_reg_names_LEN 1
  #define DT_N_S_soc_S_debug_controller_0_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/dtim@80000000
   *
   * Node identifier: DT_N_S_soc_S_dtim_80000000
   *
   * Binding (compatible = sifive,dtim0):
   *   $ZEPHYR_BASE/dts/bindings/sram/sifive,dtim0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_dtim_80000000_PATH "/soc/dtim@80000000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_dtim_80000000_FULL_NAME "dtim@80000000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_dtim_80000000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_dtim_80000000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_dtim_80000000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_dtim_80000000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_dtim_80000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_dtim_80000000_ORD 16
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_dtim_80000000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_dtim_80000000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_dtim_80000000_EXISTS 1
  #define DT_N_INST_0_sifive_dtim0 DT_N_S_soc_S_dtim_80000000
  #define DT_N_NODELABEL_dtim      DT_N_S_soc_S_dtim_80000000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_dtim_80000000_REG_NUM 1
  #define DT_N_S_soc_S_dtim_80000000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_REG_IDX_0_VAL_ADDRESS 2147483648 /* 0x80000000 */
  #define DT_N_S_soc_S_dtim_80000000_REG_IDX_0_VAL_SIZE 16384 /* 0x4000 */
  #define DT_N_S_soc_S_dtim_80000000_REG_NAME_mem_VAL_ADDRESS DT_N_S_soc_S_dtim_80000000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_dtim_80000000_REG_NAME_mem_VAL_SIZE DT_N_S_soc_S_dtim_80000000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_dtim_80000000_RANGES_NUM 0
  #define DT_N_S_soc_S_dtim_80000000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_dtim_80000000_IRQ_NUM 0
  #define DT_N_S_soc_S_dtim_80000000_COMPAT_MATCHES_sifive_dtim0 1
  #define DT_N_S_soc_S_dtim_80000000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_dtim_80000000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_dtim_80000000_P_reg {2147483648 /* 0x80000000 */, 16384 /* 0x4000 */}
  #define DT_N_S_soc_S_dtim_80000000_P_reg_IDX_0 2147483648
  #define DT_N_S_soc_S_dtim_80000000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_P_reg_IDX_1 16384
  #define DT_N_S_soc_S_dtim_80000000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dtim_80000000, reg, 0) \
  	fn(DT_N_S_soc_S_dtim_80000000, reg, 1)
  #define DT_N_S_soc_S_dtim_80000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dtim_80000000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_dtim_80000000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_dtim_80000000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_P_compatible {"sifive,dtim0"}
  #define DT_N_S_soc_S_dtim_80000000_P_compatible_IDX_0 "sifive,dtim0"
  #define DT_N_S_soc_S_dtim_80000000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dtim_80000000, compatible, 0)
  #define DT_N_S_soc_S_dtim_80000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dtim_80000000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_dtim_80000000_P_compatible_LEN 1
  #define DT_N_S_soc_S_dtim_80000000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_P_reg_names {"mem"}
  #define DT_N_S_soc_S_dtim_80000000_P_reg_names_IDX_0 "mem"
  #define DT_N_S_soc_S_dtim_80000000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dtim_80000000, reg_names, 0)
  #define DT_N_S_soc_S_dtim_80000000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dtim_80000000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_dtim_80000000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_dtim_80000000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_dtim_80000000_P_wakeup_source 0
  #define DT_N_S_soc_S_dtim_80000000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/error-device@3000
   *
   * Node identifier: DT_N_S_soc_S_error_device_3000
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_error_device_3000_PATH "/soc/error-device@3000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_error_device_3000_FULL_NAME "error-device@3000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_error_device_3000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_error_device_3000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_error_device_3000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_error_device_3000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_error_device_3000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_error_device_3000_ORD 17
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_error_device_3000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_error_device_3000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_error_device_3000_EXISTS 1
  #define DT_N_INST_0_sifive_error0 DT_N_S_soc_S_error_device_3000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_error_device_3000_REG_NUM 1
  #define DT_N_S_soc_S_error_device_3000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_error_device_3000_REG_IDX_0_VAL_ADDRESS 12288 /* 0x3000 */
  #define DT_N_S_soc_S_error_device_3000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_error_device_3000_REG_NAME_mem_VAL_ADDRESS DT_N_S_soc_S_error_device_3000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_error_device_3000_REG_NAME_mem_VAL_SIZE DT_N_S_soc_S_error_device_3000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_error_device_3000_RANGES_NUM 0
  #define DT_N_S_soc_S_error_device_3000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_error_device_3000_IRQ_NUM 0
  #define DT_N_S_soc_S_error_device_3000_COMPAT_MATCHES_sifive_error0 1
  #define DT_N_S_soc_S_error_device_3000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_error_device_3000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_error_device_3000_P_compatible {"sifive,error0"}
  #define DT_N_S_soc_S_error_device_3000_P_compatible_IDX_0 "sifive,error0"
  #define DT_N_S_soc_S_error_device_3000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_error_device_3000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_error_device_3000, compatible, 0)
  #define DT_N_S_soc_S_error_device_3000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_error_device_3000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_error_device_3000_P_compatible_LEN 1
  #define DT_N_S_soc_S_error_device_3000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_error_device_3000_P_reg {12288 /* 0x3000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_error_device_3000_P_reg_IDX_0 12288
  #define DT_N_S_soc_S_error_device_3000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_error_device_3000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_error_device_3000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_error_device_3000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_error_device_3000, reg, 0) \
  	fn(DT_N_S_soc_S_error_device_3000, reg, 1)
  #define DT_N_S_soc_S_error_device_3000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_error_device_3000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_error_device_3000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_error_device_3000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_error_device_3000_P_reg_names {"mem"}
  #define DT_N_S_soc_S_error_device_3000_P_reg_names_IDX_0 "mem"
  #define DT_N_S_soc_S_error_device_3000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_error_device_3000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_error_device_3000, reg_names, 0)
  #define DT_N_S_soc_S_error_device_3000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_error_device_3000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_error_device_3000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_error_device_3000_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/i2c@10016000
   *
   * Node identifier: DT_N_S_soc_S_i2c_10016000
   *
   * Binding (compatible = sifive,i2c0):
   *   $ZEPHYR_BASE/dts/bindings/i2c/sifive,i2c0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_i2c_10016000_PATH "/soc/i2c@10016000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_i2c_10016000_FULL_NAME "i2c@10016000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_i2c_10016000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_i2c_10016000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_i2c_10016000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_i2c_10016000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_i2c_10016000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_i2c_10016000_ORD 18
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_i2c_10016000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_i2c_10016000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_i2c_10016000_EXISTS 1
  #define DT_N_INST_0_sifive_i2c0 DT_N_S_soc_S_i2c_10016000
  #define DT_N_NODELABEL_i2c0     DT_N_S_soc_S_i2c_10016000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_i2c_10016000_REG_NUM 1
  #define DT_N_S_soc_S_i2c_10016000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_REG_IDX_0_VAL_ADDRESS 268525568 /* 0x10016000 */
  #define DT_N_S_soc_S_i2c_10016000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_i2c_10016000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_i2c_10016000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_i2c_10016000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_i2c_10016000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_i2c_10016000_RANGES_NUM 0
  #define DT_N_S_soc_S_i2c_10016000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_i2c_10016000_IRQ_NUM 1
  #define DT_N_S_soc_S_i2c_10016000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_IRQ_IDX_0_VAL_irq 13579
  #define DT_N_S_soc_S_i2c_10016000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_i2c_10016000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_COMPAT_MATCHES_sifive_i2c0 1
  #define DT_N_S_soc_S_i2c_10016000_STATUS_disabled 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_i2c_10016000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_i2c_10016000_P_reg {268525568 /* 0x10016000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_i2c_10016000_P_reg_IDX_0 268525568
  #define DT_N_S_soc_S_i2c_10016000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_i2c_10016000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_10016000, reg, 0) \
  	fn(DT_N_S_soc_S_i2c_10016000, reg, 1)
  #define DT_N_S_soc_S_i2c_10016000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_10016000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_i2c_10016000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_label "i2c_0"
  #define DT_N_S_soc_S_i2c_10016000_P_label_STRING_TOKEN i2c_0
  #define DT_N_S_soc_S_i2c_10016000_P_label_STRING_UPPER_TOKEN I2C_0
  #define DT_N_S_soc_S_i2c_10016000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_10016000, label, 0) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 1) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 2) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 3) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 4)
  #define DT_N_S_soc_S_i2c_10016000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_10016000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_i2c_10016000_P_label_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_status "disabled"
  #define DT_N_S_soc_S_i2c_10016000_P_status_STRING_TOKEN disabled
  #define DT_N_S_soc_S_i2c_10016000_P_status_STRING_UPPER_TOKEN DISABLED
  #define DT_N_S_soc_S_i2c_10016000_P_status_ENUM_IDX 2
  #define DT_N_S_soc_S_i2c_10016000_P_status_ENUM_TOKEN disabled
  #define DT_N_S_soc_S_i2c_10016000_P_status_ENUM_UPPER_TOKEN DISABLED
  #define DT_N_S_soc_S_i2c_10016000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_10016000, status, 0) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 1) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 2) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 3) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 4) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 5) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 6) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 7)
  #define DT_N_S_soc_S_i2c_10016000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_10016000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 5, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 6, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, status, 7, __VA_ARGS__)
  #define DT_N_S_soc_S_i2c_10016000_P_status_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_compatible {"sifive,i2c0"}
  #define DT_N_S_soc_S_i2c_10016000_P_compatible_IDX_0 "sifive,i2c0"
  #define DT_N_S_soc_S_i2c_10016000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_10016000, compatible, 0)
  #define DT_N_S_soc_S_i2c_10016000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_10016000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_i2c_10016000_P_compatible_LEN 1
  #define DT_N_S_soc_S_i2c_10016000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_reg_names {"control"}
  #define DT_N_S_soc_S_i2c_10016000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_i2c_10016000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_10016000, reg_names, 0)
  #define DT_N_S_soc_S_i2c_10016000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_10016000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_i2c_10016000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_i2c_10016000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts {52 /* 0x34 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts_IDX_0 52
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_10016000, interrupts, 0) \
  	fn(DT_N_S_soc_S_i2c_10016000, interrupts, 1)
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_10016000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_i2c_10016000, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_i2c_10016000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_i2c_10016000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_i2c_10016000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_i2c_10016000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_i2c_10016000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_i2c_10016000_P_wakeup_source 0
  #define DT_N_S_soc_S_i2c_10016000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/itim@8000000
   *
   * Node identifier: DT_N_S_soc_S_itim_8000000
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_itim_8000000_PATH "/soc/itim@8000000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_itim_8000000_FULL_NAME "itim@8000000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_itim_8000000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_itim_8000000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_itim_8000000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_itim_8000000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_itim_8000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_itim_8000000_ORD 19
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_itim_8000000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_itim_8000000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_itim_8000000_EXISTS 1
  #define DT_N_INST_0_sifive_itim0 DT_N_S_soc_S_itim_8000000
  #define DT_N_NODELABEL_itim      DT_N_S_soc_S_itim_8000000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_itim_8000000_REG_NUM 1
  #define DT_N_S_soc_S_itim_8000000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_itim_8000000_REG_IDX_0_VAL_ADDRESS 134217728 /* 0x8000000 */
  #define DT_N_S_soc_S_itim_8000000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */
  #define DT_N_S_soc_S_itim_8000000_REG_NAME_mem_VAL_ADDRESS DT_N_S_soc_S_itim_8000000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_itim_8000000_REG_NAME_mem_VAL_SIZE DT_N_S_soc_S_itim_8000000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_itim_8000000_RANGES_NUM 0
  #define DT_N_S_soc_S_itim_8000000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_itim_8000000_IRQ_NUM 0
  #define DT_N_S_soc_S_itim_8000000_COMPAT_MATCHES_sifive_itim0 1
  #define DT_N_S_soc_S_itim_8000000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_itim_8000000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_itim_8000000_P_compatible {"sifive,itim0"}
  #define DT_N_S_soc_S_itim_8000000_P_compatible_IDX_0 "sifive,itim0"
  #define DT_N_S_soc_S_itim_8000000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_itim_8000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_itim_8000000, compatible, 0)
  #define DT_N_S_soc_S_itim_8000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_itim_8000000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_itim_8000000_P_compatible_LEN 1
  #define DT_N_S_soc_S_itim_8000000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_itim_8000000_P_reg {134217728 /* 0x8000000 */, 8192 /* 0x2000 */}
  #define DT_N_S_soc_S_itim_8000000_P_reg_IDX_0 134217728
  #define DT_N_S_soc_S_itim_8000000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_itim_8000000_P_reg_IDX_1 8192
  #define DT_N_S_soc_S_itim_8000000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_itim_8000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_itim_8000000, reg, 0) \
  	fn(DT_N_S_soc_S_itim_8000000, reg, 1)
  #define DT_N_S_soc_S_itim_8000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_itim_8000000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_itim_8000000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_itim_8000000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_itim_8000000_P_reg_names {"mem"}
  #define DT_N_S_soc_S_itim_8000000_P_reg_names_IDX_0 "mem"
  #define DT_N_S_soc_S_itim_8000000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_itim_8000000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_itim_8000000, reg_names, 0)
  #define DT_N_S_soc_S_itim_8000000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_itim_8000000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_itim_8000000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_itim_8000000_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/otp@10010000
   *
   * Node identifier: DT_N_S_soc_S_otp_10010000
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_otp_10010000_PATH "/soc/otp@10010000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_otp_10010000_FULL_NAME "otp@10010000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_otp_10010000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_otp_10010000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_otp_10010000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_otp_10010000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_otp_10010000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_otp_10010000_ORD 20
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_otp_10010000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_otp_10010000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_otp_10010000_EXISTS 1
  #define DT_N_INST_0_sifive_otp0 DT_N_S_soc_S_otp_10010000
  #define DT_N_NODELABEL_otp      DT_N_S_soc_S_otp_10010000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_otp_10010000_REG_NUM 2
  #define DT_N_S_soc_S_otp_10010000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_REG_IDX_0_VAL_ADDRESS 268500992 /* 0x10010000 */
  #define DT_N_S_soc_S_otp_10010000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_otp_10010000_REG_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_REG_IDX_1_VAL_ADDRESS 131072 /* 0x20000 */
  #define DT_N_S_soc_S_otp_10010000_REG_IDX_1_VAL_SIZE 8192 /* 0x2000 */
  #define DT_N_S_soc_S_otp_10010000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_otp_10010000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_otp_10010000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_otp_10010000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_otp_10010000_REG_NAME_mem_VAL_ADDRESS DT_N_S_soc_S_otp_10010000_REG_IDX_1_VAL_ADDRESS
  #define DT_N_S_soc_S_otp_10010000_REG_NAME_mem_VAL_SIZE DT_N_S_soc_S_otp_10010000_REG_IDX_1_VAL_SIZE
  #define DT_N_S_soc_S_otp_10010000_RANGES_NUM 0
  #define DT_N_S_soc_S_otp_10010000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_otp_10010000_IRQ_NUM 0
  #define DT_N_S_soc_S_otp_10010000_COMPAT_MATCHES_sifive_otp0 1
  #define DT_N_S_soc_S_otp_10010000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_otp_10010000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_otp_10010000_P_compatible {"sifive,otp0"}
  #define DT_N_S_soc_S_otp_10010000_P_compatible_IDX_0 "sifive,otp0"
  #define DT_N_S_soc_S_otp_10010000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_otp_10010000, compatible, 0)
  #define DT_N_S_soc_S_otp_10010000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_otp_10010000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_otp_10010000_P_compatible_LEN 1
  #define DT_N_S_soc_S_otp_10010000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg {268500992 /* 0x10010000 */, 4096 /* 0x1000 */, 131072 /* 0x20000 */, 8192 /* 0x2000 */}
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_0 268500992
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_2 131072
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_3 8192
  #define DT_N_S_soc_S_otp_10010000_P_reg_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_otp_10010000, reg, 0) \
  	fn(DT_N_S_soc_S_otp_10010000, reg, 1) \
  	fn(DT_N_S_soc_S_otp_10010000, reg, 2) \
  	fn(DT_N_S_soc_S_otp_10010000, reg, 3)
  #define DT_N_S_soc_S_otp_10010000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_otp_10010000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_otp_10010000, reg, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_otp_10010000, reg, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_otp_10010000, reg, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_otp_10010000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg_names {"control", "mem"}
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_IDX_1 "mem"
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_otp_10010000, reg_names, 0) \
  	fn(DT_N_S_soc_S_otp_10010000, reg_names, 1)
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_otp_10010000, reg_names, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_otp_10010000, reg_names, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_LEN 2
  #define DT_N_S_soc_S_otp_10010000_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/prci@10008000
   *
   * Node identifier: DT_N_S_soc_S_prci_10008000
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_prci_10008000_PATH "/soc/prci@10008000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_prci_10008000_FULL_NAME "prci@10008000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_prci_10008000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_prci_10008000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_prci_10008000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_prci_10008000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_prci_10008000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_prci_10008000_ORD 21
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_prci_10008000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_prci_10008000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_prci_10008000_EXISTS 1
  #define DT_N_INST_0_sifive_freedome300prci0 DT_N_S_soc_S_prci_10008000
  #define DT_N_NODELABEL_prci                 DT_N_S_soc_S_prci_10008000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_prci_10008000_REG_NUM 1
  #define DT_N_S_soc_S_prci_10008000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_prci_10008000_REG_IDX_0_VAL_ADDRESS 268468224 /* 0x10008000 */
  #define DT_N_S_soc_S_prci_10008000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_prci_10008000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_prci_10008000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_prci_10008000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_prci_10008000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_prci_10008000_RANGES_NUM 0
  #define DT_N_S_soc_S_prci_10008000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_prci_10008000_IRQ_NUM 0
  #define DT_N_S_soc_S_prci_10008000_COMPAT_MATCHES_sifive_freedome300prci0 1
  #define DT_N_S_soc_S_prci_10008000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_prci_10008000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_prci_10008000_P_compatible {"sifive,freedome300prci0"}
  #define DT_N_S_soc_S_prci_10008000_P_compatible_IDX_0 "sifive,freedome300prci0"
  #define DT_N_S_soc_S_prci_10008000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_prci_10008000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_prci_10008000, compatible, 0)
  #define DT_N_S_soc_S_prci_10008000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_prci_10008000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_prci_10008000_P_compatible_LEN 1
  #define DT_N_S_soc_S_prci_10008000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_prci_10008000_P_reg {268468224 /* 0x10008000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_prci_10008000_P_reg_IDX_0 268468224
  #define DT_N_S_soc_S_prci_10008000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_prci_10008000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_prci_10008000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_prci_10008000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_prci_10008000, reg, 0) \
  	fn(DT_N_S_soc_S_prci_10008000, reg, 1)
  #define DT_N_S_soc_S_prci_10008000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_prci_10008000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_prci_10008000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_prci_10008000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_prci_10008000_P_reg_names {"control"}
  #define DT_N_S_soc_S_prci_10008000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_prci_10008000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_prci_10008000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_prci_10008000, reg_names, 0)
  #define DT_N_S_soc_S_prci_10008000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_prci_10008000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_prci_10008000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_prci_10008000_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/pwm@10015000
   *
   * Node identifier: DT_N_S_soc_S_pwm_10015000
   *
   * Binding (compatible = sifive,pwm0):
   *   $ZEPHYR_BASE/dts/bindings/pwm/sifive,pwm0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_pwm_10015000_PATH "/soc/pwm@10015000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_pwm_10015000_FULL_NAME "pwm@10015000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_pwm_10015000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_pwm_10015000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_pwm_10015000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_pwm_10015000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_pwm_10015000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_pwm_10015000_ORD 22
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_pwm_10015000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_pwm_10015000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_pwm_10015000_EXISTS 1
  #define DT_N_INST_0_sifive_pwm0 DT_N_S_soc_S_pwm_10015000
  #define DT_N_NODELABEL_pwm0     DT_N_S_soc_S_pwm_10015000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_pwm_10015000_REG_NUM 1
  #define DT_N_S_soc_S_pwm_10015000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_REG_IDX_0_VAL_ADDRESS 268521472 /* 0x10015000 */
  #define DT_N_S_soc_S_pwm_10015000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_pwm_10015000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_pwm_10015000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_pwm_10015000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_pwm_10015000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_pwm_10015000_RANGES_NUM 0
  #define DT_N_S_soc_S_pwm_10015000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_pwm_10015000_IRQ_NUM 4
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_0_VAL_irq 10507
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_1_VAL_irq 10763
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_1_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_1_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_1_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_2_VAL_irq 11019
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_2_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_2_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_2_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_3_VAL_irq 11275
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_3_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_3_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10015000_IRQ_IDX_3_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_COMPAT_MATCHES_sifive_pwm0 1
  #define DT_N_S_soc_S_pwm_10015000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_pwm_10015000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_pwm_10015000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_pwm_10015000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_reg {268521472 /* 0x10015000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_pwm_10015000_P_reg_IDX_0 268521472
  #define DT_N_S_soc_S_pwm_10015000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_pwm_10015000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10015000, reg, 0) \
  	fn(DT_N_S_soc_S_pwm_10015000, reg, 1)
  #define DT_N_S_soc_S_pwm_10015000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10015000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10015000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */, 41 /* 0x29 */, 1 /* 0x1 */, 42 /* 0x2a */, 1 /* 0x1 */, 43 /* 0x2b */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_0 40
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_2 41
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_3 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_4 42
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_4_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_5 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_5_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_6 43
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_6_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_7 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_IDX_7_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10015000, interrupts, 0) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 1) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 2) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 3) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 4) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 5) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 6) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 7)
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10015000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 5, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 6, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, interrupts, 7, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10015000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_sifive_compare_width 8
  #define DT_N_S_soc_S_pwm_10015000_P_sifive_compare_width_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_label "pwm_0"
  #define DT_N_S_soc_S_pwm_10015000_P_label_STRING_TOKEN pwm_0
  #define DT_N_S_soc_S_pwm_10015000_P_label_STRING_UPPER_TOKEN PWM_0
  #define DT_N_S_soc_S_pwm_10015000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10015000, label, 0) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 1) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 2) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 3) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 4)
  #define DT_N_S_soc_S_pwm_10015000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10015000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10015000_P_label_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_status "okay"
  #define DT_N_S_soc_S_pwm_10015000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_pwm_10015000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_pwm_10015000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_pwm_10015000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_pwm_10015000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_pwm_10015000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10015000, status, 0) \
  	fn(DT_N_S_soc_S_pwm_10015000, status, 1) \
  	fn(DT_N_S_soc_S_pwm_10015000, status, 2) \
  	fn(DT_N_S_soc_S_pwm_10015000, status, 3)
  #define DT_N_S_soc_S_pwm_10015000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10015000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10015000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10015000_P_status_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_compatible {"sifive,pwm0"}
  #define DT_N_S_soc_S_pwm_10015000_P_compatible_IDX_0 "sifive,pwm0"
  #define DT_N_S_soc_S_pwm_10015000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10015000, compatible, 0)
  #define DT_N_S_soc_S_pwm_10015000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10015000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10015000_P_compatible_LEN 1
  #define DT_N_S_soc_S_pwm_10015000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_reg_names {"control"}
  #define DT_N_S_soc_S_pwm_10015000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_pwm_10015000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10015000, reg_names, 0)
  #define DT_N_S_soc_S_pwm_10015000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10015000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10015000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_pwm_10015000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10015000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10015000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10015000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_pwm_10015000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_pwm_10015000_P_wakeup_source 0
  #define DT_N_S_soc_S_pwm_10015000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/pwm@10035000
   *
   * Node identifier: DT_N_S_soc_S_pwm_10035000
   *
   * Binding (compatible = sifive,pwm0):
   *   $ZEPHYR_BASE/dts/bindings/pwm/sifive,pwm0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_pwm_10035000_PATH "/soc/pwm@10035000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_pwm_10035000_FULL_NAME "pwm@10035000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_pwm_10035000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_pwm_10035000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_pwm_10035000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_pwm_10035000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_pwm_10035000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_pwm_10035000_ORD 23
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_pwm_10035000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_pwm_10035000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_pwm_10035000_EXISTS 1
  #define DT_N_INST_2_sifive_pwm0 DT_N_S_soc_S_pwm_10035000
  #define DT_N_NODELABEL_pwm2     DT_N_S_soc_S_pwm_10035000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_pwm_10035000_REG_NUM 1
  #define DT_N_S_soc_S_pwm_10035000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_REG_IDX_0_VAL_ADDRESS 268652544 /* 0x10035000 */
  #define DT_N_S_soc_S_pwm_10035000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_pwm_10035000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_pwm_10035000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_pwm_10035000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_pwm_10035000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_pwm_10035000_RANGES_NUM 0
  #define DT_N_S_soc_S_pwm_10035000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_pwm_10035000_IRQ_NUM 4
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_0_VAL_irq 12555
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_1_VAL_irq 12811
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_1_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_1_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_1_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_2_VAL_irq 13067
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_2_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_2_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_2_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_3_VAL_irq 13323
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_3_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_3_VAL_priority 1
  #define DT_N_S_soc_S_pwm_10035000_IRQ_IDX_3_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_COMPAT_MATCHES_sifive_pwm0 1
  #define DT_N_S_soc_S_pwm_10035000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_pwm_10035000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_pwm_10035000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_pwm_10035000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_reg {268652544 /* 0x10035000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_pwm_10035000_P_reg_IDX_0 268652544
  #define DT_N_S_soc_S_pwm_10035000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_pwm_10035000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10035000, reg, 0) \
  	fn(DT_N_S_soc_S_pwm_10035000, reg, 1)
  #define DT_N_S_soc_S_pwm_10035000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10035000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10035000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts {48 /* 0x30 */, 1 /* 0x1 */, 49 /* 0x31 */, 1 /* 0x1 */, 50 /* 0x32 */, 1 /* 0x1 */, 51 /* 0x33 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_0 48
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_2 49
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_3 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_4 50
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_4_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_5 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_5_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_6 51
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_6_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_7 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_IDX_7_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10035000, interrupts, 0) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 1) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 2) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 3) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 4) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 5) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 6) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 7)
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10035000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 5, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 6, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, interrupts, 7, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10035000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_sifive_compare_width 16
  #define DT_N_S_soc_S_pwm_10035000_P_sifive_compare_width_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_label "pwm_2"
  #define DT_N_S_soc_S_pwm_10035000_P_label_STRING_TOKEN pwm_2
  #define DT_N_S_soc_S_pwm_10035000_P_label_STRING_UPPER_TOKEN PWM_2
  #define DT_N_S_soc_S_pwm_10035000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10035000, label, 0) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 1) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 2) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 3) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 4)
  #define DT_N_S_soc_S_pwm_10035000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10035000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10035000_P_label_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_status "okay"
  #define DT_N_S_soc_S_pwm_10035000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_pwm_10035000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_pwm_10035000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_pwm_10035000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_pwm_10035000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_pwm_10035000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10035000, status, 0) \
  	fn(DT_N_S_soc_S_pwm_10035000, status, 1) \
  	fn(DT_N_S_soc_S_pwm_10035000, status, 2) \
  	fn(DT_N_S_soc_S_pwm_10035000, status, 3)
  #define DT_N_S_soc_S_pwm_10035000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10035000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_pwm_10035000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10035000_P_status_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_compatible {"sifive,pwm0"}
  #define DT_N_S_soc_S_pwm_10035000_P_compatible_IDX_0 "sifive,pwm0"
  #define DT_N_S_soc_S_pwm_10035000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10035000, compatible, 0)
  #define DT_N_S_soc_S_pwm_10035000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10035000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10035000_P_compatible_LEN 1
  #define DT_N_S_soc_S_pwm_10035000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_reg_names {"control"}
  #define DT_N_S_soc_S_pwm_10035000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_pwm_10035000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pwm_10035000, reg_names, 0)
  #define DT_N_S_soc_S_pwm_10035000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pwm_10035000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_pwm_10035000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_pwm_10035000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10035000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10035000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_pwm_10035000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_pwm_10035000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_pwm_10035000_P_wakeup_source 0
  #define DT_N_S_soc_S_pwm_10035000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/rom@1000
   *
   * Node identifier: DT_N_S_soc_S_rom_1000
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_rom_1000_PATH "/soc/rom@1000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_rom_1000_FULL_NAME "rom@1000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_rom_1000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_rom_1000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_rom_1000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_rom_1000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_rom_1000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_rom_1000_ORD 24
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_rom_1000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_rom_1000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_rom_1000_EXISTS 1
  #define DT_N_INST_0_sifive_modeselect0 DT_N_S_soc_S_rom_1000
  #define DT_N_NODELABEL_modeselect      DT_N_S_soc_S_rom_1000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_rom_1000_REG_NUM 1
  #define DT_N_S_soc_S_rom_1000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_1000_REG_IDX_0_VAL_ADDRESS 4096 /* 0x1000 */
  #define DT_N_S_soc_S_rom_1000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_rom_1000_REG_NAME_mem_VAL_ADDRESS DT_N_S_soc_S_rom_1000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_rom_1000_REG_NAME_mem_VAL_SIZE DT_N_S_soc_S_rom_1000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_rom_1000_RANGES_NUM 0
  #define DT_N_S_soc_S_rom_1000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_rom_1000_IRQ_NUM 0
  #define DT_N_S_soc_S_rom_1000_COMPAT_MATCHES_sifive_modeselect0 1
  #define DT_N_S_soc_S_rom_1000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_rom_1000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_rom_1000_P_compatible {"sifive,modeselect0"}
  #define DT_N_S_soc_S_rom_1000_P_compatible_IDX_0 "sifive,modeselect0"
  #define DT_N_S_soc_S_rom_1000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_1000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rom_1000, compatible, 0)
  #define DT_N_S_soc_S_rom_1000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rom_1000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_rom_1000_P_compatible_LEN 1
  #define DT_N_S_soc_S_rom_1000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_rom_1000_P_reg {4096 /* 0x1000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_rom_1000_P_reg_IDX_0 4096
  #define DT_N_S_soc_S_rom_1000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_1000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_rom_1000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_rom_1000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rom_1000, reg, 0) \
  	fn(DT_N_S_soc_S_rom_1000, reg, 1)
  #define DT_N_S_soc_S_rom_1000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rom_1000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_rom_1000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_rom_1000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_rom_1000_P_reg_names {"mem"}
  #define DT_N_S_soc_S_rom_1000_P_reg_names_IDX_0 "mem"
  #define DT_N_S_soc_S_rom_1000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_1000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rom_1000, reg_names, 0)
  #define DT_N_S_soc_S_rom_1000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rom_1000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_rom_1000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_rom_1000_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/rom@10000
   *
   * Node identifier: DT_N_S_soc_S_rom_10000
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_rom_10000_PATH "/soc/rom@10000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_rom_10000_FULL_NAME "rom@10000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_rom_10000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_rom_10000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_rom_10000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_rom_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_rom_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_rom_10000_ORD 25
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_rom_10000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_rom_10000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_rom_10000_EXISTS 1
  #define DT_N_INST_0_sifive_maskrom0 DT_N_S_soc_S_rom_10000
  #define DT_N_NODELABEL_maskrom      DT_N_S_soc_S_rom_10000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_rom_10000_REG_NUM 1
  #define DT_N_S_soc_S_rom_10000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */
  #define DT_N_S_soc_S_rom_10000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */
  #define DT_N_S_soc_S_rom_10000_REG_NAME_mem_VAL_ADDRESS DT_N_S_soc_S_rom_10000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_rom_10000_REG_NAME_mem_VAL_SIZE DT_N_S_soc_S_rom_10000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_rom_10000_RANGES_NUM 0
  #define DT_N_S_soc_S_rom_10000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_rom_10000_IRQ_NUM 0
  #define DT_N_S_soc_S_rom_10000_COMPAT_MATCHES_sifive_maskrom0 1
  #define DT_N_S_soc_S_rom_10000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_rom_10000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_rom_10000_P_compatible {"sifive,maskrom0"}
  #define DT_N_S_soc_S_rom_10000_P_compatible_IDX_0 "sifive,maskrom0"
  #define DT_N_S_soc_S_rom_10000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_10000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rom_10000, compatible, 0)
  #define DT_N_S_soc_S_rom_10000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rom_10000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_rom_10000_P_compatible_LEN 1
  #define DT_N_S_soc_S_rom_10000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_rom_10000_P_reg {65536 /* 0x10000 */, 8192 /* 0x2000 */}
  #define DT_N_S_soc_S_rom_10000_P_reg_IDX_0 65536
  #define DT_N_S_soc_S_rom_10000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_10000_P_reg_IDX_1 8192
  #define DT_N_S_soc_S_rom_10000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_rom_10000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rom_10000, reg, 0) \
  	fn(DT_N_S_soc_S_rom_10000, reg, 1)
  #define DT_N_S_soc_S_rom_10000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rom_10000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_rom_10000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_rom_10000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_rom_10000_P_reg_names {"mem"}
  #define DT_N_S_soc_S_rom_10000_P_reg_names_IDX_0 "mem"
  #define DT_N_S_soc_S_rom_10000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_rom_10000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rom_10000, reg_names, 0)
  #define DT_N_S_soc_S_rom_10000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rom_10000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_rom_10000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_rom_10000_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/serial@10013000
   *
   * Node identifier: DT_N_S_soc_S_serial_10013000
   *
   * Binding (compatible = sifive,uart0):
   *   $ZEPHYR_BASE/dts/bindings/serial/sifive,uart0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_serial_10013000_PATH "/soc/serial@10013000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_serial_10013000_FULL_NAME "serial@10013000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_serial_10013000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_serial_10013000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_serial_10013000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_serial_10013000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_serial_10013000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_serial_10013000_ORD 26
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_serial_10013000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_serial_10013000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_serial_10013000_EXISTS 1
  #define DT_N_INST_0_sifive_uart0 DT_N_S_soc_S_serial_10013000
  #define DT_N_NODELABEL_uart0     DT_N_S_soc_S_serial_10013000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_serial_10013000_REG_NUM 1
  #define DT_N_S_soc_S_serial_10013000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_REG_IDX_0_VAL_ADDRESS 268513280 /* 0x10013000 */
  #define DT_N_S_soc_S_serial_10013000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_serial_10013000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_serial_10013000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_serial_10013000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_serial_10013000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_serial_10013000_RANGES_NUM 0
  #define DT_N_S_soc_S_serial_10013000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_serial_10013000_IRQ_NUM 1
  #define DT_N_S_soc_S_serial_10013000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_IRQ_IDX_0_VAL_irq 1035
  #define DT_N_S_soc_S_serial_10013000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_serial_10013000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_COMPAT_MATCHES_sifive_uart0 1
  #define DT_N_S_soc_S_serial_10013000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_serial_10013000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_serial_10013000_P_reg {268513280 /* 0x10013000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_serial_10013000_P_reg_IDX_0 268513280
  #define DT_N_S_soc_S_serial_10013000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_serial_10013000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10013000, reg, 0) \
  	fn(DT_N_S_soc_S_serial_10013000, reg, 1)
  #define DT_N_S_soc_S_serial_10013000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10013000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10013000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_serial_10013000_P_interrupts_IDX_0 3
  #define DT_N_S_soc_S_serial_10013000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_serial_10013000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10013000, interrupts, 0) \
  	fn(DT_N_S_soc_S_serial_10013000, interrupts, 1)
  #define DT_N_S_soc_S_serial_10013000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10013000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10013000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_serial_10013000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_current_speed 115200
  #define DT_N_S_soc_S_serial_10013000_P_current_speed_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_label "uart_0"
  #define DT_N_S_soc_S_serial_10013000_P_label_STRING_TOKEN uart_0
  #define DT_N_S_soc_S_serial_10013000_P_label_STRING_UPPER_TOKEN UART_0
  #define DT_N_S_soc_S_serial_10013000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10013000, label, 0) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 1) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 2) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 3) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 4) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 5)
  #define DT_N_S_soc_S_serial_10013000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10013000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, label, 5, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10013000_P_label_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_hw_flow_control 0
  #define DT_N_S_soc_S_serial_10013000_P_hw_flow_control_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_status "okay"
  #define DT_N_S_soc_S_serial_10013000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_serial_10013000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_serial_10013000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_serial_10013000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_serial_10013000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_serial_10013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10013000, status, 0) \
  	fn(DT_N_S_soc_S_serial_10013000, status, 1) \
  	fn(DT_N_S_soc_S_serial_10013000, status, 2) \
  	fn(DT_N_S_soc_S_serial_10013000, status, 3)
  #define DT_N_S_soc_S_serial_10013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10013000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10013000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10013000_P_status_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_compatible {"sifive,uart0"}
  #define DT_N_S_soc_S_serial_10013000_P_compatible_IDX_0 "sifive,uart0"
  #define DT_N_S_soc_S_serial_10013000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10013000, compatible, 0)
  #define DT_N_S_soc_S_serial_10013000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10013000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10013000_P_compatible_LEN 1
  #define DT_N_S_soc_S_serial_10013000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_reg_names {"control"}
  #define DT_N_S_soc_S_serial_10013000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_serial_10013000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10013000, reg_names, 0)
  #define DT_N_S_soc_S_serial_10013000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10013000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10013000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_serial_10013000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_serial_10013000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_serial_10013000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_serial_10013000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_serial_10013000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_serial_10013000_P_wakeup_source 0
  #define DT_N_S_soc_S_serial_10013000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/serial@10023000
   *
   * Node identifier: DT_N_S_soc_S_serial_10023000
   *
   * Binding (compatible = sifive,uart0):
   *   $ZEPHYR_BASE/dts/bindings/serial/sifive,uart0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_serial_10023000_PATH "/soc/serial@10023000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_serial_10023000_FULL_NAME "serial@10023000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_serial_10023000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_serial_10023000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_serial_10023000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_serial_10023000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_serial_10023000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_serial_10023000_ORD 27
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_serial_10023000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_serial_10023000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_serial_10023000_EXISTS 1
  #define DT_N_INST_1_sifive_uart0 DT_N_S_soc_S_serial_10023000
  #define DT_N_NODELABEL_uart1     DT_N_S_soc_S_serial_10023000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_serial_10023000_REG_NUM 1
  #define DT_N_S_soc_S_serial_10023000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_REG_IDX_0_VAL_ADDRESS 268578816 /* 0x10023000 */
  #define DT_N_S_soc_S_serial_10023000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_serial_10023000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_serial_10023000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_serial_10023000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_serial_10023000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_serial_10023000_RANGES_NUM 0
  #define DT_N_S_soc_S_serial_10023000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_serial_10023000_IRQ_NUM 1
  #define DT_N_S_soc_S_serial_10023000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_IRQ_IDX_0_VAL_irq 1291
  #define DT_N_S_soc_S_serial_10023000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_serial_10023000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_COMPAT_MATCHES_sifive_uart0 1
  #define DT_N_S_soc_S_serial_10023000_STATUS_disabled 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_serial_10023000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_serial_10023000_P_reg {268578816 /* 0x10023000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_serial_10023000_P_reg_IDX_0 268578816
  #define DT_N_S_soc_S_serial_10023000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_serial_10023000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10023000, reg, 0) \
  	fn(DT_N_S_soc_S_serial_10023000, reg, 1)
  #define DT_N_S_soc_S_serial_10023000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10023000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10023000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_interrupts {4 /* 0x4 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_serial_10023000_P_interrupts_IDX_0 4
  #define DT_N_S_soc_S_serial_10023000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_serial_10023000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10023000, interrupts, 0) \
  	fn(DT_N_S_soc_S_serial_10023000, interrupts, 1)
  #define DT_N_S_soc_S_serial_10023000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10023000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10023000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_serial_10023000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_label "uart_1"
  #define DT_N_S_soc_S_serial_10023000_P_label_STRING_TOKEN uart_1
  #define DT_N_S_soc_S_serial_10023000_P_label_STRING_UPPER_TOKEN UART_1
  #define DT_N_S_soc_S_serial_10023000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10023000, label, 0) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 1) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 2) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 3) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 4) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 5)
  #define DT_N_S_soc_S_serial_10023000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10023000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, label, 5, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10023000_P_label_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_hw_flow_control 0
  #define DT_N_S_soc_S_serial_10023000_P_hw_flow_control_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_status "disabled"
  #define DT_N_S_soc_S_serial_10023000_P_status_STRING_TOKEN disabled
  #define DT_N_S_soc_S_serial_10023000_P_status_STRING_UPPER_TOKEN DISABLED
  #define DT_N_S_soc_S_serial_10023000_P_status_ENUM_IDX 2
  #define DT_N_S_soc_S_serial_10023000_P_status_ENUM_TOKEN disabled
  #define DT_N_S_soc_S_serial_10023000_P_status_ENUM_UPPER_TOKEN DISABLED
  #define DT_N_S_soc_S_serial_10023000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10023000, status, 0) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 1) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 2) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 3) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 4) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 5) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 6) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 7)
  #define DT_N_S_soc_S_serial_10023000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10023000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 5, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 6, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_serial_10023000, status, 7, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10023000_P_status_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_compatible {"sifive,uart0"}
  #define DT_N_S_soc_S_serial_10023000_P_compatible_IDX_0 "sifive,uart0"
  #define DT_N_S_soc_S_serial_10023000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10023000, compatible, 0)
  #define DT_N_S_soc_S_serial_10023000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10023000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10023000_P_compatible_LEN 1
  #define DT_N_S_soc_S_serial_10023000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_reg_names {"control"}
  #define DT_N_S_soc_S_serial_10023000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_serial_10023000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_10023000, reg_names, 0)
  #define DT_N_S_soc_S_serial_10023000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_10023000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_serial_10023000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_serial_10023000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_serial_10023000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_serial_10023000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_serial_10023000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_serial_10023000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_serial_10023000_P_wakeup_source 0
  #define DT_N_S_soc_S_serial_10023000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/spi@10024000
   *
   * Node identifier: DT_N_S_soc_S_spi_10024000
   *
   * Binding (compatible = sifive,spi0):
   *   $ZEPHYR_BASE/dts/bindings/spi/sifive,spi0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_spi_10024000_PATH "/soc/spi@10024000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_spi_10024000_FULL_NAME "spi@10024000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_spi_10024000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_spi_10024000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_spi_10024000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_spi_10024000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_spi_10024000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_spi_10024000_ORD 28
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_spi_10024000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_spi_10024000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_spi_10024000_EXISTS 1
  #define DT_N_INST_1_sifive_spi0 DT_N_S_soc_S_spi_10024000
  #define DT_N_NODELABEL_spi1     DT_N_S_soc_S_spi_10024000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_spi_10024000_REG_NUM 1
  #define DT_N_S_soc_S_spi_10024000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_REG_IDX_0_VAL_ADDRESS 268582912 /* 0x10024000 */
  #define DT_N_S_soc_S_spi_10024000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_spi_10024000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_spi_10024000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_spi_10024000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_spi_10024000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_spi_10024000_RANGES_NUM 0
  #define DT_N_S_soc_S_spi_10024000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_spi_10024000_IRQ_NUM 1
  #define DT_N_S_soc_S_spi_10024000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_IRQ_IDX_0_VAL_irq 1803
  #define DT_N_S_soc_S_spi_10024000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_spi_10024000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_COMPAT_MATCHES_sifive_spi0 1
  #define DT_N_S_soc_S_spi_10024000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_spi_10024000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_spi_10024000_P_reg {268582912 /* 0x10024000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_spi_10024000_P_reg_IDX_0 268582912
  #define DT_N_S_soc_S_spi_10024000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_spi_10024000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10024000, reg, 0) \
  	fn(DT_N_S_soc_S_spi_10024000, reg, 1)
  #define DT_N_S_soc_S_spi_10024000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10024000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10024000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_spi_10024000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_label "spi_1"
  #define DT_N_S_soc_S_spi_10024000_P_label_STRING_TOKEN spi_1
  #define DT_N_S_soc_S_spi_10024000_P_label_STRING_UPPER_TOKEN SPI_1
  #define DT_N_S_soc_S_spi_10024000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10024000, label, 0) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 1) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 2) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 3) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 4)
  #define DT_N_S_soc_S_spi_10024000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10024000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10024000_P_label_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_status "okay"
  #define DT_N_S_soc_S_spi_10024000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_spi_10024000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_spi_10024000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_spi_10024000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_spi_10024000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_spi_10024000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10024000, status, 0) \
  	fn(DT_N_S_soc_S_spi_10024000, status, 1) \
  	fn(DT_N_S_soc_S_spi_10024000, status, 2) \
  	fn(DT_N_S_soc_S_spi_10024000, status, 3)
  #define DT_N_S_soc_S_spi_10024000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10024000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10024000_P_status_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_compatible {"sifive,spi0"}
  #define DT_N_S_soc_S_spi_10024000_P_compatible_IDX_0 "sifive,spi0"
  #define DT_N_S_soc_S_spi_10024000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10024000, compatible, 0)
  #define DT_N_S_soc_S_spi_10024000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10024000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10024000_P_compatible_LEN 1
  #define DT_N_S_soc_S_spi_10024000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_reg_names {"control"}
  #define DT_N_S_soc_S_spi_10024000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_spi_10024000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10024000, reg_names, 0)
  #define DT_N_S_soc_S_spi_10024000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10024000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10024000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_spi_10024000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_interrupts {6 /* 0x6 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_spi_10024000_P_interrupts_IDX_0 6
  #define DT_N_S_soc_S_spi_10024000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_spi_10024000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10024000, interrupts, 0) \
  	fn(DT_N_S_soc_S_spi_10024000, interrupts, 1)
  #define DT_N_S_soc_S_spi_10024000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10024000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10024000, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10024000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10024000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10024000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10024000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_spi_10024000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_spi_10024000_P_wakeup_source 0
  #define DT_N_S_soc_S_spi_10024000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/spi@10034000
   *
   * Node identifier: DT_N_S_soc_S_spi_10034000
   *
   * Binding (compatible = sifive,spi0):
   *   $ZEPHYR_BASE/dts/bindings/spi/sifive,spi0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_spi_10034000_PATH "/soc/spi@10034000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_spi_10034000_FULL_NAME "spi@10034000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_spi_10034000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_spi_10034000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_spi_10034000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_spi_10034000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_spi_10034000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_spi_10034000_ORD 29
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_spi_10034000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_spi_10034000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_spi_10034000_EXISTS 1
  #define DT_N_INST_2_sifive_spi0 DT_N_S_soc_S_spi_10034000
  #define DT_N_NODELABEL_spi2     DT_N_S_soc_S_spi_10034000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_spi_10034000_REG_NUM 1
  #define DT_N_S_soc_S_spi_10034000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_REG_IDX_0_VAL_ADDRESS 268648448 /* 0x10034000 */
  #define DT_N_S_soc_S_spi_10034000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_spi_10034000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_spi_10034000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_spi_10034000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_spi_10034000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_spi_10034000_RANGES_NUM 0
  #define DT_N_S_soc_S_spi_10034000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_spi_10034000_IRQ_NUM 1
  #define DT_N_S_soc_S_spi_10034000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_IRQ_IDX_0_VAL_irq 2059
  #define DT_N_S_soc_S_spi_10034000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_spi_10034000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_COMPAT_MATCHES_sifive_spi0 1
  #define DT_N_S_soc_S_spi_10034000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_spi_10034000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_spi_10034000_P_reg {268648448 /* 0x10034000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_spi_10034000_P_reg_IDX_0 268648448
  #define DT_N_S_soc_S_spi_10034000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_spi_10034000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10034000, reg, 0) \
  	fn(DT_N_S_soc_S_spi_10034000, reg, 1)
  #define DT_N_S_soc_S_spi_10034000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10034000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10034000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_spi_10034000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_label "spi_2"
  #define DT_N_S_soc_S_spi_10034000_P_label_STRING_TOKEN spi_2
  #define DT_N_S_soc_S_spi_10034000_P_label_STRING_UPPER_TOKEN SPI_2
  #define DT_N_S_soc_S_spi_10034000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10034000, label, 0) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 1) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 2) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 3) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 4)
  #define DT_N_S_soc_S_spi_10034000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10034000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10034000_P_label_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_status "okay"
  #define DT_N_S_soc_S_spi_10034000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_spi_10034000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_spi_10034000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_spi_10034000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_spi_10034000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_spi_10034000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10034000, status, 0) \
  	fn(DT_N_S_soc_S_spi_10034000, status, 1) \
  	fn(DT_N_S_soc_S_spi_10034000, status, 2) \
  	fn(DT_N_S_soc_S_spi_10034000, status, 3)
  #define DT_N_S_soc_S_spi_10034000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10034000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10034000_P_status_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_compatible {"sifive,spi0"}
  #define DT_N_S_soc_S_spi_10034000_P_compatible_IDX_0 "sifive,spi0"
  #define DT_N_S_soc_S_spi_10034000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10034000, compatible, 0)
  #define DT_N_S_soc_S_spi_10034000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10034000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10034000_P_compatible_LEN 1
  #define DT_N_S_soc_S_spi_10034000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_reg_names {"control"}
  #define DT_N_S_soc_S_spi_10034000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_spi_10034000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10034000, reg_names, 0)
  #define DT_N_S_soc_S_spi_10034000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10034000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10034000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_spi_10034000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_interrupts {7 /* 0x7 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_spi_10034000_P_interrupts_IDX_0 7
  #define DT_N_S_soc_S_spi_10034000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_spi_10034000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10034000, interrupts, 0) \
  	fn(DT_N_S_soc_S_spi_10034000, interrupts, 1)
  #define DT_N_S_soc_S_spi_10034000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10034000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10034000, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10034000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10034000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10034000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10034000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_spi_10034000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_spi_10034000_P_wakeup_source 0
  #define DT_N_S_soc_S_spi_10034000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/teststatus@4000
   *
   * Node identifier: DT_N_S_soc_S_teststatus_4000
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_teststatus_4000_PATH "/soc/teststatus@4000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_teststatus_4000_FULL_NAME "teststatus@4000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_teststatus_4000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_teststatus_4000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_teststatus_4000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_teststatus_4000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_teststatus_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_teststatus_4000_ORD 30
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_teststatus_4000_REQUIRES_ORDS \
  	4, /* /soc */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_teststatus_4000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_teststatus_4000_EXISTS 1
  #define DT_N_INST_0_sifive_test0  DT_N_S_soc_S_teststatus_4000
  #define DT_N_NODELABEL_teststatus DT_N_S_soc_S_teststatus_4000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_teststatus_4000_REG_NUM 1
  #define DT_N_S_soc_S_teststatus_4000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_teststatus_4000_REG_IDX_0_VAL_ADDRESS 16384 /* 0x4000 */
  #define DT_N_S_soc_S_teststatus_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_teststatus_4000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_teststatus_4000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_teststatus_4000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_teststatus_4000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_teststatus_4000_RANGES_NUM 0
  #define DT_N_S_soc_S_teststatus_4000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_teststatus_4000_IRQ_NUM 0
  #define DT_N_S_soc_S_teststatus_4000_COMPAT_MATCHES_sifive_test0 1
  #define DT_N_S_soc_S_teststatus_4000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_teststatus_4000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_teststatus_4000_P_compatible {"sifive,test0"}
  #define DT_N_S_soc_S_teststatus_4000_P_compatible_IDX_0 "sifive,test0"
  #define DT_N_S_soc_S_teststatus_4000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_teststatus_4000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_teststatus_4000, compatible, 0)
  #define DT_N_S_soc_S_teststatus_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_teststatus_4000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_teststatus_4000_P_compatible_LEN 1
  #define DT_N_S_soc_S_teststatus_4000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_teststatus_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_teststatus_4000_P_reg_IDX_0 16384
  #define DT_N_S_soc_S_teststatus_4000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_teststatus_4000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_teststatus_4000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_teststatus_4000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_teststatus_4000, reg, 0) \
  	fn(DT_N_S_soc_S_teststatus_4000, reg, 1)
  #define DT_N_S_soc_S_teststatus_4000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_teststatus_4000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_teststatus_4000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_teststatus_4000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_teststatus_4000_P_reg_names {"control"}
  #define DT_N_S_soc_S_teststatus_4000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_teststatus_4000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_teststatus_4000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_teststatus_4000, reg_names, 0)
  #define DT_N_S_soc_S_teststatus_4000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_teststatus_4000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_teststatus_4000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_teststatus_4000_P_reg_names_EXISTS 1
  
  /*
   * Devicetree node: /soc/wdog@10000000
   *
   * Node identifier: DT_N_S_soc_S_wdog_10000000
   *
   * Binding (compatible = sifive,wdt):
   *   $ZEPHYR_BASE/dts/bindings/watchdog/sifive,wdt.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_wdog_10000000_PATH "/soc/wdog@10000000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_wdog_10000000_FULL_NAME "wdog@10000000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_wdog_10000000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_wdog_10000000_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_wdog_10000000_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_wdog_10000000_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_wdog_10000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_wdog_10000000_ORD 31
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_wdog_10000000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_wdog_10000000_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_wdog_10000000_EXISTS 1
  #define DT_N_INST_0_sifive_wdt DT_N_S_soc_S_wdog_10000000
  #define DT_N_NODELABEL_wdog0   DT_N_S_soc_S_wdog_10000000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_wdog_10000000_REG_NUM 1
  #define DT_N_S_soc_S_wdog_10000000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_REG_IDX_0_VAL_ADDRESS 268435456 /* 0x10000000 */
  #define DT_N_S_soc_S_wdog_10000000_REG_IDX_0_VAL_SIZE 64 /* 0x40 */
  #define DT_N_S_soc_S_wdog_10000000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_wdog_10000000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_wdog_10000000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_wdog_10000000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_wdog_10000000_RANGES_NUM 0
  #define DT_N_S_soc_S_wdog_10000000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_wdog_10000000_IRQ_NUM 1
  #define DT_N_S_soc_S_wdog_10000000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_IRQ_IDX_0_VAL_irq 523
  #define DT_N_S_soc_S_wdog_10000000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_wdog_10000000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_COMPAT_MATCHES_sifive_wdt 1
  #define DT_N_S_soc_S_wdog_10000000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_wdog_10000000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_wdog_10000000_P_reg {268435456 /* 0x10000000 */, 64 /* 0x40 */}
  #define DT_N_S_soc_S_wdog_10000000_P_reg_IDX_0 268435456
  #define DT_N_S_soc_S_wdog_10000000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_reg_IDX_1 64
  #define DT_N_S_soc_S_wdog_10000000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_wdog_10000000, reg, 0) \
  	fn(DT_N_S_soc_S_wdog_10000000, reg, 1)
  #define DT_N_S_soc_S_wdog_10000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_wdog_10000000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_wdog_10000000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_label "WDOG0"
  #define DT_N_S_soc_S_wdog_10000000_P_label_STRING_TOKEN WDOG0
  #define DT_N_S_soc_S_wdog_10000000_P_label_STRING_UPPER_TOKEN WDOG0
  #define DT_N_S_soc_S_wdog_10000000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_wdog_10000000, label, 0) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 1) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 2) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 3) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 4)
  #define DT_N_S_soc_S_wdog_10000000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_wdog_10000000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_wdog_10000000_P_label_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts {1 /* 0x1 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts_IDX_0 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_wdog_10000000, interrupts, 0) \
  	fn(DT_N_S_soc_S_wdog_10000000, interrupts, 1)
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_wdog_10000000, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_wdog_10000000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_compatible {"sifive,wdt"}
  #define DT_N_S_soc_S_wdog_10000000_P_compatible_IDX_0 "sifive,wdt"
  #define DT_N_S_soc_S_wdog_10000000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_wdog_10000000, compatible, 0)
  #define DT_N_S_soc_S_wdog_10000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_wdog_10000000_P_compatible_LEN 1
  #define DT_N_S_soc_S_wdog_10000000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_reg_names {"control"}
  #define DT_N_S_soc_S_wdog_10000000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_wdog_10000000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_wdog_10000000, reg_names, 0)
  #define DT_N_S_soc_S_wdog_10000000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_wdog_10000000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_wdog_10000000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_wdog_10000000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_wdog_10000000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_wdog_10000000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_wdog_10000000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_wdog_10000000_P_wakeup_source 0
  #define DT_N_S_soc_S_wdog_10000000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/gpio@10012000
   *
   * Node identifier: DT_N_S_soc_S_gpio_10012000
   *
   * Binding (compatible = sifive,gpio0):
   *   $ZEPHYR_BASE/dts/bindings/gpio/sifive,gpio0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_gpio_10012000_PATH "/soc/gpio@10012000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_gpio_10012000_FULL_NAME "gpio@10012000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_gpio_10012000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_gpio_10012000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038)
  #define DT_N_S_soc_S_gpio_10012000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038) 
  #define DT_N_S_soc_S_gpio_10012000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, __VA_ARGS__) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_gpio_10012000_ORD 32
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_gpio_10012000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_gpio_10012000_SUPPORTS_ORDS \
  	33, /* /soc/gpio@10012000/pinctrl@10012038 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_gpio_10012000_EXISTS 1
  #define DT_N_INST_0_sifive_gpio0 DT_N_S_soc_S_gpio_10012000
  #define DT_N_NODELABEL_gpio0     DT_N_S_soc_S_gpio_10012000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_gpio_10012000_REG_NUM 1
  #define DT_N_S_soc_S_gpio_10012000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_REG_IDX_0_VAL_ADDRESS 268509184 /* 0x10012000 */
  #define DT_N_S_soc_S_gpio_10012000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_gpio_10012000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_gpio_10012000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_gpio_10012000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_gpio_10012000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_gpio_10012000_RANGES_NUM 0
  #define DT_N_S_soc_S_gpio_10012000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_gpio_10012000_IRQ_NUM 32
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_0_VAL_irq 2315
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_1_VAL_irq 2571
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_1_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_1_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_1_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_2_VAL_irq 2827
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_2_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_2_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_2_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_3_VAL_irq 3083
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_3_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_3_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_3_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_4_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_4_VAL_irq 3339
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_4_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_4_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_4_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_4_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_5_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_5_VAL_irq 3595
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_5_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_5_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_5_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_5_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_6_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_6_VAL_irq 3851
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_6_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_6_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_6_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_6_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_7_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_7_VAL_irq 4107
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_7_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_7_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_7_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_7_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_8_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_8_VAL_irq 4363
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_8_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_8_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_8_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_8_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_9_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_9_VAL_irq 4619
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_9_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_9_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_9_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_9_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_10_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_10_VAL_irq 4875
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_10_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_10_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_10_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_10_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_11_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_11_VAL_irq 5131
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_11_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_11_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_11_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_11_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_12_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_12_VAL_irq 5387
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_12_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_12_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_12_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_12_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_13_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_13_VAL_irq 5643
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_13_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_13_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_13_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_13_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_14_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_14_VAL_irq 5899
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_14_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_14_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_14_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_14_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_15_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_15_VAL_irq 6155
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_15_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_15_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_15_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_15_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_16_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_16_VAL_irq 6411
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_16_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_16_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_16_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_16_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_17_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_17_VAL_irq 6667
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_17_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_17_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_17_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_17_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_18_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_18_VAL_irq 6923
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_18_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_18_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_18_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_18_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_19_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_19_VAL_irq 7179
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_19_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_19_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_19_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_19_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_20_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_20_VAL_irq 7435
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_20_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_20_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_20_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_20_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_21_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_21_VAL_irq 7691
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_21_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_21_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_21_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_21_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_22_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_22_VAL_irq 7947
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_22_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_22_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_22_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_22_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_23_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_23_VAL_irq 8203
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_23_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_23_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_23_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_23_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_24_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_24_VAL_irq 8459
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_24_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_24_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_24_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_24_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_25_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_25_VAL_irq 8715
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_25_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_25_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_25_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_25_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_26_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_26_VAL_irq 8971
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_26_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_26_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_26_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_26_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_27_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_27_VAL_irq 9227
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_27_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_27_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_27_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_27_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_28_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_28_VAL_irq 9483
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_28_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_28_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_28_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_28_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_29_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_29_VAL_irq 9739
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_29_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_29_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_29_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_29_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_30_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_30_VAL_irq 9995
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_30_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_30_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_30_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_30_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_31_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_31_VAL_irq 10251
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_31_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_31_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_31_VAL_priority 1
  #define DT_N_S_soc_S_gpio_10012000_IRQ_IDX_31_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_COMPAT_MATCHES_sifive_gpio0 1
  #define DT_N_S_soc_S_gpio_10012000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_gpio_10012000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_gpio_10012000_P_reg {268509184 /* 0x10012000 */, 4096 /* 0x1000 */}
  #define DT_N_S_soc_S_gpio_10012000_P_reg_IDX_0 268509184
  #define DT_N_S_soc_S_gpio_10012000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_gpio_10012000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000, reg, 0) \
  	fn(DT_N_S_soc_S_gpio_10012000, reg, 1)
  #define DT_N_S_soc_S_gpio_10012000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_label "gpio_0"
  #define DT_N_S_soc_S_gpio_10012000_P_label_STRING_TOKEN gpio_0
  #define DT_N_S_soc_S_gpio_10012000_P_label_STRING_UPPER_TOKEN GPIO_0
  #define DT_N_S_soc_S_gpio_10012000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000, label, 0) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 1) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 2) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 3) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 4) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 5)
  #define DT_N_S_soc_S_gpio_10012000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, label, 5, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_P_label_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */, 9 /* 0x9 */, 1 /* 0x1 */, 10 /* 0xa */, 1 /* 0x1 */, 11 /* 0xb */, 1 /* 0x1 */, 12 /* 0xc */, 1 /* 0x1 */, 13 /* 0xd */, 1 /* 0x1 */, 14 /* 0xe */, 1 /* 0x1 */, 15 /* 0xf */, 1 /* 0x1 */, 16 /* 0x10 */, 1 /* 0x1 */, 17 /* 0x11 */, 1 /* 0x1 */, 18 /* 0x12 */, 1 /* 0x1 */, 19 /* 0x13 */, 1 /* 0x1 */, 20 /* 0x14 */, 1 /* 0x1 */, 21 /* 0x15 */, 1 /* 0x1 */, 22 /* 0x16 */, 1 /* 0x1 */, 23 /* 0x17 */, 1 /* 0x1 */, 24 /* 0x18 */, 1 /* 0x1 */, 25 /* 0x19 */, 1 /* 0x1 */, 26 /* 0x1a */, 1 /* 0x1 */, 27 /* 0x1b */, 1 /* 0x1 */, 28 /* 0x1c */, 1 /* 0x1 */, 29 /* 0x1d */, 1 /* 0x1 */, 30 /* 0x1e */, 1 /* 0x1 */, 31 /* 0x1f */, 1 /* 0x1 */, 32 /* 0x20 */, 1 /* 0x1 */, 33 /* 0x21 */, 1 /* 0x1 */, 34 /* 0x22 */, 1 /* 0x1 */, 35 /* 0x23 */, 1 /* 0x1 */, 36 /* 0x24 */, 1 /* 0x1 */, 37 /* 0x25 */, 1 /* 0x1 */, 38 /* 0x26 */, 1 /* 0x1 */, 39 /* 0x27 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_0 8
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_2 9
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_3 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_4 10
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_4_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_5 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_5_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_6 11
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_6_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_7 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_7_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_8 12
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_8_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_9 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_9_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_10 13
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_10_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_11 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_11_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_12 14
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_12_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_13 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_13_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_14 15
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_14_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_15 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_15_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_16 16
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_16_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_17 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_17_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_18 17
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_18_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_19 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_19_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_20 18
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_20_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_21 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_21_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_22 19
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_22_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_23 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_23_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_24 20
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_24_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_25 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_25_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_26 21
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_26_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_27 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_27_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_28 22
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_28_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_29 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_29_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_30 23
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_30_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_31 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_31_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_32 24
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_32_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_33 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_33_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_34 25
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_34_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_35 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_35_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_36 26
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_36_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_37 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_37_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_38 27
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_38_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_39 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_39_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_40 28
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_40_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_41 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_41_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_42 29
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_42_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_43 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_43_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_44 30
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_44_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_45 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_45_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_46 31
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_46_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_47 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_47_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_48 32
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_48_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_49 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_49_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_50 33
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_50_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_51 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_51_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_52 34
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_52_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_53 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_53_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_54 35
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_54_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_55 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_55_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_56 36
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_56_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_57 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_57_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_58 37
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_58_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_59 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_59_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_60 38
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_60_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_61 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_61_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_62 39
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_62_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_63 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_IDX_63_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000, interrupts, 0) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 1) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 2) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 3) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 4) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 5) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 6) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 7) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 8) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 9) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 10) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 11) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 12) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 13) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 14) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 15) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 16) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 17) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 18) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 19) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 20) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 21) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 22) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 23) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 24) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 25) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 26) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 27) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 28) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 29) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 30) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 31) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 32) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 33) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 34) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 35) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 36) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 37) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 38) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 39) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 40) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 41) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 42) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 43) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 44) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 45) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 46) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 47) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 48) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 49) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 50) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 51) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 52) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 53) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 54) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 55) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 56) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 57) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 58) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 59) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 60) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 61) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 62) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 63)
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 5, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 6, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 7, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 8, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 9, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 10, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 11, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 12, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 13, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 14, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 15, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 16, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 17, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 18, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 19, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 20, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 21, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 22, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 23, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 24, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 25, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 26, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 27, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 28, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 29, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 30, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 31, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 32, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 33, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 34, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 35, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 36, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 37, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 38, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 39, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 40, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 41, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 42, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 43, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 44, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 45, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 46, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 47, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 48, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 49, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 50, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 51, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 52, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 53, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 54, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 55, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 56, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 57, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 58, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 59, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 60, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 61, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 62, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, interrupts, 63, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_gpio_controller 1
  #define DT_N_S_soc_S_gpio_10012000_P_gpio_controller_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_ngpios 32
  #define DT_N_S_soc_S_gpio_10012000_P_ngpios_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_status "okay"
  #define DT_N_S_soc_S_gpio_10012000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_gpio_10012000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_gpio_10012000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_gpio_10012000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_gpio_10012000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_gpio_10012000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000, status, 0) \
  	fn(DT_N_S_soc_S_gpio_10012000, status, 1) \
  	fn(DT_N_S_soc_S_gpio_10012000, status, 2) \
  	fn(DT_N_S_soc_S_gpio_10012000, status, 3)
  #define DT_N_S_soc_S_gpio_10012000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_P_status_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_compatible {"sifive,gpio0"}
  #define DT_N_S_soc_S_gpio_10012000_P_compatible_IDX_0 "sifive,gpio0"
  #define DT_N_S_soc_S_gpio_10012000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000, compatible, 0)
  #define DT_N_S_soc_S_gpio_10012000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_P_compatible_LEN 1
  #define DT_N_S_soc_S_gpio_10012000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_reg_names {"control"}
  #define DT_N_S_soc_S_gpio_10012000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_gpio_10012000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000, reg_names, 0)
  #define DT_N_S_soc_S_gpio_10012000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000, reg_names, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_P_reg_names_LEN 1
  #define DT_N_S_soc_S_gpio_10012000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_gpio_10012000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_gpio_10012000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_gpio_10012000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_gpio_10012000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_P_wakeup_source 0
  #define DT_N_S_soc_S_gpio_10012000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/gpio@10012000/pinctrl@10012038
   *
   * Node identifier: DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038
   *
   * Binding (compatible = sifive,iof):
   *   $ZEPHYR_BASE/dts/bindings/pinctrl/sifive,iof.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_PATH "/soc/gpio@10012000/pinctrl@10012038"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_FULL_NAME "pinctrl@10012038"
  
  /* Node parent (/soc/gpio@10012000) identifier: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_PARENT DT_N_S_soc_S_gpio_10012000
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_ORD 33
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_REQUIRES_ORDS \
  	32, /* /soc/gpio@10012000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_EXISTS 1
  #define DT_N_INST_0_sifive_iof DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038
  #define DT_N_NODELABEL_pinctrl DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_REG_NUM 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_REG_IDX_0_VAL_ADDRESS 268509240 /* 0x10012038 */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_REG_IDX_0_VAL_SIZE 8 /* 0x8 */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_RANGES_NUM 0
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_IRQ_NUM 0
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_COMPAT_MATCHES_sifive_iof 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg {268509240 /* 0x10012038 */, 8 /* 0x8 */}
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg_IDX_0 268509240
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg_IDX_1 8
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, reg, 0) \
  	fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, reg, 1)
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, reg, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_reg_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_compatible {"sifive,iof"}
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_compatible_IDX_0 "sifive,iof"
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, compatible, 0)
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_compatible_LEN 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_wakeup_source 0
  #define DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/spi@10014000
   *
   * Node identifier: DT_N_S_soc_S_spi_10014000
   *
   * Binding (compatible = sifive,spi0):
   *   $ZEPHYR_BASE/dts/bindings/spi/sifive,spi0.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_spi_10014000_PATH "/soc/spi@10014000"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_spi_10014000_FULL_NAME "spi@10014000"
  
  /* Node parent (/soc) identifier: */
  #define DT_N_S_soc_S_spi_10014000_PARENT DT_N_S_soc
  #define DT_N_S_soc_S_spi_10014000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0)
  #define DT_N_S_soc_S_spi_10014000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0) 
  #define DT_N_S_soc_S_spi_10014000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, __VA_ARGS__) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_spi_10014000_ORD 34
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_spi_10014000_REQUIRES_ORDS \
  	4, /* /soc */ \
  	8, /* /soc/interrupt-controller@c000000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_spi_10014000_SUPPORTS_ORDS \
  	35, /* /soc/spi@10014000/flash@0 */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_spi_10014000_EXISTS 1
  #define DT_N_INST_0_sifive_spi0 DT_N_S_soc_S_spi_10014000
  #define DT_N_NODELABEL_spi0     DT_N_S_soc_S_spi_10014000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_spi_10014000_REG_NUM 2
  #define DT_N_S_soc_S_spi_10014000_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_REG_IDX_0_VAL_ADDRESS 268517376 /* 0x10014000 */
  #define DT_N_S_soc_S_spi_10014000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
  #define DT_N_S_soc_S_spi_10014000_REG_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_REG_IDX_1_VAL_ADDRESS 541065216 /* 0x20400000 */
  #define DT_N_S_soc_S_spi_10014000_REG_IDX_1_VAL_SIZE 12582912 /* 0xc00000 */
  #define DT_N_S_soc_S_spi_10014000_REG_NAME_control_VAL_ADDRESS DT_N_S_soc_S_spi_10014000_REG_IDX_0_VAL_ADDRESS
  #define DT_N_S_soc_S_spi_10014000_REG_NAME_control_VAL_SIZE DT_N_S_soc_S_spi_10014000_REG_IDX_0_VAL_SIZE
  #define DT_N_S_soc_S_spi_10014000_REG_NAME_mem_VAL_ADDRESS DT_N_S_soc_S_spi_10014000_REG_IDX_1_VAL_ADDRESS
  #define DT_N_S_soc_S_spi_10014000_REG_NAME_mem_VAL_SIZE DT_N_S_soc_S_spi_10014000_REG_IDX_1_VAL_SIZE
  #define DT_N_S_soc_S_spi_10014000_RANGES_NUM 0
  #define DT_N_S_soc_S_spi_10014000_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_spi_10014000_IRQ_NUM 1
  #define DT_N_S_soc_S_spi_10014000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_IRQ_IDX_0_VAL_irq 1547
  #define DT_N_S_soc_S_spi_10014000_IRQ_IDX_0_VAL_irq_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_IRQ_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_IRQ_IDX_0_VAL_priority 1
  #define DT_N_S_soc_S_spi_10014000_IRQ_IDX_0_VAL_priority_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_COMPAT_MATCHES_sifive_spi0 1
  #define DT_N_S_soc_S_spi_10014000_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_spi_10014000_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_spi_10014000_P_reg {268517376 /* 0x10014000 */, 4096 /* 0x1000 */, 541065216 /* 0x20400000 */, 12582912 /* 0xc00000 */}
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_0 268517376
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_1 4096
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_2 541065216
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_3 12582912
  #define DT_N_S_soc_S_spi_10014000_P_reg_IDX_3_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000, reg, 0) \
  	fn(DT_N_S_soc_S_spi_10014000, reg, 1) \
  	fn(DT_N_S_soc_S_spi_10014000, reg, 2) \
  	fn(DT_N_S_soc_S_spi_10014000, reg, 3)
  #define DT_N_S_soc_S_spi_10014000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000, reg, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, reg, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, reg, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, reg, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_P_reg_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_clock_frequency 16000000
  #define DT_N_S_soc_S_spi_10014000_P_clock_frequency_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_label "spi_0"
  #define DT_N_S_soc_S_spi_10014000_P_label_STRING_TOKEN spi_0
  #define DT_N_S_soc_S_spi_10014000_P_label_STRING_UPPER_TOKEN SPI_0
  #define DT_N_S_soc_S_spi_10014000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000, label, 0) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 1) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 2) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 3) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 4)
  #define DT_N_S_soc_S_spi_10014000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, label, 4, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_P_label_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_status "okay"
  #define DT_N_S_soc_S_spi_10014000_P_status_STRING_TOKEN okay
  #define DT_N_S_soc_S_spi_10014000_P_status_STRING_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_spi_10014000_P_status_ENUM_IDX 1
  #define DT_N_S_soc_S_spi_10014000_P_status_ENUM_TOKEN okay
  #define DT_N_S_soc_S_spi_10014000_P_status_ENUM_UPPER_TOKEN OKAY
  #define DT_N_S_soc_S_spi_10014000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000, status, 0) \
  	fn(DT_N_S_soc_S_spi_10014000, status, 1) \
  	fn(DT_N_S_soc_S_spi_10014000, status, 2) \
  	fn(DT_N_S_soc_S_spi_10014000, status, 3)
  #define DT_N_S_soc_S_spi_10014000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000, status, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, status, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, status, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, status, 3, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_P_status_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_compatible {"sifive,spi0"}
  #define DT_N_S_soc_S_spi_10014000_P_compatible_IDX_0 "sifive,spi0"
  #define DT_N_S_soc_S_spi_10014000_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000, compatible, 0)
  #define DT_N_S_soc_S_spi_10014000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000, compatible, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_P_compatible_LEN 1
  #define DT_N_S_soc_S_spi_10014000_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_reg_names {"control", "mem"}
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_IDX_0 "control"
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_IDX_1 "mem"
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000, reg_names, 0) \
  	fn(DT_N_S_soc_S_spi_10014000, reg_names, 1)
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000, reg_names, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, reg_names, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_LEN 2
  #define DT_N_S_soc_S_spi_10014000_P_reg_names_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
  #define DT_N_S_soc_S_spi_10014000_P_interrupts_IDX_0 5
  #define DT_N_S_soc_S_spi_10014000_P_interrupts_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_interrupts_IDX_1 1
  #define DT_N_S_soc_S_spi_10014000_P_interrupts_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_interrupts_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000, interrupts, 0) \
  	fn(DT_N_S_soc_S_spi_10014000, interrupts, 1)
  #define DT_N_S_soc_S_spi_10014000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000, interrupts, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000, interrupts, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_P_interrupts_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10014000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10014000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_c000000
  #define DT_N_S_soc_S_spi_10014000_P_interrupt_parent_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_interrupt_parent_LEN 1
  #define DT_N_S_soc_S_spi_10014000_P_interrupt_parent_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_P_wakeup_source 0
  #define DT_N_S_soc_S_spi_10014000_P_wakeup_source_EXISTS 1
  
  /*
   * Devicetree node: /soc/spi@10014000/flash@0
   *
   * Node identifier: DT_N_S_soc_S_spi_10014000_S_flash_0
   *
   * Binding (compatible = jedec,spi-nor):
   *   $ZEPHYR_BASE/dts/bindings/mtd/jedec,spi-nor.yaml
   *
   * (Descriptions have moved to the Devicetree Bindings Index
   * in the documentation.)
   */
  
  /* Node's full path: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_PATH "/soc/spi@10014000/flash@0"
  
  /* Node's name with unit-address: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_FULL_NAME "flash@0"
  
  /* Node parent (/soc/spi@10014000) identifier: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_PARENT DT_N_S_soc_S_spi_10014000
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_FOREACH_CHILD(fn) 
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) 
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) 
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
  
  /* Node's dependency ordinal: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_ORD 35
  
  /* Ordinals for what this node depends on directly: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_REQUIRES_ORDS \
  	34, /* /soc/spi@10014000 */
  
  /* Ordinals for what depends directly on this node: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_SUPPORTS_ORDS /* nothing */
  
  /* Existence and alternate IDs: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_EXISTS 1
  #define DT_N_INST_0_issi_is25lp128 DT_N_S_soc_S_spi_10014000_S_flash_0
  #define DT_N_INST_0_jedec_spi_nor  DT_N_S_soc_S_spi_10014000_S_flash_0
  #define DT_N_NODELABEL_flash0      DT_N_S_soc_S_spi_10014000_S_flash_0
  
  /* Bus info (controller: '/soc/spi@10014000', type: 'spi') */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_BUS_spi 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_BUS DT_N_S_soc_S_spi_10014000
  
  /* Macros for properties that are special in the specification: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_REG_NUM 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_REG_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_RANGES_NUM 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_FOREACH_RANGE(fn) 
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_IRQ_NUM 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_COMPAT_MATCHES_issi_is25lp128 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_COMPAT_MATCHES_jedec_spi_nor 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_STATUS_okay 1
  
  /* Pin control (pinctrl-<i>, pinctrl-names) properties: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_PINCTRL_NUM 0
  
  /* Generic property macros: */
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_reg {0 /* 0x0 */}
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_reg_IDX_0 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_reg_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_reg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, reg, 0)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, reg, 0, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_reg_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_spi_max_frequency 133000000
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_spi_max_frequency_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_label "FLASH0"
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_label_STRING_TOKEN FLASH0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_label_STRING_UPPER_TOKEN FLASH0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 0) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 1) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 2) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 3) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 4) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 5)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 2, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 3, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 4, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, label, 5, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_label_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_frame_format 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_frame_format_ENUM_IDX 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_frame_format_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible {"issi,is25lp128", "jedec,spi-nor"}
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_IDX_0 "issi,is25lp128"
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_IDX_1 "jedec,spi-nor"
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, compatible, 0) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, compatible, 1)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, compatible, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, compatible, 1, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_LEN 2
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_compatible_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_wakeup_source 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_wakeup_source_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_requires_ulbpr 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_requires_ulbpr_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_has_dpd 0
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_has_dpd_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id {150 /* 0x96 */, 96 /* 0x60 */, 24 /* 0x18 */}
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_IDX_0 150
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_IDX_0_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_IDX_1 96
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_IDX_1_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_IDX_2 24
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_IDX_2_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, jedec_id, 0) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, jedec_id, 1) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, jedec_id, 2)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, jedec_id, 0, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, jedec_id, 1, __VA_ARGS__) \
  	fn(DT_N_S_soc_S_spi_10014000_S_flash_0, jedec_id, 2, __VA_ARGS__)
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_LEN 3
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_jedec_id_EXISTS 1
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_size 134217728
  #define DT_N_S_soc_S_spi_10014000_S_flash_0_P_size_EXISTS 1
  
  /*
   * Chosen nodes
   */
  #define DT_CHOSEN_zephyr_console           DT_N_S_soc_S_serial_10013000
  #define DT_CHOSEN_zephyr_console_EXISTS    1
  #define DT_CHOSEN_zephyr_shell_uart        DT_N_S_soc_S_serial_10013000
  #define DT_CHOSEN_zephyr_shell_uart_EXISTS 1
  #define DT_CHOSEN_zephyr_sram              DT_N_S_soc_S_dtim_80000000
  #define DT_CHOSEN_zephyr_sram_EXISTS       1
  #define DT_CHOSEN_zephyr_flash             DT_N_S_soc_S_spi_10014000_S_flash_0
  #define DT_CHOSEN_zephyr_flash_EXISTS      1
  
  /*
   * Macros for compatibles with status "okay" nodes
   */
  #define DT_COMPAT_HAS_OKAY_sifive_artya7 1
  #define DT_COMPAT_HAS_OKAY_sifive_rocket0 1
  #define DT_COMPAT_HAS_OKAY_riscv 1
  #define DT_COMPAT_HAS_OKAY_riscv_cpu_intc 1
  #define DT_COMPAT_HAS_OKAY_sifive_fe310g_0002_z0_soc 1
  #define DT_COMPAT_HAS_OKAY_fe310_soc 1
  #define DT_COMPAT_HAS_OKAY_sifive_soc 1
  #define DT_COMPAT_HAS_OKAY_simple_bus 1
  #define DT_COMPAT_HAS_OKAY_sifive_wdt 1
  #define DT_COMPAT_HAS_OKAY_sifive_aon0 1
  #define DT_COMPAT_HAS_OKAY_riscv_clint0 1
  #define DT_COMPAT_HAS_OKAY_sifive_debug_013 1
  #define DT_COMPAT_HAS_OKAY_riscv_debug_013 1
  #define DT_COMPAT_HAS_OKAY_sifive_dtim0 1
  #define DT_COMPAT_HAS_OKAY_sifive_error0 1
  #define DT_COMPAT_HAS_OKAY_sifive_gpio0 1
  #define DT_COMPAT_HAS_OKAY_sifive_iof 1
  #define DT_COMPAT_HAS_OKAY_sifive_plic_1_0_0 1
  #define DT_COMPAT_HAS_OKAY_sifive_itim0 1
  #define DT_COMPAT_HAS_OKAY_sifive_otp0 1
  #define DT_COMPAT_HAS_OKAY_sifive_freedome300prci0 1
  #define DT_COMPAT_HAS_OKAY_sifive_pwm0 1
  #define DT_COMPAT_HAS_OKAY_sifive_modeselect0 1
  #define DT_COMPAT_HAS_OKAY_sifive_maskrom0 1
  #define DT_COMPAT_HAS_OKAY_sifive_uart0 1
  #define DT_COMPAT_HAS_OKAY_sifive_spi0 1
  #define DT_COMPAT_HAS_OKAY_issi_is25lp128 1
  #define DT_COMPAT_HAS_OKAY_jedec_spi_nor 1
  #define DT_COMPAT_HAS_OKAY_sifive_test0 1
  #define DT_COMPAT_HAS_OKAY_pwm_leds 1
  
  /*
   * Macros for status "okay" instances of each compatible
   */
  #define DT_N_INST_sifive_artya7_NUM_OKAY 1
  #define DT_N_INST_sifive_rocket0_NUM_OKAY 1
  #define DT_N_INST_riscv_NUM_OKAY 1
  #define DT_N_INST_riscv_cpu_intc_NUM_OKAY 1
  #define DT_N_INST_sifive_fe310g_0002_z0_soc_NUM_OKAY 1
  #define DT_N_INST_fe310_soc_NUM_OKAY 1
  #define DT_N_INST_sifive_soc_NUM_OKAY 1
  #define DT_N_INST_simple_bus_NUM_OKAY 1
  #define DT_N_INST_sifive_wdt_NUM_OKAY 1
  #define DT_N_INST_sifive_aon0_NUM_OKAY 1
  #define DT_N_INST_riscv_clint0_NUM_OKAY 1
  #define DT_N_INST_sifive_debug_013_NUM_OKAY 1
  #define DT_N_INST_riscv_debug_013_NUM_OKAY 1
  #define DT_N_INST_sifive_dtim0_NUM_OKAY 1
  #define DT_N_INST_sifive_error0_NUM_OKAY 1
  #define DT_N_INST_sifive_gpio0_NUM_OKAY 1
  #define DT_N_INST_sifive_iof_NUM_OKAY 1
  #define DT_N_INST_sifive_plic_1_0_0_NUM_OKAY 1
  #define DT_N_INST_sifive_itim0_NUM_OKAY 1
  #define DT_N_INST_sifive_otp0_NUM_OKAY 1
  #define DT_N_INST_sifive_freedome300prci0_NUM_OKAY 1
  #define DT_N_INST_sifive_pwm0_NUM_OKAY 3
  #define DT_N_INST_sifive_modeselect0_NUM_OKAY 1
  #define DT_N_INST_sifive_maskrom0_NUM_OKAY 1
  #define DT_N_INST_sifive_uart0_NUM_OKAY 1
  #define DT_N_INST_sifive_spi0_NUM_OKAY 3
  #define DT_N_INST_issi_is25lp128_NUM_OKAY 1
  #define DT_N_INST_jedec_spi_nor_NUM_OKAY 1
  #define DT_N_INST_sifive_test0_NUM_OKAY 1
  #define DT_N_INST_pwm_leds_NUM_OKAY 1
  #define DT_FOREACH_OKAY_sifive_artya7(fn) fn(DT_N)
  #define DT_FOREACH_OKAY_VARGS_sifive_artya7(fn, ...) fn(DT_N, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_artya7(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_artya7(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_rocket0(fn) fn(DT_N_S_cpus_S_cpu_0)
  #define DT_FOREACH_OKAY_VARGS_sifive_rocket0(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_rocket0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_rocket0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_riscv(fn) fn(DT_N_S_cpus_S_cpu_0)
  #define DT_FOREACH_OKAY_VARGS_riscv(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_riscv(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_riscv(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_riscv_cpu_intc(fn) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller)
  #define DT_FOREACH_OKAY_VARGS_riscv_cpu_intc(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_interrupt_controller, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_riscv_cpu_intc(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_riscv_cpu_intc(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_fe310g_0002_z0_soc(fn) fn(DT_N_S_soc)
  #define DT_FOREACH_OKAY_VARGS_sifive_fe310g_0002_z0_soc(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_fe310g_0002_z0_soc(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_fe310g_0002_z0_soc(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_fe310_soc(fn) fn(DT_N_S_soc)
  #define DT_FOREACH_OKAY_VARGS_fe310_soc(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_fe310_soc(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_fe310_soc(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_soc(fn) fn(DT_N_S_soc)
  #define DT_FOREACH_OKAY_VARGS_sifive_soc(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_soc(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_soc(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc)
  #define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_wdt(fn) fn(DT_N_S_soc_S_wdog_10000000)
  #define DT_FOREACH_OKAY_VARGS_sifive_wdt(fn, ...) fn(DT_N_S_soc_S_wdog_10000000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_wdt(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_wdt(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_aon0(fn) fn(DT_N_S_soc_S_aon_10000040)
  #define DT_FOREACH_OKAY_VARGS_sifive_aon0(fn, ...) fn(DT_N_S_soc_S_aon_10000040, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_aon0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_aon0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_riscv_clint0(fn) fn(DT_N_S_soc_S_clint_2000000)
  #define DT_FOREACH_OKAY_VARGS_riscv_clint0(fn, ...) fn(DT_N_S_soc_S_clint_2000000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_riscv_clint0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_riscv_clint0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_debug_013(fn) fn(DT_N_S_soc_S_debug_controller_0)
  #define DT_FOREACH_OKAY_VARGS_sifive_debug_013(fn, ...) fn(DT_N_S_soc_S_debug_controller_0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_debug_013(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_debug_013(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_riscv_debug_013(fn) fn(DT_N_S_soc_S_debug_controller_0)
  #define DT_FOREACH_OKAY_VARGS_riscv_debug_013(fn, ...) fn(DT_N_S_soc_S_debug_controller_0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_riscv_debug_013(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_riscv_debug_013(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_dtim0(fn) fn(DT_N_S_soc_S_dtim_80000000)
  #define DT_FOREACH_OKAY_VARGS_sifive_dtim0(fn, ...) fn(DT_N_S_soc_S_dtim_80000000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_dtim0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_dtim0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_error0(fn) fn(DT_N_S_soc_S_error_device_3000)
  #define DT_FOREACH_OKAY_VARGS_sifive_error0(fn, ...) fn(DT_N_S_soc_S_error_device_3000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_error0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_error0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_gpio0(fn) fn(DT_N_S_soc_S_gpio_10012000)
  #define DT_FOREACH_OKAY_VARGS_sifive_gpio0(fn, ...) fn(DT_N_S_soc_S_gpio_10012000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_gpio0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_gpio0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_iof(fn) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038)
  #define DT_FOREACH_OKAY_VARGS_sifive_iof(fn, ...) fn(DT_N_S_soc_S_gpio_10012000_S_pinctrl_10012038, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_iof(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_iof(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_plic_1_0_0(fn) fn(DT_N_S_soc_S_interrupt_controller_c000000)
  #define DT_FOREACH_OKAY_VARGS_sifive_plic_1_0_0(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_c000000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_plic_1_0_0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_plic_1_0_0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_itim0(fn) fn(DT_N_S_soc_S_itim_8000000)
  #define DT_FOREACH_OKAY_VARGS_sifive_itim0(fn, ...) fn(DT_N_S_soc_S_itim_8000000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_itim0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_itim0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_otp0(fn) fn(DT_N_S_soc_S_otp_10010000)
  #define DT_FOREACH_OKAY_VARGS_sifive_otp0(fn, ...) fn(DT_N_S_soc_S_otp_10010000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_otp0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_otp0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_freedome300prci0(fn) fn(DT_N_S_soc_S_prci_10008000)
  #define DT_FOREACH_OKAY_VARGS_sifive_freedome300prci0(fn, ...) fn(DT_N_S_soc_S_prci_10008000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_freedome300prci0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_freedome300prci0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_pwm0(fn) fn(DT_N_S_soc_S_pwm_10015000) fn(DT_N_S_soc_S_pwm_10025000) fn(DT_N_S_soc_S_pwm_10035000)
  #define DT_FOREACH_OKAY_VARGS_sifive_pwm0(fn, ...) fn(DT_N_S_soc_S_pwm_10015000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10025000, __VA_ARGS__) fn(DT_N_S_soc_S_pwm_10035000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_pwm0(fn) fn(0) fn(1) fn(2)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_pwm0(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_modeselect0(fn) fn(DT_N_S_soc_S_rom_1000)
  #define DT_FOREACH_OKAY_VARGS_sifive_modeselect0(fn, ...) fn(DT_N_S_soc_S_rom_1000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_modeselect0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_modeselect0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_maskrom0(fn) fn(DT_N_S_soc_S_rom_10000)
  #define DT_FOREACH_OKAY_VARGS_sifive_maskrom0(fn, ...) fn(DT_N_S_soc_S_rom_10000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_maskrom0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_maskrom0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_uart0(fn) fn(DT_N_S_soc_S_serial_10013000)
  #define DT_FOREACH_OKAY_VARGS_sifive_uart0(fn, ...) fn(DT_N_S_soc_S_serial_10013000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_uart0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_uart0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_spi0(fn) fn(DT_N_S_soc_S_spi_10014000) fn(DT_N_S_soc_S_spi_10024000) fn(DT_N_S_soc_S_spi_10034000)
  #define DT_FOREACH_OKAY_VARGS_sifive_spi0(fn, ...) fn(DT_N_S_soc_S_spi_10014000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10024000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_10034000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_spi0(fn) fn(0) fn(1) fn(2)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_spi0(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
  #define DT_FOREACH_OKAY_issi_is25lp128(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0)
  #define DT_FOREACH_OKAY_VARGS_issi_is25lp128(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_issi_is25lp128(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_issi_is25lp128(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_jedec_spi_nor(fn) fn(DT_N_S_soc_S_spi_10014000_S_flash_0)
  #define DT_FOREACH_OKAY_VARGS_jedec_spi_nor(fn, ...) fn(DT_N_S_soc_S_spi_10014000_S_flash_0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_jedec_spi_nor(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_jedec_spi_nor(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_sifive_test0(fn) fn(DT_N_S_soc_S_teststatus_4000)
  #define DT_FOREACH_OKAY_VARGS_sifive_test0(fn, ...) fn(DT_N_S_soc_S_teststatus_4000, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_sifive_test0(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_sifive_test0(fn, ...) fn(0, __VA_ARGS__)
  #define DT_FOREACH_OKAY_pwm_leds(fn) fn(DT_N_S_leds)
  #define DT_FOREACH_OKAY_VARGS_pwm_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
  #define DT_FOREACH_OKAY_INST_pwm_leds(fn) fn(0)
  #define DT_FOREACH_OKAY_INST_VARGS_pwm_leds(fn, ...) fn(0, __VA_ARGS__)
  
  /*
   * Bus information for status "okay" nodes of each compatible
   */
  #define DT_COMPAT_issi_is25lp128_BUS_spi 1
  #define DT_COMPAT_jedec_spi_nor_BUS_spi 1
  