text: #!/usr/bin/env python3
  
  # This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
  # License: BSD
  
  import argparse
  import sys
  
  from migen import *
  from migen.genlib.resetsync import AsyncResetSynchronizer
  
  from litex_boards.platforms import camlink_4k
  
  from litex.build.lattice.trellis import trellis_args, trellis_argdict
  
  from litex.soc.cores.clock import *
  from litex.soc.integration.soc_core import *
  from litex.soc.integration.soc_sdram import *
  from litex.soc.integration.builder import *
  from litex.soc.cores.led import LedChaser
  
  from litedram.modules import MT41K64M16
  from litedram.phy import ECP5DDRPHY
  
  # CRG ----------------------------------------------------------------------------------------------
  
  class _CRG(Module):
      def __init__(self, platform, sys_clk_freq):
          self.clock_domains.cd_init    = ClockDomain()
          self.clock_domains.cd_por     = ClockDomain(reset_less=True)
          self.clock_domains.cd_sys     = ClockDomain()
          self.clock_domains.cd_sys2x   = ClockDomain()
          self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
  
          # # #
  
          self.stop = Signal()
  
          # clk / rst
          clk27 = platform.request("clk27")
  
          # power on reset
          por_count = Signal(16, reset=2**16-1)
          por_done  = Signal()
          self.comb += self.cd_por.clk.eq(ClockSignal())
          self.comb += por_done.eq(por_count == 0)
          self.sync.por += If(~por_done, por_count.eq(por_count - 1))
  
          # pll
          self.submodules.pll = pll = ECP5PLL()
          pll.register_clkin(clk27, 27e6)
          pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
          pll.create_clkout(self.cd_init, 27e6)
          self.specials += [
              Instance("ECLKSYNCB",
                  i_ECLKI = self.cd_sys2x_i.clk,
                  i_STOP  = self.stop,
                  o_ECLKO = self.cd_sys2x.clk),
              Instance("CLKDIVF",
                  p_DIV     = "2.0",
                  i_ALIGNWD = 0,
                  i_CLKI    = self.cd_sys2x.clk,
                  i_RST     = self.cd_sys2x.rst,
                  o_CDIVX   = self.cd_sys.clk),
              AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
              AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
          ]
  
  # BaseSoC ------------------------------------------------------------------------------------------
  
  class BaseSoC(SoCCore):
      def __init__(self, toolchain="trellis", **kwargs):
          platform     = camlink_4k.Platform(toolchain=toolchain)
          sys_clk_freq = int(81e6)
  
          # SoCCore ----------------------------------------------------------------------------------
          SoCCore.__init__(self, platform, sys_clk_freq,
              ident          = "LiteX SoC on Cam Link 4K",
              ident_version  = True,
              **kwargs)
  
          # CRG --------------------------------------------------------------------------------------
          self.submodules.crg = _CRG(platform, sys_clk_freq)
  
          # DDR3 SDRAM -------------------------------------------------------------------------------
          if not self.integrated_main_ram_size:
              self.submodules.ddrphy = ECP5DDRPHY(
                  platform.request("ddram"),
                  sys_clk_freq=sys_clk_freq)
              self.add_csr("ddrphy")
              self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
              self.add_sdram("sdram",
                  phy                     = self.ddrphy,
                  module                  = MT41K64M16(sys_clk_freq, "1:2"),
                  origin                  = self.mem_map["main_ram"],
                  size                    = kwargs.get("max_sdram_size", 0x40000000),
                  l2_cache_size           = kwargs.get("l2_size", 8192),
                  l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                  l2_cache_reverse        = True
              )
  
          # Leds -------------------------------------------------------------------------------------
          self.submodules.leds = LedChaser(
              pads         = Cat(*[platform.request("user_led", i) for i in range(2)]),
              sys_clk_freq = sys_clk_freq)
          self.add_csr("leds")
  
  # Build --------------------------------------------------------------------------------------------
  
  def main():
      parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
      parser.add_argument("--build", action="store_true", help="Build bitstream")
      parser.add_argument("--load",  action="store_true", help="Load bitstream")
      parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
      builder_args(parser)
      soc_sdram_args(parser)
      trellis_args(parser)
      args = parser.parse_args()
  
      soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args))
      builder = Builder(soc, **builder_argdict(args))
      builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
      builder.build(**builder_kargs, run=args.build)
  
      if args.load:
          prog = soc.platform.create_programmer()
          prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
  
  if __name__ == "__main__":
      main()
  