text: #pragma once 
  #include <Register/Utility.hpp>
  namespace Kvasir {
  //Advanced-timers
      namespace Tim8Cr1{    ///<control register 1
          using Addr = Register::Address<0x40010400,0xfffffc00,0x00000000,std::uint32_t>;
          ///Clock division
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> ckd{}; 
          ///Auto-reload preload enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> arpe{}; 
          ///Center-aligned mode              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,5),Register::ReadWriteAccess,unsigned> cms{}; 
          ///Direction
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(4,4),Register::ReadWriteAccess,unsigned> dir{}; 
          ///One-pulse mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> opm{}; 
          ///Update request source
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> urs{}; 
          ///Update disable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> udis{}; 
          ///Counter enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> cen{}; 
      }
      namespace Tim8Cr2{    ///<control register 2
          using Addr = Register::Address<0x40010404,0xffff8002,0x00000000,std::uint32_t>;
          ///Output Idle state 4
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(14,14),Register::ReadWriteAccess,unsigned> ois4{}; 
          ///Output Idle state 3
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(13,13),Register::ReadWriteAccess,unsigned> ois3n{}; 
          ///Output Idle state 3
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(12,12),Register::ReadWriteAccess,unsigned> ois3{}; 
          ///Output Idle state 2
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> ois2n{}; 
          ///Output Idle state 2
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> ois2{}; 
          ///Output Idle state 1
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,9),Register::ReadWriteAccess,unsigned> ois1n{}; 
          ///Output Idle state 1
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(8,8),Register::ReadWriteAccess,unsigned> ois1{}; 
          ///TI1 selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> ti1s{}; 
          ///Master mode selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,4),Register::ReadWriteAccess,unsigned> mms{}; 
          ///Capture/compare DMA              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> ccds{}; 
          ///Capture/compare control update              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> ccus{}; 
          ///Capture/compare preloaded              control
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> ccpc{}; 
      }
      namespace Tim8Smcr{    ///<slave mode control register
          using Addr = Register::Address<0x40010408,0xffff0008,0x00000000,std::uint32_t>;
          ///External trigger polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,15),Register::ReadWriteAccess,unsigned> etp{}; 
          ///External clock enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(14,14),Register::ReadWriteAccess,unsigned> ece{}; 
          ///External trigger prescaler
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(13,12),Register::ReadWriteAccess,unsigned> etps{}; 
          ///External trigger filter
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,8),Register::ReadWriteAccess,unsigned> etf{}; 
          ///Master/Slave mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> msm{}; 
          ///Trigger selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,4),Register::ReadWriteAccess,unsigned> ts{}; 
          ///Slave mode selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,0),Register::ReadWriteAccess,unsigned> sms{}; 
      }
      namespace Tim8Dier{    ///<DMA/Interrupt enable register
          using Addr = Register::Address<0x4001040c,0xffff8000,0x00000000,std::uint32_t>;
          ///Trigger DMA request enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(14,14),Register::ReadWriteAccess,unsigned> tde{}; 
          ///COM DMA request enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(13,13),Register::ReadWriteAccess,unsigned> comde{}; 
          ///Capture/Compare 4 DMA request              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(12,12),Register::ReadWriteAccess,unsigned> cc4de{}; 
          ///Capture/Compare 3 DMA request              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> cc3de{}; 
          ///Capture/Compare 2 DMA request              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> cc2de{}; 
          ///Capture/Compare 1 DMA request              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,9),Register::ReadWriteAccess,unsigned> cc1de{}; 
          ///Update DMA request enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(8,8),Register::ReadWriteAccess,unsigned> ude{}; 
          ///Trigger interrupt enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,6),Register::ReadWriteAccess,unsigned> tie{}; 
          ///Capture/Compare 4 interrupt              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(4,4),Register::ReadWriteAccess,unsigned> cc4ie{}; 
          ///Capture/Compare 3 interrupt              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> cc3ie{}; 
          ///Capture/Compare 2 interrupt              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> cc2ie{}; 
          ///Capture/Compare 1 interrupt              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1ie{}; 
          ///Update interrupt enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> uie{}; 
          ///Break interrupt enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> bie{}; 
          ///COM interrupt enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(5,5),Register::ReadWriteAccess,unsigned> comie{}; 
      }
      namespace Tim8Sr{    ///<status register
          using Addr = Register::Address<0x40010410,0xffffe100,0x00000000,std::uint32_t>;
          ///Capture/Compare 4 overcapture              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(12,12),Register::ReadWriteAccess,unsigned> cc4of{}; 
          ///Capture/Compare 3 overcapture              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> cc3of{}; 
          ///Capture/compare 2 overcapture              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> cc2of{}; 
          ///Capture/Compare 1 overcapture              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,9),Register::ReadWriteAccess,unsigned> cc1of{}; 
          ///Break interrupt flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> bif{}; 
          ///Trigger interrupt flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,6),Register::ReadWriteAccess,unsigned> tif{}; 
          ///COM interrupt flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(5,5),Register::ReadWriteAccess,unsigned> comif{}; 
          ///Capture/Compare 4 interrupt              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(4,4),Register::ReadWriteAccess,unsigned> cc4if{}; 
          ///Capture/Compare 3 interrupt              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> cc3if{}; 
          ///Capture/Compare 2 interrupt              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> cc2if{}; 
          ///Capture/compare 1 interrupt              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1if{}; 
          ///Update interrupt flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> uif{}; 
      }
      namespace Tim8Egr{    ///<event generation register
          using Addr = Register::Address<0x40010414,0xffffff00,0x00000000,std::uint32_t>;
          ///Break generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> bg{}; 
          ///Trigger generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,6),Register::ReadWriteAccess,unsigned> tg{}; 
          ///Capture/Compare control update              generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(5,5),Register::ReadWriteAccess,unsigned> comg{}; 
          ///Capture/compare 4              generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(4,4),Register::ReadWriteAccess,unsigned> cc4g{}; 
          ///Capture/compare 3              generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> cc3g{}; 
          ///Capture/compare 2              generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> cc2g{}; 
          ///Capture/compare 1              generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1g{}; 
          ///Update generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> ug{}; 
      }
      namespace Tim8Ccmr1Output{    ///<capture/compare mode register 1 (output          mode)
          using Addr = Register::Address<0x40010418,0xffff0000,0x00000000,std::uint32_t>;
          ///Output Compare 2 clear              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,15),Register::ReadWriteAccess,unsigned> oc2ce{}; 
          ///Output Compare 2 mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(14,12),Register::ReadWriteAccess,unsigned> oc2m{}; 
          ///Output Compare 2 preload              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> oc2pe{}; 
          ///Output Compare 2 fast              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> oc2fe{}; 
          ///Capture/Compare 2              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> cc2s{}; 
          ///Output Compare 1 clear              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> oc1ce{}; 
          ///Output Compare 1 mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,4),Register::ReadWriteAccess,unsigned> oc1m{}; 
          ///Output Compare 1 preload              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> oc1pe{}; 
          ///Output Compare 1 fast              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> oc1fe{}; 
          ///Capture/Compare 1              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,0),Register::ReadWriteAccess,unsigned> cc1s{}; 
      }
      namespace Tim8Ccmr1Input{    ///<capture/compare mode register 1 (input          mode)
          using Addr = Register::Address<0x40010418,0xffff0000,0x00000000,std::uint32_t>;
          ///Input capture 2 filter
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,12),Register::ReadWriteAccess,unsigned> ic2f{}; 
          ///Input capture 2 prescaler
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,10),Register::ReadWriteAccess,unsigned> ic2pcs{}; 
          ///Capture/Compare 2              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> cc2s{}; 
          ///Input capture 1 filter
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,4),Register::ReadWriteAccess,unsigned> ic1f{}; 
          ///Input capture 1 prescaler
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,2),Register::ReadWriteAccess,unsigned> icpcs{}; 
          ///Capture/Compare 1              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,0),Register::ReadWriteAccess,unsigned> cc1s{}; 
      }
      namespace Tim8Ccmr2Output{    ///<capture/compare mode register 2 (output          mode)
          using Addr = Register::Address<0x4001041c,0xffff0000,0x00000000,std::uint32_t>;
          ///Output compare 4 clear              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,15),Register::ReadWriteAccess,unsigned> oc4ce{}; 
          ///Output compare 4 mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(14,12),Register::ReadWriteAccess,unsigned> oc4m{}; 
          ///Output compare 4 preload              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> oc4pe{}; 
          ///Output compare 4 fast              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> oc4fe{}; 
          ///Capture/Compare 4              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> cc4s{}; 
          ///Output compare 3 clear              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> oc3ce{}; 
          ///Output compare 3 mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,4),Register::ReadWriteAccess,unsigned> oc3m{}; 
          ///Output compare 3 preload              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> oc3pe{}; 
          ///Output compare 3 fast              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> oc3fe{}; 
          ///Capture/Compare 3              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,0),Register::ReadWriteAccess,unsigned> cc3s{}; 
      }
      namespace Tim8Ccmr2Input{    ///<capture/compare mode register 2 (input          mode)
          using Addr = Register::Address<0x4001041c,0xffff0000,0x00000000,std::uint32_t>;
          ///Input capture 4 filter
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,12),Register::ReadWriteAccess,unsigned> ic4f{}; 
          ///Input capture 4 prescaler
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,10),Register::ReadWriteAccess,unsigned> ic4psc{}; 
          ///Capture/Compare 4              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> cc4s{}; 
          ///Input capture 3 filter
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,4),Register::ReadWriteAccess,unsigned> ic3f{}; 
          ///Input capture 3 prescaler
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,2),Register::ReadWriteAccess,unsigned> ic3psc{}; 
          ///Capture/compare 3              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,0),Register::ReadWriteAccess,unsigned> cc3s{}; 
      }
      namespace Tim8Ccer{    ///<capture/compare enable          register
          using Addr = Register::Address<0x40010420,0xffffc000,0x00000000,std::uint32_t>;
          ///Capture/Compare 3 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(13,13),Register::ReadWriteAccess,unsigned> cc4p{}; 
          ///Capture/Compare 4 output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(12,12),Register::ReadWriteAccess,unsigned> cc4e{}; 
          ///Capture/Compare 3 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> cc3np{}; 
          ///Capture/Compare 3 complementary output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> cc3ne{}; 
          ///Capture/Compare 3 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,9),Register::ReadWriteAccess,unsigned> cc3p{}; 
          ///Capture/Compare 3 output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(8,8),Register::ReadWriteAccess,unsigned> cc3e{}; 
          ///Capture/Compare 2 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> cc2np{}; 
          ///Capture/Compare 2 complementary output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,6),Register::ReadWriteAccess,unsigned> cc2ne{}; 
          ///Capture/Compare 2 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(5,5),Register::ReadWriteAccess,unsigned> cc2p{}; 
          ///Capture/Compare 2 output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(4,4),Register::ReadWriteAccess,unsigned> cc2e{}; 
          ///Capture/Compare 1 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> cc1np{}; 
          ///Capture/Compare 1 complementary output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> cc1ne{}; 
          ///Capture/Compare 1 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1p{}; 
          ///Capture/Compare 1 output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> cc1e{}; 
      }
      namespace Tim8Cnt{    ///<counter
          using Addr = Register::Address<0x40010424,0xffff0000,0x00000000,std::uint32_t>;
          ///counter value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> cnt{}; 
      }
      namespace Tim8Psc{    ///<prescaler
          using Addr = Register::Address<0x40010428,0xffff0000,0x00000000,std::uint32_t>;
          ///Prescaler value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> psc{}; 
      }
      namespace Tim8Arr{    ///<auto-reload register
          using Addr = Register::Address<0x4001042c,0xffff0000,0x00000000,std::uint32_t>;
          ///Auto-reload value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> arr{}; 
      }
      namespace Tim8Ccr1{    ///<capture/compare register 1
          using Addr = Register::Address<0x40010434,0xffff0000,0x00000000,std::uint32_t>;
          ///Capture/Compare 1 value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> ccr1{}; 
      }
      namespace Tim8Ccr2{    ///<capture/compare register 2
          using Addr = Register::Address<0x40010438,0xffff0000,0x00000000,std::uint32_t>;
          ///Capture/Compare 2 value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> ccr2{}; 
      }
      namespace Tim8Ccr3{    ///<capture/compare register 3
          using Addr = Register::Address<0x4001043c,0xffff0000,0x00000000,std::uint32_t>;
          ///Capture/Compare value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> ccr3{}; 
      }
      namespace Tim8Ccr4{    ///<capture/compare register 4
          using Addr = Register::Address<0x40010440,0xffff0000,0x00000000,std::uint32_t>;
          ///Capture/Compare value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> ccr4{}; 
      }
      namespace Tim8Dcr{    ///<DMA control register
          using Addr = Register::Address<0x40010448,0xffffe0e0,0x00000000,std::uint32_t>;
          ///DMA burst length
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(12,8),Register::ReadWriteAccess,unsigned> dbl{}; 
          ///DMA base address
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(4,0),Register::ReadWriteAccess,unsigned> dba{}; 
      }
      namespace Tim8Dmar{    ///<DMA address for full transfer
          using Addr = Register::Address<0x4001044c,0xffff0000,0x00000000,std::uint32_t>;
          ///DMA register for burst              accesses
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> dmab{}; 
      }
      namespace Tim8Rcr{    ///<repetition counter register
          using Addr = Register::Address<0x40010430,0xffffff00,0x00000000,std::uint32_t>;
          ///Repetition counter value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,0),Register::ReadWriteAccess,unsigned> rep{}; 
      }
      namespace Tim8Bdtr{    ///<break and dead-time register
          using Addr = Register::Address<0x40010444,0xffff0000,0x00000000,std::uint32_t>;
          ///Main output enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,15),Register::ReadWriteAccess,unsigned> moe{}; 
          ///Automatic output enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(14,14),Register::ReadWriteAccess,unsigned> aoe{}; 
          ///Break polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(13,13),Register::ReadWriteAccess,unsigned> bkp{}; 
          ///Break enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(12,12),Register::ReadWriteAccess,unsigned> bke{}; 
          ///Off-state selection for Run              mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> ossr{}; 
          ///Off-state selection for Idle              mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> ossi{}; 
          ///Lock configuration
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> lock{}; 
          ///Dead-time generator setup
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,0),Register::ReadWriteAccess,unsigned> dtg{}; 
      }
  }
  