text: // Copyright (c) 2004-2020 Microchip Technology Inc. and its subsidiaries.
  // SPDX-License-Identifier: MIT
  
  #ifndef _VTSS_MALIBU_B_HOST_PMA__API_SD10G65_UTE
  #define _VTSS_MALIBU_B_HOST_PMA__API_SD10G65_UTE
  
  
  /* Generation Tag is  UTE_release_vts_ute_tcllib_20180312_trunk_bjo */
  
  /* ================================================================= *
   *               Note: This code is autogenerated from the
   *                     Universal Tcl Environment (UTE) which provides
   *                     consistent setup functions for
   *       ^             - Verification
   *      / \            - Validation
   *     /   \           - Test Pattern Generation and
   *    /  |  \          - Software
   *   /   !   \         It should not be modified manually.
   *  /_________\        In case there is a need for modifications,
   *                     please contact
   *                       Patrick Urban <patrick.urban@microsemi.com> or
   *                       Alexander Koch <alexander.koch@microsemi.com> or
   *                       Mark Venneboerger <mark.venneboerger@microsemi.com>
   *                     Please use Bugzilla for reporting issues or requesting enhancements:
   *                     Bugzilla: Tools->Victoria
   *                     http://projissuetracker/bugzilla/enter_bug.cgi?product=Victoria
   * ================================================================= */
  
  #include <vtss/api/options.h>  // To get the ARCH define
  #if defined(VTSS_ARCH_MALIBU_B)
  #include "vtss_malibu_b_inc.h"
  
  
  static vtss_rc malibu_b_host_pma_sd10g_tx_register_cfg(vtss_state_t *vtss_state, const vtss_sd10g65_setup_tx_struct_t *const res_struct, vtss_port_no_t port_no) {
      u32 value;
  
  
  
      vtss_rc rc = VTSS_RC_OK;
      if( res_struct->pwrcycle[0] == 1 ) {
      if (res_struct->tx_synth_cfg0__synth_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      if (res_struct->tx_rcpll_cfg2__pll_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->ob_cfg0__en_ob[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB);
      }
  
      VTSS_MSLEEP(1);
  
      } 
  
      if (res_struct->sbus_tx_cfg__sbus_bias_en[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_EN,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_EN);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_EN);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_SPEED_SEL(res_struct->sbus_tx_cfg__sbus_bias_speed_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_SPEED_SEL);
  
      if (res_struct->sbus_rx_cfg__sbus_bias_en[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_SPEED_SEL(res_struct->sbus_rx_cfg__sbus_bias_speed_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_SPEED_SEL);
  
      if (res_struct->ob_cfg0__en_ob[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB);
      }
  
      if (res_struct->tx_rcpll_cfg2__pll_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_SPARE_POOL(res_struct->tx_synth_cfg0__synth_spare_pool[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_SPARE_POOL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_OFF_COMP_ENA(res_struct->tx_synth_cfg0__synth_off_comp_ena[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_OFF_COMP_ENA);
  
      if (res_struct->tx_synth_cfg0__synth_speed_sel[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_SPEED_SEL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_SPEED_SEL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_SPEED_SEL);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_FBDIV_SEL(res_struct->tx_synth_cfg0__synth_fbdiv_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_FBDIV_SEL);
  
      CSR_WARM_WR(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG3,
          res_struct->tx_synth_cfg3__synth_freqm_0[0]);
  
      CSR_WARM_WR(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG4,
          res_struct->tx_synth_cfg4__synth_freqn_0[0]);
  
      if (res_struct->tx_synth_cfg1__synth_freq_mult_byp[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQ_MULT_BYP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQ_MULT_BYP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQ_MULT_BYP);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQ_MULT_HI(res_struct->tx_synth_cfg1__synth_freq_mult_hi[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQ_MULT_HI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQ_MULT(res_struct->tx_synth_cfg1__synth_freq_mult[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQ_MULT);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQM_1(res_struct->tx_synth_cfg1__synth_freqm_1[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQM_1);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQN_1(res_struct->tx_synth_cfg1__synth_freqn_1[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG1_SYNTH_FREQN_1);
  
      if (res_struct->tx_synth_cfg0__synth_ls_speed[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_SPEED,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_SPEED);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_SPEED);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_CS_SPEED(res_struct->tx_synth_cfg0__synth_cs_speed[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_CS_SPEED);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ena_sync_unit[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA_SYNC_UNIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA_SYNC_UNIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA_SYNC_UNIT);
      }
  
      if (res_struct->tx_synth_cfg0__synth_conv_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_CONV_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_CONV_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_CONV_ENA);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ds_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_ENA);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ds_dir[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_DIR,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_DIR);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_DIR);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ds_speed[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_SPEED,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_SPEED);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_DS_SPEED);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ls_dir[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_DIR,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_DIR);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_DIR);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ls_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_LS_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_SSC_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_SSC_CFG1_SYNC_CTRL_FSEL(res_struct->ssc_cfg1__sync_ctrl_fsel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_SSC_CFG1_SYNC_CTRL_FSEL);
  
      if (res_struct->ob_cfg0__en_inp_loop[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_INP_LOOP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_INP_LOOP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_INP_LOOP);
      }
  
      if (res_struct->ob_cfg0__en_pad_loop[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_PAD_LOOP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_PAD_LOOP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_PAD_LOOP);
      }
  
      if (res_struct->ob_cfg0__ser_inv[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SER_INV,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SER_INV);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SER_INV);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW(res_struct->ob_cfg0__sel_ifw[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW);
  
      if (res_struct->ob_cfg0__incr_levn[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_INCR_LEVN,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_INCR_LEVN);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_INCR_LEVN);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_LEVN(res_struct->ob_cfg0__levn[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_LEVN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1_LEV_SHFT(res_struct->ob_cfg1__lev_shft[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1_LEV_SHFT);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1_PREDRV_R_CTRL(res_struct->ob_cfg1__predrv_r_ctrl[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1_PREDRV_R_CTRL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1_PREDRV_C_CTRL(res_struct->ob_cfg1__predrv_c_ctrl[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG1_PREDRV_C_CTRL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG2_D_FILTER(res_struct->ob_cfg2__d_filter[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG2_D_FILTER);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_VCO_CUR(res_struct->tx_rcpll_cfg2__pll_vco_cur[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_VCO_CUR);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_VREG18(res_struct->tx_rcpll_cfg2__pll_vreg18[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_VREG18);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_LPF_CUR(res_struct->tx_rcpll_cfg2__pll_lpf_cur[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_LPF_CUR);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_LPF_RES(res_struct->tx_rcpll_cfg2__pll_lpf_res[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_LPF_RES);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_START_CNT(res_struct->tx_rcpll_cfg0__pllf_start_cnt[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_START_CNT);
  
      if (res_struct->tx_rcpll_cfg0__pllf_syn_clk_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_SYN_CLK_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_SYN_CLK_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_SYN_CLK_ENA);
      }
  
      if (res_struct->tx_rcpll_cfg0__pllf_loop_ctrl_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_LOOP_CTRL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_LOOP_CTRL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_LOOP_CTRL_ENA);
      }
  
      if (res_struct->tx_rcpll_cfg0__pllf_loop_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_LOOP_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_LOOP_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_LOOP_ENA);
      }
  
      if (res_struct->tx_rcpll_cfg0__pllf_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG1_PLLF_REF_CNT_END(res_struct->tx_rcpll_cfg1__pllf_ref_cnt_end[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG1_PLLF_REF_CNT_END);
  
      if (res_struct->tx_rcpll_cfg0__pllf_oor_recal_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      }
  
      if(res_struct->chip_needs_hrate_toggle[0] == 1) {
      VTSS_MSLEEP(10);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW(res_struct->ob_cfg0__sel_ifw[1]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[2]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[3]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[4]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[5]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW(res_struct->ob_cfg0__sel_ifw[2]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[6]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[7]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[8]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->tx_synth_cfg0__synth_hrate_ena[9]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW(res_struct->ob_cfg0__sel_ifw[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_SEL_IFW);
  
      VTSS_MSLEEP(50);
  
      }  else {
      VTSS_MSLEEP(10);
  
  } 
      if (res_struct->tx_rcpll_cfg0__pllf_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_ENA);
      }
  
      if (res_struct->tx_rcpll_cfg0__pllf_oor_recal_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      CSR_RD(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_STAT0, &value);
      value &= VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_STAT0_PLLF_LOCK_STAT;
      value = (value > 0) ? 1 : 0;
      if(value != 0x1) {
          VTSS_E("The expected value for sd10g65_tx_rcpll_stat0 pllf_lock_stat was 0x1 but is 0x%x\n", value);
          rc = VTSS_RC_ERROR;
      } else {
          VTSS_D("Note: The value of sd10g65_tx_rcpll_stat0 pllf_lock_stat was 0x%x\n", value);
      }
  
      CSR_RD(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_STAT1, &value);
      value = VTSS_X_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_STAT1_PLLF_FSM_STAT(value);
      if(value != 0xd) {
          VTSS_E("The expected value for sd10g65_tx_rcpll_stat1 pllf_fsm_stat was 0xd but is 0x%x\n", value);
          rc = VTSS_RC_ERROR;
      } else {
          VTSS_D("Note: The value of sd10g65_tx_rcpll_stat1 pllf_fsm_stat was 0x%x\n", value);
      }
  
  
    return rc;
  }
  
  
  vtss_rc vtss_malibu_b_host_pma_sd10g_setup_tx(vtss_state_t *vtss_state, const vtss_sd10g65_setup_tx_args_t config, vtss_port_no_t port_no) {
      vtss_sd10g65_setup_tx_struct_t calc_results;
      vtss_rc ret_val;
      VTSS_D("This function is generated with UTE based on TAG:  UTE_release_vts_ute_tcllib_20180312_trunk_bjo");
      ret_val = vtss_calc_sd10g65_setup_tx(config, &calc_results);
      if(ret_val == VTSS_RC_OK) {
          ret_val |= malibu_b_host_pma_sd10g_tx_register_cfg(vtss_state, &calc_results, port_no);
      }
      return ret_val;
  }
  static vtss_rc malibu_b_host_pma_sd10g_rx_register_cfg(vtss_state_t *vtss_state, const vtss_sd10g65_setup_rx_struct_t *const res_struct, vtss_port_no_t port_no) {
      u32 value;
  
  
  
      vtss_rc rc = VTSS_RC_OK;
      if( res_struct->pwrcycle[0] == 1 ) {
      if (res_struct->rx_synth_cfg0__synth_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      if (res_struct->rx_rcpll_cfg2__pll_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->ib_cfg8__ib_bias_mode[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE);
      }
  
      if (res_struct->ib_cfg0__ib_dfe_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_ia_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_ld_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_clkdiv_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_eqz_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_sam_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA);
      }
  
      VTSS_MSLEEP(1);
  
      } 
  
      if( res_struct->sbus_special_handling[0] == 1 ) {
      } 
  
      if (res_struct->sbus_rx_cfg__sbus_loopdrv_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_LOOPDRV_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_LOOPDRV_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_LOOPDRV_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_SPARE_POOL(res_struct->sbus_rx_cfg__sbus_spare_pool[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_SPARE_POOL);
  
      if (res_struct->sbus_rx_cfg__sbus_bias_en[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_SPEED_SEL(res_struct->sbus_rx_cfg__sbus_bias_speed_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_SPEED_SEL);
  
      if( res_struct->sbus_special_handling[0] == 1 ) {
      } 
  
      if (res_struct->rx_rcpll_cfg2__pll_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->rx_synth_cfg0__synth_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      if (res_struct->rx_synth_cfg2__synth_aux_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_AUX_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_AUX_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_AUX_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_clkdiv_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_vbulk_sel[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_VBULK_SEL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_VBULK_SEL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_VBULK_SEL);
      }
  
      if (res_struct->ib_cfg0__ib_sam_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA);
      }
  
      if (res_struct->ib_cfg8__ib_bias_mode[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_CML_CURR(res_struct->ib_cfg8__ib_cml_curr[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_CML_CURR);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_ADJ(res_struct->ib_cfg8__ib_bias_adj[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_ADJ);
  
      if(res_struct->chip_needs_hrate_toggle[0] == 1) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL(res_struct->des_cfg0__des_if_mode_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL);
  
      if (res_struct->des_cfg0__des_dis[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      if (res_struct->des_cfg0__des_dis[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      if (res_struct->des_cfg0__des_dis[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      if (res_struct->des_cfg0__des_dis[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      if (res_struct->des_cfg0__des_dis[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      if (res_struct->des_cfg0__des_dis[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      if (res_struct->des_cfg0__des_dis[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      if (res_struct->des_cfg0__des_dis[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_DIS);
      }
  
      } 
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_SPARE_POOL(res_struct->rx_synth_cfg0__synth_spare_pool[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_SPARE_POOL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_OFF_COMP_ENA(res_struct->rx_synth_cfg0__synth_off_comp_ena[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_OFF_COMP_ENA);
  
      if (res_struct->rx_synth_cfg0__synth_speed_sel[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_SPEED_SEL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_SPEED_SEL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_SPEED_SEL);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_FBDIV_SEL(res_struct->rx_synth_cfg0__synth_fbdiv_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_FBDIV_SEL);
  
      CSR_WARM_WR(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG3,
          res_struct->rx_synth_cfg3__synth_freqm_0[0]);
  
      CSR_WARM_WR(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG4,
          res_struct->rx_synth_cfg4__synth_freqn_0[0]);
  
      if (res_struct->rx_synth_cfg1__synth_freq_mult_byp[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQ_MULT_BYP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQ_MULT_BYP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQ_MULT_BYP);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQ_MULT_HI(res_struct->rx_synth_cfg1__synth_freq_mult_hi[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQ_MULT_HI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQ_MULT(res_struct->rx_synth_cfg1__synth_freq_mult[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQ_MULT);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQM_1(res_struct->rx_synth_cfg1__synth_freqm_1[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQM_1);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQN_1(res_struct->rx_synth_cfg1__synth_freqn_1[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG1_SYNTH_FREQN_1);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_FB_STEP(res_struct->rx_synth_cfg0__synth_fb_step[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_FB_STEP);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I2_STEP(res_struct->rx_synth_cfg0__synth_i2_step[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I2_STEP);
  
      if(res_struct->fb_step_param_used[0] == 1) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_FB_STEP(res_struct->rx_synth_cfg0__synth_fb_step[1]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_FB_STEP);
  
      } 
  
      if(res_struct->i2_step_param_used[0] == 1) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I2_STEP(res_struct->rx_synth_cfg0__synth_i2_step[1]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I2_STEP);
  
      } 
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      if (res_struct->rx_synth_cfg0__synth_i2_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I2_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I2_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I2_ENA);
      }
  
      if (res_struct->rx_synth_cfg0__synth_conv_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_CONV_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_CONV_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_CONV_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_SYNC_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_SYNC_CTRL_SYNTH_SC_SYNC_TIMER_SEL(res_struct->rx_synth_sync_ctrl__synth_sc_sync[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_SYNC_CTRL_SYNTH_SC_SYNC_TIMER_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_PHASE_DATA(res_struct->rx_synth_cfg2__synth_phase_data[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_PHASE_DATA);
  
      if (res_struct->rx_synth_cfg2__synth_cpmd_dig_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_CPMD_DIG_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_CPMD_DIG_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_CPMD_DIG_ENA);
      }
  
      if (res_struct->rx_synth_cfg0__synth_p_step[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_P_STEP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_P_STEP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_P_STEP);
      }
  
      if (res_struct->rx_synth_cfg0__synth_i1_step[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I1_STEP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I1_STEP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_I1_STEP);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_DV_CTRL_I1E(res_struct->rx_synth_cfg2__synth_dv_ctrl_i1e[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_DV_CTRL_I1E);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_DV_CTRL_I1M(res_struct->rx_synth_cfg2__synth_dv_ctrl_i1m[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG2_SYNTH_DV_CTRL_I1M);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_MAX1(res_struct->rx_synth_cdrlf__synth_integ1_lim[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_MAX1);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_MAX0(res_struct->rx_synth_cdrlf__synth_integ1_lim[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_MAX0);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_LIM(res_struct->rx_synth_cdrlf__synth_integ1_lim[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_LIM);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_FSEL(res_struct->rx_synth_cdrlf__synth_integ1_fsel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG1_FSEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG2_FSEL(res_struct->rx_synth_cdrlf__synth_integ2_fsel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CDRLF_SYNTH_INTEG2_FSEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_RIB_ADJ(res_struct->ib_cfg0__ib_rib_adj[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_RIB_ADJ);
  
      if (res_struct->ib_cfg0__ib_eqz_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_dfe_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_ld_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_ia_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_ia_sdet_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_SDET_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_SDET_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_SDET_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_EQ_LD1_OFFSET(res_struct->ib_cfg3__ib_eq_ld1_offset[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_EQ_LD1_OFFSET);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_LDSD_DIVSEL(res_struct->ib_cfg3__ib_ldsd_divsel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_LDSD_DIVSEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_IA_SDET_LEVEL(res_struct->ib_cfg3__ib_ia_sdet_level[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_IA_SDET_LEVEL);
  
      if (res_struct->ib_cfg3__ib_sdet_sel[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_SDET_SEL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_SDET_SEL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_SDET_SEL);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5_IB_OFFS_VALUE(res_struct->ib_cfg5__ib_offs_value[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5_IB_OFFS_VALUE);
  
      if (res_struct->ib_cfg5__ib_calmux_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5_IB_CALMUX_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5_IB_CALMUX_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG5_IB_CALMUX_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6_IB_SAM_OFFS_ADJ(res_struct->ib_cfg6__ib_sam_offs_adj[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6_IB_SAM_OFFS_ADJ);
  
      if (res_struct->ib_cfg6__ib_auto_agc_adj[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6_IB_AUTO_AGC_ADJ,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6_IB_AUTO_AGC_ADJ);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6_IB_AUTO_AGC_ADJ);
      }
  
      if (res_struct->ib_cfg7__ib_dfe_gain_adj_s[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7_IB_DFE_GAIN_ADJ_S,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7_IB_DFE_GAIN_ADJ_S);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7_IB_DFE_GAIN_ADJ_S);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7_IB_DFE_GAIN_ADJ(res_struct->ib_cfg7__ib_dfe_gain_adj[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7_IB_DFE_GAIN_ADJ);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7_IB_DFE_OFFSET_H(res_struct->ib_cfg7__ib_dfe_offset_h[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG7_IB_DFE_OFFSET_H);
  
      if( res_struct->skip_cal[0] == 0 ) {
      if (res_struct->ib_cfg8__ib_lat_neutral[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_LAT_NEUTRAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_LAT_NEUTRAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_LAT_NEUTRAL);
      }
  
      if (res_struct->ib_cfg8__ib_lat_neutral[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_LAT_NEUTRAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_LAT_NEUTRAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_LAT_NEUTRAL);
      }
  
      } 
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_IB(res_struct->ib_cfg4__ib_eqz_c_adj_ib[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_IB);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_ES0(res_struct->ib_cfg4__ib_eqz_c_adj_es0[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_ES0);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_ES1(res_struct->ib_cfg4__ib_eqz_c_adj_es1[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_ES1);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_ES2(res_struct->ib_cfg4__ib_eqz_c_adj_es2[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_ADJ_ES2);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_MODE(res_struct->ib_cfg4__ib_eqz_c_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_C_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_L_MODE(res_struct->ib_cfg4__ib_eqz_l_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_EQZ_L_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_VSCOPE_H_THRES(res_struct->ib_cfg4__ib_vscope_h_thres[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_VSCOPE_H_THRES);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_VSCOPE_L_THRES(res_struct->ib_cfg4__ib_vscope_l_thres[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_VSCOPE_L_THRES);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_MAIN_THRES(res_struct->ib_cfg4__ib_main_thres[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG4_IB_MAIN_THRES);
  
      if (res_struct->ib_cfg3__ib_set_sdet[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_SET_SDET,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_SET_SDET);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG3_IB_SET_SDET);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SIG_SEL(res_struct->ib_cfg0__ib_sig_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SIG_SEL);
  
      if (res_struct->ib_cfg10__ib_loop_drv[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10_IB_LOOP_DRV,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10_IB_LOOP_DRV);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10_IB_LOOP_DRV);
      }
  
      if (res_struct->ib_cfg10__ib_loop_rec[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10_IB_LOOP_REC,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10_IB_LOOP_REC);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG10_IB_LOOP_REC);
      }
  
      if (res_struct->ib_cfg11__ib_ena_400_inp[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11_IB_ENA_400_INP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11_IB_ENA_400_INP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11_IB_ENA_400_INP);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11_IB_TC_DFE(res_struct->ib_cfg11__ib_tc_dfe[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11_IB_TC_DFE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11_IB_TC_EQ(res_struct->ib_cfg11__ib_tc_eq[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG11_IB_TC_EQ);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_BW_CDR_SEL_A(res_struct->moebdiv_cfg0__moebdiv_bw_cdr_sel_a[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_BW_CDR_SEL_A);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_BW_CDR_SEL_B(res_struct->moebdiv_cfg0__moebdiv_bw_cdr_sel_b[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_BW_CDR_SEL_B);
  
      if (res_struct->moebdiv_cfg0__moebdiv_cpmd_swap[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_CPMD_SWAP,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_CPMD_SWAP);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_CPMD_SWAP);
      }
  
      if (res_struct->moebdiv_cfg0__moebdiv_dis[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_DIS,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_DIS);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_MOEBDIV_CFG0_MOEBDIV_DIS);
      }
  
      if (res_struct->des_cfg0__des_inv_m[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M);
      }
  
      if (res_struct->des_cfg0__des_inv_h[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H);
      }
  
      if (res_struct->des_cfg0__des_inv_l[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL(res_struct->des_cfg0__des_if_mode_sel[1]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_VCO_CUR(res_struct->rx_rcpll_cfg2__pll_vco_cur[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_VCO_CUR);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_VREG18(res_struct->rx_rcpll_cfg2__pll_vreg18[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_VREG18);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_LPF_CUR(res_struct->rx_rcpll_cfg2__pll_lpf_cur[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_LPF_CUR);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_LPF_RES(res_struct->rx_rcpll_cfg2__pll_lpf_res[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_LPF_RES);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_START_CNT(res_struct->rx_rcpll_cfg0__pllf_start_cnt[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_START_CNT);
  
      if (res_struct->rx_rcpll_cfg0__pllf_syn_clk_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_SYN_CLK_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_SYN_CLK_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_SYN_CLK_ENA);
      }
  
      if (res_struct->rx_rcpll_cfg0__pllf_loop_ctrl_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_LOOP_CTRL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_LOOP_CTRL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_LOOP_CTRL_ENA);
      }
  
      if (res_struct->rx_rcpll_cfg0__pllf_loop_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_LOOP_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_LOOP_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_LOOP_ENA);
      }
  
      if (res_struct->rx_rcpll_cfg0__pllf_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG1_PLLF_REF_CNT_END(res_struct->rx_rcpll_cfg1__pllf_ref_cnt_end[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG1_PLLF_REF_CNT_END);
  
      if (res_struct->rx_rcpll_cfg0__pllf_oor_recal_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      }
  
      if(res_struct->chip_needs_hrate_toggle[0] == 1) {
      VTSS_MSLEEP(10);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL(res_struct->des_cfg0__des_if_mode_sel[2]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[2]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[3]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[4]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[5]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[2]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[3]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[4]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[5]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL(res_struct->des_cfg0__des_if_mode_sel[3]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[6]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[7]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[8]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_hrate_ena[9]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_HRATE_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[6]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[7]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[8]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      if (res_struct->rx_synth_cfg0__synth_ena[9]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL(res_struct->des_cfg0__des_if_mode_sel[1]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_IF_MODE_SEL);
  
      VTSS_MSLEEP(50);
  
      }  else {
      VTSS_MSLEEP(10);
  
  } 
      if (res_struct->rx_rcpll_cfg0__pllf_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_ENA);
      }
  
      if (res_struct->rx_rcpll_cfg0__pllf_oor_recal_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG0_PLLF_OOR_RECAL_ENA);
      }
  
      VTSS_MSLEEP(2);
  
      CSR_RD(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_STAT0, &value);
      value &= VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_STAT0_PLLF_LOCK_STAT;
      value = (value > 0) ? 1 : 0;
      if(value != 0x1) {
          VTSS_E("The expected value for SD10G65_rx_rcpll_stat0 pllf_lock_stat was 0x1 but is 0x%x\n", value);
          rc = VTSS_RC_ERROR;
      } else {
          VTSS_D("Note: The value of SD10G65_rx_rcpll_stat0 pllf_lock_stat was 0x%x\n", value);
      }
  
      CSR_RD(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_STAT1, &value);
      value = VTSS_X_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_STAT1_PLLF_FSM_STAT(value);
      if(value != 0xd) {
          VTSS_E("The expected value for SD10G65_rx_rcpll_stat1 pllf_fsm_stat was 0xd but is 0x%x\n", value);
          rc = VTSS_RC_ERROR;
      } else {
          VTSS_D("Note: The value of SD10G65_rx_rcpll_stat1 pllf_fsm_stat was 0x%x\n", value);
      }
  
    return rc;
  }
  
  vtss_rc vtss_malibu_b_host_pma_sd10g_setup_rx(vtss_state_t *vtss_state, const vtss_sd10g65_setup_rx_args_t config, vtss_port_no_t port_no) {
      vtss_sd10g65_setup_rx_struct_t calc_results;
      vtss_rc ret_val;
      VTSS_D("This function is generated with UTE based on TAG:  UTE_release_vts_ute_tcllib_20180312_trunk_bjo");
      ret_val = vtss_calc_sd10g65_setup_rx(config, &calc_results);
      if(ret_val == VTSS_RC_OK) {
          ret_val |= malibu_b_host_pma_sd10g_rx_register_cfg(vtss_state, &calc_results, port_no);
      }
      return ret_val;
  }
  static vtss_rc malibu_b_host_pma_sd10g_power_down_register_cfg(vtss_state_t *vtss_state, const vtss_sd10g65_pwr_down_t *const res_struct, vtss_port_no_t port_no) {
  
  
      vtss_rc rc = VTSS_RC_OK;
      if (res_struct->sbus_rx_cfg__sbus_bias_en[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      }
  
      if (res_struct->sbus_tx_cfg__sbus_bias_en[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_EN,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_EN);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_SBUS_TX_CFG_SBUS_BIAS_EN);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      if (res_struct->tx_synth_cfg0__synth_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_SYNTH_SD10G65_TX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      if (res_struct->tx_rcpll_cfg2__pll_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->tx_rcpll_cfg2__pll_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_TX_RCPLL_SD10G65_TX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->ob_cfg0__en_ob[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_OB_SD10G65_OB_CFG0_EN_OB);
      }
  
      if (res_struct->rx_synth_cfg0__synth_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      if (res_struct->rx_synth_cfg0__synth_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_SYNTH_SD10G65_RX_SYNTH_CFG0_SYNTH_ENA);
      }
  
      if (res_struct->rx_rcpll_cfg2__pll_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->rx_rcpll_cfg2__pll_ena[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_RX_RCPLL_SD10G65_RX_RCPLL_CFG2_PLL_ENA);
      }
  
      if (res_struct->ib_cfg8__ib_bias_mode[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_BIAS_MODE);
      }
  
      if (res_struct->ib_cfg0__ib_dfe_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_ia_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_IA_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_ld_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_LD_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_clkdiv_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_CLKDIV_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_eqz_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_EQZ_ENA);
      }
  
      if (res_struct->ib_cfg0__ib_sam_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_SAM_ENA);
      }
  
      if (res_struct->sbus_rx_cfg__sbus_bias_en[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_SBUS_RX_CFG_SBUS_BIAS_EN);
      }
  
  
    return rc;
  }
  
  
  vtss_rc vtss_malibu_b_host_pma_sd10g_power_down(vtss_state_t *vtss_state, vtss_port_no_t port_no) {
      vtss_sd10g65_pwr_down_t calc_results;
      vtss_rc ret_val;
      VTSS_D("This function is generated with UTE based on TAG:  UTE_release_vts_ute_tcllib_20180312_trunk_bjo");
      ret_val = vtss_sd10g65_pwr_down(&calc_results);
      if(ret_val == VTSS_RC_OK) {
          ret_val |= malibu_b_host_pma_sd10g_power_down_register_cfg(vtss_state, &calc_results, port_no);
      }
      return ret_val;
  }
  static vtss_rc malibu_b_host_pma_apc10g_register_cfg(vtss_state_t *vtss_state, const vtss_sd10g65_setup_apc_struct_t *const res_struct, vtss_port_no_t port_no) {
      u32 value;
  
  
  
      vtss_rc rc = VTSS_RC_OK;
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_FSM_RECOVER_MODE(res_struct->apc_common_cfg0__apc_fsm_recover_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_FSM_RECOVER_MODE);
  
      if (res_struct->apc_common_cfg0__hml_errcorr_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_HML_ERRCORR_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_HML_ERRCORR_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_HML_ERRCORR_ENA);
      }
  
      if (res_struct->apc_common_cfg0__skip_cal[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_SKIP_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_SKIP_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_SKIP_CAL);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_IF_WIDTH(res_struct->apc_common_cfg0__if_width[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_IF_WIDTH);
  
      if (res_struct->apc_common_cfg0__reset_apc[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      }
  
      if (res_struct->apc_common_cfg0__apc_direct_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_DIRECT_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_DIRECT_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_DIRECT_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LD_CAL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LD_CAL_CFG_CAL_CLK_DIV(res_struct->apc_ld_cal_cfg__cal_clk_div[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LD_CAL_CFG_CAL_CLK_DIV);
  
      if (res_struct->apc_is_cal_cfg0__skip_observe_init[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_offset_init[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_threshold_init[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_dfe_buffer_init[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_observe_cal[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_CAL);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_offset_cal[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_CAL);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_threshold_cal[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_dfe_buffer_cal[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_CAL);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_PAR_DATA_NUM_ONES_THRES(res_struct->apc_is_cal_cfg1__par_data_num_ones_thres[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_PAR_DATA_NUM_ONES_THRES);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_CAL_NUM_ITERATIONS(res_struct->apc_is_cal_cfg1__cal_num_iterations[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_CAL_NUM_ITERATIONS);
  
      if (res_struct->apc_eqz_common_cfg__eqz_gain_auto_restart[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG_EQZ_GAIN_AUTO_RESTART,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG_EQZ_GAIN_AUTO_RESTART);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG_EQZ_GAIN_AUTO_RESTART);
      }
  
      if( res_struct->ib_cal_only[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_INI(res_struct->apc_eqz_agc_par_cfg__eqz_agc_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_INI(res_struct->apc_dfe1_par_cfg__dfe1_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_INI(res_struct->apc_dfe2_par_cfg__dfe2_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_INI(res_struct->apc_dfe3_par_cfg__dfe3_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_INI(res_struct->apc_dfe4_par_cfg__dfe4_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_INI);
  
      }  else {
      if( res_struct->throttle_mode[0] == 1 ) {
      if (res_struct->sd10g65_ib_cfg0__ib_vscope_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_VSCOPE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_VSCOPE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_VSCOPE_ENA);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG_FSM1_OP_MODE(res_struct->apc_parctrl_sync_cfg__fsm1_op_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG_FSM1_OP_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_FSM1_TIMER_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_FSM1_TIMER_CFG_FSM1_OP_TIME(res_struct->apc_parctrl_fsm1_timer_cfg__fsm1_op_time[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_FSM1_TIMER_CFG_FSM1_OP_TIME);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_TOP_CTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_TOP_CTRL_CFG_SLEEP_TIME(res_struct->apc_top_ctrl_cfg__sleep_time[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_TOP_CTRL_CFG_SLEEP_TIME);
  
      if (res_struct->apc_common_cfg0__throttle_mode[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_THROTTLE_MODE,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_THROTTLE_MODE);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_THROTTLE_MODE);
      }
  
      }  else if( res_struct->single_step[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG_FSM1_OP_MODE(res_struct->apc_parctrl_sync_cfg__fsm1_op_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG_FSM1_OP_MODE);
  
  }  else {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_FSM1_TIMER_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_FSM1_TIMER_CFG_FSM1_OP_TIME(res_struct->apc_parctrl_fsm1_timer_cfg__fsm1_op_time[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_FSM1_TIMER_CFG_FSM1_OP_TIME);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG_FSM1_OP_MODE(res_struct->apc_parctrl_sync_cfg__fsm1_op_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_PARCTRL_SYNC_CFG_FSM1_OP_MODE);
  
  } 
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_LD_LEV_INI(res_struct->apc_eqz_ld_ctrl__ld_lev_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_LD_LEV_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG0_LD_T_DEADTIME_WRK(res_struct->apc_eqz_ld_ctrl_cfg0__ld_t_deadtime_wrk[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG0_LD_T_DEADTIME_WRK);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG0_LD_T_TIMEOUT_WRK(res_struct->apc_eqz_ld_ctrl_cfg0__ld_t_timeout_wrk[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG0_LD_T_TIMEOUT_WRK);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG1_LD_T_DEADTIME_CAL(res_struct->apc_eqz_ld_ctrl_cfg1__ld_t_deadtime_cal[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG1_LD_T_DEADTIME_CAL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG1_LD_T_TIMEOUT_CAL(res_struct->apc_eqz_ld_ctrl_cfg1__ld_t_timeout_cal[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_LD_CTRL_CFG1_LD_T_TIMEOUT_CAL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_C_PAT_MASK(res_struct->apc_eqz_pat_match_cfg0__eqz_c_pat_mask[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_C_PAT_MASK);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_C_PAT_MATCH(res_struct->apc_eqz_pat_match_cfg0__eqz_c_pat_match[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_C_PAT_MATCH);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_L_PAT_MASK(res_struct->apc_eqz_pat_match_cfg0__eqz_l_pat_mask[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_L_PAT_MASK);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_L_PAT_MATCH(res_struct->apc_eqz_pat_match_cfg0__eqz_l_pat_match[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG0_EQZ_L_PAT_MATCH);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_OFFS_PAT_MASK(res_struct->apc_eqz_pat_match_cfg1__eqz_offs_pat_mask[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_OFFS_PAT_MASK);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_OFFS_PAT_MATCH(res_struct->apc_eqz_pat_match_cfg1__eqz_offs_pat_match[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_OFFS_PAT_MATCH);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_AGC_PAT_MASK(res_struct->apc_eqz_pat_match_cfg1__eqz_agc_pat_mask[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_AGC_PAT_MASK);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_AGC_PAT_MATCH(res_struct->apc_eqz_pat_match_cfg1__eqz_agc_pat_match[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_PAT_MATCH_CFG1_EQZ_AGC_PAT_MATCH);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_CHG_MODE(res_struct->apc_eqz_offs_par_cfg__eqz_offs_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_RANGE_SEL(res_struct->apc_eqz_offs_par_cfg__eqz_offs_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_MAX(res_struct->apc_eqz_offs_par_cfg__eqz_offs_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_MIN(res_struct->apc_eqz_offs_par_cfg__eqz_offs_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_INI(res_struct->apc_eqz_offs_par_cfg__eqz_offs_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_CTRL_EQZ_OFFS_SYNC_MODE(res_struct->apc_eqz_offs_ctrl__eqz_offs_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_CTRL_EQZ_OFFS_SYNC_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_CHG_MODE(res_struct->apc_eqz_agc_par_cfg__eqz_agc_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_RANGE_SEL(res_struct->apc_eqz_agc_par_cfg__eqz_agc_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_MAX(res_struct->apc_eqz_agc_par_cfg__eqz_agc_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_MIN(res_struct->apc_eqz_agc_par_cfg__eqz_agc_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_INI(res_struct->apc_eqz_agc_par_cfg__eqz_agc_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_PAR_CFG_EQZ_AGC_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_CTRL_EQZ_AGC_SYNC_MODE(res_struct->apc_eqz_agc_ctrl__eqz_agc_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_AGC_CTRL_EQZ_AGC_SYNC_MODE);
  
      if (res_struct->apc_eqz_offs_par_cfg__eqz_offs_dir_sel[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_DIR_SEL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_DIR_SEL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_OFFS_PAR_CFG_EQZ_OFFS_DIR_SEL);
      }
  
      if( res_struct->force_eqz_l[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_CHG_MODE(res_struct->apc_eqz_l_par_cfg__eqz_l_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_INI(res_struct->apc_eqz_l_par_cfg__eqz_l_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL_EQZ_L_SYNC_MODE(res_struct->apc_eqz_l_ctrl__eqz_l_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL_EQZ_L_SYNC_MODE);
  
      }  else if( res_struct->high_data_rate[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_CHG_MODE(res_struct->apc_eqz_l_par_cfg__eqz_l_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_RANGE_SEL(res_struct->apc_eqz_l_par_cfg__eqz_l_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_MAX(res_struct->apc_eqz_l_par_cfg__eqz_l_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_MIN(res_struct->apc_eqz_l_par_cfg__eqz_l_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_INI(res_struct->apc_eqz_l_par_cfg__eqz_l_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL_EQZ_L_SYNC_MODE(res_struct->apc_eqz_l_ctrl__eqz_l_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL_EQZ_L_SYNC_MODE);
  
  }  else {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_CHG_MODE(res_struct->apc_eqz_l_par_cfg__eqz_l_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_INI(res_struct->apc_eqz_l_par_cfg__eqz_l_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_PAR_CFG_EQZ_L_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL_EQZ_L_SYNC_MODE(res_struct->apc_eqz_l_ctrl__eqz_l_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_L_CTRL_EQZ_L_SYNC_MODE);
  
  } 
      if( res_struct->force_eqz_c[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_CHG_MODE(res_struct->apc_eqz_c_par_cfg__eqz_c_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_INI(res_struct->apc_eqz_c_par_cfg__eqz_c_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL_EQZ_C_SYNC_MODE(res_struct->apc_eqz_c_ctrl__eqz_c_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL_EQZ_C_SYNC_MODE);
  
      }  else if( res_struct->high_data_rate[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_CHG_MODE(res_struct->apc_eqz_c_par_cfg__eqz_c_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_RANGE_SEL(res_struct->apc_eqz_c_par_cfg__eqz_c_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_MAX(res_struct->apc_eqz_c_par_cfg__eqz_c_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_MIN(res_struct->apc_eqz_c_par_cfg__eqz_c_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_INI(res_struct->apc_eqz_c_par_cfg__eqz_c_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL_EQZ_C_SYNC_MODE(res_struct->apc_eqz_c_ctrl__eqz_c_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL_EQZ_C_SYNC_MODE);
  
  }  else {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_CHG_MODE(res_struct->apc_eqz_c_par_cfg__eqz_c_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_INI(res_struct->apc_eqz_c_par_cfg__eqz_c_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_PAR_CFG_EQZ_C_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL_EQZ_C_SYNC_MODE(res_struct->apc_eqz_c_ctrl__eqz_c_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_C_CTRL_EQZ_C_SYNC_MODE);
  
  } 
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_CHG_MODE(res_struct->apc_dfe1_par_cfg__dfe1_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_RANGE_SEL(res_struct->apc_dfe1_par_cfg__dfe1_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_MAX(res_struct->apc_dfe1_par_cfg__dfe1_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_MIN(res_struct->apc_dfe1_par_cfg__dfe1_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_INI(res_struct->apc_dfe1_par_cfg__dfe1_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_PAR_CFG_DFE1_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_CTRL_DFE1_SYNC_MODE(res_struct->apc_dfe1_ctrl__dfe1_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE1_CTRL_DFE1_SYNC_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_CHG_MODE(res_struct->apc_dfe2_par_cfg__dfe2_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_RANGE_SEL(res_struct->apc_dfe2_par_cfg__dfe2_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_MAX(res_struct->apc_dfe2_par_cfg__dfe2_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_MIN(res_struct->apc_dfe2_par_cfg__dfe2_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_INI(res_struct->apc_dfe2_par_cfg__dfe2_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_PAR_CFG_DFE2_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_CTRL_DFE2_SYNC_MODE(res_struct->apc_dfe2_ctrl__dfe2_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE2_CTRL_DFE2_SYNC_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_CHG_MODE(res_struct->apc_dfe3_par_cfg__dfe3_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_RANGE_SEL(res_struct->apc_dfe3_par_cfg__dfe3_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_MAX(res_struct->apc_dfe3_par_cfg__dfe3_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_MIN(res_struct->apc_dfe3_par_cfg__dfe3_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_INI(res_struct->apc_dfe3_par_cfg__dfe3_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_PAR_CFG_DFE3_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_CTRL_DFE3_SYNC_MODE(res_struct->apc_dfe3_ctrl__dfe3_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE3_CTRL_DFE3_SYNC_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_CHG_MODE(res_struct->apc_dfe4_par_cfg__dfe4_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_CHG_MODE);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_RANGE_SEL(res_struct->apc_dfe4_par_cfg__dfe4_range_sel[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_RANGE_SEL);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_MAX(res_struct->apc_dfe4_par_cfg__dfe4_max[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_MAX);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_MIN(res_struct->apc_dfe4_par_cfg__dfe4_min[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_MIN);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_INI(res_struct->apc_dfe4_par_cfg__dfe4_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_PAR_CFG_DFE4_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_CTRL,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_CTRL_DFE4_SYNC_MODE(res_struct->apc_dfe4_ctrl__dfe4_sync_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_DFE4_CTRL_DFE4_SYNC_MODE);
  
      if( res_struct->apc_eqz_common_cfg__eqz_gain_chg_mode[0] != 0 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_GAIN_CTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_GAIN_CTRL_CFG_EQZ_GAIN_INI(res_struct->apc_eqz_gain_ctrl_cfg__eqz_gain_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_GAIN_CTRL_CFG_EQZ_GAIN_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_GAIN_ADJ_CTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_GAIN_ADJ_CTRL_CFG_EQZ_GAIN_ADJ_INI(res_struct->apc_eqz_gain_adj_ctrl_cfg__eqz_gain_adj_ini[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_GAIN_ADJ_CTRL_CFG_EQZ_GAIN_ADJ_INI);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG_EQZ_GAIN_CHG_MODE(res_struct->apc_eqz_common_cfg__eqz_gain_chg_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_EQZ_COMMON_CFG_EQZ_GAIN_CHG_MODE);
  
      } 
  
  } 
      if( res_struct->skip_cal[0] != 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6,
          VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6_IB_SAM_OFFS_ADJ(31),
          VTSS_M_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG6_IB_SAM_OFFS_ADJ);
  
      if( res_struct->is_2pt_cal[0] == 0 ) {
      if (res_struct->sd10g65_ib_cfg8__ib_inv_thr_cal_val[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_INV_THR_CAL_VAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_INV_THR_CAL_VAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG8_IB_INV_THR_CAL_VAL);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_CPMD_THRES_INIT(res_struct->apc_is_cal_cfg0__cpmd_thres_init[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_CPMD_THRES_INIT);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_VSC_THRES_INIT(res_struct->apc_is_cal_cfg0__vsc_thres_init[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_VSC_THRES_INIT);
  
      if (res_struct->apc_is_cal_cfg0__skip_threshold_cal[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL);
      }
  
      if (res_struct->apc_is_cal_cfg1__cal_vsc_offset_tgt[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_CAL_VSC_OFFSET_TGT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_CAL_VSC_OFFSET_TGT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_CAL_VSC_OFFSET_TGT);
      }
  
      } 
  
      if (res_struct->sd10g65_ib_cfg0__ib_dfe_ena[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      }
  
      if (res_struct->sd10g65_des_cfg0__des_inv_x[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M);
      }
  
      if (res_struct->sd10g65_des_cfg0__des_inv_x[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H);
      }
  
      if (res_struct->sd10g65_des_cfg0__des_inv_x[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L);
      }
  
      if( res_struct->incl_ld_cal[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE(res_struct->apc_common_cfg0__apc_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE);
  
      VTSS_MSLEEP(2);
  
      if (res_struct->apc_common_cfg0__reset_apc[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      }
  
      }  else {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE(res_struct->apc_common_cfg0__apc_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE);
  
      if (res_struct->apc_common_cfg0__reset_apc[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      }
  
      VTSS_MSLEEP(1);
  
      if (1) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_START_OFFSCAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_START_OFFSCAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_START_OFFSCAL);
      }
  
  } 
      VTSS_MSLEEP(res_struct->calibration_time_ms[1]);
  
      if( res_struct->incl_ld_cal[0] == 1 ) {
      CSR_RD(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LD_CAL_CFG, &value);
      value &= VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LD_CAL_CFG_DETLEV_CAL_DONE;
      value = (value > 0) ? 1 : 0;
      if(value != 0x1) {
          VTSS_E("The expected value for apc_ld_cal_cfg detlev_cal_done was 0x1 but is 0x%x\n", value);
          rc = VTSS_RC_ERROR;
      } else {
          VTSS_D("Note: The value of apc_ld_cal_cfg detlev_cal_done was 0x%x\n", value);
      }
  
      }  else {
      CSR_RD(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1, &value);
      value &= VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_OFFSCAL_DONE;
      value = (value > 0) ? 1 : 0;
      if(value != 0x1) {
          VTSS_E("The expected value for apc_is_cal_cfg1 offscal_done was 0x1 but is 0x%x\n", value);
          rc = VTSS_RC_ERROR;
      } else {
          VTSS_D("Note: The value of apc_is_cal_cfg1 offscal_done was 0x%x\n", value);
      }
  
      if (0) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_START_OFFSCAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_START_OFFSCAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG1_START_OFFSCAL);
      }
  
  } 
      if (res_struct->sd10g65_des_cfg0__des_inv_x[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_M);
      }
  
      if (res_struct->sd10g65_des_cfg0__des_inv_x[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_H);
      }
  
      if (res_struct->sd10g65_des_cfg0__des_inv_x[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_DES_SD10G65_DES_CFG0_DES_INV_L);
      }
  
      if (1) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_IB_SD10G65_IB_CFG0_IB_DFE_ENA);
      }
  
      if( res_struct->ib_cal_only[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE(0),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE);
  
      if (0) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_DIRECT_ENA,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_DIRECT_ENA);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_DIRECT_ENA);
      }
  
      } 
  
      } 
  
      if( res_struct->ib_cal_only[0] == 0 ) {
      if( res_struct->incl_ld_cal[0] == 1 ) {
      if (res_struct->apc_is_cal_cfg0__skip_observe_init[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_offset_init[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_threshold_init[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_dfe_buffer_init[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_INIT,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_INIT);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_INIT);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_observe_cal[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OBSERVE_CAL);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_offset_cal[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_OFFSET_CAL);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_threshold_cal[2]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_THRESHOLD_CAL);
      }
  
      if (res_struct->apc_is_cal_cfg0__skip_dfe_buffer_cal[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_IS_CAL_CFG0_SKIP_DFE_BUFFER_CAL);
      }
  
      }  else {
      if (res_struct->apc_common_cfg0__skip_cal[1]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_SKIP_CAL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_SKIP_CAL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_SKIP_CAL);
      }
  
  } 
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE(res_struct->apc_common_cfg0__apc_mode[2]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_APC_MODE);
  
      if( res_struct->skip_cal[0] == 1 ) {
      VTSS_MSLEEP(2);
  
      if (0) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_COMMON_CFG0_RESET_APC);
      }
  
      } 
  
      if( res_struct->lc_smartctrl[0] == 1 ) {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG1_LC_SC_DFE2_TARGET(res_struct->apc_lc_softctrl_cfg1__lc_sc_dfe2_target[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG1_LC_SC_DFE2_TARGET);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG1,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG1_LC_SC_DFE1_TARGET(res_struct->apc_lc_softctrl_cfg1__lc_sc_dfe1_target[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG1_LC_SC_DFE1_TARGET);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_TIMER(res_struct->apc_lc_softctrl_cfg__lc_sc_timer[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_TIMER);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_AVGSHFT(res_struct->apc_lc_softctrl_cfg__lc_sc_avgshft[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_AVGSHFT);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DFE1_THRESHOLD(res_struct->apc_lc_softctrl_cfg__lc_sc_dfe1_threshold[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DFE1_THRESHOLD);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DFE2_THRESHOLD(res_struct->apc_lc_softctrl_cfg__lc_sc_dfe2_threshold[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DFE2_THRESHOLD);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_AGC_THRESHOLD(res_struct->apc_lc_softctrl_cfg__lc_sc_agc_threshold[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_AGC_THRESHOLD);
  
      if (res_struct->apc_lc_softctrl_cfg__lc_sc_div_c_sel[0]) {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DIV_C_SEL,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DIV_C_SEL);
      } else {
          CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
              0,
              VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DIV_C_SEL);
      }
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DIV_L(res_struct->apc_lc_softctrl_cfg__lc_sc_div_l[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DIV_L);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DIV_C(res_struct->apc_lc_softctrl_cfg__lc_sc_div_c[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_DIV_C);
  
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_MODE(res_struct->apc_lc_softctrl_cfg__lc_sc_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_MODE);
  
      }  else {
      CSR_WARM_WRM(port_no, VTSS_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG,
          VTSS_F_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_MODE(res_struct->apc_lc_softctrl_cfg__lc_sc_mode[0]),
          VTSS_M_HOST_PMA_32BIT_SD10G65_APC_APC_LC_SOFTCTRL_CFG_LC_SC_MODE);
  
  } 
      } 
  
    return rc;
  }
  
  vtss_rc vtss_malibu_b_host_pma_apc10g_setup(vtss_state_t *vtss_state, const vtss_sd10g65_setup_apc_args_t config, vtss_port_no_t port_no) {
      vtss_sd10g65_setup_apc_struct_t calc_results;
      vtss_rc ret_val;
      VTSS_D("This function is generated with UTE based on TAG:  UTE_release_vts_ute_tcllib_20180312_trunk_bjo");
  
      ret_val = vtss_calc_sd10g65_setup_apc(config, &calc_results);
      if(ret_val == VTSS_RC_OK) {
          ret_val |= malibu_b_host_pma_apc10g_register_cfg(vtss_state, &calc_results, port_no);
      }
      return ret_val;
  }
  #endif
  #endif
  