text: /*******************************************************************
  *
  * Copyright (C) 2010-2015 Xilinx, Inc. All rights reserved.
  *
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  *copies of the Software, and to permit persons to whom the Software is
  *furnished to do so, subject to the following conditions:
  *
  *The above copyright notice and this permission notice shall be included in
  *all copies or substantial portions of the Software.
  *
  * Use of the Software is limited solely to applications:
  *(a) running on a Xilinx device, or
  *(b) that interact with a Xilinx device through a bus or interconnect.
  *
  *THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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  *OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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  *Except as contained in this notice, the name of the Xilinx shall not be used
  *in advertising or otherwise to promote the sale, use or other dealings in
  *this Software without prior written authorization from Xilinx.
  *
  *******************************************************************/
  
  #include "xparameters.h"
  #include "xzdma.h"
  
  /*
  * The configuration table for devices
  */
  
  XZDma_Config XZDma_ConfigTable[] =
  {
  	{
  		XPAR_PSU_ADMA_CH0_DEVICE_ID,
  		XPAR_PSU_ADMA_CH0_BASEADDR,
  		XPAR_PSU_ADMA_CH0_DMA_MODE
  	},
  	{
  		XPAR_PSU_ADMA_CH1_DEVICE_ID,
  		XPAR_PSU_ADMA_CH1_BASEADDR,
  		XPAR_PSU_ADMA_CH1_DMA_MODE
  	},
  	{
  		XPAR_PSU_ADMA_CH2_DEVICE_ID,
  		XPAR_PSU_ADMA_CH2_BASEADDR,
  		XPAR_PSU_ADMA_CH2_DMA_MODE
  	},
  	{
  		XPAR_PSU_ADMA_CH3_DEVICE_ID,
  		XPAR_PSU_ADMA_CH3_BASEADDR,
  		XPAR_PSU_ADMA_CH3_DMA_MODE
  	},
  	{
  		XPAR_PSU_ADMA_CH4_DEVICE_ID,
  		XPAR_PSU_ADMA_CH4_BASEADDR,
  		XPAR_PSU_ADMA_CH4_DMA_MODE
  	},
  	{
  		XPAR_PSU_ADMA_CH5_DEVICE_ID,
  		XPAR_PSU_ADMA_CH5_BASEADDR,
  		XPAR_PSU_ADMA_CH5_DMA_MODE
  	},
  	{
  		XPAR_PSU_ADMA_CH6_DEVICE_ID,
  		XPAR_PSU_ADMA_CH6_BASEADDR,
  		XPAR_PSU_ADMA_CH6_DMA_MODE
  	},
  	{
  		XPAR_PSU_ADMA_CH7_DEVICE_ID,
  		XPAR_PSU_ADMA_CH7_BASEADDR,
  		XPAR_PSU_ADMA_CH7_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH0_DEVICE_ID,
  		XPAR_PSU_GDMA_CH0_BASEADDR,
  		XPAR_PSU_GDMA_CH0_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH1_DEVICE_ID,
  		XPAR_PSU_GDMA_CH1_BASEADDR,
  		XPAR_PSU_GDMA_CH1_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH2_DEVICE_ID,
  		XPAR_PSU_GDMA_CH2_BASEADDR,
  		XPAR_PSU_GDMA_CH2_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH3_DEVICE_ID,
  		XPAR_PSU_GDMA_CH3_BASEADDR,
  		XPAR_PSU_GDMA_CH3_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH4_DEVICE_ID,
  		XPAR_PSU_GDMA_CH4_BASEADDR,
  		XPAR_PSU_GDMA_CH4_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH5_DEVICE_ID,
  		XPAR_PSU_GDMA_CH5_BASEADDR,
  		XPAR_PSU_GDMA_CH5_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH6_DEVICE_ID,
  		XPAR_PSU_GDMA_CH6_BASEADDR,
  		XPAR_PSU_GDMA_CH6_DMA_MODE
  	},
  	{
  		XPAR_PSU_GDMA_CH7_DEVICE_ID,
  		XPAR_PSU_GDMA_CH7_BASEADDR,
  		XPAR_PSU_GDMA_CH7_DMA_MODE
  	}
  };
  