text: /* mbed Microcontroller Library
   * Copyright (c) 2006-2013 ARM Limited
   *
   * Licensed under the Apache License, Version 2.0 (the "License");
   * you may not use this file except in compliance with the License.
   * You may obtain a copy of the License at
   *
   *     http://www.apache.org/licenses/LICENSE-2.0
   *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an "AS IS" BASIS,
   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
   */
  #include "gpio_api.h"
  #include "clock_config.h"
  #include "fsl_emc.h"
  #include "fsl_power.h"
  #include "fsl_flashiap.h"
  #include "hal/pinmap.h"
  
  #define CRC16
  #include "crc.h"
  
  /*******************************************************************************
   * Definitions
   ******************************************************************************/
  /* The SDRAM timing. */
  #define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
  #define SDRAM_TRP_NS (18u)
  #define SDRAM_TRAS_NS (42u)
  #define SDRAM_TSREX_NS (67u)
  #define SDRAM_TAPR_NS (18u)
  #define SDRAM_TWRDELT_NS (6u)
  #define SDRAM_TRC_NS (60u)
  #define SDRAM_RFC_NS (60u)
  #define SDRAM_XSR_NS (67u)
  #define SDRAM_RRD_NS (12u)
  #define SDRAM_MRD_NCLK (2u)
  #define SDRAM_RAS_NCLK (2u)
  #define SDRAM_MODEREG_VALUE (0x23u)
  #define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
  
  uint32_t FLASHIAP_ReadUid(uint32_t *addr)
  {
      uint32_t command[5], result[5];
  
      command[0] = kIapCmd_FLASHIAP_ReadUid;
      iap_entry(command, result);
  
      memcpy(addr, &result[1], (sizeof(uint32_t) * 4));
  
      return result[0];
  }
  
  // called before main
  void mbed_sdk_init()
  {
      if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
          BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/
          /* LPC54628 runs at a higher core speed */
          BOARD_BootClockPLL220M();
      } else {
          BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/
          BOARD_BootClockPLL180M();
      }
  }
  
  // Change the NMI pin to an input. This allows NMI pin to
  //  be used as a low power mode wakeup.  The application will
  //  need to change the pin back to NMI_b or wakeup only occurs once!
  void NMI_Handler(void)
  {
      //gpio_t gpio;
      //gpio_init_in(&gpio, PTA4);
  }
  
  // Enable the RTC oscillator if available on the board
  void rtc_setup_oscillator(void)
  {
      /* Enable the RTC 32K Oscillator */
      SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
  }
  
  uint32_t us_ticker_get_clock()
  {
      return CLOCK_GetFreq(kCLOCK_BusClk);;
  }
  
  // Provide ethernet devices with a semi-unique MAC address from the UUID
  void mbed_mac_address(char *mac)
  {
      uint16_t MAC[3];                        // 3 16 bits words for the MAC
      uint32_t UID[4];
  
      // get UID via ISP commands
      FLASHIAP_ReadUid(UID);
  
      // generate three CRC16's using different slices of the UUID
      MAC[0] = crcSlow((const uint8_t *)UID, 8);  // most significant half-word
      MAC[1] = crcSlow((const uint8_t *)UID, 12);
      MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word
  
      // The network stack expects an array of 6 bytes
      // so we copy, and shift and copy from the half-word array to the byte array
      mac[0] = MAC[0] >> 8;
      mac[1] = MAC[0];
      mac[2] = MAC[1] >> 8;
      mac[3] = MAC[1];
      mac[4] = MAC[2] >> 8;
      mac[5] = MAC[2];
  
      // We want to force bits [1:0] of the most significant byte [0]
      // to be "10"
      // http://en.wikipedia.org/wiki/MAC_address
  
      mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered"
      mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast
  
  }
  
  void ADC_ClockPower_Configuration(void)
  {
      /* SYSCON power. */
      POWER_DisablePD(kPDRUNCFG_PD_VDDA);    /* Power on VDDA. */
      POWER_DisablePD(kPDRUNCFG_PD_ADC0);    /* Power on the ADC converter. */
      POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */
      POWER_DisablePD(kPDRUNCFG_PD_VREFP);   /* Power on the reference voltage source. */
      POWER_DisablePD(kPDRUNCFG_PD_TS);      /* Power on the temperature sensor. */
  
  
      /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */
      /* Sync clock source is not used. Using sync clock source and would be divided by 2.
       * The divider would be set when configuring the converter.
       */
      CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */
  }
  
  /* Initialize the external memory. */
  void BOARD_InitSDRAM(void)
  {
      emc_basic_config_t basicConfig;
      emc_dynamic_timing_config_t dynTiming;
      emc_dynamic_chip_config_t dynChipConfig;
  
      /* Basic configuration. */
      basicConfig.endian = kEMC_LittleEndian;
      basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
      /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
       * If you change the divide to 0 and EMC clock is larger than 100M
       * please take refer to emc.dox to adjust EMC clock delay.
       */
      basicConfig.emcClkDiv = 1;
      /* Dynamic memory timing configuration. */
      dynTiming.readConfig = kEMC_Cmddelay;
      dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
      dynTiming.tRp_Ns = SDRAM_TRP_NS;
      dynTiming.tRas_Ns = SDRAM_TRAS_NS;
      dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
      dynTiming.tApr_Ns = SDRAM_TAPR_NS;
      dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */
      dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
      dynTiming.tRc_Ns = SDRAM_TRC_NS;
      dynTiming.tRfc_Ns = SDRAM_RFC_NS;
      dynTiming.tXsr_Ns = SDRAM_XSR_NS;
      dynTiming.tRrd_Ns = SDRAM_RRD_NS;
      dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
      /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
      dynChipConfig.chipIndex = 0;
      dynChipConfig.dynamicDevice = kEMC_Sdram;
      dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
      dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
      dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
      dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
      /* EMC Basic configuration. */
      EMC_Init(EMC, &basicConfig);
      /* EMC Dynamc memory configuration. */
      EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
  }
  
  // Get the QSPI clock frequency
  uint32_t qspi_get_freq(void)
  {
      CLOCK_AttachClk(kFRO_HF_to_SPIFI_CLK);
  
      return CLOCK_GetFroHfFreq();
  }
  
  const PinList *pinmap_restricted_pins()
  {
      /* D6 pin is used by the LCD
         A4 pin is used by the accelerometer */
      static const PinName pins[] = {
          D6, A4
      };
      static const PinList pin_list = {
          sizeof(pins) / sizeof(pins[0]),
          pins
      };
      return &pin_list;
  }
  
  