text: /*
   * DO NOT EDIT THIS FILE!
   * This file is auto-generated from the registers file.
   * Edits to this file will be lost when it is regenerated.
   *
   * 
   * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
   * 
   * Copyright 2007-2019 Broadcom Inc. All rights reserved.
   *
   * File:    ddrc28.h
   * Purpose: PHY info for ddrc28
   */
  
  
  #ifndef _SOC_PHY_DDRC28_H
  #define _SOC_PHY_DDRC28_H
  
  #include <soc/register.h>
  #include <soc/types.h>
  
  extern int soc_phy_ddrc28_reg32_read(int unit, soc_reg_t reg, int instance, uint32 *data);
  extern int soc_phy_ddrc28_reg32_write(int unit, soc_reg_t reg, int instance, uint32 data);
  extern int soc_phy_ddrc28_reg_field_set(int unit, soc_reg_t reg, uint32 *regval, soc_field_t field, uint32 value);
  extern int soc_phy_ddrc28_reg_field_get(int unit, soc_reg_t reg, uint32 regval, soc_field_t field, uint32* field_val);
  
  extern soc_reg_info_t soc_phy_ddrc28_reg_list[];
  
  
  extern soc_field_info_t soc_phy_ddrc28_AQ_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_LDO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_LOOPBACK_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_L_MACRO_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_L_MAX_VDL_ADDRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_L_MAX_VDL_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_L_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_U_MACRO_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_U_MAX_VDL_ADDRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_U_MAX_VDL_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_AQ_U_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_CK_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_LDO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_MACRO_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_MAX_VDL_CKr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_RESCAL_INIT_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_RESCAL_OPERATION_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_COMMON_STATUS_RESCALr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_FREQ_CNTR_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_INPUT_SHIFT_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_READ_CLOCK_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_READ_FIFO_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_RESET_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_REVISIONr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_WRITE_FIFO_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_IQ_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_OPERATION_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_PN_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_DATA_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_DQS_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_EDCEN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_LDO_R_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_LDO_W_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_MACRO_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MAX_VDL_DQSNr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MAX_VDL_DQSPr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MAX_VDL_FSMr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_EDCr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_REN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_REN_GEN_ERR_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_REN_STRETCH_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_CDR_IQ_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_CDR_OPERATIONr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_CDR_PN_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_EDCEN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_EDCRDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACHr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_GEN_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_GEN_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_WRITE_LEVELINGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_VREF_DAC_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_LEVELING_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MAX_VDL_DATAr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MAX_VDL_DQSr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_EDCr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_IQ_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_OPERATION_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_PN_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_DATA_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_DQS_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_EDCEN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_LDO_R_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_LDO_W_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_MACRO_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MAX_VDL_DQSNr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MAX_VDL_DQSPr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MAX_VDL_FSMr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_EDCr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_REN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_REN_GEN_ERR_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_REN_STRETCH_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_CDR_IQ_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_CDR_OPERATIONr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_CDR_PN_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_EDCEN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_EDCRDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACHr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_GEN_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_GEN_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_WRITE_LEVELINGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_VREF_DAC_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_LEVELING_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MAX_VDL_DATAr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MAX_VDL_DQSr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_EDCr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_IQ_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_OPERATION_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_PN_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_DATA_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_DQS_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_EDCEN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_LDO_R_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_LDO_W_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_MACRO_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MAX_VDL_DQSNr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MAX_VDL_DQSPr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MAX_VDL_FSMr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_EDCr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_REN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_REN_GEN_ERR_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_REN_STRETCH_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_CDR_IQ_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_CDR_OPERATIONr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_CDR_PN_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_EDCEN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_EDCRDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACHr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_GEN_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_GEN_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_WRITE_LEVELINGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_VREF_DAC_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_LEVELING_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MAX_VDL_DATAr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MAX_VDL_DQSr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_EDCr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_IQ_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_OPERATION_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_PN_VDL_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_DATA_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_DQS_IO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_EDCEN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_LDO_R_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_LDO_W_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_MACRO_RESERVED_REGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MAX_VDL_DQSNr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MAX_VDL_DQSPr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MAX_VDL_FSMr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_EDCr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_REN_FIFO_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_REN_GEN_ERR_CTRLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_REN_STRETCH_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_CDR_IQ_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_CDR_OPERATIONr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_CDR_PN_VDLr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_EDCEN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_EDCRDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_MACRO_RESERVEDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACHr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RDATA_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_FIFOr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_GEN_ERR1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_GEN_ERR2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_WRITE_LEVELINGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_VREF_DAC_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_LEVELING_CONFIGr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MAX_VDL_DATAr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MAX_VDL_DQSr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT0r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT1r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT2r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT3r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT4r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT5r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT6r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT7r_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_DBIr_fields[];
  extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_EDCr_fields[];
  
  typedef enum soc_phy_ddrc28_fields_e {
      SOC_PHY_FLD_ACCU_LOADf,
      SOC_PHY_FLD_ACCU_LOAD_VALUEf,
      SOC_PHY_FLD_ACCU_POS_THRESHOLDf,
      SOC_PHY_FLD_ACCU_VALUEf,
      SOC_PHY_FLD_AQ_L_FLIP_RDATA_UIf,
      SOC_PHY_FLD_AQ_L_LOOPBACK_WR_RESET_Nf,
      SOC_PHY_FLD_AQ_L_TEST_UPPER_HALFf,
      SOC_PHY_FLD_AQ_U_FLIP_RDATA_UIf,
      SOC_PHY_FLD_AQ_U_LOOPBACK_WR_RESET_Nf,
      SOC_PHY_FLD_AQ_U_TEST_UPPER_HALFf,
      SOC_PHY_FLD_A_0f,
      SOC_PHY_FLD_A_MINUS_1f,
      SOC_PHY_FLD_A_MINUS_2f,
      SOC_PHY_FLD_A_MINUS_3f,
      SOC_PHY_FLD_A_PLUS_1f,
      SOC_PHY_FLD_A_PLUS_2f,
      SOC_PHY_FLD_BIAS_CTRLf,
      SOC_PHY_FLD_BYPASSf,
      SOC_PHY_FLD_CDR_RESET_Nf,
      SOC_PHY_FLD_CK_ENABLEf,
      SOC_PHY_FLD_CLK_DIV_RATIOf,
      SOC_PHY_FLD_COMP_ACKf,
      SOC_PHY_FLD_COMP_DONEf,
      SOC_PHY_FLD_COMP_ENf,
      SOC_PHY_FLD_COMP_ERRORf,
      SOC_PHY_FLD_COMP_INIT_FDEPTHf,
      SOC_PHY_FLD_COMP_INIT_OFFSETf,
      SOC_PHY_FLD_COMP_OFFSET_ENf,
      SOC_PHY_FLD_COMP_OFFSET_OPf,
      SOC_PHY_FLD_CTRLf,
      SOC_PHY_FLD_CUR_STATEf,
      SOC_PHY_FLD_CUR_WCOUNTf,
      SOC_PHY_FLD_DATAf,
      SOC_PHY_FLD_DATAPATH_ADDITIONAL_LATENCYf,
      SOC_PHY_FLD_DATAPATH_SHIFT_ENABLEf,
      SOC_PHY_FLD_DATA_SOURCEf,
      SOC_PHY_FLD_DCOUNTf,
      SOC_PHY_FLD_DDR4_CK_PATTERNf,
      SOC_PHY_FLD_DDR4_GLUE_RESET_Nf,
      SOC_PHY_FLD_DQ_BYTE0_RD2_2G_DELAY_DECf,
      SOC_PHY_FLD_DQ_BYTE0_RD2_2G_DELAY_INCf,
      SOC_PHY_FLD_DQ_BYTE0_RD2_2G_DELAY_IN_USEf,
      SOC_PHY_FLD_DQ_BYTE0_RD2_2G_SELECTf,
      SOC_PHY_FLD_DQ_BYTE0_WRITE_ENABLEf,
      SOC_PHY_FLD_DQ_BYTE1_RD2_2G_DELAY_DECf,
      SOC_PHY_FLD_DQ_BYTE1_RD2_2G_DELAY_INCf,
      SOC_PHY_FLD_DQ_BYTE1_RD2_2G_DELAY_IN_USEf,
      SOC_PHY_FLD_DQ_BYTE1_RD2_2G_SELECTf,
      SOC_PHY_FLD_DQ_BYTE1_WRITE_ENABLEf,
      SOC_PHY_FLD_DQ_BYTE2_RD2_2G_DELAY_DECf,
      SOC_PHY_FLD_DQ_BYTE2_RD2_2G_DELAY_INCf,
      SOC_PHY_FLD_DQ_BYTE2_RD2_2G_DELAY_IN_USEf,
      SOC_PHY_FLD_DQ_BYTE2_RD2_2G_SELECTf,
      SOC_PHY_FLD_DQ_BYTE2_WRITE_ENABLEf,
      SOC_PHY_FLD_DQ_BYTE3_RD2_2G_DELAY_DECf,
      SOC_PHY_FLD_DQ_BYTE3_RD2_2G_DELAY_INCf,
      SOC_PHY_FLD_DQ_BYTE3_RD2_2G_DELAY_IN_USEf,
      SOC_PHY_FLD_DQ_BYTE3_RD2_2G_SELECTf,
      SOC_PHY_FLD_DQ_BYTE3_WRITE_ENABLEf,
      SOC_PHY_FLD_DRC_1G_RESET_Nf,
      SOC_PHY_FLD_ENABLEf,
      SOC_PHY_FLD_EN_NLDL_CLKOUT_BARf,
      SOC_PHY_FLD_ERR1_CLEARf,
      SOC_PHY_FLD_ERR2_CLEARf,
      SOC_PHY_FLD_ERRORf,
      SOC_PHY_FLD_EXP_RCMD_IDf,
      SOC_PHY_FLD_FREE_RUNNING_MODEf,
      SOC_PHY_FLD_FREQ_CNTR_FC_RESET_Nf,
      SOC_PHY_FLD_FREQ_CNTR_RO_RESET_Nf,
      SOC_PHY_FLD_GDDR5_CK_PATTERNf,
      SOC_PHY_FLD_GDDR5_MODEf,
      SOC_PHY_FLD_IB_VDL_LOAD_VALUEf,
      SOC_PHY_FLD_IB_VDL_VALUEf,
      SOC_PHY_FLD_ID4f,
      SOC_PHY_FLD_ID8f,
      SOC_PHY_FLD_INIT_LOCK_OPTIONSf,
      SOC_PHY_FLD_INIT_LOCK_STATUSf,
      SOC_PHY_FLD_INIT_LOCK_TRANSITIONf,
      SOC_PHY_FLD_I_VDL_LOAD_VALUEf,
      SOC_PHY_FLD_I_VDL_VALUEf,
      SOC_PHY_FLD_LOCK_STATUSf,
      SOC_PHY_FLD_MAJORf,
      SOC_PHY_FLD_MANUAL_OVERRIDE_ENf,
      SOC_PHY_FLD_MAX_VDL_STEPf,
      SOC_PHY_FLD_MAX_WCOUNTf,
      SOC_PHY_FLD_MINORf,
      SOC_PHY_FLD_MIN_VDL_STEPf,
      SOC_PHY_FLD_NCOMP_CODE_2COREf,
      SOC_PHY_FLD_NCOMP_DINf,
      SOC_PHY_FLD_NCOMP_ENB_2COREf,
      SOC_PHY_FLD_NCOMP_INIT_CODEf,
      SOC_PHY_FLD_NDf,
      SOC_PHY_FLD_NDONE_2COREf,
      SOC_PHY_FLD_NTERMf,
      SOC_PHY_FLD_NXT_RCMD_FIFO_WDATA0f,
      SOC_PHY_FLD_NXT_RCMD_FIFO_WDATA1f,
      SOC_PHY_FLD_NXT_RCMD_FIFO_WR0f,
      SOC_PHY_FLD_NXT_RCMD_FIFO_WR1f,
      SOC_PHY_FLD_NXT_RD_EN_UI01f,
      SOC_PHY_FLD_NXT_RD_EN_UI23f,
      SOC_PHY_FLD_NXT_STATEf,
      SOC_PHY_FLD_N_VDL_LOAD_VALUEf,
      SOC_PHY_FLD_N_VDL_VALUEf,
      SOC_PHY_FLD_OBS_INTERVALf,
      SOC_PHY_FLD_OBS_RCMD_IDf,
      SOC_PHY_FLD_OVERRIDE_ENf,
      SOC_PHY_FLD_OVERRIDE_MODEf,
      SOC_PHY_FLD_OVERRIDE_VALUEf,
      SOC_PHY_FLD_PAST_STATE0f,
      SOC_PHY_FLD_PAST_STATE1f,
      SOC_PHY_FLD_PAST_STATE2f,
      SOC_PHY_FLD_PAST_STATE3f,
      SOC_PHY_FLD_PAST_STATE4f,
      SOC_PHY_FLD_PAST_STATE5f,
      SOC_PHY_FLD_PAST_STATE6f,
      SOC_PHY_FLD_PAST_STATE7f,
      SOC_PHY_FLD_PCOMP_CODE_2COREf,
      SOC_PHY_FLD_PCOMP_DINf,
      SOC_PHY_FLD_PCOMP_ENB_2COREf,
      SOC_PHY_FLD_PCOMP_INIT_CODEf,
      SOC_PHY_FLD_PDf,
      SOC_PHY_FLD_PDONE_2COREf,
      SOC_PHY_FLD_PHY_1G_RESET_Nf,
      SOC_PHY_FLD_PHY_2G_RESET_Nf,
      SOC_PHY_FLD_PNCOMP_INIT_DIFFf,
      SOC_PHY_FLD_POWERSAVE_ENf,
      SOC_PHY_FLD_PTERMf,
      SOC_PHY_FLD_PWRDNf,
      SOC_PHY_FLD_P_VDL_LOAD_VALUEf,
      SOC_PHY_FLD_P_VDL_VALUEf,
      SOC_PHY_FLD_Q_VDL_LOAD_VALUEf,
      SOC_PHY_FLD_Q_VDL_VALUEf,
      SOC_PHY_FLD_RCMD_ADDITIONAL_LATENCYf,
      SOC_PHY_FLD_RCMD_FIFO_RDf,
      SOC_PHY_FLD_RCMD_FIFO_RDATAf,
      SOC_PHY_FLD_RCMD_FIFO_RESET_Nf,
      SOC_PHY_FLD_RCMD_PAIRf,
      SOC_PHY_FLD_RCMD_SHIFT_ENABLEf,
      SOC_PHY_FLD_RD2_2G_DELAYf,
      SOC_PHY_FLD_RD_2G_DELAYf,
      SOC_PHY_FLD_RD_2G_DELAY_DECf,
      SOC_PHY_FLD_RD_2G_DELAY_INCf,
      SOC_PHY_FLD_RD_DELAYf,
      SOC_PHY_FLD_RD_EN_UI01f,
      SOC_PHY_FLD_RD_EN_UI23f,
      SOC_PHY_FLD_RD_SELf,
      SOC_PHY_FLD_READ_FIFO_RESET_Nf,
      SOC_PHY_FLD_READ_FSM_CLOCK_SOURCEf,
      SOC_PHY_FLD_REF_CTRLf,
      SOC_PHY_FLD_REF_EXTf,
      SOC_PHY_FLD_REF_SEL_EXTf,
      SOC_PHY_FLD_RESCAL_RESET_Nf,
      SOC_PHY_FLD_RESERVEDf,
      SOC_PHY_FLD_RO_OVERFLOWf,
      SOC_PHY_FLD_RO_UCOUNTf,
      SOC_PHY_FLD_RO_VDL_STEPf,
      SOC_PHY_FLD_RPf,
      SOC_PHY_FLD_RP0f,
      SOC_PHY_FLD_RP0_XMSBf,
      SOC_PHY_FLD_RP1f,
      SOC_PHY_FLD_RP1_XMSBf,
      SOC_PHY_FLD_RP_1Gf,
      SOC_PHY_FLD_RP_1G_XMSBf,
      SOC_PHY_FLD_RP_2Gf,
      SOC_PHY_FLD_RP_2G_XMSBf,
      SOC_PHY_FLD_RP_XMSBf,
      SOC_PHY_FLD_RXENBf,
      SOC_PHY_FLD_RXENB_ALERT_Nf,
      SOC_PHY_FLD_RX_MODEf,
      SOC_PHY_FLD_SEL_FC_REFCLKf,
      SOC_PHY_FLD_SLEWf,
      SOC_PHY_FLD_START_OBSf,
      SOC_PHY_FLD_STATEf,
      SOC_PHY_FLD_TEST_PIN_DIV_SELf,
      SOC_PHY_FLD_TX_MODEf,
      SOC_PHY_FLD_UI_SHIFTf,
      SOC_PHY_FLD_UPDATE_GAPf,
      SOC_PHY_FLD_UPDATE_MODEf,
      SOC_PHY_FLD_VDL_LOADf,
      SOC_PHY_FLD_VDL_SWITCHf,
      SOC_PHY_FLD_VDL_VALUE_CAPf,
      SOC_PHY_FLD_W2R_MIN_DELAY_2f,
      SOC_PHY_FLD_WCLK_SELf,
      SOC_PHY_FLD_WFULLf,
      SOC_PHY_FLD_WPf,
      SOC_PHY_FLD_WP0f,
      SOC_PHY_FLD_WP0_XMSBf,
      SOC_PHY_FLD_WP1f,
      SOC_PHY_FLD_WP1_XMSBf,
      SOC_PHY_FLD_WP_XMSBf,
      SOC_PHY_FLD_WRITE_ERRORf,
      SOC_PHY_FLD_WRITE_LEVELING_MODEf,
      SOC_PHY_DDRC28_NUM_FIELDS
  } soc_phy_ddrc28_fields_t;
  
  #include <soc/types.h>
  
  #ifndef SOC_RESET_VAL_DEC
  #    if !defined(SOC_NO_RESET_VALS)
  #        define SOC_RESET_VAL_DEC(_lo, _hi) _lo, _hi,
  #        define SOC_RESET_MASK_DEC(_lo, _hi) _lo, _hi,
  #    else
  #        define SOC_RESET_VAL_DEC(_lo, _hi)
  #        define SOC_RESET_MASK_DEC(_lo, _hi)
  #    endif
  #endif
  
  typedef enum soc_phy_ddrc28_reg_e {
      SOC_PHY_REG_AQ_IO_CONFIGr,
      SOC_PHY_REG_AQ_LDO_CONFIGr,
      SOC_PHY_REG_AQ_LOOPBACK_CONFIGr,
      SOC_PHY_REG_AQ_L_MACRO_RESERVED_REGr,
      SOC_PHY_REG_AQ_L_MAX_VDL_ADDRr,
      SOC_PHY_REG_AQ_L_MAX_VDL_CTRLr,
      SOC_PHY_REG_AQ_L_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_AQ_U_MACRO_RESERVED_REGr,
      SOC_PHY_REG_AQ_U_MAX_VDL_ADDRr,
      SOC_PHY_REG_AQ_U_MAX_VDL_CTRLr,
      SOC_PHY_REG_AQ_U_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_COMMON_CK_CONFIGr,
      SOC_PHY_REG_COMMON_IO_CONFIGr,
      SOC_PHY_REG_COMMON_LDO_CONFIGr,
      SOC_PHY_REG_COMMON_MACRO_RESERVED_REGr,
      SOC_PHY_REG_COMMON_MAX_VDL_CKr,
      SOC_PHY_REG_COMMON_RESCAL_INIT_CONFIGr,
      SOC_PHY_REG_COMMON_RESCAL_OPERATION_CONFIGr,
      SOC_PHY_REG_COMMON_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_COMMON_STATUS_RESCALr,
      SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr,
      SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr,
      SOC_PHY_REG_CONTROL_REGS_FREQ_CNTR_CONFIGr,
      SOC_PHY_REG_CONTROL_REGS_INPUT_SHIFT_CTRLr,
      SOC_PHY_REG_CONTROL_REGS_READ_CLOCK_CONFIGr,
      SOC_PHY_REG_CONTROL_REGS_READ_FIFO_CTRLr,
      SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr,
      SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr,
      SOC_PHY_REG_CONTROL_REGS_RESERVED_REGr,
      SOC_PHY_REG_CONTROL_REGS_RESET_CTRLr,
      SOC_PHY_REG_CONTROL_REGS_REVISIONr,
      SOC_PHY_REG_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr,
      SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr,
      SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr,
      SOC_PHY_REG_CONTROL_REGS_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_CONTROL_REGS_WRITE_FIFO_CTRLr,
      SOC_PHY_REG_DQ_BYTE0_CDR_IQ_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_CDR_OPERATION_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_CDR_PN_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_DATA_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_DQS_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_EDCEN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_LDO_R_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_LDO_W_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_MACRO_RESERVED_REGr,
      SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSNr,
      SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSPr,
      SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_FSMr,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_EDCr,
      SOC_PHY_REG_DQ_BYTE0_REN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_REN_GEN_ERR_CTRLr,
      SOC_PHY_REG_DQ_BYTE0_REN_STRETCH_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_IQ_VDLr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_OPERATIONr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_PN_VDLr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_EDCEN_FIFOr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_EDCRDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACHr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_RDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_REN_FIFOr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR1r,
      SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR2r,
      SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE0_STATUS_WRITE_LEVELINGr,
      SOC_PHY_REG_DQ_BYTE0_VREF_DAC_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_WRITE_LEVELING_CONFIGr,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DATAr,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DQSr,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_EDCr,
      SOC_PHY_REG_DQ_BYTE1_CDR_IQ_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_CDR_OPERATION_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_CDR_PN_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_DATA_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_DQS_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_EDCEN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_LDO_R_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_LDO_W_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_MACRO_RESERVED_REGr,
      SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSNr,
      SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSPr,
      SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_FSMr,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_EDCr,
      SOC_PHY_REG_DQ_BYTE1_REN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_REN_GEN_ERR_CTRLr,
      SOC_PHY_REG_DQ_BYTE1_REN_STRETCH_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_IQ_VDLr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_OPERATIONr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_PN_VDLr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_EDCEN_FIFOr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_EDCRDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACHr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_RDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_REN_FIFOr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR1r,
      SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR2r,
      SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE1_STATUS_WRITE_LEVELINGr,
      SOC_PHY_REG_DQ_BYTE1_VREF_DAC_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_WRITE_LEVELING_CONFIGr,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DATAr,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DQSr,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_EDCr,
      SOC_PHY_REG_DQ_BYTE2_CDR_IQ_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_CDR_OPERATION_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_CDR_PN_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_DATA_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_DQS_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_EDCEN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_LDO_R_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_LDO_W_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_MACRO_RESERVED_REGr,
      SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSNr,
      SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSPr,
      SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_FSMr,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_EDCr,
      SOC_PHY_REG_DQ_BYTE2_REN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_REN_GEN_ERR_CTRLr,
      SOC_PHY_REG_DQ_BYTE2_REN_STRETCH_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_IQ_VDLr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_OPERATIONr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_PN_VDLr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_EDCEN_FIFOr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_EDCRDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACHr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_RDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_REN_FIFOr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR1r,
      SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR2r,
      SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE2_STATUS_WRITE_LEVELINGr,
      SOC_PHY_REG_DQ_BYTE2_VREF_DAC_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_WRITE_LEVELING_CONFIGr,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DATAr,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DQSr,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_EDCr,
      SOC_PHY_REG_DQ_BYTE3_CDR_IQ_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_CDR_OPERATION_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_CDR_PN_VDL_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_DATA_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_DQS_IO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_EDCEN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_LDO_R_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_LDO_W_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_MACRO_RESERVED_REGr,
      SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSNr,
      SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSPr,
      SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_FSMr,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_EDCr,
      SOC_PHY_REG_DQ_BYTE3_REN_FIFO_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_REN_GEN_ERR_CTRLr,
      SOC_PHY_REG_DQ_BYTE3_REN_STRETCH_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_IQ_VDLr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_OPERATIONr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_PN_VDLr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_EDCEN_FIFOr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_EDCRDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_MACRO_RESERVEDr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACHr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_RDATA_FIFOr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_REN_FIFOr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR1r,
      SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR2r,
      SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr,
      SOC_PHY_REG_DQ_BYTE3_STATUS_WRITE_LEVELINGr,
      SOC_PHY_REG_DQ_BYTE3_VREF_DAC_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_WRITE_LEVELING_CONFIGr,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DATAr,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DQSr,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT0r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT1r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT2r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT3r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT4r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT5r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT6r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT7r,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_DBIr,
      SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_EDCr,
      SOC_PHY_DDRC28_NUM_REGS
  } soc_phy_ddrc28_reg_t;
  
  #define READ_DDRC28_AQ_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_AQ_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_AQ_LDO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_LDO_CONFIGr, instance, data)
  #define WRITE_DDRC28_AQ_LDO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_LDO_CONFIGr, instance, data)
  
  #define READ_DDRC28_AQ_LOOPBACK_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_LOOPBACK_CONFIGr, instance, data)
  #define WRITE_DDRC28_AQ_LOOPBACK_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_LOOPBACK_CONFIGr, instance, data)
  
  #define READ_DDRC28_AQ_L_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_MACRO_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_AQ_L_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_MACRO_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_AQ_L_MAX_VDL_ADDRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_MAX_VDL_ADDRr, instance, data)
  #define WRITE_DDRC28_AQ_L_MAX_VDL_ADDRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_MAX_VDL_ADDRr, instance, data)
  
  #define READ_DDRC28_AQ_L_MAX_VDL_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_MAX_VDL_CTRLr, instance, data)
  #define WRITE_DDRC28_AQ_L_MAX_VDL_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_MAX_VDL_CTRLr, instance, data)
  
  #define READ_DDRC28_AQ_L_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_AQ_L_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_AQ_U_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_MACRO_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_AQ_U_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_MACRO_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_AQ_U_MAX_VDL_ADDRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_MAX_VDL_ADDRr, instance, data)
  #define WRITE_DDRC28_AQ_U_MAX_VDL_ADDRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_MAX_VDL_ADDRr, instance, data)
  
  #define READ_DDRC28_AQ_U_MAX_VDL_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_MAX_VDL_CTRLr, instance, data)
  #define WRITE_DDRC28_AQ_U_MAX_VDL_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_MAX_VDL_CTRLr, instance, data)
  
  #define READ_DDRC28_AQ_U_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_AQ_U_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_COMMON_CK_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_CK_CONFIGr, instance, data)
  #define WRITE_DDRC28_COMMON_CK_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_CK_CONFIGr, instance, data)
  
  #define READ_DDRC28_COMMON_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_COMMON_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_COMMON_LDO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_LDO_CONFIGr, instance, data)
  #define WRITE_DDRC28_COMMON_LDO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_LDO_CONFIGr, instance, data)
  
  #define READ_DDRC28_COMMON_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_MACRO_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_COMMON_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_MACRO_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_COMMON_MAX_VDL_CKr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_MAX_VDL_CKr, instance, data)
  #define WRITE_DDRC28_COMMON_MAX_VDL_CKr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_MAX_VDL_CKr, instance, data)
  
  #define READ_DDRC28_COMMON_RESCAL_INIT_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_RESCAL_INIT_CONFIGr, instance, data)
  #define WRITE_DDRC28_COMMON_RESCAL_INIT_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_RESCAL_INIT_CONFIGr, instance, data)
  
  #define READ_DDRC28_COMMON_RESCAL_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_RESCAL_OPERATION_CONFIGr, instance, data)
  #define WRITE_DDRC28_COMMON_RESCAL_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_RESCAL_OPERATION_CONFIGr, instance, data)
  
  #define READ_DDRC28_COMMON_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_COMMON_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_COMMON_STATUS_RESCALr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_STATUS_RESCALr, instance, data)
  #define WRITE_DDRC28_COMMON_STATUS_RESCALr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_STATUS_RESCALr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_FREQ_CNTR_CONFIGr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_FREQ_CNTR_CONFIGr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_INPUT_SHIFT_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_INPUT_SHIFT_CTRLr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_INPUT_SHIFT_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_INPUT_SHIFT_CTRLr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_READ_CLOCK_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_READ_CLOCK_CONFIGr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_READ_CLOCK_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_READ_CLOCK_CONFIGr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_READ_FIFO_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_READ_FIFO_CTRLr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_READ_FIFO_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_READ_FIFO_CTRLr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_RESET_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_RESET_CTRLr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_RESET_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_RESET_CTRLr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_REVISIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_REVISIONr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_REVISIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_REVISIONr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_CONTROL_REGS_WRITE_FIFO_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_WRITE_FIFO_CTRLr, instance, data)
  #define WRITE_DDRC28_CONTROL_REGS_WRITE_FIFO_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_WRITE_FIFO_CTRLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_IQ_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_IQ_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_OPERATION_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_OPERATION_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_PN_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_PN_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_DATA_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_DATA_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_DQS_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_DQS_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_EDCEN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_EDCEN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_LDO_R_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_LDO_R_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_LDO_W_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_LDO_W_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_MACRO_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_MACRO_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSNr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSNr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSPr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSPr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_FSMr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_FSMr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_EDCr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_REN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_REN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_REN_GEN_ERR_CTRLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_REN_GEN_ERR_CTRLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_REN_STRETCH_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_REN_STRETCH_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_IQ_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_IQ_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_OPERATIONr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_OPERATIONr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_PN_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_PN_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCEN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCEN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCRDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCRDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACHr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACHr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_WRITE_LEVELINGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_WRITE_LEVELINGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_VREF_DAC_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_VREF_DAC_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_LEVELING_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_LEVELING_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DATAr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DATAr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DQSr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DQSr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_EDCr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_IQ_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_IQ_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_OPERATION_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_OPERATION_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_PN_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_PN_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_DATA_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_DATA_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_DQS_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_DQS_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_EDCEN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_EDCEN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_LDO_R_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_LDO_R_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_LDO_W_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_LDO_W_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_MACRO_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_MACRO_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSNr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSNr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSPr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSPr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_FSMr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_FSMr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_EDCr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_REN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_REN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_REN_GEN_ERR_CTRLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_REN_GEN_ERR_CTRLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_REN_STRETCH_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_REN_STRETCH_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_IQ_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_IQ_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_OPERATIONr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_OPERATIONr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_PN_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_PN_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCEN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCEN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCRDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCRDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACHr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACHr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_WRITE_LEVELINGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_WRITE_LEVELINGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_VREF_DAC_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_VREF_DAC_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_LEVELING_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_LEVELING_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DATAr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DATAr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DQSr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DQSr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_EDCr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_IQ_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_IQ_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_OPERATION_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_OPERATION_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_PN_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_PN_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_DATA_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_DATA_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_DQS_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_DQS_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_EDCEN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_EDCEN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_LDO_R_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_LDO_R_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_LDO_W_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_LDO_W_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_MACRO_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_MACRO_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSNr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSNr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSPr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSPr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_FSMr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_FSMr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_EDCr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_REN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_REN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_REN_GEN_ERR_CTRLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_REN_GEN_ERR_CTRLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_REN_STRETCH_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_REN_STRETCH_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_IQ_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_IQ_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_OPERATIONr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_OPERATIONr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_PN_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_PN_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCEN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCEN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCRDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCRDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACHr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACHr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_WRITE_LEVELINGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_WRITE_LEVELINGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_VREF_DAC_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_VREF_DAC_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_LEVELING_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_LEVELING_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DATAr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DATAr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DQSr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DQSr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_EDCr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_IQ_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_CDR_IQ_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_IQ_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_OPERATION_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_CDR_OPERATION_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_OPERATION_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_PN_VDL_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_CDR_PN_VDL_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_PN_VDL_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_DATA_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_DATA_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_DATA_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_DQS_IO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_DQS_IO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_DQS_IO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_EDCEN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_EDCEN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_EDCEN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_LDO_R_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_LDO_R_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_LDO_R_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_LDO_W_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_LDO_W_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_LDO_W_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_MACRO_RESERVED_REGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_MACRO_RESERVED_REGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_MACRO_RESERVED_REGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSNr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSNr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSNr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSPr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSPr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSPr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_FSMr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MAX_VDL_FSMr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_FSMr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_EDCr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_REN_FIFO_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_REN_FIFO_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_REN_FIFO_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_REN_GEN_ERR_CTRLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_REN_GEN_ERR_CTRLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_REN_GEN_ERR_CTRLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_REN_STRETCH_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_REN_STRETCH_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_REN_STRETCH_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_IQ_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_CDR_IQ_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_IQ_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_OPERATIONr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_CDR_OPERATIONr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_OPERATIONr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_PN_VDLr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_CDR_PN_VDLr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_PN_VDLr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCEN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_EDCEN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCEN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCRDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_EDCRDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCRDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_MACRO_RESERVEDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_MACRO_RESERVEDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_MACRO_RESERVEDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACHr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACHr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACHr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RDATA_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_RDATA_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RDATA_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_FIFOr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_FIFOr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_FIFOr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_WRITE_LEVELINGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_STATUS_WRITE_LEVELINGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_WRITE_LEVELINGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_VREF_DAC_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_VREF_DAC_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_VREF_DAC_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_LEVELING_CONFIGr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_LEVELING_CONFIGr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_LEVELING_CONFIGr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DATAr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DATAr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DQSr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DQSr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT0r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT0r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT0r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT1r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT1r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT1r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT2r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT2r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT2r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT3r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT3r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT3r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT4r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT4r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT4r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT5r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT5r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT5r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT6r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT6r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT6r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT7r, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT7r(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT7r, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_DBIr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_DBIr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_DBIr, instance, data)
  
  #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_EDCr, instance, data)
  #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_EDCr(unit, instance, data) \
      soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_EDCr, instance, data)
  
  
  #endif /* _SOC_PHY_DDRC28_H */
  