text: # -*- coding: utf-8 -*-
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  # Copyright (c) 2014, Regents of the University of California
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  from __future__ import (absolute_import, division,
                          print_function, unicode_literals)
  # noinspection PyUnresolvedReferences,PyCompatibility
  from builtins import *
  
  import os
  import pkg_resources
  import math
  
  from bag.design import Module
  
  
  yaml_file = pkg_resources.resource_filename(__name__, os.path.join('netlist_info', 'cap_sw_array.yaml'))
  
  
  # noinspection PyPep8Naming
  class clk_dis_templates__cap_sw_array(Module):
      """Module for library clk_dis_templates cell cap_sw_array.
  
      Fill in high level description here.
      """
  
      def __init__(self, bag_config, parent=None, prj=None, **kwargs):
          Module.__init__(self, bag_config, yaml_file, parent=parent, prj=prj, **kwargs)
  
      def design(self, num_bits, lch, pw, nw, m, device_intent='fast'):
  
          """To be overridden by subclasses to design this module.
  
          This method should fill in values for all parameters in
          self.parameters.  To design instances of this module, you can
          call their design() method or any other ways you coded.
  
          To modify schematic structure, call:
  
          rename_pin()
          delete_instance()
          replace_instance_master()
          reconnect_instance_terminal()
          restore_instance()
          array_instance()
          """
          self.parameters['num_bits'] = num_bits
          self.parameters['lch'] = lch
          self.parameters['pw'] = pw
          self.parameters['nw'] = nw
          self.parameters['m'] = m
          self.parameters['device_intent'] = device_intent
          name_list=[]
          term_list=[]
          
          for i in range(num_bits):
  
              in_pin = 'EN<%d>'%i
              out_pin = 'VO<%d>'%i
              vss_pin = 'VSS'
              vdd_pin = 'VDD'
  
              for j in range (2**i):
                  term_list.append({'EN': in_pin, 'VO':out_pin, 'VSS':vss_pin, 'VDD':vdd_pin})
                  name_list.append('I%d_%d'%(i, j))
  
          self.array_instance('I0', name_list, term_list=term_list)
          self.rename_pin('EN','EN<%d:0>'%(num_bits-1))
          self.rename_pin('VO','VO<%d:0>'%(num_bits-1))
          
          for inst in self.instances['I0']:
              inst.design(lch=lch, pw=pw, nw=nw, m=m, device_intent=device_intent)
  
  
      
  
      def get_layout_params(self, **kwargs):
          """Returns a dictionary with layout parameters.
  
          This method computes the layout parameters used to generate implementation's
          layout.  Subclasses should override this method if you need to run post-extraction
          layout.
  
          Parameters
          ----------
          kwargs :
              any extra parameters you need to generate the layout parameters dictionary.
              Usually you specify layout-specific parameters here, like metal layers of
              input/output, customizable wire sizes, and so on.
  
          Returns
          -------
          params : dict[str, any]
              the layout parameters dictionary.
          """
          return {}
  
      def get_layout_pin_mapping(self):
          """Returns the layout pin mapping dictionary.
  
          This method returns a dictionary used to rename the layout pins, in case they are different
          than the schematic pins.
  
          Returns
          -------
          pin_mapping : dict[str, str]
              a dictionary from layout pin names to schematic pin names.
          """
          return {}
  