text: /**
   * \file
   *
   * \brief SAM3U clock configuration.
   *
   * Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries.
   *
   * \asf_license_start
   *
   * \page License
   *
   * Subject to your compliance with these terms, you may use Microchip
   * software and any derivatives exclusively with Microchip products.
   * It is your responsibility to comply with third party license terms applicable
   * to your use of third party software (including open source software) that
   * may accompany Microchip software.
   *
   * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
   * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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   * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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   * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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  /*
   * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
   */
  
  #ifndef CONF_CLOCK_H_INCLUDED
  #define CONF_CLOCK_H_INCLUDED
  
  // ===== System Clock (MCK) Source Options
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_RC
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_XTAL
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_BYPASS
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_4M_RC
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_8M_RC
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_12M_RC
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_XTAL
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_BYPASS
  #define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLLACK
  //#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_UPLLCK
  
  // ===== System Clock (MCK) Prescaler Options   (Fmck = Fsys / (SYSCLK_PRES))
  //#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_1
  #define CONFIG_SYSCLK_PRES          SYSCLK_PRES_2
  //#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_4
  //#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_8
  //#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_16
  //#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_32
  //#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_64
  //#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_3
  
  // ===== PLL0 (A) Options   (Fpll = (Fclk * PLL_mul) / PLL_div)
  // Use mul and div effective values here.
  #define CONFIG_PLL0_SOURCE          PLL_SRC_MAINCK_XTAL
  #define CONFIG_PLL0_MUL             16
  #define CONFIG_PLL0_DIV             1
  
  // ===== UPLL (UTMI) Hardware fixed at 480MHz.
  
  // ===== USB Clock Source fixed at UPLL.
  
  // ===== Target frequency (System clock)
  // - XTAL frequency: 12MHz
  // - System clock source: PLLA
  // - System clock prescaler: 2 (divided by 2)
  // - PLLA source: XTAL
  // - PLLA output: XTAL * 16 / 1
  // - System clock is: 12 * 16 / 1 / 2 = 96MHz
  // ===== Target frequency (USB Clock)
  // - USB clock source: UPLL
  // - UPLL frequency: 480MHz
  // - USB clock: 480MHz
  
  #endif /* CONF_CLOCK_H_INCLUDED */
  