text: /*
   * Copyright (c) 2019 Nuclei Limited. All rights reserved.
   *
   * SPDX-License-Identifier: Apache-2.0
   *
   * Licensed under the Apache License, Version 2.0 (the License); you may
   * not use this file except in compliance with the License.
   * You may obtain a copy of the License at
   *
   * www.apache.org/licenses/LICENSE-2.0
   *
   * Unless required by applicable law or agreed to in writing, software
   * distributed under the License is distributed on an AS IS BASIS, WITHOUT
   * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   * See the License for the specific language governing permissions and
   * limitations under the License.
   */
  #ifndef __RISCV_ENCODING_H__
  #define __RISCV_ENCODING_H__
  
  #include "riscv_bits.h"
  #ifdef __cplusplus
   extern "C" {
  #endif
  /**
   * \defgroup NMSIS_Core_CSR_Encoding    Core CSR Encodings
   * \ingroup  NMSIS_Core
   * \brief    NMSIS Core CSR Encodings
   * \details
   *
   * The following macros are used for CSR encodings
   *   @{
   */
  #define MSTATUS_UIE         0x00000001
  #define MSTATUS_SIE         0x00000002
  #define MSTATUS_HIE         0x00000004
  #define MSTATUS_MIE         0x00000008
  #define MSTATUS_UPIE        0x00000010
  #define MSTATUS_SPIE        0x00000020
  #define MSTATUS_HPIE        0x00000040
  #define MSTATUS_MPIE        0x00000080
  #define MSTATUS_SPP         0x00000100
  #define MSTATUS_MPP         0x00001800
  #define MSTATUS_FS          0x00006000
  #define MSTATUS_XS          0x00018000
  #define MSTATUS_MPRV        0x00020000
  #define MSTATUS_PUM         0x00040000
  #define MSTATUS_MXR         0x00080000
  #define MSTATUS_VM          0x1F000000
  #define MSTATUS32_SD        0x80000000
  #define MSTATUS64_SD        0x8000000000000000
  
  #define MSTATUS_FS_INITIAL  0x00002000
  #define MSTATUS_FS_CLEAN    0x00004000
  #define MSTATUS_FS_DIRTY    0x00006000
  
  #define SSTATUS_UIE         0x00000001
  #define SSTATUS_SIE         0x00000002
  #define SSTATUS_UPIE        0x00000010
  #define SSTATUS_SPIE        0x00000020
  #define SSTATUS_SPP         0x00000100
  #define SSTATUS_FS          0x00006000
  #define SSTATUS_XS          0x00018000
  #define SSTATUS_PUM         0x00040000
  #define SSTATUS32_SD        0x80000000
  #define SSTATUS64_SD        0x8000000000000000
  
  #define CSR_MCACHE_CTL_IE   0x00000001
  #define CSR_MCACHE_CTL_DE   0x00010000
  
  #define DCSR_XDEBUGVER      (3U<<30)
  #define DCSR_NDRESET        (1<<29)
  #define DCSR_FULLRESET      (1<<28)
  #define DCSR_EBREAKM        (1<<15)
  #define DCSR_EBREAKH        (1<<14)
  #define DCSR_EBREAKS        (1<<13)
  #define DCSR_EBREAKU        (1<<12)
  #define DCSR_STOPCYCLE      (1<<10)
  #define DCSR_STOPTIME       (1<<9)
  #define DCSR_CAUSE          (7<<6)
  #define DCSR_DEBUGINT       (1<<5)
  #define DCSR_HALT           (1<<3)
  #define DCSR_STEP           (1<<2)
  #define DCSR_PRV            (3<<0)
  
  #define DCSR_CAUSE_NONE     0
  #define DCSR_CAUSE_SWBP     1
  #define DCSR_CAUSE_HWBP     2
  #define DCSR_CAUSE_DEBUGINT 3
  #define DCSR_CAUSE_STEP     4
  #define DCSR_CAUSE_HALT     5
  
  #define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
  #define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
  #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
  
  #define MCONTROL_SELECT     (1<<19)
  #define MCONTROL_TIMING     (1<<18)
  #define MCONTROL_ACTION     (0x3f<<12)
  #define MCONTROL_CHAIN      (1<<11)
  #define MCONTROL_MATCH      (0xf<<7)
  #define MCONTROL_M          (1<<6)
  #define MCONTROL_H          (1<<5)
  #define MCONTROL_S          (1<<4)
  #define MCONTROL_U          (1<<3)
  #define MCONTROL_EXECUTE    (1<<2)
  #define MCONTROL_STORE      (1<<1)
  #define MCONTROL_LOAD       (1<<0)
  
  #define MCONTROL_TYPE_NONE      0
  #define MCONTROL_TYPE_MATCH     2
  
  #define MCONTROL_ACTION_DEBUG_EXCEPTION   0
  #define MCONTROL_ACTION_DEBUG_MODE        1
  #define MCONTROL_ACTION_TRACE_START       2
  #define MCONTROL_ACTION_TRACE_STOP        3
  #define MCONTROL_ACTION_TRACE_EMIT        4
  
  #define MCONTROL_MATCH_EQUAL     0
  #define MCONTROL_MATCH_NAPOT     1
  #define MCONTROL_MATCH_GE        2
  #define MCONTROL_MATCH_LT        3
  #define MCONTROL_MATCH_MASK_LOW  4
  #define MCONTROL_MATCH_MASK_HIGH 5
  
  #define MIP_SSIP            (1 << IRQ_S_SOFT)
  #define MIP_HSIP            (1 << IRQ_H_SOFT)
  #define MIP_MSIP            (1 << IRQ_M_SOFT)
  #define MIP_STIP            (1 << IRQ_S_TIMER)
  #define MIP_HTIP            (1 << IRQ_H_TIMER)
  #define MIP_MTIP            (1 << IRQ_M_TIMER)
  #define MIP_SEIP            (1 << IRQ_S_EXT)
  #define MIP_HEIP            (1 << IRQ_H_EXT)
  #define MIP_MEIP            (1 << IRQ_M_EXT)
  
  #define MIE_SSIE            MIP_SSIP
  #define MIE_HSIE            MIP_HSIP
  #define MIE_MSIE            MIP_MSIP
  #define MIE_STIE            MIP_STIP
  #define MIE_HTIE            MIP_HTIP
  #define MIE_MTIE            MIP_MTIP
  #define MIE_SEIE            MIP_SEIP
  #define MIE_HEIE            MIP_HEIP
  #define MIE_MEIE            MIP_MEIP
  
  #define WFE_WFE             0x1
  
  #define MCOUNTINHIBIT_IR    (1<<2)
  #define MCOUNTINHIBIT_CY    (1<<0)
  
  #define MMISC_CTL_NMI_CAUSE_FFF     (1<<9)
  #define MMISC_CTL_MISALIGN          (1<<6)
  #define MMISC_CTL_BPU               (1<<3)
  
  #define SIP_SSIP MIP_SSIP
  #define SIP_STIP MIP_STIP
  
  #define PRV_U 0
  #define PRV_S 1
  #define PRV_H 2
  #define PRV_M 3
  
  #define VM_MBARE 0
  #define VM_MBB   1
  #define VM_MBBID 2
  #define VM_SV32  8
  #define VM_SV39  9
  #define VM_SV48  10
  
  #define IRQ_S_SOFT   1
  #define IRQ_H_SOFT   2
  #define IRQ_M_SOFT   3
  #define IRQ_S_TIMER  5
  #define IRQ_H_TIMER  6
  #define IRQ_M_TIMER  7
  #define IRQ_S_EXT    9
  #define IRQ_H_EXT    10
  #define IRQ_M_EXT    11
  #define IRQ_COP      12
  #define IRQ_HOST     13
  
  #define DEFAULT_RSTVEC     0x00001000
  #define DEFAULT_NMIVEC     0x00001004
  #define DEFAULT_MTVEC      0x00001010
  #define CONFIG_STRING_ADDR 0x0000100C
  #define EXT_IO_BASE        0x40000000
  #define DRAM_BASE          0x80000000
  
  /* === FPU FRM Rounding Mode === */
  /** FPU Round to Nearest, ties to Even*/
  #define FRM_RNDMODE_RNE     0x0
  /** FPU Round Towards Zero */
  #define FRM_RNDMODE_RTZ     0x1
  /** FPU Round Down (towards -inf) */
  #define FRM_RNDMODE_RDN     0x2
  /** FPU Round Up (towards +inf) */
  #define FRM_RNDMODE_RUP     0x3
  /** FPU Round to nearest, ties to Max Magnitude */
  #define FRM_RNDMODE_RMM     0x4
  /**
   * In instruction's rm, selects dynamic rounding mode.
   * In Rounding Mode register, Invalid */
  #define FRM_RNDMODE_DYN     0x7
  
  /* === FPU FFLAGS Accrued Exceptions === */
  /** FPU Inexact */
  #define FFLAGS_AE_NX        (1<<0)
  /** FPU Underflow */
  #define FFLAGS_AE_UF        (1<<1)
  /** FPU Overflow */
  #define FFLAGS_AE_OF        (1<<2)
  /** FPU Divide by Zero */
  #define FFLAGS_AE_DZ        (1<<3)
  /** FPU Invalid Operation */
  #define FFLAGS_AE_NV        (1<<4)
  
  /** Floating Point Register f0-f31, eg. f0 -> FREG(0) */
  #define FREG(idx)           f##idx
  
  
  /* === PMP CFG Bits === */
  #define PMP_R				0x01
  #define PMP_W				0x02
  #define PMP_X				0x04
  #define PMP_A				0x18
  #define PMP_A_TOR			0x08
  #define PMP_A_NA4			0x10
  #define PMP_A_NAPOT			0x18
  #define PMP_L				0x80
  
  #define PMP_SHIFT			2
  #define PMP_COUNT			16
  
  // page table entry (PTE) fields
  #define PTE_V     0x001 // Valid
  #define PTE_R     0x002 // Read
  #define PTE_W     0x004 // Write
  #define PTE_X     0x008 // Execute
  #define PTE_U     0x010 // User
  #define PTE_G     0x020 // Global
  #define PTE_A     0x040 // Accessed
  #define PTE_D     0x080 // Dirty
  #define PTE_SOFT  0x300 // Reserved for Software
  
  #define PTE_PPN_SHIFT 10
  
  #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
  
  #ifdef __riscv
  
  #ifdef __riscv64
  # define MSTATUS_SD MSTATUS64_SD
  # define SSTATUS_SD SSTATUS64_SD
  # define RISCV_PGLEVEL_BITS 9
  #else
  # define MSTATUS_SD MSTATUS32_SD
  # define SSTATUS_SD SSTATUS32_SD
  # define RISCV_PGLEVEL_BITS 10
  #endif /* __riscv64 */
  
  #define RISCV_PGSHIFT 12
  #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
  
  #endif /* __riscv */
  
  #define DOWNLOAD_MODE_FLASHXIP  0
  #define DOWNLOAD_MODE_FLASH     1
  #define DOWNLOAD_MODE_ILM       2
  
  /**
   * \defgroup NMSIS_Core_CSR_Registers    Core CSR Registers
   * \ingroup  NMSIS_Core
   * \brief    NMSIS Core CSR Register Definitions
   * \details
   *
   * The following macros are used for CSR Register Defintions.
   *   @{
   */
  /* === Standard RISC-V CSR Registers === */
  #define CSR_USTATUS	0x0
  #define CSR_FFLAGS 0x1
  #define CSR_FRM 0x2
  #define CSR_FCSR 0x3
  #define CSR_CYCLE 0xc00
  #define CSR_TIME 0xc01
  #define CSR_INSTRET 0xc02
  #define CSR_HPMCOUNTER3 0xc03
  #define CSR_HPMCOUNTER4 0xc04
  #define CSR_HPMCOUNTER5 0xc05
  #define CSR_HPMCOUNTER6 0xc06
  #define CSR_HPMCOUNTER7 0xc07
  #define CSR_HPMCOUNTER8 0xc08
  #define CSR_HPMCOUNTER9 0xc09
  #define CSR_HPMCOUNTER10 0xc0a
  #define CSR_HPMCOUNTER11 0xc0b
  #define CSR_HPMCOUNTER12 0xc0c
  #define CSR_HPMCOUNTER13 0xc0d
  #define CSR_HPMCOUNTER14 0xc0e
  #define CSR_HPMCOUNTER15 0xc0f
  #define CSR_HPMCOUNTER16 0xc10
  #define CSR_HPMCOUNTER17 0xc11
  #define CSR_HPMCOUNTER18 0xc12
  #define CSR_HPMCOUNTER19 0xc13
  #define CSR_HPMCOUNTER20 0xc14
  #define CSR_HPMCOUNTER21 0xc15
  #define CSR_HPMCOUNTER22 0xc16
  #define CSR_HPMCOUNTER23 0xc17
  #define CSR_HPMCOUNTER24 0xc18
  #define CSR_HPMCOUNTER25 0xc19
  #define CSR_HPMCOUNTER26 0xc1a
  #define CSR_HPMCOUNTER27 0xc1b
  #define CSR_HPMCOUNTER28 0xc1c
  #define CSR_HPMCOUNTER29 0xc1d
  #define CSR_HPMCOUNTER30 0xc1e
  #define CSR_HPMCOUNTER31 0xc1f
  #define CSR_SSTATUS 0x100
  #define CSR_SIE 0x104
  #define CSR_STVEC 0x105
  #define CSR_SSCRATCH 0x140
  #define CSR_SEPC 0x141
  #define CSR_SCAUSE 0x142
  #define CSR_SBADADDR 0x143
  #define CSR_SIP 0x144
  #define CSR_SPTBR 0x180
  #define CSR_MSTATUS 0x300
  #define CSR_MISA 0x301
  #define CSR_MEDELEG 0x302
  #define CSR_MIDELEG 0x303
  #define CSR_MIE 0x304
  #define CSR_MTVEC 0x305
  #define CSR_MCOUNTEREN 0x306
  #define CSR_MSCRATCH 0x340
  #define CSR_MEPC 0x341
  #define CSR_MCAUSE 0x342
  #define CSR_MBADADDR 0x343
  #define CSR_MIP 0x344
  #define CSR_PMPCFG0	0x3a0
  #define CSR_PMPCFG1	0x3a1
  #define CSR_PMPCFG2	0x3a2
  #define CSR_PMPCFG3	0x3a3
  #define CSR_PMPADDR0 0x3b0
  #define CSR_PMPADDR1 0x3b1
  #define CSR_PMPADDR2 0x3b2
  #define CSR_PMPADDR3 0x3b3
  #define CSR_PMPADDR4 0x3b4
  #define CSR_PMPADDR5 0x3b5
  #define CSR_PMPADDR6 0x3b6
  #define CSR_PMPADDR7 0x3b7
  #define CSR_PMPADDR8 0x3b8
  #define CSR_PMPADDR9 0x3b9
  #define CSR_PMPADDR10 0x3ba
  #define CSR_PMPADDR11 0x3bb
  #define CSR_PMPADDR12 0x3bc
  #define CSR_PMPADDR13 0x3bd
  #define CSR_PMPADDR14 0x3be
  #define CSR_PMPADDR15 0x3bf
  #define CSR_TSELECT 0x7a0
  #define CSR_TDATA1 0x7a1
  #define CSR_TDATA2 0x7a2
  #define CSR_TDATA3 0x7a3
  #define CSR_DCSR 0x7b0
  #define CSR_DPC 0x7b1
  #define CSR_DSCRATCH 0x7b2
  #define CSR_MCYCLE 0xb00
  #define CSR_MINSTRET 0xb02
  #define CSR_MHPMCOUNTER3 0xb03
  #define CSR_MHPMCOUNTER4 0xb04
  #define CSR_MHPMCOUNTER5 0xb05
  #define CSR_MHPMCOUNTER6 0xb06
  #define CSR_MHPMCOUNTER7 0xb07
  #define CSR_MHPMCOUNTER8 0xb08
  #define CSR_MHPMCOUNTER9 0xb09
  #define CSR_MHPMCOUNTER10 0xb0a
  #define CSR_MHPMCOUNTER11 0xb0b
  #define CSR_MHPMCOUNTER12 0xb0c
  #define CSR_MHPMCOUNTER13 0xb0d
  #define CSR_MHPMCOUNTER14 0xb0e
  #define CSR_MHPMCOUNTER15 0xb0f
  #define CSR_MHPMCOUNTER16 0xb10
  #define CSR_MHPMCOUNTER17 0xb11
  #define CSR_MHPMCOUNTER18 0xb12
  #define CSR_MHPMCOUNTER19 0xb13
  #define CSR_MHPMCOUNTER20 0xb14
  #define CSR_MHPMCOUNTER21 0xb15
  #define CSR_MHPMCOUNTER22 0xb16
  #define CSR_MHPMCOUNTER23 0xb17
  #define CSR_MHPMCOUNTER24 0xb18
  #define CSR_MHPMCOUNTER25 0xb19
  #define CSR_MHPMCOUNTER26 0xb1a
  #define CSR_MHPMCOUNTER27 0xb1b
  #define CSR_MHPMCOUNTER28 0xb1c
  #define CSR_MHPMCOUNTER29 0xb1d
  #define CSR_MHPMCOUNTER30 0xb1e
  #define CSR_MHPMCOUNTER31 0xb1f
  #define CSR_MUCOUNTEREN 0x320
  #define CSR_MSCOUNTEREN 0x321
  #define CSR_MHPMEVENT3 0x323
  #define CSR_MHPMEVENT4 0x324
  #define CSR_MHPMEVENT5 0x325
  #define CSR_MHPMEVENT6 0x326
  #define CSR_MHPMEVENT7 0x327
  #define CSR_MHPMEVENT8 0x328
  #define CSR_MHPMEVENT9 0x329
  #define CSR_MHPMEVENT10 0x32a
  #define CSR_MHPMEVENT11 0x32b
  #define CSR_MHPMEVENT12 0x32c
  #define CSR_MHPMEVENT13 0x32d
  #define CSR_MHPMEVENT14 0x32e
  #define CSR_MHPMEVENT15 0x32f
  #define CSR_MHPMEVENT16 0x330
  #define CSR_MHPMEVENT17 0x331
  #define CSR_MHPMEVENT18 0x332
  #define CSR_MHPMEVENT19 0x333
  #define CSR_MHPMEVENT20 0x334
  #define CSR_MHPMEVENT21 0x335
  #define CSR_MHPMEVENT22 0x336
  #define CSR_MHPMEVENT23 0x337
  #define CSR_MHPMEVENT24 0x338
  #define CSR_MHPMEVENT25 0x339
  #define CSR_MHPMEVENT26 0x33a
  #define CSR_MHPMEVENT27 0x33b
  #define CSR_MHPMEVENT28 0x33c
  #define CSR_MHPMEVENT29 0x33d
  #define CSR_MHPMEVENT30 0x33e
  #define CSR_MHPMEVENT31 0x33f
  #define CSR_MVENDORID 0xf11
  #define CSR_MARCHID 0xf12
  #define CSR_MIMPID 0xf13
  #define CSR_MHARTID 0xf14
  #define CSR_CYCLEH 0xc80
  #define CSR_TIMEH 0xc81
  #define CSR_INSTRETH 0xc82
  #define CSR_HPMCOUNTER3H 0xc83
  #define CSR_HPMCOUNTER4H 0xc84
  #define CSR_HPMCOUNTER5H 0xc85
  #define CSR_HPMCOUNTER6H 0xc86
  #define CSR_HPMCOUNTER7H 0xc87
  #define CSR_HPMCOUNTER8H 0xc88
  #define CSR_HPMCOUNTER9H 0xc89
  #define CSR_HPMCOUNTER10H 0xc8a
  #define CSR_HPMCOUNTER11H 0xc8b
  #define CSR_HPMCOUNTER12H 0xc8c
  #define CSR_HPMCOUNTER13H 0xc8d
  #define CSR_HPMCOUNTER14H 0xc8e
  #define CSR_HPMCOUNTER15H 0xc8f
  #define CSR_HPMCOUNTER16H 0xc90
  #define CSR_HPMCOUNTER17H 0xc91
  #define CSR_HPMCOUNTER18H 0xc92
  #define CSR_HPMCOUNTER19H 0xc93
  #define CSR_HPMCOUNTER20H 0xc94
  #define CSR_HPMCOUNTER21H 0xc95
  #define CSR_HPMCOUNTER22H 0xc96
  #define CSR_HPMCOUNTER23H 0xc97
  #define CSR_HPMCOUNTER24H 0xc98
  #define CSR_HPMCOUNTER25H 0xc99
  #define CSR_HPMCOUNTER26H 0xc9a
  #define CSR_HPMCOUNTER27H 0xc9b
  #define CSR_HPMCOUNTER28H 0xc9c
  #define CSR_HPMCOUNTER29H 0xc9d
  #define CSR_HPMCOUNTER30H 0xc9e
  #define CSR_HPMCOUNTER31H 0xc9f
  #define CSR_MCYCLEH 0xb80
  #define CSR_MINSTRETH 0xb82
  #define CSR_MHPMCOUNTER3H 0xb83
  #define CSR_MHPMCOUNTER4H 0xb84
  #define CSR_MHPMCOUNTER5H 0xb85
  #define CSR_MHPMCOUNTER6H 0xb86
  #define CSR_MHPMCOUNTER7H 0xb87
  #define CSR_MHPMCOUNTER8H 0xb88
  #define CSR_MHPMCOUNTER9H 0xb89
  #define CSR_MHPMCOUNTER10H 0xb8a
  #define CSR_MHPMCOUNTER11H 0xb8b
  #define CSR_MHPMCOUNTER12H 0xb8c
  #define CSR_MHPMCOUNTER13H 0xb8d
  #define CSR_MHPMCOUNTER14H 0xb8e
  #define CSR_MHPMCOUNTER15H 0xb8f
  #define CSR_MHPMCOUNTER16H 0xb90
  #define CSR_MHPMCOUNTER17H 0xb91
  #define CSR_MHPMCOUNTER18H 0xb92
  #define CSR_MHPMCOUNTER19H 0xb93
  #define CSR_MHPMCOUNTER20H 0xb94
  #define CSR_MHPMCOUNTER21H 0xb95
  #define CSR_MHPMCOUNTER22H 0xb96
  #define CSR_MHPMCOUNTER23H 0xb97
  #define CSR_MHPMCOUNTER24H 0xb98
  #define CSR_MHPMCOUNTER25H 0xb99
  #define CSR_MHPMCOUNTER26H 0xb9a
  #define CSR_MHPMCOUNTER27H 0xb9b
  #define CSR_MHPMCOUNTER28H 0xb9c
  #define CSR_MHPMCOUNTER29H 0xb9d
  #define CSR_MHPMCOUNTER30H 0xb9e
  #define CSR_MHPMCOUNTER31H 0xb9f
  
  /* === CLIC CSR Registers === */
  #define CSR_MTVT                0x307
  #define CSR_MNXTI               0x345
  #define CSR_MINTSTATUS          0x346
  #define CSR_MSCRATCHCSW         0x348
  #define CSR_MSCRATCHCSWL        0x349
  #define CSR_MCLICBASE           0x350
  
  /* === Nuclei custom CSR Registers === */
  #define CSR_MCOUNTINHIBIT       0x320
  #define CSR_MNVEC               0x7C3
  #define CSR_MSUBM               0x7C4
  #define CSR_MDCAUSE             0x7C9
  #define CSR_MCACHE_CTL          0x7CA
  #define CSR_MMISC_CTL           0x7D0
  #define CSR_MSAVESTATUS         0x7D6
  #define CSR_MSAVEEPC1           0x7D7
  #define CSR_MSAVECAUSE1         0x7D8
  #define CSR_MSAVEEPC2           0x7D9
  #define CSR_MSAVECAUSE2         0x7DA
  #define CSR_MSAVEDCAUSE1        0x7DB
  #define CSR_MSAVEDCAUSE2        0x7DC
  #define CSR_PUSHMSUBM           0x7EB
  #define CSR_MTVT2               0x7EC
  #define CSR_JALMNXTI            0x7ED
  #define CSR_PUSHMCAUSE          0x7EE
  #define CSR_PUSHMEPC            0x7EF
  #define CSR_SLEEPVALUE          0x811
  #define CSR_TXEVT               0x812
  #define CSR_WFE                 0x810
  
  /** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Registers **/
  
  /* Exception Code in MCAUSE CSR */
  #define CAUSE_MISALIGNED_FETCH 0x0
  #define CAUSE_FAULT_FETCH 0x1
  #define CAUSE_ILLEGAL_INSTRUCTION 0x2
  #define CAUSE_BREAKPOINT 0x3
  #define CAUSE_MISALIGNED_LOAD 0x4
  #define CAUSE_FAULT_LOAD 0x5
  #define CAUSE_MISALIGNED_STORE 0x6
  #define CAUSE_FAULT_STORE 0x7
  #define CAUSE_USER_ECALL 0x8
  #define CAUSE_SUPERVISOR_ECALL 0x9
  #define CAUSE_HYPERVISOR_ECALL 0xa
  #define CAUSE_MACHINE_ECALL 0xb
  
  /* Exception Subcode in MDCAUSE CSR */
  #define DCAUSE_FAULT_FETCH_PMP      0x1
  #define DCAUSE_FAULT_FETCH_INST     0x2
  
  #define DCAUSE_FAULT_LOAD_PMP       0x1
  #define DCAUSE_FAULT_LOAD_INST      0x2
  #define DCAUSE_FAULT_LOAD_NICE      0x3
  
  #define DCAUSE_FAULT_STORE_PMP      0x1
  #define DCAUSE_FAULT_STORE_INST     0x2
  
  /** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Encoding **/
  
  #ifdef __cplusplus
  }
  #endif
  #endif /* __RISCV_ENCODING_H__ */
  