text: /*
   * Copyright (C) 2017 Freie Universität Berlin
   *               2017 Inria
   *
   * This file is subject to the terms and conditions of the GNU Lesser
   * General Public License v2.1. See the file LICENSE in the top level
   * directory for more details.
   */
  
  /**
   * @defgroup    boards_nucleo-l053r8 STM32 Nucleo-L053R8
   * @ingroup     boards_common_nucleo64
   * @brief       Support for the STM32 Nucleo-L053R8
   * @{
   *
   * @file
   * @brief       Peripheral MCU configuration for the nucleo-l053r8 board
   *
   * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
   * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
   */
  
  #ifndef PERIPH_CONF_H
  #define PERIPH_CONF_H
  
  #include "periph_cpu.h"
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * @name    Clock system configuration
   * @{
   */
  #define CLOCK_HSI           (16000000U)         /* internal oscillator */
  #define CLOCK_CORECLOCK     (32000000U)         /* desired core clock frequency */
  
  /* configuration of PLL prescaler and multiply values */
  /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
  #define CLOCK_PLL_DIV       RCC_CFGR_PLLDIV2
  #define CLOCK_PLL_MUL       RCC_CFGR_PLLMUL4
  /* configuration of peripheral bus clock prescalers */
  #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1      /* AHB clock -> 32MHz */
  #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* APB2 clock -> 32MHz */
  #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV1     /* APB1 clock -> 32MHz */
  /* configuration of flash access cycles */
  #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
  
  /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
  #define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
  #define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
  #define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
  /** @} */
  
  /**
   * @name    Timer configuration
   * @{
   */
  static const timer_conf_t timer_config[] = {
      {
          .dev      = TIM2,
          .max      = 0x0000ffff,
          .rcc_mask = RCC_APB1ENR_TIM2EN,
          .bus      = APB1,
          .irqn     = TIM2_IRQn
      }
  };
  
  #define TIMER_0_ISR         isr_tim2
  
  #define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
  /** @} */
  
  /**
   * @name    UART configuration
   * @{
   */
  static const uart_conf_t uart_config[] = {
      {
          .dev        = USART2,
          .rcc_mask   = RCC_APB1ENR_USART2EN,
          .rx_pin     = GPIO_PIN(PORT_A, 3),
          .tx_pin     = GPIO_PIN(PORT_A, 2),
          .rx_af      = GPIO_AF4,
          .tx_af      = GPIO_AF4,
          .bus        = APB1,
          .irqn       = USART2_IRQn
      },
      {
          .dev        = USART1,
          .rcc_mask   = RCC_APB2ENR_USART1EN,
          .rx_pin     = GPIO_PIN(PORT_A, 10),
          .tx_pin     = GPIO_PIN(PORT_A, 9),
          .rx_af      = GPIO_AF4,
          .tx_af      = GPIO_AF4,
          .bus        = APB2,
          .irqn       = USART1_IRQn
      }
  };
  
  #define UART_0_ISR          (isr_usart2)
  #define UART_1_ISR          (isr_usart1)
  
  #define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
  /** @} */
  
  /**
   * @name    PWM configuration
   * @{
   */
  static const pwm_conf_t pwm_config[] = {
      {
          .dev      = TIM22,
          .rcc_mask = RCC_APB2ENR_TIM22EN,
          .chan     = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
                        { .pin = GPIO_PIN(PORT_B, 5),          .cc_chan = 1 },
                        { .pin = GPIO_UNDEF,                   .cc_chan = 0 },
                        { .pin = GPIO_UNDEF,                   .cc_chan = 0 } },
          .af       = GPIO_AF4,
          .bus      = APB2
      }
  };
  
  #define PWM_NUMOF           (sizeof(pwm_config) / sizeof(pwm_config[0]))
  /** @} */
  
  /**
   * @name    SPI configuration
   *
   * @note    The spi_divtable is auto-generated from
   *          `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
   * @{
   */
  static const uint8_t spi_divtable[2][5] = {
      {       /* for APB1 @ 32000000Hz */
          7,  /* -> 125000Hz */
          5,  /* -> 500000Hz */
          4,  /* -> 1000000Hz */
          2,  /* -> 4000000Hz */
          1   /* -> 8000000Hz */
      },
      {       /* for APB2 @ 32000000Hz */
          7,  /* -> 125000Hz */
          5,  /* -> 500000Hz */
          4,  /* -> 1000000Hz */
          2,  /* -> 4000000Hz */
          1   /* -> 8000000Hz */
      }
  };
  
  static const spi_conf_t spi_config[] = {
      {
          .dev      = SPI1,
          .mosi_pin = GPIO_PIN(PORT_A, 7),
          .miso_pin = GPIO_PIN(PORT_A, 6),
          .sclk_pin = GPIO_PIN(PORT_A, 5),
          .cs_pin   = GPIO_UNDEF,
          .af       = GPIO_AF0,
          .rccmask  = RCC_APB2ENR_SPI1EN,
          .apbbus   = APB2
      }
  };
  
  #define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
  /** @} */
  
  /**
   * @name    ADC configuration
   * @{
   */
  #define ADC_NUMOF           (0)
  /** @} */
  
  /**
   * @name    RTC configuration
   * @{
   */
  #define RTC_NUMOF           (1U)
  /** @} */
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* PERIPH_CONF_H */
  /** @} */
  