text: /*
   * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
  
  #include <common.h>
  #include <asm/io.h>
  #include <asm/arch/imx-regs.h>
  #include <asm/arch/mx6-pins.h>
  #include <asm/arch/clock.h>
  #include <asm/errno.h>
  #include <asm/gpio.h>
  #include <asm/imx-common/iomux-v3.h>
  #include <mmc.h>
  #include <fsl_esdhc.h>
  #include <miiphy.h>
  #include <netdev.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
  #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  
  #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
  	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  
  #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  
  int dram_init(void)
  {
  #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
  	defined(CONFIG_DDR_32BIT)
  	gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
  #else
  	gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
  #endif
  
  	return 0;
  }
  
  iomux_v3_cfg_t const uart4_pads[] = {
  	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  
  iomux_v3_cfg_t const usdhc3_pads[] = {
  	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_NANDF_CS0__GPIO6_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  };
  
  iomux_v3_cfg_t const usdhc4_pads[] = {
  	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  };
  
  iomux_v3_cfg_t const enet_pads[] = {
  	MX6_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  };
  
  
  static void setup_iomux_uart(void)
  {
  	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  }
  
  static void setup_iomux_enet(void)
  {
  	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  }
  
  #ifdef CONFIG_FSL_ESDHC
  struct fsl_esdhc_cfg usdhc_cfg[2] = {
  	{USDHC3_BASE_ADDR},
  	{USDHC4_BASE_ADDR},
  };
  
  int board_mmc_getcd(struct mmc *mmc)
  {
  	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  	int ret;
  
  	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  		gpio_direction_input(IMX_GPIO_NR(6, 11));
  		ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
  	} else /* Don't have the CD GPIO pin on board */
  		ret = 1;
  
  	return ret;
  }
  
  int board_mmc_init(bd_t *bis)
  {
  	s32 status = 0;
  	u32 index = 0;
  
  	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  
  	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  		switch (index) {
  		case 0:
  			imx_iomux_v3_setup_multiple_pads(
  				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  			break;
  		case 1:
  			imx_iomux_v3_setup_multiple_pads(
  				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  			break;
  		default:
  			printf("Warning: you configured more USDHC controllers"
  				"(%d) then supported by the board (%d)\n",
  				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  			return status;
  		}
  
  		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  	}
  
  	return status;
  }
  #endif
  
  #define MII_MMD_ACCESS_CTRL_REG		0xd
  #define MII_MMD_ACCESS_ADDR_DATA_REG	0xe
  #define MII_DBG_PORT_REG		0x1d
  #define MII_DBG_PORT2_REG		0x1e
  
  int fecmxc_mii_postcall(int phy)
  {
  	unsigned short val;
  
  	/*
  	 * Due to the i.MX6Q Armadillo2 board HW design,there is
  	 * no 125Mhz clock input from SOC. In order to use RGMII,
  	 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
  	 */
  	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
  	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
  	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
  	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
  	val &= 0xffe3;
  	val |= 0x18;
  	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
  
  	/* For the RGMII phy, we need enable tx clock delay */
  	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
  	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
  	val |= 0x0100;
  	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
  
  	miiphy_write("FEC", phy, MII_BMCR, 0xa100);
  
  	return 0;
  }
  
  int board_eth_init(bd_t *bis)
  {
  	struct eth_device *dev;
  	int ret = cpu_eth_init(bis);
  
  	if (ret)
  		return ret;
  
  	dev = eth_get_dev_by_name("FEC");
  	if (!dev) {
  		printf("FEC MXC: Unable to get FEC device entry\n");
  		return -EINVAL;
  	}
  
  	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
  	if (ret) {
  		printf("FEC MXC: Unable to register FEC mii postcall\n");
  		return ret;
  	}
  
  	return 0;
  }
  
  int board_early_init_f(void)
  {
  	setup_iomux_uart();
  	setup_iomux_enet();
  
  	return 0;
  }
  
  int board_init(void)
  {
  	/* address of boot parameters */
  	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  
  	return 0;
  }
  
  int checkboard(void)
  {
  #ifdef CONFIG_MX6DL
  	puts("Board: MX6DL-Armadillo2\n");
  #else
  	puts("Board: MX6Q-Armadillo2\n");
  #endif
  
  	return 0;
  }
  