text: DECL|AutomaticOutput|member|uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
  DECL|Autoreload|member|uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
  DECL|BreakPolarity|member|uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
  DECL|BreakState|member|uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
  DECL|ClockDivision|member|uint32_t ClockDivision; /*!< Specifies the clock division.
  DECL|CommutationDelay|member|uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
  DECL|CompareValue|member|uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
  DECL|CounterMode|member|uint32_t CounterMode; /*!< Specifies the counter mode.
  DECL|DT_DELAY_1|macro|DT_DELAY_1
  DECL|DT_DELAY_2|macro|DT_DELAY_2
  DECL|DT_DELAY_3|macro|DT_DELAY_3
  DECL|DT_DELAY_4|macro|DT_DELAY_4
  DECL|DT_RANGE_1|macro|DT_RANGE_1
  DECL|DT_RANGE_2|macro|DT_RANGE_2
  DECL|DT_RANGE_3|macro|DT_RANGE_3
  DECL|DT_RANGE_4|macro|DT_RANGE_4
  DECL|DeadTime|member|uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
  DECL|EncoderMode|member|uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
  DECL|IC1ActiveInput|member|uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
  DECL|IC1Filter|member|uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
  DECL|IC1Filter|member|uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
  DECL|IC1Polarity|member|uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
  DECL|IC1Polarity|member|uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
  DECL|IC1Prescaler|member|uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
  DECL|IC1Prescaler|member|uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
  DECL|IC2ActiveInput|member|uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
  DECL|IC2Filter|member|uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
  DECL|IC2Polarity|member|uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
  DECL|IC2Prescaler|member|uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
  DECL|ICActiveInput|member|uint32_t ICActiveInput; /*!< Specifies the input.
  DECL|ICFilter|member|uint32_t ICFilter; /*!< Specifies the input capture filter.
  DECL|ICPolarity|member|uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
  DECL|ICPrescaler|member|uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
  DECL|LL_TIM_ACTIVEINPUT_DIRECTTI|macro|LL_TIM_ACTIVEINPUT_DIRECTTI
  DECL|LL_TIM_ACTIVEINPUT_INDIRECTTI|macro|LL_TIM_ACTIVEINPUT_INDIRECTTI
  DECL|LL_TIM_ACTIVEINPUT_TRC|macro|LL_TIM_ACTIVEINPUT_TRC
  DECL|LL_TIM_AUTOMATICOUTPUT_DISABLE|macro|LL_TIM_AUTOMATICOUTPUT_DISABLE
  DECL|LL_TIM_AUTOMATICOUTPUT_ENABLE|macro|LL_TIM_AUTOMATICOUTPUT_ENABLE
  DECL|LL_TIM_BDTR_InitTypeDef|typedef|} LL_TIM_BDTR_InitTypeDef;
  DECL|LL_TIM_BREAK_DISABLE|macro|LL_TIM_BREAK_DISABLE
  DECL|LL_TIM_BREAK_ENABLE|macro|LL_TIM_BREAK_ENABLE
  DECL|LL_TIM_BREAK_POLARITY_HIGH|macro|LL_TIM_BREAK_POLARITY_HIGH
  DECL|LL_TIM_BREAK_POLARITY_LOW|macro|LL_TIM_BREAK_POLARITY_LOW
  DECL|LL_TIM_CCDMAREQUEST_CC|macro|LL_TIM_CCDMAREQUEST_CC
  DECL|LL_TIM_CCDMAREQUEST_UPDATE|macro|LL_TIM_CCDMAREQUEST_UPDATE
  DECL|LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI|macro|LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
  DECL|LL_TIM_CCUPDATESOURCE_COMG_ONLY|macro|LL_TIM_CCUPDATESOURCE_COMG_ONLY
  DECL|LL_TIM_CC_DisableChannel|function|__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
  DECL|LL_TIM_CC_DisablePreload|function|__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
  DECL|LL_TIM_CC_EnableChannel|function|__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
  DECL|LL_TIM_CC_EnablePreload|function|__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
  DECL|LL_TIM_CC_GetDMAReqTrigger|function|__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
  DECL|LL_TIM_CC_IsEnabledChannel|function|__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
  DECL|LL_TIM_CC_SetDMAReqTrigger|function|__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
  DECL|LL_TIM_CC_SetLockLevel|function|__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
  DECL|LL_TIM_CC_SetUpdate|function|__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
  DECL|LL_TIM_CHANNEL_CH1N|macro|LL_TIM_CHANNEL_CH1N
  DECL|LL_TIM_CHANNEL_CH1|macro|LL_TIM_CHANNEL_CH1
  DECL|LL_TIM_CHANNEL_CH2N|macro|LL_TIM_CHANNEL_CH2N
  DECL|LL_TIM_CHANNEL_CH2|macro|LL_TIM_CHANNEL_CH2
  DECL|LL_TIM_CHANNEL_CH3N|macro|LL_TIM_CHANNEL_CH3N
  DECL|LL_TIM_CHANNEL_CH3|macro|LL_TIM_CHANNEL_CH3
  DECL|LL_TIM_CHANNEL_CH4|macro|LL_TIM_CHANNEL_CH4
  DECL|LL_TIM_CLOCKDIVISION_DIV1|macro|LL_TIM_CLOCKDIVISION_DIV1
  DECL|LL_TIM_CLOCKDIVISION_DIV2|macro|LL_TIM_CLOCKDIVISION_DIV2
  DECL|LL_TIM_CLOCKDIVISION_DIV4|macro|LL_TIM_CLOCKDIVISION_DIV4
  DECL|LL_TIM_CLOCKSOURCE_EXT_MODE1|macro|LL_TIM_CLOCKSOURCE_EXT_MODE1
  DECL|LL_TIM_CLOCKSOURCE_EXT_MODE2|macro|LL_TIM_CLOCKSOURCE_EXT_MODE2
  DECL|LL_TIM_CLOCKSOURCE_INTERNAL|macro|LL_TIM_CLOCKSOURCE_INTERNAL
  DECL|LL_TIM_COUNTERDIRECTION_DOWN|macro|LL_TIM_COUNTERDIRECTION_DOWN
  DECL|LL_TIM_COUNTERDIRECTION_UP|macro|LL_TIM_COUNTERDIRECTION_UP
  DECL|LL_TIM_COUNTERMODE_CENTER_DOWN|macro|LL_TIM_COUNTERMODE_CENTER_DOWN
  DECL|LL_TIM_COUNTERMODE_CENTER_UP_DOWN|macro|LL_TIM_COUNTERMODE_CENTER_UP_DOWN
  DECL|LL_TIM_COUNTERMODE_CENTER_UP|macro|LL_TIM_COUNTERMODE_CENTER_UP
  DECL|LL_TIM_COUNTERMODE_DOWN|macro|LL_TIM_COUNTERMODE_DOWN
  DECL|LL_TIM_COUNTERMODE_UP|macro|LL_TIM_COUNTERMODE_UP
  DECL|LL_TIM_ClearFlag_BRK|function|__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC1OVR|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC1|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC2OVR|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC2|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC3OVR|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC3|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC4OVR|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_CC4|function|__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_COM|function|__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_TRIG|function|__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ClearFlag_UPDATE|function|__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ConfigBRK|function|__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
  DECL|LL_TIM_ConfigDMABurst|function|__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
  DECL|LL_TIM_ConfigETR|function|__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
  DECL|LL_TIM_DIER_BIE|macro|LL_TIM_DIER_BIE
  DECL|LL_TIM_DIER_CC1IE|macro|LL_TIM_DIER_CC1IE
  DECL|LL_TIM_DIER_CC2IE|macro|LL_TIM_DIER_CC2IE
  DECL|LL_TIM_DIER_CC3IE|macro|LL_TIM_DIER_CC3IE
  DECL|LL_TIM_DIER_CC4IE|macro|LL_TIM_DIER_CC4IE
  DECL|LL_TIM_DIER_COMIE|macro|LL_TIM_DIER_COMIE
  DECL|LL_TIM_DIER_TIE|macro|LL_TIM_DIER_TIE
  DECL|LL_TIM_DIER_UIE|macro|LL_TIM_DIER_UIE
  DECL|LL_TIM_DMABURST_BASEADDR_ARR|macro|LL_TIM_DMABURST_BASEADDR_ARR
  DECL|LL_TIM_DMABURST_BASEADDR_BDTR|macro|LL_TIM_DMABURST_BASEADDR_BDTR
  DECL|LL_TIM_DMABURST_BASEADDR_CCER|macro|LL_TIM_DMABURST_BASEADDR_CCER
  DECL|LL_TIM_DMABURST_BASEADDR_CCMR1|macro|LL_TIM_DMABURST_BASEADDR_CCMR1
  DECL|LL_TIM_DMABURST_BASEADDR_CCMR2|macro|LL_TIM_DMABURST_BASEADDR_CCMR2
  DECL|LL_TIM_DMABURST_BASEADDR_CCR1|macro|LL_TIM_DMABURST_BASEADDR_CCR1
  DECL|LL_TIM_DMABURST_BASEADDR_CCR2|macro|LL_TIM_DMABURST_BASEADDR_CCR2
  DECL|LL_TIM_DMABURST_BASEADDR_CCR3|macro|LL_TIM_DMABURST_BASEADDR_CCR3
  DECL|LL_TIM_DMABURST_BASEADDR_CCR4|macro|LL_TIM_DMABURST_BASEADDR_CCR4
  DECL|LL_TIM_DMABURST_BASEADDR_CNT|macro|LL_TIM_DMABURST_BASEADDR_CNT
  DECL|LL_TIM_DMABURST_BASEADDR_CR1|macro|LL_TIM_DMABURST_BASEADDR_CR1
  DECL|LL_TIM_DMABURST_BASEADDR_CR2|macro|LL_TIM_DMABURST_BASEADDR_CR2
  DECL|LL_TIM_DMABURST_BASEADDR_DIER|macro|LL_TIM_DMABURST_BASEADDR_DIER
  DECL|LL_TIM_DMABURST_BASEADDR_EGR|macro|LL_TIM_DMABURST_BASEADDR_EGR
  DECL|LL_TIM_DMABURST_BASEADDR_OR|macro|LL_TIM_DMABURST_BASEADDR_OR
  DECL|LL_TIM_DMABURST_BASEADDR_PSC|macro|LL_TIM_DMABURST_BASEADDR_PSC
  DECL|LL_TIM_DMABURST_BASEADDR_RCR|macro|LL_TIM_DMABURST_BASEADDR_RCR
  DECL|LL_TIM_DMABURST_BASEADDR_SMCR|macro|LL_TIM_DMABURST_BASEADDR_SMCR
  DECL|LL_TIM_DMABURST_BASEADDR_SR|macro|LL_TIM_DMABURST_BASEADDR_SR
  DECL|LL_TIM_DMABURST_LENGTH_10TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_10TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_11TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_11TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_12TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_12TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_13TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_13TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_14TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_14TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_15TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_15TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_16TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_16TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_17TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_17TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_18TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_18TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_1TRANSFER|macro|LL_TIM_DMABURST_LENGTH_1TRANSFER
  DECL|LL_TIM_DMABURST_LENGTH_2TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_2TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_3TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_3TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_4TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_4TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_5TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_5TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_6TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_6TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_7TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_7TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_8TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_8TRANSFERS
  DECL|LL_TIM_DMABURST_LENGTH_9TRANSFERS|macro|LL_TIM_DMABURST_LENGTH_9TRANSFERS
  DECL|LL_TIM_DisableARRPreload|function|__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableAllOutputs|function|__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableAutomaticOutput|function|__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableBRK|function|__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableCounter|function|__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableDMAReq_CC1|function|__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableDMAReq_CC2|function|__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableDMAReq_CC3|function|__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableDMAReq_CC4|function|__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableDMAReq_COM|function|__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableDMAReq_TRIG|function|__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableDMAReq_UPDATE|function|__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableExternalClock|function|__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_BRK|function|__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_CC1|function|__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_CC2|function|__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_CC3|function|__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_CC4|function|__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_COM|function|__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_TRIG|function|__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableIT_UPDATE|function|__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableMasterSlaveMode|function|__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
  DECL|LL_TIM_DisableUpdateEvent|function|__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
  DECL|LL_TIM_ENCODERMODE_X2_TI1|macro|LL_TIM_ENCODERMODE_X2_TI1
  DECL|LL_TIM_ENCODERMODE_X2_TI2|macro|LL_TIM_ENCODERMODE_X2_TI2
  DECL|LL_TIM_ENCODERMODE_X4_TI12|macro|LL_TIM_ENCODERMODE_X4_TI12
  DECL|LL_TIM_ENCODER_InitTypeDef|typedef|} LL_TIM_ENCODER_InitTypeDef;
  DECL|LL_TIM_ETR_FILTER_FDIV16_N5|macro|LL_TIM_ETR_FILTER_FDIV16_N5
  DECL|LL_TIM_ETR_FILTER_FDIV16_N6|macro|LL_TIM_ETR_FILTER_FDIV16_N6
  DECL|LL_TIM_ETR_FILTER_FDIV16_N8|macro|LL_TIM_ETR_FILTER_FDIV16_N8
  DECL|LL_TIM_ETR_FILTER_FDIV1_N2|macro|LL_TIM_ETR_FILTER_FDIV1_N2
  DECL|LL_TIM_ETR_FILTER_FDIV1_N4|macro|LL_TIM_ETR_FILTER_FDIV1_N4
  DECL|LL_TIM_ETR_FILTER_FDIV1_N8|macro|LL_TIM_ETR_FILTER_FDIV1_N8
  DECL|LL_TIM_ETR_FILTER_FDIV1|macro|LL_TIM_ETR_FILTER_FDIV1
  DECL|LL_TIM_ETR_FILTER_FDIV2_N6|macro|LL_TIM_ETR_FILTER_FDIV2_N6
  DECL|LL_TIM_ETR_FILTER_FDIV2_N8|macro|LL_TIM_ETR_FILTER_FDIV2_N8
  DECL|LL_TIM_ETR_FILTER_FDIV32_N5|macro|LL_TIM_ETR_FILTER_FDIV32_N5
  DECL|LL_TIM_ETR_FILTER_FDIV32_N6|macro|LL_TIM_ETR_FILTER_FDIV32_N6
  DECL|LL_TIM_ETR_FILTER_FDIV32_N8|macro|LL_TIM_ETR_FILTER_FDIV32_N8
  DECL|LL_TIM_ETR_FILTER_FDIV4_N6|macro|LL_TIM_ETR_FILTER_FDIV4_N6
  DECL|LL_TIM_ETR_FILTER_FDIV4_N8|macro|LL_TIM_ETR_FILTER_FDIV4_N8
  DECL|LL_TIM_ETR_FILTER_FDIV8_N6|macro|LL_TIM_ETR_FILTER_FDIV8_N6
  DECL|LL_TIM_ETR_FILTER_FDIV8_N8|macro|LL_TIM_ETR_FILTER_FDIV8_N8
  DECL|LL_TIM_ETR_POLARITY_INVERTED|macro|LL_TIM_ETR_POLARITY_INVERTED
  DECL|LL_TIM_ETR_POLARITY_NONINVERTED|macro|LL_TIM_ETR_POLARITY_NONINVERTED
  DECL|LL_TIM_ETR_PRESCALER_DIV1|macro|LL_TIM_ETR_PRESCALER_DIV1
  DECL|LL_TIM_ETR_PRESCALER_DIV2|macro|LL_TIM_ETR_PRESCALER_DIV2
  DECL|LL_TIM_ETR_PRESCALER_DIV4|macro|LL_TIM_ETR_PRESCALER_DIV4
  DECL|LL_TIM_ETR_PRESCALER_DIV8|macro|LL_TIM_ETR_PRESCALER_DIV8
  DECL|LL_TIM_EnableARRPreload|function|__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableAllOutputs|function|__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableAutomaticOutput|function|__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableBRK|function|__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableCounter|function|__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableDMAReq_CC1|function|__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableDMAReq_CC2|function|__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableDMAReq_CC3|function|__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableDMAReq_CC4|function|__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableDMAReq_COM|function|__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableDMAReq_TRIG|function|__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableDMAReq_UPDATE|function|__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableExternalClock|function|__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_BRK|function|__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_CC1|function|__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_CC2|function|__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_CC3|function|__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_CC4|function|__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_COM|function|__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_TRIG|function|__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableIT_UPDATE|function|__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableMasterSlaveMode|function|__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
  DECL|LL_TIM_EnableUpdateEvent|function|__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_BRK|function|__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_CC1|function|__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_CC2|function|__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_CC3|function|__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_CC4|function|__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_COM|function|__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_TRIG|function|__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GenerateEvent_UPDATE|function|__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetAutoReload|function|__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetClockDivision|function|__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetCounterMode|function|__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetCounter|function|__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetDirection|function|__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetOnePulseMode|function|__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetPrescaler|function|__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetRepetitionCounter|function|__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
  DECL|LL_TIM_GetUpdateSource|function|__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
  DECL|LL_TIM_HALLSENSOR_InitTypeDef|typedef|} LL_TIM_HALLSENSOR_InitTypeDef;
  DECL|LL_TIM_ICPSC_DIV1|macro|LL_TIM_ICPSC_DIV1
  DECL|LL_TIM_ICPSC_DIV2|macro|LL_TIM_ICPSC_DIV2
  DECL|LL_TIM_ICPSC_DIV4|macro|LL_TIM_ICPSC_DIV4
  DECL|LL_TIM_ICPSC_DIV8|macro|LL_TIM_ICPSC_DIV8
  DECL|LL_TIM_IC_Config|function|__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
  DECL|LL_TIM_IC_DisableXORCombination|function|__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IC_EnableXORCombination|function|__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IC_FILTER_FDIV16_N5|macro|LL_TIM_IC_FILTER_FDIV16_N5
  DECL|LL_TIM_IC_FILTER_FDIV16_N6|macro|LL_TIM_IC_FILTER_FDIV16_N6
  DECL|LL_TIM_IC_FILTER_FDIV16_N8|macro|LL_TIM_IC_FILTER_FDIV16_N8
  DECL|LL_TIM_IC_FILTER_FDIV1_N2|macro|LL_TIM_IC_FILTER_FDIV1_N2
  DECL|LL_TIM_IC_FILTER_FDIV1_N4|macro|LL_TIM_IC_FILTER_FDIV1_N4
  DECL|LL_TIM_IC_FILTER_FDIV1_N8|macro|LL_TIM_IC_FILTER_FDIV1_N8
  DECL|LL_TIM_IC_FILTER_FDIV1|macro|LL_TIM_IC_FILTER_FDIV1
  DECL|LL_TIM_IC_FILTER_FDIV2_N6|macro|LL_TIM_IC_FILTER_FDIV2_N6
  DECL|LL_TIM_IC_FILTER_FDIV2_N8|macro|LL_TIM_IC_FILTER_FDIV2_N8
  DECL|LL_TIM_IC_FILTER_FDIV32_N5|macro|LL_TIM_IC_FILTER_FDIV32_N5
  DECL|LL_TIM_IC_FILTER_FDIV32_N6|macro|LL_TIM_IC_FILTER_FDIV32_N6
  DECL|LL_TIM_IC_FILTER_FDIV32_N8|macro|LL_TIM_IC_FILTER_FDIV32_N8
  DECL|LL_TIM_IC_FILTER_FDIV4_N6|macro|LL_TIM_IC_FILTER_FDIV4_N6
  DECL|LL_TIM_IC_FILTER_FDIV4_N8|macro|LL_TIM_IC_FILTER_FDIV4_N8
  DECL|LL_TIM_IC_FILTER_FDIV8_N6|macro|LL_TIM_IC_FILTER_FDIV8_N6
  DECL|LL_TIM_IC_FILTER_FDIV8_N8|macro|LL_TIM_IC_FILTER_FDIV8_N8
  DECL|LL_TIM_IC_GetActiveInput|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_IC_GetCaptureCH1|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IC_GetCaptureCH2|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IC_GetCaptureCH3|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IC_GetCaptureCH4|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IC_GetFilter|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_IC_GetPolarity|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_IC_GetPrescaler|function|__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_IC_InitTypeDef|typedef|} LL_TIM_IC_InitTypeDef;
  DECL|LL_TIM_IC_IsEnabledXORCombination|function|__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IC_POLARITY_BOTHEDGE|macro|LL_TIM_IC_POLARITY_BOTHEDGE
  DECL|LL_TIM_IC_POLARITY_FALLING|macro|LL_TIM_IC_POLARITY_FALLING
  DECL|LL_TIM_IC_POLARITY_RISING|macro|LL_TIM_IC_POLARITY_RISING
  DECL|LL_TIM_IC_SetActiveInput|function|__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
  DECL|LL_TIM_IC_SetFilter|function|__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
  DECL|LL_TIM_IC_SetPolarity|function|__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
  DECL|LL_TIM_IC_SetPrescaler|function|__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
  DECL|LL_TIM_InitTypeDef|typedef|} LL_TIM_InitTypeDef;
  DECL|LL_TIM_IsActiveFlag_BRK|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC1OVR|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC1|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC2OVR|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC2|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC3OVR|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC3|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC4OVR|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_CC4|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_COM|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_TRIG|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsActiveFlag_UPDATE|function|__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledARRPreload|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledAllOutputs|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledAutomaticOutput|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledCounter|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledDMAReq_CC1|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledDMAReq_CC2|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledDMAReq_CC3|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledDMAReq_CC4|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledDMAReq_COM|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledDMAReq_TRIG|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledDMAReq_UPDATE|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledExternalClock|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_BRK|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_CC1|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_CC2|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_CC3|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_CC4|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_COM|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_TRIG|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledIT_UPDATE|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledMasterSlaveMode|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
  DECL|LL_TIM_IsEnabledUpdateEvent|function|__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
  DECL|LL_TIM_LOCKLEVEL_1|macro|LL_TIM_LOCKLEVEL_1
  DECL|LL_TIM_LOCKLEVEL_2|macro|LL_TIM_LOCKLEVEL_2
  DECL|LL_TIM_LOCKLEVEL_3|macro|LL_TIM_LOCKLEVEL_3
  DECL|LL_TIM_LOCKLEVEL_OFF|macro|LL_TIM_LOCKLEVEL_OFF
  DECL|LL_TIM_OCIDLESTATE_HIGH|macro|LL_TIM_OCIDLESTATE_HIGH
  DECL|LL_TIM_OCIDLESTATE_LOW|macro|LL_TIM_OCIDLESTATE_LOW
  DECL|LL_TIM_OCMODE_ACTIVE|macro|LL_TIM_OCMODE_ACTIVE
  DECL|LL_TIM_OCMODE_FORCED_ACTIVE|macro|LL_TIM_OCMODE_FORCED_ACTIVE
  DECL|LL_TIM_OCMODE_FORCED_INACTIVE|macro|LL_TIM_OCMODE_FORCED_INACTIVE
  DECL|LL_TIM_OCMODE_FROZEN|macro|LL_TIM_OCMODE_FROZEN
  DECL|LL_TIM_OCMODE_INACTIVE|macro|LL_TIM_OCMODE_INACTIVE
  DECL|LL_TIM_OCMODE_PWM1|macro|LL_TIM_OCMODE_PWM1
  DECL|LL_TIM_OCMODE_PWM2|macro|LL_TIM_OCMODE_PWM2
  DECL|LL_TIM_OCMODE_TOGGLE|macro|LL_TIM_OCMODE_TOGGLE
  DECL|LL_TIM_OCPOLARITY_HIGH|macro|LL_TIM_OCPOLARITY_HIGH
  DECL|LL_TIM_OCPOLARITY_LOW|macro|LL_TIM_OCPOLARITY_LOW
  DECL|LL_TIM_OCSTATE_DISABLE|macro|LL_TIM_OCSTATE_DISABLE
  DECL|LL_TIM_OCSTATE_ENABLE|macro|LL_TIM_OCSTATE_ENABLE
  DECL|LL_TIM_OC_ConfigOutput|function|__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
  DECL|LL_TIM_OC_DisableClear|function|__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_DisableFast|function|__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_DisablePreload|function|__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_EnableClear|function|__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_EnableFast|function|__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_EnablePreload|function|__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_GetCompareCH1|function|__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
  DECL|LL_TIM_OC_GetCompareCH2|function|__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
  DECL|LL_TIM_OC_GetCompareCH3|function|__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
  DECL|LL_TIM_OC_GetCompareCH4|function|__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
  DECL|LL_TIM_OC_GetIdleState|function|__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_GetMode|function|__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_GetPolarity|function|__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_InitTypeDef|typedef|} LL_TIM_OC_InitTypeDef;
  DECL|LL_TIM_OC_IsEnabledClear|function|__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_IsEnabledFast|function|__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_IsEnabledPreload|function|__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
  DECL|LL_TIM_OC_SetCompareCH1|function|__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
  DECL|LL_TIM_OC_SetCompareCH2|function|__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
  DECL|LL_TIM_OC_SetCompareCH3|function|__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
  DECL|LL_TIM_OC_SetCompareCH4|function|__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
  DECL|LL_TIM_OC_SetDeadTime|function|__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
  DECL|LL_TIM_OC_SetIdleState|function|__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
  DECL|LL_TIM_OC_SetMode|function|__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
  DECL|LL_TIM_OC_SetPolarity|function|__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
  DECL|LL_TIM_ONEPULSEMODE_REPETITIVE|macro|LL_TIM_ONEPULSEMODE_REPETITIVE
  DECL|LL_TIM_ONEPULSEMODE_SINGLE|macro|LL_TIM_ONEPULSEMODE_SINGLE
  DECL|LL_TIM_OSSI_DISABLE|macro|LL_TIM_OSSI_DISABLE
  DECL|LL_TIM_OSSI_ENABLE|macro|LL_TIM_OSSI_ENABLE
  DECL|LL_TIM_OSSR_DISABLE|macro|LL_TIM_OSSR_DISABLE
  DECL|LL_TIM_OSSR_ENABLE|macro|LL_TIM_OSSR_ENABLE
  DECL|LL_TIM_ReadReg|macro|LL_TIM_ReadReg
  DECL|LL_TIM_SLAVEMODE_DISABLED|macro|LL_TIM_SLAVEMODE_DISABLED
  DECL|LL_TIM_SLAVEMODE_GATED|macro|LL_TIM_SLAVEMODE_GATED
  DECL|LL_TIM_SLAVEMODE_RESET|macro|LL_TIM_SLAVEMODE_RESET
  DECL|LL_TIM_SLAVEMODE_TRIGGER|macro|LL_TIM_SLAVEMODE_TRIGGER
  DECL|LL_TIM_SR_BIF|macro|LL_TIM_SR_BIF
  DECL|LL_TIM_SR_CC1IF|macro|LL_TIM_SR_CC1IF
  DECL|LL_TIM_SR_CC1OF|macro|LL_TIM_SR_CC1OF
  DECL|LL_TIM_SR_CC2IF|macro|LL_TIM_SR_CC2IF
  DECL|LL_TIM_SR_CC2OF|macro|LL_TIM_SR_CC2OF
  DECL|LL_TIM_SR_CC3IF|macro|LL_TIM_SR_CC3IF
  DECL|LL_TIM_SR_CC3OF|macro|LL_TIM_SR_CC3OF
  DECL|LL_TIM_SR_CC4IF|macro|LL_TIM_SR_CC4IF
  DECL|LL_TIM_SR_CC4OF|macro|LL_TIM_SR_CC4OF
  DECL|LL_TIM_SR_COMIF|macro|LL_TIM_SR_COMIF
  DECL|LL_TIM_SR_TIF|macro|LL_TIM_SR_TIF
  DECL|LL_TIM_SR_UIF|macro|LL_TIM_SR_UIF
  DECL|LL_TIM_SetAutoReload|function|__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
  DECL|LL_TIM_SetClockDivision|function|__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
  DECL|LL_TIM_SetClockSource|function|__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
  DECL|LL_TIM_SetCounterMode|function|__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
  DECL|LL_TIM_SetCounter|function|__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
  DECL|LL_TIM_SetEncoderMode|function|__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
  DECL|LL_TIM_SetOffStates|function|__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
  DECL|LL_TIM_SetOnePulseMode|function|__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
  DECL|LL_TIM_SetPrescaler|function|__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
  DECL|LL_TIM_SetRemap|function|__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
  DECL|LL_TIM_SetRepetitionCounter|function|__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
  DECL|LL_TIM_SetSlaveMode|function|__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
  DECL|LL_TIM_SetTriggerInput|function|__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
  DECL|LL_TIM_SetTriggerOutput|function|__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
  DECL|LL_TIM_SetUpdateSource|function|__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
  DECL|LL_TIM_TIM11_TI1_RMP_GPIO1|macro|LL_TIM_TIM11_TI1_RMP_GPIO1
  DECL|LL_TIM_TIM11_TI1_RMP_GPIO2|macro|LL_TIM_TIM11_TI1_RMP_GPIO2
  DECL|LL_TIM_TIM11_TI1_RMP_GPIO|macro|LL_TIM_TIM11_TI1_RMP_GPIO
  DECL|LL_TIM_TIM11_TI1_RMP_HSE_RTC|macro|LL_TIM_TIM11_TI1_RMP_HSE_RTC
  DECL|LL_TIM_TIM2_ITR1_RMP_ETH_PTP|macro|LL_TIM_TIM2_ITR1_RMP_ETH_PTP
  DECL|LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF|macro|LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
  DECL|LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF|macro|LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
  DECL|LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO|macro|LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
  DECL|LL_TIM_TIM5_TI4_RMP_GPIO|macro|LL_TIM_TIM5_TI4_RMP_GPIO
  DECL|LL_TIM_TIM5_TI4_RMP_LSE|macro|LL_TIM_TIM5_TI4_RMP_LSE
  DECL|LL_TIM_TIM5_TI4_RMP_LSI|macro|LL_TIM_TIM5_TI4_RMP_LSI
  DECL|LL_TIM_TIM5_TI4_RMP_RTC|macro|LL_TIM_TIM5_TI4_RMP_RTC
  DECL|LL_TIM_TRGO_CC1IF|macro|LL_TIM_TRGO_CC1IF
  DECL|LL_TIM_TRGO_ENABLE|macro|LL_TIM_TRGO_ENABLE
  DECL|LL_TIM_TRGO_OC1REF|macro|LL_TIM_TRGO_OC1REF
  DECL|LL_TIM_TRGO_OC2REF|macro|LL_TIM_TRGO_OC2REF
  DECL|LL_TIM_TRGO_OC3REF|macro|LL_TIM_TRGO_OC3REF
  DECL|LL_TIM_TRGO_OC4REF|macro|LL_TIM_TRGO_OC4REF
  DECL|LL_TIM_TRGO_RESET|macro|LL_TIM_TRGO_RESET
  DECL|LL_TIM_TRGO_UPDATE|macro|LL_TIM_TRGO_UPDATE
  DECL|LL_TIM_TS_ETRF|macro|LL_TIM_TS_ETRF
  DECL|LL_TIM_TS_ITR0|macro|LL_TIM_TS_ITR0
  DECL|LL_TIM_TS_ITR1|macro|LL_TIM_TS_ITR1
  DECL|LL_TIM_TS_ITR2|macro|LL_TIM_TS_ITR2
  DECL|LL_TIM_TS_ITR3|macro|LL_TIM_TS_ITR3
  DECL|LL_TIM_TS_TI1FP1|macro|LL_TIM_TS_TI1FP1
  DECL|LL_TIM_TS_TI1F_ED|macro|LL_TIM_TS_TI1F_ED
  DECL|LL_TIM_TS_TI2FP2|macro|LL_TIM_TS_TI2FP2
  DECL|LL_TIM_UPDATESOURCE_COUNTER|macro|LL_TIM_UPDATESOURCE_COUNTER
  DECL|LL_TIM_UPDATESOURCE_REGULAR|macro|LL_TIM_UPDATESOURCE_REGULAR
  DECL|LL_TIM_WriteReg|macro|LL_TIM_WriteReg
  DECL|LockLevel|member|uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
  DECL|OCIdleState|member|uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  DECL|OCMode|member|uint32_t OCMode; /*!< Specifies the output mode.
  DECL|OCNIdleState|member|uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
  DECL|OCNPolarity|member|uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
  DECL|OCNState|member|uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
  DECL|OCPolarity|member|uint32_t OCPolarity; /*!< Specifies the output polarity.
  DECL|OCState|member|uint32_t OCState; /*!< Specifies the TIM Output Compare state.
  DECL|OFFSET_TAB_CCMRx|variable|OFFSET_TAB_CCMRx
  DECL|OSSIState|member|uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
  DECL|OSSRState|member|uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
  DECL|Prescaler|member|uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
  DECL|RepetitionCounter|member|uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
  DECL|SHIFT_TAB_CCxP|variable|SHIFT_TAB_CCxP
  DECL|SHIFT_TAB_ICxx|variable|SHIFT_TAB_ICxx
  DECL|SHIFT_TAB_OCxx|variable|SHIFT_TAB_OCxx
  DECL|SHIFT_TAB_OISx|variable|SHIFT_TAB_OISx
  DECL|TIM11_OR_RMP_MASK|macro|TIM11_OR_RMP_MASK
  DECL|TIM2_OR_RMP_MASK|macro|TIM2_OR_RMP_MASK
  DECL|TIM5_OR_RMP_MASK|macro|TIM5_OR_RMP_MASK
  DECL|TIM_CALC_DTS|macro|TIM_CALC_DTS
  DECL|TIM_GET_CHANNEL_INDEX|macro|TIM_GET_CHANNEL_INDEX
  DECL|TIMx_OR_RMP_MASK|macro|TIMx_OR_RMP_MASK
  DECL|TIMx_OR_RMP_SHIFT|macro|TIMx_OR_RMP_SHIFT
  DECL|__LL_TIM_CALC_ARR|macro|__LL_TIM_CALC_ARR
  DECL|__LL_TIM_CALC_DEADTIME|macro|__LL_TIM_CALC_DEADTIME
  DECL|__LL_TIM_CALC_DELAY|macro|__LL_TIM_CALC_DELAY
  DECL|__LL_TIM_CALC_PSC|macro|__LL_TIM_CALC_PSC
  DECL|__LL_TIM_CALC_PULSE|macro|__LL_TIM_CALC_PULSE
  DECL|__LL_TIM_GET_ICPSC_RATIO|macro|__LL_TIM_GET_ICPSC_RATIO
  DECL|__STM32F2xx_LL_TIM_H|macro|__STM32F2xx_LL_TIM_H
  