text: /* 
  / *
  / *
  / * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
  / * 
  / * Copyright 2007-2019 Broadcom Inc. All rights reserved.
   */ 
  
  #define TH3_UDF_PIPE0 {th3_udf_pipe0_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE0r}
  #define TH3_UDF_PIPE1 {th3_udf_pipe1_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE1r}
  #define TH3_UDF_PIPE2 {th3_udf_pipe2_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE2r}
  #define TH3_UDF_PIPE3 {th3_udf_pipe3_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE3r}
  #define TH3_UDF_PIPE4 {th3_udf_pipe4_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE4r}
  #define TH3_UDF_PIPE5 {th3_udf_pipe5_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE5r}
  #define TH3_UDF_PIPE6 {th3_udf_pipe6_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE6r}
  #define TH3_UDF_PIPE7 {th3_udf_pipe7_name, NO_MODE, NO_MODE_FIELD, UDF_TCAM_CAM_BIST_CONFIG_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, UDF_TCAM_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_CPU_COS_PIPE0 {th3_cpu_cos_pipe0_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE0r}
  #define TH3_CPU_COS_PIPE1 {th3_cpu_cos_pipe1_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE1r}
  #define TH3_CPU_COS_PIPE2 {th3_cpu_cos_pipe2_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE2r}
  #define TH3_CPU_COS_PIPE3 {th3_cpu_cos_pipe3_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE3r}
  #define TH3_CPU_COS_PIPE4 {th3_cpu_cos_pipe4_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE4r}
  #define TH3_CPU_COS_PIPE5 {th3_cpu_cos_pipe5_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE5r}
  #define TH3_CPU_COS_PIPE6 {th3_cpu_cos_pipe6_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE6r}
  #define TH3_CPU_COS_PIPE7 {th3_cpu_cos_pipe7_name, NO_MODE, NO_MODE_FIELD, CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, CPU_COS_MAP_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_EFP_PIPE0_SLICE0 {th3_efp_pipe0_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE0r}
  #define TH3_EFP_PIPE1_SLICE0 {th3_efp_pipe1_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE1r}
  #define TH3_EFP_PIPE2_SLICE0 {th3_efp_pipe2_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE2r}
  #define TH3_EFP_PIPE3_SLICE0 {th3_efp_pipe3_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE3r}
  #define TH3_EFP_PIPE4_SLICE0 {th3_efp_pipe4_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE4r}
  #define TH3_EFP_PIPE5_SLICE0 {th3_efp_pipe5_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE5r}
  #define TH3_EFP_PIPE6_SLICE0 {th3_efp_pipe6_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE6r}
  #define TH3_EFP_PIPE7_SLICE0 {th3_efp_pipe7_slice0_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_0_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_EFP_PIPE0_SLICE1 {th3_efp_pipe0_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE0r}
  #define TH3_EFP_PIPE1_SLICE1 {th3_efp_pipe1_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE1r}
  #define TH3_EFP_PIPE2_SLICE1 {th3_efp_pipe2_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE2r}
  #define TH3_EFP_PIPE3_SLICE1 {th3_efp_pipe3_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE3r}
  #define TH3_EFP_PIPE4_SLICE1 {th3_efp_pipe4_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE4r}
  #define TH3_EFP_PIPE5_SLICE1 {th3_efp_pipe5_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE5r}
  #define TH3_EFP_PIPE6_SLICE1 {th3_efp_pipe6_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE6r}
  #define TH3_EFP_PIPE7_SLICE1 {th3_efp_pipe7_slice1_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_1_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_EFP_PIPE0_SLICE2 {th3_efp_pipe0_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE0r}
  #define TH3_EFP_PIPE1_SLICE2 {th3_efp_pipe1_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE1r}
  #define TH3_EFP_PIPE2_SLICE2 {th3_efp_pipe2_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE2r}
  #define TH3_EFP_PIPE3_SLICE2 {th3_efp_pipe3_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE3r}
  #define TH3_EFP_PIPE4_SLICE2 {th3_efp_pipe4_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE4r}
  #define TH3_EFP_PIPE5_SLICE2 {th3_efp_pipe5_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE5r}
  #define TH3_EFP_PIPE6_SLICE2 {th3_efp_pipe6_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE6r}
  #define TH3_EFP_PIPE7_SLICE2 {th3_efp_pipe7_slice2_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_2_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_EFP_PIPE0_SLICE3 {th3_efp_pipe0_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE0r}
  #define TH3_EFP_PIPE1_SLICE3 {th3_efp_pipe1_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE1r}
  #define TH3_EFP_PIPE2_SLICE3 {th3_efp_pipe2_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE2r}
  #define TH3_EFP_PIPE3_SLICE3 {th3_efp_pipe3_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE3r}
  #define TH3_EFP_PIPE4_SLICE3 {th3_efp_pipe4_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE4r}
  #define TH3_EFP_PIPE5_SLICE3 {th3_efp_pipe5_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE5r}
  #define TH3_EFP_PIPE6_SLICE3 {th3_efp_pipe6_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE6r}
  #define TH3_EFP_PIPE7_SLICE3 {th3_efp_pipe7_slice3_name, NO_MODE, NO_MODE_FIELD, EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EFP_SLICE_3_CAM_BIST_STATUS_PIPE7r}
     
  
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0 {th3_exact_match_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r}
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1 {th3_exact_match_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r}
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2 {th3_exact_match_logical_table_select_pipe2_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2r}
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3 {th3_exact_match_logical_table_select_pipe3_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3r}
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4 {th3_exact_match_logical_table_select_pipe4_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE4r}
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5 {th3_exact_match_logical_table_select_pipe5_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE5r}
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6 {th3_exact_match_logical_table_select_pipe6_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE6r}
  #define TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7 {th3_exact_match_logical_table_select_pipe7_name, NO_MODE, NO_MODE_FIELD, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_IFP_TCAM_POOL0_PIPE0 {th3_ifp_tcam_pool0_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE0r}
  #define TH3_IFP_TCAM_POOL0_PIPE1 {th3_ifp_tcam_pool0_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE1r}
  #define TH3_IFP_TCAM_POOL0_PIPE2 {th3_ifp_tcam_pool0_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1,  IFP_TCAM_POOL0_BIST_STATUS_PIPE2r}
  #define TH3_IFP_TCAM_POOL0_PIPE3 {th3_ifp_tcam_pool0_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE3r}
  #define TH3_IFP_TCAM_POOL0_PIPE4 {th3_ifp_tcam_pool0_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE4r}
  #define TH3_IFP_TCAM_POOL0_PIPE5 {th3_ifp_tcam_pool0_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE5r}
  #define TH3_IFP_TCAM_POOL0_PIPE6 {th3_ifp_tcam_pool0_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE6r}
  #define TH3_IFP_TCAM_POOL0_PIPE7 {th3_ifp_tcam_pool0_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL0_BIST_STATUS_PIPE7r}
  
  #define TH3_IFP_TCAM_POOL1_PIPE0 {th3_ifp_tcam_pool1_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE0r}
  #define TH3_IFP_TCAM_POOL1_PIPE1 {th3_ifp_tcam_pool1_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE1r}
  #define TH3_IFP_TCAM_POOL1_PIPE2 {th3_ifp_tcam_pool1_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE2r}
  #define TH3_IFP_TCAM_POOL1_PIPE3 {th3_ifp_tcam_pool1_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE3r}
  #define TH3_IFP_TCAM_POOL1_PIPE4 {th3_ifp_tcam_pool1_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE4r}
  #define TH3_IFP_TCAM_POOL1_PIPE5 {th3_ifp_tcam_pool1_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE5r}
  #define TH3_IFP_TCAM_POOL1_PIPE6 {th3_ifp_tcam_pool1_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE6r}
  #define TH3_IFP_TCAM_POOL1_PIPE7 {th3_ifp_tcam_pool1_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL1_BIST_STATUS_PIPE7r}
  
  #define TH3_IFP_TCAM_POOL2_PIPE0 {th3_ifp_tcam_pool2_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE0r}
  #define TH3_IFP_TCAM_POOL2_PIPE1 {th3_ifp_tcam_pool2_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE1r}
  #define TH3_IFP_TCAM_POOL2_PIPE2 {th3_ifp_tcam_pool2_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE2r}
  #define TH3_IFP_TCAM_POOL2_PIPE3 {th3_ifp_tcam_pool2_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE3r}
  #define TH3_IFP_TCAM_POOL2_PIPE4 {th3_ifp_tcam_pool2_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE4r}
  #define TH3_IFP_TCAM_POOL2_PIPE5 {th3_ifp_tcam_pool2_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE5r}
  #define TH3_IFP_TCAM_POOL2_PIPE6 {th3_ifp_tcam_pool2_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE6r}
  #define TH3_IFP_TCAM_POOL2_PIPE7 {th3_ifp_tcam_pool2_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_TCAM_POOL2_BIST_STATUS_PIPE7r}
   
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE0 {th3_ifp_logical_table_select_pipe0_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0r}
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE1 {th3_ifp_logical_table_select_pipe1_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1r}
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE2 {th3_ifp_logical_table_select_pipe2_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2r}
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE3 {th3_ifp_logical_table_select_pipe3_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3r}
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE4 {th3_ifp_logical_table_select_pipe4_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE4r}
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE5 {th3_ifp_logical_table_select_pipe5_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE5r}
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE6 {th3_ifp_logical_table_select_pipe6_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE6r}
  #define TH3_IFP_LOGICAL_TABLE_SELECT_PIPE7 {th3_ifp_logical_table_select_pipe7_name, NO_MODE, NO_MODE_FIELD, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_L2_USER_ENTRY_PIPE0 {th3_l2_user_entry_pipe0_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE0r}
  #define TH3_L2_USER_ENTRY_PIPE1 {th3_l2_user_entry_pipe1_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE1r}
  #define TH3_L2_USER_ENTRY_PIPE2 {th3_l2_user_entry_pipe2_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE2r}
  #define TH3_L2_USER_ENTRY_PIPE3 {th3_l2_user_entry_pipe3_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE3r}
  #define TH3_L2_USER_ENTRY_PIPE4 {th3_l2_user_entry_pipe4_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE4r}
  #define TH3_L2_USER_ENTRY_PIPE5 {th3_l2_user_entry_pipe5_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE5r}
  #define TH3_L2_USER_ENTRY_PIPE6 {th3_l2_user_entry_pipe6_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE6r}
  #define TH3_L2_USER_ENTRY_PIPE7 {th3_l2_user_entry_pipe7_name, NO_MODE, NO_MODE_FIELD, L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 1, L2_USER_ENTRY_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_L3_DEFIP_PIPE0_MODE0 {th3_l3_defip_pipe0_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE0r}
  #define TH3_L3_DEFIP_PIPE1_MODE0 {th3_l3_defip_pipe1_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE1r}
  #define TH3_L3_DEFIP_PIPE2_MODE0 {th3_l3_defip_pipe2_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE2r}
  #define TH3_L3_DEFIP_PIPE3_MODE0 {th3_l3_defip_pipe3_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE3r}
  #define TH3_L3_DEFIP_PIPE4_MODE0 {th3_l3_defip_pipe4_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE4r}
  #define TH3_L3_DEFIP_PIPE5_MODE0 {th3_l3_defip_pipe5_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE5r}
  #define TH3_L3_DEFIP_PIPE6_MODE0 {th3_l3_defip_pipe6_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE6r}
  #define TH3_L3_DEFIP_PIPE7_MODE0 {th3_l3_defip_pipe7_mode0_name, 0, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_L3_DEFIP_PIPE0_MODE1 {th3_l3_defip_pipe0_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE0r}
  #define TH3_L3_DEFIP_PIPE1_MODE1 {th3_l3_defip_pipe1_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE1r}
  #define TH3_L3_DEFIP_PIPE2_MODE1 {th3_l3_defip_pipe2_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE2r}
  #define TH3_L3_DEFIP_PIPE3_MODE1 {th3_l3_defip_pipe3_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE3r}
  #define TH3_L3_DEFIP_PIPE4_MODE1 {th3_l3_defip_pipe4_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE4r}
  #define TH3_L3_DEFIP_PIPE5_MODE1 {th3_l3_defip_pipe5_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE5r}
  #define TH3_L3_DEFIP_PIPE6_MODE1 {th3_l3_defip_pipe6_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE6r}
  #define TH3_L3_DEFIP_PIPE7_MODE1 {th3_l3_defip_pipe7_mode1_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_L3_DEFIP_PIPE0_MODE2 {th3_l3_defip_pipe0_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE0r}
  #define TH3_L3_DEFIP_PIPE1_MODE2 {th3_l3_defip_pipe1_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE1r}
  #define TH3_L3_DEFIP_PIPE2_MODE2 {th3_l3_defip_pipe2_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE2r}
  #define TH3_L3_DEFIP_PIPE3_MODE2 {th3_l3_defip_pipe3_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE3r}
  #define TH3_L3_DEFIP_PIPE4_MODE2 {th3_l3_defip_pipe4_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE4r}
  #define TH3_L3_DEFIP_PIPE5_MODE2 {th3_l3_defip_pipe5_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE5r}
  #define TH3_L3_DEFIP_PIPE6_MODE2 {th3_l3_defip_pipe6_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE6r}
  #define TH3_L3_DEFIP_PIPE7_MODE2 {th3_l3_defip_pipe7_mode2_name, 1, NO_MODE_FIELD, L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 4, L3_DEFIP_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_VFP_PIPE0 {th3_vfp_pipe0_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE0r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE0r}
  #define TH3_VFP_PIPE1 {th3_vfp_pipe1_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE1r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE1r}
  #define TH3_VFP_PIPE2 {th3_vfp_pipe2_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE2r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE2r}
  #define TH3_VFP_PIPE3 {th3_vfp_pipe3_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE3r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE3r}
  #define TH3_VFP_PIPE4 {th3_vfp_pipe4_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE4r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE4r}
  #define TH3_VFP_PIPE5 {th3_vfp_pipe5_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE5r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE5r}
  #define TH3_VFP_PIPE6 {th3_vfp_pipe6_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE6r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE6r}
  #define TH3_VFP_PIPE7 {th3_vfp_pipe7_name, NO_MODE, NO_MODE_FIELD, VFP_CAM_BIST_CONFIG_64_PIPE7r, NO_CONTROL_REGISTER, NO_CONTROL_ENABLE_FIELD, 8, VFP_CAM_BIST_STATUS_PIPE7r}
  
  #define TH3_TOTAL_CAMBIST_COUNT 128
  
  #define TH3_DONE_BIT_MASK 0x00000001
  #define TH3_BIST_SUCCESS_MASK 0x00000002
  
  static char th3_cpu_cos_pipe0_name[] = "CPU_COS_PIPE0";
  static char th3_cpu_cos_pipe1_name[] = "CPU_COS_PIPE1";
  static char th3_cpu_cos_pipe2_name[] = "CPU_COS_PIPE2";
  static char th3_cpu_cos_pipe3_name[] = "CPU_COS_PIPE3";
  static char th3_cpu_cos_pipe4_name[] = "CPU_COS_PIPE4";
  static char th3_cpu_cos_pipe5_name[] = "CPU_COS_PIPE5";
  static char th3_cpu_cos_pipe6_name[] = "CPU_COS_PIPE6";
  static char th3_cpu_cos_pipe7_name[] = "CPU_COS_PIPE7";
  static char th3_efp_pipe0_slice0_name[] = "EFP_PIPE0_SLICE0";
  static char th3_efp_pipe0_slice1_name[] = "EFP_PIPE0_SLICE1";
  static char th3_efp_pipe0_slice2_name[] = "EFP_PIPE0_SLICE2";
  static char th3_efp_pipe0_slice3_name[] = "EFP_PIPE0_SLICE3";
  static char th3_efp_pipe1_slice0_name[] = "EFP_PIPE1_SLICE0";
  static char th3_efp_pipe1_slice1_name[] = "EFP_PIPE1_SLICE1";
  static char th3_efp_pipe1_slice2_name[] = "EFP_PIPE1_SLICE2";
  static char th3_efp_pipe1_slice3_name[] = "EFP_PIPE1_SLICE3";
  static char th3_efp_pipe2_slice0_name[] = "EFP_PIPE2_SLICE0";
  static char th3_efp_pipe2_slice1_name[] = "EFP_PIPE2_SLICE1";
  static char th3_efp_pipe2_slice2_name[] = "EFP_PIPE2_SLICE2";
  static char th3_efp_pipe2_slice3_name[] = "EFP_PIPE2_SLICE3";
  static char th3_efp_pipe3_slice0_name[] = "EFP_PIPE3_SLICE0";
  static char th3_efp_pipe3_slice1_name[] = "EFP_PIPE3_SLICE1";
  static char th3_efp_pipe3_slice2_name[] = "EFP_PIPE3_SLICE2";
  static char th3_efp_pipe3_slice3_name[] = "EFP_PIPE3_SLICE3";
  static char th3_efp_pipe4_slice0_name[] = "EFP_PIPE4_SLICE0";
  static char th3_efp_pipe4_slice1_name[] = "EFP_PIPE4_SLICE1";
  static char th3_efp_pipe4_slice2_name[] = "EFP_PIPE4_SLICE2";
  static char th3_efp_pipe4_slice3_name[] = "EFP_PIPE4_SLICE3";
  static char th3_efp_pipe5_slice0_name[] = "EFP_PIPE5_SLICE0";
  static char th3_efp_pipe5_slice1_name[] = "EFP_PIPE5_SLICE1";
  static char th3_efp_pipe5_slice2_name[] = "EFP_PIPE5_SLICE2";
  static char th3_efp_pipe5_slice3_name[] = "EFP_PIPE5_SLICE3";
  static char th3_efp_pipe6_slice0_name[] = "EFP_PIPE6_SLICE0";
  static char th3_efp_pipe6_slice1_name[] = "EFP_PIPE6_SLICE1";
  static char th3_efp_pipe6_slice2_name[] = "EFP_PIPE6_SLICE2";
  static char th3_efp_pipe6_slice3_name[] = "EFP_PIPE6_SLICE3";
  static char th3_efp_pipe7_slice0_name[] = "EFP_PIPE7_SLICE0";
  static char th3_efp_pipe7_slice1_name[] = "EFP_PIPE7_SLICE1";
  static char th3_efp_pipe7_slice2_name[] = "EFP_PIPE7_SLICE2";
  static char th3_efp_pipe7_slice3_name[] = "EFP_PIPE7_SLICE3";
  static char th3_exact_match_logical_table_select_pipe0_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0";
  static char th3_exact_match_logical_table_select_pipe1_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1";
  static char th3_exact_match_logical_table_select_pipe2_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2";
  static char th3_exact_match_logical_table_select_pipe3_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3";
  static char th3_exact_match_logical_table_select_pipe4_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4";
  static char th3_exact_match_logical_table_select_pipe5_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5";
  static char th3_exact_match_logical_table_select_pipe6_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6";
  static char th3_exact_match_logical_table_select_pipe7_name[] = "EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7";
  static char th3_ifp_tcam_pool0_pipe0_name[] = "IFP_TCAM_POOL0_PIPE0";
  static char th3_ifp_tcam_pool1_pipe0_name[] = "IFP_TCAM_POOL1_PIPE0";
  static char th3_ifp_tcam_pool2_pipe0_name[] = "IFP_TCAM_POOL2_PIPE0";
  static char th3_ifp_tcam_pool0_pipe1_name[] = "IFP_TCAM_POOL0_PIPE1";
  static char th3_ifp_tcam_pool1_pipe1_name[] = "IFP_TCAM_POOL1_PIPE1";
  static char th3_ifp_tcam_pool2_pipe1_name[] = "IFP_TCAM_POOL2_PIPE1";
  static char th3_ifp_tcam_pool0_pipe2_name[] = "IFP_TCAM_POOL0_PIPE2";
  static char th3_ifp_tcam_pool1_pipe2_name[] = "IFP_TCAM_POOL1_PIPE2";
  static char th3_ifp_tcam_pool2_pipe2_name[] = "IFP_TCAM_POOL2_PIPE2";
  static char th3_ifp_tcam_pool0_pipe3_name[] = "IFP_TCAM_POOL0_PIPE3";
  static char th3_ifp_tcam_pool1_pipe3_name[] = "IFP_TCAM_POOL1_PIPE3";
  static char th3_ifp_tcam_pool2_pipe3_name[] = "IFP_TCAM_POOL2_PIPE3";
  static char th3_ifp_tcam_pool0_pipe4_name[] = "IFP_TCAM_POOL0_PIPE4";
  static char th3_ifp_tcam_pool1_pipe4_name[] = "IFP_TCAM_POOL1_PIPE4";
  static char th3_ifp_tcam_pool2_pipe4_name[] = "IFP_TCAM_POOL2_PIPE4";
  static char th3_ifp_tcam_pool0_pipe5_name[] = "IFP_TCAM_POOL0_PIPE5";
  static char th3_ifp_tcam_pool1_pipe5_name[] = "IFP_TCAM_POOL1_PIPE5";
  static char th3_ifp_tcam_pool2_pipe5_name[] = "IFP_TCAM_POOL2_PIPE5";
  static char th3_ifp_tcam_pool0_pipe6_name[] = "IFP_TCAM_POOL0_PIPE6";
  static char th3_ifp_tcam_pool1_pipe6_name[] = "IFP_TCAM_POOL1_PIPE6";
  static char th3_ifp_tcam_pool2_pipe6_name[] = "IFP_TCAM_POOL2_PIPE6";
  static char th3_ifp_tcam_pool0_pipe7_name[] = "IFP_TCAM_POOL0_PIPE7";
  static char th3_ifp_tcam_pool1_pipe7_name[] = "IFP_TCAM_POOL1_PIPE7";
  static char th3_ifp_tcam_pool2_pipe7_name[] = "IFP_TCAM_POOL2_PIPE7";
  static char th3_ifp_logical_table_select_pipe0_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE0";
  static char th3_ifp_logical_table_select_pipe1_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE1";
  static char th3_ifp_logical_table_select_pipe2_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE2";
  static char th3_ifp_logical_table_select_pipe3_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE3";
  static char th3_ifp_logical_table_select_pipe4_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE4";
  static char th3_ifp_logical_table_select_pipe5_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE5";
  static char th3_ifp_logical_table_select_pipe6_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE6";
  static char th3_ifp_logical_table_select_pipe7_name[] = "IFP_LOGICAL_TABLE_SELECT_PIPE7";
  static char th3_l2_user_entry_pipe0_name[] = "L2_USER_ENTRY_PIPE0";
  static char th3_l2_user_entry_pipe1_name[] = "L2_USER_ENTRY_PIPE1";
  static char th3_l2_user_entry_pipe2_name[] = "L2_USER_ENTRY_PIPE2";
  static char th3_l2_user_entry_pipe3_name[] = "L2_USER_ENTRY_PIPE3";
  static char th3_l2_user_entry_pipe4_name[] = "L2_USER_ENTRY_PIPE4";
  static char th3_l2_user_entry_pipe5_name[] = "L2_USER_ENTRY_PIPE5";
  static char th3_l2_user_entry_pipe6_name[] = "L2_USER_ENTRY_PIPE6";
  static char th3_l2_user_entry_pipe7_name[] = "L2_USER_ENTRY_PIPE7";
  static char th3_l3_defip_pipe0_mode0_name[] = "L3_DEFIP_PIPE0_MODE0";
  static char th3_l3_defip_pipe1_mode0_name[] = "L3_DEFIP_PIPE1_MODE0";
  static char th3_l3_defip_pipe2_mode0_name[] = "L3_DEFIP_PIPE2_MODE0";
  static char th3_l3_defip_pipe3_mode0_name[] = "L3_DEFIP_PIPE3_MODE0";
  static char th3_l3_defip_pipe4_mode0_name[] = "L3_DEFIP_PIPE4_MODE0";
  static char th3_l3_defip_pipe5_mode0_name[] = "L3_DEFIP_PIPE5_MODE0";
  static char th3_l3_defip_pipe6_mode0_name[] = "L3_DEFIP_PIPE6_MODE0";
  static char th3_l3_defip_pipe7_mode0_name[] = "L3_DEFIP_PIPE7_MODE0";
  static char th3_l3_defip_pipe0_mode1_name[] = "L3_DEFIP_PIPE0_MODE1";
  static char th3_l3_defip_pipe1_mode1_name[] = "L3_DEFIP_PIPE1_MODE1";
  static char th3_l3_defip_pipe2_mode1_name[] = "L3_DEFIP_PIPE2_MODE1";
  static char th3_l3_defip_pipe3_mode1_name[] = "L3_DEFIP_PIPE3_MODE1";
  static char th3_l3_defip_pipe4_mode1_name[] = "L3_DEFIP_PIPE4_MODE1";
  static char th3_l3_defip_pipe5_mode1_name[] = "L3_DEFIP_PIPE5_MODE1";
  static char th3_l3_defip_pipe6_mode1_name[] = "L3_DEFIP_PIPE6_MODE1";
  static char th3_l3_defip_pipe7_mode1_name[] = "L3_DEFIP_PIPE7_MODE1";
  static char th3_l3_defip_pipe0_mode2_name[] = "L3_DEFIP_PIPE0_MODE2";
  static char th3_l3_defip_pipe1_mode2_name[] = "L3_DEFIP_PIPE1_MODE2";
  static char th3_l3_defip_pipe2_mode2_name[] = "L3_DEFIP_PIPE2_MODE2";
  static char th3_l3_defip_pipe3_mode2_name[] = "L3_DEFIP_PIPE3_MODE2";
  static char th3_l3_defip_pipe4_mode2_name[] = "L3_DEFIP_PIPE4_MODE2";
  static char th3_l3_defip_pipe5_mode2_name[] = "L3_DEFIP_PIPE5_MODE2";
  static char th3_l3_defip_pipe6_mode2_name[] = "L3_DEFIP_PIPE6_MODE2";
  static char th3_l3_defip_pipe7_mode2_name[] = "L3_DEFIP_PIPE7_MODE2";
  static char th3_udf_pipe0_name[] = "UDF_PIPE0";
  static char th3_udf_pipe1_name[] = "UDF_PIPE1";
  static char th3_udf_pipe2_name[] = "UDF_PIPE2";
  static char th3_udf_pipe3_name[] = "UDF_PIPE3";
  static char th3_udf_pipe4_name[] = "UDF_PIPE4";
  static char th3_udf_pipe5_name[] = "UDF_PIPE6";
  static char th3_udf_pipe6_name[] = "UDF_PIPE6";
  static char th3_udf_pipe7_name[] = "UDF_PIPE7";
  static char th3_vfp_pipe0_name[] = "VFP_PIPE0";
  static char th3_vfp_pipe1_name[] = "VFP_PIPE1";
  static char th3_vfp_pipe2_name[] = "VFP_PIPE2";
  static char th3_vfp_pipe3_name[] = "VFP_PIPE3";
  static char th3_vfp_pipe4_name[] = "VFP_PIPE4";
  static char th3_vfp_pipe5_name[] = "VFP_PIPE5";
  static char th3_vfp_pipe6_name[] = "VFP_PIPE6";
  static char th3_vfp_pipe7_name[] = "VFP_PIPE7";
  
  static cambist_t th3_cambist_array[] = {
                                          TH3_CPU_COS_PIPE0,
                                          TH3_CPU_COS_PIPE1,
                                          TH3_CPU_COS_PIPE2,
                                          TH3_CPU_COS_PIPE3,
                                          TH3_CPU_COS_PIPE4,
                                          TH3_CPU_COS_PIPE5,
                                          TH3_CPU_COS_PIPE6,
                                          TH3_CPU_COS_PIPE7,
                                          TH3_EFP_PIPE0_SLICE0,
                                          TH3_EFP_PIPE0_SLICE1,
                                          TH3_EFP_PIPE0_SLICE2,
                                          TH3_EFP_PIPE0_SLICE3,
                                          TH3_EFP_PIPE1_SLICE0,
                                          TH3_EFP_PIPE1_SLICE1,
                                          TH3_EFP_PIPE1_SLICE2,
                                          TH3_EFP_PIPE1_SLICE3,
                                          TH3_EFP_PIPE2_SLICE0,
                                          TH3_EFP_PIPE2_SLICE1,
                                          TH3_EFP_PIPE2_SLICE2,
                                          TH3_EFP_PIPE2_SLICE3,
                                          TH3_EFP_PIPE3_SLICE0,
                                          TH3_EFP_PIPE3_SLICE1,
                                          TH3_EFP_PIPE3_SLICE2,
                                          TH3_EFP_PIPE3_SLICE3,
                                          TH3_EFP_PIPE4_SLICE0,
                                          TH3_EFP_PIPE4_SLICE1,
                                          TH3_EFP_PIPE4_SLICE2,
                                          TH3_EFP_PIPE4_SLICE3,
                                          TH3_EFP_PIPE5_SLICE0,
                                          TH3_EFP_PIPE5_SLICE1,
                                          TH3_EFP_PIPE5_SLICE2,
                                          TH3_EFP_PIPE5_SLICE3,
                                          TH3_EFP_PIPE6_SLICE0,
                                          TH3_EFP_PIPE6_SLICE1,
                                          TH3_EFP_PIPE6_SLICE2,
                                          TH3_EFP_PIPE6_SLICE3,
                                          TH3_EFP_PIPE7_SLICE0,
                                          TH3_EFP_PIPE7_SLICE1,
                                          TH3_EFP_PIPE7_SLICE2,
                                          TH3_EFP_PIPE7_SLICE3,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6,
                                          TH3_EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7,
                                          TH3_IFP_TCAM_POOL0_PIPE0,
                                          TH3_IFP_TCAM_POOL1_PIPE0,
                                          TH3_IFP_TCAM_POOL2_PIPE0,
                                          TH3_IFP_TCAM_POOL0_PIPE1,
                                          TH3_IFP_TCAM_POOL1_PIPE1,
                                          TH3_IFP_TCAM_POOL2_PIPE1,
                                          TH3_IFP_TCAM_POOL0_PIPE2,
                                          TH3_IFP_TCAM_POOL1_PIPE2,
                                          TH3_IFP_TCAM_POOL2_PIPE2,
                                          TH3_IFP_TCAM_POOL0_PIPE3,
                                          TH3_IFP_TCAM_POOL1_PIPE3,
                                          TH3_IFP_TCAM_POOL2_PIPE3,
                                          TH3_IFP_TCAM_POOL0_PIPE4,
                                          TH3_IFP_TCAM_POOL1_PIPE4,
                                          TH3_IFP_TCAM_POOL2_PIPE4,
                                          TH3_IFP_TCAM_POOL0_PIPE5,
                                          TH3_IFP_TCAM_POOL1_PIPE5,
                                          TH3_IFP_TCAM_POOL2_PIPE5,
                                          TH3_IFP_TCAM_POOL0_PIPE6,
                                          TH3_IFP_TCAM_POOL1_PIPE6,
                                          TH3_IFP_TCAM_POOL2_PIPE6,
                                          TH3_IFP_TCAM_POOL0_PIPE7,
                                          TH3_IFP_TCAM_POOL1_PIPE7,
                                          TH3_IFP_TCAM_POOL2_PIPE7,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE0,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE1,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE2,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE3,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE4,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE5,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE6,
                                          TH3_IFP_LOGICAL_TABLE_SELECT_PIPE7,
                                          TH3_L2_USER_ENTRY_PIPE0,
                                          TH3_L2_USER_ENTRY_PIPE1,
                                          TH3_L2_USER_ENTRY_PIPE2,
                                          TH3_L2_USER_ENTRY_PIPE3,
                                          TH3_L2_USER_ENTRY_PIPE4,
                                          TH3_L2_USER_ENTRY_PIPE5,
                                          TH3_L2_USER_ENTRY_PIPE6,
                                          TH3_L2_USER_ENTRY_PIPE7,
                                          TH3_L3_DEFIP_PIPE0_MODE0,
                                          TH3_L3_DEFIP_PIPE1_MODE0,
                                          TH3_L3_DEFIP_PIPE2_MODE0,
                                          TH3_L3_DEFIP_PIPE3_MODE0,
                                          TH3_L3_DEFIP_PIPE4_MODE0,
                                          TH3_L3_DEFIP_PIPE5_MODE0,
                                          TH3_L3_DEFIP_PIPE6_MODE0,
                                          TH3_L3_DEFIP_PIPE7_MODE0,
                                          TH3_L3_DEFIP_PIPE0_MODE1,
                                          TH3_L3_DEFIP_PIPE1_MODE1,
                                          TH3_L3_DEFIP_PIPE2_MODE1,
                                          TH3_L3_DEFIP_PIPE3_MODE1,
                                          TH3_L3_DEFIP_PIPE4_MODE1,
                                          TH3_L3_DEFIP_PIPE5_MODE1,
                                          TH3_L3_DEFIP_PIPE6_MODE1,
                                          TH3_L3_DEFIP_PIPE7_MODE1,
                                          TH3_L3_DEFIP_PIPE0_MODE2,
                                          TH3_L3_DEFIP_PIPE1_MODE2,
                                          TH3_L3_DEFIP_PIPE2_MODE2,
                                          TH3_L3_DEFIP_PIPE3_MODE2,
                                          TH3_L3_DEFIP_PIPE4_MODE2,
                                          TH3_L3_DEFIP_PIPE5_MODE2,
                                          TH3_L3_DEFIP_PIPE6_MODE2,
                                          TH3_L3_DEFIP_PIPE7_MODE2,
                                          TH3_UDF_PIPE0,
                                          TH3_UDF_PIPE1,
                                          TH3_UDF_PIPE2,
                                          TH3_UDF_PIPE3,
                                          TH3_UDF_PIPE4,
                                          TH3_UDF_PIPE5,
                                          TH3_UDF_PIPE6,
                                          TH3_UDF_PIPE7,
                                          TH3_VFP_PIPE0,
                                          TH3_VFP_PIPE1,
                                          TH3_VFP_PIPE2,
                                          TH3_VFP_PIPE3,
                                          TH3_VFP_PIPE4,
                                          TH3_VFP_PIPE5,
                                          TH3_VFP_PIPE6,
                                          TH3_VFP_PIPE7
                                      };
  