text: /**
    ******************************************************************************
    * @file    stm32wbxx_ll_spi.h
    * @author  MCD Application Team
    * @brief   Header file of SPI LL module.
    ******************************************************************************
    * @attention
    *
    * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
    * All rights reserved.</center></h2>
    *
    * This software component is licensed by ST under BSD 3-Clause license,
    * the "License"; You may not use this file except in compliance with the
    * License. You may obtain a copy of the License at:
    *                        opensource.org/licenses/BSD-3-Clause
    *
    ******************************************************************************
    */
  
  /* Define to prevent recursive inclusion -------------------------------------*/
  #ifndef STM32WBxx_LL_SPI_H
  #define STM32WBxx_LL_SPI_H
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /* Includes ------------------------------------------------------------------*/
  #include "stm32wbxx.h"
  
  /** @addtogroup STM32WBxx_LL_Driver
    * @{
    */
  
  #if defined (SPI1) || defined (SPI2)
  
  /** @defgroup SPI_LL SPI
    * @{
    */
  
  /* Private types -------------------------------------------------------------*/
  /* Private variables ---------------------------------------------------------*/
  /* Private macros ------------------------------------------------------------*/
  
  /* Exported types ------------------------------------------------------------*/
  #if defined(USE_FULL_LL_DRIVER)
  /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
    * @{
    */
  
  /**
    * @brief  SPI Init structures definition
    */
  typedef struct
  {
    uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
                                           This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
  
    uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
                                           This parameter can be a value of @ref SPI_LL_EC_MODE.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
  
    uint32_t DataWidth;               /*!< Specifies the SPI data width.
                                           This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
  
    uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
                                           This parameter can be a value of @ref SPI_LL_EC_POLARITY.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
  
    uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
                                           This parameter can be a value of @ref SPI_LL_EC_PHASE.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
  
    uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
                                           This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
  
    uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
                                           This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
                                           @note The communication clock is derived from the master clock. The slave clock does not need to be set.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
  
    uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
                                           This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
  
    uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
                                           This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
  
                                           This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
  
    uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
                                           This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
  
                                           This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
  
  } LL_SPI_InitTypeDef;
  
  /**
    * @}
    */
  #endif /* USE_FULL_LL_DRIVER */
  
  /* Exported constants --------------------------------------------------------*/
  /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
    * @{
    */
  
  /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
    * @brief    Flags defines which can be used with LL_SPI_ReadReg function
    * @{
    */
  #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
  #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
  #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
  #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
  #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
  #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
  #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_IT IT Defines
    * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
    * @{
    */
  #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
  #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
  #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_MODE Operation Mode
    * @{
    */
  #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
  #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
    * @{
    */
  #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
  #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_PHASE Clock Phase
    * @{
    */
  #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
  #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
    * @{
    */
  #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
  #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
    * @{
    */
  #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
  #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
  #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
  #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
  #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
  #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
  #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
  #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
    * @{
    */
  #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
  #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
    * @{
    */
  #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
  #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
  #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
  #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
    * @{
    */
  #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
  #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
  #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
    * @{
    */
  #define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
  #define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
  #define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
  #define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
  #define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
  #define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
  #define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
  #define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
  #define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
  #define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
  #define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
  #define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
  #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
  /**
    * @}
    */
  #if defined(USE_FULL_LL_DRIVER)
  
  /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
    * @{
    */
  #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
  #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
  /**
    * @}
    */
  #endif /* USE_FULL_LL_DRIVER */
  
  /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
    * @{
    */
  #define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
  #define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
    * @{
    */
  #define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
  #define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)  */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
    * @{
    */
  #define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
  #define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
  #define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
  #define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
    * @{
    */
  #define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
  #define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
  #define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
  #define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
    * @{
    */
  #define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
  #define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
  
  /**
    * @}
    */
  
  /**
    * @}
    */
  
  /* Exported macro ------------------------------------------------------------*/
  /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
    * @{
    */
  
  /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
    * @{
    */
  
  /**
    * @brief  Write a value in SPI register
    * @param  __INSTANCE__ SPI Instance
    * @param  __REG__ Register to be written
    * @param  __VALUE__ Value to be written in the register
    * @retval None
    */
  #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  
  /**
    * @brief  Read a value in SPI register
    * @param  __INSTANCE__ SPI Instance
    * @param  __REG__ Register to be read
    * @retval Register value
    */
  #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  /**
    * @}
    */
  
  /**
    * @}
    */
  
  /* Exported functions --------------------------------------------------------*/
  /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
    * @{
    */
  
  /** @defgroup SPI_LL_EF_Configuration Configuration
    * @{
    */
  
  /**
    * @brief  Enable SPI peripheral
    * @rmtoll CR1          SPE           LL_SPI_Enable
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR1, SPI_CR1_SPE);
  }
  
  /**
    * @brief  Disable SPI peripheral
    * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
    * @rmtoll CR1          SPE           LL_SPI_Disable
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  }
  
  /**
    * @brief  Check if SPI peripheral is enabled
    * @rmtoll CR1          SPE           LL_SPI_IsEnabled
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Set SPI operation mode to Master or Slave
    * @note   This bit should not be changed when communication is ongoing.
    * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
    *         CR1          SSI           LL_SPI_SetMode
    * @param  SPIx SPI Instance
    * @param  Mode This parameter can be one of the following values:
    *         @arg @ref LL_SPI_MODE_MASTER
    *         @arg @ref LL_SPI_MODE_SLAVE
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
  }
  
  /**
    * @brief  Get SPI operation mode (Master or Slave)
    * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
    *         CR1          SSI           LL_SPI_GetMode
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_MODE_MASTER
    *         @arg @ref LL_SPI_MODE_SLAVE
    */
  __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
  }
  
  /**
    * @brief  Set serial protocol used
    * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
    * @rmtoll CR2          FRF           LL_SPI_SetStandard
    * @param  SPIx SPI Instance
    * @param  Standard This parameter can be one of the following values:
    *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
    *         @arg @ref LL_SPI_PROTOCOL_TI
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  {
    MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
  }
  
  /**
    * @brief  Get serial protocol used
    * @rmtoll CR2          FRF           LL_SPI_GetStandard
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
    *         @arg @ref LL_SPI_PROTOCOL_TI
    */
  __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
  }
  
  /**
    * @brief  Set clock phase
    * @note   This bit should not be changed when communication is ongoing.
    *         This bit is not used in SPI TI mode.
    * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
    * @param  SPIx SPI Instance
    * @param  ClockPhase This parameter can be one of the following values:
    *         @arg @ref LL_SPI_PHASE_1EDGE
    *         @arg @ref LL_SPI_PHASE_2EDGE
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
  }
  
  /**
    * @brief  Get clock phase
    * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_PHASE_1EDGE
    *         @arg @ref LL_SPI_PHASE_2EDGE
    */
  __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
  }
  
  /**
    * @brief  Set clock polarity
    * @note   This bit should not be changed when communication is ongoing.
    *         This bit is not used in SPI TI mode.
    * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
    * @param  SPIx SPI Instance
    * @param  ClockPolarity This parameter can be one of the following values:
    *         @arg @ref LL_SPI_POLARITY_LOW
    *         @arg @ref LL_SPI_POLARITY_HIGH
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
  }
  
  /**
    * @brief  Get clock polarity
    * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_POLARITY_LOW
    *         @arg @ref LL_SPI_POLARITY_HIGH
    */
  __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
  }
  
  /**
    * @brief  Set baud rate prescaler
    * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
    * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
    * @param  SPIx SPI Instance
    * @param  BaudRate This parameter can be one of the following values:
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
  }
  
  /**
    * @brief  Get baud rate prescaler
    * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
    *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
    */
  __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
  }
  
  /**
    * @brief  Set transfer bit order
    * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
    * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
    * @param  SPIx SPI Instance
    * @param  BitOrder This parameter can be one of the following values:
    *         @arg @ref LL_SPI_LSB_FIRST
    *         @arg @ref LL_SPI_MSB_FIRST
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
  }
  
  /**
    * @brief  Get transfer bit order
    * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_LSB_FIRST
    *         @arg @ref LL_SPI_MSB_FIRST
    */
  __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
  }
  
  /**
    * @brief  Set transfer direction mode
    * @note   For Half-Duplex mode, Rx Direction is set by default.
    *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
    * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
    *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
    *         CR1          BIDIOE        LL_SPI_SetTransferDirection
    * @param  SPIx SPI Instance
    * @param  TransferDirection This parameter can be one of the following values:
    *         @arg @ref LL_SPI_FULL_DUPLEX
    *         @arg @ref LL_SPI_SIMPLEX_RX
    *         @arg @ref LL_SPI_HALF_DUPLEX_RX
    *         @arg @ref LL_SPI_HALF_DUPLEX_TX
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
  }
  
  /**
    * @brief  Get transfer direction mode
    * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
    *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
    *         CR1          BIDIOE        LL_SPI_GetTransferDirection
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_FULL_DUPLEX
    *         @arg @ref LL_SPI_SIMPLEX_RX
    *         @arg @ref LL_SPI_HALF_DUPLEX_RX
    *         @arg @ref LL_SPI_HALF_DUPLEX_TX
    */
  __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
  }
  
  /**
    * @brief  Set frame data width
    * @rmtoll CR2          DS            LL_SPI_SetDataWidth
    * @param  SPIx SPI Instance
    * @param  DataWidth This parameter can be one of the following values:
    *         @arg @ref LL_SPI_DATAWIDTH_4BIT
    *         @arg @ref LL_SPI_DATAWIDTH_5BIT
    *         @arg @ref LL_SPI_DATAWIDTH_6BIT
    *         @arg @ref LL_SPI_DATAWIDTH_7BIT
    *         @arg @ref LL_SPI_DATAWIDTH_8BIT
    *         @arg @ref LL_SPI_DATAWIDTH_9BIT
    *         @arg @ref LL_SPI_DATAWIDTH_10BIT
    *         @arg @ref LL_SPI_DATAWIDTH_11BIT
    *         @arg @ref LL_SPI_DATAWIDTH_12BIT
    *         @arg @ref LL_SPI_DATAWIDTH_13BIT
    *         @arg @ref LL_SPI_DATAWIDTH_14BIT
    *         @arg @ref LL_SPI_DATAWIDTH_15BIT
    *         @arg @ref LL_SPI_DATAWIDTH_16BIT
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
  {
    MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
  }
  
  /**
    * @brief  Get frame data width
    * @rmtoll CR2          DS            LL_SPI_GetDataWidth
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_DATAWIDTH_4BIT
    *         @arg @ref LL_SPI_DATAWIDTH_5BIT
    *         @arg @ref LL_SPI_DATAWIDTH_6BIT
    *         @arg @ref LL_SPI_DATAWIDTH_7BIT
    *         @arg @ref LL_SPI_DATAWIDTH_8BIT
    *         @arg @ref LL_SPI_DATAWIDTH_9BIT
    *         @arg @ref LL_SPI_DATAWIDTH_10BIT
    *         @arg @ref LL_SPI_DATAWIDTH_11BIT
    *         @arg @ref LL_SPI_DATAWIDTH_12BIT
    *         @arg @ref LL_SPI_DATAWIDTH_13BIT
    *         @arg @ref LL_SPI_DATAWIDTH_14BIT
    *         @arg @ref LL_SPI_DATAWIDTH_15BIT
    *         @arg @ref LL_SPI_DATAWIDTH_16BIT
    */
  __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
  }
  
  /**
    * @brief  Set threshold of RXFIFO that triggers an RXNE event
    * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
    * @param  SPIx SPI Instance
    * @param  Threshold This parameter can be one of the following values:
    *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
    *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
  {
    MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
  }
  
  /**
    * @brief  Get threshold of RXFIFO that triggers an RXNE event
    * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
    *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
    */
  __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
  }
  
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EF_CRC_Management CRC Management
    * @{
    */
  
  /**
    * @brief  Enable CRC
    * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
    * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  }
  
  /**
    * @brief  Disable CRC
    * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
    * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  }
  
  /**
    * @brief  Check if CRC is enabled
    * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
    * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Set CRC Length
    * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
    * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
    * @param  SPIx SPI Instance
    * @param  CRCLength This parameter can be one of the following values:
    *         @arg @ref LL_SPI_CRC_8BIT
    *         @arg @ref LL_SPI_CRC_16BIT
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
  }
  
  /**
    * @brief  Get CRC Length
    * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_CRC_8BIT
    *         @arg @ref LL_SPI_CRC_16BIT
    */
  __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
  }
  
  /**
    * @brief  Set CRCNext to transfer CRC on the line
    * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
    * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
  }
  
  /**
    * @brief  Set polynomial for CRC calculation
    * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
    * @param  SPIx SPI Instance
    * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
  {
    WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
  }
  
  /**
    * @brief  Get polynomial for CRC calculation
    * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
    * @param  SPIx SPI Instance
    * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
    */
  __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_REG(SPIx->CRCPR));
  }
  
  /**
    * @brief  Get Rx CRC
    * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
    * @param  SPIx SPI Instance
    * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
    */
  __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_REG(SPIx->RXCRCR));
  }
  
  /**
    * @brief  Get Tx CRC
    * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
    * @param  SPIx SPI Instance
    * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
    */
  __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_REG(SPIx->TXCRCR));
  }
  
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
    * @{
    */
  
  /**
    * @brief  Set NSS mode
    * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
    * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
    * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
    * @param  SPIx SPI Instance
    * @param  NSS This parameter can be one of the following values:
    *         @arg @ref LL_SPI_NSS_SOFT
    *         @arg @ref LL_SPI_NSS_HARD_INPUT
    *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
  {
    MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
    MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
  }
  
  /**
    * @brief  Get NSS mode
    * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
    * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_NSS_SOFT
    *         @arg @ref LL_SPI_NSS_HARD_INPUT
    *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
    */
  __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
  {
    uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
    uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
    return (Ssm | Ssoe);
  }
  
  /**
    * @brief  Enable NSS pulse management
    * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
    * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
  }
  
  /**
    * @brief  Disable NSS pulse management
    * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
    * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
  }
  
  /**
    * @brief  Check if NSS pulse is enabled
    * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
    * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
  }
  
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
    * @{
    */
  
  /**
    * @brief  Check if Rx buffer is not empty
    * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Check if Tx buffer is empty
    * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Get CRC error flag
    * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Get mode fault error flag
    * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Get overrun error flag
    * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Get busy flag
    * @note   The BSY flag is cleared under any one of the following conditions:
    * -When the SPI is correctly disabled
    * -When a fault is detected in Master mode (MODF bit set to 1)
    * -In Master mode, when it finishes a data transmission and no new data is ready to be
    * sent
    * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
    * each data transfer.
    * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Get frame format error flag
    * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Get FIFO reception Level
    * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_RX_FIFO_EMPTY
    *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
    *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
    *         @arg @ref LL_SPI_RX_FIFO_FULL
    */
  __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
  }
  
  /**
    * @brief  Get FIFO Transmission Level
    * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_TX_FIFO_EMPTY
    *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
    *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
    *         @arg @ref LL_SPI_TX_FIFO_FULL
    */
  __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
  }
  
  /**
    * @brief  Clear CRC error flag
    * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
  }
  
  /**
    * @brief  Clear mode fault error flag
    * @note   Clearing this flag is done by a read access to the SPIx_SR
    *         register followed by a write access to the SPIx_CR1 register
    * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
  {
    __IO uint32_t tmpreg_sr;
    tmpreg_sr = SPIx->SR;
    (void) tmpreg_sr;
    CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  }
  
  /**
    * @brief  Clear overrun error flag
    * @note   Clearing this flag is done by a read access to the SPIx_DR
    *         register followed by a read access to the SPIx_SR register
    * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
  {
    __IO uint32_t tmpreg;
    tmpreg = SPIx->DR;
    (void) tmpreg;
    tmpreg = SPIx->SR;
    (void) tmpreg;
  }
  
  /**
    * @brief  Clear frame format error flag
    * @note   Clearing this flag is done by reading SPIx_SR register
    * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
  {
    __IO uint32_t tmpreg;
    tmpreg = SPIx->SR;
    (void) tmpreg;
  }
  
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
    * @{
    */
  
  /**
    * @brief  Enable error interrupt
    * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
    * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  }
  
  /**
    * @brief  Enable Rx buffer not empty interrupt
    * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  }
  
  /**
    * @brief  Enable Tx buffer empty interrupt
    * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  }
  
  /**
    * @brief  Disable error interrupt
    * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
    * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  }
  
  /**
    * @brief  Disable Rx buffer not empty interrupt
    * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  }
  
  /**
    * @brief  Disable Tx buffer empty interrupt
    * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  }
  
  /**
    * @brief  Check if error interrupt is enabled
    * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Check if Rx buffer not empty interrupt is enabled
    * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Check if Tx buffer empty interrupt
    * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
  }
  
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EF_DMA_Management DMA Management
    * @{
    */
  
  /**
    * @brief  Enable DMA Rx
    * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  }
  
  /**
    * @brief  Disable DMA Rx
    * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  }
  
  /**
    * @brief  Check if DMA Rx is enabled
    * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Enable DMA Tx
    * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  {
    SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  }
  
  /**
    * @brief  Disable DMA Tx
    * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
    * @param  SPIx SPI Instance
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  {
    CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  }
  
  /**
    * @brief  Check if DMA Tx is enabled
    * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
    * @param  SPIx SPI Instance
    * @retval State of bit (1 or 0).
    */
  __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  {
    return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
  }
  
  /**
    * @brief  Set parity of  Last DMA reception
    * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
    * @param  SPIx SPI Instance
    * @param  Parity This parameter can be one of the following values:
    *         @arg @ref LL_SPI_DMA_PARITY_ODD
    *         @arg @ref LL_SPI_DMA_PARITY_EVEN
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
  {
    MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
  }
  
  /**
    * @brief  Get parity configuration for  Last DMA reception
    * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_DMA_PARITY_ODD
    *         @arg @ref LL_SPI_DMA_PARITY_EVEN
    */
  __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
  }
  
  /**
    * @brief  Set parity of  Last DMA transmission
    * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
    * @param  SPIx SPI Instance
    * @param  Parity This parameter can be one of the following values:
    *         @arg @ref LL_SPI_DMA_PARITY_ODD
    *         @arg @ref LL_SPI_DMA_PARITY_EVEN
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
  {
    MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
  }
  
  /**
    * @brief  Get parity configuration for Last DMA transmission
    * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
    * @param  SPIx SPI Instance
    * @retval Returned value can be one of the following values:
    *         @arg @ref LL_SPI_DMA_PARITY_ODD
    *         @arg @ref LL_SPI_DMA_PARITY_EVEN
    */
  __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
  {
    return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
  }
  
  /**
    * @brief  Get the data register address used for DMA transfer
    * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
    * @param  SPIx SPI Instance
    * @retval Address of data register
    */
  __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
  {
    return (uint32_t) &(SPIx->DR);
  }
  
  /**
    * @}
    */
  
  /** @defgroup SPI_LL_EF_DATA_Management DATA Management
    * @{
    */
  
  /**
    * @brief  Read 8-Bits in the data register
    * @rmtoll DR           DR            LL_SPI_ReceiveData8
    * @param  SPIx SPI Instance
    * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
    */
  __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
  {
    return (uint8_t)(READ_REG(SPIx->DR));
  }
  
  /**
    * @brief  Read 16-Bits in the data register
    * @rmtoll DR           DR            LL_SPI_ReceiveData16
    * @param  SPIx SPI Instance
    * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
    */
  __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
  {
    return (uint16_t)(READ_REG(SPIx->DR));
  }
  
  /**
    * @brief  Write 8-Bits in the data register
    * @rmtoll DR           DR            LL_SPI_TransmitData8
    * @param  SPIx SPI Instance
    * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
  {
  #if defined (__GNUC__)
    __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
    *spidr = TxData;
  #else
    *((__IO uint8_t *)&SPIx->DR) = TxData;
  #endif /* __GNUC__ */
  }
  
  /**
    * @brief  Write 16-Bits in the data register
    * @rmtoll DR           DR            LL_SPI_TransmitData16
    * @param  SPIx SPI Instance
    * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
    * @retval None
    */
  __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  {
  #if defined (__GNUC__)
    __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
    *spidr = TxData;
  #else
    SPIx->DR = TxData;
  #endif /* __GNUC__ */
  }
  
  /**
    * @}
    */
  #if defined(USE_FULL_LL_DRIVER)
  /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
    * @{
    */
  
  ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
  ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
  void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
  
  /**
    * @}
    */
  #endif /* USE_FULL_LL_DRIVER */
  /**
    * @}
    */
  
  /**
    * @}
    */
  
  #endif /* defined (SPI1) || defined (SPI2) */
  
  /**
    * @}
    */
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* STM32WBxx_LL_SPI_H */
  
  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  