text: /*******************************************************************************
  * File Name: cyfitter_gpio.h
  * 
  * PSoC Creator  4.2
  *
  * Description:
  * 
  * This file is automatically generated by PSoC Creator.
  *
  ********************************************************************************
  * Copyright (c) 2007-2018 Cypress Semiconductor.  All rights reserved.
  * You may use this file only in accordance with the license, terms, conditions, 
  * disclaimers, and limitations in the end user license agreement accompanying 
  * the software package with which this file was provided.
  ********************************************************************************/
  
  #ifndef INCLUDED_CYFITTER_GPIO_H
  #define INCLUDED_CYFITTER_GPIO_H
  #include "cy_device_headers.h"
  
  /* SW2 */
  #define SW2_0_DRIVEMODE CY_GPIO_DM_PULLUP
  #define SW2_0_INBUF_ENABLED 1u
  #define SW2_0_INIT_DRIVESTATE 1u
  #define SW2_0_INIT_MUXSEL 0u
  #define SW2_0_INPUT_SYNC 2u
  #define SW2_0_INTERRUPT_MODE CY_GPIO_INTR_FALLING
  #define SW2_0_NUM 4u
  #define SW2_0_PORT GPIO_PRT0
  #define SW2_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define SW2_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
  #define SW2_INBUF_ENABLED 1u
  #define SW2_INIT_DRIVESTATE 1u
  #define SW2_INIT_MUXSEL 0u
  #define SW2_INPUT_SYNC 2u
  #define SW2_INTERRUPT_MODE CY_GPIO_INTR_FALLING
  #define SW2_NUM 4u
  #define SW2_PORT GPIO_PRT0
  #define SW2_SLEWRATE CY_GPIO_SLEW_FAST
  #define SW2_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* SW3 */
  #define SW3_0_DRIVEMODE CY_GPIO_DM_PULLUP
  #define SW3_0_INBUF_ENABLED 1u
  #define SW3_0_INIT_DRIVESTATE 1u
  #define SW3_0_INIT_MUXSEL 0u
  #define SW3_0_INPUT_SYNC 2u
  #define SW3_0_INTERRUPT_MODE CY_GPIO_INTR_BOTH
  #define SW3_0_NUM 4u
  #define SW3_0_PORT GPIO_PRT10
  #define SW3_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define SW3_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define SW3_DRIVEMODE CY_GPIO_DM_PULLUP
  #define SW3_INBUF_ENABLED 1u
  #define SW3_INIT_DRIVESTATE 1u
  #define SW3_INIT_MUXSEL 0u
  #define SW3_INPUT_SYNC 2u
  #define SW3_INTERRUPT_MODE CY_GPIO_INTR_BOTH
  #define SW3_NUM 4u
  #define SW3_PORT GPIO_PRT10
  #define SW3_SLEWRATE CY_GPIO_SLEW_FAST
  #define SW3_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* ULF_BB */
  #define ULF_BB_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_BB_0_INBUF_ENABLED 0u
  #define ULF_BB_0_INIT_DRIVESTATE 0u
  #define ULF_BB_0_INIT_MUXSEL 0u
  #define ULF_BB_0_INPUT_SYNC 2u
  #define ULF_BB_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_BB_0_NUM 3u
  #define ULF_BB_0_PORT GPIO_PRT6
  #define ULF_BB_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_BB_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define ULF_BB_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_BB_INBUF_ENABLED 0u
  #define ULF_BB_INIT_DRIVESTATE 0u
  #define ULF_BB_INIT_MUXSEL 0u
  #define ULF_BB_INPUT_SYNC 2u
  #define ULF_BB_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_BB_NUM 3u
  #define ULF_BB_PORT GPIO_PRT6
  #define ULF_BB_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_BB_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* ULF_BO */
  #define ULF_BO_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_BO_0_INBUF_ENABLED 0u
  #define ULF_BO_0_INIT_DRIVESTATE 0u
  #define ULF_BO_0_INIT_MUXSEL 0u
  #define ULF_BO_0_INPUT_SYNC 2u
  #define ULF_BO_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_BO_0_NUM 6u
  #define ULF_BO_0_PORT GPIO_PRT10
  #define ULF_BO_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_BO_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define ULF_BO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_BO_INBUF_ENABLED 0u
  #define ULF_BO_INIT_DRIVESTATE 0u
  #define ULF_BO_INIT_MUXSEL 0u
  #define ULF_BO_INPUT_SYNC 2u
  #define ULF_BO_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_BO_NUM 6u
  #define ULF_BO_PORT GPIO_PRT10
  #define ULF_BO_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_BO_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* ULF_IN */
  #define ULF_IN_0_DRIVEMODE CY_GPIO_DM_HIGHZ
  #define ULF_IN_0_INBUF_ENABLED 1u
  #define ULF_IN_0_INIT_DRIVESTATE 0u
  #define ULF_IN_0_INIT_MUXSEL 0u
  #define ULF_IN_0_INPUT_SYNC 2u
  #define ULF_IN_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_IN_0_NUM 6u
  #define ULF_IN_0_PORT GPIO_PRT13
  #define ULF_IN_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_IN_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define ULF_IN_DRIVEMODE CY_GPIO_DM_HIGHZ
  #define ULF_IN_INBUF_ENABLED 1u
  #define ULF_IN_INIT_DRIVESTATE 0u
  #define ULF_IN_INIT_MUXSEL 0u
  #define ULF_IN_INPUT_SYNC 2u
  #define ULF_IN_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_IN_NUM 6u
  #define ULF_IN_PORT GPIO_PRT13
  #define ULF_IN_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_IN_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* Red_LED */
  #define Red_LED_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define Red_LED_0_INBUF_ENABLED 0u
  #define Red_LED_0_INIT_DRIVESTATE 0u
  #define Red_LED_0_INIT_MUXSEL 0u
  #define Red_LED_0_INPUT_SYNC 2u
  #define Red_LED_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define Red_LED_0_NUM 7u
  #define Red_LED_0_PORT GPIO_PRT13
  #define Red_LED_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define Red_LED_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define Red_LED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define Red_LED_INBUF_ENABLED 0u
  #define Red_LED_INIT_DRIVESTATE 0u
  #define Red_LED_INIT_MUXSEL 0u
  #define Red_LED_INPUT_SYNC 2u
  #define Red_LED_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define Red_LED_NUM 7u
  #define Red_LED_PORT GPIO_PRT13
  #define Red_LED_SLEWRATE CY_GPIO_SLEW_FAST
  #define Red_LED_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* ULF_OUT */
  #define ULF_OUT_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_OUT_0_INBUF_ENABLED 0u
  #define ULF_OUT_0_INIT_DRIVESTATE 1u
  #define ULF_OUT_0_INIT_MUXSEL 3u
  #define ULF_OUT_0_INPUT_SYNC 2u
  #define ULF_OUT_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_OUT_0_NUM 2u
  #define ULF_OUT_0_PORT GPIO_PRT6
  #define ULF_OUT_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_OUT_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define ULF_OUT_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_OUT_INBUF_ENABLED 0u
  #define ULF_OUT_INIT_DRIVESTATE 1u
  #define ULF_OUT_INIT_MUXSEL 3u
  #define ULF_OUT_INPUT_SYNC 2u
  #define ULF_OUT_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_OUT_NUM 2u
  #define ULF_OUT_PORT GPIO_PRT6
  #define ULF_OUT_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_OUT_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* ULF_TXen */
  #define ULF_TXen_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_TXen_0_INBUF_ENABLED 0u
  #define ULF_TXen_0_INIT_DRIVESTATE 0u
  #define ULF_TXen_0_INIT_MUXSEL 0u
  #define ULF_TXen_0_INPUT_SYNC 2u
  #define ULF_TXen_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_TXen_0_NUM 5u
  #define ULF_TXen_0_PORT GPIO_PRT10
  #define ULF_TXen_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_TXen_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define ULF_TXen_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define ULF_TXen_INBUF_ENABLED 0u
  #define ULF_TXen_INIT_DRIVESTATE 0u
  #define ULF_TXen_INIT_MUXSEL 0u
  #define ULF_TXen_INPUT_SYNC 2u
  #define ULF_TXen_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define ULF_TXen_NUM 5u
  #define ULF_TXen_PORT GPIO_PRT10
  #define ULF_TXen_SLEWRATE CY_GPIO_SLEW_FAST
  #define ULF_TXen_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* Orange_LED */
  #define Orange_LED_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define Orange_LED_0_INBUF_ENABLED 0u
  #define Orange_LED_0_INIT_DRIVESTATE 0u
  #define Orange_LED_0_INIT_MUXSEL 0u
  #define Orange_LED_0_INPUT_SYNC 2u
  #define Orange_LED_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define Orange_LED_0_NUM 5u
  #define Orange_LED_0_PORT GPIO_PRT1
  #define Orange_LED_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define Orange_LED_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define Orange_LED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define Orange_LED_INBUF_ENABLED 0u
  #define Orange_LED_INIT_DRIVESTATE 0u
  #define Orange_LED_INIT_MUXSEL 0u
  #define Orange_LED_INPUT_SYNC 2u
  #define Orange_LED_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define Orange_LED_NUM 5u
  #define Orange_LED_PORT GPIO_PRT1
  #define Orange_LED_SLEWRATE CY_GPIO_SLEW_FAST
  #define Orange_LED_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* UART_DEBUG_rx */
  #define UART_DEBUG_rx_0_DRIVEMODE CY_GPIO_DM_HIGHZ
  #define UART_DEBUG_rx_0_INBUF_ENABLED 1u
  #define UART_DEBUG_rx_0_INIT_DRIVESTATE 1u
  #define UART_DEBUG_rx_0_INIT_MUXSEL 18u
  #define UART_DEBUG_rx_0_INPUT_SYNC 2u
  #define UART_DEBUG_rx_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define UART_DEBUG_rx_0_NUM 0u
  #define UART_DEBUG_rx_0_PORT GPIO_PRT5
  #define UART_DEBUG_rx_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define UART_DEBUG_rx_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define UART_DEBUG_rx_DRIVEMODE CY_GPIO_DM_HIGHZ
  #define UART_DEBUG_rx_INBUF_ENABLED 1u
  #define UART_DEBUG_rx_INIT_DRIVESTATE 1u
  #define UART_DEBUG_rx_INIT_MUXSEL 18u
  #define UART_DEBUG_rx_INPUT_SYNC 2u
  #define UART_DEBUG_rx_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define UART_DEBUG_rx_NUM 0u
  #define UART_DEBUG_rx_PORT GPIO_PRT5
  #define UART_DEBUG_rx_SLEWRATE CY_GPIO_SLEW_FAST
  #define UART_DEBUG_rx_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  /* UART_DEBUG_tx */
  #define UART_DEBUG_tx_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define UART_DEBUG_tx_0_INBUF_ENABLED 0u
  #define UART_DEBUG_tx_0_INIT_DRIVESTATE 1u
  #define UART_DEBUG_tx_0_INIT_MUXSEL 18u
  #define UART_DEBUG_tx_0_INPUT_SYNC 2u
  #define UART_DEBUG_tx_0_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define UART_DEBUG_tx_0_NUM 1u
  #define UART_DEBUG_tx_0_PORT GPIO_PRT5
  #define UART_DEBUG_tx_0_SLEWRATE CY_GPIO_SLEW_FAST
  #define UART_DEBUG_tx_0_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  #define UART_DEBUG_tx_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
  #define UART_DEBUG_tx_INBUF_ENABLED 0u
  #define UART_DEBUG_tx_INIT_DRIVESTATE 1u
  #define UART_DEBUG_tx_INIT_MUXSEL 18u
  #define UART_DEBUG_tx_INPUT_SYNC 2u
  #define UART_DEBUG_tx_INTERRUPT_MODE CY_GPIO_INTR_DISABLE
  #define UART_DEBUG_tx_NUM 1u
  #define UART_DEBUG_tx_PORT GPIO_PRT5
  #define UART_DEBUG_tx_SLEWRATE CY_GPIO_SLEW_FAST
  #define UART_DEBUG_tx_THRESHOLD_LEVEL CY_GPIO_VTRIP_CMOS
  
  #endif /* INCLUDED_CYFITTER_GPIO_H */
  