text: /**************************************************************************//**
   * @file     core_cm3.h
   * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
   * @version  V1.30
   * @date     30. October 2009
   *
   * @note
   * Copyright (C) 2009 ARM Limited. All rights reserved.
   *
   * @par
   * ARM Limited (ARM) is supplying this software for use with Cortex-M 
   * processor based microcontrollers.  This file can be freely distributed 
   * within development tools that are supporting such ARM based processors. 
   *
   * @par
   * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
   * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
   * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
   * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
   * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
   *
   ******************************************************************************/
  
  #ifndef __CM3_CORE_H__
  #define __CM3_CORE_H__
  
  /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
   *
   * List of Lint messages which will be suppressed and not shown:
   *   - Error 10: \n
   *     register uint32_t __regBasePri         __asm("basepri"); \n
   *     Error 10: Expecting ';'
   * .
   *   - Error 530: \n
   *     return(__regBasePri); \n
   *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
   * . 
   *   - Error 550: \n
   *     __regBasePri = (basePri & 0x1ff); \n
   *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
   * .
   *   - Error 754: \n
   *     uint32_t RESERVED0[24]; \n
   *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
   * .
   *   - Error 750: \n
   *     #define __CM3_CORE_H__ \n
   *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
   * .
   *   - Error 528: \n
   *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
   *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
   * .
   *   - Error 751: \n
   *     } InterruptType_Type; \n
   *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
   * .
   * Note:  To re-enable a Message, insert a space before 'lint' *
   *
   */
  
  /*lint -save */
  /*lint -e10  */
  /*lint -e530 */
  /*lint -e550 */
  /*lint -e754 */
  /*lint -e750 */
  /*lint -e528 */
  /*lint -e751 */
  
  
  /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
    This file defines all structures and symbols for CMSIS core:
      - CMSIS version number
      - Cortex-M core registers and bitfields
      - Cortex-M core peripheral base address
    @{
   */
  
  #ifdef __cplusplus
   extern "C" {
  #endif 
  
  #define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
  #define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
  #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
  
  #define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
  
  #include <stdint.h>                           /* Include standard types */
  
  #if defined (__ICCARM__)
    #include <intrinsics.h>                     /* IAR Intrinsics   */
  #endif
  
  
  #ifndef __NVIC_PRIO_BITS
    #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
  #endif
  
  
  
  
  /**
   * IO definitions
   *
   * define access restrictions to peripheral registers
   */
  
  #ifdef __cplusplus
    #define     __I     volatile                /*!< defines 'read only' permissions      */
  #else
    #define     __I     volatile const          /*!< defines 'read only' permissions      */
  #endif
  #define     __O     volatile                  /*!< defines 'write only' permissions     */
  #define     __IO    volatile                  /*!< defines 'read / write' permissions   */
  
  
  
  /*******************************************************************************
   *                 Register Abstraction
   ******************************************************************************/
  /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
   @{
  */
  
  
  /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
    memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
    @{
   */
  typedef struct
  {
    __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
         uint32_t RESERVED0[24];                                   
    __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
         uint32_t RSERVED1[24];                                    
    __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
         uint32_t RESERVED2[24];                                   
    __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
         uint32_t RESERVED3[24];                                   
    __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
         uint32_t RESERVED4[56];                                   
    __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
         uint32_t RESERVED5[644];                                  
    __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
  }  NVIC_Type;                                               
  /*@}*/ /* end of group CMSIS_CM3_NVIC */
  
  
  /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
    memory mapped structure for System Control Block (SCB)
    @{
   */
  typedef struct
  {
    __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
    __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
    __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
    __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
    __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
    __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
    __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
    __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
    __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
    __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
    __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
    __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
    __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
    __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
    __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
    __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
    __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
    __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
    __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
  } SCB_Type;                                                
  
  /* SCB CPUID Register Definitions */
  #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
  #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
  
  #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
  #define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
  
  #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
  #define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
  
  #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
  #define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
  
  /* SCB Interrupt Control State Register Definitions */
  #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
  #define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
  
  #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
  #define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
  
  #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
  #define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
  
  #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
  #define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
  
  #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
  #define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
  
  #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
  #define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
  
  #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
  #define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
  
  #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
  #define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
  
  #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
  #define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
  
  #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
  #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
  
  /* SCB Interrupt Control State Register Definitions */
  #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
  #define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
  
  #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
  #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
  
  /* SCB Application Interrupt and Reset Control Register Definitions */
  #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
  #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
  
  #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
  #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
  
  #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
  #define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
  
  #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
  #define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
  
  #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
  #define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
  
  #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
  #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
  
  #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
  #define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
  
  /* SCB System Control Register Definitions */
  #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
  #define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
  
  #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
  #define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
  
  #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
  #define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
  
  /* SCB Configuration Control Register Definitions */
  #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
  #define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
  
  #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
  #define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
  
  #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
  #define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
  
  #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
  #define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
  
  #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
  #define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
  
  #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
  #define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
  
  /* SCB System Handler Control and State Register Definitions */
  #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
  #define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
  
  #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
  #define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
  
  #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
  #define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
  
  #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
  #define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
  
  #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
  #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
  
  #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
  #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
  
  #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
  #define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
  
  #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
  #define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
  
  #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
  #define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
  
  #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
  #define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
  
  #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
  #define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
                                       
  #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
  #define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
  
  #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
  #define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
  
  #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
  #define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
  
  /* SCB Configurable Fault Status Registers Definitions */
  #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
  #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
  
  #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
  #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
  
  #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
  #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
  
  /* SCB Hard Fault Status Registers Definitions */
  #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
  #define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
  
  #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
  #define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
  
  #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
  #define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
  
  /* SCB Debug Fault Status Register Definitions */
  #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
  #define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
  
  #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
  #define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
  
  #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
  #define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
  
  #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
  #define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
  
  #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
  #define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
  /*@}*/ /* end of group CMSIS_CM3_SCB */
  
  
  /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
    memory mapped structure for SysTick
    @{
   */
  typedef struct
  {
    __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
    __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
    __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
    __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
  } SysTick_Type;
  
  /* SysTick Control / Status Register Definitions */
  #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
  #define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
  
  #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
  #define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
  
  #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
  #define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
  
  #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
  #define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
  
  /* SysTick Reload Register Definitions */
  #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
  #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
  
  /* SysTick Current Register Definitions */
  #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
  #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
  
  /* SysTick Calibration Register Definitions */
  #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
  #define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
  
  #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
  #define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
  
  #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
  #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
  /*@}*/ /* end of group CMSIS_CM3_SysTick */
  
  
  /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
    memory mapped structure for Instrumentation Trace Macrocell (ITM)
    @{
   */
  typedef struct
  {
    __O  union  
    {
      __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */
      __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */
      __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */
    }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */
         uint32_t RESERVED0[864];                                 
    __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */
         uint32_t RESERVED1[15];                                  
    __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */
         uint32_t RESERVED2[15];                                  
    __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */
         uint32_t RESERVED3[29];                                  
    __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */
    __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */
    __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */
         uint32_t RESERVED4[43];                                  
    __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */
    __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */
         uint32_t RESERVED5[6];                                   
    __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */
    __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */
    __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */
    __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */
    __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */
    __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */
    __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */
    __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */
    __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */
    __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */
    __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */
    __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */
  } ITM_Type;                                                
  
  /* ITM Trace Privilege Register Definitions */
  #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
  #define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
  
  /* ITM Trace Control Register Definitions */
  #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
  #define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
  
  #define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
  #define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
  
  #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
  #define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
  
  #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
  #define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
  
  #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
  #define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
  
  #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
  #define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
  
  #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
  #define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
  
  #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
  #define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
  
  /* ITM Integration Write Register Definitions */
  #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
  #define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
  
  /* ITM Integration Read Register Definitions */
  #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
  #define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
  
  /* ITM Integration Mode Control Register Definitions */
  #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
  #define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
  
  /* ITM Lock Status Register Definitions */
  #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
  #define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
  
  #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
  #define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
  
  #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
  #define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
  /*@}*/ /* end of group CMSIS_CM3_ITM */
  
  
  /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
    memory mapped structure for Interrupt Type
    @{
   */
  typedef struct
  {
         uint32_t RESERVED0;
    __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */
  #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
    __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */
  #else
         uint32_t RESERVED1;
  #endif
  } InterruptType_Type;
  
  /* Interrupt Controller Type Register Definitions */
  #define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */
  #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
  
  /* Auxiliary Control Register Definitions */
  #define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */
  #define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */
  
  #define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */
  #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */
  
  #define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */
  #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */
  /*@}*/ /* end of group CMSIS_CM3_InterruptType */
  
  
  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
  /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
    memory mapped structure for Memory Protection Unit (MPU)
    @{
   */
  typedef struct
  {
    __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */
    __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */
    __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */
    __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */
    __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */
    __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */
    __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */
    __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */
    __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */
    __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */
    __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */
  } MPU_Type;                                                
  
  /* MPU Type Register */
  #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
  #define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
  
  #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
  #define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
  
  #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
  #define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
  
  /* MPU Control Register */
  #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
  #define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
  
  #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
  #define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
  
  #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
  #define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
  
  /* MPU Region Number Register */
  #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
  #define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
  
  /* MPU Region Base Address Register */
  #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
  #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
  
  #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
  #define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
  
  #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
  #define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
  
  /* MPU Region Attribute and Size Register */
  #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
  #define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
  
  #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
  #define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
  
  #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
  #define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
  
  #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
  #define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
  
  #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
  #define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
  
  #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
  #define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
  
  #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
  #define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
  
  #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
  #define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
  
  #define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
  #define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */
  
  /*@}*/ /* end of group CMSIS_CM3_MPU */
  #endif
  
  
  /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
    memory mapped structure for Core Debug Register
    @{
   */
  typedef struct
  {
    __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
    __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
    __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
    __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
  } CoreDebug_Type;
  
  /* Debug Halting Control and Status Register */
  #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
  #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
  
  #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
  #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
  
  #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
  #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
  
  #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
  #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
  
  #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
  #define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
  
  #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
  #define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
  
  #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
  #define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
  
  #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
  #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
  
  #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
  #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
  
  #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
  #define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
  
  #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
  #define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
  
  #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
  #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
  
  /* Debug Core Register Selector Register */
  #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
  #define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
  
  #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
  #define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
  
  /* Debug Exception and Monitor Control Register */
  #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
  #define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
  
  #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
  #define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
  
  #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
  #define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
  
  #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
  #define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
  
  #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
  #define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
  
  #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
  #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
  
  #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
  #define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
  
  #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
  #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
  
  #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
  #define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
  
  #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
  #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
  
  #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
  #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
  
  #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
  #define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
  
  #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
  #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
  /*@}*/ /* end of group CMSIS_CM3_CoreDebug */
  
  
  /* Memory mapping of Cortex-M3 Hardware */
  #define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
  #define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */
  #define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
  #define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
  #define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
  #define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
  
  #define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
  #define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
  #define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
  #define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
  #define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
  
  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
    #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */
    #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
  #endif
  
  /*@}*/ /* end of group CMSIS_CM3_core_register */
  
  
  /*******************************************************************************
   *                Hardware Abstraction Layer
   ******************************************************************************/
  
  #if defined ( __CC_ARM   )
    #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
    #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
  
  #elif defined ( __ICCARM__ )
    #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
    #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
  
  #elif defined   (  __GNUC__  )
    #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
    #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
  
  #elif defined   (  __TASKING__  )
    #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
    #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
  
  #endif
  
  
  /* ###################  Compiler specific Intrinsics  ########################### */
  
  #if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
  /* ARM armcc specific functions */
  
  #define __enable_fault_irq                __enable_fiq
  #define __disable_fault_irq               __disable_fiq
  
  #define __NOP                             __nop
  #define __WFI                             __wfi
  #define __WFE                             __wfe
  #define __SEV                             __sev
  #define __ISB()                           __isb(0)
  #define __DSB()                           __dsb(0)
  #define __DMB()                           __dmb(0)
  #define __REV                             __rev
  #define __RBIT                            __rbit
  #define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
  #define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
  #define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
  #define __STREXB(value, ptr)              __strex(value, ptr)
  #define __STREXH(value, ptr)              __strex(value, ptr)
  #define __STREXW(value, ptr)              __strex(value, ptr)
  
  
  /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
  /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
  /* intrinsic void __enable_irq();     */
  /* intrinsic void __disable_irq();    */
  
  
  /**
   * @brief  Return the Process Stack Pointer
   *
   * @return ProcessStackPointer
   *
   * Return the actual process stack pointer
   */
  extern uint32_t __get_PSP(void);
  
  /**
   * @brief  Set the Process Stack Pointer
   *
   * @param  topOfProcStack  Process Stack Pointer
   *
   * Assign the value ProcessStackPointer to the MSP 
   * (process stack pointer) Cortex processor register
   */
  extern void __set_PSP(uint32_t topOfProcStack);
  
  /**
   * @brief  Return the Main Stack Pointer
   *
   * @return Main Stack Pointer
   *
   * Return the current value of the MSP (main stack pointer)
   * Cortex processor register
   */
  extern uint32_t __get_MSP(void);
  
  /**
   * @brief  Set the Main Stack Pointer
   *
   * @param  topOfMainStack  Main Stack Pointer
   *
   * Assign the value mainStackPointer to the MSP 
   * (main stack pointer) Cortex processor register
   */
  extern void __set_MSP(uint32_t topOfMainStack);
  
  /**
   * @brief  Reverse byte order in unsigned short value
   *
   * @param   value  value to reverse
   * @return         reversed value
   *
   * Reverse byte order in unsigned short value
   */
  extern uint32_t __REV16(uint16_t value);
  
  /**
   * @brief  Reverse byte order in signed short value with sign extension to integer
   *
   * @param   value  value to reverse
   * @return         reversed value
   *
   * Reverse byte order in signed short value with sign extension to integer
   */
  extern int32_t __REVSH(int16_t value);
  
  
  #if (__ARMCC_VERSION < 400000)
  
  /**
   * @brief  Remove the exclusive lock created by ldrex
   *
   * Removes the exclusive lock which is created by ldrex.
   */
  extern void __CLREX(void);
  
  /**
   * @brief  Return the Base Priority value
   *
   * @return BasePriority
   *
   * Return the content of the base priority register
   */
  extern uint32_t __get_BASEPRI(void);
  
  /**
   * @brief  Set the Base Priority value
   *
   * @param  basePri  BasePriority
   *
   * Set the base priority register
   */
  extern void __set_BASEPRI(uint32_t basePri);
  
  /**
   * @brief  Return the Priority Mask value
   *
   * @return PriMask
   *
   * Return state of the priority mask bit from the priority mask register
   */
  extern uint32_t __get_PRIMASK(void);
  
  /**
   * @brief  Set the Priority Mask value
   *
   * @param   priMask  PriMask
   *
   * Set the priority mask bit in the priority mask register
   */
  extern void __set_PRIMASK(uint32_t priMask);
  
  /**
   * @brief  Return the Fault Mask value
   *
   * @return FaultMask
   *
   * Return the content of the fault mask register
   */
  extern uint32_t __get_FAULTMASK(void);
  
  /**
   * @brief  Set the Fault Mask value
   *
   * @param  faultMask faultMask value
   *
   * Set the fault mask register
   */
  extern void __set_FAULTMASK(uint32_t faultMask);
  
  /**
   * @brief  Return the Control Register value
   * 
   * @return Control value
   *
   * Return the content of the control register
   */
  extern uint32_t __get_CONTROL(void);
  
  /**
   * @brief  Set the Control Register value
   *
   * @param  control  Control value
   *
   * Set the control register
   */
  extern void __set_CONTROL(uint32_t control);
  
  #else  /* (__ARMCC_VERSION >= 400000)  */
  
  /**
   * @brief  Remove the exclusive lock created by ldrex
   *
   * Removes the exclusive lock which is created by ldrex.
   */
  #define __CLREX                           __clrex
  
  /**
   * @brief  Return the Base Priority value
   *
   * @return BasePriority
   *
   * Return the content of the base priority register
   */
  static __INLINE uint32_t  __get_BASEPRI(void)
  {
    register uint32_t __regBasePri         __ASM("basepri");
    return(__regBasePri);
  }
  
  /**
   * @brief  Set the Base Priority value
   *
   * @param  basePri  BasePriority
   *
   * Set the base priority register
   */
  static __INLINE void __set_BASEPRI(uint32_t basePri)
  {
    register uint32_t __regBasePri         __ASM("basepri");
    __regBasePri = (basePri & 0xff);
  }
  
  /**
   * @brief  Return the Priority Mask value
   *
   * @return PriMask
   *
   * Return state of the priority mask bit from the priority mask register
   */
  static __INLINE uint32_t __get_PRIMASK(void)
  {
    register uint32_t __regPriMask         __ASM("primask");
    return(__regPriMask);
  }
  
  /**
   * @brief  Set the Priority Mask value
   *
   * @param  priMask  PriMask
   *
   * Set the priority mask bit in the priority mask register
   */
  static __INLINE void __set_PRIMASK(uint32_t priMask)
  {
    register uint32_t __regPriMask         __ASM("primask");
    __regPriMask = (priMask);
  }
  
  /**
   * @brief  Return the Fault Mask value
   *
   * @return FaultMask
   *
   * Return the content of the fault mask register
   */
  static __INLINE uint32_t __get_FAULTMASK(void)
  {
    register uint32_t __regFaultMask       __ASM("faultmask");
    return(__regFaultMask);
  }
  
  /**
   * @brief  Set the Fault Mask value
   *
   * @param  faultMask  faultMask value
   *
   * Set the fault mask register
   */
  static __INLINE void __set_FAULTMASK(uint32_t faultMask)
  {
    register uint32_t __regFaultMask       __ASM("faultmask");
    __regFaultMask = (faultMask & 1);
  }
  
  /**
   * @brief  Return the Control Register value
   * 
   * @return Control value
   *
   * Return the content of the control register
   */
  static __INLINE uint32_t __get_CONTROL(void)
  {
    register uint32_t __regControl         __ASM("control");
    return(__regControl);
  }
  
  /**
   * @brief  Set the Control Register value
   *
   * @param  control  Control value
   *
   * Set the control register
   */
  static __INLINE void __set_CONTROL(uint32_t control)
  {
    register uint32_t __regControl         __ASM("control");
    __regControl = control;
  }
  
  #endif /* __ARMCC_VERSION  */ 
  
  
  
  #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
  /* IAR iccarm specific functions */
  
  #define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
  #define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
  
  static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
  static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
  
  #define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */ 
  static __INLINE  void __WFI()                     { __ASM ("wfi"); }
  static __INLINE  void __WFE()                     { __ASM ("wfe"); }
  static __INLINE  void __SEV()                     { __ASM ("sev"); }
  static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
  
  /* intrinsic void __ISB(void)                                     */
  /* intrinsic void __DSB(void)                                     */
  /* intrinsic void __DMB(void)                                     */
  /* intrinsic void __set_PRIMASK();                                */
  /* intrinsic void __get_PRIMASK();                                */
  /* intrinsic void __set_FAULTMASK();                              */
  /* intrinsic void __get_FAULTMASK();                              */
  /* intrinsic uint32_t __REV(uint32_t value);                      */
  /* intrinsic uint32_t __REVSH(uint32_t value);                    */
  /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
  /* intrinsic unsigned long __LDREX(unsigned long *);              */
  
  
  /**
   * @brief  Return the Process Stack Pointer
   *
   * @return ProcessStackPointer
   *
   * Return the actual process stack pointer
   */
  extern uint32_t __get_PSP(void);
  
  /**
   * @brief  Set the Process Stack Pointer
   *
   * @param  topOfProcStack  Process Stack Pointer
   *
   * Assign the value ProcessStackPointer to the MSP 
   * (process stack pointer) Cortex processor register
   */
  extern void __set_PSP(uint32_t topOfProcStack);
  
  /**
   * @brief  Return the Main Stack Pointer
   *
   * @return Main Stack Pointer
   *
   * Return the current value of the MSP (main stack pointer)
   * Cortex processor register
   */
  extern uint32_t __get_MSP(void);
  
  /**
   * @brief  Set the Main Stack Pointer
   *
   * @param  topOfMainStack  Main Stack Pointer
   *
   * Assign the value mainStackPointer to the MSP 
   * (main stack pointer) Cortex processor register
   */
  extern void __set_MSP(uint32_t topOfMainStack);
  
  /**
   * @brief  Reverse byte order in unsigned short value
   *
   * @param  value  value to reverse
   * @return        reversed value
   *
   * Reverse byte order in unsigned short value
   */
  extern uint32_t __REV16(uint16_t value);
  
  /**
   * @brief  Reverse bit order of value
   *
   * @param  value  value to reverse
   * @return        reversed value
   *
   * Reverse bit order of value
   */
  extern uint32_t __RBIT(uint32_t value);
  
  /**
   * @brief  LDR Exclusive (8 bit)
   *
   * @param  *addr  address pointer
   * @return        value of (*address)
   *
   * Exclusive LDR command for 8 bit values)
   */
  extern uint8_t __LDREXB(uint8_t *addr);
  
  /**
   * @brief  LDR Exclusive (16 bit)
   *
   * @param  *addr  address pointer
   * @return        value of (*address)
   *
   * Exclusive LDR command for 16 bit values
   */
  extern uint16_t __LDREXH(uint16_t *addr);
  
  /**
   * @brief  LDR Exclusive (32 bit)
   *
   * @param  *addr  address pointer
   * @return        value of (*address)
   *
   * Exclusive LDR command for 32 bit values
   */
  extern uint32_t __LDREXW(uint32_t *addr);
  
  /**
   * @brief  STR Exclusive (8 bit)
   *
   * @param  value  value to store
   * @param  *addr  address pointer
   * @return        successful / failed
   *
   * Exclusive STR command for 8 bit values
   */
  extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
  
  /**
   * @brief  STR Exclusive (16 bit)
   *
   * @param  value  value to store
   * @param  *addr  address pointer
   * @return        successful / failed
   *
   * Exclusive STR command for 16 bit values
   */
  extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
  
  /**
   * @brief  STR Exclusive (32 bit)
   *
   * @param  value  value to store
   * @param  *addr  address pointer
   * @return        successful / failed
   *
   * Exclusive STR command for 32 bit values
   */
  extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
  
  
  
  #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
  /* GNU gcc specific functions */
  
  static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
  static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
  
  static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
  static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
  
  static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
  static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
  static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
  static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
  static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
  static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
  static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
  static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
  
  
  /**
   * @brief  Return the Process Stack Pointer
   *
   * @return ProcessStackPointer
   *
   * Return the actual process stack pointer
   */
  extern uint32_t __get_PSP(void);
  
  /**
   * @brief  Set the Process Stack Pointer
   *
   * @param  topOfProcStack  Process Stack Pointer
   *
   * Assign the value ProcessStackPointer to the MSP 
   * (process stack pointer) Cortex processor register
   */
  extern void __set_PSP(uint32_t topOfProcStack);
  
  /**
   * @brief  Return the Main Stack Pointer
   *
   * @return Main Stack Pointer
   *
   * Return the current value of the MSP (main stack pointer)
   * Cortex processor register
   */
  extern uint32_t __get_MSP(void);
  
  /**
   * @brief  Set the Main Stack Pointer
   *
   * @param  topOfMainStack  Main Stack Pointer
   *
   * Assign the value mainStackPointer to the MSP 
   * (main stack pointer) Cortex processor register
   */
  extern void __set_MSP(uint32_t topOfMainStack);
  
  /**
   * @brief  Return the Base Priority value
   *
   * @return BasePriority
   *
   * Return the content of the base priority register
   */
  extern uint32_t __get_BASEPRI(void);
  
  /**
   * @brief  Set the Base Priority value
   *
   * @param  basePri  BasePriority
   *
   * Set the base priority register
   */
  extern void __set_BASEPRI(uint32_t basePri);
  
  /**
   * @brief  Return the Priority Mask value
   *
   * @return PriMask
   *
   * Return state of the priority mask bit from the priority mask register
   */
  extern uint32_t  __get_PRIMASK(void);
  
  /**
   * @brief  Set the Priority Mask value
   *
   * @param  priMask  PriMask
   *
   * Set the priority mask bit in the priority mask register
   */
  extern void __set_PRIMASK(uint32_t priMask);
  
  /**
   * @brief  Return the Fault Mask value
   *
   * @return FaultMask
   *
   * Return the content of the fault mask register
   */
  extern uint32_t __get_FAULTMASK(void);
  
  /**
   * @brief  Set the Fault Mask value
   *
   * @param  faultMask  faultMask value
   *
   * Set the fault mask register
   */
  extern void __set_FAULTMASK(uint32_t faultMask);
  
  /**
   * @brief  Return the Control Register value
  * 
  *  @return Control value
   *
   * Return the content of the control register
   */
  extern uint32_t __get_CONTROL(void);
  
  /**
   * @brief  Set the Control Register value
   *
   * @param  control  Control value
   *
   * Set the control register
   */
  extern void __set_CONTROL(uint32_t control);
  
  /**
   * @brief  Reverse byte order in integer value
   *
   * @param  value  value to reverse
   * @return        reversed value
   *
   * Reverse byte order in integer value
   */
  extern uint32_t __REV(uint32_t value);
  
  /**
   * @brief  Reverse byte order in unsigned short value
   *
   * @param  value  value to reverse
   * @return        reversed value
   *
   * Reverse byte order in unsigned short value
   */
  extern uint32_t __REV16(uint16_t value);
  
  /**
   * @brief  Reverse byte order in signed short value with sign extension to integer
   *
   * @param  value  value to reverse
   * @return        reversed value
   *
   * Reverse byte order in signed short value with sign extension to integer
   */
  extern int32_t __REVSH(int16_t value);
  
  /**
   * @brief  Reverse bit order of value
   *
   * @param  value  value to reverse
   * @return        reversed value
   *
   * Reverse bit order of value
   */
  extern uint32_t __RBIT(uint32_t value);
  
  /**
   * @brief  LDR Exclusive (8 bit)
   *
   * @param  *addr  address pointer
   * @return        value of (*address)
   *
   * Exclusive LDR command for 8 bit value
   */
  extern uint8_t __LDREXB(uint8_t *addr);
  
  /**
   * @brief  LDR Exclusive (16 bit)
   *
   * @param  *addr  address pointer
   * @return        value of (*address)
   *
   * Exclusive LDR command for 16 bit values
   */
  extern uint16_t __LDREXH(uint16_t *addr);
  
  /**
   * @brief  LDR Exclusive (32 bit)
   *
   * @param  *addr  address pointer
   * @return        value of (*address)
   *
   * Exclusive LDR command for 32 bit values
   */
  extern uint32_t __LDREXW(uint32_t *addr);
  
  /**
   * @brief  STR Exclusive (8 bit)
   *
   * @param  value  value to store
   * @param  *addr  address pointer
   * @return        successful / failed
   *
   * Exclusive STR command for 8 bit values
   */
  extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
  
  /**
   * @brief  STR Exclusive (16 bit)
   *
   * @param  value  value to store
   * @param  *addr  address pointer
   * @return        successful / failed
   *
   * Exclusive STR command for 16 bit values
   */
  extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
  
  /**
   * @brief  STR Exclusive (32 bit)
   *
   * @param  value  value to store
   * @param  *addr  address pointer
   * @return        successful / failed
   *
   * Exclusive STR command for 32 bit values
   */
  extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
  
  
  #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
  /* TASKING carm specific functions */
  
  /*
   * The CMSIS functions have been implemented as intrinsics in the compiler.
   * Please use "carm -?i" to get an up to date list of all instrinsics,
   * Including the CMSIS ones.
   */
  
  #endif
  
  
  /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
    Core  Function Interface containing:
    - Core NVIC Functions
    - Core SysTick Functions
    - Core Reset Functions
  */
  /*@{*/
  
  /* ##########################   NVIC functions  #################################### */
  
  /**
   * @brief  Set the Priority Grouping in NVIC Interrupt Controller
   *
   * @param  PriorityGroup is priority grouping field
   *
   * Set the priority grouping field using the required unlock sequence.
   * The parameter priority_grouping is assigned to the field 
   * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
   * In case of a conflict between priority grouping and available
   * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
   */
  static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  {
    uint32_t reg_value;
    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
    
    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
    reg_value  =  (reg_value                       |
                  (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
                  (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
    SCB->AIRCR =  reg_value;
  }
  
  /**
   * @brief  Get the Priority Grouping from NVIC Interrupt Controller
   *
   * @return priority grouping field 
   *
   * Get the priority grouping from NVIC Interrupt Controller.
   * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
   */
  static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
  {
    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
  }
  
  /**
   * @brief  Enable Interrupt in NVIC Interrupt Controller
   *
   * @param  IRQn   The positive number of the external interrupt to enable
   *
   * Enable a device specific interupt in the NVIC interrupt controller.
   * The interrupt number cannot be a negative value.
   */
  static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  {
    NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
  }
  
  /**
   * @brief  Disable the interrupt line for external interrupt specified
   * 
   * @param  IRQn   The positive number of the external interrupt to disable
   * 
   * Disable a device specific interupt in the NVIC interrupt controller.
   * The interrupt number cannot be a negative value.
   */
  static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  {
    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
  }
  
  /**
   * @brief  Read the interrupt pending bit for a device specific interrupt source
   * 
   * @param  IRQn    The number of the device specifc interrupt
   * @return         1 = interrupt pending, 0 = interrupt not pending
   *
   * Read the pending register in NVIC and return 1 if its status is pending, 
   * otherwise it returns 0
   */
  static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  {
    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
  }
  
  /**
   * @brief  Set the pending bit for an external interrupt
   * 
   * @param  IRQn    The number of the interrupt for set pending
   *
   * Set the pending bit for the specified interrupt.
   * The interrupt number cannot be a negative value.
   */
  static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  {
    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
  }
  
  /**
   * @brief  Clear the pending bit for an external interrupt
   *
   * @param  IRQn    The number of the interrupt for clear pending
   *
   * Clear the pending bit for the specified interrupt. 
   * The interrupt number cannot be a negative value.
   */
  static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  {
    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
  }
  
  /**
   * @brief  Read the active bit for an external interrupt
   *
   * @param  IRQn    The number of the interrupt for read active bit
   * @return         1 = interrupt active, 0 = interrupt not active
   *
   * Read the active register in NVIC and returns 1 if its status is active, 
   * otherwise it returns 0.
   */
  static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  {
    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
  }
  
  /**
   * @brief  Set the priority for an interrupt
   *
   * @param  IRQn      The number of the interrupt for set priority
   * @param  priority  The priority to set
   *
   * Set the priority for the specified interrupt. The interrupt 
   * number can be positive to specify an external (device specific) 
   * interrupt, or negative to specify an internal (core) interrupt.
   *
   * Note: The priority cannot be set for every core interrupt.
   */
  static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  {
    if(IRQn < 0) {
      SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
    else {
      NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
  }
  
  /**
   * @brief  Read the priority for an interrupt
   *
   * @param  IRQn      The number of the interrupt for get priority
   * @return           The priority for the interrupt
   *
   * Read the priority for the specified interrupt. The interrupt 
   * number can be positive to specify an external (device specific) 
   * interrupt, or negative to specify an internal (core) interrupt.
   *
   * The returned priority value is automatically aligned to the implemented
   * priority bits of the microcontroller.
   *
   * Note: The priority cannot be set for every core interrupt.
   */
  static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  {
  
    if(IRQn < 0) {
      return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
    else {
      return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
  }
  
  
  /**
   * @brief  Encode the priority for an interrupt
   *
   * @param  PriorityGroup    The used priority group
   * @param  PreemptPriority  The preemptive priority value (starting from 0)
   * @param  SubPriority      The sub priority value (starting from 0)
   * @return                  The encoded priority for the interrupt
   *
   * Encode the priority for an interrupt with the given priority group,
   * preemptive priority value and sub priority value.
   * In case of a conflict between priority grouping and available
   * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
   *
   * The returned priority value can be used for NVIC_SetPriority(...) function
   */
  static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
  {
    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
    uint32_t PreemptPriorityBits;
    uint32_t SubPriorityBits;
  
    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
   
    return (
             ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
             ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
           );
  }
  
  
  /**
   * @brief  Decode the priority of an interrupt
   *
   * @param  Priority           The priority for the interrupt
   * @param  PriorityGroup      The used priority group
   * @param  pPreemptPriority   The preemptive priority value (starting from 0)
   * @param  pSubPriority       The sub priority value (starting from 0)
   *
   * Decode an interrupt priority value with the given priority group to 
   * preemptive priority value and sub priority value.
   * In case of a conflict between priority grouping and available
   * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
   *
   * The priority value can be retrieved with NVIC_GetPriority(...) function
   */
  static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
  {
    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
    uint32_t PreemptPriorityBits;
    uint32_t SubPriorityBits;
  
    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
    
    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
  }
  
  
  
  /* ##################################    SysTick function  ############################################ */
  
  #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
  
  /**
   * @brief  Initialize and start the SysTick counter and its interrupt.
   *
   * @param   ticks   number of ticks between two interrupts
   * @return  1 = failed, 0 = successful
   *
   * Initialise the system tick timer and its interrupt and start the
   * system tick timer / counter in free running mode to generate 
   * periodical interrupts.
   */
  static __INLINE uint32_t SysTick_Config(uint32_t ticks)
  { 
    if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
                                                                 
    SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
    NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
  //	NVIC_SetPriority (SysTick_IRQn, 2);
    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
                     SysTick_CTRL_TICKINT_Msk   | 
                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
    return (0);                                                  /* Function successful */
  }
  
  #endif
  
  
  
  
  /* ##################################    Reset function  ############################################ */
  
  /**
   * @brief  Initiate a system reset request.
   *
   * Initiate a system reset request to reset the MCU
   */
  static __INLINE void NVIC_SystemReset(void)
  {
    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
    __DSB();                                                     /* Ensure completion of memory access */              
    while(1);                                                    /* wait until reset */
  }
  
  /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
  
  
  
  /* ##################################### Debug In/Output function ########################################### */
  
  /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
    Core Debug Interface containing:
    - Core Debug Receive / Transmit Functions
    - Core Debug Defines
    - Core Debug Variables
  */
  /*@{*/
  
  extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */
  #define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
  
  
  /**
   * @brief  Outputs a character via the ITM channel 0
   *
   * @param  ch   character to output
   * @return      character to output
   *
   * The function outputs a character via the ITM channel 0. 
   * The function returns when no debugger is connected that has booked the output.  
   * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
   */
  static __INLINE uint32_t ITM_SendChar (uint32_t ch)
  {
    if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
        (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
        (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */
    {
      while (ITM->PORT[0].u32 == 0);
      ITM->PORT[0].u8 = (uint8_t) ch;
    }  
    return (ch);
  }
  
  
  /**
   * @brief  Inputs a character via variable ITM_RxBuffer
   *
   * @return      received character, -1 = no character received
   *
   * The function inputs a character via variable ITM_RxBuffer. 
   * The function returns when no debugger is connected that has booked the output.  
   * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
   */
  static __INLINE int ITM_ReceiveChar (void) {
    int ch = -1;                               /* no character available */
  
    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
      ch = ITM_RxBuffer;
      ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
    }
    
    return (ch); 
  }
  
  
  /**
   * @brief  Check if a character via variable ITM_RxBuffer is available
   *
   * @return      1 = character available, 0 = no character available
   *
   * The function checks  variable ITM_RxBuffer whether a character is available or not. 
   * The function returns '1' if a character is available and '0' if no character is available. 
   */
  static __INLINE int ITM_CheckChar (void) {
  
    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
      return (0);                                 /* no character available */
    } else {
      return (1);                                 /*    character available */
    }
  }
  
  /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
  
  
  #ifdef __cplusplus
  }
  #endif
  
  /*@}*/ /* end of group CMSIS_CM3_core_definitions */
  
  #endif /* __CM3_CORE_H__ */
  
  /*lint -restore */
  