text: /* SPDX-License-Identifier: BSD-2-Clause */
  /*
   * Copyright 2017 NXP
   * All rights reserved.
   *
   * Peng Fan <peng.fan@nxp.com>
   *
   * Redistribution and use in source and binary forms, with or without
   * modification, are permitted provided that the following conditions are met:
   *
   * 1. Redistributions of source code must retain the above copyright notice,
   * this list of conditions and the following disclaimer.
   *
   * 2. Redistributions in binary form must reproduce the above copyright notice,
   * this list of conditions and the following disclaimer in the documentation
   * and/or other materials provided with the distribution.
   *
   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   * POSSIBILITY OF SUCH DAMAGE.
   */
  
  #ifndef __CONFIG_IMX6SX_H
  #define __CONFIG_IMX6SX_H
  
  #ifndef CFG_UART_BASE
  #define CFG_UART_BASE	(UART1_BASE)
  #endif
  
  #ifndef CFG_DDR_SIZE
  #error "CFG_DDR_SIZE not defined"
  #endif
  
  #define DRAM0_SIZE		CFG_DDR_SIZE
  
  /* Location of trusted dram */
  #define TZDRAM_BASE		(DRAM0_BASE - 32 * 1024 * 1024 + CFG_DDR_SIZE)
  #define TZDRAM_SIZE		(30 * 1024 * 1024)
  
  /* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */
  #define CFG_SHMEM_START		(TZDRAM_BASE + TZDRAM_SIZE)
  #define CFG_SHMEM_SIZE		0x200000
  
  #define CFG_TEE_RAM_VA_SIZE	(1024 * 1024)
  
  /*
   * Everything is in TZDRAM.
   * +------------------+
   * |        | TEE_RAM |
   * + TZDRAM +---------+
   * |        | TA_RAM  |
   * +--------+---------+
   */
  #define CFG_TEE_RAM_PH_SIZE     CFG_TEE_RAM_VA_SIZE
  #define CFG_TEE_RAM_START	TZDRAM_BASE
  #define CFG_TA_RAM_START	ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \
  					CORE_MMU_DEVICE_SIZE)
  #define CFG_TA_RAM_SIZE		ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \
  					  CORE_MMU_DEVICE_SIZE)
  
  #ifndef CFG_TEE_LOAD_ADDR
  #define CFG_TEE_LOAD_ADDR	CFG_TEE_RAM_START
  #endif
  
  #define CONSOLE_UART_BASE	(CFG_UART_BASE)
  
  /*
   * PL310 TAG RAM Control Register
   *
   * bit[10:8]:1 - 2 cycle of write accesses latency
   * bit[6:4]:3 - 4 cycle of read accesses latency
   * bit[2:0]:2 - 3 cycle of setup latency
   */
  #ifndef PL310_TAG_RAM_CTRL_INIT
  #define PL310_TAG_RAM_CTRL_INIT		0x00000132
  #endif
  
  /*
   * PL310 DATA RAM Control Register
   *
   * bit[10:8]:1 - 2 cycle of write accesses latency
   * bit[6:4]:3 - 4 cycle of read accesses latency
   * bit[2:0]:2 - 3 cycle of setup latency
   */
  #ifndef PL310_DATA_RAM_CTRL_INIT
  #define PL310_DATA_RAM_CTRL_INIT	0x00000232
  #endif
  
  /*
   * PL310 Auxiliary Control Register
   *
   * I/Dcache prefetch enabled (bit29:28=2b11)
   * NS can access interrupts (bit27=1)
   * NS can lockown cache lines (bit26=1)
   * Pseudo-random replacement policy (bit25=0)
   * Force write allocated (default)
   * Shared attribute internally ignored (bit22=1, bit13=0)
   * Parity disabled (bit21=0)
   * Event monitor disabled (bit20=0)
   * Platform fmavor specific way config (dual / quad):
   * - 16kb way size (bit19:17=3b001)
   * - 16-way associciativity (bit16=1)
   * Store buffer device limitation enabled (bit11=1)
   * Cacheable accesses have high prio (bit10=0)
   * Full Line Zero (FLZ) disabled (bit0=0)
   */
  #define PL310_AUX_CTRL_INIT		0x3C430800
  
  /*
   * PL310 Prefetch Control Register
   *
   * Double linefill disabled (bit30=0)
   * I/D prefetch enabled (bit29:28=2b11)
   * Prefetch drop enabled (bit24=1)
   * Incr double linefill disable (bit23=0)
   * Prefetch offset = 7 (bit4:0)
   */
  #define PL310_PREFETCH_CTRL_INIT	0x31000007
  
  /*
   * PL310 Power Register
   *
   * Dynamic clock gating enabled
   * Standby mode enabled
   */
  #define PL310_POWER_CTRL_INIT		0x00000003
  
  /*
   * SCU Invalidate Register
   *
   * Invalidate all registers
   */
  #define	SCU_INV_CTRL_INIT		0xFFFFFFFF
  
  /*
   * SCU Access Register
   * - both secure CPU access SCU
   */
  #define SCU_SAC_CTRL_INIT		0x0000000F
  
  /*
   * SCU NonSecure Access Register
   * - both nonsec cpu access SCU, private and global timer
   */
  #define SCU_NSAC_CTRL_INIT		0x00000FFF
  
  #endif
  