text: // SPDX-License-Identifier: GPL-2.0-only
  /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   */
  
  #include "dpu_hwio.h"
  #include "dpu_hw_catalog.h"
  #include "dpu_hw_lm.h"
  #include "dpu_hw_dspp.h"
  #include "dpu_kms.h"
  
  
  /* DSPP_PCC */
  #define PCC_EN BIT(0)
  #define PCC_DIS 0
  #define PCC_RED_R_OFF 0x10
  #define PCC_RED_G_OFF 0x1C
  #define PCC_RED_B_OFF 0x28
  #define PCC_GREEN_R_OFF 0x14
  #define PCC_GREEN_G_OFF 0x20
  #define PCC_GREEN_B_OFF 0x2C
  #define PCC_BLUE_R_OFF 0x18
  #define PCC_BLUE_G_OFF 0x24
  #define PCC_BLUE_B_OFF 0x30
  
  static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx,
  		struct dpu_hw_pcc_cfg *cfg)
  {
  
  	u32 base;
  
  	if (!ctx) {
  		DRM_ERROR("invalid ctx %pK\n", ctx);
  		return;
  	}
  
  	base = ctx->cap->sblk->pcc.base;
  
  	if (!base) {
  		DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base);
  		return;
  	}
  
  	if (!cfg) {
  		DRM_DEBUG_DRIVER("disable pcc feature\n");
  		DPU_REG_WRITE(&ctx->hw, base, PCC_DIS);
  		return;
  	}
  
  	DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r);
  	DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g);
  	DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b);
  
  	DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r);
  	DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g);
  	DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b);
  
  	DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r);
  	DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g);
  	DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b);
  
  	DPU_REG_WRITE(&ctx->hw, base, PCC_EN);
  }
  
  static void _setup_dspp_ops(struct dpu_hw_dspp *c,
  		unsigned long features)
  {
  	if (test_bit(DPU_DSPP_PCC, &features))
  		c->ops.setup_pcc = dpu_setup_dspp_pcc;
  }
  
  static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp,
  		const struct dpu_mdss_cfg *m,
  		void __iomem *addr,
  		struct dpu_hw_blk_reg_map *b)
  {
  	int i;
  
  	if (!m || !addr || !b)
  		return ERR_PTR(-EINVAL);
  
  	for (i = 0; i < m->dspp_count; i++) {
  		if (dspp == m->dspp[i].id) {
  			b->base_off = addr;
  			b->blk_off = m->dspp[i].base;
  			b->length = m->dspp[i].len;
  			b->hwversion = m->hwversion;
  			b->log_mask = DPU_DBG_MASK_DSPP;
  			return &m->dspp[i];
  		}
  	}
  
  	return ERR_PTR(-EINVAL);
  }
  
  struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
  			void __iomem *addr,
  			const struct dpu_mdss_cfg *m)
  {
  	struct dpu_hw_dspp *c;
  	const struct dpu_dspp_cfg *cfg;
  
  	if (!addr || !m)
  		return ERR_PTR(-EINVAL);
  
  	c = kzalloc(sizeof(*c), GFP_KERNEL);
  	if (!c)
  		return ERR_PTR(-ENOMEM);
  
  	cfg = _dspp_offset(idx, m, addr, &c->hw);
  	if (IS_ERR_OR_NULL(cfg)) {
  		kfree(c);
  		return ERR_PTR(-EINVAL);
  	}
  
  	/* Assign ops */
  	c->idx = idx;
  	c->cap = cfg;
  	_setup_dspp_ops(c, c->cap->features);
  
  	return c;
  }
  
  void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
  {
  	kfree(dspp);
  }
  
  
  