text: /******************************************************************************
  *
  * Copyright (C) 2018-2019 Xilinx, Inc.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  *
  *
  *
  ******************************************************************************/
  /*****************************************************************************/
  /**
  *
  * @file xospipsv_hw.h
  * @addtogroup ospipsv_v1_1
  * @{
  *
  * This file contains low level access functions using the base address
  * directly without an instance.
  *
  * <pre>
  * MODIFICATION HISTORY:
  *
  * Ver   Who Date     Changes
  * ----- --- -------- -----------------------------------------------.
  * 1.0   nsk  02/19/18 First release
  *       sk   02/04/19 Added support for SDR+PHY and DDR+PHY modes.
  *
  * </pre>
  *
  ******************************************************************************/
  #ifndef _XOSPIPSV_HW_H_		/* prevent circular inclusions */
  #define _XOSPIPSV_HW_H_		/* by using protection macros */
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /***************************** Include Files *********************************/
  
  #include "xil_types.h"
  #include "xil_assert.h"
  #include "xil_io.h"
  #include "xparameters.h"
  
  /************************** Constant Definitions *****************************/
  
  #define DQ0	0U
  #define DQ0_1	1U
  #define DQ0_3	2U
  #define DQ0_7	3U
  #define XOSPIPSV_MAX_DUMMY 31
  
  #define IOU_MUX_SEL	0xF0780508
  
  /**
   * OSPI Base Address
   */
  #define XOSPIPSV_BASEADDR      0XF1010000
  
  /**
   * Register: OSPI_CONFIG_REG
   */
  #define XOSPIPSV_CONFIG_REG   0X00000000U
  
  #define XOSPIPSV_CONFIG_REG_IDLE_FLD_SHIFT   31
  #define XOSPIPSV_CONFIG_REG_IDLE_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_IDLE_FLD_MASK    0X80000000U
  
  #define XOSPIPSV_CONFIG_REG_DUAL_BYTE_OPCODE_EN_FLD_SHIFT   30
  #define XOSPIPSV_CONFIG_REG_DUAL_BYTE_OPCODE_EN_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_DUAL_BYTE_OPCODE_EN_FLD_MASK    0X40000000U
  
  #define XOSPIPSV_CONFIG_REG_CRC_ENABLE_FLD_SHIFT   29
  #define XOSPIPSV_CONFIG_REG_CRC_ENABLE_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_CRC_ENABLE_FLD_MASK    0X20000000U
  
  #define XOSPIPSV_CONFIG_REG_CONFIG_RESV2_FLD_SHIFT   26
  #define XOSPIPSV_CONFIG_REG_CONFIG_RESV2_FLD_WIDTH   3
  #define XOSPIPSV_CONFIG_REG_CONFIG_RESV2_FLD_MASK    0X1C000000U
  
  #define XOSPIPSV_CONFIG_REG_PIPELINE_PHY_FLD_SHIFT   25
  #define XOSPIPSV_CONFIG_REG_PIPELINE_PHY_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_PIPELINE_PHY_FLD_MASK    0X02000000U
  
  #define XOSPIPSV_CONFIG_REG_ENABLE_DTR_PROTOCOL_FLD_SHIFT   24
  #define XOSPIPSV_CONFIG_REG_ENABLE_DTR_PROTOCOL_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENABLE_DTR_PROTOCOL_FLD_MASK    0X01000000U
  
  #define XOSPIPSV_CONFIG_REG_ENABLE_AHB_DECODER_FLD_SHIFT   23
  #define XOSPIPSV_CONFIG_REG_ENABLE_AHB_DECODER_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENABLE_AHB_DECODER_FLD_MASK    0X00800000U
  
  #define XOSPIPSV_CONFIG_REG_MSTR_BAUD_DIV_FLD_SHIFT   19
  #define XOSPIPSV_CONFIG_REG_MSTR_BAUD_DIV_FLD_WIDTH   4
  #define XOSPIPSV_CONFIG_REG_MSTR_BAUD_DIV_FLD_MASK    0X00780000U
  
  #define XOSPIPSV_CONFIG_REG_ENTER_XIP_MODE_IMM_FLD_SHIFT   18
  #define XOSPIPSV_CONFIG_REG_ENTER_XIP_MODE_IMM_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENTER_XIP_MODE_IMM_FLD_MASK    0X00040000U
  
  #define XOSPIPSV_CONFIG_REG_ENTER_XIP_MODE_FLD_SHIFT   17
  #define XOSPIPSV_CONFIG_REG_ENTER_XIP_MODE_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENTER_XIP_MODE_FLD_MASK    0X00020000U
  
  #define XOSPIPSV_CONFIG_REG_ENB_AHB_ADDR_REMAP_FLD_SHIFT   16
  #define XOSPIPSV_CONFIG_REG_ENB_AHB_ADDR_REMAP_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENB_AHB_ADDR_REMAP_FLD_MASK    0X00010000U
  
  #define XOSPIPSV_CONFIG_REG_ENB_DMA_IF_FLD_SHIFT   15
  #define XOSPIPSV_CONFIG_REG_ENB_DMA_IF_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENB_DMA_IF_FLD_MASK    0X00008000U
  
  #define XOSPIPSV_CONFIG_REG_WR_PROT_FLASH_FLD_SHIFT   14
  #define XOSPIPSV_CONFIG_REG_WR_PROT_FLASH_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_WR_PROT_FLASH_FLD_MASK    0X00004000U
  
  #define XOSPIPSV_CONFIG_REG_PERIPH_CS_LINES_FLD_SHIFT   10
  #define XOSPIPSV_CONFIG_REG_PERIPH_CS_LINES_FLD_WIDTH   4
  #define XOSPIPSV_CONFIG_REG_PERIPH_CS_LINES_FLD_MASK    0X00003C00U
  
  #define XOSPIPSV_CONFIG_REG_PERIPH_SEL_DEC_FLD_SHIFT   9
  #define XOSPIPSV_CONFIG_REG_PERIPH_SEL_DEC_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_PERIPH_SEL_DEC_FLD_MASK    0X00000200U
  
  #define XOSPIPSV_CONFIG_REG_ENB_DIR_ACC_CTLR_FLD_SHIFT   7
  #define XOSPIPSV_CONFIG_REG_ENB_DIR_ACC_CTLR_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENB_DIR_ACC_CTLR_FLD_MASK    0X00000080U
  
  #define XOSPIPSV_CONFIG_REG_RESET_CFG_FLD_SHIFT   6
  #define XOSPIPSV_CONFIG_REG_RESET_CFG_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_RESET_CFG_FLD_MASK    0X00000040U
  
  #define XOSPIPSV_CONFIG_REG_RESET_PIN_FLD_SHIFT   5
  #define XOSPIPSV_CONFIG_REG_RESET_PIN_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_RESET_PIN_FLD_MASK    0X00000020U
  
  #define XOSPIPSV_CONFIG_REG_HOLD_PIN_FLD_SHIFT   4
  #define XOSPIPSV_CONFIG_REG_HOLD_PIN_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_HOLD_PIN_FLD_MASK    0X00000010U
  
  #define XOSPIPSV_CONFIG_REG_PHY_MODE_ENABLE_FLD_SHIFT   3
  #define XOSPIPSV_CONFIG_REG_PHY_MODE_ENABLE_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_PHY_MODE_ENABLE_FLD_MASK    0X00000008U
  
  #define XOSPIPSV_CONFIG_REG_SEL_CLK_PHASE_FLD_SHIFT   2
  #define XOSPIPSV_CONFIG_REG_SEL_CLK_PHASE_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_SEL_CLK_PHASE_FLD_MASK    0X00000004U
  
  #define XOSPIPSV_CONFIG_REG_SEL_CLK_POL_FLD_SHIFT   1
  #define XOSPIPSV_CONFIG_REG_SEL_CLK_POL_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_SEL_CLK_POL_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_CONFIG_REG_ENB_SPI_FLD_SHIFT   0
  #define XOSPIPSV_CONFIG_REG_ENB_SPI_FLD_WIDTH   1
  #define XOSPIPSV_CONFIG_REG_ENB_SPI_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_DEV_INSTR_RD_CONFIG_REG
   */
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG    0X00000004U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV5_FLD_SHIFT   29
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV5_FLD_WIDTH   3
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV5_FLD_MASK    0XE0000000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DUMMY_RD_CLK_CYCLES_FLD_SHIFT   24
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DUMMY_RD_CLK_CYCLES_FLD_WIDTH   5
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DUMMY_RD_CLK_CYCLES_FLD_MASK    0X1F000000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV4_FLD_SHIFT   21
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV4_FLD_WIDTH   3
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV4_FLD_MASK    0X00E00000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_MODE_BIT_ENABLE_FLD_SHIFT   20
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_MODE_BIT_ENABLE_FLD_WIDTH   1
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_MODE_BIT_ENABLE_FLD_MASK    0X00100000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV3_FLD_SHIFT   18
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV3_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV3_FLD_MASK    0X000C0000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_SHIFT   16
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_MASK    0X00030000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV2_FLD_SHIFT   14
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV2_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_INSTR_RESV2_FLD_MASK    0X0000C000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_SHIFT   12
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_MASK    0X00003000U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_PRED_DIS_FLD_SHIFT   11
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_PRED_DIS_FLD_WIDTH   1
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_PRED_DIS_FLD_MASK    0X00000800U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DDR_EN_FLD_SHIFT   10
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DDR_EN_FLD_WIDTH   1
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_DDR_EN_FLD_MASK    0X00000400U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_INSTR_TYPE_FLD_SHIFT   8
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_INSTR_TYPE_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_INSTR_TYPE_FLD_MASK    0X00000300U
  
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_OPCODE_NON_XIP_FLD_SHIFT   0
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_OPCODE_NON_XIP_FLD_WIDTH   8
  #define XOSPIPSV_DEV_INSTR_RD_CONFIG_REG_RD_OPCODE_NON_XIP_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_DEV_INSTR_WR_CONFIG_REG
   */
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG   0X00000008U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV4_FLD_SHIFT   29
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV4_FLD_WIDTH   3
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV4_FLD_MASK    0XE0000000U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_DUMMY_WR_CLK_CYCLES_FLD_SHIFT   24
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_DUMMY_WR_CLK_CYCLES_FLD_WIDTH   5
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_DUMMY_WR_CLK_CYCLES_FLD_MASK    0X1F000000U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV3_FLD_SHIFT   18
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV3_FLD_WIDTH   6
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV3_FLD_MASK    0X00FC0000U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_SHIFT   16
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_MASK    0X00030000U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV2_FLD_SHIFT   14
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV2_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV2_FLD_MASK    0X0000C000U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_SHIFT   12
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_WIDTH   2
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_MASK    0X00003000U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV1_FLD_SHIFT   9
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV1_FLD_WIDTH   3
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV1_FLD_MASK    0X00000E00U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WEL_DIS_FLD_SHIFT   8
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WEL_DIS_FLD_WIDTH   1
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WEL_DIS_FLD_MASK    0X00000100U
  
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_OPCODE_FLD_SHIFT   0
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_DEV_INSTR_WR_CONFIG_REG_WR_OPCODE_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_DEV_DELAY_REG
   */
  #define XOSPIPSV_DEV_DELAY_REG    0X0000000CU
  
  #define XOSPIPSV_DEV_DELAY_REG_D_NSS_FLD_SHIFT   24
  #define XOSPIPSV_DEV_DELAY_REG_D_NSS_FLD_WIDTH   8
  #define XOSPIPSV_DEV_DELAY_REG_D_NSS_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_DEV_DELAY_REG_D_BTWN_FLD_SHIFT   16
  #define XOSPIPSV_DEV_DELAY_REG_D_BTWN_FLD_WIDTH   8
  #define XOSPIPSV_DEV_DELAY_REG_D_BTWN_FLD_MASK    0X00FF0000U
  
  #define XOSPIPSV_DEV_DELAY_REG_D_AFTER_FLD_SHIFT   8
  #define XOSPIPSV_DEV_DELAY_REG_D_AFTER_FLD_WIDTH   8
  #define XOSPIPSV_DEV_DELAY_REG_D_AFTER_FLD_MASK    0X0000FF00U
  
  #define XOSPIPSV_DEV_DELAY_REG_D_INIT_FLD_SHIFT   0
  #define XOSPIPSV_DEV_DELAY_REG_D_INIT_FLD_WIDTH   8
  #define XOSPIPSV_DEV_DELAY_REG_D_INIT_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_RD_DATA_CAPTURE_REG
   */
  #define XOSPIPSV_RD_DATA_CAPTURE_REG    0X00000010U
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV3_FLD_SHIFT   20
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV3_FLD_WIDTH   12
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV3_FLD_MASK    0XFFF00000U
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DDR_READ_DELAY_FLD_SHIFT   16
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DDR_READ_DELAY_FLD_WIDTH   4
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DDR_READ_DELAY_FLD_MASK    0X000F0000U
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV2_FLD_SHIFT   9
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV2_FLD_WIDTH   7
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV2_FLD_MASK    0X0000FE00U
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DQS_ENABLE_FLD_SHIFT   8
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DQS_ENABLE_FLD_WIDTH   1
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DQS_ENABLE_FLD_MASK    0X00000100U
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV1_FLD_SHIFT   6
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV1_FLD_WIDTH   2
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_RD_DATA_RESV1_FLD_MASK    0X000000C0U
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD_SHIFT   5
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD_WIDTH   1
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD_MASK    0X00000020U
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DELAY_FLD_SHIFT   1
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DELAY_FLD_WIDTH   4
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_DELAY_FLD_MASK    0X0000001EU
  
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_BYPASS_FLD_SHIFT   0
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_BYPASS_FLD_WIDTH   1
  #define XOSPIPSV_RD_DATA_CAPTURE_REG_BYPASS_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_DEV_SIZE_CONFIG_REG
   */
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG    0X00000014U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_DEV_SIZE_RESV_FLD_SHIFT   29
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_DEV_SIZE_RESV_FLD_WIDTH   3
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_DEV_SIZE_RESV_FLD_MASK    0XE0000000U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS3_FLD_SHIFT   27
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS3_FLD_WIDTH   2
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS3_FLD_MASK    0X18000000U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS2_FLD_SHIFT   25
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS2_FLD_WIDTH   2
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS2_FLD_MASK    0X06000000U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS1_FLD_SHIFT   23
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS1_FLD_WIDTH   2
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS1_FLD_MASK    0X01800000U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS0_FLD_SHIFT   21
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS0_FLD_WIDTH   2
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS0_FLD_MASK    0X00600000U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_BYTES_PER_SUBSECTOR_FLD_SHIFT   16
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_BYTES_PER_SUBSECTOR_FLD_WIDTH   5
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_BYTES_PER_SUBSECTOR_FLD_MASK    0X001F0000U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_BYTES_PER_DEVICE_PAGE_FLD_SHIFT   4
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_BYTES_PER_DEVICE_PAGE_FLD_WIDTH   12
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_BYTES_PER_DEVICE_PAGE_FLD_MASK    0X0000FFF0U
  
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_NUM_ADDR_BYTES_FLD_SHIFT   0
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_NUM_ADDR_BYTES_FLD_WIDTH   4
  #define XOSPIPSV_DEV_SIZE_CONFIG_REG_NUM_ADDR_BYTES_FLD_MASK    0X0000000FU
  
  /**
   * Register: OSPI_SRAM_PARTITION_CFG_REG
   */
  #define XOSPIPSV_SRAM_PARTITION_CFG_REG    0X00000018U
  
  #define XOSPIPSV_SRAM_PARTITION_CFG_REG_SRAM_PARTITION_RESV_FLD_SHIFT   8
  #define XOSPIPSV_SRAM_PARTITION_CFG_REG_SRAM_PARTITION_RESV_FLD_WIDTH   24
  #define XOSPIPSV_SRAM_PARTITION_CFG_REG_SRAM_PARTITION_RESV_FLD_MASK    0XFFFFFF00U
  
  #define XOSPIPSV_SRAM_PARTITION_CFG_REG_ADDR_FLD_SHIFT   0
  #define XOSPIPSV_SRAM_PARTITION_CFG_REG_ADDR_FLD_WIDTH   8
  #define XOSPIPSV_SRAM_PARTITION_CFG_REG_ADDR_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_IND_AHB_ADDR_TRIGGER_REG
   */
  #define XOSPIPSV_IND_AHB_ADDR_TRIGGER_REG    0X0000001CU
  
  #define XOSPIPSV_IND_AHB_ADDR_TRIGGER_REG_ADDR_FLD_SHIFT   0
  #define XOSPIPSV_IND_AHB_ADDR_TRIGGER_REG_ADDR_FLD_WIDTH   32
  #define XOSPIPSV_IND_AHB_ADDR_TRIGGER_REG_ADDR_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_DMA_PERIPH_CONFIG_REG
   */
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG    0X00000020U
  
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_DMA_PERIPH_RESV2_FLD_SHIFT   12
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_DMA_PERIPH_RESV2_FLD_WIDTH   20
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_DMA_PERIPH_RESV2_FLD_MASK    0XFFFFF000U
  
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_NUM_BURST_REQ_BYTES_FLD_SHIFT   8
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_NUM_BURST_REQ_BYTES_FLD_WIDTH   4
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_NUM_BURST_REQ_BYTES_FLD_MASK    0X00000F00U
  
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_DMA_PERIPH_RESV1_FLD_SHIFT   4
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_DMA_PERIPH_RESV1_FLD_WIDTH   4
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_DMA_PERIPH_RESV1_FLD_MASK    0X000000F0U
  
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_NUM_SINGLE_REQ_BYTES_FLD_SHIFT   0
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_NUM_SINGLE_REQ_BYTES_FLD_WIDTH   4
  #define XOSPIPSV_DMA_PERIPH_CONFIG_REG_NUM_SINGLE_REQ_BYTES_FLD_MASK    0X0000000FU
  
  /**
   * Register: OSPI_REMAP_ADDR_REG
   */
  #define XOSPIPSV_REMAP_ADDR_REG    0X00000024U
  
  #define XOSPIPSV_REMAP_ADDR_REG_VALUE_FLD_SHIFT   0
  #define XOSPIPSV_REMAP_ADDR_REG_VALUE_FLD_WIDTH   32
  #define XOSPIPSV_REMAP_ADDR_REG_VALUE_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_MODE_BIT_CONFIG_REG
   */
  #define XOSPIPSV_MODE_BIT_CONFIG_REG    0X00000028U
  
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_RX_CRC_DATA_LOW_FLD_SHIFT   24
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_RX_CRC_DATA_LOW_FLD_WIDTH   8
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_RX_CRC_DATA_LOW_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_RX_CRC_DATA_UP_FLD_SHIFT   16
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_RX_CRC_DATA_UP_FLD_WIDTH   8
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_RX_CRC_DATA_UP_FLD_MASK    0X00FF0000U
  
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_CRC_OUT_ENABLE_FLD_SHIFT   15
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_CRC_OUT_ENABLE_FLD_WIDTH   1
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_CRC_OUT_ENABLE_FLD_MASK    0X00008000U
  
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_MODE_BIT_RESV1_FLD_SHIFT   11
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_MODE_BIT_RESV1_FLD_WIDTH   4
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_MODE_BIT_RESV1_FLD_MASK    0X00007800U
  
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_CHUNK_SIZE_FLD_SHIFT   8
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_CHUNK_SIZE_FLD_WIDTH   3
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_CHUNK_SIZE_FLD_MASK    0X00000700U
  
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_MODE_FLD_SHIFT   0
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_MODE_FLD_WIDTH   8
  #define XOSPIPSV_MODE_BIT_CONFIG_REG_MODE_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_SRAM_FILL_REG
   */
  #define XOSPIPSV_SRAM_FILL_REG    0X0000002CU
  
  #define XOSPIPSV_SRAM_FILL_REG_SRAM_FILL_INDAC_WRITE_FLD_SHIFT   16
  #define XOSPIPSV_SRAM_FILL_REG_SRAM_FILL_INDAC_WRITE_FLD_WIDTH   16
  #define XOSPIPSV_SRAM_FILL_REG_SRAM_FILL_INDAC_WRITE_FLD_MASK    0XFFFF0000U
  
  #define XOSPIPSV_SRAM_FILL_REG_SRAM_FILL_INDAC_READ_FLD_SHIFT   0
  #define XOSPIPSV_SRAM_FILL_REG_SRAM_FILL_INDAC_READ_FLD_WIDTH   16
  #define XOSPIPSV_SRAM_FILL_REG_SRAM_FILL_INDAC_READ_FLD_MASK    0X0000FFFFU
  
  /**
   * Register: OSPI_TX_THRESH_REG
   */
  #define XOSPIPSV_TX_THRESH_REG    0X00000030U
  
  #define XOSPIPSV_TX_THRESH_REG_TX_THRESH_RESV_FLD_SHIFT   5
  #define XOSPIPSV_TX_THRESH_REG_TX_THRESH_RESV_FLD_WIDTH   27
  #define XOSPIPSV_TX_THRESH_REG_TX_THRESH_RESV_FLD_MASK    0XFFFFFFE0U
  
  #define XOSPIPSV_TX_THRESH_REG_LEVEL_FLD_SHIFT   0
  #define XOSPIPSV_TX_THRESH_REG_LEVEL_FLD_WIDTH   5
  #define XOSPIPSV_TX_THRESH_REG_LEVEL_FLD_MASK    0X0000001FU
  
  /**
   * Register: OSPI_RX_THRESH_REG
   */
  #define XOSPIPSV_RX_THRESH_REG    0X00000034U
  
  #define XOSPIPSV_RX_THRESH_REG_RX_THRESH_RESV_FLD_SHIFT   5
  #define XOSPIPSV_RX_THRESH_REG_RX_THRESH_RESV_FLD_WIDTH   27
  #define XOSPIPSV_RX_THRESH_REG_RX_THRESH_RESV_FLD_MASK    0XFFFFFFE0U
  
  #define XOSPIPSV_RX_THRESH_REG_LEVEL_FLD_SHIFT   0
  #define XOSPIPSV_RX_THRESH_REG_LEVEL_FLD_WIDTH   5
  #define XOSPIPSV_RX_THRESH_REG_LEVEL_FLD_MASK    0X0000001FU
  
  /**
   * Register: OSPI_WRITE_COMPLETION_CTRL_REG
   */
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG    0X00000038U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLL_REP_DELAY_FLD_SHIFT   24
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLL_REP_DELAY_FLD_WIDTH   8
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLL_REP_DELAY_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLL_COUNT_FLD_SHIFT   16
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLL_COUNT_FLD_WIDTH   8
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLL_COUNT_FLD_MASK    0X00FF0000U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_ENABLE_POLLING_EXP_FLD_SHIFT   15
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_ENABLE_POLLING_EXP_FLD_WIDTH   1
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_ENABLE_POLLING_EXP_FLD_MASK    0X00008000U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_DISABLE_POLLING_FLD_SHIFT   14
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_DISABLE_POLLING_FLD_WIDTH   1
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_DISABLE_POLLING_FLD_MASK    0X00004000U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_POLARITY_FLD_SHIFT   13
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_POLARITY_FLD_WIDTH   1
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_POLARITY_FLD_MASK    0X00002000U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_WR_COMP_CTRL_RESV1_FLD_SHIFT   12
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_WR_COMP_CTRL_RESV1_FLD_WIDTH   1
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_WR_COMP_CTRL_RESV1_FLD_MASK    0X00001000U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_ADDR_EN_FLD_SHIFT   11
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_ADDR_EN_FLD_WIDTH   1
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_ADDR_EN_FLD_MASK    0X00000800U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_BIT_INDEX_FLD_SHIFT   8
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_BIT_INDEX_FLD_WIDTH   3
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_POLLING_BIT_INDEX_FLD_MASK    0X00000700U
  
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_OPCODE_FLD_SHIFT   0
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_WRITE_COMPLETION_CTRL_REG_OPCODE_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_NO_OF_POLLS_BEF_EXP_REG
   */
  #define XOSPIPSV_NO_OF_POLLS_BEF_EXP_REG    0X0000003CU
  
  #define XOSPIPSV_NO_OF_POLLS_BEF_EXP_REG_NO_OF_POLLS_BEF_EXP_FLD_SHIFT   0
  #define XOSPIPSV_NO_OF_POLLS_BEF_EXP_REG_NO_OF_POLLS_BEF_EXP_FLD_WIDTH   32
  #define XOSPIPSV_NO_OF_POLLS_BEF_EXP_REG_NO_OF_POLLS_BEF_EXP_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_IRQ_STATUS_REG
   */
  #define XOSPIPSV_IRQ_STATUS_REG    0X00000040U
  
  #define XOSPIPSV_IRQ_STATUS_REG_IRQ_STAT_RESV_FLD_SHIFT   20
  #define XOSPIPSV_IRQ_STATUS_REG_IRQ_STAT_RESV_FLD_WIDTH   12
  #define XOSPIPSV_IRQ_STATUS_REG_IRQ_STAT_RESV_FLD_MASK    0XFFF00000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_ECC_FAIL_FLD_SHIFT   19
  #define XOSPIPSV_IRQ_STATUS_REG_ECC_FAIL_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_ECC_FAIL_FLD_MASK    0X00080000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_TX_CRC_CHUNK_BRK_FLD_SHIFT   18
  #define XOSPIPSV_IRQ_STATUS_REG_TX_CRC_CHUNK_BRK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_TX_CRC_CHUNK_BRK_FLD_MASK    0X00040000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_RX_CRC_DATA_VAL_FLD_SHIFT   17
  #define XOSPIPSV_IRQ_STATUS_REG_RX_CRC_DATA_VAL_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_RX_CRC_DATA_VAL_FLD_MASK    0X00020000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_RX_CRC_DATA_ERR_FLD_SHIFT   16
  #define XOSPIPSV_IRQ_STATUS_REG_RX_CRC_DATA_ERR_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_RX_CRC_DATA_ERR_FLD_MASK    0X00010000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_IRQ_STAT_RESV1_FLD_SHIFT   15
  #define XOSPIPSV_IRQ_STATUS_REG_IRQ_STAT_RESV1_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_IRQ_STAT_RESV1_FLD_MASK    0X00008000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_STIG_REQ_INT_FLD_SHIFT   14
  #define XOSPIPSV_IRQ_STATUS_REG_STIG_REQ_INT_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_STIG_REQ_INT_FLD_MASK    0X00004000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_POLL_EXP_INT_FLD_SHIFT   13
  #define XOSPIPSV_IRQ_STATUS_REG_POLL_EXP_INT_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_POLL_EXP_INT_FLD_MASK    0X00002000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_INDRD_SRAM_FULL_FLD_SHIFT   12
  #define XOSPIPSV_IRQ_STATUS_REG_INDRD_SRAM_FULL_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_INDRD_SRAM_FULL_FLD_MASK    0X00001000U
  
  #define XOSPIPSV_IRQ_STATUS_REG_RX_FIFO_FULL_FLD_SHIFT   11
  #define XOSPIPSV_IRQ_STATUS_REG_RX_FIFO_FULL_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_RX_FIFO_FULL_FLD_MASK    0X00000800U
  
  #define XOSPIPSV_IRQ_STATUS_REG_RX_FIFO_NOT_EMPTY_FLD_SHIFT   10
  #define XOSPIPSV_IRQ_STATUS_REG_RX_FIFO_NOT_EMPTY_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_RX_FIFO_NOT_EMPTY_FLD_MASK    0X00000400U
  
  #define XOSPIPSV_IRQ_STATUS_REG_TX_FIFO_FULL_FLD_SHIFT   9
  #define XOSPIPSV_IRQ_STATUS_REG_TX_FIFO_FULL_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_TX_FIFO_FULL_FLD_MASK    0X00000200U
  
  #define XOSPIPSV_IRQ_STATUS_REG_TX_FIFO_NOT_FULL_FLD_SHIFT   8
  #define XOSPIPSV_IRQ_STATUS_REG_TX_FIFO_NOT_FULL_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_TX_FIFO_NOT_FULL_FLD_MASK    0X00000100U
  
  #define XOSPIPSV_IRQ_STATUS_REG_RECV_OVERFLOW_FLD_SHIFT   7
  #define XOSPIPSV_IRQ_STATUS_REG_RECV_OVERFLOW_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_RECV_OVERFLOW_FLD_MASK    0X00000080U
  
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_SHIFT   6
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_MASK    0X00000040U
  
  #define XOSPIPSV_IRQ_STATUS_REG_ILLEGAL_ACCESS_DET_FLD_SHIFT   5
  #define XOSPIPSV_IRQ_STATUS_REG_ILLEGAL_ACCESS_DET_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_ILLEGAL_ACCESS_DET_FLD_MASK    0X00000020U
  
  #define XOSPIPSV_IRQ_STATUS_REG_PROT_WR_ATTEMPT_FLD_SHIFT   4
  #define XOSPIPSV_IRQ_STATUS_REG_PROT_WR_ATTEMPT_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_PROT_WR_ATTEMPT_FLD_MASK    0X00000010U
  
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_TRANSFER_REJECT_FLD_SHIFT   3
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_TRANSFER_REJECT_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_TRANSFER_REJECT_FLD_MASK    0X00000008U
  
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_SHIFT   2
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK    0X00000004U
  
  #define XOSPIPSV_IRQ_STATUS_REG_UNDERFLOW_DET_FLD_SHIFT   1
  #define XOSPIPSV_IRQ_STATUS_REG_UNDERFLOW_DET_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_UNDERFLOW_DET_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_IRQ_STATUS_REG_MODE_M_FAIL_FLD_SHIFT   0
  #define XOSPIPSV_IRQ_STATUS_REG_MODE_M_FAIL_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_STATUS_REG_MODE_M_FAIL_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_IRQ_MASK_REG
   */
  #define XOSPIPSV_IRQ_MASK_REG    0X00000044U
  
  #define XOSPIPSV_IRQ_MASK_REG_IRQ_MASK_RESV_FLD_SHIFT   20
  #define XOSPIPSV_IRQ_MASK_REG_IRQ_MASK_RESV_FLD_WIDTH   12
  #define XOSPIPSV_IRQ_MASK_REG_IRQ_MASK_RESV_FLD_MASK    0XFFF00000U
  
  #define XOSPIPSV_IRQ_MASK_REG_TX_CRC_CHUNK_BRK_MASK_FLD_SHIFT   18
  #define XOSPIPSV_IRQ_MASK_REG_TX_CRC_CHUNK_BRK_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_TX_CRC_CHUNK_BRK_MASK_FLD_MASK    0X00040000U
  
  #define XOSPIPSV_IRQ_MASK_REG_RX_CRC_DATA_VAL_MASK_FLD_SHIFT   17
  #define XOSPIPSV_IRQ_MASK_REG_RX_CRC_DATA_VAL_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_RX_CRC_DATA_VAL_MASK_FLD_MASK    0X00020000U
  
  #define XOSPIPSV_IRQ_MASK_REG_RX_CRC_DATA_ERR_MASK_FLD_SHIFT   16
  #define XOSPIPSV_IRQ_MASK_REG_RX_CRC_DATA_ERR_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_RX_CRC_DATA_ERR_MASK_FLD_MASK    0X00010000U
  
  #define XOSPIPSV_IRQ_MASK_REG_IRQ_MASK_RESV1_FLD_SHIFT   15
  #define XOSPIPSV_IRQ_MASK_REG_IRQ_MASK_RESV1_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_IRQ_MASK_RESV1_FLD_MASK    0X00008000U
  
  #define XOSPIPSV_IRQ_MASK_REG_STIG_REQ_MASK_FLD_SHIFT   14
  #define XOSPIPSV_IRQ_MASK_REG_STIG_REQ_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_STIG_REQ_MASK_FLD_MASK    0X00004000U
  
  #define XOSPIPSV_IRQ_MASK_REG_POLL_EXP_INT_MASK_FLD_SHIFT   13
  #define XOSPIPSV_IRQ_MASK_REG_POLL_EXP_INT_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_POLL_EXP_INT_MASK_FLD_MASK    0X00002000U
  
  #define XOSPIPSV_IRQ_MASK_REG_INDRD_SRAM_FULL_MASK_FLD_SHIFT   12
  #define XOSPIPSV_IRQ_MASK_REG_INDRD_SRAM_FULL_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_INDRD_SRAM_FULL_MASK_FLD_MASK    0X00001000U
  
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_XFER_LEVEL_BREACH_MASK_FLD_SHIFT   6
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_XFER_LEVEL_BREACH_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_XFER_LEVEL_BREACH_MASK_FLD_MASK    0X00000040U
  
  #define XOSPIPSV_IRQ_MASK_REG_ILLEGAL_ACCESS_DET_MASK_FLD_SHIFT   5
  #define XOSPIPSV_IRQ_MASK_REG_ILLEGAL_ACCESS_DET_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_ILLEGAL_ACCESS_DET_MASK_FLD_MASK    0X00000020U
  
  #define XOSPIPSV_IRQ_MASK_REG_PROT_WR_ATTEMPT_MASK_FLD_SHIFT   4
  #define XOSPIPSV_IRQ_MASK_REG_PROT_WR_ATTEMPT_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_PROT_WR_ATTEMPT_MASK_FLD_MASK    0X00000010U
  
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_TRANSFER_REJECT_MASK_FLD_SHIFT   3
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_TRANSFER_REJECT_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_TRANSFER_REJECT_MASK_FLD_MASK    0X00000008U
  
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_OP_DONE_MASK_FLD_SHIFT   2
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_OP_DONE_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_INDIRECT_OP_DONE_MASK_FLD_MASK    0X00000004U
  
  #define XOSPIPSV_IRQ_MASK_REG_UNDERFLOW_DET_MASK_FLD_SHIFT   1
  #define XOSPIPSV_IRQ_MASK_REG_UNDERFLOW_DET_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_UNDERFLOW_DET_MASK_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_IRQ_MASK_REG_MODE_M_FAIL_MASK_FLD_SHIFT   0
  #define XOSPIPSV_IRQ_MASK_REG_MODE_M_FAIL_MASK_FLD_WIDTH   1
  #define XOSPIPSV_IRQ_MASK_REG_MODE_M_FAIL_MASK_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_LOWER_WR_PROT_REG
   */
  #define XOSPIPSV_LOWER_WR_PROT_REG    0X00000050U
  
  #define XOSPIPSV_LOWER_WR_PROT_REG_SUBSECTOR_FLD_SHIFT   0
  #define XOSPIPSV_LOWER_WR_PROT_REG_SUBSECTOR_FLD_WIDTH   32
  #define XOSPIPSV_LOWER_WR_PROT_REG_SUBSECTOR_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_UPPER_WR_PROT_REG
   */
  #define XOSPIPSV_UPPER_WR_PROT_REG    0X00000054U
  
  #define XOSPIPSV_UPPER_WR_PROT_REG_SUBSECTOR_FLD_SHIFT   0
  #define XOSPIPSV_UPPER_WR_PROT_REG_SUBSECTOR_FLD_WIDTH   32
  #define XOSPIPSV_UPPER_WR_PROT_REG_SUBSECTOR_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_WR_PROT_CTRL_REG
   */
  #define XOSPIPSV_WR_PROT_CTRL_REG   0X00000058U
  
  #define XOSPIPSV_WR_PROT_CTRL_REG_WR_PROT_CTRL_RESV_FLD_SHIFT   2
  #define XOSPIPSV_WR_PROT_CTRL_REG_WR_PROT_CTRL_RESV_FLD_WIDTH   30
  #define XOSPIPSV_WR_PROT_CTRL_REG_WR_PROT_CTRL_RESV_FLD_MASK    0XFFFFFFFCU
  
  #define XOSPIPSV_WR_PROT_CTRL_REG_ENB_FLD_SHIFT   1
  #define XOSPIPSV_WR_PROT_CTRL_REG_ENB_FLD_WIDTH   1
  #define XOSPIPSV_WR_PROT_CTRL_REG_ENB_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_WR_PROT_CTRL_REG_INV_FLD_SHIFT   0
  #define XOSPIPSV_WR_PROT_CTRL_REG_INV_FLD_WIDTH   1
  #define XOSPIPSV_WR_PROT_CTRL_REG_INV_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_INDIRECT_READ_XFER_CTRL_REG
   */
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG    0X00000060U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_INDIR_RD_XFER_RESV_FLD_SHIFT   8
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_INDIR_RD_XFER_RESV_FLD_WIDTH   24
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_INDIR_RD_XFER_RESV_FLD_MASK    0XFFFFFF00U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD_SHIFT   6
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD_WIDTH   2
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD_MASK    0X000000C0U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_SHIFT   5
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_MASK    0X00000020U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_RD_QUEUED_FLD_SHIFT   4
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_RD_QUEUED_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_RD_QUEUED_FLD_MASK    0X00000010U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_SRAM_FULL_FLD_SHIFT   3
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_SRAM_FULL_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_SRAM_FULL_FLD_MASK    0X00000008U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_RD_STATUS_FLD_SHIFT   2
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_RD_STATUS_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_RD_STATUS_FLD_MASK    0X00000004U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_CANCEL_FLD_SHIFT   1
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_CANCEL_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_CANCEL_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_START_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_START_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_READ_XFER_CTRL_REG_START_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_INDIRECT_READ_XFER_WATERMARK_REG
   */
  #define XOSPIPSV_INDIRECT_READ_XFER_WATERMARK_REG    0X00000064U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_WATERMARK_REG_LEVEL_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_READ_XFER_WATERMARK_REG_LEVEL_FLD_WIDTH   32
  #define XOSPIPSV_INDIRECT_READ_XFER_WATERMARK_REG_LEVEL_FLD_MASK    0XFFFFFFFF
  
  /**
   * Register: OSPI_INDIRECT_READ_XFER_START_REG
   */
  #define XOSPIPSV_INDIRECT_READ_XFER_START_REG    0X00000068U
  
  #define XOSPIPSV_INDIRECT_READ_XFER_START_REG_ADDR_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_READ_XFER_START_REG_ADDR_FLD_WIDTH   32
  #define XOSPIPSV_INDIRECT_READ_XFER_START_REG_ADDR_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG
   */
  #define XOSPIPSV_INDIRECT_READ_XFER_NUM_BYTES_REG   0X0000006CU
  
  #define XOSPIPSV_INDIRECT_READ_XFER_NUM_BYTES_REG_VALUE_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_READ_XFER_NUM_BYTES_REG_VALUE_FLD_WIDTH   32
  #define XOSPIPSV_INDIRECT_READ_XFER_NUM_BYTES_REG_VALUE_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_INDIRECT_WRITE_XFER_CTRL_REG
   */
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG    0X00000070U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_INDIR_WR_XFER_RESV2_FLD_SHIFT   8
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_INDIR_WR_XFER_RESV2_FLD_WIDTH   24
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_INDIR_WR_XFER_RESV2_FLD_MASK    0XFFFFFF00U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD_SHIFT   6
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD_WIDTH   2
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD_MASK    0X000000C0U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_SHIFT   5
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_MASK    0X00000020U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_WR_QUEUED_FLD_SHIFT   4
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_WR_QUEUED_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_WR_QUEUED_FLD_MASK    0X00000010U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_INDIR_WR_XFER_RESV1_FLD_SHIFT   3
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_INDIR_WR_XFER_RESV1_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_INDIR_WR_XFER_RESV1_FLD_MASK    0X00000008
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_WR_STATUS_FLD_SHIFT   2
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_WR_STATUS_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_WR_STATUS_FLD_MASK    0X00000004U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_CANCEL_FLD_SHIFT   1
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_CANCEL_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_CANCEL_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_START_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_START_FLD_WIDTH   1
  #define XOSPIPSV_INDIRECT_WRITE_XFER_CTRL_REG_START_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG
   */
  #define XOSPIPSV_INDIRECT_WRITE_XFER_WATERMARK_REG    0X00000074U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_WATERMARK_REG_LEVEL_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_WRITE_XFER_WATERMARK_REG_LEVEL_FLD_WIDTH   32
  #define XOSPIPSV_INDIRECT_WRITE_XFER_WATERMARK_REG_LEVEL_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_INDIRECT_WRITE_XFER_START_REG
   */
  #define XOSPIPSV_INDIRECT_WRITE_XFER_START_REG    0X00000078U
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_START_REG_ADDR_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_WRITE_XFER_START_REG_ADDR_FLD_WIDTH   32
  #define XOSPIPSV_INDIRECT_WRITE_XFER_START_REG_ADDR_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG
   */
  #define XOSPIPSV_INDIRECT_WRITE_XFER_NUM_BYTES_REG    0X0000007CU
  
  #define XOSPIPSV_INDIRECT_WRITE_XFER_NUM_BYTES_REG_VALUE_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_WRITE_XFER_NUM_BYTES_REG_VALUE_FLD_WIDTH   32
  #define XOSPIPSV_INDIRECT_WRITE_XFER_NUM_BYTES_REG_VALUE_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG
   */
  #define XOSPIPSV_INDIRECT_TRIGGER_ADDR_RANGE_REG    0X00000080U
  
  #define XOSPIPSV_INDIRECT_TRIGGER_ADDR_RANGE_REG_IND_RANGE_RESV1_FLD_SHIFT   4
  #define XOSPIPSV_INDIRECT_TRIGGER_ADDR_RANGE_REG_IND_RANGE_RESV1_FLD_WIDTH   28
  #define XOSPIPSV_INDIRECT_TRIGGER_ADDR_RANGE_REG_IND_RANGE_RESV1_FLD_MASK    0XFFFFFFF0U
  
  #define XOSPIPSV_INDIRECT_TRIGGER_ADDR_RANGE_REG_IND_RANGE_WIDTH_FLD_SHIFT   0
  #define XOSPIPSV_INDIRECT_TRIGGER_ADDR_RANGE_REG_IND_RANGE_WIDTH_FLD_WIDTH   4
  #define XOSPIPSV_INDIRECT_TRIGGER_ADDR_RANGE_REG_IND_RANGE_WIDTH_FLD_MASK    0X0000000FU
  
  /**
   * Register: OSPI_FLASH_COMMAND_CTRL_MEM_REG
   */
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG    0X0000008CU
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV1_FLD_SHIFT   29
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV1_FLD_WIDTH   3
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV1_FLD_MASK    0XE0000000U
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_ADDR_FLD_SHIFT   20
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_ADDR_FLD_WIDTH   9
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_ADDR_FLD_MASK    0X1FF00000U
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV2_FLD_SHIFT   19
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV2_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV2_FLD_MASK    0X00080000U
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_NB_OF_STIG_READ_BYTES_FLD_SHIFT   16
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_NB_OF_STIG_READ_BYTES_FLD_WIDTH   3
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_NB_OF_STIG_READ_BYTES_FLD_MASK    0X00070000U
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_READ_DATA_FLD_SHIFT   8
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_READ_DATA_FLD_WIDTH   8
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_READ_DATA_FLD_MASK    0X0000FF00U
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV3_FLD_SHIFT   2
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV3_FLD_WIDTH   6
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_FLASH_COMMAND_CTRL_MEM_RESV3_FLD_MASK    0X000000FCU
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_REQ_IN_PROGRESS_FLD_SHIFT   1
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_REQ_IN_PROGRESS_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_MEM_BANK_REQ_IN_PROGRESS_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_TRIGGER_MEM_BANK_REQ_FLD_SHIFT   0
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_TRIGGER_MEM_BANK_REQ_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_COMMAND_CTRL_MEM_REG_TRIGGER_MEM_BANK_REQ_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_FLASH_CMD_CTRL_REG
   */
  #define XOSPIPSV_FLASH_CMD_CTRL_REG    0X00000090U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_OPCODE_FLD_SHIFT   24
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_OPCODE_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_READ_DATA_FLD_SHIFT   23
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_READ_DATA_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_READ_DATA_FLD_MASK    0X00800000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_RD_DATA_BYTES_FLD_SHIFT   20
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_RD_DATA_BYTES_FLD_WIDTH   3
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_RD_DATA_BYTES_FLD_MASK    0X00700000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_COMD_ADDR_FLD_SHIFT   19
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_COMD_ADDR_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_COMD_ADDR_FLD_MASK    0X00080000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_MODE_BIT_FLD_SHIFT   18
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_MODE_BIT_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_MODE_BIT_FLD_MASK    0X00040000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES_FLD_SHIFT   16
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES_FLD_WIDTH   2
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES_FLD_MASK    0X00030000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_WRITE_DATA_FLD_SHIFT   15
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_WRITE_DATA_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_ENB_WRITE_DATA_FLD_MASK    0X00008000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_WR_DATA_BYTES_FLD_SHIFT   12
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_WR_DATA_BYTES_FLD_WIDTH   3
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_WR_DATA_BYTES_FLD_MASK    0X00007000U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_DUMMY_CYCLES_FLD_SHIFT   7
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_DUMMY_CYCLES_FLD_WIDTH   5
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_NUM_DUMMY_CYCLES_FLD_MASK    0X00000F80U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_FLASH_CMD_CTRL_RESV1_FLD_SHIFT   3
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_FLASH_CMD_CTRL_RESV1_FLD_WIDTH   4
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_FLASH_CMD_CTRL_RESV1_FLD_MASK    0X00000078U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_STIG_MEM_BANK_EN_FLD_SHIFT   2
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_STIG_MEM_BANK_EN_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_STIG_MEM_BANK_EN_FLD_MASK    0X00000004U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_EXEC_STATUS_FLD_SHIFT   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_EXEC_STATUS_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_EXEC_STATUS_FLD_MASK    0X00000002U
  
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_EXEC_FLD_SHIFT   0
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_EXEC_FLD_WIDTH   1
  #define XOSPIPSV_FLASH_CMD_CTRL_REG_CMD_EXEC_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_FLASH_CMD_ADDR_REG
   */
  #define XOSPIPSV_FLASH_CMD_ADDR_REG    0X00000094U
  
  #define XOSPIPSV_FLASH_CMD_ADDR_REG_ADDR_FLD_SHIFT   0
  #define XOSPIPSV_FLASH_CMD_ADDR_REG_ADDR_FLD_WIDTH   32
  #define XOSPIPSV_FLASH_CMD_ADDR_REG_ADDR_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_FLASH_RD_DATA_LOWER_REG
   */
  #define XOSPIPSV_FLASH_RD_DATA_LOWER_REG    0X000000A0U
  
  #define XOSPIPSV_FLASH_RD_DATA_LOWER_REG_DATA_FLD_SHIFT   0
  #define XOSPIPSV_FLASH_RD_DATA_LOWER_REG_DATA_FLD_WIDTH   32
  #define XOSPIPSV_FLASH_RD_DATA_LOWER_REG_DATA_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_FLASH_RD_DATA_UPPER_REG
   */
  #define XOSPIPSV_FLASH_RD_DATA_UPPER_REG    0X000000A4U
  
  #define XOSPIPSV_FLASH_RD_DATA_UPPER_REG_DATA_FLD_SHIFT   0
  #define XOSPIPSV_FLASH_RD_DATA_UPPER_REG_DATA_FLD_WIDTH   32
  #define XOSPIPSV_FLASH_RD_DATA_UPPER_REG_DATA_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_FLASH_WR_DATA_LOWER_REG
   */
  #define XOSPIPSV_FLASH_WR_DATA_LOWER_REG    0X000000A8U
  
  #define XOSPIPSV_FLASH_WR_DATA_LOWER_REG_DATA_FLD_SHIFT   0
  #define XOSPIPSV_FLASH_WR_DATA_LOWER_REG_DATA_FLD_WIDTH   32
  #define XOSPIPSV_FLASH_WR_DATA_LOWER_REG_DATA_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_FLASH_WR_DATA_UPPER_REG
   */
  #define XOSPIPSV_FLASH_WR_DATA_UPPER_REG    0X000000ACU
  
  #define XOSPIPSV_FLASH_WR_DATA_UPPER_REG_DATA_FLD_SHIFT   0
  #define XOSPIPSV_FLASH_WR_DATA_UPPER_REG_DATA_FLD_WIDTH   32
  #define XOSPIPSV_FLASH_WR_DATA_UPPER_REG_DATA_FLD_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_POLLING_FLASH_STATUS_REG
   */
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG    0X000000B0U
  
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_RSVD_FLD2_SHIFT   21
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_RSVD_FLD2_WIDTH   11
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_RSVD_FLD2_MASK    0XFFE00000U
  
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_NB_DUMMY_SHIFT   16
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_NB_DUMMY_WIDTH   5
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_NB_DUMMY_MASK    0X001F0000U
  
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_RSVD_FLD1_SHIFT   9
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_RSVD_FLD1_WIDTH   7
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_RSVD_FLD1_MASK    0X0000FE00U
  
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_VALID_FLD_SHIFT   8
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_VALID_FLD_WIDTH   1
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_VALID_FLD_MASK    0X00000100U
  
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_FLD_SHIFT   0
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_FLD_WIDTH   8
  #define XOSPIPSV_POLLING_FLASH_STATUS_REG_DEVICE_STATUS_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_PHY_CONFIGURATION_REG
   */
  #define XOSPIPSV_PHY_CONFIGURATION_REG    0X000000B4U
  
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESYNC_FLD_SHIFT   31
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESYNC_FLD_WIDTH   1
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESYNC_FLD_MASK    0X80000000U
  
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESET_FLD_SHIFT   30
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESET_FLD_WIDTH   1
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESET_FLD_MASK    0X40000000U
  
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_BYPASS_FLD_SHIFT   29
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_BYPASS_FLD_WIDTH   1
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_BYPASS_FLD_MASK    0X20000000U
  
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESV2_FLD_SHIFT   23
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESV2_FLD_WIDTH   6
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESV2_FLD_MASK    0X1F800000U
  
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_TX_DLL_DELAY_FLD_SHIFT   16
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_TX_DLL_DELAY_FLD_WIDTH   7
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_TX_DLL_DELAY_FLD_MASK    0X007F0000U
  
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESV1_FLD_SHIFT   7
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESV1_FLD_WIDTH   9
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RESV1_FLD_MASK    0X0000FF80U
  
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_DELAY_FLD_SHIFT   0
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_DELAY_FLD_WIDTH   7
  #define XOSPIPSV_PHY_CONFIGURATION_REG_PHY_CONFIG_RX_DLL_DELAY_FLD_MASK    0X0000007FU
  
  /**
   * Register: OSPI_PHY_MASTER_CONTROL_REG
   */
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG    0X000000B8U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV3_FLD_SHIFT   25
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV3_FLD_WIDTH   7
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV3_FLD_MASK    0XFE000000U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_LOCK_MODE_FLD_SHIFT   24
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_LOCK_MODE_FLD_WIDTH   1
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_LOCK_MODE_FLD_MASK    0X01000000U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_BYPASS_MODE_FLD_SHIFT   23
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_BYPASS_MODE_FLD_WIDTH   1
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_BYPASS_MODE_FLD_MASK    0X00800000U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_PHASE_DETECT_SELECTOR_FLD_SHIFT   20
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_PHASE_DETECT_SELECTOR_FLD_WIDTH   3
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_PHASE_DETECT_SELECTOR_FLD_MASK    0X00700000U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV2_FLD_SHIFT   19
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV2_FLD_WIDTH   1
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV2_FLD_MASK    0X00080000U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_NB_INDICATIONS_FLD_SHIFT   16
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_NB_INDICATIONS_FLD_WIDTH   3
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_NB_INDICATIONS_FLD_MASK    0X00070000U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV1_FLD_SHIFT   7
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV1_FLD_WIDTH   9
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_CONTROL_RESV1_FLD_MASK    0X0000FF80U
  
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_INITIAL_DELAY_FLD_SHIFT   0
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_INITIAL_DELAY_FLD_WIDTH   7
  #define XOSPIPSV_PHY_MASTER_CONTROL_REG_PHY_MASTER_INITIAL_DELAY_FLD_MASK    0X0000007FU
  
  /**
   * Register: OSPI_DLL_OBSERVABLE_LOWER_REG
   */
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG    0X000000BCU
  
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD_SHIFT   24
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD_WIDTH   8
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD_SHIFT   16
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD_WIDTH   8
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD_MASK    0X00FF0000U
  
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD_SHIFT   15
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD_WIDTH   1
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD_MASK    0X00008000U
  
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD_SHIFT   8
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD_WIDTH   7
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD_MASK    0X00007F00U
  
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD_SHIFT   3
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD_WIDTH   5
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD_MASK    0X000000F8U
  
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD_SHIFT   1
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD_WIDTH   2
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD_MASK    0X00000006U
  
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD_SHIFT   0
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD_WIDTH   1
  #define XOSPIPSV_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD_MASK    0X00000001U
  
  /**
   * Register: OSPI_DLL_OBSERVABLE_UPPER_REG
   */
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG    0X000000C0U
  
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_RESV2_FLD_SHIFT   23
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_RESV2_FLD_WIDTH   9
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_RESV2_FLD_MASK    0XFF800000U
  
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD_SHIFT   16
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD_WIDTH   7
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD_MASK    0X007F0000U
  
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_RESV1_FLD_SHIFT   7
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_RESV1_FLD_WIDTH   9
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE_UPPER_RESV1_FLD_MASK    0X0000FF80U
  
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD_SHIFT   0
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD_WIDTH   7
  #define XOSPIPSV_DLL_OBSERVABLE_UPPER_REG_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD_MASK    0X0000007FU
  
  /**
   * Register: OSPI_OPCODE_EXT_LOWER_REG
   */
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG    0X000000E0U
  
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_READ_OPCODE_FLD_SHIFT   24
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_READ_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_READ_OPCODE_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_WRITE_OPCODE_FLD_SHIFT   16
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_WRITE_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_WRITE_OPCODE_FLD_MASK    0X00FF0000U
  
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_POLL_OPCODE_FLD_SHIFT   8
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_POLL_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_POLL_OPCODE_FLD_MASK    0X0000FF00U
  
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_STIG_OPCODE_FLD_SHIFT   0
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_STIG_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_OPCODE_EXT_LOWER_REG_EXT_STIG_OPCODE_FLD_MASK    0X000000FFU
  
  /**
   * Register: OSPI_OPCODE_EXT_UPPER_REG
   */
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG    0X000000E4U
  
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_WEL_OPCODE_FLD_SHIFT   24
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_WEL_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_WEL_OPCODE_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_EXT_WEL_OPCODE_FLD_SHIFT   16
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_EXT_WEL_OPCODE_FLD_WIDTH   8
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_EXT_WEL_OPCODE_FLD_MASK    0X00FF0000U
  
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_OPCODE_EXT_UPPER_RESV1_FLD_SHIFT   0
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_OPCODE_EXT_UPPER_RESV1_FLD_WIDTH   16
  #define XOSPIPSV_OPCODE_EXT_UPPER_REG_OPCODE_EXT_UPPER_RESV1_FLD_MASK    0X0000FFFFU
  
  /**
   * Register: OSPI_MODULE_ID_REG
   */
  #define XOSPIPSV_MODULE_ID_REG    0X000000FCU
  
  #define XOSPIPSV_MODULE_ID_REG_FIX_PATCH_FLD_SHIFT   24
  #define XOSPIPSV_MODULE_ID_REG_FIX_PATCH_FLD_WIDTH   8
  #define XOSPIPSV_MODULE_ID_REG_FIX_PATCH_FLD_MASK    0XFF000000U
  
  #define XOSPIPSV_MODULE_ID_REG_MODULE_ID_FLD_SHIFT   8
  #define XOSPIPSV_MODULE_ID_REG_MODULE_ID_FLD_WIDTH   16
  #define XOSPIPSV_MODULE_ID_REG_MODULE_ID_FLD_MASK    0X00FFFF00U
  
  #define XOSPIPSV_MODULE_ID_REG_MODULE_ID_RESV_FLD_SHIFT   2
  #define XOSPIPSV_MODULE_ID_REG_MODULE_ID_RESV_FLD_WIDTH   6
  #define XOSPIPSV_MODULE_ID_REG_MODULE_ID_RESV_FLD_MASK    0X000000FCU
  
  #define XOSPIPSV_MODULE_ID_REG_CONF_FLD_SHIFT   0
  #define XOSPIPSV_MODULE_ID_REG_CONF_FLD_WIDTH   2
  #define XOSPIPSV_MODULE_ID_REG_CONF_FLD_MASK    0X00000003U
  
  /**
   * Register: OSPI_OSPIDMA_SRC_RD_ADDR
   */
  #define XOSPIPSV_OSPIDMA_SRC_RD_ADDR    0X00001000U
  
  #define XOSPIPSV_OSPIDMA_SRC_RD_ADDR_ADDR_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_RD_ADDR_ADDR_WIDTH   32
  #define XOSPIPSV_OSPIDMA_SRC_RD_ADDR_ADDR_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_OSPIDMA_SRC_SIZE
   */
  #define XOSPIPSV_OSPIDMA_SRC_SIZE    0X00001004U
  
  #define XOSPIPSV_OSPIDMA_SRC_SIZE_SIZE_SHIFT   2
  #define XOSPIPSV_OSPIDMA_SRC_SIZE_SIZE_WIDTH   27
  #define XOSPIPSV_OSPIDMA_SRC_SIZE_SIZE_MASK    0X1FFFFFFCU
  
  /**
   * Register: OSPI_OSPIDMA_SRC_STS
   */
  #define XOSPIPSV_OSPIDMA_SRC_STS   0X00001008U
  
  #define XOSPIPSV_OSPIDMA_SRC_STS_DONE_CNT_SHIFT   13
  #define XOSPIPSV_OSPIDMA_SRC_STS_DONE_CNT_WIDTH   3
  #define XOSPIPSV_OSPIDMA_SRC_STS_DONE_CNT_MASK    0X0000E000U
  
  #define XOSPIPSV_OSPIDMA_SRC_STS_SRC_FIFO_LEVEL_SHIFT   5
  #define XOSPIPSV_OSPIDMA_SRC_STS_SRC_FIFO_LEVEL_WIDTH   8
  #define XOSPIPSV_OSPIDMA_SRC_STS_SRC_FIFO_LEVEL_MASK    0X00001FE0U
  
  #define XOSPIPSV_OSPIDMA_SRC_STS_RD_OUTSTANDING_SHIFT   1
  #define XOSPIPSV_OSPIDMA_SRC_STS_RD_OUTSTANDING_WIDTH   4
  #define XOSPIPSV_OSPIDMA_SRC_STS_RD_OUTSTANDING_MASK    0X0000001EU
  
  #define XOSPIPSV_OSPIDMA_SRC_STS_BUSY_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_STS_BUSY_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_STS_BUSY_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_SRC_CTRL
   */
  #define XOSPIPSV_OSPIDMA_SRC_CTRL    0X0000100CU
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_APB_ERR_RESP_SHIFT   24
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_APB_ERR_RESP_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_APB_ERR_RESP_MASK    0X01000000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_ENDIANNESS_SHIFT   23
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_ENDIANNESS_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_ENDIANNESS_MASK    0X00800000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_AXI_BRST_TYPE_SHIFT   22
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_AXI_BRST_TYPE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_AXI_BRST_TYPE_MASK    0X00400000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_TIMEOUT_VAL_SHIFT   10
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_TIMEOUT_VAL_WIDTH   12
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_TIMEOUT_VAL_MASK    0X003FFC00U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_FIFO_THRESH_SHIFT   2
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_FIFO_THRESH_WIDTH   8
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_FIFO_THRESH_MASK    0X000003FCU
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_PAUSE_STRM_SHIFT   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_PAUSE_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_PAUSE_STRM_MASK    0X00000002U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_PAUSE_MEM_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_PAUSE_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL_PAUSE_MEM_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_SRC_CRC
   */
  #define XOSPIPSV_OSPIDMA_SRC_CRC   0X00001010U
  
  #define XOSPIPSV_OSPIDMA_SRC_CRC_CRC_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_CRC_CRC_WIDTH   32
  #define XOSPIPSV_OSPIDMA_SRC_CRC_CRC_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_OSPIDMA_SRC_I_STS
   */
  #define XOSPIPSV_OSPIDMA_SRC_I_STS    0X00001014U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_AXI_RDERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_AXI_RDERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_AXI_RDERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_DONE_MASK    0X00000002U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_MEM_DONE_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_MEM_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_STS_MEM_DONE_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_SRC_I_EN
   */
  #define XOSPIPSV_OSPIDMA_SRC_I_EN    0X00001018U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_AXI_RDERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_AXI_RDERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_AXI_RDERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_DONE_MASK    0X00000002U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_MEM_DONE_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_MEM_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_EN_MEM_DONE_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_SRC_I_DIS
   */
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS    0X0000101CU
  
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_AXI_RDERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_AXI_RDERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_AXI_RDERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_DONE_MASK    0X00000002U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_MEM_DONE_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_MEM_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_DIS_MEM_DONE_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_SRC_I_MASK
   */
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK    0X00001020U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_AXI_RDERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_AXI_RDERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_AXI_RDERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_DONE_MASK    0X00000002U
  
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_MEM_DONE_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_MEM_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_I_MASK_MEM_DONE_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_SRC_CTRL2
   */
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2    0X00001024U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMASA_SHIFT   27
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMASA_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMASA_MASK    0X08000000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_ARCACHE_SHIFT   24
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_ARCACHE_WIDTH   3
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_ARCACHE_MASK    0X07000000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_TIMEOUT_EN_SHIFT   22
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_TIMEOUT_EN_WIDTH   1
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_TIMEOUT_EN_MASK    0X00400000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMAB_SHIFT   19
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMAB_WIDTH   3
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMAB_MASK    0X00380000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMAA_SHIFT   16
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMAA_WIDTH   3
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_RAM_EMAA_MASK    0X00070000U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_TIMEOUT_PRE_SHIFT   4
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_TIMEOUT_PRE_WIDTH   12
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_TIMEOUT_PRE_MASK    0X0000FFF0U
  
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_MAX_OUTS_CMDS_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_MAX_OUTS_CMDS_WIDTH   4
  #define XOSPIPSV_OSPIDMA_SRC_CTRL2_MAX_OUTS_CMDS_MASK    0X0000000FU
  
  /**
   * Register: OSPI_OSPIDMA_DST_ADDR
   */
  #define XOSPIPSV_OSPIDMA_DST_ADDR    0X00001800U
  
  #define XOSPIPSV_OSPIDMA_DST_ADDR_ADDR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_DST_ADDR_ADDR_WIDTH   30
  #define XOSPIPSV_OSPIDMA_DST_ADDR_ADDR_MASK    0XFFFFFFFCU
  
  /**
   * Register: OSPI_OSPIDMA_DST_SIZE
   */
  #define XOSPIPSV_OSPIDMA_DST_SIZE    0X00001804U
  
  #define XOSPIPSV_OSPIDMA_DST_SIZE_SIZE_SHIFT   2
  #define XOSPIPSV_OSPIDMA_DST_SIZE_SIZE_WIDTH   27
  #define XOSPIPSV_OSPIDMA_DST_SIZE_SIZE_MASK    0X1FFFFFFCU
  
  /**
   * Register: OSPI_OSPIDMA_DST_STS
   */
  #define XOSPIPSV_OSPIDMA_DST_STS    0X00001808U
  
  #define XOSPIPSV_OSPIDMA_DST_STS_DONE_CNT_SHIFT   13
  #define XOSPIPSV_OSPIDMA_DST_STS_DONE_CNT_WIDTH   3
  #define XOSPIPSV_OSPIDMA_DST_STS_DONE_CNT_MASK    0X0000E000U
  
  #define XOSPIPSV_OSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5
  #define XOSPIPSV_OSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8
  #define XOSPIPSV_OSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK    0X00001FE0U
  
  #define XOSPIPSV_OSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1
  #define XOSPIPSV_OSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4
  #define XOSPIPSV_OSPIDMA_DST_STS_WR_OUTSTANDING_MASK    0X0000001EU
  
  #define XOSPIPSV_OSPIDMA_DST_STS_BUSY_SHIFT   0
  #define XOSPIPSV_OSPIDMA_DST_STS_BUSY_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_STS_BUSY_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_DST_CTRL
   */
  #define XOSPIPSV_OSPIDMA_DST_CTRL    0X0000180CU
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_SSS_FIFOTHRESH_SHIFT   25
  #define XOSPIPSV_OSPIDMA_DST_CTRL_SSS_FIFOTHRESH_WIDTH   7
  #define XOSPIPSV_OSPIDMA_DST_CTRL_SSS_FIFOTHRESH_MASK    0XFE000000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24
  #define XOSPIPSV_OSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL_APB_ERR_RESP_MASK    0X01000000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_ENDIANNESS_SHIFT   23
  #define XOSPIPSV_OSPIDMA_DST_CTRL_ENDIANNESS_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL_ENDIANNESS_MASK    0X00800000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22
  #define XOSPIPSV_OSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK    0X00400000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_TIMEOUT_VAL_SHIFT   10
  #define XOSPIPSV_OSPIDMA_DST_CTRL_TIMEOUT_VAL_WIDTH   12
  #define XOSPIPSV_OSPIDMA_DST_CTRL_TIMEOUT_VAL_MASK    0X003FFC00U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_FIFO_THRESH_SHIFT   2
  #define XOSPIPSV_OSPIDMA_DST_CTRL_FIFO_THRESH_WIDTH   8
  #define XOSPIPSV_OSPIDMA_DST_CTRL_FIFO_THRESH_MASK    0X000003FCU
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL_PAUSE_STRM_MASK    0X00000002U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0
  #define XOSPIPSV_OSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL_PAUSE_MEM_MASK    0X00000001U
  
  /**
   * Register: OSPI_OSPIDMA_DST_I_STS
   */
  #define XOSPIPSV_OSPIDMA_DST_I_STS    0X00001814U
  
  #define XOSPIPSV_OSPIDMA_DST_I_STS_FIFO_OVERFLOW_SHIFT   7
  #define XOSPIPSV_OSPIDMA_DST_I_STS_FIFO_OVERFLOW_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_FIFO_OVERFLOW_MASK    0X00000080U
  
  #define XOSPIPSV_OSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_DST_I_STS_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_DST_I_STS_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_DST_I_STS_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_DST_I_STS_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_DST_I_STS_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_DST_I_STS_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_DST_I_STS_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_STS_DONE_MASK    0X00000002U
  
  /**
   * Register: OSPI_OSPIDMA_DST_I_EN
   */
  #define XOSPIPSV_OSPIDMA_DST_I_EN    0X00001818U
  
  #define XOSPIPSV_OSPIDMA_DST_I_EN_FIFO_OVERFLOW_SHIFT   7
  #define XOSPIPSV_OSPIDMA_DST_I_EN_FIFO_OVERFLOW_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_FIFO_OVERFLOW_MASK    0X00000080U
  
  #define XOSPIPSV_OSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_DST_I_EN_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_DST_I_EN_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_DST_I_EN_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_DST_I_EN_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_DST_I_EN_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_DST_I_EN_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_DST_I_EN_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_EN_DONE_MASK    0X00000002U
  
  /**
   * Register: OSPI_OSPIDMA_DST_I_DIS
   */
  #define XOSPIPSV_OSPIDMA_DST_I_DIS    0X0000181CU
  
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_FIFO_OVERFLOW_SHIFT   7
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_FIFO_OVERFLOW_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_FIFO_OVERFLOW_MASK    0X00000080U
  
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_DIS_DONE_MASK    0X00000002U
  
  /**
   * Register: OSPI_OSPIDMA_DST_I_MASK
   */
  #define XOSPIPSV_OSPIDMA_DST_I_MASK    0X00001820U
  
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_FIFO_OVERFLOW_SHIFT   7
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_FIFO_OVERFLOW_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_FIFO_OVERFLOW_MASK    0X00000080U
  
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_INVALID_APB_SHIFT   6
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_INVALID_APB_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_INVALID_APB_MASK    0X00000040U
  
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_THRESH_HIT_SHIFT   5
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_THRESH_HIT_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_THRESH_HIT_MASK    0X00000020U
  
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_TIMEOUT_MEM_SHIFT   4
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_TIMEOUT_MEM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_TIMEOUT_MEM_MASK    0X00000010U
  
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_TIMEOUT_STRM_SHIFT   3
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_TIMEOUT_STRM_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_TIMEOUT_STRM_MASK    0X00000008U
  
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_AXI_BRESP_ERR_SHIFT   2
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_AXI_BRESP_ERR_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_AXI_BRESP_ERR_MASK    0X00000004U
  
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_DONE_SHIFT   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_DONE_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_I_MASK_DONE_MASK    0X00000002U
  
  /**
   * Register: OSPI_OSPIDMA_DST_CTRL2
   */
  #define XOSPIPSV_OSPIDMA_DST_CTRL2    0X00001824U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMASA_MASK    0X08000000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_AWCACHE_MASK    0X07000000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_TIMEOUT_EN_SHIFT   22
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_TIMEOUT_EN_WIDTH   1
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_TIMEOUT_EN_MASK    0X00400000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMAB_MASK    0X00380000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_RAM_EMAA_MASK    0X00070000U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_TIMEOUT_PRE_SHIFT   4
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_TIMEOUT_PRE_WIDTH   12
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_TIMEOUT_PRE_MASK    0X0000FFF0U
  
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4
  #define XOSPIPSV_OSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK    0X0000000F
  
  /**
   * Register: OSPI_OSPIDMA_DST_ADDR_MSB
   */
  #define XOSPIPSV_OSPIDMA_DST_ADDR_MSB    0X00001828U
  
  #define XOSPIPSV_OSPIDMA_DST_ADDR_MSB_ADDR_MSB_SHIFT   0
  #define XOSPIPSV_OSPIDMA_DST_ADDR_MSB_ADDR_MSB_WIDTH   17
  #define XOSPIPSV_OSPIDMA_DST_ADDR_MSB_ADDR_MSB_MASK    0X0001FFFFU
  
  /**
   * Register: OSPI_OSPIDMA_SAFETY_CHK
   */
  #define XOSPIPSV_OSPIDMA_SAFETY_CHK   0X00001FF8U
  
  #define XOSPIPSV_OSPIDMA_SAFETY_CHK_CHK_VAL_SHIFT   0
  #define XOSPIPSV_OSPIDMA_SAFETY_CHK_CHK_VAL_WIDTH   32
  #define XOSPIPSV_OSPIDMA_SAFETY_CHK_CHK_VAL_MASK    0XFFFFFFFFU
  
  /**
   * Register: OSPI_OSPIDMA_FUTURE_ECO
   */
  #define XOSPIPSV_OSPIDMA_FUTURE_ECO    0X00001FFCU
  
  #define XOSPIPSV_OSPIDMA_FUTURE_ECO_VAL_SHIFT   0
  #define XOSPIPSV_OSPIDMA_FUTURE_ECO_VAL_WIDTH   32
  #define XOSPIPSV_OSPIDMA_FUTURE_ECO_VAL_MASK    0XFFFFFFFFU
  
  #define XOSPIPSV_IND_TRIGGAHB_BASE 0xC0000000U
  #define XOSPIPSV_IND_TRIGGER_RANGE 0x6
  #define XOSPIPSV_DMA_PERIPH_CONFIG_VAL 0x602
  #define XOSPIPSV_SRAM_PARTITION_CFG_VAL 0xFE
  #define SIZE_512MB (512U*1024U*1024U)
  #define XOSPIPSV_RXWATER_MARK_DEF 0x0
  #define XOSPIPSV_DMA_DST_CTRL_DEF	0xF43FFA00U
  #define XOSPIPSV_LINEAR_ADDR_BASE	0xC0000000U
  #define XOSPIPSV_DELY_DEF_VALUE		0x00000101U
  #define XOSPIPSV_DMA_DST_ADDR_MASK	0xFFFFFFFFU
  
  #define XPMC_IOU_SLCR_BASEADDR		0xF1060000U
  #define XPMC_IOU_SLCR_OSPI_MUX_SEL		0x00000504U
  #define XPMC_IOU_SLCR_OSPI_MUX_SEL_DAC_MASK		0x00000002U
  
  #define XPMC_MIO12_MASK		0x1000U
  #define XPMC_GPIO_DIRM		0xF1020204U
  #define XPMC_GPIO_OUTEN		0xF1020208U
  #define XPMC_GPIO_DATA		0xF1020040U
  #define XPMC_BNK0_EN_RX_SCHMITT_HYST	0xF106010CU
  #define XPMC_IOU_MIO_TRI0				0xF1060200U
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* _XOSPIPSV_H_ */
  /** @} */
  